Removed old xen patchset

[people/pmueller/ipfire-2.x.git] / src / patches / suse-2.6.27.25 / patches.arch / x86-disable-intel-boot-interrupt-generation.patch

diff --git a/src/patches/suse-2.6.27.25/patches.arch/x86-disable-intel-boot-interrupt-generation.patch b/src/patches/suse-2.6.27.25/patches.arch/x86-disable-intel-boot-interrupt-generation.patch
deleted file mode 100644 (file)
index 56bf1f4..0000000
--- a/src/patches/suse-2.6.27.25/patches.arch/x86-disable-intel-boot-interrupt-generation.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From: Stefan Assmann <sassmann@suse.de>
-Subject: pci: add quirk to disable boot interrupt generation on intel 6300ESB
-
-Add a quirk to disable legacy boot interrupt generation on intel devices
-that support disabling it.
-
-This patch benefited from discussions with Alexander Graf, Torsten Duwe,
-Ihno Krumreich, Daniel Gollub, Hannes Reinecke. The conclusions we drew
-and the patch itself are the authors' responsibility alone.
-
-Signed-off-by: Stefan Assmann <sassmann@suse.de>
-Signed-off-by: Olaf Dabrunz <od@suse.de>
-Signed-off-by: Ingo Molnar <mingo@elte.hu>
----
- drivers/pci/quirks.c |   30 ++++++++++++++++++++++++++++++
- 1 file changed, 30 insertions(+)
-
---- a/drivers/pci/quirks.c
-+++ b/drivers/pci/quirks.c
-@@ -1423,6 +1423,36 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN
- DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,  0x260a, quirk_intel_pcie_pm);
- DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,  0x260b, quirk_intel_pcie_pm);
- 
-+#ifdef CONFIG_X86_IO_APIC
-+/*
-+ * On some chipsets we can disable the generation of legacy INTx boot
-+ * interrupts.
-+ */
-+
-+/*
-+ * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
-+ * 300641-004US, section 5.7.3.
-+ */
-+#define INTEL_6300_IOAPIC_ABAR                0x40
-+#define INTEL_6300_DISABLE_BOOT_IRQ   (1<<14)
-+
-+static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
-+{
-+      u16 pci_config_word;
-+
-+      if (noioapicquirk)
-+              return;
-+
-+      pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
-+      pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
-+      pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
-+
-+      printk(KERN_INFO "disabled boot interrupt on device 0x%04x:0x%04x\n",
-+              dev->vendor, dev->device);
-+}
-+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10,    quirk_disable_intel_boot_interrupt);
-+#endif /* CONFIG_X86_IO_APIC */
-+
- /*
-  * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
-  * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.