--- /dev/null
+Commit-Id: f231e0a5a2d01da40515c24f1daa689fe8cfd8d7
+From: Divy Le Ray <divy@chelsio.com>
+Date: Wed, 8 Oct 2008 17:39:00 -0700
+Acked-by: Karsten Keil <kkeil@novell.com>
+Subject: [PATCH] cxgb3: More flexible support for PHY interrupts.
+Reference: bnc#446739
+
+Do not require PHY interrupts to be connected to GPIs in ascending order.
+Base interrupt availability both on PHYs supporting them and on GPIs being
+hooked up. Allows boards to specify interrupt GPIs though the PHYs don't
+use them.
+
+Remove spurious PHY interrupts due to clearing T3DBG interrupts before
+setting their polarity.
+
+Signed-off-by: Divy Le Ray <divy@chelsio.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+
+diff --git a/drivers/net/cxgb3/common.h b/drivers/net/cxgb3/common.h
+index e83a360..75b5ee6 100644
+--- a/drivers/net/cxgb3/common.h
++++ b/drivers/net/cxgb3/common.h
+@@ -194,7 +194,7 @@ struct adapter_info {
+ unsigned char nports; /* # of ports */
+ unsigned char phy_base_addr; /* MDIO PHY base address */
+ unsigned int gpio_out; /* GPIO output settings */
+- unsigned int gpio_intr; /* GPIO IRQ enable mask */
++ unsigned char gpio_intr[MAX_NPORTS]; /* GPIO PHY IRQ pins */
+ unsigned long caps; /* adapter capabilities */
+ const struct mdio_ops *mdio_ops; /* MDIO operations */
+ const char *desc; /* product description */
+@@ -517,7 +517,7 @@ enum {
+ MAC_RXFIFO_SIZE = 32768
+ };
+
+-/* IEEE 802.3ae specified MDIO devices */
++/* IEEE 802.3 specified MDIO devices */
+ enum {
+ MDIO_DEV_PMA_PMD = 1,
+ MDIO_DEV_WIS = 2,
+diff --git a/drivers/net/cxgb3/regs.h b/drivers/net/cxgb3/regs.h
+index 4bda27c..a035d5c 100644
+--- a/drivers/net/cxgb3/regs.h
++++ b/drivers/net/cxgb3/regs.h
+@@ -573,6 +573,10 @@
+ #define V_GPIO10(x) ((x) << S_GPIO10)
+ #define F_GPIO10 V_GPIO10(1U)
+
++#define S_GPIO9 9
++#define V_GPIO9(x) ((x) << S_GPIO9)
++#define F_GPIO9 V_GPIO9(1U)
++
+ #define S_GPIO7 7
+ #define V_GPIO7(x) ((x) << S_GPIO7)
+ #define F_GPIO7 V_GPIO7(1U)
+diff --git a/drivers/net/cxgb3/t3_hw.c b/drivers/net/cxgb3/t3_hw.c
+index f7ced32..bfce761 100644
+--- a/drivers/net/cxgb3/t3_hw.c
++++ b/drivers/net/cxgb3/t3_hw.c
+@@ -445,24 +445,22 @@ int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex)
+ static const struct adapter_info t3_adap_info[] = {
+ {2, 0,
+ F_GPIO2_OEN | F_GPIO4_OEN |
+- F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, F_GPIO3 | F_GPIO5,
+- 0,
++ F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0,
+ &mi1_mdio_ops, "Chelsio PE9000"},
+ {2, 0,
+ F_GPIO2_OEN | F_GPIO4_OEN |
+- F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, F_GPIO3 | F_GPIO5,
+- 0,
++ F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0,
+ &mi1_mdio_ops, "Chelsio T302"},
+ {1, 0,
+ F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN |
+ F_GPIO11_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
+- 0, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
++ { 0 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
+ &mi1_mdio_ext_ops, "Chelsio T310"},
+ {2, 0,
+ F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN |
+ F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL |
+- F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, 0,
+- SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
++ F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
++ { S_GPIO9, S_GPIO3 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
+ &mi1_mdio_ext_ops, "Chelsio T320"},
+ };
+
+@@ -1684,19 +1682,15 @@ static int mac_intr_handler(struct adapter *adap, unsigned int idx)
+ */
+ int t3_phy_intr_handler(struct adapter *adapter)
+ {
+- u32 mask, gpi = adapter_info(adapter)->gpio_intr;
+ u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE);
+
+ for_each_port(adapter, i) {
+ struct port_info *p = adap2pinfo(adapter, i);
+
+- mask = gpi - (gpi & (gpi - 1));
+- gpi -= mask;
+-
+ if (!(p->phy.caps & SUPPORTED_IRQ))
+ continue;
+
+- if (cause & mask) {
++ if (cause & (1 << adapter_info(adapter)->gpio_intr[i])) {
+ int phy_cause = p->phy.ops->intr_handler(&p->phy);
+
+ if (phy_cause & cphy_cause_link_change)
+@@ -1765,6 +1759,17 @@ int t3_slow_intr_handler(struct adapter *adapter)
+ return 1;
+ }
+
++static unsigned int calc_gpio_intr(struct adapter *adap)
++{
++ unsigned int i, gpi_intr = 0;
++
++ for_each_port(adap, i)
++ if ((adap2pinfo(adap, i)->phy.caps & SUPPORTED_IRQ) &&
++ adapter_info(adap)->gpio_intr[i])
++ gpi_intr |= 1 << adapter_info(adap)->gpio_intr[i];
++ return gpi_intr;
++}
++
+ /**
+ * t3_intr_enable - enable interrupts
+ * @adapter: the adapter whose interrupts should be enabled
+@@ -1807,10 +1812,8 @@ void t3_intr_enable(struct adapter *adapter)
+ t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK);
+ }
+
+- t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW,
+- adapter_info(adapter)->gpio_intr);
+- t3_write_reg(adapter, A_T3DBG_INT_ENABLE,
+- adapter_info(adapter)->gpio_intr);
++ t3_write_reg(adapter, A_T3DBG_INT_ENABLE, calc_gpio_intr(adapter));
++
+ if (is_pcie(adapter))
+ t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK);
+ else
+@@ -3331,6 +3334,8 @@ int t3_init_hw(struct adapter *adapter, u32 fw_params)
+ init_hw_for_avail_ports(adapter, adapter->params.nports);
+ t3_sge_init(adapter, &adapter->params.sge);
+
++ t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW, calc_gpio_intr(adapter));
++
+ t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params);
+ t3_write_reg(adapter, A_CIM_BOOT_CFG,
+ V_BOOTADDR(FW_FLASH_BOOT_ADDR >> 2));
projects / people / teissler / ipfire-2.x.git / blobdiff