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[thirdparty/binutils-gdb.git] / bfd / elf32-arm.c
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252b5132 1/* 32-bit ELF support for ARM
250d07de 2 Copyright (C) 1998-2021 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
00a97672 25#include "libiberty.h"
7f266840
DJ		 26#include "libbfd.h"
27#include "elf-bfd.h"
b38cadfb 28#include "elf-nacl.h"
00a97672 29#include "elf-vxworks.h"
ee065d83 30#include "elf/arm.h"
f37164d7
AM		 31#include "elf32-arm.h"
32#include "cpu-arm.h"
7f266840 33
00a97672
RS		 34/* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36#define RELOC_SECTION(HTAB, NAME) \
37 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
38
39/* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41#define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
45
46/* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48#define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
52
53/* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55#define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
59
f3185997 60#define elf_info_to_howto NULL
07d6d2b8 61#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 62
63#define ARM_ELF_ABI_VERSION 0
64#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
65
79f08007
YZ		 66/* The Adjusted Place, as defined by AAELF. */
67#define Pa(X) ((X) & 0xfffffffc)
68
3e6b1042
DJ		 69static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
70 struct bfd_link_info *link_info,
71 asection *sec,
72 bfd_byte *contents);
73
7f266840
DJ		 74/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
77
c19d1205 78static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 79{
8029a119 80 /* No relocation. */
7f266840
DJ		 81 HOWTO (R_ARM_NONE, /* type */
82 0, /* rightshift */
6346d5ca 83 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 84 0, /* bitsize */
85 FALSE, /* pc_relative */
86 0, /* bitpos */
87 complain_overflow_dont,/* complain_on_overflow */
88 bfd_elf_generic_reloc, /* special_function */
89 "R_ARM_NONE", /* name */
90 FALSE, /* partial_inplace */
91 0, /* src_mask */
92 0, /* dst_mask */
93 FALSE), /* pcrel_offset */
94
95 HOWTO (R_ARM_PC24, /* type */
96 2, /* rightshift */
97 2, /* size (0 = byte, 1 = short, 2 = long) */
98 24, /* bitsize */
99 TRUE, /* pc_relative */
100 0, /* bitpos */
101 complain_overflow_signed,/* complain_on_overflow */
102 bfd_elf_generic_reloc, /* special_function */
103 "R_ARM_PC24", /* name */
104 FALSE, /* partial_inplace */
105 0x00ffffff, /* src_mask */
106 0x00ffffff, /* dst_mask */
107 TRUE), /* pcrel_offset */
108
109 /* 32 bit absolute */
110 HOWTO (R_ARM_ABS32, /* type */
111 0, /* rightshift */
112 2, /* size (0 = byte, 1 = short, 2 = long) */
113 32, /* bitsize */
114 FALSE, /* pc_relative */
115 0, /* bitpos */
116 complain_overflow_bitfield,/* complain_on_overflow */
117 bfd_elf_generic_reloc, /* special_function */
118 "R_ARM_ABS32", /* name */
119 FALSE, /* partial_inplace */
120 0xffffffff, /* src_mask */
121 0xffffffff, /* dst_mask */
122 FALSE), /* pcrel_offset */
123
124 /* standard 32bit pc-relative reloc */
125 HOWTO (R_ARM_REL32, /* type */
126 0, /* rightshift */
127 2, /* size (0 = byte, 1 = short, 2 = long) */
128 32, /* bitsize */
129 TRUE, /* pc_relative */
130 0, /* bitpos */
131 complain_overflow_bitfield,/* complain_on_overflow */
132 bfd_elf_generic_reloc, /* special_function */
133 "R_ARM_REL32", /* name */
134 FALSE, /* partial_inplace */
135 0xffffffff, /* src_mask */
136 0xffffffff, /* dst_mask */
137 TRUE), /* pcrel_offset */
138
c19d1205 139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 140 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 141 0, /* rightshift */
142 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 143 32, /* bitsize */
144 TRUE, /* pc_relative */
7f266840 145 0, /* bitpos */
4962c51a 146 complain_overflow_dont,/* complain_on_overflow */
7f266840 147 bfd_elf_generic_reloc, /* special_function */
4962c51a 148 "R_ARM_LDR_PC_G0", /* name */
7f266840 149 FALSE, /* partial_inplace */
4962c51a
MS		 150 0xffffffff, /* src_mask */
151 0xffffffff, /* dst_mask */
152 TRUE), /* pcrel_offset */
7f266840
DJ		 153
154 /* 16 bit absolute */
155 HOWTO (R_ARM_ABS16, /* type */
156 0, /* rightshift */
157 1, /* size (0 = byte, 1 = short, 2 = long) */
158 16, /* bitsize */
159 FALSE, /* pc_relative */
160 0, /* bitpos */
161 complain_overflow_bitfield,/* complain_on_overflow */
162 bfd_elf_generic_reloc, /* special_function */
163 "R_ARM_ABS16", /* name */
164 FALSE, /* partial_inplace */
165 0x0000ffff, /* src_mask */
166 0x0000ffff, /* dst_mask */
167 FALSE), /* pcrel_offset */
168
169 /* 12 bit absolute */
170 HOWTO (R_ARM_ABS12, /* type */
171 0, /* rightshift */
172 2, /* size (0 = byte, 1 = short, 2 = long) */
173 12, /* bitsize */
174 FALSE, /* pc_relative */
175 0, /* bitpos */
176 complain_overflow_bitfield,/* complain_on_overflow */
177 bfd_elf_generic_reloc, /* special_function */
178 "R_ARM_ABS12", /* name */
179 FALSE, /* partial_inplace */
00a97672
RS		 180 0x00000fff, /* src_mask */
181 0x00000fff, /* dst_mask */
7f266840
DJ		 182 FALSE), /* pcrel_offset */
183
184 HOWTO (R_ARM_THM_ABS5, /* type */
185 6, /* rightshift */
186 1, /* size (0 = byte, 1 = short, 2 = long) */
187 5, /* bitsize */
188 FALSE, /* pc_relative */
189 0, /* bitpos */
190 complain_overflow_bitfield,/* complain_on_overflow */
191 bfd_elf_generic_reloc, /* special_function */
192 "R_ARM_THM_ABS5", /* name */
193 FALSE, /* partial_inplace */
194 0x000007e0, /* src_mask */
195 0x000007e0, /* dst_mask */
196 FALSE), /* pcrel_offset */
197
198 /* 8 bit absolute */
199 HOWTO (R_ARM_ABS8, /* type */
200 0, /* rightshift */
201 0, /* size (0 = byte, 1 = short, 2 = long) */
202 8, /* bitsize */
203 FALSE, /* pc_relative */
204 0, /* bitpos */
205 complain_overflow_bitfield,/* complain_on_overflow */
206 bfd_elf_generic_reloc, /* special_function */
207 "R_ARM_ABS8", /* name */
208 FALSE, /* partial_inplace */
209 0x000000ff, /* src_mask */
210 0x000000ff, /* dst_mask */
211 FALSE), /* pcrel_offset */
212
213 HOWTO (R_ARM_SBREL32, /* type */
214 0, /* rightshift */
215 2, /* size (0 = byte, 1 = short, 2 = long) */
216 32, /* bitsize */
217 FALSE, /* pc_relative */
218 0, /* bitpos */
219 complain_overflow_dont,/* complain_on_overflow */
220 bfd_elf_generic_reloc, /* special_function */
221 "R_ARM_SBREL32", /* name */
222 FALSE, /* partial_inplace */
223 0xffffffff, /* src_mask */
224 0xffffffff, /* dst_mask */
225 FALSE), /* pcrel_offset */
226
c19d1205 227 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 228 1, /* rightshift */
229 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 230 24, /* bitsize */
7f266840
DJ		 231 TRUE, /* pc_relative */
232 0, /* bitpos */
233 complain_overflow_signed,/* complain_on_overflow */
234 bfd_elf_generic_reloc, /* special_function */
c19d1205 235 "R_ARM_THM_CALL", /* name */
7f266840 236 FALSE, /* partial_inplace */
7f6ab9f8
AM		 237 0x07ff2fff, /* src_mask */
238 0x07ff2fff, /* dst_mask */
7f266840
DJ		 239 TRUE), /* pcrel_offset */
240
07d6d2b8 241 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 242 1, /* rightshift */
243 1, /* size (0 = byte, 1 = short, 2 = long) */
244 8, /* bitsize */
245 TRUE, /* pc_relative */
246 0, /* bitpos */
247 complain_overflow_signed,/* complain_on_overflow */
248 bfd_elf_generic_reloc, /* special_function */
249 "R_ARM_THM_PC8", /* name */
250 FALSE, /* partial_inplace */
251 0x000000ff, /* src_mask */
252 0x000000ff, /* dst_mask */
253 TRUE), /* pcrel_offset */
254
c19d1205 255 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 256 1, /* rightshift */
257 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 258 32, /* bitsize */
259 FALSE, /* pc_relative */
7f266840
DJ		 260 0, /* bitpos */
261 complain_overflow_signed,/* complain_on_overflow */
262 bfd_elf_generic_reloc, /* special_function */
c19d1205 263 "R_ARM_BREL_ADJ", /* name */
7f266840 264 FALSE, /* partial_inplace */
c19d1205
ZW		 265 0xffffffff, /* src_mask */
266 0xffffffff, /* dst_mask */
267 FALSE), /* pcrel_offset */
7f266840 268
0855e32b 269 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 270 0, /* rightshift */
0855e32b
NS		 271 2, /* size (0 = byte, 1 = short, 2 = long) */
272 32, /* bitsize */
7f266840
DJ		 273 FALSE, /* pc_relative */
274 0, /* bitpos */
0855e32b 275 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 276 bfd_elf_generic_reloc, /* special_function */
0855e32b 277 "R_ARM_TLS_DESC", /* name */
7f266840 278 FALSE, /* partial_inplace */
0855e32b
NS		 279 0xffffffff, /* src_mask */
280 0xffffffff, /* dst_mask */
7f266840
DJ		 281 FALSE), /* pcrel_offset */
282
283 HOWTO (R_ARM_THM_SWI8, /* type */
284 0, /* rightshift */
285 0, /* size (0 = byte, 1 = short, 2 = long) */
286 0, /* bitsize */
287 FALSE, /* pc_relative */
288 0, /* bitpos */
289 complain_overflow_signed,/* complain_on_overflow */
290 bfd_elf_generic_reloc, /* special_function */
291 "R_ARM_SWI8", /* name */
292 FALSE, /* partial_inplace */
293 0x00000000, /* src_mask */
294 0x00000000, /* dst_mask */
295 FALSE), /* pcrel_offset */
296
297 /* BLX instruction for the ARM. */
298 HOWTO (R_ARM_XPC25, /* type */
299 2, /* rightshift */
300 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 301 24, /* bitsize */
7f266840
DJ		 302 TRUE, /* pc_relative */
303 0, /* bitpos */
304 complain_overflow_signed,/* complain_on_overflow */
305 bfd_elf_generic_reloc, /* special_function */
306 "R_ARM_XPC25", /* name */
307 FALSE, /* partial_inplace */
308 0x00ffffff, /* src_mask */
309 0x00ffffff, /* dst_mask */
310 TRUE), /* pcrel_offset */
311
312 /* BLX instruction for the Thumb. */
313 HOWTO (R_ARM_THM_XPC22, /* type */
314 2, /* rightshift */
315 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 316 24, /* bitsize */
7f266840
DJ		 317 TRUE, /* pc_relative */
318 0, /* bitpos */
319 complain_overflow_signed,/* complain_on_overflow */
320 bfd_elf_generic_reloc, /* special_function */
321 "R_ARM_THM_XPC22", /* name */
322 FALSE, /* partial_inplace */
7f6ab9f8
AM		 323 0x07ff2fff, /* src_mask */
324 0x07ff2fff, /* dst_mask */
7f266840
DJ		 325 TRUE), /* pcrel_offset */
326
ba93b8ac 327 /* Dynamic TLS relocations. */
7f266840 328
ba93b8ac 329 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 330 0, /* rightshift */
331 2, /* size (0 = byte, 1 = short, 2 = long) */
332 32, /* bitsize */
333 FALSE, /* pc_relative */
334 0, /* bitpos */
99059e56
RM		 335 complain_overflow_bitfield,/* complain_on_overflow */
336 bfd_elf_generic_reloc, /* special_function */
337 "R_ARM_TLS_DTPMOD32", /* name */
338 TRUE, /* partial_inplace */
339 0xffffffff, /* src_mask */
340 0xffffffff, /* dst_mask */
07d6d2b8 341 FALSE), /* pcrel_offset */
7f266840 342
ba93b8ac 343 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 344 0, /* rightshift */
345 2, /* size (0 = byte, 1 = short, 2 = long) */
346 32, /* bitsize */
347 FALSE, /* pc_relative */
348 0, /* bitpos */
99059e56
RM		 349 complain_overflow_bitfield,/* complain_on_overflow */
350 bfd_elf_generic_reloc, /* special_function */
351 "R_ARM_TLS_DTPOFF32", /* name */
352 TRUE, /* partial_inplace */
353 0xffffffff, /* src_mask */
354 0xffffffff, /* dst_mask */
07d6d2b8 355 FALSE), /* pcrel_offset */
7f266840 356
ba93b8ac 357 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 358 0, /* rightshift */
359 2, /* size (0 = byte, 1 = short, 2 = long) */
360 32, /* bitsize */
361 FALSE, /* pc_relative */
362 0, /* bitpos */
99059e56
RM		 363 complain_overflow_bitfield,/* complain_on_overflow */
364 bfd_elf_generic_reloc, /* special_function */
365 "R_ARM_TLS_TPOFF32", /* name */
366 TRUE, /* partial_inplace */
367 0xffffffff, /* src_mask */
368 0xffffffff, /* dst_mask */
07d6d2b8 369 FALSE), /* pcrel_offset */
7f266840
DJ		 370
371 /* Relocs used in ARM Linux */
372
373 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 374 0, /* rightshift */
375 2, /* size (0 = byte, 1 = short, 2 = long) */
376 32, /* bitsize */
377 FALSE, /* pc_relative */
378 0, /* bitpos */
99059e56
RM		 379 complain_overflow_bitfield,/* complain_on_overflow */
380 bfd_elf_generic_reloc, /* special_function */
381 "R_ARM_COPY", /* name */
382 TRUE, /* partial_inplace */
383 0xffffffff, /* src_mask */
384 0xffffffff, /* dst_mask */
07d6d2b8 385 FALSE), /* pcrel_offset */
7f266840
DJ		 386
387 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 388 0, /* rightshift */
389 2, /* size (0 = byte, 1 = short, 2 = long) */
390 32, /* bitsize */
391 FALSE, /* pc_relative */
392 0, /* bitpos */
99059e56
RM		 393 complain_overflow_bitfield,/* complain_on_overflow */
394 bfd_elf_generic_reloc, /* special_function */
395 "R_ARM_GLOB_DAT", /* name */
396 TRUE, /* partial_inplace */
397 0xffffffff, /* src_mask */
398 0xffffffff, /* dst_mask */
07d6d2b8 399 FALSE), /* pcrel_offset */
7f266840
DJ		 400
401 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 402 0, /* rightshift */
403 2, /* size (0 = byte, 1 = short, 2 = long) */
404 32, /* bitsize */
405 FALSE, /* pc_relative */
406 0, /* bitpos */
99059e56
RM		 407 complain_overflow_bitfield,/* complain_on_overflow */
408 bfd_elf_generic_reloc, /* special_function */
409 "R_ARM_JUMP_SLOT", /* name */
410 TRUE, /* partial_inplace */
411 0xffffffff, /* src_mask */
412 0xffffffff, /* dst_mask */
07d6d2b8 413 FALSE), /* pcrel_offset */
7f266840
DJ		 414
415 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 416 0, /* rightshift */
417 2, /* size (0 = byte, 1 = short, 2 = long) */
418 32, /* bitsize */
419 FALSE, /* pc_relative */
420 0, /* bitpos */
99059e56
RM		 421 complain_overflow_bitfield,/* complain_on_overflow */
422 bfd_elf_generic_reloc, /* special_function */
423 "R_ARM_RELATIVE", /* name */
424 TRUE, /* partial_inplace */
425 0xffffffff, /* src_mask */
426 0xffffffff, /* dst_mask */
07d6d2b8 427 FALSE), /* pcrel_offset */
7f266840 428
c19d1205 429 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 430 0, /* rightshift */
431 2, /* size (0 = byte, 1 = short, 2 = long) */
432 32, /* bitsize */
433 FALSE, /* pc_relative */
434 0, /* bitpos */
99059e56
RM		 435 complain_overflow_bitfield,/* complain_on_overflow */
436 bfd_elf_generic_reloc, /* special_function */
437 "R_ARM_GOTOFF32", /* name */
438 TRUE, /* partial_inplace */
439 0xffffffff, /* src_mask */
440 0xffffffff, /* dst_mask */
07d6d2b8 441 FALSE), /* pcrel_offset */
7f266840
DJ		 442
443 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 444 0, /* rightshift */
445 2, /* size (0 = byte, 1 = short, 2 = long) */
446 32, /* bitsize */
99059e56 447 TRUE, /* pc_relative */
07d6d2b8 448 0, /* bitpos */
99059e56
RM		 449 complain_overflow_bitfield,/* complain_on_overflow */
450 bfd_elf_generic_reloc, /* special_function */
451 "R_ARM_GOTPC", /* name */
452 TRUE, /* partial_inplace */
453 0xffffffff, /* src_mask */
454 0xffffffff, /* dst_mask */
455 TRUE), /* pcrel_offset */
7f266840
DJ		 456
457 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 458 0, /* rightshift */
459 2, /* size (0 = byte, 1 = short, 2 = long) */
460 32, /* bitsize */
99059e56 461 FALSE, /* pc_relative */
07d6d2b8 462 0, /* bitpos */
99059e56
RM		 463 complain_overflow_bitfield,/* complain_on_overflow */
464 bfd_elf_generic_reloc, /* special_function */
465 "R_ARM_GOT32", /* name */
466 TRUE, /* partial_inplace */
467 0xffffffff, /* src_mask */
468 0xffffffff, /* dst_mask */
469 FALSE), /* pcrel_offset */
7f266840
DJ		 470
471 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 472 2, /* rightshift */
473 2, /* size (0 = byte, 1 = short, 2 = long) */
474 24, /* bitsize */
99059e56 475 TRUE, /* pc_relative */
07d6d2b8 476 0, /* bitpos */
99059e56
RM		 477 complain_overflow_bitfield,/* complain_on_overflow */
478 bfd_elf_generic_reloc, /* special_function */
479 "R_ARM_PLT32", /* name */
480 FALSE, /* partial_inplace */
481 0x00ffffff, /* src_mask */
482 0x00ffffff, /* dst_mask */
483 TRUE), /* pcrel_offset */
7f266840
DJ		 484
485 HOWTO (R_ARM_CALL, /* type */
486 2, /* rightshift */
487 2, /* size (0 = byte, 1 = short, 2 = long) */
488 24, /* bitsize */
489 TRUE, /* pc_relative */
490 0, /* bitpos */
491 complain_overflow_signed,/* complain_on_overflow */
492 bfd_elf_generic_reloc, /* special_function */
493 "R_ARM_CALL", /* name */
494 FALSE, /* partial_inplace */
495 0x00ffffff, /* src_mask */
496 0x00ffffff, /* dst_mask */
497 TRUE), /* pcrel_offset */
498
499 HOWTO (R_ARM_JUMP24, /* type */
500 2, /* rightshift */
501 2, /* size (0 = byte, 1 = short, 2 = long) */
502 24, /* bitsize */
503 TRUE, /* pc_relative */
504 0, /* bitpos */
505 complain_overflow_signed,/* complain_on_overflow */
506 bfd_elf_generic_reloc, /* special_function */
507 "R_ARM_JUMP24", /* name */
508 FALSE, /* partial_inplace */
509 0x00ffffff, /* src_mask */
510 0x00ffffff, /* dst_mask */
511 TRUE), /* pcrel_offset */
512
c19d1205
ZW		 513 HOWTO (R_ARM_THM_JUMP24, /* type */
514 1, /* rightshift */
515 2, /* size (0 = byte, 1 = short, 2 = long) */
516 24, /* bitsize */
517 TRUE, /* pc_relative */
7f266840 518 0, /* bitpos */
c19d1205 519 complain_overflow_signed,/* complain_on_overflow */
7f266840 520 bfd_elf_generic_reloc, /* special_function */
c19d1205 521 "R_ARM_THM_JUMP24", /* name */
7f266840 522 FALSE, /* partial_inplace */
c19d1205
ZW		 523 0x07ff2fff, /* src_mask */
524 0x07ff2fff, /* dst_mask */
525 TRUE), /* pcrel_offset */
7f266840 526
c19d1205 527 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 528 0, /* rightshift */
c19d1205
ZW		 529 2, /* size (0 = byte, 1 = short, 2 = long) */
530 32, /* bitsize */
7f266840
DJ		 531 FALSE, /* pc_relative */
532 0, /* bitpos */
533 complain_overflow_dont,/* complain_on_overflow */
534 bfd_elf_generic_reloc, /* special_function */
c19d1205 535 "R_ARM_BASE_ABS", /* name */
7f266840 536 FALSE, /* partial_inplace */
c19d1205
ZW		 537 0xffffffff, /* src_mask */
538 0xffffffff, /* dst_mask */
7f266840
DJ		 539 FALSE), /* pcrel_offset */
540
541 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
542 0, /* rightshift */
543 2, /* size (0 = byte, 1 = short, 2 = long) */
544 12, /* bitsize */
545 TRUE, /* pc_relative */
546 0, /* bitpos */
547 complain_overflow_dont,/* complain_on_overflow */
548 bfd_elf_generic_reloc, /* special_function */
549 "R_ARM_ALU_PCREL_7_0", /* name */
550 FALSE, /* partial_inplace */
551 0x00000fff, /* src_mask */
552 0x00000fff, /* dst_mask */
553 TRUE), /* pcrel_offset */
554
555 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
556 0, /* rightshift */
557 2, /* size (0 = byte, 1 = short, 2 = long) */
558 12, /* bitsize */
559 TRUE, /* pc_relative */
560 8, /* bitpos */
561 complain_overflow_dont,/* complain_on_overflow */
562 bfd_elf_generic_reloc, /* special_function */
563 "R_ARM_ALU_PCREL_15_8",/* name */
564 FALSE, /* partial_inplace */
565 0x00000fff, /* src_mask */
566 0x00000fff, /* dst_mask */
567 TRUE), /* pcrel_offset */
568
569 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
570 0, /* rightshift */
571 2, /* size (0 = byte, 1 = short, 2 = long) */
572 12, /* bitsize */
573 TRUE, /* pc_relative */
574 16, /* bitpos */
575 complain_overflow_dont,/* complain_on_overflow */
576 bfd_elf_generic_reloc, /* special_function */
577 "R_ARM_ALU_PCREL_23_15",/* name */
578 FALSE, /* partial_inplace */
579 0x00000fff, /* src_mask */
580 0x00000fff, /* dst_mask */
581 TRUE), /* pcrel_offset */
582
583 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
584 0, /* rightshift */
585 2, /* size (0 = byte, 1 = short, 2 = long) */
586 12, /* bitsize */
587 FALSE, /* pc_relative */
588 0, /* bitpos */
589 complain_overflow_dont,/* complain_on_overflow */
590 bfd_elf_generic_reloc, /* special_function */
591 "R_ARM_LDR_SBREL_11_0",/* name */
592 FALSE, /* partial_inplace */
593 0x00000fff, /* src_mask */
594 0x00000fff, /* dst_mask */
595 FALSE), /* pcrel_offset */
596
597 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
598 0, /* rightshift */
599 2, /* size (0 = byte, 1 = short, 2 = long) */
600 8, /* bitsize */
601 FALSE, /* pc_relative */
602 12, /* bitpos */
603 complain_overflow_dont,/* complain_on_overflow */
604 bfd_elf_generic_reloc, /* special_function */
605 "R_ARM_ALU_SBREL_19_12",/* name */
606 FALSE, /* partial_inplace */
607 0x000ff000, /* src_mask */
608 0x000ff000, /* dst_mask */
609 FALSE), /* pcrel_offset */
610
611 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
612 0, /* rightshift */
613 2, /* size (0 = byte, 1 = short, 2 = long) */
614 8, /* bitsize */
615 FALSE, /* pc_relative */
616 20, /* bitpos */
617 complain_overflow_dont,/* complain_on_overflow */
618 bfd_elf_generic_reloc, /* special_function */
619 "R_ARM_ALU_SBREL_27_20",/* name */
620 FALSE, /* partial_inplace */
621 0x0ff00000, /* src_mask */
622 0x0ff00000, /* dst_mask */
623 FALSE), /* pcrel_offset */
624
625 HOWTO (R_ARM_TARGET1, /* type */
626 0, /* rightshift */
627 2, /* size (0 = byte, 1 = short, 2 = long) */
628 32, /* bitsize */
629 FALSE, /* pc_relative */
630 0, /* bitpos */
631 complain_overflow_dont,/* complain_on_overflow */
632 bfd_elf_generic_reloc, /* special_function */
633 "R_ARM_TARGET1", /* name */
634 FALSE, /* partial_inplace */
635 0xffffffff, /* src_mask */
636 0xffffffff, /* dst_mask */
637 FALSE), /* pcrel_offset */
638
639 HOWTO (R_ARM_ROSEGREL32, /* type */
640 0, /* rightshift */
641 2, /* size (0 = byte, 1 = short, 2 = long) */
642 32, /* bitsize */
643 FALSE, /* pc_relative */
644 0, /* bitpos */
645 complain_overflow_dont,/* complain_on_overflow */
646 bfd_elf_generic_reloc, /* special_function */
647 "R_ARM_ROSEGREL32", /* name */
648 FALSE, /* partial_inplace */
649 0xffffffff, /* src_mask */
650 0xffffffff, /* dst_mask */
651 FALSE), /* pcrel_offset */
652
653 HOWTO (R_ARM_V4BX, /* type */
654 0, /* rightshift */
655 2, /* size (0 = byte, 1 = short, 2 = long) */
656 32, /* bitsize */
657 FALSE, /* pc_relative */
658 0, /* bitpos */
659 complain_overflow_dont,/* complain_on_overflow */
660 bfd_elf_generic_reloc, /* special_function */
661 "R_ARM_V4BX", /* name */
662 FALSE, /* partial_inplace */
663 0xffffffff, /* src_mask */
664 0xffffffff, /* dst_mask */
665 FALSE), /* pcrel_offset */
666
667 HOWTO (R_ARM_TARGET2, /* type */
668 0, /* rightshift */
669 2, /* size (0 = byte, 1 = short, 2 = long) */
670 32, /* bitsize */
671 FALSE, /* pc_relative */
672 0, /* bitpos */
673 complain_overflow_signed,/* complain_on_overflow */
674 bfd_elf_generic_reloc, /* special_function */
675 "R_ARM_TARGET2", /* name */
676 FALSE, /* partial_inplace */
677 0xffffffff, /* src_mask */
678 0xffffffff, /* dst_mask */
679 TRUE), /* pcrel_offset */
680
681 HOWTO (R_ARM_PREL31, /* type */
682 0, /* rightshift */
683 2, /* size (0 = byte, 1 = short, 2 = long) */
684 31, /* bitsize */
685 TRUE, /* pc_relative */
686 0, /* bitpos */
687 complain_overflow_signed,/* complain_on_overflow */
688 bfd_elf_generic_reloc, /* special_function */
689 "R_ARM_PREL31", /* name */
690 FALSE, /* partial_inplace */
691 0x7fffffff, /* src_mask */
692 0x7fffffff, /* dst_mask */
693 TRUE), /* pcrel_offset */
c19d1205
ZW		 694
695 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
696 0, /* rightshift */
697 2, /* size (0 = byte, 1 = short, 2 = long) */
698 16, /* bitsize */
699 FALSE, /* pc_relative */
700 0, /* bitpos */
701 complain_overflow_dont,/* complain_on_overflow */
702 bfd_elf_generic_reloc, /* special_function */
703 "R_ARM_MOVW_ABS_NC", /* name */
704 FALSE, /* partial_inplace */
39623e12
PB		 705 0x000f0fff, /* src_mask */
706 0x000f0fff, /* dst_mask */
c19d1205
ZW		 707 FALSE), /* pcrel_offset */
708
709 HOWTO (R_ARM_MOVT_ABS, /* type */
710 0, /* rightshift */
711 2, /* size (0 = byte, 1 = short, 2 = long) */
712 16, /* bitsize */
713 FALSE, /* pc_relative */
714 0, /* bitpos */
715 complain_overflow_bitfield,/* complain_on_overflow */
716 bfd_elf_generic_reloc, /* special_function */
717 "R_ARM_MOVT_ABS", /* name */
718 FALSE, /* partial_inplace */
39623e12
PB		 719 0x000f0fff, /* src_mask */
720 0x000f0fff, /* dst_mask */
c19d1205
ZW		 721 FALSE), /* pcrel_offset */
722
723 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
724 0, /* rightshift */
725 2, /* size (0 = byte, 1 = short, 2 = long) */
726 16, /* bitsize */
727 TRUE, /* pc_relative */
728 0, /* bitpos */
729 complain_overflow_dont,/* complain_on_overflow */
730 bfd_elf_generic_reloc, /* special_function */
731 "R_ARM_MOVW_PREL_NC", /* name */
732 FALSE, /* partial_inplace */
39623e12
PB		 733 0x000f0fff, /* src_mask */
734 0x000f0fff, /* dst_mask */
c19d1205
ZW		 735 TRUE), /* pcrel_offset */
736
737 HOWTO (R_ARM_MOVT_PREL, /* type */
738 0, /* rightshift */
739 2, /* size (0 = byte, 1 = short, 2 = long) */
740 16, /* bitsize */
741 TRUE, /* pc_relative */
742 0, /* bitpos */
743 complain_overflow_bitfield,/* complain_on_overflow */
744 bfd_elf_generic_reloc, /* special_function */
745 "R_ARM_MOVT_PREL", /* name */
746 FALSE, /* partial_inplace */
39623e12
PB		 747 0x000f0fff, /* src_mask */
748 0x000f0fff, /* dst_mask */
c19d1205
ZW		 749 TRUE), /* pcrel_offset */
750
751 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
752 0, /* rightshift */
753 2, /* size (0 = byte, 1 = short, 2 = long) */
754 16, /* bitsize */
755 FALSE, /* pc_relative */
756 0, /* bitpos */
757 complain_overflow_dont,/* complain_on_overflow */
758 bfd_elf_generic_reloc, /* special_function */
759 "R_ARM_THM_MOVW_ABS_NC",/* name */
760 FALSE, /* partial_inplace */
761 0x040f70ff, /* src_mask */
762 0x040f70ff, /* dst_mask */
763 FALSE), /* pcrel_offset */
764
765 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
766 0, /* rightshift */
767 2, /* size (0 = byte, 1 = short, 2 = long) */
768 16, /* bitsize */
769 FALSE, /* pc_relative */
770 0, /* bitpos */
771 complain_overflow_bitfield,/* complain_on_overflow */
772 bfd_elf_generic_reloc, /* special_function */
773 "R_ARM_THM_MOVT_ABS", /* name */
774 FALSE, /* partial_inplace */
775 0x040f70ff, /* src_mask */
776 0x040f70ff, /* dst_mask */
777 FALSE), /* pcrel_offset */
778
779 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
780 0, /* rightshift */
781 2, /* size (0 = byte, 1 = short, 2 = long) */
782 16, /* bitsize */
783 TRUE, /* pc_relative */
784 0, /* bitpos */
785 complain_overflow_dont,/* complain_on_overflow */
786 bfd_elf_generic_reloc, /* special_function */
787 "R_ARM_THM_MOVW_PREL_NC",/* name */
788 FALSE, /* partial_inplace */
789 0x040f70ff, /* src_mask */
790 0x040f70ff, /* dst_mask */
791 TRUE), /* pcrel_offset */
792
793 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
794 0, /* rightshift */
795 2, /* size (0 = byte, 1 = short, 2 = long) */
796 16, /* bitsize */
797 TRUE, /* pc_relative */
798 0, /* bitpos */
799 complain_overflow_bitfield,/* complain_on_overflow */
800 bfd_elf_generic_reloc, /* special_function */
801 "R_ARM_THM_MOVT_PREL", /* name */
802 FALSE, /* partial_inplace */
803 0x040f70ff, /* src_mask */
804 0x040f70ff, /* dst_mask */
805 TRUE), /* pcrel_offset */
806
807 HOWTO (R_ARM_THM_JUMP19, /* type */
808 1, /* rightshift */
809 2, /* size (0 = byte, 1 = short, 2 = long) */
810 19, /* bitsize */
811 TRUE, /* pc_relative */
812 0, /* bitpos */
813 complain_overflow_signed,/* complain_on_overflow */
814 bfd_elf_generic_reloc, /* special_function */
815 "R_ARM_THM_JUMP19", /* name */
816 FALSE, /* partial_inplace */
817 0x043f2fff, /* src_mask */
818 0x043f2fff, /* dst_mask */
819 TRUE), /* pcrel_offset */
820
821 HOWTO (R_ARM_THM_JUMP6, /* type */
822 1, /* rightshift */
823 1, /* size (0 = byte, 1 = short, 2 = long) */
824 6, /* bitsize */
825 TRUE, /* pc_relative */
826 0, /* bitpos */
827 complain_overflow_unsigned,/* complain_on_overflow */
828 bfd_elf_generic_reloc, /* special_function */
829 "R_ARM_THM_JUMP6", /* name */
830 FALSE, /* partial_inplace */
831 0x02f8, /* src_mask */
832 0x02f8, /* dst_mask */
833 TRUE), /* pcrel_offset */
834
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
838 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
839 0, /* rightshift */
840 2, /* size (0 = byte, 1 = short, 2 = long) */
841 13, /* bitsize */
842 TRUE, /* pc_relative */
843 0, /* bitpos */
2cab6cc3 844 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 845 bfd_elf_generic_reloc, /* special_function */
846 "R_ARM_THM_ALU_PREL_11_0",/* name */
847 FALSE, /* partial_inplace */
2cab6cc3
MS		 848 0xffffffff, /* src_mask */
849 0xffffffff, /* dst_mask */
c19d1205
ZW		 850 TRUE), /* pcrel_offset */
851
852 HOWTO (R_ARM_THM_PC12, /* type */
853 0, /* rightshift */
854 2, /* size (0 = byte, 1 = short, 2 = long) */
855 13, /* bitsize */
856 TRUE, /* pc_relative */
857 0, /* bitpos */
2cab6cc3 858 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 859 bfd_elf_generic_reloc, /* special_function */
860 "R_ARM_THM_PC12", /* name */
861 FALSE, /* partial_inplace */
2cab6cc3
MS		 862 0xffffffff, /* src_mask */
863 0xffffffff, /* dst_mask */
c19d1205
ZW		 864 TRUE), /* pcrel_offset */
865
866 HOWTO (R_ARM_ABS32_NOI, /* type */
867 0, /* rightshift */
868 2, /* size (0 = byte, 1 = short, 2 = long) */
869 32, /* bitsize */
870 FALSE, /* pc_relative */
871 0, /* bitpos */
872 complain_overflow_dont,/* complain_on_overflow */
873 bfd_elf_generic_reloc, /* special_function */
874 "R_ARM_ABS32_NOI", /* name */
875 FALSE, /* partial_inplace */
876 0xffffffff, /* src_mask */
877 0xffffffff, /* dst_mask */
878 FALSE), /* pcrel_offset */
879
880 HOWTO (R_ARM_REL32_NOI, /* type */
881 0, /* rightshift */
882 2, /* size (0 = byte, 1 = short, 2 = long) */
883 32, /* bitsize */
884 TRUE, /* pc_relative */
885 0, /* bitpos */
886 complain_overflow_dont,/* complain_on_overflow */
887 bfd_elf_generic_reloc, /* special_function */
888 "R_ARM_REL32_NOI", /* name */
889 FALSE, /* partial_inplace */
890 0xffffffff, /* src_mask */
891 0xffffffff, /* dst_mask */
892 FALSE), /* pcrel_offset */
7f266840 893
4962c51a
MS		 894 /* Group relocations. */
895
896 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
897 0, /* rightshift */
898 2, /* size (0 = byte, 1 = short, 2 = long) */
899 32, /* bitsize */
900 TRUE, /* pc_relative */
901 0, /* bitpos */
902 complain_overflow_dont,/* complain_on_overflow */
903 bfd_elf_generic_reloc, /* special_function */
904 "R_ARM_ALU_PC_G0_NC", /* name */
905 FALSE, /* partial_inplace */
906 0xffffffff, /* src_mask */
907 0xffffffff, /* dst_mask */
908 TRUE), /* pcrel_offset */
909
07d6d2b8 910 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 911 0, /* rightshift */
912 2, /* size (0 = byte, 1 = short, 2 = long) */
913 32, /* bitsize */
914 TRUE, /* pc_relative */
915 0, /* bitpos */
916 complain_overflow_dont,/* complain_on_overflow */
917 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 918 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 919 FALSE, /* partial_inplace */
920 0xffffffff, /* src_mask */
921 0xffffffff, /* dst_mask */
922 TRUE), /* pcrel_offset */
923
924 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
925 0, /* rightshift */
926 2, /* size (0 = byte, 1 = short, 2 = long) */
927 32, /* bitsize */
928 TRUE, /* pc_relative */
929 0, /* bitpos */
930 complain_overflow_dont,/* complain_on_overflow */
931 bfd_elf_generic_reloc, /* special_function */
932 "R_ARM_ALU_PC_G1_NC", /* name */
933 FALSE, /* partial_inplace */
934 0xffffffff, /* src_mask */
935 0xffffffff, /* dst_mask */
936 TRUE), /* pcrel_offset */
937
07d6d2b8 938 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 939 0, /* rightshift */
940 2, /* size (0 = byte, 1 = short, 2 = long) */
941 32, /* bitsize */
942 TRUE, /* pc_relative */
943 0, /* bitpos */
944 complain_overflow_dont,/* complain_on_overflow */
945 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 946 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 947 FALSE, /* partial_inplace */
948 0xffffffff, /* src_mask */
949 0xffffffff, /* dst_mask */
950 TRUE), /* pcrel_offset */
951
07d6d2b8 952 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 953 0, /* rightshift */
954 2, /* size (0 = byte, 1 = short, 2 = long) */
955 32, /* bitsize */
956 TRUE, /* pc_relative */
957 0, /* bitpos */
958 complain_overflow_dont,/* complain_on_overflow */
959 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 960 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 961 FALSE, /* partial_inplace */
962 0xffffffff, /* src_mask */
963 0xffffffff, /* dst_mask */
964 TRUE), /* pcrel_offset */
965
07d6d2b8 966 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 967 0, /* rightshift */
968 2, /* size (0 = byte, 1 = short, 2 = long) */
969 32, /* bitsize */
970 TRUE, /* pc_relative */
971 0, /* bitpos */
972 complain_overflow_dont,/* complain_on_overflow */
973 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 974 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 975 FALSE, /* partial_inplace */
976 0xffffffff, /* src_mask */
977 0xffffffff, /* dst_mask */
978 TRUE), /* pcrel_offset */
979
07d6d2b8 980 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 981 0, /* rightshift */
982 2, /* size (0 = byte, 1 = short, 2 = long) */
983 32, /* bitsize */
984 TRUE, /* pc_relative */
985 0, /* bitpos */
986 complain_overflow_dont,/* complain_on_overflow */
987 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 988 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 989 FALSE, /* partial_inplace */
990 0xffffffff, /* src_mask */
991 0xffffffff, /* dst_mask */
992 TRUE), /* pcrel_offset */
993
07d6d2b8 994 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 995 0, /* rightshift */
996 2, /* size (0 = byte, 1 = short, 2 = long) */
997 32, /* bitsize */
998 TRUE, /* pc_relative */
999 0, /* bitpos */
1000 complain_overflow_dont,/* complain_on_overflow */
1001 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1002 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1003 FALSE, /* partial_inplace */
1004 0xffffffff, /* src_mask */
1005 0xffffffff, /* dst_mask */
1006 TRUE), /* pcrel_offset */
1007
07d6d2b8 1008 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1009 0, /* rightshift */
1010 2, /* size (0 = byte, 1 = short, 2 = long) */
1011 32, /* bitsize */
1012 TRUE, /* pc_relative */
1013 0, /* bitpos */
1014 complain_overflow_dont,/* complain_on_overflow */
1015 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1016 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1017 FALSE, /* partial_inplace */
1018 0xffffffff, /* src_mask */
1019 0xffffffff, /* dst_mask */
1020 TRUE), /* pcrel_offset */
1021
07d6d2b8 1022 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1023 0, /* rightshift */
1024 2, /* size (0 = byte, 1 = short, 2 = long) */
1025 32, /* bitsize */
1026 TRUE, /* pc_relative */
1027 0, /* bitpos */
1028 complain_overflow_dont,/* complain_on_overflow */
1029 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1030 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1031 FALSE, /* partial_inplace */
1032 0xffffffff, /* src_mask */
1033 0xffffffff, /* dst_mask */
1034 TRUE), /* pcrel_offset */
1035
07d6d2b8 1036 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1037 0, /* rightshift */
1038 2, /* size (0 = byte, 1 = short, 2 = long) */
1039 32, /* bitsize */
1040 TRUE, /* pc_relative */
1041 0, /* bitpos */
1042 complain_overflow_dont,/* complain_on_overflow */
1043 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1044 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1045 FALSE, /* partial_inplace */
1046 0xffffffff, /* src_mask */
1047 0xffffffff, /* dst_mask */
1048 TRUE), /* pcrel_offset */
1049
07d6d2b8 1050 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1051 0, /* rightshift */
1052 2, /* size (0 = byte, 1 = short, 2 = long) */
1053 32, /* bitsize */
1054 TRUE, /* pc_relative */
1055 0, /* bitpos */
1056 complain_overflow_dont,/* complain_on_overflow */
1057 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1058 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1059 FALSE, /* partial_inplace */
1060 0xffffffff, /* src_mask */
1061 0xffffffff, /* dst_mask */
1062 TRUE), /* pcrel_offset */
1063
07d6d2b8 1064 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1065 0, /* rightshift */
1066 2, /* size (0 = byte, 1 = short, 2 = long) */
1067 32, /* bitsize */
1068 TRUE, /* pc_relative */
1069 0, /* bitpos */
1070 complain_overflow_dont,/* complain_on_overflow */
1071 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1072 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1073 FALSE, /* partial_inplace */
1074 0xffffffff, /* src_mask */
1075 0xffffffff, /* dst_mask */
1076 TRUE), /* pcrel_offset */
1077
07d6d2b8 1078 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1079 0, /* rightshift */
1080 2, /* size (0 = byte, 1 = short, 2 = long) */
1081 32, /* bitsize */
1082 TRUE, /* pc_relative */
1083 0, /* bitpos */
1084 complain_overflow_dont,/* complain_on_overflow */
1085 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1086 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1087 FALSE, /* partial_inplace */
1088 0xffffffff, /* src_mask */
1089 0xffffffff, /* dst_mask */
1090 TRUE), /* pcrel_offset */
1091
07d6d2b8 1092 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1093 0, /* rightshift */
1094 2, /* size (0 = byte, 1 = short, 2 = long) */
1095 32, /* bitsize */
1096 TRUE, /* pc_relative */
1097 0, /* bitpos */
1098 complain_overflow_dont,/* complain_on_overflow */
1099 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1100 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1101 FALSE, /* partial_inplace */
1102 0xffffffff, /* src_mask */
1103 0xffffffff, /* dst_mask */
1104 TRUE), /* pcrel_offset */
1105
07d6d2b8 1106 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1107 0, /* rightshift */
1108 2, /* size (0 = byte, 1 = short, 2 = long) */
1109 32, /* bitsize */
1110 TRUE, /* pc_relative */
1111 0, /* bitpos */
1112 complain_overflow_dont,/* complain_on_overflow */
1113 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1114 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1115 FALSE, /* partial_inplace */
1116 0xffffffff, /* src_mask */
1117 0xffffffff, /* dst_mask */
1118 TRUE), /* pcrel_offset */
1119
07d6d2b8 1120 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1121 0, /* rightshift */
1122 2, /* size (0 = byte, 1 = short, 2 = long) */
1123 32, /* bitsize */
1124 TRUE, /* pc_relative */
1125 0, /* bitpos */
1126 complain_overflow_dont,/* complain_on_overflow */
1127 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1128 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1129 FALSE, /* partial_inplace */
1130 0xffffffff, /* src_mask */
1131 0xffffffff, /* dst_mask */
1132 TRUE), /* pcrel_offset */
1133
07d6d2b8 1134 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1135 0, /* rightshift */
1136 2, /* size (0 = byte, 1 = short, 2 = long) */
1137 32, /* bitsize */
1138 TRUE, /* pc_relative */
1139 0, /* bitpos */
1140 complain_overflow_dont,/* complain_on_overflow */
1141 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1142 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1143 FALSE, /* partial_inplace */
1144 0xffffffff, /* src_mask */
1145 0xffffffff, /* dst_mask */
1146 TRUE), /* pcrel_offset */
1147
07d6d2b8 1148 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1149 0, /* rightshift */
1150 2, /* size (0 = byte, 1 = short, 2 = long) */
1151 32, /* bitsize */
1152 TRUE, /* pc_relative */
1153 0, /* bitpos */
1154 complain_overflow_dont,/* complain_on_overflow */
1155 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1156 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1157 FALSE, /* partial_inplace */
1158 0xffffffff, /* src_mask */
1159 0xffffffff, /* dst_mask */
1160 TRUE), /* pcrel_offset */
1161
07d6d2b8 1162 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1163 0, /* rightshift */
1164 2, /* size (0 = byte, 1 = short, 2 = long) */
1165 32, /* bitsize */
1166 TRUE, /* pc_relative */
1167 0, /* bitpos */
1168 complain_overflow_dont,/* complain_on_overflow */
1169 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1170 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1171 FALSE, /* partial_inplace */
1172 0xffffffff, /* src_mask */
1173 0xffffffff, /* dst_mask */
1174 TRUE), /* pcrel_offset */
1175
07d6d2b8 1176 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1177 0, /* rightshift */
1178 2, /* size (0 = byte, 1 = short, 2 = long) */
1179 32, /* bitsize */
1180 TRUE, /* pc_relative */
1181 0, /* bitpos */
1182 complain_overflow_dont,/* complain_on_overflow */
1183 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1184 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1185 FALSE, /* partial_inplace */
1186 0xffffffff, /* src_mask */
1187 0xffffffff, /* dst_mask */
1188 TRUE), /* pcrel_offset */
1189
07d6d2b8 1190 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1191 0, /* rightshift */
1192 2, /* size (0 = byte, 1 = short, 2 = long) */
1193 32, /* bitsize */
1194 TRUE, /* pc_relative */
1195 0, /* bitpos */
1196 complain_overflow_dont,/* complain_on_overflow */
1197 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1198 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1199 FALSE, /* partial_inplace */
1200 0xffffffff, /* src_mask */
1201 0xffffffff, /* dst_mask */
1202 TRUE), /* pcrel_offset */
1203
07d6d2b8 1204 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1205 0, /* rightshift */
1206 2, /* size (0 = byte, 1 = short, 2 = long) */
1207 32, /* bitsize */
1208 TRUE, /* pc_relative */
1209 0, /* bitpos */
1210 complain_overflow_dont,/* complain_on_overflow */
1211 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1212 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1213 FALSE, /* partial_inplace */
1214 0xffffffff, /* src_mask */
1215 0xffffffff, /* dst_mask */
1216 TRUE), /* pcrel_offset */
1217
07d6d2b8 1218 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1219 0, /* rightshift */
1220 2, /* size (0 = byte, 1 = short, 2 = long) */
1221 32, /* bitsize */
1222 TRUE, /* pc_relative */
1223 0, /* bitpos */
1224 complain_overflow_dont,/* complain_on_overflow */
1225 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1226 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1227 FALSE, /* partial_inplace */
1228 0xffffffff, /* src_mask */
1229 0xffffffff, /* dst_mask */
1230 TRUE), /* pcrel_offset */
1231
07d6d2b8 1232 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1233 0, /* rightshift */
1234 2, /* size (0 = byte, 1 = short, 2 = long) */
1235 32, /* bitsize */
1236 TRUE, /* pc_relative */
1237 0, /* bitpos */
1238 complain_overflow_dont,/* complain_on_overflow */
1239 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1240 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1241 FALSE, /* partial_inplace */
1242 0xffffffff, /* src_mask */
1243 0xffffffff, /* dst_mask */
1244 TRUE), /* pcrel_offset */
1245
07d6d2b8 1246 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1247 0, /* rightshift */
1248 2, /* size (0 = byte, 1 = short, 2 = long) */
1249 32, /* bitsize */
1250 TRUE, /* pc_relative */
1251 0, /* bitpos */
1252 complain_overflow_dont,/* complain_on_overflow */
1253 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1254 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1255 FALSE, /* partial_inplace */
1256 0xffffffff, /* src_mask */
1257 0xffffffff, /* dst_mask */
1258 TRUE), /* pcrel_offset */
1259
07d6d2b8 1260 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1261 0, /* rightshift */
1262 2, /* size (0 = byte, 1 = short, 2 = long) */
1263 32, /* bitsize */
1264 TRUE, /* pc_relative */
1265 0, /* bitpos */
1266 complain_overflow_dont,/* complain_on_overflow */
1267 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1268 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1269 FALSE, /* partial_inplace */
1270 0xffffffff, /* src_mask */
1271 0xffffffff, /* dst_mask */
1272 TRUE), /* pcrel_offset */
1273
1274 /* End of group relocations. */
c19d1205 1275
c19d1205
ZW		 1276 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1277 0, /* rightshift */
1278 2, /* size (0 = byte, 1 = short, 2 = long) */
1279 16, /* bitsize */
1280 FALSE, /* pc_relative */
1281 0, /* bitpos */
1282 complain_overflow_dont,/* complain_on_overflow */
1283 bfd_elf_generic_reloc, /* special_function */
1284 "R_ARM_MOVW_BREL_NC", /* name */
1285 FALSE, /* partial_inplace */
1286 0x0000ffff, /* src_mask */
1287 0x0000ffff, /* dst_mask */
1288 FALSE), /* pcrel_offset */
1289
1290 HOWTO (R_ARM_MOVT_BREL, /* type */
1291 0, /* rightshift */
1292 2, /* size (0 = byte, 1 = short, 2 = long) */
1293 16, /* bitsize */
1294 FALSE, /* pc_relative */
1295 0, /* bitpos */
1296 complain_overflow_bitfield,/* complain_on_overflow */
1297 bfd_elf_generic_reloc, /* special_function */
1298 "R_ARM_MOVT_BREL", /* name */
1299 FALSE, /* partial_inplace */
1300 0x0000ffff, /* src_mask */
1301 0x0000ffff, /* dst_mask */
1302 FALSE), /* pcrel_offset */
1303
1304 HOWTO (R_ARM_MOVW_BREL, /* type */
1305 0, /* rightshift */
1306 2, /* size (0 = byte, 1 = short, 2 = long) */
1307 16, /* bitsize */
1308 FALSE, /* pc_relative */
1309 0, /* bitpos */
1310 complain_overflow_dont,/* complain_on_overflow */
1311 bfd_elf_generic_reloc, /* special_function */
1312 "R_ARM_MOVW_BREL", /* name */
1313 FALSE, /* partial_inplace */
1314 0x0000ffff, /* src_mask */
1315 0x0000ffff, /* dst_mask */
1316 FALSE), /* pcrel_offset */
1317
1318 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1319 0, /* rightshift */
1320 2, /* size (0 = byte, 1 = short, 2 = long) */
1321 16, /* bitsize */
1322 FALSE, /* pc_relative */
1323 0, /* bitpos */
1324 complain_overflow_dont,/* complain_on_overflow */
1325 bfd_elf_generic_reloc, /* special_function */
1326 "R_ARM_THM_MOVW_BREL_NC",/* name */
1327 FALSE, /* partial_inplace */
1328 0x040f70ff, /* src_mask */
1329 0x040f70ff, /* dst_mask */
1330 FALSE), /* pcrel_offset */
1331
1332 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1333 0, /* rightshift */
1334 2, /* size (0 = byte, 1 = short, 2 = long) */
1335 16, /* bitsize */
1336 FALSE, /* pc_relative */
1337 0, /* bitpos */
1338 complain_overflow_bitfield,/* complain_on_overflow */
1339 bfd_elf_generic_reloc, /* special_function */
1340 "R_ARM_THM_MOVT_BREL", /* name */
1341 FALSE, /* partial_inplace */
1342 0x040f70ff, /* src_mask */
1343 0x040f70ff, /* dst_mask */
1344 FALSE), /* pcrel_offset */
1345
1346 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1347 0, /* rightshift */
1348 2, /* size (0 = byte, 1 = short, 2 = long) */
1349 16, /* bitsize */
1350 FALSE, /* pc_relative */
1351 0, /* bitpos */
1352 complain_overflow_dont,/* complain_on_overflow */
1353 bfd_elf_generic_reloc, /* special_function */
1354 "R_ARM_THM_MOVW_BREL", /* name */
1355 FALSE, /* partial_inplace */
1356 0x040f70ff, /* src_mask */
1357 0x040f70ff, /* dst_mask */
1358 FALSE), /* pcrel_offset */
1359
0855e32b
NS		 1360 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1361 0, /* rightshift */
1362 2, /* size (0 = byte, 1 = short, 2 = long) */
1363 32, /* bitsize */
1364 FALSE, /* pc_relative */
1365 0, /* bitpos */
1366 complain_overflow_bitfield,/* complain_on_overflow */
1367 NULL, /* special_function */
1368 "R_ARM_TLS_GOTDESC", /* name */
1369 TRUE, /* partial_inplace */
1370 0xffffffff, /* src_mask */
1371 0xffffffff, /* dst_mask */
1372 FALSE), /* pcrel_offset */
1373
1374 HOWTO (R_ARM_TLS_CALL, /* type */
1375 0, /* rightshift */
1376 2, /* size (0 = byte, 1 = short, 2 = long) */
1377 24, /* bitsize */
1378 FALSE, /* pc_relative */
1379 0, /* bitpos */
1380 complain_overflow_dont,/* complain_on_overflow */
1381 bfd_elf_generic_reloc, /* special_function */
1382 "R_ARM_TLS_CALL", /* name */
1383 FALSE, /* partial_inplace */
1384 0x00ffffff, /* src_mask */
1385 0x00ffffff, /* dst_mask */
1386 FALSE), /* pcrel_offset */
1387
1388 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1389 0, /* rightshift */
1390 2, /* size (0 = byte, 1 = short, 2 = long) */
1391 0, /* bitsize */
1392 FALSE, /* pc_relative */
1393 0, /* bitpos */
821e059c 1394 complain_overflow_dont,/* complain_on_overflow */
0855e32b
NS		 1395 bfd_elf_generic_reloc, /* special_function */
1396 "R_ARM_TLS_DESCSEQ", /* name */
1397 FALSE, /* partial_inplace */
1398 0x00000000, /* src_mask */
1399 0x00000000, /* dst_mask */
1400 FALSE), /* pcrel_offset */
1401
1402 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1403 0, /* rightshift */
1404 2, /* size (0 = byte, 1 = short, 2 = long) */
1405 24, /* bitsize */
1406 FALSE, /* pc_relative */
1407 0, /* bitpos */
1408 complain_overflow_dont,/* complain_on_overflow */
1409 bfd_elf_generic_reloc, /* special_function */
1410 "R_ARM_THM_TLS_CALL", /* name */
1411 FALSE, /* partial_inplace */
1412 0x07ff07ff, /* src_mask */
1413 0x07ff07ff, /* dst_mask */
1414 FALSE), /* pcrel_offset */
c19d1205
ZW		 1415
1416 HOWTO (R_ARM_PLT32_ABS, /* type */
1417 0, /* rightshift */
1418 2, /* size (0 = byte, 1 = short, 2 = long) */
1419 32, /* bitsize */
1420 FALSE, /* pc_relative */
1421 0, /* bitpos */
1422 complain_overflow_dont,/* complain_on_overflow */
1423 bfd_elf_generic_reloc, /* special_function */
1424 "R_ARM_PLT32_ABS", /* name */
1425 FALSE, /* partial_inplace */
1426 0xffffffff, /* src_mask */
1427 0xffffffff, /* dst_mask */
1428 FALSE), /* pcrel_offset */
1429
1430 HOWTO (R_ARM_GOT_ABS, /* type */
1431 0, /* rightshift */
1432 2, /* size (0 = byte, 1 = short, 2 = long) */
1433 32, /* bitsize */
1434 FALSE, /* pc_relative */
1435 0, /* bitpos */
1436 complain_overflow_dont,/* complain_on_overflow */
1437 bfd_elf_generic_reloc, /* special_function */
1438 "R_ARM_GOT_ABS", /* name */
1439 FALSE, /* partial_inplace */
1440 0xffffffff, /* src_mask */
1441 0xffffffff, /* dst_mask */
1442 FALSE), /* pcrel_offset */
1443
1444 HOWTO (R_ARM_GOT_PREL, /* type */
1445 0, /* rightshift */
1446 2, /* size (0 = byte, 1 = short, 2 = long) */
1447 32, /* bitsize */
1448 TRUE, /* pc_relative */
1449 0, /* bitpos */
1450 complain_overflow_dont, /* complain_on_overflow */
1451 bfd_elf_generic_reloc, /* special_function */
1452 "R_ARM_GOT_PREL", /* name */
1453 FALSE, /* partial_inplace */
1454 0xffffffff, /* src_mask */
1455 0xffffffff, /* dst_mask */
1456 TRUE), /* pcrel_offset */
1457
1458 HOWTO (R_ARM_GOT_BREL12, /* type */
1459 0, /* rightshift */
1460 2, /* size (0 = byte, 1 = short, 2 = long) */
1461 12, /* bitsize */
1462 FALSE, /* pc_relative */
1463 0, /* bitpos */
1464 complain_overflow_bitfield,/* complain_on_overflow */
1465 bfd_elf_generic_reloc, /* special_function */
1466 "R_ARM_GOT_BREL12", /* name */
1467 FALSE, /* partial_inplace */
1468 0x00000fff, /* src_mask */
1469 0x00000fff, /* dst_mask */
1470 FALSE), /* pcrel_offset */
1471
1472 HOWTO (R_ARM_GOTOFF12, /* type */
1473 0, /* rightshift */
1474 2, /* size (0 = byte, 1 = short, 2 = long) */
1475 12, /* bitsize */
1476 FALSE, /* pc_relative */
1477 0, /* bitpos */
1478 complain_overflow_bitfield,/* complain_on_overflow */
1479 bfd_elf_generic_reloc, /* special_function */
1480 "R_ARM_GOTOFF12", /* name */
1481 FALSE, /* partial_inplace */
1482 0x00000fff, /* src_mask */
1483 0x00000fff, /* dst_mask */
1484 FALSE), /* pcrel_offset */
1485
07d6d2b8 1486 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1487
1488 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1489 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1490 0, /* rightshift */
1491 2, /* size (0 = byte, 1 = short, 2 = long) */
1492 0, /* bitsize */
1493 FALSE, /* pc_relative */
1494 0, /* bitpos */
99059e56 1495 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1496 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1497 "R_ARM_GNU_VTENTRY", /* name */
1498 FALSE, /* partial_inplace */
1499 0, /* src_mask */
1500 0, /* dst_mask */
1501 FALSE), /* pcrel_offset */
c19d1205
ZW		 1502
1503 /* GNU extension to record C++ vtable hierarchy */
1504 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1505 0, /* rightshift */
1506 2, /* size (0 = byte, 1 = short, 2 = long) */
1507 0, /* bitsize */
1508 FALSE, /* pc_relative */
1509 0, /* bitpos */
99059e56 1510 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1511 NULL, /* special_function */
99059e56 1512 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1513 FALSE, /* partial_inplace */
1514 0, /* src_mask */
1515 0, /* dst_mask */
1516 FALSE), /* pcrel_offset */
c19d1205
ZW		 1517
1518 HOWTO (R_ARM_THM_JUMP11, /* type */
1519 1, /* rightshift */
1520 1, /* size (0 = byte, 1 = short, 2 = long) */
1521 11, /* bitsize */
1522 TRUE, /* pc_relative */
1523 0, /* bitpos */
1524 complain_overflow_signed, /* complain_on_overflow */
1525 bfd_elf_generic_reloc, /* special_function */
1526 "R_ARM_THM_JUMP11", /* name */
1527 FALSE, /* partial_inplace */
1528 0x000007ff, /* src_mask */
1529 0x000007ff, /* dst_mask */
1530 TRUE), /* pcrel_offset */
1531
1532 HOWTO (R_ARM_THM_JUMP8, /* type */
1533 1, /* rightshift */
1534 1, /* size (0 = byte, 1 = short, 2 = long) */
1535 8, /* bitsize */
1536 TRUE, /* pc_relative */
1537 0, /* bitpos */
1538 complain_overflow_signed, /* complain_on_overflow */
1539 bfd_elf_generic_reloc, /* special_function */
1540 "R_ARM_THM_JUMP8", /* name */
1541 FALSE, /* partial_inplace */
1542 0x000000ff, /* src_mask */
1543 0x000000ff, /* dst_mask */
1544 TRUE), /* pcrel_offset */
ba93b8ac 1545
c19d1205
ZW		 1546 /* TLS relocations */
1547 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1548 0, /* rightshift */
1549 2, /* size (0 = byte, 1 = short, 2 = long) */
1550 32, /* bitsize */
1551 FALSE, /* pc_relative */
1552 0, /* bitpos */
99059e56
RM		 1553 complain_overflow_bitfield,/* complain_on_overflow */
1554 NULL, /* special_function */
1555 "R_ARM_TLS_GD32", /* name */
1556 TRUE, /* partial_inplace */
1557 0xffffffff, /* src_mask */
1558 0xffffffff, /* dst_mask */
07d6d2b8 1559 FALSE), /* pcrel_offset */
ba93b8ac 1560
ba93b8ac 1561 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1562 0, /* rightshift */
1563 2, /* size (0 = byte, 1 = short, 2 = long) */
1564 32, /* bitsize */
1565 FALSE, /* pc_relative */
1566 0, /* bitpos */
99059e56
RM		 1567 complain_overflow_bitfield,/* complain_on_overflow */
1568 bfd_elf_generic_reloc, /* special_function */
1569 "R_ARM_TLS_LDM32", /* name */
1570 TRUE, /* partial_inplace */
1571 0xffffffff, /* src_mask */
1572 0xffffffff, /* dst_mask */
07d6d2b8 1573 FALSE), /* pcrel_offset */
ba93b8ac 1574
c19d1205 1575 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1576 0, /* rightshift */
1577 2, /* size (0 = byte, 1 = short, 2 = long) */
1578 32, /* bitsize */
1579 FALSE, /* pc_relative */
1580 0, /* bitpos */
99059e56
RM		 1581 complain_overflow_bitfield,/* complain_on_overflow */
1582 bfd_elf_generic_reloc, /* special_function */
1583 "R_ARM_TLS_LDO32", /* name */
1584 TRUE, /* partial_inplace */
1585 0xffffffff, /* src_mask */
1586 0xffffffff, /* dst_mask */
07d6d2b8 1587 FALSE), /* pcrel_offset */
ba93b8ac 1588
ba93b8ac 1589 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1590 0, /* rightshift */
1591 2, /* size (0 = byte, 1 = short, 2 = long) */
1592 32, /* bitsize */
1593 FALSE, /* pc_relative */
1594 0, /* bitpos */
99059e56
RM		 1595 complain_overflow_bitfield,/* complain_on_overflow */
1596 NULL, /* special_function */
1597 "R_ARM_TLS_IE32", /* name */
1598 TRUE, /* partial_inplace */
1599 0xffffffff, /* src_mask */
1600 0xffffffff, /* dst_mask */
07d6d2b8 1601 FALSE), /* pcrel_offset */
7f266840 1602
c19d1205 1603 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1604 0, /* rightshift */
1605 2, /* size (0 = byte, 1 = short, 2 = long) */
1606 32, /* bitsize */
1607 FALSE, /* pc_relative */
1608 0, /* bitpos */
99059e56 1609 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1610 NULL, /* special_function */
99059e56
RM		 1611 "R_ARM_TLS_LE32", /* name */
1612 TRUE, /* partial_inplace */
1613 0xffffffff, /* src_mask */
1614 0xffffffff, /* dst_mask */
07d6d2b8 1615 FALSE), /* pcrel_offset */
7f266840 1616
c19d1205
ZW		 1617 HOWTO (R_ARM_TLS_LDO12, /* type */
1618 0, /* rightshift */
1619 2, /* size (0 = byte, 1 = short, 2 = long) */
1620 12, /* bitsize */
1621 FALSE, /* pc_relative */
7f266840 1622 0, /* bitpos */
c19d1205 1623 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1624 bfd_elf_generic_reloc, /* special_function */
c19d1205 1625 "R_ARM_TLS_LDO12", /* name */
7f266840 1626 FALSE, /* partial_inplace */
c19d1205
ZW		 1627 0x00000fff, /* src_mask */
1628 0x00000fff, /* dst_mask */
1629 FALSE), /* pcrel_offset */
7f266840 1630
c19d1205
ZW		 1631 HOWTO (R_ARM_TLS_LE12, /* type */
1632 0, /* rightshift */
1633 2, /* size (0 = byte, 1 = short, 2 = long) */
1634 12, /* bitsize */
1635 FALSE, /* pc_relative */
7f266840 1636 0, /* bitpos */
c19d1205 1637 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1638 bfd_elf_generic_reloc, /* special_function */
c19d1205 1639 "R_ARM_TLS_LE12", /* name */
7f266840 1640 FALSE, /* partial_inplace */
c19d1205
ZW		 1641 0x00000fff, /* src_mask */
1642 0x00000fff, /* dst_mask */
1643 FALSE), /* pcrel_offset */
7f266840 1644
c19d1205 1645 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1646 0, /* rightshift */
1647 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1648 12, /* bitsize */
1649 FALSE, /* pc_relative */
7f266840 1650 0, /* bitpos */
c19d1205 1651 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1652 bfd_elf_generic_reloc, /* special_function */
c19d1205 1653 "R_ARM_TLS_IE12GP", /* name */
7f266840 1654 FALSE, /* partial_inplace */
c19d1205
ZW		 1655 0x00000fff, /* src_mask */
1656 0x00000fff, /* dst_mask */
1657 FALSE), /* pcrel_offset */
0855e32b 1658
34e77a92 1659 /* 112-127 private relocations. */
0855e32b
NS		 1660 EMPTY_HOWTO (112),
1661 EMPTY_HOWTO (113),
1662 EMPTY_HOWTO (114),
1663 EMPTY_HOWTO (115),
1664 EMPTY_HOWTO (116),
1665 EMPTY_HOWTO (117),
1666 EMPTY_HOWTO (118),
1667 EMPTY_HOWTO (119),
1668 EMPTY_HOWTO (120),
1669 EMPTY_HOWTO (121),
1670 EMPTY_HOWTO (122),
1671 EMPTY_HOWTO (123),
1672 EMPTY_HOWTO (124),
1673 EMPTY_HOWTO (125),
1674 EMPTY_HOWTO (126),
1675 EMPTY_HOWTO (127),
34e77a92
RS		 1676
1677 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1678 EMPTY_HOWTO (128),
1679
1680 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1681 0, /* rightshift */
1682 1, /* size (0 = byte, 1 = short, 2 = long) */
1683 0, /* bitsize */
1684 FALSE, /* pc_relative */
1685 0, /* bitpos */
821e059c 1686 complain_overflow_dont,/* complain_on_overflow */
0855e32b
NS		 1687 bfd_elf_generic_reloc, /* special_function */
1688 "R_ARM_THM_TLS_DESCSEQ",/* name */
1689 FALSE, /* partial_inplace */
1690 0x00000000, /* src_mask */
1691 0x00000000, /* dst_mask */
1692 FALSE), /* pcrel_offset */
72d98d16
MG		 1693 EMPTY_HOWTO (130),
1694 EMPTY_HOWTO (131),
1695 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1696 0, /* rightshift. */
1697 1, /* size (0 = byte, 1 = short, 2 = long). */
1698 16, /* bitsize. */
1699 FALSE, /* pc_relative. */
1700 0, /* bitpos. */
1701 complain_overflow_bitfield,/* complain_on_overflow. */
1702 bfd_elf_generic_reloc, /* special_function. */
1703 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1704 FALSE, /* partial_inplace. */
1705 0x00000000, /* src_mask. */
1706 0x00000000, /* dst_mask. */
1707 FALSE), /* pcrel_offset. */
1708 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1709 0, /* rightshift. */
1710 1, /* size (0 = byte, 1 = short, 2 = long). */
1711 16, /* bitsize. */
1712 FALSE, /* pc_relative. */
1713 0, /* bitpos. */
1714 complain_overflow_bitfield,/* complain_on_overflow. */
1715 bfd_elf_generic_reloc, /* special_function. */
1716 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1717 FALSE, /* partial_inplace. */
1718 0x00000000, /* src_mask. */
1719 0x00000000, /* dst_mask. */
1720 FALSE), /* pcrel_offset. */
1721 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1722 0, /* rightshift. */
1723 1, /* size (0 = byte, 1 = short, 2 = long). */
1724 16, /* bitsize. */
1725 FALSE, /* pc_relative. */
1726 0, /* bitpos. */
1727 complain_overflow_bitfield,/* complain_on_overflow. */
1728 bfd_elf_generic_reloc, /* special_function. */
1729 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1730 FALSE, /* partial_inplace. */
1731 0x00000000, /* src_mask. */
1732 0x00000000, /* dst_mask. */
1733 FALSE), /* pcrel_offset. */
1734 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1735 0, /* rightshift. */
1736 1, /* size (0 = byte, 1 = short, 2 = long). */
1737 16, /* bitsize. */
1738 FALSE, /* pc_relative. */
1739 0, /* bitpos. */
1740 complain_overflow_bitfield,/* complain_on_overflow. */
1741 bfd_elf_generic_reloc, /* special_function. */
1742 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1743 FALSE, /* partial_inplace. */
1744 0x00000000, /* src_mask. */
1745 0x00000000, /* dst_mask. */
1746 FALSE), /* pcrel_offset. */
e5d6e09e
AV		 1747 /* Relocations for Armv8.1-M Mainline. */
1748 HOWTO (R_ARM_THM_BF16, /* type. */
1749 0, /* rightshift. */
1750 1, /* size (0 = byte, 1 = short, 2 = long). */
1751 16, /* bitsize. */
1752 TRUE, /* pc_relative. */
1753 0, /* bitpos. */
1754 complain_overflow_dont,/* do not complain_on_overflow. */
1755 bfd_elf_generic_reloc, /* special_function. */
1756 "R_ARM_THM_BF16", /* name. */
1757 FALSE, /* partial_inplace. */
1758 0x001f0ffe, /* src_mask. */
1759 0x001f0ffe, /* dst_mask. */
1760 TRUE), /* pcrel_offset. */
1889da70
AV		 1761 HOWTO (R_ARM_THM_BF12, /* type. */
1762 0, /* rightshift. */
1763 1, /* size (0 = byte, 1 = short, 2 = long). */
1764 12, /* bitsize. */
1765 TRUE, /* pc_relative. */
1766 0, /* bitpos. */
1767 complain_overflow_dont,/* do not complain_on_overflow. */
1768 bfd_elf_generic_reloc, /* special_function. */
1769 "R_ARM_THM_BF12", /* name. */
1770 FALSE, /* partial_inplace. */
1771 0x00010ffe, /* src_mask. */
1772 0x00010ffe, /* dst_mask. */
1773 TRUE), /* pcrel_offset. */
1caf72a5
AV		 1774 HOWTO (R_ARM_THM_BF18, /* type. */
1775 0, /* rightshift. */
1776 1, /* size (0 = byte, 1 = short, 2 = long). */
1777 18, /* bitsize. */
1778 TRUE, /* pc_relative. */
1779 0, /* bitpos. */
1780 complain_overflow_dont,/* do not complain_on_overflow. */
1781 bfd_elf_generic_reloc, /* special_function. */
1782 "R_ARM_THM_BF18", /* name. */
1783 FALSE, /* partial_inplace. */
1784 0x007f0ffe, /* src_mask. */
1785 0x007f0ffe, /* dst_mask. */
1786 TRUE), /* pcrel_offset. */
c19d1205
ZW		 1787};
1788
34e77a92 1789/* 160 onwards: */
5c5a4843 1790static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1791{
1792 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1793 0, /* rightshift */
1794 2, /* size (0 = byte, 1 = short, 2 = long) */
1795 32, /* bitsize */
1796 FALSE, /* pc_relative */
1797 0, /* bitpos */
99059e56
RM		 1798 complain_overflow_bitfield,/* complain_on_overflow */
1799 bfd_elf_generic_reloc, /* special_function */
1800 "R_ARM_IRELATIVE", /* name */
1801 TRUE, /* partial_inplace */
1802 0xffffffff, /* src_mask */
1803 0xffffffff, /* dst_mask */
188fd7ae
CL		 1804 FALSE), /* pcrel_offset */
1805 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1806 0, /* rightshift */
1807 2, /* size (0 = byte, 1 = short, 2 = long) */
1808 32, /* bitsize */
1809 FALSE, /* pc_relative */
1810 0, /* bitpos */
1811 complain_overflow_bitfield,/* complain_on_overflow */
1812 bfd_elf_generic_reloc, /* special_function */
1813 "R_ARM_GOTFUNCDESC", /* name */
1814 FALSE, /* partial_inplace */
1815 0, /* src_mask */
1816 0xffffffff, /* dst_mask */
1817 FALSE), /* pcrel_offset */
1818 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1819 0, /* rightshift */
1820 2, /* size (0 = byte, 1 = short, 2 = long) */
1821 32, /* bitsize */
1822 FALSE, /* pc_relative */
1823 0, /* bitpos */
1824 complain_overflow_bitfield,/* complain_on_overflow */
1825 bfd_elf_generic_reloc, /* special_function */
1826 "R_ARM_GOTOFFFUNCDESC",/* name */
1827 FALSE, /* partial_inplace */
1828 0, /* src_mask */
1829 0xffffffff, /* dst_mask */
1830 FALSE), /* pcrel_offset */
1831 HOWTO (R_ARM_FUNCDESC, /* type */
1832 0, /* rightshift */
1833 2, /* size (0 = byte, 1 = short, 2 = long) */
1834 32, /* bitsize */
1835 FALSE, /* pc_relative */
1836 0, /* bitpos */
1837 complain_overflow_bitfield,/* complain_on_overflow */
1838 bfd_elf_generic_reloc, /* special_function */
1839 "R_ARM_FUNCDESC", /* name */
1840 FALSE, /* partial_inplace */
1841 0, /* src_mask */
1842 0xffffffff, /* dst_mask */
1843 FALSE), /* pcrel_offset */
1844 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1845 0, /* rightshift */
1846 2, /* size (0 = byte, 1 = short, 2 = long) */
1847 64, /* bitsize */
1848 FALSE, /* pc_relative */
1849 0, /* bitpos */
1850 complain_overflow_bitfield,/* complain_on_overflow */
1851 bfd_elf_generic_reloc, /* special_function */
1852 "R_ARM_FUNCDESC_VALUE",/* name */
1853 FALSE, /* partial_inplace */
1854 0, /* src_mask */
1855 0xffffffff, /* dst_mask */
1856 FALSE), /* pcrel_offset */
5c5a4843
CL		 1857 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1858 0, /* rightshift */
1859 2, /* size (0 = byte, 1 = short, 2 = long) */
1860 32, /* bitsize */
1861 FALSE, /* pc_relative */
1862 0, /* bitpos */
1863 complain_overflow_bitfield,/* complain_on_overflow */
1864 bfd_elf_generic_reloc, /* special_function */
1865 "R_ARM_TLS_GD32_FDPIC",/* name */
1866 FALSE, /* partial_inplace */
1867 0, /* src_mask */
1868 0xffffffff, /* dst_mask */
1869 FALSE), /* pcrel_offset */
1870 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1871 0, /* rightshift */
1872 2, /* size (0 = byte, 1 = short, 2 = long) */
1873 32, /* bitsize */
1874 FALSE, /* pc_relative */
1875 0, /* bitpos */
1876 complain_overflow_bitfield,/* complain_on_overflow */
1877 bfd_elf_generic_reloc, /* special_function */
1878 "R_ARM_TLS_LDM32_FDPIC",/* name */
1879 FALSE, /* partial_inplace */
1880 0, /* src_mask */
1881 0xffffffff, /* dst_mask */
1882 FALSE), /* pcrel_offset */
1883 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1884 0, /* rightshift */
1885 2, /* size (0 = byte, 1 = short, 2 = long) */
1886 32, /* bitsize */
1887 FALSE, /* pc_relative */
1888 0, /* bitpos */
1889 complain_overflow_bitfield,/* complain_on_overflow */
1890 bfd_elf_generic_reloc, /* special_function */
1891 "R_ARM_TLS_IE32_FDPIC",/* name */
1892 FALSE, /* partial_inplace */
1893 0, /* src_mask */
1894 0xffffffff, /* dst_mask */
1895 FALSE), /* pcrel_offset */
34e77a92 1896};
c19d1205 1897
34e77a92
RS		 1898/* 249-255 extended, currently unused, relocations: */
1899static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1900{
1901 HOWTO (R_ARM_RREL32, /* type */
1902 0, /* rightshift */
1903 0, /* size (0 = byte, 1 = short, 2 = long) */
1904 0, /* bitsize */
1905 FALSE, /* pc_relative */
1906 0, /* bitpos */
1907 complain_overflow_dont,/* complain_on_overflow */
1908 bfd_elf_generic_reloc, /* special_function */
1909 "R_ARM_RREL32", /* name */
1910 FALSE, /* partial_inplace */
1911 0, /* src_mask */
1912 0, /* dst_mask */
1913 FALSE), /* pcrel_offset */
1914
1915 HOWTO (R_ARM_RABS32, /* type */
1916 0, /* rightshift */
1917 0, /* size (0 = byte, 1 = short, 2 = long) */
1918 0, /* bitsize */
1919 FALSE, /* pc_relative */
1920 0, /* bitpos */
1921 complain_overflow_dont,/* complain_on_overflow */
1922 bfd_elf_generic_reloc, /* special_function */
1923 "R_ARM_RABS32", /* name */
1924 FALSE, /* partial_inplace */
1925 0, /* src_mask */
1926 0, /* dst_mask */
1927 FALSE), /* pcrel_offset */
1928
1929 HOWTO (R_ARM_RPC24, /* type */
1930 0, /* rightshift */
1931 0, /* size (0 = byte, 1 = short, 2 = long) */
1932 0, /* bitsize */
1933 FALSE, /* pc_relative */
1934 0, /* bitpos */
1935 complain_overflow_dont,/* complain_on_overflow */
1936 bfd_elf_generic_reloc, /* special_function */
1937 "R_ARM_RPC24", /* name */
1938 FALSE, /* partial_inplace */
1939 0, /* src_mask */
1940 0, /* dst_mask */
1941 FALSE), /* pcrel_offset */
1942
1943 HOWTO (R_ARM_RBASE, /* type */
1944 0, /* rightshift */
1945 0, /* size (0 = byte, 1 = short, 2 = long) */
1946 0, /* bitsize */
1947 FALSE, /* pc_relative */
1948 0, /* bitpos */
1949 complain_overflow_dont,/* complain_on_overflow */
1950 bfd_elf_generic_reloc, /* special_function */
1951 "R_ARM_RBASE", /* name */
1952 FALSE, /* partial_inplace */
1953 0, /* src_mask */
1954 0, /* dst_mask */
1955 FALSE) /* pcrel_offset */
1956};
1957
1958static reloc_howto_type *
1959elf32_arm_howto_from_type (unsigned int r_type)
1960{
906e58ca 1961 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1962 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1963
188fd7ae
CL		 1964 if (r_type >= R_ARM_IRELATIVE
1965 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1966 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1967
c19d1205 1968 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1969 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1970 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1971
c19d1205 1972 return NULL;
7f266840
DJ		 1973}
1974
f3185997
NC		 1975static bfd_boolean
1976elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1977 Elf_Internal_Rela * elf_reloc)
1978{
1979 unsigned int r_type;
1980
1981 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1982 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1983 {
1984 /* xgettext:c-format */
1985 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1986 abfd, r_type);
1987 bfd_set_error (bfd_error_bad_value);
1988 return FALSE;
1989 }
1990 return TRUE;
7f266840
DJ		 1991}
1992
1993struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1996 unsigned char elf_reloc_val;
7f266840
DJ		 1997 };
1998
1999/* All entries in this list must also be present in elf32_arm_howto_table. */
2000static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
2001 {
07d6d2b8 2002 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 2003 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 2004 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
2005 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 2006 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
2007 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
2008 {BFD_RELOC_32, R_ARM_ABS32},
2009 {BFD_RELOC_32_PCREL, R_ARM_REL32},
2010 {BFD_RELOC_8, R_ARM_ABS8},
2011 {BFD_RELOC_16, R_ARM_ABS16},
2012 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 2013 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 2014 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
2015 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
2016 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
2017 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
2018 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
2019 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 2020 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
2021 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
2022 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
2023 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
2024 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
2025 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
2026 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
2027 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 2028 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
2029 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
2030 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
2031 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 2032 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 2033 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
2034 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
2035 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 2036 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 2037 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 2038 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 2039 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 2040 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2041 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2042 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2043 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2044 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2045 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2046 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2047 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2048 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2049 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2050 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2051 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2052 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2053 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2054 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2055 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2056 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2057 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2058 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2059 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2060 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2061 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2062 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2063 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2064 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2065 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2066 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2067 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2068 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2069 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2070 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2071 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2072 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2073 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2074 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2075 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2076 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2077 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2078 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2079 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2080 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2081 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2082 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2083 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2084 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2085 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2086 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2087 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2088 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2089 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2090 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2091 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2092 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2093 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2094 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2095 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2096 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2097 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
e5d6e09e 2098 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
1caf72a5 2099 {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
1889da70 2100 {BFD_RELOC_ARM_THUMB_BF13, R_ARM_THM_BF12},
1caf72a5 2101 {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
7f266840
DJ		 2102 };
2103
2104static reloc_howto_type *
f1c71a59
ZW		 2105elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2106 bfd_reloc_code_real_type code)
7f266840
DJ		 2107{
2108 unsigned int i;
8029a119 2109
906e58ca 2110 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2111 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2112 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2113
c19d1205 2114 return NULL;
7f266840
DJ		 2115}
2116
157090f7
AM		 2117static reloc_howto_type *
2118elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2119 const char *r_name)
2120{
2121 unsigned int i;
2122
906e58ca 2123 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2124 if (elf32_arm_howto_table_1[i].name != NULL
2125 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2126 return &elf32_arm_howto_table_1[i];
2127
906e58ca 2128 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2129 if (elf32_arm_howto_table_2[i].name != NULL
2130 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2131 return &elf32_arm_howto_table_2[i];
2132
34e77a92
RS		 2133 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2134 if (elf32_arm_howto_table_3[i].name != NULL
2135 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2136 return &elf32_arm_howto_table_3[i];
2137
157090f7
AM		 2138 return NULL;
2139}
2140
906e58ca
NC		 2141/* Support for core dump NOTE sections. */
2142
7f266840 2143static bfd_boolean
f1c71a59 2144elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2145{
2146 int offset;
2147 size_t size;
2148
2149 switch (note->descsz)
2150 {
2151 default:
2152 return FALSE;
2153
8029a119 2154 case 148: /* Linux/ARM 32-bit. */
7f266840 2155 /* pr_cursig */
228e534f 2156 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2157
2158 /* pr_pid */
228e534f 2159 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2160
2161 /* pr_reg */
2162 offset = 72;
2163 size = 72;
2164
2165 break;
2166 }
2167
2168 /* Make a ".reg/999" section. */
2169 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2170 size, note->descpos + offset);
2171}
2172
2173static bfd_boolean
f1c71a59 2174elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2175{
2176 switch (note->descsz)
2177 {
2178 default:
2179 return FALSE;
2180
8029a119 2181 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2182 elf_tdata (abfd)->core->pid
4395ee08 2183 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2184 elf_tdata (abfd)->core->program
7f266840 2185 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2186 elf_tdata (abfd)->core->command
7f266840
DJ		 2187 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2188 }
2189
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
7f266840 2193 {
228e534f 2194 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2195 int n = strlen (command);
2196
2197 if (0 < n && command[n - 1] == ' ')
2198 command[n - 1] = '\0';
2199 }
2200
2201 return TRUE;
2202}
2203
1f20dca5
UW		 2204static char *
2205elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2206 int note_type, ...)
2207{
2208 switch (note_type)
2209 {
2210 default:
2211 return NULL;
2212
2213 case NT_PRPSINFO:
2214 {
602f1657 2215 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2216 va_list ap;
2217
2218 va_start (ap, note_type);
2219 memset (data, 0, sizeof (data));
2220 strncpy (data + 28, va_arg (ap, const char *), 16);
be3e27bb 2221#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2222 DIAGNOSTIC_PUSH;
be3e27bb 2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
95da9854
L		 2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228#endif
1f20dca5 2229 strncpy (data + 44, va_arg (ap, const char *), 80);
be3e27bb 2230#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2231 DIAGNOSTIC_POP;
fe75810f 2232#endif
1f20dca5
UW		 2233 va_end (ap);
2234
2235 return elfcore_write_note (abfd, buf, bufsiz,
2236 "CORE", note_type, data, sizeof (data));
2237 }
2238
2239 case NT_PRSTATUS:
2240 {
2241 char data[148];
2242 va_list ap;
2243 long pid;
2244 int cursig;
2245 const void *greg;
2246
2247 va_start (ap, note_type);
2248 memset (data, 0, sizeof (data));
2249 pid = va_arg (ap, long);
2250 bfd_put_32 (abfd, pid, data + 24);
2251 cursig = va_arg (ap, int);
2252 bfd_put_16 (abfd, cursig, data + 12);
2253 greg = va_arg (ap, const void *);
2254 memcpy (data + 72, greg, 72);
2255 va_end (ap);
2256
2257 return elfcore_write_note (abfd, buf, bufsiz,
2258 "CORE", note_type, data, sizeof (data));
2259 }
2260 }
2261}
2262
07d6d2b8
AM		 2263#define TARGET_LITTLE_SYM arm_elf32_le_vec
2264#define TARGET_LITTLE_NAME "elf32-littlearm"
2265#define TARGET_BIG_SYM arm_elf32_be_vec
2266#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2267
2268#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2270#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2271
252b5132
RH		 2272typedef unsigned long int insn32;
2273typedef unsigned short int insn16;
2274
3a4a14e9
PB		 2275/* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
57e8b36a 2277#define INTERWORK_FLAG(abfd) \
3a4a14e9 2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2281
252b5132
RH		 2282/* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
9b485d32 2285 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2286#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2287#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2288
2289#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2290#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2291
c7b8f16e
JB		 2292#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2293#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2294
a504d23a
LA		 2295#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2296#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2297
845b51d6
PB		 2298#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2299#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2300
7413f23f
DJ		 2301#define STUB_ENTRY_NAME "__%s_veneer"
2302
4ba2ef8f
TP		 2303#define CMSE_PREFIX "__acle_se_"
2304
4d83e8d9
CL		 2305#define CMSE_STUB_NAME ".gnu.sgstubs"
2306
252b5132
RH		 2307/* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2309#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2310
cb10292c
CL		 2311/* FDPIC default stack size. */
2312#define DEFAULT_STACK_SIZE 0x8000
2313
0855e32b 2314static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2315{
2316 0xe08e0000, /* add r0, lr, r0 */
2317 0xe5901004, /* ldr r1, [r0,#4] */
2318 0xe12fff11, /* bx r1 */
2319};
0855e32b
NS		 2320
2321static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2322{
2323 0xe52d2004, /* push {r2} */
2324 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2325 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2326 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2327 0xe081100f, /* 2: add r1, pc */
2328 0xe12fff12, /* bx r2 */
2329 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2330 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2331 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2332};
0855e32b 2333
b4e87f2c
TC		 2334/* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2338
7801f98f
CL		 2339/* ARM FDPIC PLT entry. */
2340/* The last 5 words contain PLT lazy fragment code and data. */
2341static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2342 {
2343 0xe59fc008, /* ldr r12, .L1 */
2344 0xe08cc009, /* add r12, r12, r9 */
2345 0xe59c9004, /* ldr r9, [r12, #4] */
2346 0xe59cf000, /* ldr pc, [r12] */
2347 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2348 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2349 0xe51fc00c, /* ldr r12, [pc, #-12] */
2350 0xe92d1000, /* push {r12} */
2351 0xe599c004, /* ldr r12, [r9, #4] */
2352 0xe599f000, /* ldr pc, [r9] */
2353 };
2354
59029f57
CL		 2355/* Thumb FDPIC PLT entry. */
2356/* The last 5 words contain PLT lazy fragment code and data. */
2357static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2358 {
2359 0xc00cf8df, /* ldr.w r12, .L1 */
2360 0x0c09eb0c, /* add.w r12, r12, r9 */
2361 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2362 0xf000f8dc, /* ldr.w pc, [r12] */
2363 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2364 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2365 0xc008f85f, /* ldr.w r12, .L2 */
2366 0xcd04f84d, /* push {r12} */
2367 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2368 0xf000f8d9, /* ldr.w pc, [r9] */
2369 };
2370
5e681ec4
PB		 2371#ifdef FOUR_WORD_PLT
2372
252b5132
RH		 2373/* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
59f2c4e7 2375 called before the relocation has been set up calls the dynamic
9b485d32 2376 linker first. */
e5a52504 2377static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2378{
2379 0xe52de004, /* str lr, [sp, #-4]! */
2380 0xe59fe010, /* ldr lr, [pc, #16] */
2381 0xe08fe00e, /* add lr, pc, lr */
2382 0xe5bef008, /* ldr pc, [lr, #8]! */
2383};
5e681ec4
PB		 2384
2385/* Subsequent entries in a procedure linkage table look like
2386 this. */
e5a52504 2387static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2388{
2389 0xe28fc600, /* add ip, pc, #NN */
2390 0xe28cca00, /* add ip, ip, #NN */
2391 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2392 0x00000000, /* unused */
2393};
5e681ec4 2394
eed94f8f 2395#else /* not FOUR_WORD_PLT */
5e681ec4 2396
5e681ec4
PB		 2397/* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
e5a52504 2401static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2402{
07d6d2b8
AM		 2403 0xe52de004, /* str lr, [sp, #-4]! */
2404 0xe59fe004, /* ldr lr, [pc, #4] */
2405 0xe08fe00e, /* add lr, pc, lr */
2406 0xe5bef008, /* ldr pc, [lr, #8]! */
2407 0x00000000, /* &GOT[0] - . */
b38cadfb 2408};
252b5132 2409
1db37fe6
YG		 2410/* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2412static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2413{
2414 0xe28fc600, /* add ip, pc, #0xNN00000 */
2415 0xe28cca00, /* add ip, ip, #0xNN000 */
2416 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2417};
5e681ec4 2418
1db37fe6
YG		 2419/* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2421static const bfd_vma elf32_arm_plt_entry_long [] =
2422{
07d6d2b8
AM		 2423 0xe28fc200, /* add ip, pc, #0xN0000000 */
2424 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2425 0xe28cca00, /* add ip, ip, #0xNN000 */
2426 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2427};
2428
2429static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2430
eed94f8f
NC		 2431#endif /* not FOUR_WORD_PLT */
2432
2433/* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2436static const bfd_vma elf32_thumb2_plt0_entry [] =
2437{
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2440 0xf8dfb500, /* push {lr} */
2441 0x44fee008, /* ldr.w lr, [pc, #8] */
2442 /* add lr, pc */
eed94f8f 2443 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2444 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2445};
2446
2447/* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2449static const bfd_vma elf32_thumb2_plt_entry [] =
2450{
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2453 0x0c00f240, /* movw ip, #0xNNNN */
2454 0x0c00f2c0, /* movt ip, #0xNNNN */
2455 0xf8dc44fc, /* add ip, pc */
15ccbdd7
TC		 2456 0xe7fcf000 /* ldr.w pc, [ip] */
2457 /* b .-4 */
eed94f8f 2458};
252b5132 2459
00a97672
RS		 2460/* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2462static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2463{
07d6d2b8
AM		 2464 0xe52dc008, /* str ip,[sp,#-8]! */
2465 0xe59fc000, /* ldr ip,[pc] */
2466 0xe59cf008, /* ldr pc,[ip,#8] */
2467 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2468};
00a97672
RS		 2469
2470/* The format of subsequent entries in a VxWorks executable. */
2471static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2472{
07d6d2b8
AM		 2473 0xe59fc000, /* ldr ip,[pc] */
2474 0xe59cf000, /* ldr pc,[ip] */
2475 0x00000000, /* .long @got */
2476 0xe59fc000, /* ldr ip,[pc] */
2477 0xea000000, /* b _PLT */
2478 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2479};
00a97672
RS		 2480
2481/* The format of entries in a VxWorks shared library. */
2482static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2483{
07d6d2b8
AM		 2484 0xe59fc000, /* ldr ip,[pc] */
2485 0xe79cf009, /* ldr pc,[ip,r9] */
2486 0x00000000, /* .long @got */
2487 0xe59fc000, /* ldr ip,[pc] */
2488 0xe599f008, /* ldr pc,[r9,#8] */
2489 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2490};
00a97672 2491
b7693d02
DJ		 2492/* An initial stub used if the PLT entry is referenced from Thumb code. */
2493#define PLT_THUMB_STUB_SIZE 4
2494static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2495{
2496 0x4778, /* bx pc */
b4e87f2c 2497 0xe7fd /* b .-2 */
b38cadfb 2498};
b7693d02 2499
e5a52504
MM		 2500/* The entries in a PLT when using a DLL-based target with multiple
2501 address spaces. */
906e58ca 2502static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2503{
07d6d2b8
AM		 2504 0xe51ff004, /* ldr pc, [pc, #-4] */
2505 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2506};
2507
2508/* The first entry in a procedure linkage table looks like
2509 this. It is set up so that any shared library function that is
2510 called before the relocation has been set up calls the dynamic
2511 linker first. */
2512static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2513{
2514 /* First bundle: */
2515 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2516 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2517 0xe08cc00f, /* add ip, ip, pc */
2518 0xe52dc008, /* str ip, [sp, #-8]! */
2519 /* Second bundle: */
edccdf7c
RM		 2520 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2521 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2522 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2523 0xe12fff1c, /* bx ip */
b38cadfb 2524 /* Third bundle: */
edccdf7c
RM		 2525 0xe320f000, /* nop */
2526 0xe320f000, /* nop */
2527 0xe320f000, /* nop */
b38cadfb
NC		 2528 /* .Lplt_tail: */
2529 0xe50dc004, /* str ip, [sp, #-4] */
2530 /* Fourth bundle: */
edccdf7c
RM		 2531 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2532 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2533 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2534 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2535};
2536#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2537
2538/* Subsequent entries in a procedure linkage table look like this. */
2539static const bfd_vma elf32_arm_nacl_plt_entry [] =
2540{
2541 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2542 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2543 0xe08cc00f, /* add ip, ip, pc */
2544 0xea000000, /* b .Lplt_tail */
2545};
e5a52504 2546
906e58ca
NC		 2547#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2548#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2549#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2550#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2551#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2552#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2553#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2554#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2555
461a49ca 2556enum stub_insn_type
b38cadfb
NC		 2557{
2558 THUMB16_TYPE = 1,
2559 THUMB32_TYPE,
2560 ARM_TYPE,
2561 DATA_TYPE
2562};
461a49ca 2563
48229727
JB		 2564#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2565/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2566 is inserted in arm_build_one_stub(). */
2567#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2568#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2569#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2570#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2571#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2572#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2573#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2574#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2575
2576typedef struct
2577{
07d6d2b8 2578 bfd_vma data;
b38cadfb 2579 enum stub_insn_type type;
07d6d2b8
AM		 2580 unsigned int r_type;
2581 int reloc_addend;
461a49ca
DJ		 2582} insn_sequence;
2583
b4e87f2c
TC		 2584/* See note [Thumb nop sequence] when adding a veneer. */
2585
fea2b4d6
CL		 2586/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2587 to reach the stub if necessary. */
461a49ca 2588static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2589{
07d6d2b8 2590 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2591 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2592};
906e58ca 2593
fea2b4d6
CL		 2594/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2595 available. */
461a49ca 2596static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2597{
07d6d2b8
AM		 2598 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2599 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2600 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2601};
906e58ca 2602
d3626fb0 2603/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2604static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2605{
07d6d2b8
AM		 2606 THUMB16_INSN (0xb401), /* push {r0} */
2607 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2608 THUMB16_INSN (0x4684), /* mov ip, r0 */
2609 THUMB16_INSN (0xbc01), /* pop {r0} */
2610 THUMB16_INSN (0x4760), /* bx ip */
2611 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2612 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2613};
906e58ca 2614
80c135e5
TP		 2615/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2616static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2617{
07d6d2b8 2618 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2619 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2620};
2621
d5a67c02
AV		 2622/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2623 M-profile architectures. */
2624static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2625{
2626 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2627 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2628 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2629};
2630
d3626fb0
CL		 2631/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2632 allowed. */
2633static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2634{
07d6d2b8 2635 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2636 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2637 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2638 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2639 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2640};
d3626fb0 2641
fea2b4d6
CL		 2642/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2643 available. */
461a49ca 2644static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2645{
07d6d2b8 2646 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2647 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8 2648 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2649 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2650};
906e58ca 2651
fea2b4d6
CL		 2652/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2653 one, when the destination is close enough. */
461a49ca 2654static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2655{
07d6d2b8 2656 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2657 THUMB16_INSN (0xe7fd), /* b .-2 */
b38cadfb
NC		 2658 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2659};
c820be07 2660
cf3eccff 2661/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2662 blx to reach the stub if necessary. */
cf3eccff 2663static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2664{
07d6d2b8
AM		 2665 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2666 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2667 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2668};
906e58ca 2669
cf3eccff
DJ		 2670/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2671 blx to reach the stub if necessary. We can not add into pc;
2672 it is not guaranteed to mode switch (different in ARMv6 and
2673 ARMv7). */
2674static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2675{
07d6d2b8
AM		 2676 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2677 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2678 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2679 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2680};
cf3eccff 2681
ebe24dd4
CL		 2682/* V4T ARM -> ARM long branch stub, PIC. */
2683static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2684{
07d6d2b8
AM		 2685 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2686 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2687 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2688 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2689};
ebe24dd4
CL		 2690
2691/* V4T Thumb -> ARM long branch stub, PIC. */
2692static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2693{
07d6d2b8 2694 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2695 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2696 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2697 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2698 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2699};
ebe24dd4 2700
d3626fb0
CL		 2701/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2702 architectures. */
ebe24dd4 2703static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2704{
07d6d2b8
AM		 2705 THUMB16_INSN (0xb401), /* push {r0} */
2706 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2707 THUMB16_INSN (0x46fc), /* mov ip, pc */
2708 THUMB16_INSN (0x4484), /* add ip, r0 */
2709 THUMB16_INSN (0xbc01), /* pop {r0} */
2710 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2711 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2712};
ebe24dd4 2713
d3626fb0
CL		 2714/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2715 allowed. */
2716static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2717{
07d6d2b8 2718 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2719 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2720 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2721 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2722 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2723 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2724};
d3626fb0 2725
0855e32b
NS		 2726/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2727 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2728static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2729{
07d6d2b8
AM		 2730 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2731 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2732 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2733};
2734
2735/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2736 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2737static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2738{
07d6d2b8 2739 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2740 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2741 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2742 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2743 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2744};
2745
7a89b94e
NC		 2746/* NaCl ARM -> ARM long branch stub. */
2747static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2748{
2749 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2750 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2751 ARM_INSN (0xe12fff1c), /* bx ip */
2752 ARM_INSN (0xe320f000), /* nop */
2753 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2754 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2755 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2756 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2757};
2758
2759/* NaCl ARM -> ARM long branch stub, PIC. */
2760static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2761{
2762 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2763 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2764 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2765 ARM_INSN (0xe12fff1c), /* bx ip */
2766 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2767 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2768 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2769 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2770};
2771
4ba2ef8f
TP		 2772/* Stub used for transition to secure state (aka SG veneer). */
2773static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2774{
2775 THUMB32_INSN (0xe97fe97f), /* sg. */
2776 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2777};
2778
7a89b94e 2779
48229727
JB		 2780/* Cortex-A8 erratum-workaround stubs. */
2781
2782/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2783 can't use a conditional branch to reach this stub). */
2784
2785static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2786{
07d6d2b8 2787 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2788 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2789 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2790};
48229727
JB		 2791
2792/* Stub used for b.w and bl.w instructions. */
2793
2794static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2795{
2796 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2797};
48229727
JB		 2798
2799static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2800{
2801 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2802};
48229727
JB		 2803
2804/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2805 instruction (which switches to ARM mode) to point to this stub. Jump to the
2806 real destination using an ARM-mode branch. */
2807
2808static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2809{
2810 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2811};
48229727 2812
9553db3c
NC		 2813/* For each section group there can be a specially created linker section
2814 to hold the stubs for that group. The name of the stub section is based
2815 upon the name of another section within that group with the suffix below
2816 applied.
2817
2818 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2819 create what appeared to be a linker stub section when it actually
2820 contained user code/data. For example, consider this fragment:
b38cadfb 2821
9553db3c
NC		 2822 const char * stubborn_problems[] = { "np" };
2823
2824 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2825 section called:
2826
2827 .data.rel.local.stubborn_problems
2828
2829 This then causes problems in arm32_arm_build_stubs() as it triggers:
2830
2831 // Ignore non-stub sections.
2832 if (!strstr (stub_sec->name, STUB_SUFFIX))
2833 continue;
2834
2835 And so the section would be ignored instead of being processed. Hence
2836 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2837 C identifier. */
2838#define STUB_SUFFIX ".__stub"
906e58ca 2839
738a79f6
CL		 2840/* One entry per long/short branch stub defined above. */
2841#define DEF_STUBS \
2842 DEF_STUB(long_branch_any_any) \
2843 DEF_STUB(long_branch_v4t_arm_thumb) \
2844 DEF_STUB(long_branch_thumb_only) \
2845 DEF_STUB(long_branch_v4t_thumb_thumb) \
2846 DEF_STUB(long_branch_v4t_thumb_arm) \
2847 DEF_STUB(short_branch_v4t_thumb_arm) \
2848 DEF_STUB(long_branch_any_arm_pic) \
2849 DEF_STUB(long_branch_any_thumb_pic) \
2850 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2851 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2852 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2853 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2854 DEF_STUB(long_branch_any_tls_pic) \
2855 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2856 DEF_STUB(long_branch_arm_nacl) \
2857 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2858 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2859 DEF_STUB(a8_veneer_b_cond) \
2860 DEF_STUB(a8_veneer_b) \
2861 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2862 DEF_STUB(a8_veneer_blx) \
2863 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2864 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2865
2866#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2867enum elf32_arm_stub_type
2868{
906e58ca 2869 arm_stub_none,
738a79f6 2870 DEF_STUBS
4f4faa4d 2871 max_stub_type
738a79f6
CL		 2872};
2873#undef DEF_STUB
2874
8d9d9490
TP		 2875/* Note the first a8_veneer type. */
2876const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2877
738a79f6
CL		 2878typedef struct
2879{
d3ce72d0 2880 const insn_sequence* template_sequence;
738a79f6
CL		 2881 int template_size;
2882} stub_def;
2883
2884#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2885static const stub_def stub_definitions[] =
2886{
738a79f6
CL		 2887 {NULL, 0},
2888 DEF_STUBS
906e58ca
NC		 2889};
2890
2891struct elf32_arm_stub_hash_entry
2892{
2893 /* Base hash table entry structure. */
2894 struct bfd_hash_entry root;
2895
2896 /* The stub section. */
2897 asection *stub_sec;
2898
2899 /* Offset within stub_sec of the beginning of this stub. */
2900 bfd_vma stub_offset;
2901
2902 /* Given the symbol's value and its section we can determine its final
2903 value when building the stubs (so the stub knows where to jump). */
2904 bfd_vma target_value;
2905 asection *target_section;
2906
8d9d9490
TP		 2907 /* Same as above but for the source of the branch to the stub. Used for
2908 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2909 such, source section does not need to be recorded since Cortex-A8 erratum
2910 workaround stubs are only generated when both source and target are in the
2911 same section. */
2912 bfd_vma source_value;
48229727
JB		 2913
2914 /* The instruction which caused this stub to be generated (only valid for
2915 Cortex-A8 erratum workaround stubs at present). */
2916 unsigned long orig_insn;
2917
461a49ca 2918 /* The stub type. */
906e58ca 2919 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2920 /* Its encoding size in bytes. */
2921 int stub_size;
2922 /* Its template. */
2923 const insn_sequence *stub_template;
2924 /* The size of the template (number of entries). */
2925 int stub_template_size;
906e58ca
NC		 2926
2927 /* The symbol table entry, if any, that this was derived from. */
2928 struct elf32_arm_link_hash_entry *h;
2929
35fc36a8
RS		 2930 /* Type of branch. */
2931 enum arm_st_branch_type branch_type;
906e58ca
NC		 2932
2933 /* Where this stub is being called from, or, in the case of combined
2934 stub sections, the first input section in the group. */
2935 asection *id_sec;
7413f23f
DJ		 2936
2937 /* The name for the local symbol at the start of this stub. The
2938 stub name in the hash table has to be unique; this does not, so
2939 it can be friendlier. */
2940 char *output_name;
906e58ca
NC		 2941};
2942
e489d0ae
PB		 2943/* Used to build a map of a section. This is required for mixed-endian
2944 code/data. */
2945
2946typedef struct elf32_elf_section_map
2947{
2948 bfd_vma vma;
2949 char type;
2950}
2951elf32_arm_section_map;
2952
c7b8f16e
JB		 2953/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2954
2955typedef enum
2956{
2957 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2958 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2959 VFP11_ERRATUM_ARM_VENEER,
2960 VFP11_ERRATUM_THUMB_VENEER
2961}
2962elf32_vfp11_erratum_type;
2963
2964typedef struct elf32_vfp11_erratum_list
2965{
2966 struct elf32_vfp11_erratum_list *next;
2967 bfd_vma vma;
2968 union
2969 {
2970 struct
2971 {
2972 struct elf32_vfp11_erratum_list *veneer;
2973 unsigned int vfp_insn;
2974 } b;
2975 struct
2976 {
2977 struct elf32_vfp11_erratum_list *branch;
2978 unsigned int id;
2979 } v;
2980 } u;
2981 elf32_vfp11_erratum_type type;
2982}
2983elf32_vfp11_erratum_list;
2984
a504d23a
LA		 2985/* Information about a STM32L4XX erratum veneer, or a branch to such a
2986 veneer. */
2987typedef enum
2988{
2989 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2990 STM32L4XX_ERRATUM_VENEER
2991}
2992elf32_stm32l4xx_erratum_type;
2993
2994typedef struct elf32_stm32l4xx_erratum_list
2995{
2996 struct elf32_stm32l4xx_erratum_list *next;
2997 bfd_vma vma;
2998 union
2999 {
3000 struct
3001 {
3002 struct elf32_stm32l4xx_erratum_list *veneer;
3003 unsigned int insn;
3004 } b;
3005 struct
3006 {
3007 struct elf32_stm32l4xx_erratum_list *branch;
3008 unsigned int id;
3009 } v;
3010 } u;
3011 elf32_stm32l4xx_erratum_type type;
3012}
3013elf32_stm32l4xx_erratum_list;
3014
2468f9c9
PB		 3015typedef enum
3016{
3017 DELETE_EXIDX_ENTRY,
3018 INSERT_EXIDX_CANTUNWIND_AT_END
3019}
3020arm_unwind_edit_type;
3021
3022/* A (sorted) list of edits to apply to an unwind table. */
3023typedef struct arm_unwind_table_edit
3024{
3025 arm_unwind_edit_type type;
3026 /* Note: we sometimes want to insert an unwind entry corresponding to a
3027 section different from the one we're currently writing out, so record the
3028 (text) section this edit relates to here. */
3029 asection *linked_section;
3030 unsigned int index;
3031 struct arm_unwind_table_edit *next;
3032}
3033arm_unwind_table_edit;
3034
8e3de13a 3035typedef struct _arm_elf_section_data
e489d0ae 3036{
2468f9c9 3037 /* Information about mapping symbols. */
e489d0ae 3038 struct bfd_elf_section_data elf;
8e3de13a 3039 unsigned int mapcount;
c7b8f16e 3040 unsigned int mapsize;
e489d0ae 3041 elf32_arm_section_map *map;
2468f9c9 3042 /* Information about CPU errata. */
c7b8f16e
JB		 3043 unsigned int erratumcount;
3044 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 3045 unsigned int stm32l4xx_erratumcount;
3046 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 3047 unsigned int additional_reloc_count;
2468f9c9
PB		 3048 /* Information about unwind tables. */
3049 union
3050 {
3051 /* Unwind info attached to a text section. */
3052 struct
3053 {
3054 asection *arm_exidx_sec;
3055 } text;
3056
3057 /* Unwind info attached to an .ARM.exidx section. */
3058 struct
3059 {
3060 arm_unwind_table_edit *unwind_edit_list;
3061 arm_unwind_table_edit *unwind_edit_tail;
3062 } exidx;
3063 } u;
8e3de13a
NC		 3064}
3065_arm_elf_section_data;
e489d0ae
PB		 3066
3067#define elf32_arm_section_data(sec) \
8e3de13a 3068 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3069
48229727
JB		 3070/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3071 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3072 so may be created multiple times: we use an array of these entries whilst
3073 relaxing which we can refresh easily, then create stubs for each potentially
3074 erratum-triggering instruction once we've settled on a solution. */
3075
b38cadfb
NC		 3076struct a8_erratum_fix
3077{
48229727
JB		 3078 bfd *input_bfd;
3079 asection *section;
3080 bfd_vma offset;
8d9d9490 3081 bfd_vma target_offset;
48229727
JB		 3082 unsigned long orig_insn;
3083 char *stub_name;
3084 enum elf32_arm_stub_type stub_type;
35fc36a8 3085 enum arm_st_branch_type branch_type;
48229727
JB		 3086};
3087
3088/* A table of relocs applied to branches which might trigger Cortex-A8
3089 erratum. */
3090
b38cadfb
NC		 3091struct a8_erratum_reloc
3092{
48229727
JB		 3093 bfd_vma from;
3094 bfd_vma destination;
92750f34
DJ		 3095 struct elf32_arm_link_hash_entry *hash;
3096 const char *sym_name;
48229727 3097 unsigned int r_type;
35fc36a8 3098 enum arm_st_branch_type branch_type;
48229727
JB		 3099 bfd_boolean non_a8_stub;
3100};
3101
ba93b8ac
DJ		 3102/* The size of the thread control block. */
3103#define TCB_SIZE 8
3104
34e77a92
RS		 3105/* ARM-specific information about a PLT entry, over and above the usual
3106 gotplt_union. */
b38cadfb
NC		 3107struct arm_plt_info
3108{
34e77a92
RS		 3109 /* We reference count Thumb references to a PLT entry separately,
3110 so that we can emit the Thumb trampoline only if needed. */
3111 bfd_signed_vma thumb_refcount;
3112
3113 /* Some references from Thumb code may be eliminated by BL->BLX
3114 conversion, so record them separately. */
3115 bfd_signed_vma maybe_thumb_refcount;
3116
3117 /* How many of the recorded PLT accesses were from non-call relocations.
3118 This information is useful when deciding whether anything takes the
3119 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3120 non-call references to the function should resolve directly to the
3121 real runtime target. */
3122 unsigned int noncall_refcount;
3123
3124 /* Since PLT entries have variable size if the Thumb prologue is
3125 used, we need to record the index into .got.plt instead of
3126 recomputing it from the PLT offset. */
3127 bfd_signed_vma got_offset;
3128};
3129
3130/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3131struct arm_local_iplt_info
3132{
34e77a92
RS		 3133 /* The information that is usually found in the generic ELF part of
3134 the hash table entry. */
3135 union gotplt_union root;
3136
3137 /* The information that is usually found in the ARM-specific part of
3138 the hash table entry. */
3139 struct arm_plt_info arm;
3140
3141 /* A list of all potential dynamic relocations against this symbol. */
3142 struct elf_dyn_relocs *dyn_relocs;
3143};
3144
e8b09b87
CL		 3145/* Structure to handle FDPIC support for local functions. */
3146struct fdpic_local {
3147 unsigned int funcdesc_cnt;
3148 unsigned int gotofffuncdesc_cnt;
3149 int funcdesc_offset;
3150};
3151
0ffa91dd 3152struct elf_arm_obj_tdata
ba93b8ac
DJ		 3153{
3154 struct elf_obj_tdata root;
3155
3156 /* tls_type for each local got entry. */
3157 char *local_got_tls_type;
ee065d83 3158
0855e32b
NS		 3159 /* GOTPLT entries for TLS descriptors. */
3160 bfd_vma *local_tlsdesc_gotent;
3161
34e77a92
RS		 3162 /* Information for local symbols that need entries in .iplt. */
3163 struct arm_local_iplt_info **local_iplt;
3164
bf21ed78
MS		 3165 /* Zero to warn when linking objects with incompatible enum sizes. */
3166 int no_enum_size_warning;
a9dc9481
JM		 3167
3168 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3169 int no_wchar_size_warning;
e8b09b87
CL		 3170
3171 /* Maintains FDPIC counters and funcdesc info. */
3172 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3173};
3174
0ffa91dd
NC		 3175#define elf_arm_tdata(bfd) \
3176 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3177
0ffa91dd
NC		 3178#define elf32_arm_local_got_tls_type(bfd) \
3179 (elf_arm_tdata (bfd)->local_got_tls_type)
3180
0855e32b
NS		 3181#define elf32_arm_local_tlsdesc_gotent(bfd) \
3182 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3183
34e77a92
RS		 3184#define elf32_arm_local_iplt(bfd) \
3185 (elf_arm_tdata (bfd)->local_iplt)
3186
e8b09b87
CL		 3187#define elf32_arm_local_fdpic_cnts(bfd) \
3188 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3189
0ffa91dd
NC		 3190#define is_arm_elf(bfd) \
3191 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3192 && elf_tdata (bfd) != NULL \
4dfe6ac6 3193 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3194
3195static bfd_boolean
3196elf32_arm_mkobject (bfd *abfd)
3197{
0ffa91dd 3198 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3199 ARM_ELF_DATA);
ba93b8ac
DJ		 3200}
3201
ba93b8ac
DJ		 3202#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3203
e8b09b87
CL		 3204/* Structure to handle FDPIC support for extern functions. */
3205struct fdpic_global {
3206 unsigned int gotofffuncdesc_cnt;
3207 unsigned int gotfuncdesc_cnt;
3208 unsigned int funcdesc_cnt;
3209 int funcdesc_offset;
3210 int gotfuncdesc_offset;
3211};
3212
ba96a88f 3213/* Arm ELF linker hash entry. */
252b5132 3214struct elf32_arm_link_hash_entry
b38cadfb
NC		 3215{
3216 struct elf_link_hash_entry root;
252b5132 3217
b38cadfb
NC		 3218 /* ARM-specific PLT information. */
3219 struct arm_plt_info plt;
ba93b8ac
DJ		 3220
3221#define GOT_UNKNOWN 0
3222#define GOT_NORMAL 1
3223#define GOT_TLS_GD 2
3224#define GOT_TLS_IE 4
0855e32b
NS		 3225#define GOT_TLS_GDESC 8
3226#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3227 unsigned int tls_type : 8;
34e77a92 3228
b38cadfb
NC		 3229 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3230 unsigned int is_iplt : 1;
34e77a92 3231
b38cadfb 3232 unsigned int unused : 23;
a4fd1a8e 3233
b38cadfb
NC		 3234 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3235 starting at the end of the jump table. */
3236 bfd_vma tlsdesc_got;
0855e32b 3237
b38cadfb
NC		 3238 /* The symbol marking the real symbol location for exported thumb
3239 symbols with Arm stubs. */
3240 struct elf_link_hash_entry *export_glue;
906e58ca 3241
b38cadfb 3242 /* A pointer to the most recently used stub hash entry against this
8029a119 3243 symbol. */
b38cadfb 3244 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3245
3246 /* Counter for FDPIC relocations against this symbol. */
3247 struct fdpic_global fdpic_cnts;
b38cadfb 3248};
252b5132 3249
252b5132 3250/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3251#define elf32_arm_link_hash_traverse(table, func, info) \
3252 (elf_link_hash_traverse \
3253 (&(table)->root, \
b7693d02 3254 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3255 (info)))
3256
3257/* Get the ARM elf linker hash table from a link_info structure. */
0f55320b
AM		 3258#define elf32_arm_hash_table(p) \
3259 ((is_elf_hash_table ((p)->hash) \
3260 && elf_hash_table_id (elf_hash_table (p)) == ARM_ELF_DATA) \
3261 ? (struct elf32_arm_link_hash_table *) (p)->hash : NULL)
252b5132 3262
906e58ca
NC		 3263#define arm_stub_hash_lookup(table, string, create, copy) \
3264 ((struct elf32_arm_stub_hash_entry *) \
3265 bfd_hash_lookup ((table), (string), (create), (copy)))
3266
21d799b5
NC		 3267/* Array to keep track of which stub sections have been created, and
3268 information on stub grouping. */
3269struct map_stub
3270{
3271 /* This is the section to which stubs in the group will be
3272 attached. */
3273 asection *link_sec;
3274 /* The stub section. */
3275 asection *stub_sec;
3276};
3277
0855e32b
NS		 3278#define elf32_arm_compute_jump_table_size(htab) \
3279 ((htab)->next_tls_desc_index * 4)
3280
9b485d32 3281/* ARM ELF linker hash table. */
252b5132 3282struct elf32_arm_link_hash_table
906e58ca
NC		 3283{
3284 /* The main hash table. */
3285 struct elf_link_hash_table root;
252b5132 3286
906e58ca
NC		 3287 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3288 bfd_size_type thumb_glue_size;
252b5132 3289
906e58ca
NC		 3290 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3291 bfd_size_type arm_glue_size;
252b5132 3292
906e58ca
NC		 3293 /* The size in bytes of section containing the ARMv4 BX veneers. */
3294 bfd_size_type bx_glue_size;
845b51d6 3295
906e58ca
NC		 3296 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3297 veneer has been populated. */
3298 bfd_vma bx_glue_offset[15];
845b51d6 3299
906e58ca
NC		 3300 /* The size in bytes of the section containing glue for VFP11 erratum
3301 veneers. */
3302 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3303
a504d23a
LA		 3304 /* The size in bytes of the section containing glue for STM32L4XX erratum
3305 veneers. */
3306 bfd_size_type stm32l4xx_erratum_glue_size;
3307
48229727
JB		 3308 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3309 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3310 elf32_arm_write_section(). */
3311 struct a8_erratum_fix *a8_erratum_fixes;
3312 unsigned int num_a8_erratum_fixes;
3313
906e58ca
NC		 3314 /* An arbitrary input BFD chosen to hold the glue sections. */
3315 bfd * bfd_of_glue_owner;
ba96a88f 3316
906e58ca
NC		 3317 /* Nonzero to output a BE8 image. */
3318 int byteswap_code;
e489d0ae 3319
906e58ca
NC		 3320 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3321 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3322 int target1_is_rel;
9c504268 3323
906e58ca
NC		 3324 /* The relocation to use for R_ARM_TARGET2 relocations. */
3325 int target2_reloc;
eb043451 3326
906e58ca
NC		 3327 /* 0 = Ignore R_ARM_V4BX.
3328 1 = Convert BX to MOV PC.
3329 2 = Generate v4 interworing stubs. */
3330 int fix_v4bx;
319850b4 3331
48229727
JB		 3332 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3333 int fix_cortex_a8;
3334
2de70689
MGD		 3335 /* Whether we should fix the ARM1176 BLX immediate issue. */
3336 int fix_arm1176;
3337
906e58ca
NC		 3338 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3339 int use_blx;
33bfe774 3340
906e58ca
NC		 3341 /* What sort of code sequences we should look for which may trigger the
3342 VFP11 denorm erratum. */
3343 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3344
906e58ca
NC		 3345 /* Global counter for the number of fixes we have emitted. */
3346 int num_vfp11_fixes;
c7b8f16e 3347
a504d23a
LA		 3348 /* What sort of code sequences we should look for which may trigger the
3349 STM32L4XX erratum. */
3350 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3351
3352 /* Global counter for the number of fixes we have emitted. */
3353 int num_stm32l4xx_fixes;
3354
906e58ca
NC		 3355 /* Nonzero to force PIC branch veneers. */
3356 int pic_veneer;
27e55c4d 3357
906e58ca
NC		 3358 /* The number of bytes in the initial entry in the PLT. */
3359 bfd_size_type plt_header_size;
e5a52504 3360
906e58ca
NC		 3361 /* The number of bytes in the subsequent PLT etries. */
3362 bfd_size_type plt_entry_size;
e5a52504 3363
906e58ca 3364 /* True if the target uses REL relocations. */
f3185997 3365 bfd_boolean use_rel;
4e7fd91e 3366
54ddd295
TP		 3367 /* Nonzero if import library must be a secure gateway import library
3368 as per ARMv8-M Security Extensions. */
3369 int cmse_implib;
3370
0955507f
TP		 3371 /* The import library whose symbols' address must remain stable in
3372 the import library generated. */
3373 bfd *in_implib_bfd;
3374
0855e32b
NS		 3375 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3376 bfd_vma next_tls_desc_index;
3377
3378 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3379 bfd_vma num_tls_desc;
3380
906e58ca
NC		 3381 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3382 asection *srelplt2;
00a97672 3383
0855e32b
NS		 3384 /* Offset in .plt section of tls_arm_trampoline. */
3385 bfd_vma tls_trampoline;
3386
5c5a4843 3387 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3388 union
3389 {
3390 bfd_signed_vma refcount;
3391 bfd_vma offset;
3392 } tls_ldm_got;
b7693d02 3393
906e58ca
NC		 3394 /* For convenience in allocate_dynrelocs. */
3395 bfd * obfd;
3396
0855e32b
NS		 3397 /* The amount of space used by the reserved portion of the sgotplt
3398 section, plus whatever space is used by the jump slots. */
3399 bfd_vma sgotplt_jump_table_size;
3400
906e58ca
NC		 3401 /* The stub hash table. */
3402 struct bfd_hash_table stub_hash_table;
3403
3404 /* Linker stub bfd. */
3405 bfd *stub_bfd;
3406
3407 /* Linker call-backs. */
6bde4c52
TP		 3408 asection * (*add_stub_section) (const char *, asection *, asection *,
3409 unsigned int);
906e58ca
NC		 3410 void (*layout_sections_again) (void);
3411
3412 /* Array to keep track of which stub sections have been created, and
3413 information on stub grouping. */
21d799b5 3414 struct map_stub *stub_group;
906e58ca 3415
4ba2ef8f
TP		 3416 /* Input stub section holding secure gateway veneers. */
3417 asection *cmse_stub_sec;
3418
0955507f
TP		 3419 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3420 start to be allocated. */
3421 bfd_vma new_cmse_stub_offset;
3422
fe33d2fa 3423 /* Number of elements in stub_group. */
7292b3ac 3424 unsigned int top_id;
fe33d2fa 3425
906e58ca
NC		 3426 /* Assorted information used by elf32_arm_size_stubs. */
3427 unsigned int bfd_count;
7292b3ac 3428 unsigned int top_index;
906e58ca 3429 asection **input_list;
617a5ada
CL		 3430
3431 /* True if the target system uses FDPIC. */
3432 int fdpic_p;
e8b09b87
CL		 3433
3434 /* Fixup section. Used for FDPIC. */
3435 asection *srofixup;
906e58ca 3436};
252b5132 3437
e8b09b87
CL		 3438/* Add an FDPIC read-only fixup. */
3439static void
3440arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3441{
3442 bfd_vma fixup_offset;
3443
3444 fixup_offset = srofixup->reloc_count++ * 4;
3445 BFD_ASSERT (fixup_offset < srofixup->size);
3446 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3447}
3448
a504d23a
LA		 3449static inline int
3450ctz (unsigned int mask)
3451{
3452#if GCC_VERSION >= 3004
3453 return __builtin_ctz (mask);
3454#else
3455 unsigned int i;
3456
3457 for (i = 0; i < 8 * sizeof (mask); i++)
3458 {
3459 if (mask & 0x1)
3460 break;
3461 mask = (mask >> 1);
3462 }
3463 return i;
3464#endif
3465}
3466
3467static inline int
b25e998d 3468elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3469{
3470#if GCC_VERSION >= 3004
3471 return __builtin_popcount (mask);
3472#else
b25e998d
CG		 3473 unsigned int i;
3474 int sum = 0;
a504d23a
LA		 3475
3476 for (i = 0; i < 8 * sizeof (mask); i++)
3477 {
3478 if (mask & 0x1)
3479 sum++;
3480 mask = (mask >> 1);
3481 }
3482 return sum;
3483#endif
3484}
3485
e8b09b87
CL		 3486static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3487 asection *sreloc, Elf_Internal_Rela *rel);
3488
3489static void
3490arm_elf_fill_funcdesc(bfd *output_bfd,
3491 struct bfd_link_info *info,
3492 int *funcdesc_offset,
3493 int dynindx,
3494 int offset,
3495 bfd_vma addr,
3496 bfd_vma dynreloc_value,
3497 bfd_vma seg)
3498{
3499 if ((*funcdesc_offset & 1) == 0)
3500 {
3501 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3502 asection *sgot = globals->root.sgot;
3503
3504 if (bfd_link_pic(info))
3505 {
3506 asection *srelgot = globals->root.srelgot;
3507 Elf_Internal_Rela outrel;
3508
3509 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3510 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3511 outrel.r_addend = 0;
3512
3513 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3514 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3515 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3516 }
3517 else
3518 {
3519 struct elf_link_hash_entry *hgot = globals->root.hgot;
3520 bfd_vma got_value = hgot->root.u.def.value
3521 + hgot->root.u.def.section->output_section->vma
3522 + hgot->root.u.def.section->output_offset;
3523
3524 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3525 sgot->output_section->vma + sgot->output_offset
3526 + offset);
3527 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3528 sgot->output_section->vma + sgot->output_offset
3529 + offset + 4);
3530 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3531 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3532 }
3533 *funcdesc_offset |= 1;
3534 }
3535}
3536
780a67af
NC		 3537/* Create an entry in an ARM ELF linker hash table. */
3538
3539static struct bfd_hash_entry *
57e8b36a 3540elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3541 struct bfd_hash_table * table,
3542 const char * string)
780a67af
NC		 3543{
3544 struct elf32_arm_link_hash_entry * ret =
3545 (struct elf32_arm_link_hash_entry *) entry;
3546
3547 /* Allocate the structure if it has not already been allocated by a
3548 subclass. */
906e58ca 3549 if (ret == NULL)
21d799b5 3550 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3551 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3552 if (ret == NULL)
780a67af
NC		 3553 return (struct bfd_hash_entry *) ret;
3554
3555 /* Call the allocation method of the superclass. */
3556 ret = ((struct elf32_arm_link_hash_entry *)
3557 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3558 table, string));
57e8b36a 3559 if (ret != NULL)
b7693d02 3560 {
ba93b8ac 3561 ret->tls_type = GOT_UNKNOWN;
0855e32b 3562 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3563 ret->plt.thumb_refcount = 0;
3564 ret->plt.maybe_thumb_refcount = 0;
3565 ret->plt.noncall_refcount = 0;
3566 ret->plt.got_offset = -1;
3567 ret->is_iplt = FALSE;
a4fd1a8e 3568 ret->export_glue = NULL;
906e58ca
NC		 3569
3570 ret->stub_cache = NULL;
e8b09b87
CL		 3571
3572 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3573 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3574 ret->fdpic_cnts.funcdesc_cnt = 0;
3575 ret->fdpic_cnts.funcdesc_offset = -1;
3576 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3577 }
780a67af
NC		 3578
3579 return (struct bfd_hash_entry *) ret;
3580}
3581
34e77a92
RS		 3582/* Ensure that we have allocated bookkeeping structures for ABFD's local
3583 symbols. */
3584
3585static bfd_boolean
3586elf32_arm_allocate_local_sym_info (bfd *abfd)
3587{
3588 if (elf_local_got_refcounts (abfd) == NULL)
3589 {
3590 bfd_size_type num_syms;
3591 bfd_size_type size;
3592 char *data;
3593
3594 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3595 size = num_syms * (sizeof (bfd_signed_vma)
34e77a92 3596 + sizeof (bfd_vma)
f911bb22
AM		 3597 + sizeof (struct arm_local_iplt_info *)
3598 + sizeof (struct fdpic_local)
3599 + sizeof (char));
34e77a92
RS		 3600 data = bfd_zalloc (abfd, size);
3601 if (data == NULL)
3602 return FALSE;
3603
f911bb22
AM		 3604 /* It is important that these all be allocated in descending
3605 order of required alignment, so that arrays allocated later
3606 will be sufficiently aligned. */
34e77a92
RS		 3607 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3608 data += num_syms * sizeof (bfd_signed_vma);
3609
f911bb22
AM		 3610 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3611 data += num_syms * sizeof (bfd_vma);
3612
34e77a92
RS		 3613 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3614 data += num_syms * sizeof (struct arm_local_iplt_info *);
3615
f911bb22
AM		 3616 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3617 data += num_syms * sizeof (struct fdpic_local);
34e77a92
RS		 3618
3619 elf32_arm_local_got_tls_type (abfd) = data;
f911bb22
AM		 3620#if GCC_VERSION >= 3000
3621 BFD_ASSERT (__alignof__ (*elf32_arm_local_tlsdesc_gotent (abfd))
3622 <= __alignof__ (*elf_local_got_refcounts (abfd)));
3623 BFD_ASSERT (__alignof__ (*elf32_arm_local_iplt (abfd))
3624 <= __alignof__ (*elf32_arm_local_tlsdesc_gotent (abfd)));
3625 BFD_ASSERT (__alignof__ (*elf32_arm_local_fdpic_cnts (abfd))
3626 <= __alignof__ (*elf32_arm_local_iplt (abfd)));
3627 BFD_ASSERT (__alignof__ (*elf32_arm_local_got_tls_type (abfd))
3628 <= __alignof__ (*elf32_arm_local_fdpic_cnts (abfd)));
3629#endif
34e77a92
RS		 3630 }
3631 return TRUE;
3632}
3633
3634/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3635 to input bfd ABFD. Create the information if it doesn't already exist.
3636 Return null if an allocation fails. */
3637
3638static struct arm_local_iplt_info *
3639elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3640{
3641 struct arm_local_iplt_info **ptr;
3642
3643 if (!elf32_arm_allocate_local_sym_info (abfd))
3644 return NULL;
3645
3646 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3647 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3648 if (*ptr == NULL)
3649 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3650 return *ptr;
3651}
3652
3653/* Try to obtain PLT information for the symbol with index R_SYMNDX
3654 in ABFD's symbol table. If the symbol is global, H points to its
3655 hash table entry, otherwise H is null.
3656
3657 Return true if the symbol does have PLT information. When returning
3658 true, point *ROOT_PLT at the target-independent reference count/offset
3659 union and *ARM_PLT at the ARM-specific information. */
3660
3661static bfd_boolean
4ba2ef8f
TP		 3662elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3663 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3664 unsigned long r_symndx, union gotplt_union **root_plt,
3665 struct arm_plt_info **arm_plt)
3666{
3667 struct arm_local_iplt_info *local_iplt;
3668
4ba2ef8f
TP		 3669 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3670 return FALSE;
3671
34e77a92
RS		 3672 if (h != NULL)
3673 {
3674 *root_plt = &h->root.plt;
3675 *arm_plt = &h->plt;
3676 return TRUE;
3677 }
3678
3679 if (elf32_arm_local_iplt (abfd) == NULL)
3680 return FALSE;
3681
3682 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3683 if (local_iplt == NULL)
3684 return FALSE;
3685
3686 *root_plt = &local_iplt->root;
3687 *arm_plt = &local_iplt->arm;
3688 return TRUE;
3689}
3690
59029f57
CL		 3691static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3692
34e77a92
RS		 3693/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3694 before it. */
3695
3696static bfd_boolean
3697elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3698 struct arm_plt_info *arm_plt)
3699{
3700 struct elf32_arm_link_hash_table *htab;
3701
3702 htab = elf32_arm_hash_table (info);
59029f57
CL		 3703
3704 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3705 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3706}
3707
3708/* Return a pointer to the head of the dynamic reloc list that should
3709 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3710 ABFD's symbol table. Return null if an error occurs. */
3711
3712static struct elf_dyn_relocs **
3713elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3714 Elf_Internal_Sym *isym)
3715{
3716 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3717 {
3718 struct arm_local_iplt_info *local_iplt;
3719
3720 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3721 if (local_iplt == NULL)
3722 return NULL;
3723 return &local_iplt->dyn_relocs;
3724 }
3725 else
3726 {
3727 /* Track dynamic relocs needed for local syms too.
3728 We really need local syms available to do this
3729 easily. Oh well. */
3730 asection *s;
3731 void *vpp;
3732
3733 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3734 if (s == NULL)
3735 abort ();
3736
3737 vpp = &elf_section_data (s)->local_dynrel;
3738 return (struct elf_dyn_relocs **) vpp;
3739 }
3740}
3741
906e58ca
NC		 3742/* Initialize an entry in the stub hash table. */
3743
3744static struct bfd_hash_entry *
3745stub_hash_newfunc (struct bfd_hash_entry *entry,
3746 struct bfd_hash_table *table,
3747 const char *string)
3748{
3749 /* Allocate the structure if it has not already been allocated by a
3750 subclass. */
3751 if (entry == NULL)
3752 {
21d799b5 3753 entry = (struct bfd_hash_entry *)
99059e56 3754 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3755 if (entry == NULL)
3756 return entry;
3757 }
3758
3759 /* Call the allocation method of the superclass. */
3760 entry = bfd_hash_newfunc (entry, table, string);
3761 if (entry != NULL)
3762 {
3763 struct elf32_arm_stub_hash_entry *eh;
3764
3765 /* Initialize the local fields. */
3766 eh = (struct elf32_arm_stub_hash_entry *) entry;
3767 eh->stub_sec = NULL;
0955507f 3768 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3769 eh->source_value = 0;
906e58ca
NC		 3770 eh->target_value = 0;
3771 eh->target_section = NULL;
cedfb179 3772 eh->orig_insn = 0;
906e58ca 3773 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3774 eh->stub_size = 0;
3775 eh->stub_template = NULL;
0955507f 3776 eh->stub_template_size = -1;
906e58ca
NC		 3777 eh->h = NULL;
3778 eh->id_sec = NULL;
d8d2f433 3779 eh->output_name = NULL;
906e58ca
NC		 3780 }
3781
3782 return entry;
3783}
3784
00a97672 3785/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3786 shortcuts to them in our hash table. */
3787
3788static bfd_boolean
57e8b36a 3789create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3790{
3791 struct elf32_arm_link_hash_table *htab;
3792
e5a52504 3793 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3794 if (htab == NULL)
3795 return FALSE;
3796
e5a52504 3797 /* BPABI objects never have a GOT, or associated sections. */
90c14f0c 3798 if (htab->root.target_os == is_symbian)
e5a52504
MM		 3799 return TRUE;
3800
5e681ec4
PB		 3801 if (! _bfd_elf_create_got_section (dynobj, info))
3802 return FALSE;
3803
e8b09b87
CL		 3804 /* Also create .rofixup. */
3805 if (htab->fdpic_p)
3806 {
3807 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3808 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3809 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
fd361982
AM		 3810 if (htab->srofixup == NULL
3811 || !bfd_set_section_alignment (htab->srofixup, 2))
e8b09b87
CL		 3812 return FALSE;
3813 }
3814
5e681ec4
PB		 3815 return TRUE;
3816}
3817
34e77a92
RS		 3818/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3819
3820static bfd_boolean
3821create_ifunc_sections (struct bfd_link_info *info)
3822{
3823 struct elf32_arm_link_hash_table *htab;
3824 const struct elf_backend_data *bed;
3825 bfd *dynobj;
3826 asection *s;
3827 flagword flags;
b38cadfb 3828
34e77a92
RS		 3829 htab = elf32_arm_hash_table (info);
3830 dynobj = htab->root.dynobj;
3831 bed = get_elf_backend_data (dynobj);
3832 flags = bed->dynamic_sec_flags;
3833
3834 if (htab->root.iplt == NULL)
3835 {
3d4d4302
AM		 3836 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3837 flags | SEC_READONLY | SEC_CODE);
34e77a92 3838 if (s == NULL
fd361982 3839 || !bfd_set_section_alignment (s, bed->plt_alignment))
34e77a92
RS		 3840 return FALSE;
3841 htab->root.iplt = s;
3842 }
3843
3844 if (htab->root.irelplt == NULL)
3845 {
3d4d4302
AM		 3846 s = bfd_make_section_anyway_with_flags (dynobj,
3847 RELOC_SECTION (htab, ".iplt"),
3848 flags | SEC_READONLY);
34e77a92 3849 if (s == NULL
fd361982 3850 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3851 return FALSE;
3852 htab->root.irelplt = s;
3853 }
3854
3855 if (htab->root.igotplt == NULL)
3856 {
3d4d4302 3857 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92 3858 if (s == NULL
fd361982 3859 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3860 return FALSE;
3861 htab->root.igotplt = s;
3862 }
3863 return TRUE;
3864}
3865
eed94f8f
NC		 3866/* Determine if we're dealing with a Thumb only architecture. */
3867
3868static bfd_boolean
3869using_thumb_only (struct elf32_arm_link_hash_table *globals)
3870{
2fd158eb
TP		 3871 int arch;
3872 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3873 Tag_CPU_arch_profile);
eed94f8f 3874
2fd158eb
TP		 3875 if (profile)
3876 return profile == 'M';
eed94f8f 3877
2fd158eb 3878 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3879
60a019a0 3880 /* Force return logic to be reviewed for each new architecture. */
031254f2 3881 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0 3882
2fd158eb
TP		 3883 if (arch == TAG_CPU_ARCH_V6_M
3884 || arch == TAG_CPU_ARCH_V6S_M
3885 || arch == TAG_CPU_ARCH_V7E_M
3886 || arch == TAG_CPU_ARCH_V8M_BASE
031254f2
AV		 3887 || arch == TAG_CPU_ARCH_V8M_MAIN
3888 || arch == TAG_CPU_ARCH_V8_1M_MAIN)
2fd158eb 3889 return TRUE;
eed94f8f 3890
2fd158eb 3891 return FALSE;
eed94f8f
NC		 3892}
3893
3894/* Determine if we're dealing with a Thumb-2 object. */
3895
3896static bfd_boolean
3897using_thumb2 (struct elf32_arm_link_hash_table *globals)
3898{
60a019a0
TP		 3899 int arch;
3900 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3901 Tag_THUMB_ISA_use);
3902
3903 if (thumb_isa)
3904 return thumb_isa == 2;
3905
3906 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3907
3908 /* Force return logic to be reviewed for each new architecture. */
031254f2 3909 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 3910
3911 return (arch == TAG_CPU_ARCH_V6T2
3912 || arch == TAG_CPU_ARCH_V7
3913 || arch == TAG_CPU_ARCH_V7E_M
3914 || arch == TAG_CPU_ARCH_V8
bff0500d 3915 || arch == TAG_CPU_ARCH_V8R
031254f2
AV		 3916 || arch == TAG_CPU_ARCH_V8M_MAIN
3917 || arch == TAG_CPU_ARCH_V8_1M_MAIN);
eed94f8f
NC		 3918}
3919
5e866f5a
TP		 3920/* Determine whether Thumb-2 BL instruction is available. */
3921
3922static bfd_boolean
3923using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3924{
3925 int arch =
3926 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3927
3928 /* Force return logic to be reviewed for each new architecture. */
031254f2 3929 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
5e866f5a
TP		 3930
3931 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3932 return (arch == TAG_CPU_ARCH_V6T2
3933 || arch >= TAG_CPU_ARCH_V7);
3934}
3935
00a97672
RS		 3936/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3937 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3938 hash table. */
3939
3940static bfd_boolean
57e8b36a 3941elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3942{
3943 struct elf32_arm_link_hash_table *htab;
3944
3945 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3946 if (htab == NULL)
3947 return FALSE;
3948
362d30a1 3949 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3950 return FALSE;
3951
3952 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3953 return FALSE;
3954
90c14f0c 3955 if (htab->root.target_os == is_vxworks)
00a97672
RS		 3956 {
3957 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3958 return FALSE;
3959
0e1862bb 3960 if (bfd_link_pic (info))
00a97672
RS		 3961 {
3962 htab->plt_header_size = 0;
3963 htab->plt_entry_size
3964 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3965 }
3966 else
3967 {
3968 htab->plt_header_size
3969 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3970 htab->plt_entry_size
3971 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3972 }
aebf9be7
NC		 3973
3974 if (elf_elfheader (dynobj))
3975 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3976 }
eed94f8f
NC		 3977 else
3978 {
3979 /* PR ld/16017
3980 Test for thumb only architectures. Note - we cannot just call
3981 using_thumb_only() as the attributes in the output bfd have not been
3982 initialised at this point, so instead we use the input bfd. */
3983 bfd * saved_obfd = htab->obfd;
3984
3985 htab->obfd = dynobj;
3986 if (using_thumb_only (htab))
3987 {
3988 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3989 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3990 }
3991 htab->obfd = saved_obfd;
3992 }
5e681ec4 3993
7801f98f
CL		 3994 if (htab->fdpic_p) {
3995 htab->plt_header_size = 0;
3996 if (info->flags & DF_BIND_NOW)
3997 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
3998 else
3999 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
4000 }
4001
362d30a1
RS		 4002 if (!htab->root.splt
4003 || !htab->root.srelplt
9d19e4fd
AM		 4004 || !htab->root.sdynbss
4005 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 4006 abort ();
4007
4008 return TRUE;
4009}
4010
906e58ca
NC		 4011/* Copy the extra info we tack onto an elf_link_hash_entry. */
4012
4013static void
4014elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
4015 struct elf_link_hash_entry *dir,
4016 struct elf_link_hash_entry *ind)
4017{
4018 struct elf32_arm_link_hash_entry *edir, *eind;
4019
4020 edir = (struct elf32_arm_link_hash_entry *) dir;
4021 eind = (struct elf32_arm_link_hash_entry *) ind;
4022
906e58ca
NC		 4023 if (ind->root.type == bfd_link_hash_indirect)
4024 {
4025 /* Copy over PLT info. */
34e77a92
RS		 4026 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4027 eind->plt.thumb_refcount = 0;
4028 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4029 eind->plt.maybe_thumb_refcount = 0;
4030 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4031 eind->plt.noncall_refcount = 0;
4032
e8b09b87
CL		 4033 /* Copy FDPIC counters. */
4034 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4035 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4036 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4037
34e77a92
RS		 4038 /* We should only allocate a function to .iplt once the final
4039 symbol information is known. */
4040 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4041
4042 if (dir->got.refcount <= 0)
4043 {
4044 edir->tls_type = eind->tls_type;
4045 eind->tls_type = GOT_UNKNOWN;
4046 }
4047 }
4048
4049 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4050}
4051
68faa637
AM		 4052/* Destroy an ARM elf linker hash table. */
4053
4054static void
d495ab0d 4055elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4056{
4057 struct elf32_arm_link_hash_table *ret
d495ab0d 4058 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4059
4060 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4061 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4062}
4063
906e58ca
NC		 4064/* Create an ARM elf linker hash table. */
4065
4066static struct bfd_link_hash_table *
4067elf32_arm_link_hash_table_create (bfd *abfd)
4068{
4069 struct elf32_arm_link_hash_table *ret;
986f0783 4070 size_t amt = sizeof (struct elf32_arm_link_hash_table);
906e58ca 4071
7bf52ea2 4072 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4073 if (ret == NULL)
4074 return NULL;
4075
4076 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4077 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4078 sizeof (struct elf32_arm_link_hash_entry),
4079 ARM_ELF_DATA))
906e58ca
NC		 4080 {
4081 free (ret);
4082 return NULL;
4083 }
4084
906e58ca 4085 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4086 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4087#ifdef FOUR_WORD_PLT
4088 ret->plt_header_size = 16;
4089 ret->plt_entry_size = 16;
4090#else
4091 ret->plt_header_size = 20;
1db37fe6 4092 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4093#endif
f3185997 4094 ret->use_rel = TRUE;
906e58ca 4095 ret->obfd = abfd;
617a5ada 4096 ret->fdpic_p = 0;
906e58ca
NC		 4097
4098 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4099 sizeof (struct elf32_arm_stub_hash_entry)))
4100 {
d495ab0d 4101 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4102 return NULL;
4103 }
d495ab0d 4104 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4105
4106 return &ret->root.root;
4107}
4108
cd1dac3d
DG		 4109/* Determine what kind of NOPs are available. */
4110
4111static bfd_boolean
4112arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4113{
4114 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4115 Tag_CPU_arch);
cd1dac3d 4116
60a019a0 4117 /* Force return logic to be reviewed for each new architecture. */
031254f2 4118 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 4119
4120 return (arch == TAG_CPU_ARCH_V6T2
4121 || arch == TAG_CPU_ARCH_V6K
4122 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4123 || arch == TAG_CPU_ARCH_V8
4124 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4125}
4126
f4ac8484
DJ		 4127static bfd_boolean
4128arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4129{
4130 switch (stub_type)
4131 {
fea2b4d6 4132 case arm_stub_long_branch_thumb_only:
80c135e5 4133 case arm_stub_long_branch_thumb2_only:
d5a67c02 4134 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4135 case arm_stub_long_branch_v4t_thumb_arm:
4136 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4137 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4138 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4139 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4140 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4141 return TRUE;
4142 case arm_stub_none:
4143 BFD_FAIL ();
4144 return FALSE;
4145 break;
4146 default:
4147 return FALSE;
4148 }
4149}
4150
906e58ca
NC		 4151/* Determine the type of stub needed, if any, for a call. */
4152
4153static enum elf32_arm_stub_type
4154arm_type_of_stub (struct bfd_link_info *info,
4155 asection *input_sec,
4156 const Elf_Internal_Rela *rel,
34e77a92 4157 unsigned char st_type,
35fc36a8 4158 enum arm_st_branch_type *actual_branch_type,
906e58ca 4159 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4160 bfd_vma destination,
4161 asection *sym_sec,
4162 bfd *input_bfd,
4163 const char *name)
906e58ca
NC		 4164{
4165 bfd_vma location;
4166 bfd_signed_vma branch_offset;
4167 unsigned int r_type;
4168 struct elf32_arm_link_hash_table * globals;
5e866f5a 4169 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4170 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4171 int use_plt = 0;
35fc36a8 4172 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4173 union gotplt_union *root_plt;
4174 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4175 int arch;
4176 int thumb2_movw;
906e58ca 4177
35fc36a8 4178 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4179 return stub_type;
4180
906e58ca 4181 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4182 if (globals == NULL)
4183 return stub_type;
906e58ca
NC		 4184
4185 thumb_only = using_thumb_only (globals);
906e58ca 4186 thumb2 = using_thumb2 (globals);
5e866f5a 4187 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4188
d5a67c02
AV		 4189 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4190
4191 /* True for architectures that implement the thumb2 movw instruction. */
4192 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4193
906e58ca
NC		 4194 /* Determine where the call point is. */
4195 location = (input_sec->output_offset
4196 + input_sec->output_section->vma
4197 + rel->r_offset);
4198
906e58ca
NC		 4199 r_type = ELF32_R_TYPE (rel->r_info);
4200
39f21624
NC		 4201 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4202 are considering a function call relocation. */
c5423981 4203 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4204 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4205 && branch_type == ST_BRANCH_TO_ARM)
4206 branch_type = ST_BRANCH_TO_THUMB;
4207
34e77a92
RS		 4208 /* For TLS call relocs, it is the caller's responsibility to provide
4209 the address of the appropriate trampoline. */
4210 if (r_type != R_ARM_TLS_CALL
4211 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4212 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4213 ELF32_R_SYM (rel->r_info), &root_plt,
4214 &arm_plt)
34e77a92 4215 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4216 {
34e77a92 4217 asection *splt;
fe33d2fa 4218
34e77a92
RS		 4219 if (hash == NULL || hash->is_iplt)
4220 splt = globals->root.iplt;
4221 else
4222 splt = globals->root.splt;
4223 if (splt != NULL)
b38cadfb 4224 {
34e77a92
RS		 4225 use_plt = 1;
4226
4227 /* Note when dealing with PLT entries: the main PLT stub is in
4228 ARM mode, so if the branch is in Thumb mode, another
4229 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4230 PLT stub. If a long branch stub is needed, we'll add a
4231 Thumb->Arm one and branch directly to the ARM PLT entry.
4232 Here, we have to check if a pre-PLT Thumb->ARM stub
4233 is needed and if it will be close enough. */
34e77a92
RS		 4234
4235 destination = (splt->output_section->vma
4236 + splt->output_offset
4237 + root_plt->offset);
4238 st_type = STT_FUNC;
2df2751d
CL		 4239
4240 /* Thumb branch/call to PLT: it can become a branch to ARM
4241 or to Thumb. We must perform the same checks and
4242 corrections as in elf32_arm_final_link_relocate. */
4243 if ((r_type == R_ARM_THM_CALL)
4244 || (r_type == R_ARM_THM_JUMP24))
4245 {
4246 if (globals->use_blx
4247 && r_type == R_ARM_THM_CALL
4248 && !thumb_only)
4249 {
4250 /* If the Thumb BLX instruction is available, convert
4251 the BL to a BLX instruction to call the ARM-mode
4252 PLT entry. */
4253 branch_type = ST_BRANCH_TO_ARM;
4254 }
4255 else
4256 {
4257 if (!thumb_only)
4258 /* Target the Thumb stub before the ARM PLT entry. */
4259 destination -= PLT_THUMB_STUB_SIZE;
4260 branch_type = ST_BRANCH_TO_THUMB;
4261 }
4262 }
4263 else
4264 {
4265 branch_type = ST_BRANCH_TO_ARM;
4266 }
34e77a92 4267 }
5fa9e92f 4268 }
34e77a92
RS		 4269 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4270 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4271
fe33d2fa
CL		 4272 branch_offset = (bfd_signed_vma)(destination - location);
4273
0855e32b 4274 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4275 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4276 {
5fa9e92f
CL		 4277 /* Handle cases where:
4278 - this call goes too far (different Thumb/Thumb2 max
99059e56 4279 distance)
155d87d7 4280 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4281 Thumb->Arm branch (not bl). A stub is needed in this case,
4282 but only if this call is not through a PLT entry. Indeed,
695344c0 4283 PLT stubs handle mode switching already. */
5e866f5a 4284 if ((!thumb2_bl
906e58ca
NC		 4285 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4286 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4287 || (thumb2_bl
906e58ca
NC		 4288 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4289 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4290 || (thumb2
4291 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4292 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4293 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4294 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4295 && (((r_type == R_ARM_THM_CALL
4296 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4297 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4298 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4299 && !use_plt))
906e58ca 4300 {
2df2751d
CL		 4301 /* If we need to insert a Thumb-Thumb long branch stub to a
4302 PLT, use one that branches directly to the ARM PLT
4303 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4304 stub, undo this now. */
695344c0
NC		 4305 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4306 {
4307 branch_type = ST_BRANCH_TO_ARM;
4308 branch_offset += PLT_THUMB_STUB_SIZE;
4309 }
2df2751d 4310
35fc36a8 4311 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4312 {
4313 /* Thumb to thumb. */
4314 if (!thumb_only)
4315 {
d5a67c02 4316 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4317 _bfd_error_handler
871b3ab2 4318 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4319 " section with SHF_ARM_PURECODE section"
4320 " attribute is only supported for M-profile"
90b6238f 4321 " targets that implement the movw instruction"),
10463f39 4322 input_bfd, input_sec);
d5a67c02 4323
0e1862bb 4324 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4325 /* PIC stubs. */
155d87d7 4326 ? ((globals->use_blx
9553db3c 4327 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4328 /* V5T and above. Stub starts with ARM code, so
4329 we must be able to switch mode before
4330 reaching it, which is only possible for 'bl'
4331 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4332 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4333 /* On V4T, use Thumb code only. */
d3626fb0 4334 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4335
4336 /* non-PIC stubs. */
155d87d7 4337 : ((globals->use_blx
9553db3c 4338 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4339 /* V5T and above. */
4340 ? arm_stub_long_branch_any_any
4341 /* V4T. */
d3626fb0 4342 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4343 }
4344 else
4345 {
d5a67c02
AV		 4346 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4347 stub_type = arm_stub_long_branch_thumb2_only_pure;
4348 else
4349 {
4350 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4351 _bfd_error_handler
871b3ab2 4352 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4353 " section with SHF_ARM_PURECODE section"
4354 " attribute is only supported for M-profile"
90b6238f 4355 " targets that implement the movw instruction"),
10463f39 4356 input_bfd, input_sec);
d5a67c02
AV		 4357
4358 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4359 /* PIC stub. */
4360 ? arm_stub_long_branch_thumb_only_pic
4361 /* non-PIC stub. */
4362 : (thumb2 ? arm_stub_long_branch_thumb2_only
4363 : arm_stub_long_branch_thumb_only);
4364 }
906e58ca
NC		 4365 }
4366 }
4367 else
4368 {
d5a67c02 4369 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4370 _bfd_error_handler
871b3ab2 4371 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4372 " section with SHF_ARM_PURECODE section"
4373 " attribute is only supported" " for M-profile"
90b6238f 4374 " targets that implement the movw instruction"),
10463f39 4375 input_bfd, input_sec);
d5a67c02 4376
906e58ca 4377 /* Thumb to arm. */
c820be07
NC		 4378 if (sym_sec != NULL
4379 && sym_sec->owner != NULL
4380 && !INTERWORK_FLAG (sym_sec->owner))
4381 {
4eca0228 4382 _bfd_error_handler
90b6238f
AM		 4383 (_("%pB(%s): warning: interworking not enabled;"
4384 " first occurrence: %pB: %s call to %s"),
4385 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4386 }
4387
0855e32b 4388 stub_type =
0e1862bb 4389 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4390 /* PIC stubs. */
0855e32b 4391 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4392 /* TLS PIC stubs. */
0855e32b
NS		 4393 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4394 : arm_stub_long_branch_v4t_thumb_tls_pic)
4395 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4396 /* V5T PIC and above. */
4397 ? arm_stub_long_branch_any_arm_pic
4398 /* V4T PIC stub. */
4399 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4400
4401 /* non-PIC stubs. */
0855e32b 4402 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4403 /* V5T and above. */
4404 ? arm_stub_long_branch_any_any
4405 /* V4T. */
4406 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4407
4408 /* Handle v4t short branches. */
fea2b4d6 4409 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4410 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4411 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4412 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4413 }
4414 }
4415 }
fe33d2fa
CL		 4416 else if (r_type == R_ARM_CALL
4417 || r_type == R_ARM_JUMP24
0855e32b
NS		 4418 || r_type == R_ARM_PLT32
4419 || r_type == R_ARM_TLS_CALL)
906e58ca 4420 {
d5a67c02 4421 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4422 _bfd_error_handler
871b3ab2 4423 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4424 " section with SHF_ARM_PURECODE section"
4425 " attribute is only supported for M-profile"
90b6238f 4426 " targets that implement the movw instruction"),
10463f39 4427 input_bfd, input_sec);
35fc36a8 4428 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4429 {
4430 /* Arm to thumb. */
c820be07
NC		 4431
4432 if (sym_sec != NULL
4433 && sym_sec->owner != NULL
4434 && !INTERWORK_FLAG (sym_sec->owner))
4435 {
4eca0228 4436 _bfd_error_handler
90b6238f
AM		 4437 (_("%pB(%s): warning: interworking not enabled;"
4438 " first occurrence: %pB: %s call to %s"),
4439 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4440 }
4441
4442 /* We have an extra 2-bytes reach because of
4443 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4444 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4445 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4446 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4447 || (r_type == R_ARM_JUMP24)
4448 || (r_type == R_ARM_PLT32))
906e58ca 4449 {
0e1862bb 4450 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4451 /* PIC stubs. */
ebe24dd4
CL		 4452 ? ((globals->use_blx)
4453 /* V5T and above. */
4454 ? arm_stub_long_branch_any_thumb_pic
4455 /* V4T stub. */
4456 : arm_stub_long_branch_v4t_arm_thumb_pic)
4457
c2b4a39d
CL		 4458 /* non-PIC stubs. */
4459 : ((globals->use_blx)
4460 /* V5T and above. */
4461 ? arm_stub_long_branch_any_any
4462 /* V4T. */
4463 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4464 }
4465 }
4466 else
4467 {
4468 /* Arm to arm. */
4469 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4470 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4471 {
0855e32b 4472 stub_type =
0e1862bb 4473 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4474 /* PIC stubs. */
0855e32b 4475 ? (r_type == R_ARM_TLS_CALL
6a631e86 4476 /* TLS PIC Stub. */
0855e32b 4477 ? arm_stub_long_branch_any_tls_pic
90c14f0c 4478 : (globals->root.target_os == is_nacl
7a89b94e
NC		 4479 ? arm_stub_long_branch_arm_nacl_pic
4480 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4481 /* non-PIC stubs. */
90c14f0c 4482 : (globals->root.target_os == is_nacl
7a89b94e
NC		 4483 ? arm_stub_long_branch_arm_nacl
4484 : arm_stub_long_branch_any_any);
906e58ca
NC		 4485 }
4486 }
4487 }
4488
fe33d2fa
CL		 4489 /* If a stub is needed, record the actual destination type. */
4490 if (stub_type != arm_stub_none)
35fc36a8 4491 *actual_branch_type = branch_type;
fe33d2fa 4492
906e58ca
NC		 4493 return stub_type;
4494}
4495
4496/* Build a name for an entry in the stub hash table. */
4497
4498static char *
4499elf32_arm_stub_name (const asection *input_section,
4500 const asection *sym_sec,
4501 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4502 const Elf_Internal_Rela *rel,
4503 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4504{
4505 char *stub_name;
4506 bfd_size_type len;
4507
4508 if (hash)
4509 {
fe33d2fa 4510 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4511 stub_name = (char *) bfd_malloc (len);
906e58ca 4512 if (stub_name != NULL)
fe33d2fa 4513 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4514 input_section->id & 0xffffffff,
4515 hash->root.root.root.string,
fe33d2fa
CL		 4516 (int) rel->r_addend & 0xffffffff,
4517 (int) stub_type);
906e58ca
NC		 4518 }
4519 else
4520 {
fe33d2fa 4521 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4522 stub_name = (char *) bfd_malloc (len);
906e58ca 4523 if (stub_name != NULL)
fe33d2fa 4524 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4525 input_section->id & 0xffffffff,
4526 sym_sec->id & 0xffffffff,
0855e32b
NS		 4527 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4528 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4529 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4530 (int) rel->r_addend & 0xffffffff,
4531 (int) stub_type);
906e58ca
NC		 4532 }
4533
4534 return stub_name;
4535}
4536
4537/* Look up an entry in the stub hash. Stub entries are cached because
4538 creating the stub name takes a bit of time. */
4539
4540static struct elf32_arm_stub_hash_entry *
4541elf32_arm_get_stub_entry (const asection *input_section,
4542 const asection *sym_sec,
4543 struct elf_link_hash_entry *hash,
4544 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4545 struct elf32_arm_link_hash_table *htab,
4546 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4547{
4548 struct elf32_arm_stub_hash_entry *stub_entry;
4549 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4550 const asection *id_sec;
4551
4552 if ((input_section->flags & SEC_CODE) == 0)
4553 return NULL;
4554
4d83e8d9
CL		 4555 /* If the input section is the CMSE stubs one and it needs a long
4556 branch stub to reach it's final destination, give up with an
4557 error message: this is not supported. See PR ld/24709. */
4558 if (!strncmp (input_section->name, CMSE_STUB_NAME, strlen(CMSE_STUB_NAME)))
4559 {
4560 bfd *output_bfd = htab->obfd;
4561 asection *out_sec = bfd_get_section_by_name (output_bfd, CMSE_STUB_NAME);
4562
4563 _bfd_error_handler (_("ERROR: CMSE stub (%s section) too far "
4564 "(%#" PRIx64 ") from destination (%#" PRIx64 ")"),
4565 CMSE_STUB_NAME,
4566 (uint64_t)out_sec->output_section->vma
4567 + out_sec->output_offset,
4568 (uint64_t)sym_sec->output_section->vma
4569 + sym_sec->output_offset
4570 + h->root.root.u.def.value);
4571 /* Exit, rather than leave incompletely processed
4572 relocations. */
4573 xexit(1);
4574 }
4575
906e58ca
NC		 4576 /* If this input section is part of a group of sections sharing one
4577 stub section, then use the id of the first section in the group.
4578 Stub names need to include a section id, as there may well be
4579 more than one stub used to reach say, printf, and we need to
4580 distinguish between them. */
c2abbbeb 4581 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4582 id_sec = htab->stub_group[input_section->id].link_sec;
4583
4584 if (h != NULL && h->stub_cache != NULL
4585 && h->stub_cache->h == h
fe33d2fa
CL		 4586 && h->stub_cache->id_sec == id_sec
4587 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4588 {
4589 stub_entry = h->stub_cache;
4590 }
4591 else
4592 {
4593 char *stub_name;
4594
fe33d2fa 4595 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4596 if (stub_name == NULL)
4597 return NULL;
4598
4599 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4600 stub_name, FALSE, FALSE);
4601 if (h != NULL)
4602 h->stub_cache = stub_entry;
4603
4604 free (stub_name);
4605 }
4606
4607 return stub_entry;
4608}
4609
daa4adae
TP		 4610/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4611 section. */
4612
4613static bfd_boolean
4614arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4615{
4616 if (stub_type >= max_stub_type)
4617 abort (); /* Should be unreachable. */
4618
4ba2ef8f
TP		 4619 switch (stub_type)
4620 {
4621 case arm_stub_cmse_branch_thumb_only:
4622 return TRUE;
4623
4624 default:
4625 return FALSE;
4626 }
4627
4628 abort (); /* Should be unreachable. */
daa4adae
TP		 4629}
4630
4631/* Required alignment (as a power of 2) for the dedicated section holding
4632 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4633 with input sections. */
4634
4635static int
4636arm_dedicated_stub_output_section_required_alignment
4637 (enum elf32_arm_stub_type stub_type)
4638{
4639 if (stub_type >= max_stub_type)
4640 abort (); /* Should be unreachable. */
4641
4ba2ef8f
TP		 4642 switch (stub_type)
4643 {
4644 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4645 boundary. */
4646 case arm_stub_cmse_branch_thumb_only:
4647 return 5;
4648
4649 default:
4650 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4651 return 0;
4652 }
4653
4654 abort (); /* Should be unreachable. */
daa4adae
TP		 4655}
4656
4657/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4658 NULL if veneers of this type are interspersed with input sections. */
4659
4660static const char *
4661arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4662{
4663 if (stub_type >= max_stub_type)
4664 abort (); /* Should be unreachable. */
4665
4ba2ef8f
TP		 4666 switch (stub_type)
4667 {
4668 case arm_stub_cmse_branch_thumb_only:
4d83e8d9 4669 return CMSE_STUB_NAME;
4ba2ef8f
TP		 4670
4671 default:
4672 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4673 return NULL;
4674 }
4675
4676 abort (); /* Should be unreachable. */
daa4adae
TP		 4677}
4678
4679/* If veneers of type STUB_TYPE should go in a dedicated output section,
4680 returns the address of the hash table field in HTAB holding a pointer to the
4681 corresponding input section. Otherwise, returns NULL. */
4682
4683static asection **
4ba2ef8f
TP		 4684arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4685 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4686{
4687 if (stub_type >= max_stub_type)
4688 abort (); /* Should be unreachable. */
4689
4ba2ef8f
TP		 4690 switch (stub_type)
4691 {
4692 case arm_stub_cmse_branch_thumb_only:
4693 return &htab->cmse_stub_sec;
4694
4695 default:
4696 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4697 return NULL;
4698 }
4699
4700 abort (); /* Should be unreachable. */
daa4adae
TP		 4701}
4702
4703/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4704 is the section that branch into veneer and can be NULL if stub should go in
4705 a dedicated output section. Returns a pointer to the stub section, and the
4706 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4707 LINK_SEC_P may be NULL. */
906e58ca 4708
48229727
JB		 4709static asection *
4710elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4711 struct elf32_arm_link_hash_table *htab,
4712 enum elf32_arm_stub_type stub_type)
906e58ca 4713{
daa4adae
TP		 4714 asection *link_sec, *out_sec, **stub_sec_p;
4715 const char *stub_sec_prefix;
4716 bfd_boolean dedicated_output_section =
4717 arm_dedicated_stub_output_section_required (stub_type);
4718 int align;
906e58ca 4719
daa4adae 4720 if (dedicated_output_section)
906e58ca 4721 {
daa4adae
TP		 4722 bfd *output_bfd = htab->obfd;
4723 const char *out_sec_name =
4724 arm_dedicated_stub_output_section_name (stub_type);
4725 link_sec = NULL;
4726 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4727 stub_sec_prefix = out_sec_name;
4728 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4729 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4730 if (out_sec == NULL)
906e58ca 4731 {
90b6238f 4732 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4733 "section %s"), out_sec_name);
daa4adae 4734 return NULL;
906e58ca 4735 }
daa4adae
TP		 4736 }
4737 else
4738 {
c2abbbeb 4739 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4740 link_sec = htab->stub_group[section->id].link_sec;
4741 BFD_ASSERT (link_sec != NULL);
4742 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4743 if (*stub_sec_p == NULL)
4744 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4745 stub_sec_prefix = link_sec->name;
4746 out_sec = link_sec->output_section;
90c14f0c 4747 align = htab->root.target_os == is_nacl ? 4 : 3;
906e58ca 4748 }
b38cadfb 4749
daa4adae
TP		 4750 if (*stub_sec_p == NULL)
4751 {
4752 size_t namelen;
4753 bfd_size_type len;
4754 char *s_name;
4755
4756 namelen = strlen (stub_sec_prefix);
4757 len = namelen + sizeof (STUB_SUFFIX);
4758 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4759 if (s_name == NULL)
4760 return NULL;
4761
4762 memcpy (s_name, stub_sec_prefix, namelen);
4763 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4764 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4765 align);
4766 if (*stub_sec_p == NULL)
4767 return NULL;
4768
4769 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4770 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4771 | SEC_KEEP;
4772 }
4773
4774 if (!dedicated_output_section)
4775 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4776
48229727
JB		 4777 if (link_sec_p)
4778 *link_sec_p = link_sec;
b38cadfb 4779
daa4adae 4780 return *stub_sec_p;
48229727
JB		 4781}
4782
4783/* Add a new stub entry to the stub hash. Not all fields of the new
4784 stub entry are initialised. */
4785
4786static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4787elf32_arm_add_stub (const char *stub_name, asection *section,
4788 struct elf32_arm_link_hash_table *htab,
4789 enum elf32_arm_stub_type stub_type)
48229727
JB		 4790{
4791 asection *link_sec;
4792 asection *stub_sec;
4793 struct elf32_arm_stub_hash_entry *stub_entry;
4794
daa4adae
TP		 4795 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4796 stub_type);
48229727
JB		 4797 if (stub_sec == NULL)
4798 return NULL;
906e58ca
NC		 4799
4800 /* Enter this entry into the linker stub hash table. */
4801 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4802 TRUE, FALSE);
4803 if (stub_entry == NULL)
4804 {
6bde4c52
TP		 4805 if (section == NULL)
4806 section = stub_sec;
871b3ab2 4807 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4808 section->owner, stub_name);
906e58ca
NC		 4809 return NULL;
4810 }
4811
4812 stub_entry->stub_sec = stub_sec;
0955507f 4813 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4814 stub_entry->id_sec = link_sec;
4815
906e58ca
NC		 4816 return stub_entry;
4817}
4818
4819/* Store an Arm insn into an output section not processed by
4820 elf32_arm_write_section. */
4821
4822static void
8029a119
NC		 4823put_arm_insn (struct elf32_arm_link_hash_table * htab,
4824 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4825{
4826 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4827 bfd_putl32 (val, ptr);
4828 else
4829 bfd_putb32 (val, ptr);
4830}
4831
4832/* Store a 16-bit Thumb insn into an output section not processed by
4833 elf32_arm_write_section. */
4834
4835static void
8029a119
NC		 4836put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4837 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4838{
4839 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4840 bfd_putl16 (val, ptr);
4841 else
4842 bfd_putb16 (val, ptr);
4843}
4844
a504d23a
LA		 4845/* Store a Thumb2 insn into an output section not processed by
4846 elf32_arm_write_section. */
4847
4848static void
4849put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4850 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4851{
4852 /* T2 instructions are 16-bit streamed. */
4853 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4854 {
4855 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4856 bfd_putl16 ((val & 0xffff), ptr + 2);
4857 }
4858 else
4859 {
4860 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4861 bfd_putb16 ((val & 0xffff), ptr + 2);
4862 }
4863}
4864
0855e32b
NS		 4865/* If it's possible to change R_TYPE to a more efficient access
4866 model, return the new reloc type. */
4867
4868static unsigned
b38cadfb 4869elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4870 struct elf_link_hash_entry *h)
4871{
4872 int is_local = (h == NULL);
4873
9cb09e33 4874 if (bfd_link_dll (info)
0e1862bb 4875 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4876 return r_type;
4877
b38cadfb 4878 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4879 switch (r_type)
4880 {
4881 case R_ARM_TLS_GOTDESC:
4882 case R_ARM_TLS_CALL:
4883 case R_ARM_THM_TLS_CALL:
4884 case R_ARM_TLS_DESCSEQ:
4885 case R_ARM_THM_TLS_DESCSEQ:
4886 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4887 }
4888
4889 return r_type;
4890}
4891
48229727
JB		 4892static bfd_reloc_status_type elf32_arm_final_link_relocate
4893 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4894 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4895 const char *, unsigned char, enum arm_st_branch_type,
4896 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4897
4563a860
JB		 4898static unsigned int
4899arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4900{
4901 switch (stub_type)
4902 {
4903 case arm_stub_a8_veneer_b_cond:
4904 case arm_stub_a8_veneer_b:
4905 case arm_stub_a8_veneer_bl:
4906 return 2;
4907
4908 case arm_stub_long_branch_any_any:
4909 case arm_stub_long_branch_v4t_arm_thumb:
4910 case arm_stub_long_branch_thumb_only:
80c135e5 4911 case arm_stub_long_branch_thumb2_only:
d5a67c02 4912 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4913 case arm_stub_long_branch_v4t_thumb_thumb:
4914 case arm_stub_long_branch_v4t_thumb_arm:
4915 case arm_stub_short_branch_v4t_thumb_arm:
4916 case arm_stub_long_branch_any_arm_pic:
4917 case arm_stub_long_branch_any_thumb_pic:
4918 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4919 case arm_stub_long_branch_v4t_arm_thumb_pic:
4920 case arm_stub_long_branch_v4t_thumb_arm_pic:
4921 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4922 case arm_stub_long_branch_any_tls_pic:
4923 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4924 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4925 case arm_stub_a8_veneer_blx:
4926 return 4;
b38cadfb 4927
7a89b94e
NC		 4928 case arm_stub_long_branch_arm_nacl:
4929 case arm_stub_long_branch_arm_nacl_pic:
4930 return 16;
4931
4563a860
JB		 4932 default:
4933 abort (); /* Should be unreachable. */
4934 }
4935}
4936
4f4faa4d
TP		 4937/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4938 veneering (TRUE) or have their own symbol (FALSE). */
4939
4940static bfd_boolean
4941arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4942{
4943 if (stub_type >= max_stub_type)
4944 abort (); /* Should be unreachable. */
4945
4ba2ef8f
TP		 4946 switch (stub_type)
4947 {
4948 case arm_stub_cmse_branch_thumb_only:
4949 return TRUE;
4950
4951 default:
4952 return FALSE;
4953 }
4954
4955 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4956}
4957
d7c5bd02
TP		 4958/* Returns the padding needed for the dedicated section used stubs of type
4959 STUB_TYPE. */
4960
4961static int
4962arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4963{
4964 if (stub_type >= max_stub_type)
4965 abort (); /* Should be unreachable. */
4966
4ba2ef8f
TP		 4967 switch (stub_type)
4968 {
4969 case arm_stub_cmse_branch_thumb_only:
4970 return 32;
4971
4972 default:
4973 return 0;
4974 }
4975
4976 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4977}
4978
0955507f
TP		 4979/* If veneers of type STUB_TYPE should go in a dedicated output section,
4980 returns the address of the hash table field in HTAB holding the offset at
4981 which new veneers should be layed out in the stub section. */
4982
4983static bfd_vma*
4984arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4985 enum elf32_arm_stub_type stub_type)
4986{
4987 switch (stub_type)
4988 {
4989 case arm_stub_cmse_branch_thumb_only:
4990 return &htab->new_cmse_stub_offset;
4991
4992 default:
4993 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4994 return NULL;
4995 }
4996}
4997
906e58ca
NC		 4998static bfd_boolean
4999arm_build_one_stub (struct bfd_hash_entry *gen_entry,
5000 void * in_arg)
5001{
7a89b94e 5002#define MAXRELOCS 3
0955507f 5003 bfd_boolean removed_sg_veneer;
906e58ca 5004 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 5005 struct elf32_arm_link_hash_table *globals;
906e58ca 5006 struct bfd_link_info *info;
906e58ca
NC		 5007 asection *stub_sec;
5008 bfd *stub_bfd;
906e58ca
NC		 5009 bfd_byte *loc;
5010 bfd_vma sym_value;
5011 int template_size;
5012 int size;
d3ce72d0 5013 const insn_sequence *template_sequence;
906e58ca 5014 int i;
48229727
JB		 5015 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
5016 int stub_reloc_offset[MAXRELOCS] = {0, 0};
5017 int nrelocs = 0;
0955507f 5018 int just_allocated = 0;
906e58ca
NC		 5019
5020 /* Massage our args to the form they really have. */
5021 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5022 info = (struct bfd_link_info *) in_arg;
5023
abf874aa
CL		 5024 /* Fail if the target section could not be assigned to an output
5025 section. The user should fix his linker script. */
5026 if (stub_entry->target_section->output_section == NULL
5027 && info->non_contiguous_regions)
53215f21
CL		 5028 info->callbacks->einfo (_("%F%P: Could not assign '%pA' to an output section. "
5029 "Retry without --enable-non-contiguous-regions.\n"),
5030 stub_entry->target_section);
abf874aa 5031
906e58ca 5032 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5033 if (globals == NULL)
5034 return FALSE;
906e58ca 5035
906e58ca
NC		 5036 stub_sec = stub_entry->stub_sec;
5037
4dfe6ac6 5038 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 5039 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
5040 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 5041 return TRUE;
fe33d2fa 5042
0955507f
TP		 5043 /* Assign a slot at the end of section if none assigned yet. */
5044 if (stub_entry->stub_offset == (bfd_vma) -1)
5045 {
5046 stub_entry->stub_offset = stub_sec->size;
5047 just_allocated = 1;
5048 }
906e58ca
NC		 5049 loc = stub_sec->contents + stub_entry->stub_offset;
5050
5051 stub_bfd = stub_sec->owner;
5052
906e58ca
NC		 5053 /* This is the address of the stub destination. */
5054 sym_value = (stub_entry->target_value
5055 + stub_entry->target_section->output_offset
5056 + stub_entry->target_section->output_section->vma);
5057
d3ce72d0 5058 template_sequence = stub_entry->stub_template;
461a49ca 5059 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5060
5061 size = 0;
461a49ca 5062 for (i = 0; i < template_size; i++)
906e58ca 5063 {
d3ce72d0 5064 switch (template_sequence[i].type)
461a49ca
DJ		 5065 {
5066 case THUMB16_TYPE:
48229727 5067 {
d3ce72d0
NC		 5068 bfd_vma data = (bfd_vma) template_sequence[i].data;
5069 if (template_sequence[i].reloc_addend != 0)
48229727 5070 {
99059e56
RM		 5071 /* We've borrowed the reloc_addend field to mean we should
5072 insert a condition code into this (Thumb-1 branch)
5073 instruction. See THUMB16_BCOND_INSN. */
5074 BFD_ASSERT ((data & 0xff00) == 0xd000);
5075 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5076 }
fe33d2fa 5077 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5078 size += 2;
5079 }
461a49ca 5080 break;
906e58ca 5081
48229727 5082 case THUMB32_TYPE:
fe33d2fa
CL		 5083 bfd_put_16 (stub_bfd,
5084 (template_sequence[i].data >> 16) & 0xffff,
5085 loc + size);
5086 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5087 loc + size + 2);
99059e56
RM		 5088 if (template_sequence[i].r_type != R_ARM_NONE)
5089 {
5090 stub_reloc_idx[nrelocs] = i;
5091 stub_reloc_offset[nrelocs++] = size;
5092 }
5093 size += 4;
5094 break;
48229727 5095
461a49ca 5096 case ARM_TYPE:
fe33d2fa
CL		 5097 bfd_put_32 (stub_bfd, template_sequence[i].data,
5098 loc + size);
461a49ca
DJ		 5099 /* Handle cases where the target is encoded within the
5100 instruction. */
d3ce72d0 5101 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5102 {
48229727
JB		 5103 stub_reloc_idx[nrelocs] = i;
5104 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5105 }
5106 size += 4;
5107 break;
5108
5109 case DATA_TYPE:
d3ce72d0 5110 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5111 stub_reloc_idx[nrelocs] = i;
5112 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5113 size += 4;
5114 break;
5115
5116 default:
5117 BFD_FAIL ();
5118 return FALSE;
5119 }
906e58ca 5120 }
461a49ca 5121
0955507f
TP		 5122 if (just_allocated)
5123 stub_sec->size += size;
906e58ca 5124
461a49ca
DJ		 5125 /* Stub size has already been computed in arm_size_one_stub. Check
5126 consistency. */
5127 BFD_ASSERT (size == stub_entry->stub_size);
5128
906e58ca 5129 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5130 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5131 sym_value |= 1;
5132
0955507f
TP		 5133 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5134 to relocate in each stub. */
5135 removed_sg_veneer =
5136 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5137 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5138
48229727 5139 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5140 {
5141 Elf_Internal_Rela rel;
5142 bfd_boolean unresolved_reloc;
5143 char *error_message;
5144 bfd_vma points_to =
5145 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5146
5147 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5148 rel.r_info = ELF32_R_INFO (0,
5149 template_sequence[stub_reloc_idx[i]].r_type);
5150 rel.r_addend = 0;
5151
5152 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5153 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5154 template should refer back to the instruction after the original
5155 branch. We use target_section as Cortex-A8 erratum workaround stubs
5156 are only generated when both source and target are in the same
5157 section. */
5158 points_to = stub_entry->target_section->output_section->vma
5159 + stub_entry->target_section->output_offset
5160 + stub_entry->source_value;
5161
5162 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5163 (template_sequence[stub_reloc_idx[i]].r_type),
5164 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5165 points_to, info, stub_entry->target_section, "", STT_FUNC,
5166 stub_entry->branch_type,
5167 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5168 &error_message);
5169 }
906e58ca
NC		 5170
5171 return TRUE;
48229727 5172#undef MAXRELOCS
906e58ca
NC		 5173}
5174
48229727
JB		 5175/* Calculate the template, template size and instruction size for a stub.
5176 Return value is the instruction size. */
906e58ca 5177
48229727
JB		 5178static unsigned int
5179find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5180 const insn_sequence **stub_template,
5181 int *stub_template_size)
906e58ca 5182{
d3ce72d0 5183 const insn_sequence *template_sequence = NULL;
48229727
JB		 5184 int template_size = 0, i;
5185 unsigned int size;
906e58ca 5186
d3ce72d0 5187 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5188 if (stub_template)
5189 *stub_template = template_sequence;
5190
48229727 5191 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5192 if (stub_template_size)
5193 *stub_template_size = template_size;
906e58ca
NC		 5194
5195 size = 0;
461a49ca
DJ		 5196 for (i = 0; i < template_size; i++)
5197 {
d3ce72d0 5198 switch (template_sequence[i].type)
461a49ca
DJ		 5199 {
5200 case THUMB16_TYPE:
5201 size += 2;
5202 break;
5203
5204 case ARM_TYPE:
48229727 5205 case THUMB32_TYPE:
461a49ca
DJ		 5206 case DATA_TYPE:
5207 size += 4;
5208 break;
5209
5210 default:
5211 BFD_FAIL ();
2a229407 5212 return 0;
461a49ca
DJ		 5213 }
5214 }
5215
48229727
JB		 5216 return size;
5217}
5218
5219/* As above, but don't actually build the stub. Just bump offset so
5220 we know stub section sizes. */
5221
5222static bfd_boolean
5223arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5224 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5225{
5226 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5227 const insn_sequence *template_sequence;
48229727
JB		 5228 int template_size, size;
5229
5230 /* Massage our args to the form they really have. */
5231 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5232
5233 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5234 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5235
d3ce72d0 5236 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5237 &template_size);
5238
0955507f
TP		 5239 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5240 if (stub_entry->stub_template_size)
5241 {
5242 stub_entry->stub_size = size;
5243 stub_entry->stub_template = template_sequence;
5244 stub_entry->stub_template_size = template_size;
5245 }
5246
5247 /* Already accounted for. */
5248 if (stub_entry->stub_offset != (bfd_vma) -1)
5249 return TRUE;
461a49ca 5250
906e58ca
NC		 5251 size = (size + 7) & ~7;
5252 stub_entry->stub_sec->size += size;
461a49ca 5253
906e58ca
NC		 5254 return TRUE;
5255}
5256
5257/* External entry points for sizing and building linker stubs. */
5258
5259/* Set up various things so that we can make a list of input sections
5260 for each output section included in the link. Returns -1 on error,
5261 0 when no stubs will be needed, and 1 on success. */
5262
5263int
5264elf32_arm_setup_section_lists (bfd *output_bfd,
5265 struct bfd_link_info *info)
5266{
5267 bfd *input_bfd;
5268 unsigned int bfd_count;
7292b3ac 5269 unsigned int top_id, top_index;
906e58ca
NC		 5270 asection *section;
5271 asection **input_list, **list;
986f0783 5272 size_t amt;
906e58ca
NC		 5273 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5274
4dfe6ac6
NC		 5275 if (htab == NULL)
5276 return 0;
906e58ca
NC		 5277 if (! is_elf_hash_table (htab))
5278 return 0;
5279
5280 /* Count the number of input BFDs and find the top input section id. */
5281 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5282 input_bfd != NULL;
c72f2fb2 5283 input_bfd = input_bfd->link.next)
906e58ca
NC		 5284 {
5285 bfd_count += 1;
5286 for (section = input_bfd->sections;
5287 section != NULL;
5288 section = section->next)
5289 {
5290 if (top_id < section->id)
5291 top_id = section->id;
5292 }
5293 }
5294 htab->bfd_count = bfd_count;
5295
5296 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5297 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5298 if (htab->stub_group == NULL)
5299 return -1;
fe33d2fa 5300 htab->top_id = top_id;
906e58ca
NC		 5301
5302 /* We can't use output_bfd->section_count here to find the top output
5303 section index as some sections may have been removed, and
5304 _bfd_strip_section_from_output doesn't renumber the indices. */
5305 for (section = output_bfd->sections, top_index = 0;
5306 section != NULL;
5307 section = section->next)
5308 {
5309 if (top_index < section->index)
5310 top_index = section->index;
5311 }
5312
5313 htab->top_index = top_index;
5314 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5315 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5316 htab->input_list = input_list;
5317 if (input_list == NULL)
5318 return -1;
5319
5320 /* For sections we aren't interested in, mark their entries with a
5321 value we can check later. */
5322 list = input_list + top_index;
5323 do
5324 *list = bfd_abs_section_ptr;
5325 while (list-- != input_list);
5326
5327 for (section = output_bfd->sections;
5328 section != NULL;
5329 section = section->next)
5330 {
5331 if ((section->flags & SEC_CODE) != 0)
5332 input_list[section->index] = NULL;
5333 }
5334
5335 return 1;
5336}
5337
5338/* The linker repeatedly calls this function for each input section,
5339 in the order that input sections are linked into output sections.
5340 Build lists of input sections to determine groupings between which
5341 we may insert linker stubs. */
5342
5343void
5344elf32_arm_next_input_section (struct bfd_link_info *info,
5345 asection *isec)
5346{
5347 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5348
4dfe6ac6
NC		 5349 if (htab == NULL)
5350 return;
5351
906e58ca
NC		 5352 if (isec->output_section->index <= htab->top_index)
5353 {
5354 asection **list = htab->input_list + isec->output_section->index;
5355
a7470592 5356 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5357 {
5358 /* Steal the link_sec pointer for our list. */
5359#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5360 /* This happens to make the list in reverse order,
07d72278 5361 which we reverse later. */
906e58ca
NC		 5362 PREV_SEC (isec) = *list;
5363 *list = isec;
5364 }
5365 }
5366}
5367
5368/* See whether we can group stub sections together. Grouping stub
5369 sections may result in fewer stubs. More importantly, we need to
07d72278 5370 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5371 .fini output sections respectively, because glibc splits the
5372 _init and _fini functions into multiple parts. Putting a stub in
5373 the middle of a function is not a good idea. */
5374
5375static void
5376group_sections (struct elf32_arm_link_hash_table *htab,
5377 bfd_size_type stub_group_size,
07d72278 5378 bfd_boolean stubs_always_after_branch)
906e58ca 5379{
07d72278 5380 asection **list = htab->input_list;
906e58ca
NC		 5381
5382 do
5383 {
5384 asection *tail = *list;
07d72278 5385 asection *head;
906e58ca
NC		 5386
5387 if (tail == bfd_abs_section_ptr)
5388 continue;
5389
07d72278
DJ		 5390 /* Reverse the list: we must avoid placing stubs at the
5391 beginning of the section because the beginning of the text
5392 section may be required for an interrupt vector in bare metal
5393 code. */
5394#define NEXT_SEC PREV_SEC
e780aef2
CL		 5395 head = NULL;
5396 while (tail != NULL)
99059e56
RM		 5397 {
5398 /* Pop from tail. */
5399 asection *item = tail;
5400 tail = PREV_SEC (item);
e780aef2 5401
99059e56
RM		 5402 /* Push on head. */
5403 NEXT_SEC (item) = head;
5404 head = item;
5405 }
07d72278
DJ		 5406
5407 while (head != NULL)
906e58ca
NC		 5408 {
5409 asection *curr;
07d72278 5410 asection *next;
e780aef2
CL		 5411 bfd_vma stub_group_start = head->output_offset;
5412 bfd_vma end_of_next;
906e58ca 5413
07d72278 5414 curr = head;
e780aef2 5415 while (NEXT_SEC (curr) != NULL)
8cd931b7 5416 {
e780aef2
CL		 5417 next = NEXT_SEC (curr);
5418 end_of_next = next->output_offset + next->size;
5419 if (end_of_next - stub_group_start >= stub_group_size)
5420 /* End of NEXT is too far from start, so stop. */
8cd931b7 5421 break;
e780aef2
CL		 5422 /* Add NEXT to the group. */
5423 curr = next;
8cd931b7 5424 }
906e58ca 5425
07d72278 5426 /* OK, the size from the start to the start of CURR is less
906e58ca 5427 than stub_group_size and thus can be handled by one stub
07d72278 5428 section. (Or the head section is itself larger than
906e58ca
NC		 5429 stub_group_size, in which case we may be toast.)
5430 We should really be keeping track of the total size of
5431 stubs added here, as stubs contribute to the final output
7fb9f789 5432 section size. */
906e58ca
NC		 5433 do
5434 {
07d72278 5435 next = NEXT_SEC (head);
906e58ca 5436 /* Set up this stub group. */
07d72278 5437 htab->stub_group[head->id].link_sec = curr;
906e58ca 5438 }
07d72278 5439 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5440
5441 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5442 bytes after the stub section can be handled by it too. */
5443 if (!stubs_always_after_branch)
906e58ca 5444 {
e780aef2
CL		 5445 stub_group_start = curr->output_offset + curr->size;
5446
8cd931b7 5447 while (next != NULL)
906e58ca 5448 {
e780aef2
CL		 5449 end_of_next = next->output_offset + next->size;
5450 if (end_of_next - stub_group_start >= stub_group_size)
5451 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5452 break;
e780aef2 5453 /* Add NEXT to the stub group. */
07d72278
DJ		 5454 head = next;
5455 next = NEXT_SEC (head);
5456 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5457 }
5458 }
07d72278 5459 head = next;
906e58ca
NC		 5460 }
5461 }
07d72278 5462 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5463
5464 free (htab->input_list);
5465#undef PREV_SEC
07d72278 5466#undef NEXT_SEC
906e58ca
NC		 5467}
5468
48229727
JB		 5469/* Comparison function for sorting/searching relocations relating to Cortex-A8
5470 erratum fix. */
5471
5472static int
5473a8_reloc_compare (const void *a, const void *b)
5474{
21d799b5
NC		 5475 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5476 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5477
5478 if (ra->from < rb->from)
5479 return -1;
5480 else if (ra->from > rb->from)
5481 return 1;
5482 else
5483 return 0;
5484}
5485
5486static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5487 const char *, char **);
5488
5489/* Helper function to scan code for sequences which might trigger the Cortex-A8
5490 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5491 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5492 otherwise. */
5493
81694485
NC		 5494static bfd_boolean
5495cortex_a8_erratum_scan (bfd *input_bfd,
5496 struct bfd_link_info *info,
48229727
JB		 5497 struct a8_erratum_fix **a8_fixes_p,
5498 unsigned int *num_a8_fixes_p,
5499 unsigned int *a8_fix_table_size_p,
5500 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5501 unsigned int num_a8_relocs,
5502 unsigned prev_num_a8_fixes,
5503 bfd_boolean *stub_changed_p)
48229727
JB		 5504{
5505 asection *section;
5506 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5507 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5508 unsigned int num_a8_fixes = *num_a8_fixes_p;
5509 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5510
4dfe6ac6
NC		 5511 if (htab == NULL)
5512 return FALSE;
5513
48229727
JB		 5514 for (section = input_bfd->sections;
5515 section != NULL;
5516 section = section->next)
5517 {
5518 bfd_byte *contents = NULL;
5519 struct _arm_elf_section_data *sec_data;
5520 unsigned int span;
5521 bfd_vma base_vma;
5522
5523 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5524 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5525 || (section->flags & SEC_EXCLUDE) != 0
5526 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5527 || (section->output_section == bfd_abs_section_ptr))
5528 continue;
48229727
JB		 5529
5530 base_vma = section->output_section->vma + section->output_offset;
5531
5532 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5533 contents = elf_section_data (section)->this_hdr.contents;
48229727 5534 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5535 return TRUE;
48229727
JB		 5536
5537 sec_data = elf32_arm_section_data (section);
5538
5539 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5540 {
5541 unsigned int span_start = sec_data->map[span].vma;
5542 unsigned int span_end = (span == sec_data->mapcount - 1)
5543 ? section->size : sec_data->map[span + 1].vma;
5544 unsigned int i;
5545 char span_type = sec_data->map[span].type;
5546 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5547
5548 if (span_type != 't')
5549 continue;
5550
5551 /* Span is entirely within a single 4KB region: skip scanning. */
5552 if (((base_vma + span_start) & ~0xfff)
48229727 5553 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5554 continue;
5555
5556 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5557
5558 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5559 * The branch target is in the same 4KB region as the
5560 first half of the branch.
5561 * The instruction before the branch is a 32-bit
5562 length non-branch instruction. */
5563 for (i = span_start; i < span_end;)
5564 {
5565 unsigned int insn = bfd_getl16 (&contents[i]);
5566 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5567 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5568
99059e56
RM		 5569 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5570 insn_32bit = TRUE;
48229727
JB		 5571
5572 if (insn_32bit)
99059e56
RM		 5573 {
5574 /* Load the rest of the insn (in manual-friendly order). */
5575 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5576
5577 /* Encoding T4: B<c>.W. */
5578 is_b = (insn & 0xf800d000) == 0xf0009000;
5579 /* Encoding T1: BL<c>.W. */
5580 is_bl = (insn & 0xf800d000) == 0xf000d000;
5581 /* Encoding T2: BLX<c>.W. */
5582 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5583 /* Encoding T3: B<c>.W (not permitted in IT block). */
5584 is_bcc = (insn & 0xf800d000) == 0xf0008000
5585 && (insn & 0x07f00000) != 0x03800000;
5586 }
5587
5588 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5589
99059e56 5590 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5591 && insn_32bit
5592 && is_32bit_branch
5593 && last_was_32bit
5594 && ! last_was_branch)
99059e56
RM		 5595 {
5596 bfd_signed_vma offset = 0;
5597 bfd_boolean force_target_arm = FALSE;
48229727 5598 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5599 bfd_vma target;
5600 enum elf32_arm_stub_type stub_type = arm_stub_none;
5601 struct a8_erratum_reloc key, *found;
5602 bfd_boolean use_plt = FALSE;
48229727 5603
99059e56
RM		 5604 key.from = base_vma + i;
5605 found = (struct a8_erratum_reloc *)
5606 bsearch (&key, a8_relocs, num_a8_relocs,
5607 sizeof (struct a8_erratum_reloc),
5608 &a8_reloc_compare);
48229727
JB		 5609
5610 if (found)
5611 {
5612 char *error_message = NULL;
5613 struct elf_link_hash_entry *entry;
5614
5615 /* We don't care about the error returned from this
99059e56 5616 function, only if there is glue or not. */
48229727
JB		 5617 entry = find_thumb_glue (info, found->sym_name,
5618 &error_message);
5619
5620 if (entry)
5621 found->non_a8_stub = TRUE;
5622
92750f34 5623 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5624 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5625 && found->hash->root.plt.offset != (bfd_vma) -1)
5626 use_plt = TRUE;
5627
5628 if (found->r_type == R_ARM_THM_CALL)
5629 {
35fc36a8
RS		 5630 if (found->branch_type == ST_BRANCH_TO_ARM
5631 || use_plt)
92750f34
DJ		 5632 force_target_arm = TRUE;
5633 else
5634 force_target_thumb = TRUE;
5635 }
48229727
JB		 5636 }
5637
99059e56 5638 /* Check if we have an offending branch instruction. */
48229727
JB		 5639
5640 if (found && found->non_a8_stub)
5641 /* We've already made a stub for this instruction, e.g.
5642 it's a long branch or a Thumb->ARM stub. Assume that
5643 stub will suffice to work around the A8 erratum (see
5644 setting of always_after_branch above). */
5645 ;
99059e56
RM		 5646 else if (is_bcc)
5647 {
5648 offset = (insn & 0x7ff) << 1;
5649 offset |= (insn & 0x3f0000) >> 4;
5650 offset |= (insn & 0x2000) ? 0x40000 : 0;
5651 offset |= (insn & 0x800) ? 0x80000 : 0;
5652 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5653 if (offset & 0x100000)
5654 offset |= ~ ((bfd_signed_vma) 0xfffff);
5655 stub_type = arm_stub_a8_veneer_b_cond;
5656 }
5657 else if (is_b || is_bl || is_blx)
5658 {
5659 int s = (insn & 0x4000000) != 0;
5660 int j1 = (insn & 0x2000) != 0;
5661 int j2 = (insn & 0x800) != 0;
5662 int i1 = !(j1 ^ s);
5663 int i2 = !(j2 ^ s);
5664
5665 offset = (insn & 0x7ff) << 1;
5666 offset |= (insn & 0x3ff0000) >> 4;
5667 offset |= i2 << 22;
5668 offset |= i1 << 23;
5669 offset |= s << 24;
5670 if (offset & 0x1000000)
5671 offset |= ~ ((bfd_signed_vma) 0xffffff);
5672
5673 if (is_blx)
5674 offset &= ~ ((bfd_signed_vma) 3);
5675
5676 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5677 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5678 }
5679
5680 if (stub_type != arm_stub_none)
5681 {
5682 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5683
5684 /* The original instruction is a BL, but the target is
99059e56 5685 an ARM instruction. If we were not making a stub,
48229727
JB		 5686 the BL would have been converted to a BLX. Use the
5687 BLX stub instead in that case. */
5688 if (htab->use_blx && force_target_arm
5689 && stub_type == arm_stub_a8_veneer_bl)
5690 {
5691 stub_type = arm_stub_a8_veneer_blx;
5692 is_blx = TRUE;
5693 is_bl = FALSE;
5694 }
5695 /* Conversely, if the original instruction was
5696 BLX but the target is Thumb mode, use the BL
5697 stub. */
5698 else if (force_target_thumb
5699 && stub_type == arm_stub_a8_veneer_blx)
5700 {
5701 stub_type = arm_stub_a8_veneer_bl;
5702 is_blx = FALSE;
5703 is_bl = TRUE;
5704 }
5705
99059e56
RM		 5706 if (is_blx)
5707 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5708
99059e56
RM		 5709 /* If we found a relocation, use the proper destination,
5710 not the offset in the (unrelocated) instruction.
48229727
JB		 5711 Note this is always done if we switched the stub type
5712 above. */
99059e56
RM		 5713 if (found)
5714 offset =
81694485 5715 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5716
99059e56
RM		 5717 /* If the stub will use a Thumb-mode branch to a
5718 PLT target, redirect it to the preceding Thumb
5719 entry point. */
5720 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5721 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5722
99059e56 5723 target = pc_for_insn + offset;
48229727 5724
99059e56
RM		 5725 /* The BLX stub is ARM-mode code. Adjust the offset to
5726 take the different PC value (+8 instead of +4) into
48229727 5727 account. */
99059e56
RM		 5728 if (stub_type == arm_stub_a8_veneer_blx)
5729 offset += 4;
5730
5731 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5732 {
5733 char *stub_name = NULL;
5734
5735 if (num_a8_fixes == a8_fix_table_size)
5736 {
5737 a8_fix_table_size *= 2;
5738 a8_fixes = (struct a8_erratum_fix *)
5739 bfd_realloc (a8_fixes,
5740 sizeof (struct a8_erratum_fix)
5741 * a8_fix_table_size);
5742 }
48229727 5743
eb7c4339
NS		 5744 if (num_a8_fixes < prev_num_a8_fixes)
5745 {
5746 /* If we're doing a subsequent scan,
5747 check if we've found the same fix as
5748 before, and try and reuse the stub
5749 name. */
5750 stub_name = a8_fixes[num_a8_fixes].stub_name;
5751 if ((a8_fixes[num_a8_fixes].section != section)
5752 || (a8_fixes[num_a8_fixes].offset != i))
5753 {
5754 free (stub_name);
5755 stub_name = NULL;
5756 *stub_changed_p = TRUE;
5757 }
5758 }
5759
5760 if (!stub_name)
5761 {
21d799b5 5762 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5763 if (stub_name != NULL)
5764 sprintf (stub_name, "%x:%x", section->id, i);
5765 }
48229727 5766
99059e56
RM		 5767 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5768 a8_fixes[num_a8_fixes].section = section;
5769 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5770 a8_fixes[num_a8_fixes].target_offset =
5771 target - base_vma;
99059e56
RM		 5772 a8_fixes[num_a8_fixes].orig_insn = insn;
5773 a8_fixes[num_a8_fixes].stub_name = stub_name;
5774 a8_fixes[num_a8_fixes].stub_type = stub_type;
5775 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5776 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5777
99059e56
RM		 5778 num_a8_fixes++;
5779 }
5780 }
5781 }
48229727 5782
99059e56
RM		 5783 i += insn_32bit ? 4 : 2;
5784 last_was_32bit = insn_32bit;
48229727 5785 last_was_branch = is_32bit_branch;
99059e56
RM		 5786 }
5787 }
48229727
JB		 5788
5789 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5790 free (contents);
48229727 5791 }
fe33d2fa 5792
48229727
JB		 5793 *a8_fixes_p = a8_fixes;
5794 *num_a8_fixes_p = num_a8_fixes;
5795 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5796
81694485 5797 return FALSE;
48229727
JB		 5798}
5799
b715f643
TP		 5800/* Create or update a stub entry depending on whether the stub can already be
5801 found in HTAB. The stub is identified by:
5802 - its type STUB_TYPE
5803 - its source branch (note that several can share the same stub) whose
5804 section and relocation (if any) are given by SECTION and IRELA
5805 respectively
5806 - its target symbol whose input section, hash, name, value and branch type
5807 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5808 respectively
5809
5810 If found, the value of the stub's target symbol is updated from SYM_VALUE
5811 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5812 TRUE and the stub entry is initialized.
5813
0955507f
TP		 5814 Returns the stub that was created or updated, or NULL if an error
5815 occurred. */
b715f643 5816
0955507f 5817static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5818elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5819 enum elf32_arm_stub_type stub_type, asection *section,
5820 Elf_Internal_Rela *irela, asection *sym_sec,
5821 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5822 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5823 bfd_boolean *new_stub)
5824{
5825 const asection *id_sec;
5826 char *stub_name;
5827 struct elf32_arm_stub_hash_entry *stub_entry;
5828 unsigned int r_type;
4f4faa4d 5829 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5830
5831 BFD_ASSERT (stub_type != arm_stub_none);
5832 *new_stub = FALSE;
5833
4f4faa4d
TP		 5834 if (sym_claimed)
5835 stub_name = sym_name;
5836 else
5837 {
5838 BFD_ASSERT (irela);
5839 BFD_ASSERT (section);
c2abbbeb 5840 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5841
4f4faa4d
TP		 5842 /* Support for grouping stub sections. */
5843 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5844
4f4faa4d
TP		 5845 /* Get the name of this stub. */
5846 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5847 stub_type);
5848 if (!stub_name)
0955507f 5849 return NULL;
4f4faa4d 5850 }
b715f643
TP		 5851
5852 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5853 FALSE);
5854 /* The proper stub has already been created, just update its value. */
5855 if (stub_entry != NULL)
5856 {
4f4faa4d
TP		 5857 if (!sym_claimed)
5858 free (stub_name);
b715f643 5859 stub_entry->target_value = sym_value;
0955507f 5860 return stub_entry;
b715f643
TP		 5861 }
5862
daa4adae 5863 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5864 if (stub_entry == NULL)
5865 {
4f4faa4d
TP		 5866 if (!sym_claimed)
5867 free (stub_name);
0955507f 5868 return NULL;
b715f643
TP		 5869 }
5870
5871 stub_entry->target_value = sym_value;
5872 stub_entry->target_section = sym_sec;
5873 stub_entry->stub_type = stub_type;
5874 stub_entry->h = hash;
5875 stub_entry->branch_type = branch_type;
5876
4f4faa4d
TP		 5877 if (sym_claimed)
5878 stub_entry->output_name = sym_name;
5879 else
b715f643 5880 {
4f4faa4d
TP		 5881 if (sym_name == NULL)
5882 sym_name = "unnamed";
5883 stub_entry->output_name = (char *)
5884 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5885 + strlen (sym_name));
5886 if (stub_entry->output_name == NULL)
5887 {
5888 free (stub_name);
0955507f 5889 return NULL;
4f4faa4d 5890 }
b715f643 5891
4f4faa4d
TP		 5892 /* For historical reasons, use the existing names for ARM-to-Thumb and
5893 Thumb-to-ARM stubs. */
5894 r_type = ELF32_R_TYPE (irela->r_info);
5895 if ((r_type == (unsigned int) R_ARM_THM_CALL
5896 || r_type == (unsigned int) R_ARM_THM_JUMP24
5897 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5898 && branch_type == ST_BRANCH_TO_ARM)
5899 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5900 else if ((r_type == (unsigned int) R_ARM_CALL
5901 || r_type == (unsigned int) R_ARM_JUMP24)
5902 && branch_type == ST_BRANCH_TO_THUMB)
5903 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5904 else
5905 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5906 }
b715f643
TP		 5907
5908 *new_stub = TRUE;
0955507f 5909 return stub_entry;
b715f643
TP		 5910}
5911
4ba2ef8f
TP		 5912/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5913 gateway veneer to transition from non secure to secure state and create them
5914 accordingly.
5915
5916 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5917 defines the conditions that govern Secure Gateway veneer creation for a
5918 given symbol <SYM> as follows:
5919 - it has function type
5920 - it has non local binding
5921 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5922 same type, binding and value as <SYM> (called normal symbol).
5923 An entry function can handle secure state transition itself in which case
5924 its special symbol would have a different value from the normal symbol.
5925
5926 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5927 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5928 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5929 created.
4ba2ef8f 5930
0955507f 5931 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5932
5933static bfd_boolean
5934cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5935 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5936 int *cmse_stub_created)
4ba2ef8f
TP		 5937{
5938 const struct elf_backend_data *bed;
5939 Elf_Internal_Shdr *symtab_hdr;
5940 unsigned i, j, sym_count, ext_start;
5941 Elf_Internal_Sym *cmse_sym, *local_syms;
5942 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5943 enum arm_st_branch_type branch_type;
5944 char *sym_name, *lsym_name;
5945 bfd_vma sym_value;
5946 asection *section;
0955507f
TP		 5947 struct elf32_arm_stub_hash_entry *stub_entry;
5948 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5949
5950 bed = get_elf_backend_data (input_bfd);
5951 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5952 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5953 ext_start = symtab_hdr->sh_info;
5954 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5955 && out_attr[Tag_CPU_arch_profile].i == 'M');
5956
5957 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5958 if (local_syms == NULL)
5959 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5960 symtab_hdr->sh_info, 0, NULL, NULL,
5961 NULL);
5962 if (symtab_hdr->sh_info && local_syms == NULL)
5963 return FALSE;
5964
5965 /* Scan symbols. */
5966 for (i = 0; i < sym_count; i++)
5967 {
5968 cmse_invalid = FALSE;
5969
5970 if (i < ext_start)
5971 {
5972 cmse_sym = &local_syms[i];
4ba2ef8f
TP		 5973 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5974 symtab_hdr->sh_link,
5975 cmse_sym->st_name);
baf46cd7
AM		 5976 if (!sym_name || !CONST_STRNEQ (sym_name, CMSE_PREFIX))
5977 continue;
5978
4ba2ef8f
TP		 5979 /* Special symbol with local binding. */
5980 cmse_invalid = TRUE;
5981 }
5982 else
5983 {
5984 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5985 sym_name = (char *) cmse_hash->root.root.root.string;
baf46cd7 5986 if (!CONST_STRNEQ (sym_name, CMSE_PREFIX))
4ba2ef8f
TP		 5987 continue;
5988
5989 /* Special symbol has incorrect binding or type. */
5990 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5991 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5992 || cmse_hash->root.type != STT_FUNC)
5993 cmse_invalid = TRUE;
5994 }
5995
5996 if (!is_v8m)
5997 {
90b6238f
AM		 5998 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
5999 "ARMv8-M architecture or later"),
4eca0228 6000 input_bfd, sym_name);
4ba2ef8f
TP		 6001 is_v8m = TRUE; /* Avoid multiple warning. */
6002 ret = FALSE;
6003 }
6004
6005 if (cmse_invalid)
6006 {
90b6238f
AM		 6007 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
6008 " a global or weak function symbol"),
4eca0228 6009 input_bfd, sym_name);
4ba2ef8f
TP		 6010 ret = FALSE;
6011 if (i < ext_start)
6012 continue;
6013 }
6014
6015 sym_name += strlen (CMSE_PREFIX);
6016 hash = (struct elf32_arm_link_hash_entry *)
6017 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6018
6019 /* No associated normal symbol or it is neither global nor weak. */
6020 if (!hash
6021 || (hash->root.root.type != bfd_link_hash_defined
6022 && hash->root.root.type != bfd_link_hash_defweak)
6023 || hash->root.type != STT_FUNC)
6024 {
6025 /* Initialize here to avoid warning about use of possibly
6026 uninitialized variable. */
6027 j = 0;
6028
6029 if (!hash)
6030 {
6031 /* Searching for a normal symbol with local binding. */
6032 for (; j < ext_start; j++)
6033 {
6034 lsym_name =
6035 bfd_elf_string_from_elf_section (input_bfd,
6036 symtab_hdr->sh_link,
6037 local_syms[j].st_name);
6038 if (!strcmp (sym_name, lsym_name))
6039 break;
6040 }
6041 }
6042
6043 if (hash || j < ext_start)
6044 {
4eca0228 6045 _bfd_error_handler
90b6238f
AM		 6046 (_("%pB: invalid standard symbol `%s'; it must be "
6047 "a global or weak function symbol"),
6048 input_bfd, sym_name);
4ba2ef8f
TP		 6049 }
6050 else
4eca0228 6051 _bfd_error_handler
90b6238f 6052 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6053 ret = FALSE;
6054 if (!hash)
6055 continue;
6056 }
6057
6058 sym_value = hash->root.root.u.def.value;
6059 section = hash->root.root.u.def.section;
6060
6061 if (cmse_hash->root.root.u.def.section != section)
6062 {
4eca0228 6063 _bfd_error_handler
90b6238f 6064 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6065 input_bfd, sym_name);
6066 ret = FALSE;
6067 }
6068 if (cmse_hash->root.root.u.def.value != sym_value)
6069 continue; /* Ignore: could be an entry function starting with SG. */
6070
6071 /* If this section is a link-once section that will be discarded, then
6072 don't create any stubs. */
6073 if (section->output_section == NULL)
6074 {
4eca0228 6075 _bfd_error_handler
90b6238f 6076 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6077 continue;
6078 }
6079
6080 if (hash->root.size == 0)
6081 {
4eca0228 6082 _bfd_error_handler
90b6238f 6083 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6084 ret = FALSE;
6085 }
6086
6087 if (!ret)
6088 continue;
6089 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6090 stub_entry
4ba2ef8f
TP		 6091 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6092 NULL, NULL, section, hash, sym_name,
6093 sym_value, branch_type, &new_stub);
6094
0955507f 6095 if (stub_entry == NULL)
4ba2ef8f
TP		 6096 ret = FALSE;
6097 else
6098 {
6099 BFD_ASSERT (new_stub);
0955507f 6100 (*cmse_stub_created)++;
4ba2ef8f
TP		 6101 }
6102 }
6103
6104 if (!symtab_hdr->contents)
6105 free (local_syms);
6106 return ret;
6107}
6108
0955507f
TP		 6109/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6110 code entry function, ie can be called from non secure code without using a
6111 veneer. */
6112
6113static bfd_boolean
6114cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6115{
42484486 6116 bfd_byte contents[4];
0955507f
TP		 6117 uint32_t first_insn;
6118 asection *section;
6119 file_ptr offset;
6120 bfd *abfd;
6121
6122 /* Defined symbol of function type. */
6123 if (hash->root.root.type != bfd_link_hash_defined
6124 && hash->root.root.type != bfd_link_hash_defweak)
6125 return FALSE;
6126 if (hash->root.type != STT_FUNC)
6127 return FALSE;
6128
6129 /* Read first instruction. */
6130 section = hash->root.root.u.def.section;
6131 abfd = section->owner;
6132 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6133 if (!bfd_get_section_contents (abfd, section, contents, offset,
6134 sizeof (contents)))
0955507f
TP		 6135 return FALSE;
6136
42484486
TP		 6137 first_insn = bfd_get_32 (abfd, contents);
6138
6139 /* Starts by SG instruction. */
0955507f
TP		 6140 return first_insn == 0xe97fe97f;
6141}
6142
6143/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6144 secure gateway veneers (ie. the veneers was not in the input import library)
6145 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6146
6147static bfd_boolean
6148arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6149{
6150 struct elf32_arm_stub_hash_entry *stub_entry;
6151 struct bfd_link_info *info;
6152
6153 /* Massage our args to the form they really have. */
6154 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6155 info = (struct bfd_link_info *) gen_info;
6156
6157 if (info->out_implib_bfd)
6158 return TRUE;
6159
6160 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6161 return TRUE;
6162
6163 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6164 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6165
6166 return TRUE;
6167}
6168
6169/* Set offset of each secure gateway veneers so that its address remain
6170 identical to the one in the input import library referred by
6171 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6172 (present in input import library but absent from the executable being
6173 linked) or if new veneers appeared and there is no output import library
6174 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6175 number of secure gateway veneers found in the input import library.
6176
6177 The function returns whether an error occurred. If no error occurred,
6178 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6179 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6180 veneer observed set for new veneers to be layed out after. */
6181
6182static bfd_boolean
6183set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6184 struct elf32_arm_link_hash_table *htab,
6185 int *cmse_stub_created)
6186{
6187 long symsize;
6188 char *sym_name;
6189 flagword flags;
6190 long i, symcount;
6191 bfd *in_implib_bfd;
6192 asection *stub_out_sec;
6193 bfd_boolean ret = TRUE;
6194 Elf_Internal_Sym *intsym;
6195 const char *out_sec_name;
6196 bfd_size_type cmse_stub_size;
6197 asymbol **sympp = NULL, *sym;
6198 struct elf32_arm_link_hash_entry *hash;
6199 const insn_sequence *cmse_stub_template;
6200 struct elf32_arm_stub_hash_entry *stub_entry;
6201 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6202 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6203 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6204
6205 /* No input secure gateway import library. */
6206 if (!htab->in_implib_bfd)
6207 return TRUE;
6208
6209 in_implib_bfd = htab->in_implib_bfd;
6210 if (!htab->cmse_implib)
6211 {
871b3ab2 6212 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6213 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6214 return FALSE;
6215 }
6216
6217 /* Get symbol table size. */
6218 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6219 if (symsize < 0)
6220 return FALSE;
6221
6222 /* Read in the input secure gateway import library's symbol table. */
9a733151
AM		 6223 sympp = (asymbol **) bfd_malloc (symsize);
6224 if (sympp == NULL)
6225 return FALSE;
6226
0955507f
TP		 6227 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6228 if (symcount < 0)
6229 {
6230 ret = FALSE;
6231 goto free_sym_buf;
6232 }
6233
6234 htab->new_cmse_stub_offset = 0;
6235 cmse_stub_size =
6236 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6237 &cmse_stub_template,
6238 &cmse_stub_template_size);
6239 out_sec_name =
6240 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6241 stub_out_sec =
6242 bfd_get_section_by_name (htab->obfd, out_sec_name);
6243 if (stub_out_sec != NULL)
6244 cmse_stub_sec_vma = stub_out_sec->vma;
6245
6246 /* Set addresses of veneers mentionned in input secure gateway import
6247 library's symbol table. */
6248 for (i = 0; i < symcount; i++)
6249 {
6250 sym = sympp[i];
6251 flags = sym->flags;
6252 sym_name = (char *) bfd_asymbol_name (sym);
6253 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6254
6255 if (sym->section != bfd_abs_section_ptr
6256 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6257 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6258 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6259 != ST_BRANCH_TO_THUMB))
6260 {
90b6238f
AM		 6261 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6262 "symbol should be absolute, global and "
6263 "refer to Thumb functions"),
4eca0228 6264 in_implib_bfd, sym_name);
0955507f
TP		 6265 ret = FALSE;
6266 continue;
6267 }
6268
6269 veneer_value = bfd_asymbol_value (sym);
6270 stub_offset = veneer_value - cmse_stub_sec_vma;
6271 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6272 FALSE, FALSE);
6273 hash = (struct elf32_arm_link_hash_entry *)
6274 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6275
6276 /* Stub entry should have been created by cmse_scan or the symbol be of
6277 a secure function callable from non secure code. */
6278 if (!stub_entry && !hash)
6279 {
6280 bfd_boolean new_stub;
6281
4eca0228 6282 _bfd_error_handler
90b6238f 6283 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6284 hash = (struct elf32_arm_link_hash_entry *)
6285 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6286 stub_entry
6287 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6288 NULL, NULL, bfd_abs_section_ptr, hash,
6289 sym_name, veneer_value,
6290 ST_BRANCH_TO_THUMB, &new_stub);
6291 if (stub_entry == NULL)
6292 ret = FALSE;
6293 else
6294 {
6295 BFD_ASSERT (new_stub);
6296 new_cmse_stubs_created++;
6297 (*cmse_stub_created)++;
6298 }
6299 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6300 stub_entry->stub_offset = stub_offset;
6301 }
6302 /* Symbol found is not callable from non secure code. */
6303 else if (!stub_entry)
6304 {
6305 if (!cmse_entry_fct_p (hash))
6306 {
90b6238f 6307 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6308 sym_name);
0955507f
TP		 6309 ret = FALSE;
6310 }
6311 continue;
6312 }
6313 else
6314 {
6315 /* Only stubs for SG veneers should have been created. */
6316 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6317
6318 /* Check visibility hasn't changed. */
6319 if (!!(flags & BSF_GLOBAL)
6320 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6321 _bfd_error_handler
90b6238f 6322 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6323 sym_name);
6324
6325 stub_entry->stub_offset = stub_offset;
6326 }
6327
6328 /* Size should match that of a SG veneer. */
6329 if (intsym->st_size != cmse_stub_size)
6330 {
90b6238f 6331 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6332 in_implib_bfd, sym_name);
0955507f
TP		 6333 ret = FALSE;
6334 }
6335
6336 /* Previous veneer address is before current SG veneer section. */
6337 if (veneer_value < cmse_stub_sec_vma)
6338 {
6339 /* Avoid offset underflow. */
6340 if (stub_entry)
6341 stub_entry->stub_offset = 0;
6342 stub_offset = 0;
6343 ret = FALSE;
6344 }
6345
6346 /* Complain if stub offset not a multiple of stub size. */
6347 if (stub_offset % cmse_stub_size)
6348 {
4eca0228 6349 _bfd_error_handler
90b6238f
AM		 6350 (_("offset of veneer for entry function `%s' not a multiple of "
6351 "its size"), sym_name);
0955507f
TP		 6352 ret = FALSE;
6353 }
6354
6355 if (!ret)
6356 continue;
6357
6358 new_cmse_stubs_created--;
6359 if (veneer_value < cmse_stub_array_start)
6360 cmse_stub_array_start = veneer_value;
6361 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6362 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6363 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6364 }
6365
6366 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6367 {
6368 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6369 _bfd_error_handler
0955507f
TP		 6370 (_("new entry function(s) introduced but no output import library "
6371 "specified:"));
6372 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6373 }
6374
6375 if (cmse_stub_array_start != cmse_stub_sec_vma)
6376 {
4eca0228 6377 _bfd_error_handler
90b6238f 6378 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6379 out_sec_name);
6380 ret = FALSE;
6381 }
6382
dc1e8a47 6383 free_sym_buf:
0955507f
TP		 6384 free (sympp);
6385 return ret;
6386}
6387
906e58ca
NC		 6388/* Determine and set the size of the stub section for a final link.
6389
6390 The basic idea here is to examine all the relocations looking for
6391 PC-relative calls to a target that is unreachable with a "bl"
6392 instruction. */
6393
6394bfd_boolean
6395elf32_arm_size_stubs (bfd *output_bfd,
6396 bfd *stub_bfd,
6397 struct bfd_link_info *info,
6398 bfd_signed_vma group_size,
7a89b94e 6399 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6400 asection *,
7a89b94e 6401 unsigned int),
906e58ca
NC		 6402 void (*layout_sections_again) (void))
6403{
0955507f 6404 bfd_boolean ret = TRUE;
4ba2ef8f 6405 obj_attribute *out_attr;
0955507f 6406 int cmse_stub_created = 0;
906e58ca 6407 bfd_size_type stub_group_size;
4ba2ef8f 6408 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6409 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6410 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6411 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6412 struct a8_erratum_reloc *a8_relocs = NULL;
6413 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6414
4dfe6ac6
NC		 6415 if (htab == NULL)
6416 return FALSE;
6417
48229727
JB		 6418 if (htab->fix_cortex_a8)
6419 {
21d799b5 6420 a8_fixes = (struct a8_erratum_fix *)
99059e56 6421 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6422 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6423 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6424 }
906e58ca
NC		 6425
6426 /* Propagate mach to stub bfd, because it may not have been
6427 finalized when we created stub_bfd. */
6428 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6429 bfd_get_mach (output_bfd));
6430
6431 /* Stash our params away. */
6432 htab->stub_bfd = stub_bfd;
6433 htab->add_stub_section = add_stub_section;
6434 htab->layout_sections_again = layout_sections_again;
07d72278 6435 stubs_always_after_branch = group_size < 0;
48229727 6436
4ba2ef8f
TP		 6437 out_attr = elf_known_obj_attributes_proc (output_bfd);
6438 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6439
48229727
JB		 6440 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6441 as the first half of a 32-bit branch straddling two 4K pages. This is a
6442 crude way of enforcing that. */
6443 if (htab->fix_cortex_a8)
6444 stubs_always_after_branch = 1;
6445
906e58ca
NC		 6446 if (group_size < 0)
6447 stub_group_size = -group_size;
6448 else
6449 stub_group_size = group_size;
6450
6451 if (stub_group_size == 1)
6452 {
6453 /* Default values. */
6454 /* Thumb branch range is +-4MB has to be used as the default
6455 maximum size (a given section can contain both ARM and Thumb
6456 code, so the worst case has to be taken into account).
6457
6458 This value is 24K less than that, which allows for 2025
6459 12-byte stubs. If we exceed that, then we will fail to link.
6460 The user will have to relink with an explicit group size
6461 option. */
6462 stub_group_size = 4170000;
6463 }
6464
07d72278 6465 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6466
3ae046cc
NS		 6467 /* If we're applying the cortex A8 fix, we need to determine the
6468 program header size now, because we cannot change it later --
6469 that could alter section placements. Notice the A8 erratum fix
6470 ends up requiring the section addresses to remain unchanged
6471 modulo the page size. That's something we cannot represent
6472 inside BFD, and we don't want to force the section alignment to
6473 be the page size. */
6474 if (htab->fix_cortex_a8)
6475 (*htab->layout_sections_again) ();
6476
906e58ca
NC		 6477 while (1)
6478 {
6479 bfd *input_bfd;
6480 unsigned int bfd_indx;
6481 asection *stub_sec;
d7c5bd02 6482 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6483 bfd_boolean stub_changed = FALSE;
6484 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6485
48229727 6486 num_a8_fixes = 0;
906e58ca
NC		 6487 for (input_bfd = info->input_bfds, bfd_indx = 0;
6488 input_bfd != NULL;
c72f2fb2 6489 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6490 {
6491 Elf_Internal_Shdr *symtab_hdr;
6492 asection *section;
6493 Elf_Internal_Sym *local_syms = NULL;
6494
73d5efd7
AM		 6495 if (!is_arm_elf (input_bfd))
6496 continue;
6497 if ((input_bfd->flags & DYNAMIC) != 0
6498 && (elf_sym_hashes (input_bfd) == NULL
6499 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0))
99059e56 6500 continue;
adbcc655 6501
48229727
JB		 6502 num_a8_relocs = 0;
6503
906e58ca
NC		 6504 /* We'll need the symbol table in a second. */
6505 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6506 if (symtab_hdr->sh_info == 0)
6507 continue;
6508
4ba2ef8f
TP		 6509 /* Limit scan of symbols to object file whose profile is
6510 Microcontroller to not hinder performance in the general case. */
6511 if (m_profile && first_veneer_scan)
6512 {
6513 struct elf_link_hash_entry **sym_hashes;
6514
6515 sym_hashes = elf_sym_hashes (input_bfd);
6516 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6517 &cmse_stub_created))
4ba2ef8f 6518 goto error_ret_free_local;
0955507f
TP		 6519
6520 if (cmse_stub_created != 0)
6521 stub_changed = TRUE;
4ba2ef8f
TP		 6522 }
6523
906e58ca
NC		 6524 /* Walk over each section attached to the input bfd. */
6525 for (section = input_bfd->sections;
6526 section != NULL;
6527 section = section->next)
6528 {
6529 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6530
6531 /* If there aren't any relocs, then there's nothing more
6532 to do. */
6533 if ((section->flags & SEC_RELOC) == 0
6534 || section->reloc_count == 0
6535 || (section->flags & SEC_CODE) == 0)
6536 continue;
6537
6538 /* If this section is a link-once section that will be
6539 discarded, then don't create any stubs. */
6540 if (section->output_section == NULL
6541 || section->output_section->owner != output_bfd)
6542 continue;
6543
6544 /* Get the relocs. */
6545 internal_relocs
6546 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6547 NULL, info->keep_memory);
6548 if (internal_relocs == NULL)
6549 goto error_ret_free_local;
6550
6551 /* Now examine each relocation. */
6552 irela = internal_relocs;
6553 irelaend = irela + section->reloc_count;
6554 for (; irela < irelaend; irela++)
6555 {
6556 unsigned int r_type, r_indx;
906e58ca
NC		 6557 asection *sym_sec;
6558 bfd_vma sym_value;
6559 bfd_vma destination;
6560 struct elf32_arm_link_hash_entry *hash;
7413f23f 6561 const char *sym_name;
34e77a92 6562 unsigned char st_type;
35fc36a8 6563 enum arm_st_branch_type branch_type;
48229727 6564 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6565
6566 r_type = ELF32_R_TYPE (irela->r_info);
6567 r_indx = ELF32_R_SYM (irela->r_info);
6568
6569 if (r_type >= (unsigned int) R_ARM_max)
6570 {
6571 bfd_set_error (bfd_error_bad_value);
6572 error_ret_free_internal:
6573 if (elf_section_data (section)->relocs == NULL)
6574 free (internal_relocs);
15dd01b1
TP		 6575 /* Fall through. */
6576 error_ret_free_local:
c9594989 6577 if (symtab_hdr->contents != (unsigned char *) local_syms)
15dd01b1
TP		 6578 free (local_syms);
6579 return FALSE;
906e58ca 6580 }
b38cadfb 6581
0855e32b
NS		 6582 hash = NULL;
6583 if (r_indx >= symtab_hdr->sh_info)
6584 hash = elf32_arm_hash_entry
6585 (elf_sym_hashes (input_bfd)
6586 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6587
0855e32b
NS		 6588 /* Only look for stubs on branch instructions, or
6589 non-relaxed TLSCALL */
906e58ca 6590 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6591 && (r_type != (unsigned int) R_ARM_THM_CALL)
6592 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6593 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6594 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6595 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6596 && (r_type != (unsigned int) R_ARM_PLT32)
6597 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6598 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6599 && r_type == elf32_arm_tls_transition
6600 (info, r_type, &hash->root)
6601 && ((hash ? hash->tls_type
6602 : (elf32_arm_local_got_tls_type
6603 (input_bfd)[r_indx]))
6604 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6605 continue;
6606
6607 /* Now determine the call target, its name, value,
6608 section. */
6609 sym_sec = NULL;
6610 sym_value = 0;
6611 destination = 0;
7413f23f 6612 sym_name = NULL;
b38cadfb 6613
0855e32b
NS		 6614 if (r_type == (unsigned int) R_ARM_TLS_CALL
6615 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6616 {
6617 /* A non-relaxed TLS call. The target is the
6618 plt-resident trampoline and nothing to do
6619 with the symbol. */
6620 BFD_ASSERT (htab->tls_trampoline > 0);
6621 sym_sec = htab->root.splt;
6622 sym_value = htab->tls_trampoline;
6623 hash = 0;
34e77a92 6624 st_type = STT_FUNC;
35fc36a8 6625 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6626 }
6627 else if (!hash)
906e58ca
NC		 6628 {
6629 /* It's a local symbol. */
6630 Elf_Internal_Sym *sym;
906e58ca
NC		 6631
6632 if (local_syms == NULL)
6633 {
6634 local_syms
6635 = (Elf_Internal_Sym *) symtab_hdr->contents;
6636 if (local_syms == NULL)
6637 local_syms
6638 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6639 symtab_hdr->sh_info, 0,
6640 NULL, NULL, NULL);
6641 if (local_syms == NULL)
6642 goto error_ret_free_internal;
6643 }
6644
6645 sym = local_syms + r_indx;
f6d250ce
TS		 6646 if (sym->st_shndx == SHN_UNDEF)
6647 sym_sec = bfd_und_section_ptr;
6648 else if (sym->st_shndx == SHN_ABS)
6649 sym_sec = bfd_abs_section_ptr;
6650 else if (sym->st_shndx == SHN_COMMON)
6651 sym_sec = bfd_com_section_ptr;
6652 else
6653 sym_sec =
6654 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6655
ffcb4889
NS		 6656 if (!sym_sec)
6657 /* This is an undefined symbol. It can never
6a631e86 6658 be resolved. */
ffcb4889 6659 continue;
fe33d2fa 6660
906e58ca
NC		 6661 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6662 sym_value = sym->st_value;
6663 destination = (sym_value + irela->r_addend
6664 + sym_sec->output_offset
6665 + sym_sec->output_section->vma);
34e77a92 6666 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6667 branch_type =
6668 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6669 sym_name
6670 = bfd_elf_string_from_elf_section (input_bfd,
6671 symtab_hdr->sh_link,
6672 sym->st_name);
906e58ca
NC		 6673 }
6674 else
6675 {
6676 /* It's an external symbol. */
906e58ca
NC		 6677 while (hash->root.root.type == bfd_link_hash_indirect
6678 || hash->root.root.type == bfd_link_hash_warning)
6679 hash = ((struct elf32_arm_link_hash_entry *)
6680 hash->root.root.u.i.link);
6681
6682 if (hash->root.root.type == bfd_link_hash_defined
6683 || hash->root.root.type == bfd_link_hash_defweak)
6684 {
6685 sym_sec = hash->root.root.u.def.section;
6686 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6687
6688 struct elf32_arm_link_hash_table *globals =
6689 elf32_arm_hash_table (info);
6690
6691 /* For a destination in a shared library,
6692 use the PLT stub as target address to
6693 decide whether a branch stub is
6694 needed. */
4dfe6ac6 6695 if (globals != NULL
362d30a1 6696 && globals->root.splt != NULL
4dfe6ac6 6697 && hash != NULL
022f8312
CL		 6698 && hash->root.plt.offset != (bfd_vma) -1)
6699 {
362d30a1 6700 sym_sec = globals->root.splt;
022f8312
CL		 6701 sym_value = hash->root.plt.offset;
6702 if (sym_sec->output_section != NULL)
6703 destination = (sym_value
6704 + sym_sec->output_offset
6705 + sym_sec->output_section->vma);
6706 }
6707 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6708 destination = (sym_value + irela->r_addend
6709 + sym_sec->output_offset
6710 + sym_sec->output_section->vma);
6711 }
69c5861e
CL		 6712 else if ((hash->root.root.type == bfd_link_hash_undefined)
6713 || (hash->root.root.type == bfd_link_hash_undefweak))
6714 {
6715 /* For a shared library, use the PLT stub as
6716 target address to decide whether a long
6717 branch stub is needed.
6718 For absolute code, they cannot be handled. */
6719 struct elf32_arm_link_hash_table *globals =
6720 elf32_arm_hash_table (info);
6721
4dfe6ac6 6722 if (globals != NULL
362d30a1 6723 && globals->root.splt != NULL
4dfe6ac6 6724 && hash != NULL
69c5861e
CL		 6725 && hash->root.plt.offset != (bfd_vma) -1)
6726 {
362d30a1 6727 sym_sec = globals->root.splt;
69c5861e
CL		 6728 sym_value = hash->root.plt.offset;
6729 if (sym_sec->output_section != NULL)
6730 destination = (sym_value
6731 + sym_sec->output_offset
6732 + sym_sec->output_section->vma);
6733 }
6734 else
6735 continue;
6736 }
906e58ca
NC		 6737 else
6738 {
6739 bfd_set_error (bfd_error_bad_value);
6740 goto error_ret_free_internal;
6741 }
34e77a92 6742 st_type = hash->root.type;
39d911fc
TP		 6743 branch_type =
6744 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6745 sym_name = hash->root.root.root.string;
906e58ca
NC		 6746 }
6747
48229727 6748 do
7413f23f 6749 {
b715f643 6750 bfd_boolean new_stub;
0955507f 6751 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6752
48229727
JB		 6753 /* Determine what (if any) linker stub is needed. */
6754 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6755 st_type, &branch_type,
6756 hash, destination, sym_sec,
48229727
JB		 6757 input_bfd, sym_name);
6758 if (stub_type == arm_stub_none)
6759 break;
6760
48229727
JB		 6761 /* We've either created a stub for this reloc already,
6762 or we are about to. */
0955507f 6763 stub_entry =
b715f643
TP		 6764 elf32_arm_create_stub (htab, stub_type, section, irela,
6765 sym_sec, hash,
6766 (char *) sym_name, sym_value,
6767 branch_type, &new_stub);
7413f23f 6768
0955507f 6769 created_stub = stub_entry != NULL;
b715f643
TP		 6770 if (!created_stub)
6771 goto error_ret_free_internal;
6772 else if (!new_stub)
6773 break;
99059e56 6774 else
b715f643 6775 stub_changed = TRUE;
99059e56
RM		 6776 }
6777 while (0);
6778
6779 /* Look for relocations which might trigger Cortex-A8
6780 erratum. */
6781 if (htab->fix_cortex_a8
6782 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6783 || r_type == (unsigned int) R_ARM_THM_JUMP19
6784 || r_type == (unsigned int) R_ARM_THM_CALL
6785 || r_type == (unsigned int) R_ARM_THM_XPC22))
6786 {
6787 bfd_vma from = section->output_section->vma
6788 + section->output_offset
6789 + irela->r_offset;
6790
6791 if ((from & 0xfff) == 0xffe)
6792 {
6793 /* Found a candidate. Note we haven't checked the
6794 destination is within 4K here: if we do so (and
6795 don't create an entry in a8_relocs) we can't tell
6796 that a branch should have been relocated when
6797 scanning later. */
6798 if (num_a8_relocs == a8_reloc_table_size)
6799 {
6800 a8_reloc_table_size *= 2;
6801 a8_relocs = (struct a8_erratum_reloc *)
6802 bfd_realloc (a8_relocs,
6803 sizeof (struct a8_erratum_reloc)
6804 * a8_reloc_table_size);
6805 }
6806
6807 a8_relocs[num_a8_relocs].from = from;
6808 a8_relocs[num_a8_relocs].destination = destination;
6809 a8_relocs[num_a8_relocs].r_type = r_type;
6810 a8_relocs[num_a8_relocs].branch_type = branch_type;
6811 a8_relocs[num_a8_relocs].sym_name = sym_name;
6812 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6813 a8_relocs[num_a8_relocs].hash = hash;
6814
6815 num_a8_relocs++;
6816 }
6817 }
906e58ca
NC		 6818 }
6819
99059e56
RM		 6820 /* We're done with the internal relocs, free them. */
6821 if (elf_section_data (section)->relocs == NULL)
6822 free (internal_relocs);
6823 }
48229727 6824
99059e56 6825 if (htab->fix_cortex_a8)
48229727 6826 {
99059e56
RM		 6827 /* Sort relocs which might apply to Cortex-A8 erratum. */
6828 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6829 sizeof (struct a8_erratum_reloc),
99059e56 6830 &a8_reloc_compare);
48229727 6831
99059e56
RM		 6832 /* Scan for branches which might trigger Cortex-A8 erratum. */
6833 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6834 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6835 a8_relocs, num_a8_relocs,
6836 prev_num_a8_fixes, &stub_changed)
6837 != 0)
48229727 6838 goto error_ret_free_local;
5e681ec4 6839 }
7f991970
AM		 6840
6841 if (local_syms != NULL
6842 && symtab_hdr->contents != (unsigned char *) local_syms)
6843 {
6844 if (!info->keep_memory)
6845 free (local_syms);
6846 else
6847 symtab_hdr->contents = (unsigned char *) local_syms;
6848 }
5e681ec4
PB		 6849 }
6850
0955507f
TP		 6851 if (first_veneer_scan
6852 && !set_cmse_veneer_addr_from_implib (info, htab,
6853 &cmse_stub_created))
6854 ret = FALSE;
6855
eb7c4339 6856 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6857 stub_changed = TRUE;
48229727 6858
906e58ca
NC		 6859 if (!stub_changed)
6860 break;
5e681ec4 6861
906e58ca
NC		 6862 /* OK, we've added some stubs. Find out the new size of the
6863 stub sections. */
6864 for (stub_sec = htab->stub_bfd->sections;
6865 stub_sec != NULL;
6866 stub_sec = stub_sec->next)
3e6b1042
DJ		 6867 {
6868 /* Ignore non-stub sections. */
6869 if (!strstr (stub_sec->name, STUB_SUFFIX))
6870 continue;
6871
6872 stub_sec->size = 0;
6873 }
b34b2d70 6874
0955507f
TP		 6875 /* Add new SG veneers after those already in the input import
6876 library. */
6877 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6878 stub_type++)
6879 {
6880 bfd_vma *start_offset_p;
6881 asection **stub_sec_p;
6882
6883 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6884 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6885 if (start_offset_p == NULL)
6886 continue;
6887
6888 BFD_ASSERT (stub_sec_p != NULL);
6889 if (*stub_sec_p != NULL)
6890 (*stub_sec_p)->size = *start_offset_p;
6891 }
6892
d7c5bd02 6893 /* Compute stub section size, considering padding. */
906e58ca 6894 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6895 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6896 stub_type++)
6897 {
6898 int size, padding;
6899 asection **stub_sec_p;
6900
6901 padding = arm_dedicated_stub_section_padding (stub_type);
6902 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6903 /* Skip if no stub input section or no stub section padding
6904 required. */
6905 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6906 continue;
6907 /* Stub section padding required but no dedicated section. */
6908 BFD_ASSERT (stub_sec_p);
6909
6910 size = (*stub_sec_p)->size;
6911 size = (size + padding - 1) & ~(padding - 1);
6912 (*stub_sec_p)->size = size;
6913 }
906e58ca 6914
48229727
JB		 6915 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6916 if (htab->fix_cortex_a8)
99059e56
RM		 6917 for (i = 0; i < num_a8_fixes; i++)
6918 {
48229727 6919 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6920 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6921
6922 if (stub_sec == NULL)
7f991970 6923 return FALSE;
48229727 6924
99059e56
RM		 6925 stub_sec->size
6926 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6927 NULL);
6928 }
48229727
JB		 6929
6930
906e58ca
NC		 6931 /* Ask the linker to do its stuff. */
6932 (*htab->layout_sections_again) ();
4ba2ef8f 6933 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6934 }
6935
48229727
JB		 6936 /* Add stubs for Cortex-A8 erratum fixes now. */
6937 if (htab->fix_cortex_a8)
6938 {
6939 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6940 {
6941 struct elf32_arm_stub_hash_entry *stub_entry;
6942 char *stub_name = a8_fixes[i].stub_name;
6943 asection *section = a8_fixes[i].section;
6944 unsigned int section_id = a8_fixes[i].section->id;
6945 asection *link_sec = htab->stub_group[section_id].link_sec;
6946 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6947 const insn_sequence *template_sequence;
6948 int template_size, size = 0;
6949
6950 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6951 TRUE, FALSE);
6952 if (stub_entry == NULL)
6953 {
871b3ab2 6954 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6955 section->owner, stub_name);
99059e56
RM		 6956 return FALSE;
6957 }
6958
6959 stub_entry->stub_sec = stub_sec;
0955507f 6960 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6961 stub_entry->id_sec = link_sec;
6962 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6963 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6964 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6965 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6966 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6967 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6968
99059e56
RM		 6969 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6970 &template_sequence,
6971 &template_size);
48229727 6972
99059e56
RM		 6973 stub_entry->stub_size = size;
6974 stub_entry->stub_template = template_sequence;
6975 stub_entry->stub_template_size = template_size;
6976 }
48229727
JB		 6977
6978 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6979 elf32_arm_write_section(). */
48229727
JB		 6980 htab->a8_erratum_fixes = a8_fixes;
6981 htab->num_a8_erratum_fixes = num_a8_fixes;
6982 }
6983 else
6984 {
6985 htab->a8_erratum_fixes = NULL;
6986 htab->num_a8_erratum_fixes = 0;
6987 }
0955507f 6988 return ret;
5e681ec4
PB		 6989}
6990
906e58ca
NC		 6991/* Build all the stubs associated with the current output file. The
6992 stubs are kept in a hash table attached to the main linker hash
6993 table. We also set up the .plt entries for statically linked PIC
6994 functions here. This function is called via arm_elf_finish in the
6995 linker. */
252b5132 6996
906e58ca
NC		 6997bfd_boolean
6998elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6999{
906e58ca
NC		 7000 asection *stub_sec;
7001 struct bfd_hash_table *table;
0955507f 7002 enum elf32_arm_stub_type stub_type;
906e58ca 7003 struct elf32_arm_link_hash_table *htab;
252b5132 7004
906e58ca 7005 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 7006 if (htab == NULL)
7007 return FALSE;
252b5132 7008
906e58ca
NC		 7009 for (stub_sec = htab->stub_bfd->sections;
7010 stub_sec != NULL;
7011 stub_sec = stub_sec->next)
252b5132 7012 {
906e58ca
NC		 7013 bfd_size_type size;
7014
8029a119 7015 /* Ignore non-stub sections. */
906e58ca
NC		 7016 if (!strstr (stub_sec->name, STUB_SUFFIX))
7017 continue;
7018
d7c5bd02 7019 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 7020 must at least be done for stub section requiring padding and for SG
7021 veneers to ensure that a non secure code branching to a removed SG
7022 veneer causes an error. */
906e58ca 7023 size = stub_sec->size;
21d799b5 7024 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 7025 if (stub_sec->contents == NULL && size != 0)
7026 return FALSE;
0955507f 7027
906e58ca 7028 stub_sec->size = 0;
252b5132
RH		 7029 }
7030
0955507f
TP		 7031 /* Add new SG veneers after those already in the input import library. */
7032 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7033 {
7034 bfd_vma *start_offset_p;
7035 asection **stub_sec_p;
7036
7037 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
7038 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
7039 if (start_offset_p == NULL)
7040 continue;
7041
7042 BFD_ASSERT (stub_sec_p != NULL);
7043 if (*stub_sec_p != NULL)
7044 (*stub_sec_p)->size = *start_offset_p;
7045 }
7046
906e58ca
NC		 7047 /* Build the stubs as directed by the stub hash table. */
7048 table = &htab->stub_hash_table;
7049 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7050 if (htab->fix_cortex_a8)
7051 {
7052 /* Place the cortex a8 stubs last. */
7053 htab->fix_cortex_a8 = -1;
7054 bfd_hash_traverse (table, arm_build_one_stub, info);
7055 }
252b5132 7056
906e58ca 7057 return TRUE;
252b5132
RH		 7058}
7059
9b485d32
NC		 7060/* Locate the Thumb encoded calling stub for NAME. */
7061
252b5132 7062static struct elf_link_hash_entry *
57e8b36a
NC		 7063find_thumb_glue (struct bfd_link_info *link_info,
7064 const char *name,
f2a9dd69 7065 char **error_message)
252b5132
RH		 7066{
7067 char *tmp_name;
7068 struct elf_link_hash_entry *hash;
7069 struct elf32_arm_link_hash_table *hash_table;
7070
7071 /* We need a pointer to the armelf specific hash table. */
7072 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7073 if (hash_table == NULL)
7074 return NULL;
252b5132 7075
21d799b5 7076 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7077 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7078
7079 BFD_ASSERT (tmp_name);
7080
7081 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7082
7083 hash = elf_link_hash_lookup
b34976b6 7084 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7085
b1657152 7086 if (hash == NULL
90b6238f
AM		 7087 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7088 "Thumb", tmp_name, name) == -1)
b1657152 7089 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7090
7091 free (tmp_name);
7092
7093 return hash;
7094}
7095
9b485d32
NC		 7096/* Locate the ARM encoded calling stub for NAME. */
7097
252b5132 7098static struct elf_link_hash_entry *
57e8b36a
NC		 7099find_arm_glue (struct bfd_link_info *link_info,
7100 const char *name,
f2a9dd69 7101 char **error_message)
252b5132
RH		 7102{
7103 char *tmp_name;
7104 struct elf_link_hash_entry *myh;
7105 struct elf32_arm_link_hash_table *hash_table;
7106
7107 /* We need a pointer to the elfarm specific hash table. */
7108 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7109 if (hash_table == NULL)
7110 return NULL;
252b5132 7111
21d799b5 7112 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7113 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7114 BFD_ASSERT (tmp_name);
7115
7116 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7117
7118 myh = elf_link_hash_lookup
b34976b6 7119 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7120
b1657152 7121 if (myh == NULL
90b6238f
AM		 7122 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7123 "ARM", tmp_name, name) == -1)
b1657152 7124 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7125
7126 free (tmp_name);
7127
7128 return myh;
7129}
7130
8f6277f5 7131/* ARM->Thumb glue (static images):
252b5132
RH		 7132
7133 .arm
7134 __func_from_arm:
7135 ldr r12, __func_addr
7136 bx r12
7137 __func_addr:
906e58ca 7138 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7139
26079076
PB		 7140 (v5t static images)
7141 .arm
7142 __func_from_arm:
7143 ldr pc, __func_addr
7144 __func_addr:
906e58ca 7145 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7146
8f6277f5
PB		 7147 (relocatable images)
7148 .arm
7149 __func_from_arm:
7150 ldr r12, __func_offset
7151 add r12, r12, pc
7152 bx r12
7153 __func_offset:
8029a119 7154 .word func - . */
8f6277f5
PB		 7155
7156#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7157static const insn32 a2t1_ldr_insn = 0xe59fc000;
7158static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7159static const insn32 a2t3_func_addr_insn = 0x00000001;
7160
26079076
PB		 7161#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7162static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7163static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7164
8f6277f5
PB		 7165#define ARM2THUMB_PIC_GLUE_SIZE 16
7166static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7167static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7168static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7169
07d6d2b8 7170/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7171
07d6d2b8
AM		 7172 .thumb .thumb
7173 .align 2 .align 2
7174 __func_from_thumb: __func_from_thumb:
7175 bx pc push {r6, lr}
7176 nop ldr r6, __func_addr
7177 .arm mov lr, pc
7178 b func bx r6
99059e56
RM		 7179 .arm
7180 ;; back_to_thumb
7181 ldmia r13! {r6, lr}
7182 bx lr
7183 __func_addr:
07d6d2b8 7184 .word func */
252b5132
RH		 7185
7186#define THUMB2ARM_GLUE_SIZE 8
7187static const insn16 t2a1_bx_pc_insn = 0x4778;
7188static const insn16 t2a2_noop_insn = 0x46c0;
7189static const insn32 t2a3_b_insn = 0xea000000;
7190
c7b8f16e 7191#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7192#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7193#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7194
845b51d6
PB		 7195#define ARM_BX_VENEER_SIZE 12
7196static const insn32 armbx1_tst_insn = 0xe3100001;
7197static const insn32 armbx2_moveq_insn = 0x01a0f000;
7198static const insn32 armbx3_bx_insn = 0xe12fff10;
7199
7e392df6 7200#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7201static void
7202arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7203{
7204 asection * s;
8029a119 7205 bfd_byte * contents;
252b5132 7206
8029a119 7207 if (size == 0)
3e6b1042
DJ		 7208 {
7209 /* Do not include empty glue sections in the output. */
7210 if (abfd != NULL)
7211 {
3d4d4302 7212 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7213 if (s != NULL)
7214 s->flags |= SEC_EXCLUDE;
7215 }
7216 return;
7217 }
252b5132 7218
8029a119 7219 BFD_ASSERT (abfd != NULL);
252b5132 7220
3d4d4302 7221 s = bfd_get_linker_section (abfd, name);
8029a119 7222 BFD_ASSERT (s != NULL);
252b5132 7223
b0f4fbf8 7224 contents = (bfd_byte *) bfd_zalloc (abfd, size);
252b5132 7225
8029a119
NC		 7226 BFD_ASSERT (s->size == size);
7227 s->contents = contents;
7228}
906e58ca 7229
8029a119
NC		 7230bfd_boolean
7231bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7232{
7233 struct elf32_arm_link_hash_table * globals;
906e58ca 7234
8029a119
NC		 7235 globals = elf32_arm_hash_table (info);
7236 BFD_ASSERT (globals != NULL);
906e58ca 7237
8029a119
NC		 7238 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7239 globals->arm_glue_size,
7240 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7241
8029a119
NC		 7242 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7243 globals->thumb_glue_size,
7244 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7245
8029a119
NC		 7246 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7247 globals->vfp11_erratum_glue_size,
7248 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7249
a504d23a
LA		 7250 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7251 globals->stm32l4xx_erratum_glue_size,
7252 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7253
8029a119
NC		 7254 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7255 globals->bx_glue_size,
845b51d6
PB		 7256 ARM_BX_GLUE_SECTION_NAME);
7257
b34976b6 7258 return TRUE;
252b5132
RH		 7259}
7260
a4fd1a8e 7261/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7262 returns the symbol identifying the stub. */
7263
a4fd1a8e 7264static struct elf_link_hash_entry *
57e8b36a
NC		 7265record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7266 struct elf_link_hash_entry * h)
252b5132
RH		 7267{
7268 const char * name = h->root.root.string;
63b0f745 7269 asection * s;
252b5132
RH		 7270 char * tmp_name;
7271 struct elf_link_hash_entry * myh;
14a793b2 7272 struct bfd_link_hash_entry * bh;
252b5132 7273 struct elf32_arm_link_hash_table * globals;
dc810e39 7274 bfd_vma val;
2f475487 7275 bfd_size_type size;
252b5132
RH		 7276
7277 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7278 BFD_ASSERT (globals != NULL);
7279 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7280
3d4d4302 7281 s = bfd_get_linker_section
252b5132
RH		 7282 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7283
252b5132
RH		 7284 BFD_ASSERT (s != NULL);
7285
21d799b5 7286 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7287 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7288 BFD_ASSERT (tmp_name);
7289
7290 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7291
7292 myh = elf_link_hash_lookup
b34976b6 7293 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7294
7295 if (myh != NULL)
7296 {
9b485d32 7297 /* We've already seen this guy. */
252b5132 7298 free (tmp_name);
a4fd1a8e 7299 return myh;
252b5132
RH		 7300 }
7301
57e8b36a
NC		 7302 /* The only trick here is using hash_table->arm_glue_size as the value.
7303 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7304 putting it. The +1 on the value marks that the stub has not been
7305 output yet - not that it is a Thumb function. */
14a793b2 7306 bh = NULL;
dc810e39
AM		 7307 val = globals->arm_glue_size + 1;
7308 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7309 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7310 NULL, TRUE, FALSE, &bh);
252b5132 7311
b7693d02
DJ		 7312 myh = (struct elf_link_hash_entry *) bh;
7313 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7314 myh->forced_local = 1;
7315
252b5132
RH		 7316 free (tmp_name);
7317
0e1862bb
L		 7318 if (bfd_link_pic (link_info)
7319 || globals->root.is_relocatable_executable
27e55c4d 7320 || globals->pic_veneer)
2f475487 7321 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7322 else if (globals->use_blx)
7323 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7324 else
2f475487
AM		 7325 size = ARM2THUMB_STATIC_GLUE_SIZE;
7326
7327 s->size += size;
7328 globals->arm_glue_size += size;
252b5132 7329
a4fd1a8e 7330 return myh;
252b5132
RH		 7331}
7332
845b51d6
PB		 7333/* Allocate space for ARMv4 BX veneers. */
7334
7335static void
7336record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7337{
7338 asection * s;
7339 struct elf32_arm_link_hash_table *globals;
7340 char *tmp_name;
7341 struct elf_link_hash_entry *myh;
7342 struct bfd_link_hash_entry *bh;
7343 bfd_vma val;
7344
7345 /* BX PC does not need a veneer. */
7346 if (reg == 15)
7347 return;
7348
7349 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7350 BFD_ASSERT (globals != NULL);
7351 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7352
7353 /* Check if this veneer has already been allocated. */
7354 if (globals->bx_glue_offset[reg])
7355 return;
7356
3d4d4302 7357 s = bfd_get_linker_section
845b51d6
PB		 7358 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7359
7360 BFD_ASSERT (s != NULL);
7361
7362 /* Add symbol for veneer. */
21d799b5
NC		 7363 tmp_name = (char *)
7364 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
845b51d6 7365 BFD_ASSERT (tmp_name);
906e58ca 7366
845b51d6 7367 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7368
845b51d6
PB		 7369 myh = elf_link_hash_lookup
7370 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7371
845b51d6 7372 BFD_ASSERT (myh == NULL);
906e58ca 7373
845b51d6
PB		 7374 bh = NULL;
7375 val = globals->bx_glue_size;
7376 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7377 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7378 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7379
7380 myh = (struct elf_link_hash_entry *) bh;
7381 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7382 myh->forced_local = 1;
7383
7384 s->size += ARM_BX_VENEER_SIZE;
7385 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7386 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7387}
7388
7389
c7b8f16e
JB		 7390/* Add an entry to the code/data map for section SEC. */
7391
7392static void
7393elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7394{
7395 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7396 unsigned int newidx;
906e58ca 7397
c7b8f16e
JB		 7398 if (sec_data->map == NULL)
7399 {
21d799b5 7400 sec_data->map = (elf32_arm_section_map *)
99059e56 7401 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7402 sec_data->mapcount = 0;
7403 sec_data->mapsize = 1;
7404 }
906e58ca 7405
c7b8f16e 7406 newidx = sec_data->mapcount++;
906e58ca 7407
c7b8f16e
JB		 7408 if (sec_data->mapcount > sec_data->mapsize)
7409 {
7410 sec_data->mapsize *= 2;
21d799b5 7411 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7412 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7413 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7414 }
7415
7416 if (sec_data->map)
7417 {
7418 sec_data->map[newidx].vma = vma;
7419 sec_data->map[newidx].type = type;
c7b8f16e 7420 }
c7b8f16e
JB		 7421}
7422
7423
7424/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7425 veneers are handled for now. */
7426
7427static bfd_vma
7428record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7429 elf32_vfp11_erratum_list *branch,
7430 bfd *branch_bfd,
7431 asection *branch_sec,
7432 unsigned int offset)
c7b8f16e
JB		 7433{
7434 asection *s;
7435 struct elf32_arm_link_hash_table *hash_table;
7436 char *tmp_name;
7437 struct elf_link_hash_entry *myh;
7438 struct bfd_link_hash_entry *bh;
7439 bfd_vma val;
7440 struct _arm_elf_section_data *sec_data;
c7b8f16e 7441 elf32_vfp11_erratum_list *newerr;
906e58ca 7442
c7b8f16e 7443 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7444 BFD_ASSERT (hash_table != NULL);
7445 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7446
3d4d4302 7447 s = bfd_get_linker_section
c7b8f16e 7448 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7449
c7b8f16e 7450 sec_data = elf32_arm_section_data (s);
906e58ca 7451
c7b8f16e 7452 BFD_ASSERT (s != NULL);
906e58ca 7453
21d799b5 7454 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7455 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e 7456 BFD_ASSERT (tmp_name);
906e58ca 7457
c7b8f16e
JB		 7458 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7459 hash_table->num_vfp11_fixes);
906e58ca 7460
c7b8f16e
JB		 7461 myh = elf_link_hash_lookup
7462 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7463
c7b8f16e 7464 BFD_ASSERT (myh == NULL);
906e58ca 7465
c7b8f16e
JB		 7466 bh = NULL;
7467 val = hash_table->vfp11_erratum_glue_size;
7468 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7469 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7470 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7471
7472 myh = (struct elf_link_hash_entry *) bh;
7473 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7474 myh->forced_local = 1;
7475
7476 /* Link veneer back to calling location. */
c7e2358a 7477 sec_data->erratumcount += 1;
21d799b5
NC		 7478 newerr = (elf32_vfp11_erratum_list *)
7479 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7480
c7b8f16e
JB		 7481 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7482 newerr->vma = -1;
7483 newerr->u.v.branch = branch;
7484 newerr->u.v.id = hash_table->num_vfp11_fixes;
7485 branch->u.b.veneer = newerr;
7486
7487 newerr->next = sec_data->erratumlist;
7488 sec_data->erratumlist = newerr;
7489
7490 /* A symbol for the return from the veneer. */
7491 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7492 hash_table->num_vfp11_fixes);
7493
7494 myh = elf_link_hash_lookup
7495 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7496
c7b8f16e
JB		 7497 if (myh != NULL)
7498 abort ();
7499
7500 bh = NULL;
7501 val = offset + 4;
7502 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7503 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7504
c7b8f16e
JB		 7505 myh = (struct elf_link_hash_entry *) bh;
7506 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7507 myh->forced_local = 1;
7508
7509 free (tmp_name);
906e58ca 7510
c7b8f16e
JB		 7511 /* Generate a mapping symbol for the veneer section, and explicitly add an
7512 entry for that symbol to the code/data map for the section. */
7513 if (hash_table->vfp11_erratum_glue_size == 0)
7514 {
7515 bh = NULL;
7516 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7517 ever requires this erratum fix. */
c7b8f16e
JB		 7518 _bfd_generic_link_add_one_symbol (link_info,
7519 hash_table->bfd_of_glue_owner, "$a",
7520 BSF_LOCAL, s, 0, NULL,
99059e56 7521 TRUE, FALSE, &bh);
c7b8f16e
JB		 7522
7523 myh = (struct elf_link_hash_entry *) bh;
7524 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7525 myh->forced_local = 1;
906e58ca 7526
c7b8f16e 7527 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7528 BFDs. We must make a note of this generated mapping symbol
7529 ourselves so that code byteswapping works properly in
7530 elf32_arm_write_section. */
c7b8f16e
JB		 7531 elf32_arm_section_map_add (s, 'a', 0);
7532 }
906e58ca 7533
c7b8f16e
JB		 7534 s->size += VFP11_ERRATUM_VENEER_SIZE;
7535 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7536 hash_table->num_vfp11_fixes++;
906e58ca 7537
c7b8f16e
JB		 7538 /* The offset of the veneer. */
7539 return val;
7540}
7541
a504d23a
LA		 7542/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7543 veneers need to be handled because used only in Cortex-M. */
7544
7545static bfd_vma
7546record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7547 elf32_stm32l4xx_erratum_list *branch,
7548 bfd *branch_bfd,
7549 asection *branch_sec,
7550 unsigned int offset,
7551 bfd_size_type veneer_size)
7552{
7553 asection *s;
7554 struct elf32_arm_link_hash_table *hash_table;
7555 char *tmp_name;
7556 struct elf_link_hash_entry *myh;
7557 struct bfd_link_hash_entry *bh;
7558 bfd_vma val;
7559 struct _arm_elf_section_data *sec_data;
7560 elf32_stm32l4xx_erratum_list *newerr;
7561
7562 hash_table = elf32_arm_hash_table (link_info);
7563 BFD_ASSERT (hash_table != NULL);
7564 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7565
7566 s = bfd_get_linker_section
7567 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7568
7569 BFD_ASSERT (s != NULL);
7570
7571 sec_data = elf32_arm_section_data (s);
7572
7573 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7574 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
a504d23a
LA		 7575 BFD_ASSERT (tmp_name);
7576
7577 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7578 hash_table->num_stm32l4xx_fixes);
7579
7580 myh = elf_link_hash_lookup
7581 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7582
7583 BFD_ASSERT (myh == NULL);
7584
7585 bh = NULL;
7586 val = hash_table->stm32l4xx_erratum_glue_size;
7587 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7588 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7589 NULL, TRUE, FALSE, &bh);
7590
7591 myh = (struct elf_link_hash_entry *) bh;
7592 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7593 myh->forced_local = 1;
7594
7595 /* Link veneer back to calling location. */
7596 sec_data->stm32l4xx_erratumcount += 1;
7597 newerr = (elf32_stm32l4xx_erratum_list *)
7598 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7599
7600 newerr->type = STM32L4XX_ERRATUM_VENEER;
7601 newerr->vma = -1;
7602 newerr->u.v.branch = branch;
7603 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7604 branch->u.b.veneer = newerr;
7605
7606 newerr->next = sec_data->stm32l4xx_erratumlist;
7607 sec_data->stm32l4xx_erratumlist = newerr;
7608
7609 /* A symbol for the return from the veneer. */
7610 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7611 hash_table->num_stm32l4xx_fixes);
7612
7613 myh = elf_link_hash_lookup
7614 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7615
7616 if (myh != NULL)
7617 abort ();
7618
7619 bh = NULL;
7620 val = offset + 4;
7621 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7622 branch_sec, val, NULL, TRUE, FALSE, &bh);
7623
7624 myh = (struct elf_link_hash_entry *) bh;
7625 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7626 myh->forced_local = 1;
7627
7628 free (tmp_name);
7629
7630 /* Generate a mapping symbol for the veneer section, and explicitly add an
7631 entry for that symbol to the code/data map for the section. */
7632 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7633 {
7634 bh = NULL;
7635 /* Creates a THUMB symbol since there is no other choice. */
7636 _bfd_generic_link_add_one_symbol (link_info,
7637 hash_table->bfd_of_glue_owner, "$t",
7638 BSF_LOCAL, s, 0, NULL,
7639 TRUE, FALSE, &bh);
7640
7641 myh = (struct elf_link_hash_entry *) bh;
7642 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7643 myh->forced_local = 1;
7644
7645 /* The elf32_arm_init_maps function only cares about symbols from input
7646 BFDs. We must make a note of this generated mapping symbol
7647 ourselves so that code byteswapping works properly in
7648 elf32_arm_write_section. */
7649 elf32_arm_section_map_add (s, 't', 0);
7650 }
7651
7652 s->size += veneer_size;
7653 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7654 hash_table->num_stm32l4xx_fixes++;
7655
7656 /* The offset of the veneer. */
7657 return val;
7658}
7659
8029a119 7660#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7661 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7662 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7663
7664/* Create a fake section for use by the ARM backend of the linker. */
7665
7666static bfd_boolean
7667arm_make_glue_section (bfd * abfd, const char * name)
7668{
7669 asection * sec;
7670
3d4d4302 7671 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7672 if (sec != NULL)
7673 /* Already made. */
7674 return TRUE;
7675
3d4d4302 7676 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7677
7678 if (sec == NULL
fd361982 7679 || !bfd_set_section_alignment (sec, 2))
8029a119
NC		 7680 return FALSE;
7681
7682 /* Set the gc mark to prevent the section from being removed by garbage
7683 collection, despite the fact that no relocs refer to this section. */
7684 sec->gc_mark = 1;
7685
7686 return TRUE;
7687}
7688
1db37fe6
YG		 7689/* Set size of .plt entries. This function is called from the
7690 linker scripts in ld/emultempl/{armelf}.em. */
7691
7692void
7693bfd_elf32_arm_use_long_plt (void)
7694{
7695 elf32_arm_use_long_plt_entry = TRUE;
7696}
7697
8afb0e02
NC		 7698/* Add the glue sections to ABFD. This function is called from the
7699 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7700
b34976b6 7701bfd_boolean
57e8b36a
NC		 7702bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7703 struct bfd_link_info *info)
252b5132 7704{
a504d23a
LA		 7705 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7706 bfd_boolean dostm32l4xx = globals
7707 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7708 bfd_boolean addglue;
7709
8afb0e02
NC		 7710 /* If we are only performing a partial
7711 link do not bother adding the glue. */
0e1862bb 7712 if (bfd_link_relocatable (info))
b34976b6 7713 return TRUE;
252b5132 7714
a504d23a 7715 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7716 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7717 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7718 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7719
7720 if (!dostm32l4xx)
7721 return addglue;
7722
7723 return addglue
7724 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7725}
7726
daa4adae
TP		 7727/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7728 ensures they are not marked for deletion by
7729 strip_excluded_output_sections () when veneers are going to be created
7730 later. Not doing so would trigger assert on empty section size in
7731 lang_size_sections_1 (). */
7732
7733void
7734bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7735{
7736 enum elf32_arm_stub_type stub_type;
7737
7738 /* If we are only performing a partial
7739 link do not bother adding the glue. */
7740 if (bfd_link_relocatable (info))
7741 return;
7742
7743 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7744 {
7745 asection *out_sec;
7746 const char *out_sec_name;
7747
7748 if (!arm_dedicated_stub_output_section_required (stub_type))
7749 continue;
7750
7751 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7752 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7753 if (out_sec != NULL)
7754 out_sec->flags |= SEC_KEEP;
7755 }
7756}
7757
8afb0e02
NC		 7758/* Select a BFD to be used to hold the sections used by the glue code.
7759 This function is called from the linker scripts in ld/emultempl/
8029a119 7760 {armelf/pe}.em. */
8afb0e02 7761
b34976b6 7762bfd_boolean
57e8b36a 7763bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7764{
7765 struct elf32_arm_link_hash_table *globals;
7766
7767 /* If we are only performing a partial link
7768 do not bother getting a bfd to hold the glue. */
0e1862bb 7769 if (bfd_link_relocatable (info))
b34976b6 7770 return TRUE;
8afb0e02 7771
b7693d02
DJ		 7772 /* Make sure we don't attach the glue sections to a dynamic object. */
7773 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7774
8afb0e02 7775 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7776 BFD_ASSERT (globals != NULL);
7777
7778 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7779 return TRUE;
8afb0e02 7780
252b5132
RH		 7781 /* Save the bfd for later use. */
7782 globals->bfd_of_glue_owner = abfd;
cedb70c5 7783
b34976b6 7784 return TRUE;
252b5132
RH		 7785}
7786
906e58ca
NC		 7787static void
7788check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7789{
2de70689
MGD		 7790 int cpu_arch;
7791
b38cadfb 7792 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7793 Tag_CPU_arch);
7794
7795 if (globals->fix_arm1176)
7796 {
7797 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7798 globals->use_blx = 1;
7799 }
7800 else
7801 {
7802 if (cpu_arch > TAG_CPU_ARCH_V4T)
7803 globals->use_blx = 1;
7804 }
39b41c9c
PB		 7805}
7806
b34976b6 7807bfd_boolean
57e8b36a 7808bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7809 struct bfd_link_info *link_info)
252b5132
RH		 7810{
7811 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7812 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7813 Elf_Internal_Rela *irel, *irelend;
7814 bfd_byte *contents = NULL;
252b5132
RH		 7815
7816 asection *sec;
7817 struct elf32_arm_link_hash_table *globals;
7818
7819 /* If we are only performing a partial link do not bother
7820 to construct any glue. */
0e1862bb 7821 if (bfd_link_relocatable (link_info))
b34976b6 7822 return TRUE;
252b5132 7823
39ce1a6a
NC		 7824 /* Here we have a bfd that is to be included on the link. We have a
7825 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7826 globals = elf32_arm_hash_table (link_info);
252b5132 7827 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7828
7829 check_use_blx (globals);
252b5132 7830
d504ffc8 7831 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7832 {
90b6238f 7833 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7834 abfd);
e489d0ae
PB		 7835 return FALSE;
7836 }
f21f3fe0 7837
39ce1a6a
NC		 7838 /* PR 5398: If we have not decided to include any loadable sections in
7839 the output then we will not have a glue owner bfd. This is OK, it
7840 just means that there is nothing else for us to do here. */
7841 if (globals->bfd_of_glue_owner == NULL)
7842 return TRUE;
7843
252b5132
RH		 7844 /* Rummage around all the relocs and map the glue vectors. */
7845 sec = abfd->sections;
7846
7847 if (sec == NULL)
b34976b6 7848 return TRUE;
252b5132
RH		 7849
7850 for (; sec != NULL; sec = sec->next)
7851 {
7852 if (sec->reloc_count == 0)
7853 continue;
7854
2f475487
AM		 7855 if ((sec->flags & SEC_EXCLUDE) != 0)
7856 continue;
7857
0ffa91dd 7858 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7859
9b485d32 7860 /* Load the relocs. */
6cdc0ccc 7861 internal_relocs
906e58ca 7862 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7863
6cdc0ccc
AM		 7864 if (internal_relocs == NULL)
7865 goto error_return;
252b5132 7866
6cdc0ccc
AM		 7867 irelend = internal_relocs + sec->reloc_count;
7868 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7869 {
7870 long r_type;
7871 unsigned long r_index;
252b5132
RH		 7872
7873 struct elf_link_hash_entry *h;
7874
7875 r_type = ELF32_R_TYPE (irel->r_info);
7876 r_index = ELF32_R_SYM (irel->r_info);
7877
9b485d32 7878 /* These are the only relocation types we care about. */
ba96a88f 7879 if ( r_type != R_ARM_PC24
845b51d6 7880 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7881 continue;
7882
7883 /* Get the section contents if we haven't done so already. */
7884 if (contents == NULL)
7885 {
7886 /* Get cached copy if it exists. */
7887 if (elf_section_data (sec)->this_hdr.contents != NULL)
7888 contents = elf_section_data (sec)->this_hdr.contents;
7889 else
7890 {
7891 /* Go get them off disk. */
57e8b36a 7892 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7893 goto error_return;
7894 }
7895 }
7896
845b51d6
PB		 7897 if (r_type == R_ARM_V4BX)
7898 {
7899 int reg;
7900
7901 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7902 record_arm_bx_glue (link_info, reg);
7903 continue;
7904 }
7905
a7c10850 7906 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7907 h = NULL;
7908
9b485d32 7909 /* We don't care about local symbols. */
252b5132
RH		 7910 if (r_index < symtab_hdr->sh_info)
7911 continue;
7912
9b485d32 7913 /* This is an external symbol. */
252b5132
RH		 7914 r_index -= symtab_hdr->sh_info;
7915 h = (struct elf_link_hash_entry *)
7916 elf_sym_hashes (abfd)[r_index];
7917
7918 /* If the relocation is against a static symbol it must be within
7919 the current section and so cannot be a cross ARM/Thumb relocation. */
7920 if (h == NULL)
7921 continue;
7922
d504ffc8
DJ		 7923 /* If the call will go through a PLT entry then we do not need
7924 glue. */
362d30a1 7925 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7926 continue;
7927
252b5132
RH		 7928 switch (r_type)
7929 {
7930 case R_ARM_PC24:
7931 /* This one is a call from arm code. We need to look up
99059e56
RM		 7932 the target of the call. If it is a thumb target, we
7933 insert glue. */
39d911fc
TP		 7934 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7935 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7936 record_arm_to_thumb_glue (link_info, h);
7937 break;
7938
252b5132 7939 default:
c6596c5e 7940 abort ();
252b5132
RH		 7941 }
7942 }
6cdc0ccc 7943
c9594989 7944 if (elf_section_data (sec)->this_hdr.contents != contents)
6cdc0ccc
AM		 7945 free (contents);
7946 contents = NULL;
7947
c9594989 7948 if (elf_section_data (sec)->relocs != internal_relocs)
6cdc0ccc
AM		 7949 free (internal_relocs);
7950 internal_relocs = NULL;
252b5132
RH		 7951 }
7952
b34976b6 7953 return TRUE;
9a5aca8c 7954
dc1e8a47 7955 error_return:
c9594989 7956 if (elf_section_data (sec)->this_hdr.contents != contents)
6cdc0ccc 7957 free (contents);
c9594989 7958 if (elf_section_data (sec)->relocs != internal_relocs)
6cdc0ccc 7959 free (internal_relocs);
9a5aca8c 7960
b34976b6 7961 return FALSE;
252b5132 7962}
7e392df6 7963#endif
252b5132 7964
eb043451 7965
c7b8f16e
JB		 7966/* Initialise maps of ARM/Thumb/data for input BFDs. */
7967
7968void
7969bfd_elf32_arm_init_maps (bfd *abfd)
7970{
7971 Elf_Internal_Sym *isymbuf;
7972 Elf_Internal_Shdr *hdr;
7973 unsigned int i, localsyms;
7974
af1f4419
NC		 7975 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7976 if (! is_arm_elf (abfd))
7977 return;
7978
c7b8f16e
JB		 7979 if ((abfd->flags & DYNAMIC) != 0)
7980 return;
7981
0ffa91dd 7982 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7983 localsyms = hdr->sh_info;
7984
7985 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7986 should contain the number of local symbols, which should come before any
7987 global symbols. Mapping symbols are always local. */
7988 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7989 NULL);
7990
7991 /* No internal symbols read? Skip this BFD. */
7992 if (isymbuf == NULL)
7993 return;
7994
7995 for (i = 0; i < localsyms; i++)
7996 {
7997 Elf_Internal_Sym *isym = &isymbuf[i];
7998 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7999 const char *name;
906e58ca 8000
c7b8f16e 8001 if (sec != NULL
99059e56
RM		 8002 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
8003 {
8004 name = bfd_elf_string_from_elf_section (abfd,
8005 hdr->sh_link, isym->st_name);
906e58ca 8006
99059e56 8007 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 8008 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 8009 elf32_arm_section_map_add (sec, name[1], isym->st_value);
8010 }
c7b8f16e
JB		 8011 }
8012}
8013
8014
48229727
JB		 8015/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8016 say what they wanted. */
8017
8018void
8019bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
8020{
8021 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8022 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8023
4dfe6ac6
NC		 8024 if (globals == NULL)
8025 return;
8026
48229727
JB		 8027 if (globals->fix_cortex_a8 == -1)
8028 {
8029 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8030 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
8031 && (out_attr[Tag_CPU_arch_profile].i == 'A'
8032 || out_attr[Tag_CPU_arch_profile].i == 0))
8033 globals->fix_cortex_a8 = 1;
8034 else
8035 globals->fix_cortex_a8 = 0;
8036 }
8037}
8038
8039
c7b8f16e
JB		 8040void
8041bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8042{
8043 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8044 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8045
4dfe6ac6
NC		 8046 if (globals == NULL)
8047 return;
c7b8f16e
JB		 8048 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8049 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8050 {
8051 switch (globals->vfp11_fix)
99059e56
RM		 8052 {
8053 case BFD_ARM_VFP11_FIX_DEFAULT:
8054 case BFD_ARM_VFP11_FIX_NONE:
8055 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8056 break;
8057
8058 default:
8059 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8060 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8061 "workaround is not necessary for target architecture"), obfd);
8062 }
c7b8f16e
JB		 8063 }
8064 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8065 /* For earlier architectures, we might need the workaround, but do not
8066 enable it by default. If users is running with broken hardware, they
8067 must enable the erratum fix explicitly. */
8068 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8069}
8070
a504d23a
LA		 8071void
8072bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8073{
8074 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8075 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8076
8077 if (globals == NULL)
8078 return;
8079
8080 /* We assume only Cortex-M4 may require the fix. */
8081 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8082 || out_attr[Tag_CPU_arch_profile].i != 'M')
8083 {
8084 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8085 /* Give a warning, but do as the user requests anyway. */
4eca0228 8086 _bfd_error_handler
871b3ab2 8087 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8088 "workaround is not necessary for target architecture"), obfd);
8089 }
8090}
c7b8f16e 8091
906e58ca
NC		 8092enum bfd_arm_vfp11_pipe
8093{
c7b8f16e
JB		 8094 VFP11_FMAC,
8095 VFP11_LS,
8096 VFP11_DS,
8097 VFP11_BAD
8098};
8099
8100/* Return a VFP register number. This is encoded as RX:X for single-precision
8101 registers, or X:RX for double-precision registers, where RX is the group of
8102 four bits in the instruction encoding and X is the single extension bit.
8103 RX and X fields are specified using their lowest (starting) bit. The return
8104 value is:
8105
8106 0...31: single-precision registers s0...s31
8107 32...63: double-precision registers d0...d31.
906e58ca 8108
c7b8f16e
JB		 8109 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8110 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8111
c7b8f16e
JB		 8112static unsigned int
8113bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8114 unsigned int x)
c7b8f16e
JB		 8115{
8116 if (is_double)
8117 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8118 else
8119 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8120}
8121
8122/* Set bits in *WMASK according to a register number REG as encoded by
8123 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8124
8125static void
8126bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8127{
8128 if (reg < 32)
8129 *wmask |= 1 << reg;
8130 else if (reg < 48)
8131 *wmask |= 3 << ((reg - 32) * 2);
8132}
8133
8134/* Return TRUE if WMASK overwrites anything in REGS. */
8135
8136static bfd_boolean
8137bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8138{
8139 int i;
906e58ca 8140
c7b8f16e
JB		 8141 for (i = 0; i < numregs; i++)
8142 {
8143 unsigned int reg = regs[i];
8144
8145 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8146 return TRUE;
906e58ca 8147
c7b8f16e
JB		 8148 reg -= 32;
8149
8150 if (reg >= 16)
99059e56 8151 continue;
906e58ca 8152
c7b8f16e 8153 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8154 return TRUE;
c7b8f16e 8155 }
906e58ca 8156
c7b8f16e
JB		 8157 return FALSE;
8158}
8159
8160/* In this function, we're interested in two things: finding input registers
8161 for VFP data-processing instructions, and finding the set of registers which
8162 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8163 hold the written set, so FLDM etc. are easy to deal with (we're only
8164 interested in 32 SP registers or 16 dp registers, due to the VFP version
8165 implemented by the chip in question). DP registers are marked by setting
8166 both SP registers in the write mask). */
8167
8168static enum bfd_arm_vfp11_pipe
8169bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8170 int *numregs)
c7b8f16e 8171{
91d6fa6a 8172 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8173 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8174
8175 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8176 {
8177 unsigned int pqrs;
8178 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8179 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8180
8181 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8182 | ((insn & 0x00300000) >> 19)
8183 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8184
8185 switch (pqrs)
99059e56
RM		 8186 {
8187 case 0: /* fmac[sd]. */
8188 case 1: /* fnmac[sd]. */
8189 case 2: /* fmsc[sd]. */
8190 case 3: /* fnmsc[sd]. */
8191 vpipe = VFP11_FMAC;
8192 bfd_arm_vfp11_write_mask (destmask, fd);
8193 regs[0] = fd;
8194 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8195 regs[2] = fm;
8196 *numregs = 3;
8197 break;
8198
8199 case 4: /* fmul[sd]. */
8200 case 5: /* fnmul[sd]. */
8201 case 6: /* fadd[sd]. */
8202 case 7: /* fsub[sd]. */
8203 vpipe = VFP11_FMAC;
8204 goto vfp_binop;
8205
8206 case 8: /* fdiv[sd]. */
8207 vpipe = VFP11_DS;
8208 vfp_binop:
8209 bfd_arm_vfp11_write_mask (destmask, fd);
8210 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8211 regs[1] = fm;
8212 *numregs = 2;
8213 break;
8214
8215 case 15: /* extended opcode. */
8216 {
8217 unsigned int extn = ((insn >> 15) & 0x1e)
8218 | ((insn >> 7) & 1);
8219
8220 switch (extn)
8221 {
8222 case 0: /* fcpy[sd]. */
8223 case 1: /* fabs[sd]. */
8224 case 2: /* fneg[sd]. */
8225 case 8: /* fcmp[sd]. */
8226 case 9: /* fcmpe[sd]. */
8227 case 10: /* fcmpz[sd]. */
8228 case 11: /* fcmpez[sd]. */
8229 case 16: /* fuito[sd]. */
8230 case 17: /* fsito[sd]. */
8231 case 24: /* ftoui[sd]. */
8232 case 25: /* ftouiz[sd]. */
8233 case 26: /* ftosi[sd]. */
8234 case 27: /* ftosiz[sd]. */
8235 /* These instructions will not bounce due to underflow. */
8236 *numregs = 0;
8237 vpipe = VFP11_FMAC;
8238 break;
8239
8240 case 3: /* fsqrt[sd]. */
8241 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8242 registers to cause the erratum in previous instructions. */
8243 bfd_arm_vfp11_write_mask (destmask, fd);
8244 vpipe = VFP11_DS;
8245 break;
8246
8247 case 15: /* fcvt{ds,sd}. */
8248 {
8249 int rnum = 0;
8250
8251 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8252
8253 /* Only FCVTSD can underflow. */
99059e56
RM		 8254 if ((insn & 0x100) != 0)
8255 regs[rnum++] = fm;
c7b8f16e 8256
99059e56 8257 *numregs = rnum;
c7b8f16e 8258
99059e56
RM		 8259 vpipe = VFP11_FMAC;
8260 }
8261 break;
c7b8f16e 8262
99059e56
RM		 8263 default:
8264 return VFP11_BAD;
8265 }
8266 }
8267 break;
c7b8f16e 8268
99059e56
RM		 8269 default:
8270 return VFP11_BAD;
8271 }
c7b8f16e
JB		 8272 }
8273 /* Two-register transfer. */
8274 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8275 {
8276 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8277
c7b8f16e
JB		 8278 if ((insn & 0x100000) == 0)
8279 {
99059e56
RM		 8280 if (is_double)
8281 bfd_arm_vfp11_write_mask (destmask, fm);
8282 else
8283 {
8284 bfd_arm_vfp11_write_mask (destmask, fm);
8285 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8286 }
c7b8f16e
JB		 8287 }
8288
91d6fa6a 8289 vpipe = VFP11_LS;
c7b8f16e
JB		 8290 }
8291 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8292 {
8293 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8294 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8295
c7b8f16e 8296 switch (puw)
99059e56
RM		 8297 {
8298 case 0: /* Two-reg transfer. We should catch these above. */
8299 abort ();
906e58ca 8300
99059e56
RM		 8301 case 2: /* fldm[sdx]. */
8302 case 3:
8303 case 5:
8304 {
8305 unsigned int i, offset = insn & 0xff;
c7b8f16e 8306
99059e56
RM		 8307 if (is_double)
8308 offset >>= 1;
c7b8f16e 8309
99059e56
RM		 8310 for (i = fd; i < fd + offset; i++)
8311 bfd_arm_vfp11_write_mask (destmask, i);
8312 }
8313 break;
906e58ca 8314
99059e56
RM		 8315 case 4: /* fld[sd]. */
8316 case 6:
8317 bfd_arm_vfp11_write_mask (destmask, fd);
8318 break;
906e58ca 8319
99059e56
RM		 8320 default:
8321 return VFP11_BAD;
8322 }
c7b8f16e 8323
91d6fa6a 8324 vpipe = VFP11_LS;
c7b8f16e
JB		 8325 }
8326 /* Single-register transfer. Note L==0. */
8327 else if ((insn & 0x0f100e10) == 0x0e000a10)
8328 {
8329 unsigned int opcode = (insn >> 21) & 7;
8330 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8331
8332 switch (opcode)
99059e56
RM		 8333 {
8334 case 0: /* fmsr/fmdlr. */
8335 case 1: /* fmdhr. */
8336 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8337 destination register. I don't know if this is exactly right,
8338 but it is the conservative choice. */
8339 bfd_arm_vfp11_write_mask (destmask, fn);
8340 break;
8341
8342 case 7: /* fmxr. */
8343 break;
8344 }
c7b8f16e 8345
91d6fa6a 8346 vpipe = VFP11_LS;
c7b8f16e
JB		 8347 }
8348
91d6fa6a 8349 return vpipe;
c7b8f16e
JB		 8350}
8351
8352
8353static int elf32_arm_compare_mapping (const void * a, const void * b);
8354
8355
8356/* Look for potentially-troublesome code sequences which might trigger the
8357 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8358 (available from ARM) for details of the erratum. A short version is
8359 described in ld.texinfo. */
8360
8361bfd_boolean
8362bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8363{
8364 asection *sec;
8365 bfd_byte *contents = NULL;
8366 int state = 0;
8367 int regs[3], numregs = 0;
8368 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8369 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8370
4dfe6ac6
NC		 8371 if (globals == NULL)
8372 return FALSE;
8373
c7b8f16e
JB		 8374 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8375 The states transition as follows:
906e58ca 8376
c7b8f16e 8377 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8378 A VFP FMAC-pipeline instruction has been seen. Fill
8379 regs[0]..regs[numregs-1] with its input operands. Remember this
8380 instruction in 'first_fmac'.
c7b8f16e
JB		 8381
8382 1 -> 2
99059e56
RM		 8383 Any instruction, except for a VFP instruction which overwrites
8384 regs[*].
906e58ca 8385
c7b8f16e
JB		 8386 1 -> 3 [ -> 0 ] or
8387 2 -> 3 [ -> 0 ]
99059e56
RM		 8388 A VFP instruction has been seen which overwrites any of regs[*].
8389 We must make a veneer! Reset state to 0 before examining next
8390 instruction.
906e58ca 8391
c7b8f16e 8392 2 -> 0
99059e56
RM		 8393 If we fail to match anything in state 2, reset to state 0 and reset
8394 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8395
8396 If the VFP11 vector mode is in use, there must be at least two unrelated
8397 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8398 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8399
8400 /* If we are only performing a partial link do not bother
8401 to construct any glue. */
0e1862bb 8402 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8403 return TRUE;
8404
0ffa91dd
NC		 8405 /* Skip if this bfd does not correspond to an ELF image. */
8406 if (! is_arm_elf (abfd))
8407 return TRUE;
906e58ca 8408
c7b8f16e
JB		 8409 /* We should have chosen a fix type by the time we get here. */
8410 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8411
8412 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8413 return TRUE;
2e6030b9 8414
33a7ffc2
JM		 8415 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8416 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8417 return TRUE;
8418
c7b8f16e
JB		 8419 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8420 {
8421 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8422 struct _arm_elf_section_data *sec_data;
8423
8424 /* If we don't have executable progbits, we're not interested in this
99059e56 8425 section. Also skip if section is to be excluded. */
c7b8f16e 8426 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8427 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8428 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8429 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8430 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8431 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8432 continue;
c7b8f16e
JB		 8433
8434 sec_data = elf32_arm_section_data (sec);
906e58ca 8435
c7b8f16e 8436 if (sec_data->mapcount == 0)
99059e56 8437 continue;
906e58ca 8438
c7b8f16e
JB		 8439 if (elf_section_data (sec)->this_hdr.contents != NULL)
8440 contents = elf_section_data (sec)->this_hdr.contents;
8441 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8442 goto error_return;
8443
8444 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8445 elf32_arm_compare_mapping);
8446
8447 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8448 {
8449 unsigned int span_start = sec_data->map[span].vma;
8450 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8451 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8452 char span_type = sec_data->map[span].type;
8453
8454 /* FIXME: Only ARM mode is supported at present. We may need to
8455 support Thumb-2 mode also at some point. */
8456 if (span_type != 'a')
8457 continue;
8458
8459 for (i = span_start; i < span_end;)
8460 {
8461 unsigned int next_i = i + 4;
8462 unsigned int insn = bfd_big_endian (abfd)
13c9c485
AM		 8463 ? (((unsigned) contents[i] << 24)
8464 | (contents[i + 1] << 16)
8465 | (contents[i + 2] << 8)
8466 | contents[i + 3])
8467 : (((unsigned) contents[i + 3] << 24)
8468 | (contents[i + 2] << 16)
8469 | (contents[i + 1] << 8)
8470 | contents[i]);
99059e56
RM		 8471 unsigned int writemask = 0;
8472 enum bfd_arm_vfp11_pipe vpipe;
8473
8474 switch (state)
8475 {
8476 case 0:
8477 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8478 &numregs);
8479 /* I'm assuming the VFP11 erratum can trigger with denorm
8480 operands on either the FMAC or the DS pipeline. This might
8481 lead to slightly overenthusiastic veneer insertion. */
8482 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8483 {
8484 state = use_vector ? 1 : 2;
8485 first_fmac = i;
8486 veneer_of_insn = insn;
8487 }
8488 break;
8489
8490 case 1:
8491 {
8492 int other_regs[3], other_numregs;
8493 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8494 other_regs,
99059e56
RM		 8495 &other_numregs);
8496 if (vpipe != VFP11_BAD
8497 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8498 numregs))
99059e56
RM		 8499 state = 3;
8500 else
8501 state = 2;
8502 }
8503 break;
8504
8505 case 2:
8506 {
8507 int other_regs[3], other_numregs;
8508 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8509 other_regs,
99059e56
RM		 8510 &other_numregs);
8511 if (vpipe != VFP11_BAD
8512 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8513 numregs))
99059e56
RM		 8514 state = 3;
8515 else
8516 {
8517 state = 0;
8518 next_i = first_fmac + 4;
8519 }
8520 }
8521 break;
8522
8523 case 3:
8524 abort (); /* Should be unreachable. */
8525 }
8526
8527 if (state == 3)
8528 {
8529 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8530 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8531
8532 elf32_arm_section_data (sec)->erratumcount += 1;
8533
8534 newerr->u.b.vfp_insn = veneer_of_insn;
8535
8536 switch (span_type)
8537 {
8538 case 'a':
8539 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8540 break;
8541
8542 default:
8543 abort ();
8544 }
8545
8546 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8547 first_fmac);
8548
99059e56 8549 newerr->vma = -1;
c7b8f16e 8550
99059e56
RM		 8551 newerr->next = sec_data->erratumlist;
8552 sec_data->erratumlist = newerr;
c7b8f16e 8553
99059e56
RM		 8554 state = 0;
8555 }
c7b8f16e 8556
99059e56
RM		 8557 i = next_i;
8558 }
8559 }
906e58ca 8560
c9594989 8561 if (elf_section_data (sec)->this_hdr.contents != contents)
99059e56 8562 free (contents);
c7b8f16e
JB		 8563 contents = NULL;
8564 }
8565
8566 return TRUE;
8567
dc1e8a47 8568 error_return:
c9594989 8569 if (elf_section_data (sec)->this_hdr.contents != contents)
c7b8f16e 8570 free (contents);
906e58ca 8571
c7b8f16e
JB		 8572 return FALSE;
8573}
8574
8575/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8576 after sections have been laid out, using specially-named symbols. */
8577
8578void
8579bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8580 struct bfd_link_info *link_info)
8581{
8582 asection *sec;
8583 struct elf32_arm_link_hash_table *globals;
8584 char *tmp_name;
906e58ca 8585
0e1862bb 8586 if (bfd_link_relocatable (link_info))
c7b8f16e 8587 return;
2e6030b9
MS		 8588
8589 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8590 if (! is_arm_elf (abfd))
2e6030b9
MS		 8591 return;
8592
c7b8f16e 8593 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8594 if (globals == NULL)
8595 return;
906e58ca 8596
21d799b5 8597 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8598 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
7a0fb7be 8599 BFD_ASSERT (tmp_name);
c7b8f16e
JB		 8600
8601 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8602 {
8603 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8604 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8605
c7b8f16e 8606 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8607 {
8608 struct elf_link_hash_entry *myh;
8609 bfd_vma vma;
8610
8611 switch (errnode->type)
8612 {
8613 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8614 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8615 /* Find veneer symbol. */
8616 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8617 errnode->u.b.veneer->u.v.id);
8618
99059e56
RM		 8619 myh = elf_link_hash_lookup
8620 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8621
a504d23a 8622 if (myh == NULL)
90b6238f
AM		 8623 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8624 abfd, "VFP11", tmp_name);
a504d23a
LA		 8625
8626 vma = myh->root.u.def.section->output_section->vma
8627 + myh->root.u.def.section->output_offset
8628 + myh->root.u.def.value;
8629
8630 errnode->u.b.veneer->vma = vma;
8631 break;
8632
8633 case VFP11_ERRATUM_ARM_VENEER:
8634 case VFP11_ERRATUM_THUMB_VENEER:
8635 /* Find return location. */
8636 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8637 errnode->u.v.id);
8638
8639 myh = elf_link_hash_lookup
8640 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8641
8642 if (myh == NULL)
90b6238f
AM		 8643 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8644 abfd, "VFP11", tmp_name);
a504d23a
LA		 8645
8646 vma = myh->root.u.def.section->output_section->vma
8647 + myh->root.u.def.section->output_offset
8648 + myh->root.u.def.value;
8649
8650 errnode->u.v.branch->vma = vma;
8651 break;
8652
8653 default:
8654 abort ();
8655 }
8656 }
8657 }
8658
8659 free (tmp_name);
8660}
8661
8662/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8663 return locations after sections have been laid out, using
8664 specially-named symbols. */
8665
8666void
8667bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8668 struct bfd_link_info *link_info)
8669{
8670 asection *sec;
8671 struct elf32_arm_link_hash_table *globals;
8672 char *tmp_name;
8673
8674 if (bfd_link_relocatable (link_info))
8675 return;
8676
8677 /* Skip if this bfd does not correspond to an ELF image. */
8678 if (! is_arm_elf (abfd))
8679 return;
8680
8681 globals = elf32_arm_hash_table (link_info);
8682 if (globals == NULL)
8683 return;
8684
8685 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8686 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7a0fb7be 8687 BFD_ASSERT (tmp_name);
a504d23a
LA		 8688
8689 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8690 {
8691 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8692 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8693
8694 for (; errnode != NULL; errnode = errnode->next)
8695 {
8696 struct elf_link_hash_entry *myh;
8697 bfd_vma vma;
8698
8699 switch (errnode->type)
8700 {
8701 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8702 /* Find veneer symbol. */
8703 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8704 errnode->u.b.veneer->u.v.id);
8705
8706 myh = elf_link_hash_lookup
8707 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8708
8709 if (myh == NULL)
90b6238f
AM		 8710 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8711 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8712
8713 vma = myh->root.u.def.section->output_section->vma
8714 + myh->root.u.def.section->output_offset
8715 + myh->root.u.def.value;
8716
8717 errnode->u.b.veneer->vma = vma;
8718 break;
8719
8720 case STM32L4XX_ERRATUM_VENEER:
8721 /* Find return location. */
8722 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8723 errnode->u.v.id);
8724
8725 myh = elf_link_hash_lookup
8726 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8727
8728 if (myh == NULL)
90b6238f
AM		 8729 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8730 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8731
8732 vma = myh->root.u.def.section->output_section->vma
8733 + myh->root.u.def.section->output_offset
8734 + myh->root.u.def.value;
8735
8736 errnode->u.v.branch->vma = vma;
8737 break;
8738
8739 default:
8740 abort ();
8741 }
8742 }
8743 }
8744
8745 free (tmp_name);
8746}
8747
8748static inline bfd_boolean
8749is_thumb2_ldmia (const insn32 insn)
8750{
8751 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8752 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8753 return (insn & 0xffd02000) == 0xe8900000;
8754}
8755
8756static inline bfd_boolean
8757is_thumb2_ldmdb (const insn32 insn)
8758{
8759 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8760 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8761 return (insn & 0xffd02000) == 0xe9100000;
8762}
8763
8764static inline bfd_boolean
8765is_thumb2_vldm (const insn32 insn)
8766{
8767 /* A6.5 Extension register load or store instruction
8768 A7.7.229
9239bbd3
CM		 8769 We look for SP 32-bit and DP 64-bit registers.
8770 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8771 <list> is consecutive 64-bit registers
8772 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8773 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8774 <list> is consecutive 32-bit registers
8775 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8776 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8777 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8778 return
9239bbd3
CM		 8779 (((insn & 0xfe100f00) == 0xec100b00) ||
8780 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8781 && /* (IA without !). */
8782 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8783 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8784 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8785 /* (DB with !). */
8786 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8787}
8788
8789/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8790 VLDM opcode and:
8791 - computes the number and the mode of memory accesses
8792 - decides if the replacement should be done:
8793 . replaces only if > 8-word accesses
8794 . or (testing purposes only) replaces all accesses. */
8795
8796static bfd_boolean
8797stm32l4xx_need_create_replacing_stub (const insn32 insn,
8798 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8799{
9239bbd3 8800 int nb_words = 0;
a504d23a
LA		 8801
8802 /* The field encoding the register list is the same for both LDMIA
8803 and LDMDB encodings. */
8804 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8805 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8806 else if (is_thumb2_vldm (insn))
9239bbd3 8807 nb_words = (insn & 0xff);
a504d23a
LA		 8808
8809 /* DEFAULT mode accounts for the real bug condition situation,
8810 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8811 return
9239bbd3 8812 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8813 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8814}
8815
8816/* Look for potentially-troublesome code sequences which might trigger
8817 the STM STM32L4XX erratum. */
8818
8819bfd_boolean
8820bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8821 struct bfd_link_info *link_info)
8822{
8823 asection *sec;
8824 bfd_byte *contents = NULL;
8825 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8826
8827 if (globals == NULL)
8828 return FALSE;
8829
8830 /* If we are only performing a partial link do not bother
8831 to construct any glue. */
8832 if (bfd_link_relocatable (link_info))
8833 return TRUE;
8834
8835 /* Skip if this bfd does not correspond to an ELF image. */
8836 if (! is_arm_elf (abfd))
8837 return TRUE;
8838
8839 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8840 return TRUE;
8841
8842 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8843 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8844 return TRUE;
8845
8846 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8847 {
8848 unsigned int i, span;
8849 struct _arm_elf_section_data *sec_data;
8850
8851 /* If we don't have executable progbits, we're not interested in this
8852 section. Also skip if section is to be excluded. */
8853 if (elf_section_type (sec) != SHT_PROGBITS
8854 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8855 || (sec->flags & SEC_EXCLUDE) != 0
8856 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8857 || sec->output_section == bfd_abs_section_ptr
8858 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8859 continue;
8860
8861 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8862
a504d23a
LA		 8863 if (sec_data->mapcount == 0)
8864 continue;
c7b8f16e 8865
a504d23a
LA		 8866 if (elf_section_data (sec)->this_hdr.contents != NULL)
8867 contents = elf_section_data (sec)->this_hdr.contents;
8868 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8869 goto error_return;
c7b8f16e 8870
a504d23a
LA		 8871 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8872 elf32_arm_compare_mapping);
c7b8f16e 8873
a504d23a
LA		 8874 for (span = 0; span < sec_data->mapcount; span++)
8875 {
8876 unsigned int span_start = sec_data->map[span].vma;
8877 unsigned int span_end = (span == sec_data->mapcount - 1)
8878 ? sec->size : sec_data->map[span + 1].vma;
8879 char span_type = sec_data->map[span].type;
8880 int itblock_current_pos = 0;
c7b8f16e 8881
a504d23a
LA		 8882 /* Only Thumb2 mode need be supported with this CM4 specific
8883 code, we should not encounter any arm mode eg span_type
8884 != 'a'. */
8885 if (span_type != 't')
8886 continue;
c7b8f16e 8887
a504d23a
LA		 8888 for (i = span_start; i < span_end;)
8889 {
8890 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8891 bfd_boolean insn_32bit = FALSE;
8892 bfd_boolean is_ldm = FALSE;
8893 bfd_boolean is_vldm = FALSE;
8894 bfd_boolean is_not_last_in_it_block = FALSE;
8895
8896 /* The first 16-bits of all 32-bit thumb2 instructions start
8897 with opcode[15..13]=0b111 and the encoded op1 can be anything
8898 except opcode[12..11]!=0b00.
8899 See 32-bit Thumb instruction encoding. */
8900 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8901 insn_32bit = TRUE;
c7b8f16e 8902
a504d23a
LA		 8903 /* Compute the predicate that tells if the instruction
8904 is concerned by the IT block
8905 - Creates an error if there is a ldm that is not
8906 last in the IT block thus cannot be replaced
8907 - Otherwise we can create a branch at the end of the
8908 IT block, it will be controlled naturally by IT
8909 with the proper pseudo-predicate
8910 - So the only interesting predicate is the one that
8911 tells that we are not on the last item of an IT
8912 block. */
8913 if (itblock_current_pos != 0)
8914 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8915
a504d23a
LA		 8916 if (insn_32bit)
8917 {
8918 /* Load the rest of the insn (in manual-friendly order). */
8919 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8920 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8921 is_vldm = is_thumb2_vldm (insn);
8922
8923 /* Veneers are created for (v)ldm depending on
8924 option flags and memory accesses conditions; but
8925 if the instruction is not the last instruction of
8926 an IT block, we cannot create a jump there, so we
8927 bail out. */
5025eb7c
AO		 8928 if ((is_ldm || is_vldm)
8929 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8930 (insn, globals->stm32l4xx_fix))
8931 {
8932 if (is_not_last_in_it_block)
8933 {
4eca0228 8934 _bfd_error_handler
695344c0 8935 /* xgettext:c-format */
871b3ab2 8936 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8937 " in non-last IT block instruction:"
8938 " STM32L4XX veneer cannot be generated; "
8939 "use gcc option -mrestrict-it to generate"
8940 " only one instruction per IT block"),
d42c267e 8941 abfd, sec, i);
a504d23a
LA		 8942 }
8943 else
8944 {
8945 elf32_stm32l4xx_erratum_list *newerr =
8946 (elf32_stm32l4xx_erratum_list *)
8947 bfd_zmalloc
8948 (sizeof (elf32_stm32l4xx_erratum_list));
8949
8950 elf32_arm_section_data (sec)
8951 ->stm32l4xx_erratumcount += 1;
8952 newerr->u.b.insn = insn;
8953 /* We create only thumb branches. */
8954 newerr->type =
8955 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8956 record_stm32l4xx_erratum_veneer
8957 (link_info, newerr, abfd, sec,
8958 i,
8959 is_ldm ?
8960 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8961 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8962 newerr->vma = -1;
8963 newerr->next = sec_data->stm32l4xx_erratumlist;
8964 sec_data->stm32l4xx_erratumlist = newerr;
8965 }
8966 }
8967 }
8968 else
8969 {
8970 /* A7.7.37 IT p208
8971 IT blocks are only encoded in T1
8972 Encoding T1: IT{x{y{z}}} <firstcond>
8973 1 0 1 1 - 1 1 1 1 - firstcond - mask
8974 if mask = '0000' then see 'related encodings'
8975 We don't deal with UNPREDICTABLE, just ignore these.
8976 There can be no nested IT blocks so an IT block
8977 is naturally a new one for which it is worth
8978 computing its size. */
5025eb7c
AO		 8979 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8980 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8981 /* If we have a new IT block we compute its size. */
8982 if (is_newitblock)
8983 {
8984 /* Compute the number of instructions controlled
8985 by the IT block, it will be used to decide
8986 whether we are inside an IT block or not. */
8987 unsigned int mask = insn & 0x000f;
8988 itblock_current_pos = 4 - ctz (mask);
8989 }
8990 }
8991
8992 i += insn_32bit ? 4 : 2;
99059e56
RM		 8993 }
8994 }
a504d23a 8995
c9594989 8996 if (elf_section_data (sec)->this_hdr.contents != contents)
a504d23a
LA		 8997 free (contents);
8998 contents = NULL;
c7b8f16e 8999 }
906e58ca 9000
a504d23a
LA		 9001 return TRUE;
9002
dc1e8a47 9003 error_return:
c9594989 9004 if (elf_section_data (sec)->this_hdr.contents != contents)
a504d23a 9005 free (contents);
c7b8f16e 9006
a504d23a
LA		 9007 return FALSE;
9008}
c7b8f16e 9009
eb043451
PB		 9010/* Set target relocation values needed during linking. */
9011
9012void
68c39892 9013bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 9014 struct bfd_link_info *link_info,
68c39892 9015 struct elf32_arm_params *params)
eb043451
PB		 9016{
9017 struct elf32_arm_link_hash_table *globals;
9018
9019 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9020 if (globals == NULL)
9021 return;
eb043451 9022
68c39892 9023 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 9024 if (globals->fdpic_p)
9025 globals->target2_reloc = R_ARM_GOT32;
9026 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 9027 globals->target2_reloc = R_ARM_REL32;
68c39892 9028 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 9029 globals->target2_reloc = R_ARM_ABS32;
68c39892 9030 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 9031 globals->target2_reloc = R_ARM_GOT_PREL;
9032 else
9033 {
90b6238f 9034 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9035 params->target2_type);
eb043451 9036 }
68c39892
TP		 9037 globals->fix_v4bx = params->fix_v4bx;
9038 globals->use_blx |= params->use_blx;
9039 globals->vfp11_fix = params->vfp11_denorm_fix;
9040 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9041 if (globals->fdpic_p)
9042 globals->pic_veneer = 1;
9043 else
9044 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9045 globals->fix_cortex_a8 = params->fix_cortex_a8;
9046 globals->fix_arm1176 = params->fix_arm1176;
9047 globals->cmse_implib = params->cmse_implib;
9048 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9049
0ffa91dd 9050 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9051 elf_arm_tdata (output_bfd)->no_enum_size_warning
9052 = params->no_enum_size_warning;
9053 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9054 = params->no_wchar_size_warning;
eb043451 9055}
eb043451 9056
12a0a0fd 9057/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9058
12a0a0fd
PB		 9059static void
9060insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9061{
9062 bfd_vma upper;
9063 bfd_vma lower;
9064 int reloc_sign;
9065
9066 BFD_ASSERT ((offset & 1) == 0);
9067
9068 upper = bfd_get_16 (abfd, insn);
9069 lower = bfd_get_16 (abfd, insn + 2);
9070 reloc_sign = (offset < 0) ? 1 : 0;
9071 upper = (upper & ~(bfd_vma) 0x7ff)
9072 | ((offset >> 12) & 0x3ff)
9073 | (reloc_sign << 10);
906e58ca 9074 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9075 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9076 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9077 | ((offset >> 1) & 0x7ff);
9078 bfd_put_16 (abfd, upper, insn);
9079 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9080}
9081
9b485d32
NC		 9082/* Thumb code calling an ARM function. */
9083
252b5132 9084static int
57e8b36a 9085elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9086 const char * name,
9087 bfd * input_bfd,
9088 bfd * output_bfd,
9089 asection * input_section,
9090 bfd_byte * hit_data,
9091 asection * sym_sec,
9092 bfd_vma offset,
9093 bfd_signed_vma addend,
9094 bfd_vma val,
f2a9dd69 9095 char **error_message)
252b5132 9096{
bcbdc74c 9097 asection * s = 0;
dc810e39 9098 bfd_vma my_offset;
252b5132 9099 long int ret_offset;
bcbdc74c
NC		 9100 struct elf_link_hash_entry * myh;
9101 struct elf32_arm_link_hash_table * globals;
252b5132 9102
f2a9dd69 9103 myh = find_thumb_glue (info, name, error_message);
252b5132 9104 if (myh == NULL)
b34976b6 9105 return FALSE;
252b5132
RH		 9106
9107 globals = elf32_arm_hash_table (info);
252b5132
RH		 9108 BFD_ASSERT (globals != NULL);
9109 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9110
9111 my_offset = myh->root.u.def.value;
9112
3d4d4302
AM		 9113 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9114 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9115
9116 BFD_ASSERT (s != NULL);
9117 BFD_ASSERT (s->contents != NULL);
9118 BFD_ASSERT (s->output_section != NULL);
9119
9120 if ((my_offset & 0x01) == 0x01)
9121 {
9122 if (sym_sec != NULL
9123 && sym_sec->owner != NULL
9124 && !INTERWORK_FLAG (sym_sec->owner))
9125 {
4eca0228 9126 _bfd_error_handler
90b6238f
AM		 9127 (_("%pB(%s): warning: interworking not enabled;"
9128 " first occurrence: %pB: %s call to %s"),
9129 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9130
b34976b6 9131 return FALSE;
252b5132
RH		 9132 }
9133
9134 --my_offset;
9135 myh->root.u.def.value = my_offset;
9136
52ab56c2
PB		 9137 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9138 s->contents + my_offset);
252b5132 9139
52ab56c2
PB		 9140 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9141 s->contents + my_offset + 2);
252b5132
RH		 9142
9143 ret_offset =
9b485d32
NC		 9144 /* Address of destination of the stub. */
9145 ((bfd_signed_vma) val)
252b5132 9146 - ((bfd_signed_vma)
57e8b36a
NC		 9147 /* Offset from the start of the current section
9148 to the start of the stubs. */
9b485d32
NC		 9149 (s->output_offset
9150 /* Offset of the start of this stub from the start of the stubs. */
9151 + my_offset
9152 /* Address of the start of the current section. */
9153 + s->output_section->vma)
9154 /* The branch instruction is 4 bytes into the stub. */
9155 + 4
9156 /* ARM branches work from the pc of the instruction + 8. */
9157 + 8);
252b5132 9158
52ab56c2
PB		 9159 put_arm_insn (globals, output_bfd,
9160 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9161 s->contents + my_offset + 4);
252b5132
RH		 9162 }
9163
9164 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9165
427bfd90
NC		 9166 /* Now go back and fix up the original BL insn to point to here. */
9167 ret_offset =
9168 /* Address of where the stub is located. */
9169 (s->output_section->vma + s->output_offset + my_offset)
9170 /* Address of where the BL is located. */
57e8b36a
NC		 9171 - (input_section->output_section->vma + input_section->output_offset
9172 + offset)
427bfd90
NC		 9173 /* Addend in the relocation. */
9174 - addend
9175 /* Biassing for PC-relative addressing. */
9176 - 8;
252b5132 9177
12a0a0fd 9178 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9179
b34976b6 9180 return TRUE;
252b5132
RH		 9181}
9182
a4fd1a8e 9183/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9184
a4fd1a8e
PB		 9185static struct elf_link_hash_entry *
9186elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9187 const char * name,
9188 bfd * input_bfd,
9189 bfd * output_bfd,
9190 asection * sym_sec,
9191 bfd_vma val,
9192 asection * s,
9193 char ** error_message)
252b5132 9194{
dc810e39 9195 bfd_vma my_offset;
252b5132 9196 long int ret_offset;
bcbdc74c
NC		 9197 struct elf_link_hash_entry * myh;
9198 struct elf32_arm_link_hash_table * globals;
252b5132 9199
f2a9dd69 9200 myh = find_arm_glue (info, name, error_message);
252b5132 9201 if (myh == NULL)
a4fd1a8e 9202 return NULL;
252b5132
RH		 9203
9204 globals = elf32_arm_hash_table (info);
252b5132
RH		 9205 BFD_ASSERT (globals != NULL);
9206 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9207
9208 my_offset = myh->root.u.def.value;
252b5132
RH		 9209
9210 if ((my_offset & 0x01) == 0x01)
9211 {
9212 if (sym_sec != NULL
9213 && sym_sec->owner != NULL
9214 && !INTERWORK_FLAG (sym_sec->owner))
9215 {
4eca0228 9216 _bfd_error_handler
90b6238f
AM		 9217 (_("%pB(%s): warning: interworking not enabled;"
9218 " first occurrence: %pB: %s call to %s"),
9219 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9220 }
9b485d32 9221
252b5132
RH		 9222 --my_offset;
9223 myh->root.u.def.value = my_offset;
9224
0e1862bb
L		 9225 if (bfd_link_pic (info)
9226 || globals->root.is_relocatable_executable
27e55c4d 9227 || globals->pic_veneer)
8f6277f5
PB		 9228 {
9229 /* For relocatable objects we can't use absolute addresses,
9230 so construct the address from a relative offset. */
9231 /* TODO: If the offset is small it's probably worth
9232 constructing the address with adds. */
52ab56c2
PB		 9233 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9234 s->contents + my_offset);
9235 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9236 s->contents + my_offset + 4);
9237 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9238 s->contents + my_offset + 8);
8f6277f5
PB		 9239 /* Adjust the offset by 4 for the position of the add,
9240 and 8 for the pipeline offset. */
9241 ret_offset = (val - (s->output_offset
9242 + s->output_section->vma
9243 + my_offset + 12))
9244 | 1;
9245 bfd_put_32 (output_bfd, ret_offset,
9246 s->contents + my_offset + 12);
9247 }
26079076
PB		 9248 else if (globals->use_blx)
9249 {
9250 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9251 s->contents + my_offset);
9252
9253 /* It's a thumb address. Add the low order bit. */
9254 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9255 s->contents + my_offset + 4);
9256 }
8f6277f5
PB		 9257 else
9258 {
52ab56c2
PB		 9259 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9260 s->contents + my_offset);
252b5132 9261
52ab56c2
PB		 9262 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9263 s->contents + my_offset + 4);
252b5132 9264
8f6277f5
PB		 9265 /* It's a thumb address. Add the low order bit. */
9266 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9267 s->contents + my_offset + 8);
8029a119
NC		 9268
9269 my_offset += 12;
8f6277f5 9270 }
252b5132
RH		 9271 }
9272
9273 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9274
a4fd1a8e
PB		 9275 return myh;
9276}
9277
9278/* Arm code calling a Thumb function. */
9279
9280static int
9281elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9282 const char * name,
9283 bfd * input_bfd,
9284 bfd * output_bfd,
9285 asection * input_section,
9286 bfd_byte * hit_data,
9287 asection * sym_sec,
9288 bfd_vma offset,
9289 bfd_signed_vma addend,
9290 bfd_vma val,
f2a9dd69 9291 char **error_message)
a4fd1a8e
PB		 9292{
9293 unsigned long int tmp;
9294 bfd_vma my_offset;
9295 asection * s;
9296 long int ret_offset;
9297 struct elf_link_hash_entry * myh;
9298 struct elf32_arm_link_hash_table * globals;
9299
9300 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9301 BFD_ASSERT (globals != NULL);
9302 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9303
3d4d4302
AM		 9304 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9305 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9306 BFD_ASSERT (s != NULL);
9307 BFD_ASSERT (s->contents != NULL);
9308 BFD_ASSERT (s->output_section != NULL);
9309
9310 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9311 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9312 if (!myh)
9313 return FALSE;
9314
9315 my_offset = myh->root.u.def.value;
252b5132
RH		 9316 tmp = bfd_get_32 (input_bfd, hit_data);
9317 tmp = tmp & 0xFF000000;
9318
9b485d32 9319 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9320 ret_offset = (s->output_offset
9321 + my_offset
9322 + s->output_section->vma
9323 - (input_section->output_offset
9324 + input_section->output_section->vma
9325 + offset + addend)
9326 - 8);
9a5aca8c 9327
252b5132
RH		 9328 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9329
dc810e39 9330 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9331
b34976b6 9332 return TRUE;
252b5132
RH		 9333}
9334
a4fd1a8e
PB		 9335/* Populate Arm stub for an exported Thumb function. */
9336
9337static bfd_boolean
9338elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9339{
9340 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9341 asection * s;
9342 struct elf_link_hash_entry * myh;
9343 struct elf32_arm_link_hash_entry *eh;
9344 struct elf32_arm_link_hash_table * globals;
9345 asection *sec;
9346 bfd_vma val;
f2a9dd69 9347 char *error_message;
a4fd1a8e 9348
906e58ca 9349 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9350 /* Allocate stubs for exported Thumb functions on v4t. */
9351 if (eh->export_glue == NULL)
9352 return TRUE;
9353
9354 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9355 BFD_ASSERT (globals != NULL);
9356 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9357
3d4d4302
AM		 9358 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9359 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9360 BFD_ASSERT (s != NULL);
9361 BFD_ASSERT (s->contents != NULL);
9362 BFD_ASSERT (s->output_section != NULL);
9363
9364 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9365
9366 BFD_ASSERT (sec->output_section != NULL);
9367
a4fd1a8e
PB		 9368 val = eh->export_glue->root.u.def.value + sec->output_offset
9369 + sec->output_section->vma;
8029a119 9370
a4fd1a8e
PB		 9371 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9372 h->root.u.def.section->owner,
f2a9dd69
DJ		 9373 globals->obfd, sec, val, s,
9374 &error_message);
a4fd1a8e
PB		 9375 BFD_ASSERT (myh);
9376 return TRUE;
9377}
9378
845b51d6
PB		 9379/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9380
9381static bfd_vma
9382elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9383{
9384 bfd_byte *p;
9385 bfd_vma glue_addr;
9386 asection *s;
9387 struct elf32_arm_link_hash_table *globals;
9388
9389 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9390 BFD_ASSERT (globals != NULL);
9391 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9392
3d4d4302
AM		 9393 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9394 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9395 BFD_ASSERT (s != NULL);
9396 BFD_ASSERT (s->contents != NULL);
9397 BFD_ASSERT (s->output_section != NULL);
9398
9399 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9400
9401 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9402
9403 if ((globals->bx_glue_offset[reg] & 1) == 0)
9404 {
9405 p = s->contents + glue_addr;
9406 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9407 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9408 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9409 globals->bx_glue_offset[reg] |= 1;
9410 }
9411
9412 return glue_addr + s->output_section->vma + s->output_offset;
9413}
9414
a4fd1a8e
PB		 9415/* Generate Arm stubs for exported Thumb symbols. */
9416static void
906e58ca 9417elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9418 struct bfd_link_info *link_info)
9419{
9420 struct elf32_arm_link_hash_table * globals;
9421
8029a119
NC		 9422 if (link_info == NULL)
9423 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9424 return;
9425
9426 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9427 if (globals == NULL)
9428 return;
9429
84c08195
PB		 9430 /* If blx is available then exported Thumb symbols are OK and there is
9431 nothing to do. */
a4fd1a8e
PB		 9432 if (globals->use_blx)
9433 return;
9434
9435 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9436 link_info);
9437}
9438
47beaa6a
RS		 9439/* Reserve space for COUNT dynamic relocations in relocation selection
9440 SRELOC. */
9441
9442static void
9443elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9444 bfd_size_type count)
9445{
9446 struct elf32_arm_link_hash_table *htab;
9447
9448 htab = elf32_arm_hash_table (info);
9449 BFD_ASSERT (htab->root.dynamic_sections_created);
9450 if (sreloc == NULL)
9451 abort ();
9452 sreloc->size += RELOC_SIZE (htab) * count;
9453}
9454
34e77a92
RS		 9455/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9456 dynamic, the relocations should go in SRELOC, otherwise they should
9457 go in the special .rel.iplt section. */
9458
9459static void
9460elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9461 bfd_size_type count)
9462{
9463 struct elf32_arm_link_hash_table *htab;
9464
9465 htab = elf32_arm_hash_table (info);
9466 if (!htab->root.dynamic_sections_created)
9467 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9468 else
9469 {
9470 BFD_ASSERT (sreloc != NULL);
9471 sreloc->size += RELOC_SIZE (htab) * count;
9472 }
9473}
9474
47beaa6a
RS		 9475/* Add relocation REL to the end of relocation section SRELOC. */
9476
9477static void
9478elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9479 asection *sreloc, Elf_Internal_Rela *rel)
9480{
9481 bfd_byte *loc;
9482 struct elf32_arm_link_hash_table *htab;
9483
9484 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9485 if (!htab->root.dynamic_sections_created
9486 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9487 sreloc = htab->root.irelplt;
47beaa6a
RS		 9488 if (sreloc == NULL)
9489 abort ();
9490 loc = sreloc->contents;
9491 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9492 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9493 abort ();
9494 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9495}
9496
34e77a92
RS		 9497/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9498 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9499 to .plt. */
9500
9501static void
9502elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9503 bfd_boolean is_iplt_entry,
9504 union gotplt_union *root_plt,
9505 struct arm_plt_info *arm_plt)
9506{
9507 struct elf32_arm_link_hash_table *htab;
9508 asection *splt;
9509 asection *sgotplt;
9510
9511 htab = elf32_arm_hash_table (info);
9512
9513 if (is_iplt_entry)
9514 {
9515 splt = htab->root.iplt;
9516 sgotplt = htab->root.igotplt;
9517
99059e56 9518 /* NaCl uses a special first entry in .iplt too. */
90c14f0c 9519 if (htab->root.target_os == is_nacl && splt->size == 0)
99059e56
RM		 9520 splt->size += htab->plt_header_size;
9521
34e77a92
RS		 9522 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9523 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9524 }
9525 else
9526 {
9527 splt = htab->root.splt;
9528 sgotplt = htab->root.sgotplt;
9529
7801f98f
CL		 9530 if (htab->fdpic_p)
9531 {
9532 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9533 /* For lazy binding, relocations will be put into .rel.plt, in
9534 .rel.got otherwise. */
9535 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9536 if (info->flags & DF_BIND_NOW)
9537 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9538 else
9539 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9540 }
9541 else
9542 {
9543 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9544 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9545 }
34e77a92
RS		 9546
9547 /* If this is the first .plt entry, make room for the special
9548 first entry. */
9549 if (splt->size == 0)
9550 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9551
9552 htab->next_tls_desc_index++;
34e77a92
RS		 9553 }
9554
9555 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9556 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9557 splt->size += PLT_THUMB_STUB_SIZE;
9558 root_plt->offset = splt->size;
9559 splt->size += htab->plt_entry_size;
9560
90c14f0c 9561 if (htab->root.target_os != is_symbian)
34e77a92
RS		 9562 {
9563 /* We also need to make an entry in the .got.plt section, which
9564 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9565 if (is_iplt_entry)
9566 arm_plt->got_offset = sgotplt->size;
9567 else
9568 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9569 if (htab->fdpic_p)
9570 /* Function descriptor takes 64 bits in GOT. */
4b24dd1a 9571 sgotplt->size += 8;
7801f98f
CL		 9572 else
9573 sgotplt->size += 4;
34e77a92
RS		 9574 }
9575}
9576
b38cadfb
NC		 9577static bfd_vma
9578arm_movw_immediate (bfd_vma value)
9579{
9580 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9581}
9582
9583static bfd_vma
9584arm_movt_immediate (bfd_vma value)
9585{
9586 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9587}
9588
34e77a92
RS		 9589/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9590 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9591 Otherwise, DYNINDX is the index of the symbol in the dynamic
9592 symbol table and SYM_VALUE is undefined.
9593
9594 ROOT_PLT points to the offset of the PLT entry from the start of its
9595 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9596 bookkeeping information.
34e77a92 9597
57460bcf
NC		 9598 Returns FALSE if there was a problem. */
9599
9600static bfd_boolean
34e77a92
RS		 9601elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9602 union gotplt_union *root_plt,
9603 struct arm_plt_info *arm_plt,
9604 int dynindx, bfd_vma sym_value)
9605{
9606 struct elf32_arm_link_hash_table *htab;
9607 asection *sgot;
9608 asection *splt;
9609 asection *srel;
9610 bfd_byte *loc;
9611 bfd_vma plt_index;
9612 Elf_Internal_Rela rel;
9613 bfd_vma plt_header_size;
9614 bfd_vma got_header_size;
9615
9616 htab = elf32_arm_hash_table (info);
9617
9618 /* Pick the appropriate sections and sizes. */
9619 if (dynindx == -1)
9620 {
9621 splt = htab->root.iplt;
9622 sgot = htab->root.igotplt;
9623 srel = htab->root.irelplt;
9624
9625 /* There are no reserved entries in .igot.plt, and no special
9626 first entry in .iplt. */
9627 got_header_size = 0;
9628 plt_header_size = 0;
9629 }
9630 else
9631 {
9632 splt = htab->root.splt;
9633 sgot = htab->root.sgotplt;
9634 srel = htab->root.srelplt;
9635
9636 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9637 plt_header_size = htab->plt_header_size;
9638 }
9639 BFD_ASSERT (splt != NULL && srel != NULL);
9640
9641 /* Fill in the entry in the procedure linkage table. */
90c14f0c 9642 if (htab->root.target_os == is_symbian)
34e77a92
RS		 9643 {
9644 BFD_ASSERT (dynindx >= 0);
9645 put_arm_insn (htab, output_bfd,
9646 elf32_arm_symbian_plt_entry[0],
9647 splt->contents + root_plt->offset);
9648 bfd_put_32 (output_bfd,
9649 elf32_arm_symbian_plt_entry[1],
9650 splt->contents + root_plt->offset + 4);
9651
9652 /* Fill in the entry in the .rel.plt section. */
9653 rel.r_offset = (splt->output_section->vma
9654 + splt->output_offset
9655 + root_plt->offset + 4);
9656 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9657
9658 /* Get the index in the procedure linkage table which
9659 corresponds to this symbol. This is the index of this symbol
9660 in all the symbols for which we are making plt entries. The
9661 first entry in the procedure linkage table is reserved. */
9662 plt_index = ((root_plt->offset - plt_header_size)
9663 / htab->plt_entry_size);
9664 }
9665 else
9666 {
9667 bfd_vma got_offset, got_address, plt_address;
9668 bfd_vma got_displacement, initial_got_entry;
9669 bfd_byte * ptr;
9670
9671 BFD_ASSERT (sgot != NULL);
9672
9673 /* Get the offset into the .(i)got.plt table of the entry that
9674 corresponds to this function. */
9675 got_offset = (arm_plt->got_offset & -2);
9676
9677 /* Get the index in the procedure linkage table which
9678 corresponds to this symbol. This is the index of this symbol
9679 in all the symbols for which we are making plt entries.
9680 After the reserved .got.plt entries, all symbols appear in
9681 the same order as in .plt. */
7801f98f 9682 if (htab->fdpic_p)
4b24dd1a
AM		 9683 /* Function descriptor takes 8 bytes. */
9684 plt_index = (got_offset - got_header_size) / 8;
7801f98f 9685 else
4b24dd1a 9686 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9687
9688 /* Calculate the address of the GOT entry. */
9689 got_address = (sgot->output_section->vma
9690 + sgot->output_offset
9691 + got_offset);
9692
9693 /* ...and the address of the PLT entry. */
9694 plt_address = (splt->output_section->vma
9695 + splt->output_offset
9696 + root_plt->offset);
9697
9698 ptr = splt->contents + root_plt->offset;
90c14f0c 9699 if (htab->root.target_os == is_vxworks && bfd_link_pic (info))
34e77a92
RS		 9700 {
9701 unsigned int i;
9702 bfd_vma val;
9703
9704 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9705 {
9706 val = elf32_arm_vxworks_shared_plt_entry[i];
9707 if (i == 2)
9708 val |= got_address - sgot->output_section->vma;
9709 if (i == 5)
9710 val |= plt_index * RELOC_SIZE (htab);
9711 if (i == 2 || i == 5)
9712 bfd_put_32 (output_bfd, val, ptr);
9713 else
9714 put_arm_insn (htab, output_bfd, val, ptr);
9715 }
9716 }
90c14f0c 9717 else if (htab->root.target_os == is_vxworks)
34e77a92
RS		 9718 {
9719 unsigned int i;
9720 bfd_vma val;
9721
9722 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9723 {
9724 val = elf32_arm_vxworks_exec_plt_entry[i];
9725 if (i == 2)
9726 val |= got_address;
9727 if (i == 4)
9728 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9729 if (i == 5)
9730 val |= plt_index * RELOC_SIZE (htab);
9731 if (i == 2 || i == 5)
9732 bfd_put_32 (output_bfd, val, ptr);
9733 else
9734 put_arm_insn (htab, output_bfd, val, ptr);
9735 }
9736
9737 loc = (htab->srelplt2->contents
9738 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9739
9740 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9741 referencing the GOT for this PLT entry. */
9742 rel.r_offset = plt_address + 8;
9743 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9744 rel.r_addend = got_offset;
9745 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9746 loc += RELOC_SIZE (htab);
9747
9748 /* Create the R_ARM_ABS32 relocation referencing the
9749 beginning of the PLT for this GOT entry. */
9750 rel.r_offset = got_address;
9751 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9752 rel.r_addend = 0;
9753 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9754 }
90c14f0c 9755 else if (htab->root.target_os == is_nacl)
b38cadfb
NC		 9756 {
9757 /* Calculate the displacement between the PLT slot and the
9758 common tail that's part of the special initial PLT slot. */
6034aab8 9759 int32_t tail_displacement
b38cadfb
NC		 9760 = ((splt->output_section->vma + splt->output_offset
9761 + ARM_NACL_PLT_TAIL_OFFSET)
9762 - (plt_address + htab->plt_entry_size + 4));
9763 BFD_ASSERT ((tail_displacement & 3) == 0);
9764 tail_displacement >>= 2;
9765
9766 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9767 || (-tail_displacement & 0xff000000) == 0);
9768
9769 /* Calculate the displacement between the PLT slot and the entry
9770 in the GOT. The offset accounts for the value produced by
9771 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9772 got_displacement = (got_address
99059e56 9773 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9774
9775 /* NaCl does not support interworking at all. */
9776 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9777
9778 put_arm_insn (htab, output_bfd,
9779 elf32_arm_nacl_plt_entry[0]
9780 | arm_movw_immediate (got_displacement),
9781 ptr + 0);
9782 put_arm_insn (htab, output_bfd,
9783 elf32_arm_nacl_plt_entry[1]
9784 | arm_movt_immediate (got_displacement),
9785 ptr + 4);
9786 put_arm_insn (htab, output_bfd,
9787 elf32_arm_nacl_plt_entry[2],
9788 ptr + 8);
9789 put_arm_insn (htab, output_bfd,
9790 elf32_arm_nacl_plt_entry[3]
9791 | (tail_displacement & 0x00ffffff),
9792 ptr + 12);
9793 }
7801f98f
CL		 9794 else if (htab->fdpic_p)
9795 {
59029f57
CL		 9796 const bfd_vma *plt_entry = using_thumb_only(htab)
9797 ? elf32_arm_fdpic_thumb_plt_entry
9798 : elf32_arm_fdpic_plt_entry;
9799
7801f98f
CL		 9800 /* Fill-up Thumb stub if needed. */
9801 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9802 {
9803 put_thumb_insn (htab, output_bfd,
9804 elf32_arm_plt_thumb_stub[0], ptr - 4);
9805 put_thumb_insn (htab, output_bfd,
9806 elf32_arm_plt_thumb_stub[1], ptr - 2);
9807 }
59029f57
CL		 9808 /* As we are using 32 bit instructions even for the Thumb
9809 version, we have to use 'put_arm_insn' instead of
9810 'put_thumb_insn'. */
9811 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9812 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9813 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9814 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9815 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9816
9817 if (!(info->flags & DF_BIND_NOW))
9818 {
9819 /* funcdesc_value_reloc_offset. */
9820 bfd_put_32 (output_bfd,
9821 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9822 ptr + 20);
59029f57
CL		 9823 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9824 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9825 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9826 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9827 }
9828 }
57460bcf
NC		 9829 else if (using_thumb_only (htab))
9830 {
eed94f8f 9831 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9832 if (!using_thumb2 (htab))
eed94f8f
NC		 9833 {
9834 /* FIXME: We ought to be able to generate thumb-1 PLT
9835 instructions... */
90b6238f 9836 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9837 output_bfd);
9838 return FALSE;
9839 }
57460bcf 9840
eed94f8f
NC		 9841 /* Calculate the displacement between the PLT slot and the entry in
9842 the GOT. The 12-byte offset accounts for the value produced by
9843 adding to pc in the 3rd instruction of the PLT stub. */
9844 got_displacement = got_address - (plt_address + 12);
9845
9846 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9847 instead of 'put_thumb_insn'. */
9848 put_arm_insn (htab, output_bfd,
9849 elf32_thumb2_plt_entry[0]
9850 | ((got_displacement & 0x000000ff) << 16)
9851 | ((got_displacement & 0x00000700) << 20)
9852 | ((got_displacement & 0x00000800) >> 1)
9853 | ((got_displacement & 0x0000f000) >> 12),
9854 ptr + 0);
9855 put_arm_insn (htab, output_bfd,
9856 elf32_thumb2_plt_entry[1]
9857 | ((got_displacement & 0x00ff0000) )
9858 | ((got_displacement & 0x07000000) << 4)
9859 | ((got_displacement & 0x08000000) >> 17)
9860 | ((got_displacement & 0xf0000000) >> 28),
9861 ptr + 4);
9862 put_arm_insn (htab, output_bfd,
9863 elf32_thumb2_plt_entry[2],
9864 ptr + 8);
9865 put_arm_insn (htab, output_bfd,
9866 elf32_thumb2_plt_entry[3],
9867 ptr + 12);
57460bcf 9868 }
34e77a92
RS		 9869 else
9870 {
9871 /* Calculate the displacement between the PLT slot and the
9872 entry in the GOT. The eight-byte offset accounts for the
9873 value produced by adding to pc in the first instruction
9874 of the PLT stub. */
9875 got_displacement = got_address - (plt_address + 8);
9876
34e77a92
RS		 9877 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9878 {
9879 put_thumb_insn (htab, output_bfd,
9880 elf32_arm_plt_thumb_stub[0], ptr - 4);
9881 put_thumb_insn (htab, output_bfd,
9882 elf32_arm_plt_thumb_stub[1], ptr - 2);
9883 }
9884
1db37fe6
YG		 9885 if (!elf32_arm_use_long_plt_entry)
9886 {
9887 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9888
9889 put_arm_insn (htab, output_bfd,
9890 elf32_arm_plt_entry_short[0]
9891 | ((got_displacement & 0x0ff00000) >> 20),
9892 ptr + 0);
9893 put_arm_insn (htab, output_bfd,
9894 elf32_arm_plt_entry_short[1]
9895 | ((got_displacement & 0x000ff000) >> 12),
9896 ptr+ 4);
9897 put_arm_insn (htab, output_bfd,
9898 elf32_arm_plt_entry_short[2]
9899 | (got_displacement & 0x00000fff),
9900 ptr + 8);
34e77a92 9901#ifdef FOUR_WORD_PLT
1db37fe6 9902 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9903#endif
1db37fe6
YG		 9904 }
9905 else
9906 {
9907 put_arm_insn (htab, output_bfd,
9908 elf32_arm_plt_entry_long[0]
9909 | ((got_displacement & 0xf0000000) >> 28),
9910 ptr + 0);
9911 put_arm_insn (htab, output_bfd,
9912 elf32_arm_plt_entry_long[1]
9913 | ((got_displacement & 0x0ff00000) >> 20),
9914 ptr + 4);
9915 put_arm_insn (htab, output_bfd,
9916 elf32_arm_plt_entry_long[2]
9917 | ((got_displacement & 0x000ff000) >> 12),
9918 ptr+ 8);
9919 put_arm_insn (htab, output_bfd,
9920 elf32_arm_plt_entry_long[3]
9921 | (got_displacement & 0x00000fff),
9922 ptr + 12);
9923 }
34e77a92
RS		 9924 }
9925
9926 /* Fill in the entry in the .rel(a).(i)plt section. */
9927 rel.r_offset = got_address;
9928 rel.r_addend = 0;
9929 if (dynindx == -1)
9930 {
9931 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9932 The dynamic linker or static executable then calls SYM_VALUE
9933 to determine the correct run-time value of the .igot.plt entry. */
9934 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9935 initial_got_entry = sym_value;
9936 }
9937 else
9938 {
7801f98f
CL		 9939 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9940 used by PLT entry. */
9941 if (htab->fdpic_p)
9942 {
9943 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9944 initial_got_entry = 0;
9945 }
9946 else
9947 {
9948 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9949 initial_got_entry = (splt->output_section->vma
9950 + splt->output_offset);
a7618269
TC		 9951
9952 /* PR ld/16017
9953 When thumb only we need to set the LSB for any address that
9954 will be used with an interworking branch instruction. */
9955 if (using_thumb_only (htab))
9956 initial_got_entry |= 1;
7801f98f 9957 }
34e77a92
RS		 9958 }
9959
9960 /* Fill in the entry in the global offset table. */
9961 bfd_put_32 (output_bfd, initial_got_entry,
9962 sgot->contents + got_offset);
7801f98f
CL		 9963
9964 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
9965 {
9966 /* Setup initial funcdesc value. */
9967 /* FIXME: we don't support lazy binding because there is a
9968 race condition between both words getting written and
9969 some other thread attempting to read them. The ARM
9970 architecture does not have an atomic 64 bit load/store
9971 instruction that could be used to prevent it; it is
9972 recommended that threaded FDPIC applications run with the
9973 LD_BIND_NOW environment variable set. */
9974 bfd_put_32(output_bfd, plt_address + 0x18,
9975 sgot->contents + got_offset);
9976 bfd_put_32(output_bfd, -1 /*TODO*/,
9977 sgot->contents + got_offset + 4);
9978 }
34e77a92
RS		 9979 }
9980
aba8c3de
WN		 9981 if (dynindx == -1)
9982 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9983 else
9984 {
7801f98f
CL		 9985 if (htab->fdpic_p)
9986 {
9987 /* For FDPIC we put PLT relocationss into .rel.got when not
9988 lazy binding otherwise we put them in .rel.plt. For now,
9989 we don't support lazy binding so put it in .rel.got. */
9990 if (info->flags & DF_BIND_NOW)
9991 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
9992 else
9993 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
9994 }
9995 else
9996 {
9997 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9998 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9999 }
aba8c3de 10000 }
57460bcf
NC		 10001
10002 return TRUE;
34e77a92
RS		 10003}
10004
eb043451
PB		 10005/* Some relocations map to different relocations depending on the
10006 target. Return the real relocation. */
8029a119 10007
eb043451
PB		 10008static int
10009arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
10010 int r_type)
10011{
10012 switch (r_type)
10013 {
10014 case R_ARM_TARGET1:
10015 if (globals->target1_is_rel)
10016 return R_ARM_REL32;
10017 else
10018 return R_ARM_ABS32;
10019
10020 case R_ARM_TARGET2:
10021 return globals->target2_reloc;
10022
10023 default:
10024 return r_type;
10025 }
10026}
eb043451 10027
ba93b8ac
DJ		 10028/* Return the base VMA address which should be subtracted from real addresses
10029 when resolving @dtpoff relocation.
10030 This is PT_TLS segment p_vaddr. */
10031
10032static bfd_vma
10033dtpoff_base (struct bfd_link_info *info)
10034{
10035 /* If tls_sec is NULL, we should have signalled an error already. */
10036 if (elf_hash_table (info)->tls_sec == NULL)
10037 return 0;
10038 return elf_hash_table (info)->tls_sec->vma;
10039}
10040
10041/* Return the relocation value for @tpoff relocation
10042 if STT_TLS virtual address is ADDRESS. */
10043
10044static bfd_vma
10045tpoff (struct bfd_link_info *info, bfd_vma address)
10046{
10047 struct elf_link_hash_table *htab = elf_hash_table (info);
10048 bfd_vma base;
10049
10050 /* If tls_sec is NULL, we should have signalled an error already. */
10051 if (htab->tls_sec == NULL)
10052 return 0;
10053 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10054 return address - htab->tls_sec->vma + base;
10055}
10056
00a97672
RS		 10057/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10058 VALUE is the relocation value. */
10059
10060static bfd_reloc_status_type
10061elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10062{
10063 if (value > 0xfff)
10064 return bfd_reloc_overflow;
10065
10066 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10067 bfd_put_32 (abfd, value, data);
10068 return bfd_reloc_ok;
10069}
10070
0855e32b
NS		 10071/* Handle TLS relaxations. Relaxing is possible for symbols that use
10072 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10073 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10074
10075 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10076 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10077 case of error.
10078
10079 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10080 the pre-relaxed code. It would be nice if the relocs were updated
10081 to match the optimization. */
0855e32b 10082
b38cadfb 10083static bfd_reloc_status_type
0855e32b 10084elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10085 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10086 Elf_Internal_Rela *rel, unsigned long is_local)
10087{
10088 unsigned long insn;
b38cadfb 10089
0855e32b
NS		 10090 switch (ELF32_R_TYPE (rel->r_info))
10091 {
10092 default:
10093 return bfd_reloc_notsupported;
b38cadfb 10094
0855e32b
NS		 10095 case R_ARM_TLS_GOTDESC:
10096 if (is_local)
10097 insn = 0;
10098 else
10099 {
10100 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10101 if (insn & 1)
10102 insn -= 5; /* THUMB */
10103 else
10104 insn -= 8; /* ARM */
10105 }
10106 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10107 return bfd_reloc_continue;
10108
10109 case R_ARM_THM_TLS_DESCSEQ:
10110 /* Thumb insn. */
10111 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10112 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10113 {
10114 if (is_local)
10115 /* nop */
10116 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10117 }
10118 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10119 {
10120 if (is_local)
10121 /* nop */
10122 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10123 else
10124 /* ldr rx,[ry] */
10125 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10126 }
10127 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10128 {
10129 if (is_local)
10130 /* nop */
10131 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10132 else
10133 /* mov r0, rx */
10134 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10135 contents + rel->r_offset);
10136 }
10137 else
10138 {
10139 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10140 /* It's a 32 bit instruction, fetch the rest of it for
10141 error generation. */
10142 insn = (insn << 16)
10143 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10144 _bfd_error_handler
695344c0 10145 /* xgettext:c-format */
2dcf00ce 10146 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10147 "unexpected %s instruction '%#lx' in TLS trampoline"),
10148 input_bfd, input_sec, (uint64_t) rel->r_offset,
10149 "Thumb", insn);
0855e32b
NS		 10150 return bfd_reloc_notsupported;
10151 }
10152 break;
b38cadfb 10153
0855e32b
NS		 10154 case R_ARM_TLS_DESCSEQ:
10155 /* arm insn. */
10156 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10157 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10158 {
10159 if (is_local)
10160 /* mov rx, ry */
10161 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10162 contents + rel->r_offset);
10163 }
10164 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10165 {
10166 if (is_local)
10167 /* nop */
10168 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10169 else
10170 /* ldr rx,[ry] */
10171 bfd_put_32 (input_bfd, insn & 0xfffff000,
10172 contents + rel->r_offset);
10173 }
10174 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10175 {
10176 if (is_local)
10177 /* nop */
10178 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10179 else
10180 /* mov r0, rx */
10181 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10182 contents + rel->r_offset);
10183 }
10184 else
10185 {
4eca0228 10186 _bfd_error_handler
695344c0 10187 /* xgettext:c-format */
2dcf00ce 10188 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10189 "unexpected %s instruction '%#lx' in TLS trampoline"),
10190 input_bfd, input_sec, (uint64_t) rel->r_offset,
10191 "ARM", insn);
0855e32b
NS		 10192 return bfd_reloc_notsupported;
10193 }
10194 break;
10195
10196 case R_ARM_TLS_CALL:
10197 /* GD->IE relaxation, turn the instruction into 'nop' or
10198 'ldr r0, [pc,r0]' */
10199 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10200 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10201 break;
b38cadfb 10202
0855e32b 10203 case R_ARM_THM_TLS_CALL:
6a631e86 10204 /* GD->IE relaxation. */
0855e32b
NS		 10205 if (!is_local)
10206 /* add r0,pc; ldr r0, [r0] */
10207 insn = 0x44786800;
60a019a0 10208 else if (using_thumb2 (globals))
0855e32b
NS		 10209 /* nop.w */
10210 insn = 0xf3af8000;
10211 else
10212 /* nop; nop */
10213 insn = 0xbf00bf00;
b38cadfb 10214
0855e32b
NS		 10215 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10216 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10217 break;
10218 }
10219 return bfd_reloc_ok;
10220}
10221
4962c51a
MS		 10222/* For a given value of n, calculate the value of G_n as required to
10223 deal with group relocations. We return it in the form of an
10224 encoded constant-and-rotation, together with the final residual. If n is
10225 specified as less than zero, then final_residual is filled with the
10226 input value and no further action is performed. */
10227
10228static bfd_vma
10229calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10230{
10231 int current_n;
10232 bfd_vma g_n;
10233 bfd_vma encoded_g_n = 0;
10234 bfd_vma residual = value; /* Also known as Y_n. */
10235
10236 for (current_n = 0; current_n <= n; current_n++)
10237 {
10238 int shift;
10239
10240 /* Calculate which part of the value to mask. */
10241 if (residual == 0)
99059e56 10242 shift = 0;
4962c51a 10243 else
99059e56
RM		 10244 {
10245 int msb;
10246
10247 /* Determine the most significant bit in the residual and
10248 align the resulting value to a 2-bit boundary. */
10249 for (msb = 30; msb >= 0; msb -= 2)
00c91124 10250 if (residual & (3u << msb))
99059e56
RM		 10251 break;
10252
10253 /* The desired shift is now (msb - 6), or zero, whichever
10254 is the greater. */
10255 shift = msb - 6;
10256 if (shift < 0)
10257 shift = 0;
10258 }
4962c51a
MS		 10259
10260 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10261 g_n = residual & (0xff << shift);
10262 encoded_g_n = (g_n >> shift)
99059e56 10263 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10264
10265 /* Calculate the residual for the next time around. */
10266 residual &= ~g_n;
10267 }
10268
10269 *final_residual = residual;
10270
10271 return encoded_g_n;
10272}
10273
10274/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10275 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10276
4962c51a 10277static int
906e58ca 10278identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10279{
10280 int opcode = insn & 0x1e00000;
10281
10282 if (opcode == 1 << 23) /* ADD */
10283 return 1;
10284
10285 if (opcode == 1 << 22) /* SUB */
10286 return -1;
10287
10288 return 0;
10289}
10290
252b5132 10291/* Perform a relocation as part of a final link. */
9b485d32 10292
252b5132 10293static bfd_reloc_status_type
07d6d2b8
AM		 10294elf32_arm_final_link_relocate (reloc_howto_type * howto,
10295 bfd * input_bfd,
10296 bfd * output_bfd,
10297 asection * input_section,
10298 bfd_byte * contents,
10299 Elf_Internal_Rela * rel,
10300 bfd_vma value,
10301 struct bfd_link_info * info,
10302 asection * sym_sec,
10303 const char * sym_name,
10304 unsigned char st_type,
10305 enum arm_st_branch_type branch_type,
0945cdfd 10306 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10307 bfd_boolean * unresolved_reloc_p,
10308 char ** error_message)
10309{
10310 unsigned long r_type = howto->type;
10311 unsigned long r_symndx;
10312 bfd_byte * hit_data = contents + rel->r_offset;
10313 bfd_vma * local_got_offsets;
10314 bfd_vma * local_tlsdesc_gotents;
10315 asection * sgot;
10316 asection * splt;
10317 asection * sreloc = NULL;
10318 asection * srelgot;
10319 bfd_vma addend;
10320 bfd_signed_vma signed_addend;
10321 unsigned char dynreloc_st_type;
10322 bfd_vma dynreloc_value;
ba96a88f 10323 struct elf32_arm_link_hash_table * globals;
34e77a92 10324 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10325 union gotplt_union *root_plt;
10326 struct arm_plt_info *arm_plt;
10327 bfd_vma plt_offset;
10328 bfd_vma gotplt_offset;
10329 bfd_boolean has_iplt_entry;
10330 bfd_boolean resolved_to_zero;
f21f3fe0 10331
9c504268 10332 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10333 if (globals == NULL)
10334 return bfd_reloc_notsupported;
9c504268 10335
0ffa91dd 10336 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10337 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10338
10339 /* Some relocation types map to different relocations depending on the
9c504268 10340 target. We pick the right one here. */
eb043451 10341 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10342
10343 /* It is possible to have linker relaxations on some TLS access
10344 models. Update our information here. */
10345 r_type = elf32_arm_tls_transition (info, r_type, h);
10346
eb043451
PB		 10347 if (r_type != howto->type)
10348 howto = elf32_arm_howto_from_type (r_type);
9c504268 10349
34e77a92 10350 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10351 sgot = globals->root.sgot;
252b5132 10352 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10353 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10354
34e77a92
RS		 10355 if (globals->root.dynamic_sections_created)
10356 srelgot = globals->root.srelgot;
10357 else
10358 srelgot = NULL;
10359
252b5132
RH		 10360 r_symndx = ELF32_R_SYM (rel->r_info);
10361
4e7fd91e 10362 if (globals->use_rel)
ba96a88f 10363 {
d2327e47 10364 bfd_vma sign;
4e7fd91e 10365
d2327e47 10366 switch (howto->size)
4e7fd91e 10367 {
d2327e47
AM		 10368 case 0: addend = bfd_get_8 (input_bfd, hit_data); break;
10369 case 1: addend = bfd_get_16 (input_bfd, hit_data); break;
10370 case 2: addend = bfd_get_32 (input_bfd, hit_data); break;
10371 default: addend = 0; break;
4e7fd91e 10372 }
d2327e47
AM		 10373 /* Note: the addend and signed_addend calculated here are
10374 incorrect for any split field. */
10375 addend &= howto->src_mask;
10376 sign = howto->src_mask & ~(howto->src_mask >> 1);
10377 signed_addend = (addend ^ sign) - sign;
10378 signed_addend = (bfd_vma) signed_addend << howto->rightshift;
10379 addend <<= howto->rightshift;
ba96a88f
NC		 10380 }
10381 else
4e7fd91e 10382 addend = signed_addend = rel->r_addend;
f21f3fe0 10383
39f21624
NC		 10384 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10385 are resolving a function call relocation. */
10386 if (using_thumb_only (globals)
10387 && (r_type == R_ARM_THM_CALL
10388 || r_type == R_ARM_THM_JUMP24)
10389 && branch_type == ST_BRANCH_TO_ARM)
10390 branch_type = ST_BRANCH_TO_THUMB;
10391
34e77a92
RS		 10392 /* Record the symbol information that should be used in dynamic
10393 relocations. */
10394 dynreloc_st_type = st_type;
10395 dynreloc_value = value;
10396 if (branch_type == ST_BRANCH_TO_THUMB)
10397 dynreloc_value |= 1;
10398
10399 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10400 VALUE appropriately for relocations that we resolve at link time. */
10401 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10402 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10403 &arm_plt)
34e77a92
RS		 10404 && root_plt->offset != (bfd_vma) -1)
10405 {
10406 plt_offset = root_plt->offset;
10407 gotplt_offset = arm_plt->got_offset;
10408
10409 if (h == NULL || eh->is_iplt)
10410 {
10411 has_iplt_entry = TRUE;
10412 splt = globals->root.iplt;
10413
10414 /* Populate .iplt entries here, because not all of them will
10415 be seen by finish_dynamic_symbol. The lower bit is set if
10416 we have already populated the entry. */
10417 if (plt_offset & 1)
10418 plt_offset--;
10419 else
10420 {
57460bcf
NC		 10421 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10422 -1, dynreloc_value))
10423 root_plt->offset |= 1;
10424 else
10425 return bfd_reloc_notsupported;
34e77a92
RS		 10426 }
10427
10428 /* Static relocations always resolve to the .iplt entry. */
10429 st_type = STT_FUNC;
10430 value = (splt->output_section->vma
10431 + splt->output_offset
10432 + plt_offset);
10433 branch_type = ST_BRANCH_TO_ARM;
10434
10435 /* If there are non-call relocations that resolve to the .iplt
10436 entry, then all dynamic ones must too. */
10437 if (arm_plt->noncall_refcount != 0)
10438 {
10439 dynreloc_st_type = st_type;
10440 dynreloc_value = value;
10441 }
10442 }
10443 else
10444 /* We populate the .plt entry in finish_dynamic_symbol. */
10445 splt = globals->root.splt;
10446 }
10447 else
10448 {
10449 splt = NULL;
10450 plt_offset = (bfd_vma) -1;
10451 gotplt_offset = (bfd_vma) -1;
10452 }
10453
95b03e4a
L		 10454 resolved_to_zero = (h != NULL
10455 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10456
252b5132
RH		 10457 switch (r_type)
10458 {
10459 case R_ARM_NONE:
28a094c2
DJ		 10460 /* We don't need to find a value for this symbol. It's just a
10461 marker. */
10462 *unresolved_reloc_p = FALSE;
252b5132
RH		 10463 return bfd_reloc_ok;
10464
00a97672 10465 case R_ARM_ABS12:
90c14f0c 10466 if (globals->root.target_os != is_vxworks)
00a97672 10467 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10468 /* Fall through. */
00a97672 10469
252b5132
RH		 10470 case R_ARM_PC24:
10471 case R_ARM_ABS32:
bb224fc3 10472 case R_ARM_ABS32_NOI:
252b5132 10473 case R_ARM_REL32:
bb224fc3 10474 case R_ARM_REL32_NOI:
5b5bb741
PB		 10475 case R_ARM_CALL:
10476 case R_ARM_JUMP24:
dfc5f959 10477 case R_ARM_XPC25:
eb043451 10478 case R_ARM_PREL31:
7359ea65 10479 case R_ARM_PLT32:
7359ea65
DJ		 10480 /* Handle relocations which should use the PLT entry. ABS32/REL32
10481 will use the symbol's value, which may point to a PLT entry, but we
10482 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10483 branches in this object should go to it, except if the PLT is too
10484 far away, in which case a long branch stub should be inserted. */
bb224fc3 10485 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10486 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10487 && r_type != R_ARM_CALL
10488 && r_type != R_ARM_JUMP24
10489 && r_type != R_ARM_PLT32)
34e77a92 10490 && plt_offset != (bfd_vma) -1)
7359ea65 10491 {
34e77a92
RS		 10492 /* If we've created a .plt section, and assigned a PLT entry
10493 to this function, it must either be a STT_GNU_IFUNC reference
10494 or not be known to bind locally. In other cases, we should
10495 have cleared the PLT entry by now. */
10496 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10497
10498 value = (splt->output_section->vma
10499 + splt->output_offset
34e77a92 10500 + plt_offset);
0945cdfd 10501 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10502 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10503 contents, rel->r_offset, value,
00a97672 10504 rel->r_addend);
7359ea65
DJ		 10505 }
10506
67687978
PB		 10507 /* When generating a shared object or relocatable executable, these
10508 relocations are copied into the output file to be resolved at
10509 run time. */
0e1862bb 10510 if ((bfd_link_pic (info)
e8b09b87
CL		 10511 || globals->root.is_relocatable_executable
10512 || globals->fdpic_p)
7359ea65 10513 && (input_section->flags & SEC_ALLOC)
90c14f0c 10514 && !(globals->root.target_os == is_vxworks
3348747a
NS		 10515 && strcmp (input_section->output_section->name,
10516 ".tls_vars") == 0)
bb224fc3 10517 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10518 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10519 && !(input_bfd == globals->stub_bfd
10520 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10521 && (h == NULL
95b03e4a
L		 10522 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10523 && !resolved_to_zero)
7359ea65
DJ		 10524 || h->root.type != bfd_link_hash_undefweak)
10525 && r_type != R_ARM_PC24
5b5bb741
PB		 10526 && r_type != R_ARM_CALL
10527 && r_type != R_ARM_JUMP24
ee06dc07 10528 && r_type != R_ARM_PREL31
7359ea65 10529 && r_type != R_ARM_PLT32)
252b5132 10530 {
947216bf 10531 Elf_Internal_Rela outrel;
b34976b6 10532 bfd_boolean skip, relocate;
e8b09b87 10533 int isrofixup = 0;
f21f3fe0 10534
52db4ec2
JW		 10535 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10536 && !h->def_regular)
10537 {
10538 char *v = _("shared object");
10539
0e1862bb 10540 if (bfd_link_executable (info))
52db4ec2
JW		 10541 v = _("PIE executable");
10542
4eca0228 10543 _bfd_error_handler
871b3ab2 10544 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10545 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10546 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10547 return bfd_reloc_notsupported;
10548 }
10549
0945cdfd
DJ		 10550 *unresolved_reloc_p = FALSE;
10551
34e77a92 10552 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10553 {
83bac4b0
NC		 10554 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10555 ! globals->use_rel);
f21f3fe0 10556
83bac4b0 10557 if (sreloc == NULL)
252b5132 10558 return bfd_reloc_notsupported;
252b5132 10559 }
f21f3fe0 10560
b34976b6
AM		 10561 skip = FALSE;
10562 relocate = FALSE;
f21f3fe0 10563
00a97672 10564 outrel.r_addend = addend;
c629eae0
JJ		 10565 outrel.r_offset =
10566 _bfd_elf_section_offset (output_bfd, info, input_section,
10567 rel->r_offset);
10568 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10569 skip = TRUE;
0bb2d96a 10570 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10571 skip = TRUE, relocate = TRUE;
252b5132
RH		 10572 outrel.r_offset += (input_section->output_section->vma
10573 + input_section->output_offset);
f21f3fe0 10574
252b5132 10575 if (skip)
0bb2d96a 10576 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10577 else if (h != NULL
10578 && h->dynindx != -1
0e1862bb 10579 && (!bfd_link_pic (info)
1dcb9720
JW		 10580 || !(bfd_link_pie (info)
10581 || SYMBOLIC_BIND (info, h))
f5385ebf 10582 || !h->def_regular))
5e681ec4 10583 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10584 else
10585 {
a16385dc
MM		 10586 int symbol;
10587
5e681ec4 10588 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10589 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10590 || (globals->fdpic_p && !bfd_link_pic(info)));
90c14f0c 10591 if (globals->root.target_os == is_symbian)
6366ff1e 10592 {
74541ad4
AM		 10593 asection *osec;
10594
6366ff1e
MM		 10595 /* On Symbian OS, the data segment and text segement
10596 can be relocated independently. Therefore, we
10597 must indicate the segment to which this
10598 relocation is relative. The BPABI allows us to
10599 use any symbol in the right segment; we just use
10600 the section symbol as it is convenient. (We
10601 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10602 will not appear in the dynamic symbol table.)
10603
10604 Note that the dynamic linker ignores the section
10605 symbol value, so we don't subtract osec->vma
10606 from the emitted reloc addend. */
10dbd1f3 10607 if (sym_sec)
74541ad4 10608 osec = sym_sec->output_section;
10dbd1f3 10609 else
74541ad4 10610 osec = input_section->output_section;
2ac865ac
AM		 10611 symbol = 0;
10612 if (osec && elf_section_data (osec))
10613 symbol = elf_section_data (osec)->dynindx;
74541ad4
AM		 10614 if (symbol == 0)
10615 {
10616 struct elf_link_hash_table *htab = elf_hash_table (info);
10617
10618 if ((osec->flags & SEC_READONLY) == 0
10619 && htab->data_index_section != NULL)
10620 osec = htab->data_index_section;
10621 else
10622 osec = htab->text_index_section;
10623 symbol = elf_section_data (osec)->dynindx;
10624 }
6366ff1e
MM		 10625 BFD_ASSERT (symbol != 0);
10626 }
a16385dc
MM		 10627 else
10628 /* On SVR4-ish systems, the dynamic loader cannot
10629 relocate the text and data segments independently,
10630 so the symbol does not matter. */
10631 symbol = 0;
34e77a92
RS		 10632 if (dynreloc_st_type == STT_GNU_IFUNC)
10633 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10634 to the .iplt entry. Instead, every non-call reference
10635 must use an R_ARM_IRELATIVE relocation to obtain the
10636 correct run-time address. */
10637 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10638 else if (globals->fdpic_p && !bfd_link_pic(info))
10639 isrofixup = 1;
34e77a92
RS		 10640 else
10641 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10642 if (globals->use_rel)
10643 relocate = TRUE;
10644 else
34e77a92 10645 outrel.r_addend += dynreloc_value;
252b5132 10646 }
f21f3fe0 10647
e8b09b87
CL		 10648 if (isrofixup)
10649 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10650 else
10651 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10652
f21f3fe0 10653 /* If this reloc is against an external symbol, we do not want to
252b5132 10654 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10655 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10656 if (! relocate)
10657 return bfd_reloc_ok;
9a5aca8c 10658
f21f3fe0 10659 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10660 contents, rel->r_offset,
10661 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10662 }
10663 else switch (r_type)
10664 {
00a97672
RS		 10665 case R_ARM_ABS12:
10666 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10667
dfc5f959 10668 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10669 case R_ARM_CALL:
10670 case R_ARM_JUMP24:
8029a119 10671 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10672 case R_ARM_PLT32:
906e58ca 10673 {
906e58ca
NC		 10674 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10675
dfc5f959 10676 if (r_type == R_ARM_XPC25)
252b5132 10677 {
dfc5f959
NC		 10678 /* Check for Arm calling Arm function. */
10679 /* FIXME: Should we translate the instruction into a BL
10680 instruction instead ? */
35fc36a8 10681 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10682 _bfd_error_handler
90b6238f
AM		 10683 (_("\%pB: warning: %s BLX instruction targets"
10684 " %s function '%s'"),
10685 input_bfd, "ARM",
10686 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10687 }
155d87d7 10688 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10689 {
10690 /* Check for Arm calling Thumb function. */
35fc36a8 10691 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10692 {
f2a9dd69
DJ		 10693 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10694 output_bfd, input_section,
10695 hit_data, sym_sec, rel->r_offset,
10696 signed_addend, value,
10697 error_message))
10698 return bfd_reloc_ok;
10699 else
10700 return bfd_reloc_dangerous;
dfc5f959 10701 }
252b5132 10702 }
ba96a88f 10703
906e58ca 10704 /* Check if a stub has to be inserted because the
8029a119 10705 destination is too far or we are changing mode. */
155d87d7
CL		 10706 if ( r_type == R_ARM_CALL
10707 || r_type == R_ARM_JUMP24
10708 || r_type == R_ARM_PLT32)
906e58ca 10709 {
fe33d2fa
CL		 10710 enum elf32_arm_stub_type stub_type = arm_stub_none;
10711 struct elf32_arm_link_hash_entry *hash;
10712
10713 hash = (struct elf32_arm_link_hash_entry *) h;
10714 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10715 st_type, &branch_type,
10716 hash, value, sym_sec,
fe33d2fa 10717 input_bfd, sym_name);
5fa9e92f 10718
fe33d2fa 10719 if (stub_type != arm_stub_none)
906e58ca
NC		 10720 {
10721 /* The target is out of reach, so redirect the
10722 branch to the local stub for this function. */
906e58ca
NC		 10723 stub_entry = elf32_arm_get_stub_entry (input_section,
10724 sym_sec, h,
fe33d2fa
CL		 10725 rel, globals,
10726 stub_type);
9cd3e4e5
NC		 10727 {
10728 if (stub_entry != NULL)
10729 value = (stub_entry->stub_offset
10730 + stub_entry->stub_sec->output_offset
10731 + stub_entry->stub_sec->output_section->vma);
10732
10733 if (plt_offset != (bfd_vma) -1)
10734 *unresolved_reloc_p = FALSE;
10735 }
906e58ca 10736 }
fe33d2fa
CL		 10737 else
10738 {
10739 /* If the call goes through a PLT entry, make sure to
10740 check distance to the right destination address. */
34e77a92 10741 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10742 {
10743 value = (splt->output_section->vma
10744 + splt->output_offset
34e77a92 10745 + plt_offset);
fe33d2fa
CL		 10746 *unresolved_reloc_p = FALSE;
10747 /* The PLT entry is in ARM mode, regardless of the
10748 target function. */
35fc36a8 10749 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10750 }
10751 }
906e58ca
NC		 10752 }
10753
dea514f5
PB		 10754 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10755 where:
10756 S is the address of the symbol in the relocation.
10757 P is address of the instruction being relocated.
10758 A is the addend (extracted from the instruction) in bytes.
10759
10760 S is held in 'value'.
10761 P is the base address of the section containing the
10762 instruction plus the offset of the reloc into that
10763 section, ie:
10764 (input_section->output_section->vma +
10765 input_section->output_offset +
10766 rel->r_offset).
10767 A is the addend, converted into bytes, ie:
10768 (signed_addend * 4)
10769
10770 Note: None of these operations have knowledge of the pipeline
10771 size of the processor, thus it is up to the assembler to
10772 encode this information into the addend. */
10773 value -= (input_section->output_section->vma
10774 + input_section->output_offset);
10775 value -= rel->r_offset;
d2327e47 10776 value += signed_addend;
23080146 10777
dcb5e6e6
NC		 10778 signed_addend = value;
10779 signed_addend >>= howto->rightshift;
9a5aca8c 10780
5ab79981 10781 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10782 the next instruction unless a PLT entry will be created.
77b4f08f 10783 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10784 The jump to the next instruction is optimized as a NOP depending
10785 on the architecture. */
ffcb4889 10786 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10787 && plt_offset == (bfd_vma) -1)
77b4f08f 10788 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10789 {
cd1dac3d
DG		 10790 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10791
10792 if (arch_has_arm_nop (globals))
10793 value |= 0x0320f000;
10794 else
10795 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10796 }
10797 else
59f2c4e7 10798 {
9b485d32 10799 /* Perform a signed range check. */
dcb5e6e6 10800 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10801 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10802 return bfd_reloc_overflow;
9a5aca8c 10803
5ab79981 10804 addend = (value & 2);
39b41c9c 10805
5ab79981
PB		 10806 value = (signed_addend & howto->dst_mask)
10807 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10808
5ab79981
PB		 10809 if (r_type == R_ARM_CALL)
10810 {
155d87d7 10811 /* Set the H bit in the BLX instruction. */
35fc36a8 10812 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10813 {
10814 if (addend)
10815 value |= (1 << 24);
10816 else
10817 value &= ~(bfd_vma)(1 << 24);
10818 }
10819
5ab79981 10820 /* Select the correct instruction (BL or BLX). */
906e58ca 10821 /* Only if we are not handling a BL to a stub. In this
8029a119 10822 case, mode switching is performed by the stub. */
35fc36a8 10823 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10824 value |= (1 << 28);
63e1a0fc 10825 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10826 {
10827 value &= ~(bfd_vma)(1 << 28);
10828 value |= (1 << 24);
10829 }
39b41c9c
PB		 10830 }
10831 }
906e58ca 10832 }
252b5132 10833 break;
f21f3fe0 10834
252b5132
RH		 10835 case R_ARM_ABS32:
10836 value += addend;
35fc36a8 10837 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10838 value |= 1;
10839 break;
f21f3fe0 10840
bb224fc3
MS		 10841 case R_ARM_ABS32_NOI:
10842 value += addend;
10843 break;
10844
252b5132 10845 case R_ARM_REL32:
a8bc6c78 10846 value += addend;
35fc36a8 10847 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10848 value |= 1;
252b5132 10849 value -= (input_section->output_section->vma
62efb346 10850 + input_section->output_offset + rel->r_offset);
252b5132 10851 break;
eb043451 10852
bb224fc3
MS		 10853 case R_ARM_REL32_NOI:
10854 value += addend;
10855 value -= (input_section->output_section->vma
10856 + input_section->output_offset + rel->r_offset);
10857 break;
10858
eb043451
PB		 10859 case R_ARM_PREL31:
10860 value -= (input_section->output_section->vma
10861 + input_section->output_offset + rel->r_offset);
10862 value += signed_addend;
10863 if (! h || h->root.type != bfd_link_hash_undefweak)
10864 {
8029a119 10865 /* Check for overflow. */
eb043451
PB		 10866 if ((value ^ (value >> 1)) & (1 << 30))
10867 return bfd_reloc_overflow;
10868 }
10869 value &= 0x7fffffff;
10870 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10871 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10872 value |= 1;
10873 break;
252b5132 10874 }
f21f3fe0 10875
252b5132
RH		 10876 bfd_put_32 (input_bfd, value, hit_data);
10877 return bfd_reloc_ok;
10878
10879 case R_ARM_ABS8:
10880 value += addend;
4e67d4ca
DG		 10881
10882 /* There is no way to tell whether the user intended to use a signed or
10883 unsigned addend. When checking for overflow we accept either,
10884 as specified by the AAELF. */
10885 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10886 return bfd_reloc_overflow;
10887
10888 bfd_put_8 (input_bfd, value, hit_data);
10889 return bfd_reloc_ok;
10890
10891 case R_ARM_ABS16:
10892 value += addend;
10893
4e67d4ca
DG		 10894 /* See comment for R_ARM_ABS8. */
10895 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10896 return bfd_reloc_overflow;
10897
10898 bfd_put_16 (input_bfd, value, hit_data);
10899 return bfd_reloc_ok;
10900
252b5132 10901 case R_ARM_THM_ABS5:
9b485d32 10902 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10903 if (globals->use_rel)
10904 {
10905 /* Need to refetch addend. */
10906 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10907 /* ??? Need to determine shift amount from operand size. */
10908 addend >>= howto->rightshift;
10909 }
252b5132
RH		 10910 value += addend;
10911
10912 /* ??? Isn't value unsigned? */
10913 if ((long) value > 0x1f || (long) value < -0x10)
10914 return bfd_reloc_overflow;
10915
10916 /* ??? Value needs to be properly shifted into place first. */
10917 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10918 bfd_put_16 (input_bfd, value, hit_data);
10919 return bfd_reloc_ok;
10920
2cab6cc3
MS		 10921 case R_ARM_THM_ALU_PREL_11_0:
10922 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10923 {
10924 bfd_vma insn;
10925 bfd_signed_vma relocation;
10926
10927 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10928 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10929
99059e56
RM		 10930 if (globals->use_rel)
10931 {
10932 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10933 | ((insn & (1 << 26)) >> 15);
10934 if (insn & 0xf00000)
10935 signed_addend = -signed_addend;
10936 }
2cab6cc3
MS		 10937
10938 relocation = value + signed_addend;
79f08007 10939 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10940 + input_section->output_offset
10941 + rel->r_offset);
2cab6cc3 10942
8c65b54f
CS		 10943 /* PR 21523: Use an absolute value. The user of this reloc will
10944 have already selected an ADD or SUB insn appropriately. */
453f8e1e 10945 value = llabs (relocation);
2cab6cc3 10946
99059e56
RM		 10947 if (value >= 0x1000)
10948 return bfd_reloc_overflow;
2cab6cc3 10949
e645cf40
AG		 10950 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10951 if (branch_type == ST_BRANCH_TO_THUMB)
10952 value |= 1;
10953
2cab6cc3 10954 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10955 | ((value & 0x700) << 4)
10956 | ((value & 0x800) << 15);
10957 if (relocation < 0)
10958 insn |= 0xa00000;
2cab6cc3
MS		 10959
10960 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10961 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10962
99059e56 10963 return bfd_reloc_ok;
2cab6cc3
MS		 10964 }
10965
e1ec24c6
NC		 10966 case R_ARM_THM_PC8:
10967 /* PR 10073: This reloc is not generated by the GNU toolchain,
10968 but it is supported for compatibility with third party libraries
10969 generated by other compilers, specifically the ARM/IAR. */
10970 {
10971 bfd_vma insn;
10972 bfd_signed_vma relocation;
10973
10974 insn = bfd_get_16 (input_bfd, hit_data);
10975
99059e56 10976 if (globals->use_rel)
79f08007 10977 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10978
10979 relocation = value + addend;
79f08007 10980 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10981 + input_section->output_offset
10982 + rel->r_offset);
e1ec24c6 10983
b6518b38 10984 value = relocation;
e1ec24c6
NC		 10985
10986 /* We do not check for overflow of this reloc. Although strictly
10987 speaking this is incorrect, it appears to be necessary in order
10988 to work with IAR generated relocs. Since GCC and GAS do not
10989 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10990 a problem for them. */
10991 value &= 0x3fc;
10992
10993 insn = (insn & 0xff00) | (value >> 2);
10994
10995 bfd_put_16 (input_bfd, insn, hit_data);
10996
99059e56 10997 return bfd_reloc_ok;
e1ec24c6
NC		 10998 }
10999
2cab6cc3
MS		 11000 case R_ARM_THM_PC12:
11001 /* Corresponds to: ldr.w reg, [pc, #offset]. */
11002 {
11003 bfd_vma insn;
11004 bfd_signed_vma relocation;
11005
11006 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 11007 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 11008
99059e56
RM		 11009 if (globals->use_rel)
11010 {
11011 signed_addend = insn & 0xfff;
11012 if (!(insn & (1 << 23)))
11013 signed_addend = -signed_addend;
11014 }
2cab6cc3
MS		 11015
11016 relocation = value + signed_addend;
79f08007 11017 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11018 + input_section->output_offset
11019 + rel->r_offset);
2cab6cc3 11020
b6518b38 11021 value = relocation;
2cab6cc3 11022
99059e56
RM		 11023 if (value >= 0x1000)
11024 return bfd_reloc_overflow;
2cab6cc3
MS		 11025
11026 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 11027 if (relocation >= 0)
11028 insn |= (1 << 23);
2cab6cc3
MS		 11029
11030 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11031 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11032
99059e56 11033 return bfd_reloc_ok;
2cab6cc3
MS		 11034 }
11035
dfc5f959 11036 case R_ARM_THM_XPC22:
c19d1205 11037 case R_ARM_THM_CALL:
bd97cb95 11038 case R_ARM_THM_JUMP24:
dfc5f959 11039 /* Thumb BL (branch long instruction). */
252b5132 11040 {
b34976b6 11041 bfd_vma relocation;
99059e56 11042 bfd_vma reloc_sign;
b34976b6
AM		 11043 bfd_boolean overflow = FALSE;
11044 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11045 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11046 bfd_signed_vma reloc_signed_max;
11047 bfd_signed_vma reloc_signed_min;
b34976b6 11048 bfd_vma check;
252b5132 11049 bfd_signed_vma signed_check;
e95de063 11050 int bitsize;
cd1dac3d 11051 const int thumb2 = using_thumb2 (globals);
5e866f5a 11052 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11053
5ab79981 11054 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11055 the next instruction unless a PLT entry will be created.
11056 The jump to the next instruction is optimized as a NOP.W for
11057 Thumb-2 enabled architectures. */
19540007 11058 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11059 && plt_offset == (bfd_vma) -1)
5ab79981 11060 {
60a019a0 11061 if (thumb2)
cd1dac3d
DG		 11062 {
11063 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11064 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11065 }
11066 else
11067 {
11068 bfd_put_16 (input_bfd, 0xe000, hit_data);
11069 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11070 }
5ab79981
PB		 11071 return bfd_reloc_ok;
11072 }
11073
e95de063 11074 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11075 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11076 if (globals->use_rel)
11077 {
99059e56
RM		 11078 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11079 bfd_vma upper = upper_insn & 0x3ff;
11080 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11081 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11082 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11083 bfd_vma i1 = j1 ^ s ? 0 : 1;
11084 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11085
99059e56
RM		 11086 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11087 /* Sign extend. */
11088 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11089
4e7fd91e
PB		 11090 signed_addend = addend;
11091 }
cb1afa5c 11092
dfc5f959
NC		 11093 if (r_type == R_ARM_THM_XPC22)
11094 {
11095 /* Check for Thumb to Thumb call. */
11096 /* FIXME: Should we translate the instruction into a BL
11097 instruction instead ? */
35fc36a8 11098 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11099 _bfd_error_handler
90b6238f
AM		 11100 (_("%pB: warning: %s BLX instruction targets"
11101 " %s function '%s'"),
11102 input_bfd, "Thumb",
11103 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11104 }
11105 else
252b5132 11106 {
dfc5f959
NC		 11107 /* If it is not a call to Thumb, assume call to Arm.
11108 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11109 function call at all, but rather a long jump. Calls through
11110 the PLT do not require stubs. */
34e77a92 11111 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11112 {
bd97cb95 11113 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11114 {
11115 /* Convert BL to BLX. */
11116 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11117 }
155d87d7
CL		 11118 else if (( r_type != R_ARM_THM_CALL)
11119 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11120 {
11121 if (elf32_thumb_to_arm_stub
11122 (info, sym_name, input_bfd, output_bfd, input_section,
11123 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11124 error_message))
11125 return bfd_reloc_ok;
11126 else
11127 return bfd_reloc_dangerous;
11128 }
da5938a2 11129 }
35fc36a8
RS		 11130 else if (branch_type == ST_BRANCH_TO_THUMB
11131 && globals->use_blx
bd97cb95 11132 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11133 {
11134 /* Make sure this is a BL. */
11135 lower_insn |= 0x1800;
11136 }
252b5132 11137 }
f21f3fe0 11138
fe33d2fa 11139 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11140 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11141 {
11142 /* Check if a stub has to be inserted because the destination
8029a119 11143 is too far. */
fe33d2fa
CL		 11144 struct elf32_arm_stub_hash_entry *stub_entry;
11145 struct elf32_arm_link_hash_entry *hash;
11146
11147 hash = (struct elf32_arm_link_hash_entry *) h;
11148
11149 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11150 st_type, &branch_type,
11151 hash, value, sym_sec,
fe33d2fa
CL		 11152 input_bfd, sym_name);
11153
11154 if (stub_type != arm_stub_none)
906e58ca
NC		 11155 {
11156 /* The target is out of reach or we are changing modes, so
11157 redirect the branch to the local stub for this
11158 function. */
11159 stub_entry = elf32_arm_get_stub_entry (input_section,
11160 sym_sec, h,
fe33d2fa
CL		 11161 rel, globals,
11162 stub_type);
906e58ca 11163 if (stub_entry != NULL)
9cd3e4e5
NC		 11164 {
11165 value = (stub_entry->stub_offset
11166 + stub_entry->stub_sec->output_offset
11167 + stub_entry->stub_sec->output_section->vma);
11168
11169 if (plt_offset != (bfd_vma) -1)
11170 *unresolved_reloc_p = FALSE;
11171 }
906e58ca 11172
f4ac8484 11173 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11174 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11175 {
11176 if ((stub_entry
11177 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11178 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11179 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11180 }
906e58ca
NC		 11181 }
11182 }
11183
fe33d2fa 11184 /* Handle calls via the PLT. */
34e77a92 11185 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11186 {
11187 value = (splt->output_section->vma
11188 + splt->output_offset
34e77a92 11189 + plt_offset);
fe33d2fa 11190
eed94f8f
NC		 11191 if (globals->use_blx
11192 && r_type == R_ARM_THM_CALL
11193 && ! using_thumb_only (globals))
fe33d2fa
CL		 11194 {
11195 /* If the Thumb BLX instruction is available, convert
11196 the BL to a BLX instruction to call the ARM-mode
11197 PLT entry. */
11198 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11199 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11200 }
11201 else
11202 {
eed94f8f
NC		 11203 if (! using_thumb_only (globals))
11204 /* Target the Thumb stub before the ARM PLT entry. */
11205 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11206 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11207 }
11208 *unresolved_reloc_p = FALSE;
11209 }
11210
ba96a88f 11211 relocation = value + signed_addend;
f21f3fe0 11212
252b5132 11213 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11214 + input_section->output_offset
11215 + rel->r_offset);
9a5aca8c 11216
252b5132
RH		 11217 check = relocation >> howto->rightshift;
11218
11219 /* If this is a signed value, the rightshift just dropped
11220 leading 1 bits (assuming twos complement). */
11221 if ((bfd_signed_vma) relocation >= 0)
11222 signed_check = check;
11223 else
11224 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11225
e95de063
MS		 11226 /* Calculate the permissable maximum and minimum values for
11227 this relocation according to whether we're relocating for
11228 Thumb-2 or not. */
11229 bitsize = howto->bitsize;
5e866f5a 11230 if (!thumb2_bl)
e95de063 11231 bitsize -= 2;
f6ebfac0 11232 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11233 reloc_signed_min = ~reloc_signed_max;
11234
252b5132 11235 /* Assumes two's complement. */
ba96a88f 11236 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11237 overflow = TRUE;
252b5132 11238
bd97cb95 11239 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11240 /* For a BLX instruction, make sure that the relocation is rounded up
11241 to a word boundary. This follows the semantics of the instruction
11242 which specifies that bit 1 of the target address will come from bit
11243 1 of the base address. */
11244 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11245
e95de063
MS		 11246 /* Put RELOCATION back into the insn. Assumes two's complement.
11247 We use the Thumb-2 encoding, which is safe even if dealing with
11248 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11249 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11250 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11251 | ((relocation >> 12) & 0x3ff)
11252 | (reloc_sign << 10);
906e58ca 11253 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11254 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11255 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11256 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11257
252b5132
RH		 11258 /* Put the relocated value back in the object file: */
11259 bfd_put_16 (input_bfd, upper_insn, hit_data);
11260 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11261
11262 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11263 }
11264 break;
11265
c19d1205
ZW		 11266 case R_ARM_THM_JUMP19:
11267 /* Thumb32 conditional branch instruction. */
11268 {
11269 bfd_vma relocation;
11270 bfd_boolean overflow = FALSE;
11271 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11272 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11273 bfd_signed_vma reloc_signed_max = 0xffffe;
11274 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11275 bfd_signed_vma signed_check;
07d6d2b8 11276 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11277 struct elf32_arm_stub_hash_entry *stub_entry;
11278 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11279
11280 /* Need to refetch the addend, reconstruct the top three bits,
11281 and squish the two 11 bit pieces together. */
11282 if (globals->use_rel)
11283 {
11284 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11285 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11286 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11287 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11288 bfd_vma lower = (lower_insn & 0x07ff);
11289
a00a1f35
MS		 11290 upper |= J1 << 6;
11291 upper |= J2 << 7;
11292 upper |= (!S) << 8;
c19d1205
ZW		 11293 upper -= 0x0100; /* Sign extend. */
11294
11295 addend = (upper << 12) | (lower << 1);
11296 signed_addend = addend;
11297 }
11298
bd97cb95 11299 /* Handle calls via the PLT. */
34e77a92 11300 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11301 {
11302 value = (splt->output_section->vma
11303 + splt->output_offset
34e77a92 11304 + plt_offset);
bd97cb95
DJ		 11305 /* Target the Thumb stub before the ARM PLT entry. */
11306 value -= PLT_THUMB_STUB_SIZE;
11307 *unresolved_reloc_p = FALSE;
11308 }
11309
c5423981
TG		 11310 hash = (struct elf32_arm_link_hash_entry *)h;
11311
11312 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11313 st_type, &branch_type,
11314 hash, value, sym_sec,
11315 input_bfd, sym_name);
c5423981
TG		 11316 if (stub_type != arm_stub_none)
11317 {
11318 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11319 sym_sec, h,
11320 rel, globals,
11321 stub_type);
c5423981
TG		 11322 if (stub_entry != NULL)
11323 {
07d6d2b8
AM		 11324 value = (stub_entry->stub_offset
11325 + stub_entry->stub_sec->output_offset
11326 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11327 }
11328 }
c19d1205 11329
99059e56 11330 relocation = value + signed_addend;
c19d1205
ZW		 11331 relocation -= (input_section->output_section->vma
11332 + input_section->output_offset
11333 + rel->r_offset);
a00a1f35 11334 signed_check = (bfd_signed_vma) relocation;
c19d1205 11335
c19d1205
ZW		 11336 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11337 overflow = TRUE;
11338
11339 /* Put RELOCATION back into the insn. */
11340 {
11341 bfd_vma S = (relocation & 0x00100000) >> 20;
11342 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11343 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11344 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11345 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11346
a00a1f35 11347 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11348 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11349 }
11350
11351 /* Put the relocated value back in the object file: */
11352 bfd_put_16 (input_bfd, upper_insn, hit_data);
11353 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11354
11355 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11356 }
11357
11358 case R_ARM_THM_JUMP11:
11359 case R_ARM_THM_JUMP8:
11360 case R_ARM_THM_JUMP6:
51c5503b
NC		 11361 /* Thumb B (branch) instruction). */
11362 {
6cf9e9fe 11363 bfd_signed_vma relocation;
51c5503b
NC		 11364 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11365 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11366 bfd_signed_vma signed_check;
11367
c19d1205
ZW		 11368 /* CZB cannot jump backward. */
11369 if (r_type == R_ARM_THM_JUMP6)
6cf9e9fe 11370 {
d2327e47
AM		 11371 reloc_signed_min = 0;
11372 if (globals->use_rel)
11373 signed_addend = ((addend & 0x200) >> 3) | ((addend & 0xf8) >> 2);
6cf9e9fe 11374 }
d2327e47 11375
6cf9e9fe 11376 relocation = value + signed_addend;
51c5503b
NC		 11377
11378 relocation -= (input_section->output_section->vma
11379 + input_section->output_offset
11380 + rel->r_offset);
11381
6cf9e9fe
NC		 11382 relocation >>= howto->rightshift;
11383 signed_check = relocation;
c19d1205
ZW		 11384
11385 if (r_type == R_ARM_THM_JUMP6)
11386 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11387 else
11388 relocation &= howto->dst_mask;
51c5503b 11389 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11390
51c5503b
NC		 11391 bfd_put_16 (input_bfd, relocation, hit_data);
11392
11393 /* Assumes two's complement. */
11394 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11395 return bfd_reloc_overflow;
11396
11397 return bfd_reloc_ok;
11398 }
cedb70c5 11399
8375c36b
PB		 11400 case R_ARM_ALU_PCREL7_0:
11401 case R_ARM_ALU_PCREL15_8:
11402 case R_ARM_ALU_PCREL23_15:
11403 {
11404 bfd_vma insn;
11405 bfd_vma relocation;
11406
11407 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11408 if (globals->use_rel)
11409 {
11410 /* Extract the addend. */
11411 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11412 signed_addend = addend;
11413 }
8375c36b
PB		 11414 relocation = value + signed_addend;
11415
11416 relocation -= (input_section->output_section->vma
11417 + input_section->output_offset
11418 + rel->r_offset);
11419 insn = (insn & ~0xfff)
11420 | ((howto->bitpos << 7) & 0xf00)
11421 | ((relocation >> howto->bitpos) & 0xff);
11422 bfd_put_32 (input_bfd, value, hit_data);
11423 }
11424 return bfd_reloc_ok;
11425
252b5132
RH		 11426 case R_ARM_GNU_VTINHERIT:
11427 case R_ARM_GNU_VTENTRY:
11428 return bfd_reloc_ok;
11429
c19d1205 11430 case R_ARM_GOTOFF32:
252b5132 11431 /* Relocation is relative to the start of the
99059e56 11432 global offset table. */
252b5132
RH		 11433
11434 BFD_ASSERT (sgot != NULL);
11435 if (sgot == NULL)
99059e56 11436 return bfd_reloc_notsupported;
9a5aca8c 11437
cedb70c5 11438 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11439 address by one, so that attempts to call the function pointer will
11440 correctly interpret it as Thumb code. */
35fc36a8 11441 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11442 value += 1;
11443
252b5132 11444 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11445 calculation. We always want the start of .got. If we
11446 define _GLOBAL_OFFSET_TABLE in a different way, as is
11447 permitted by the ABI, we might have to change this
11448 calculation. */
252b5132 11449 value -= sgot->output_section->vma;
f21f3fe0 11450 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11451 contents, rel->r_offset, value,
00a97672 11452 rel->r_addend);
252b5132
RH		 11453
11454 case R_ARM_GOTPC:
a7c10850 11455 /* Use global offset table as symbol value. */
252b5132 11456 BFD_ASSERT (sgot != NULL);
f21f3fe0 11457
252b5132 11458 if (sgot == NULL)
99059e56 11459 return bfd_reloc_notsupported;
252b5132 11460
0945cdfd 11461 *unresolved_reloc_p = FALSE;
252b5132 11462 value = sgot->output_section->vma;
f21f3fe0 11463 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11464 contents, rel->r_offset, value,
00a97672 11465 rel->r_addend);
f21f3fe0 11466
252b5132 11467 case R_ARM_GOT32:
eb043451 11468 case R_ARM_GOT_PREL:
252b5132 11469 /* Relocation is to the entry for this symbol in the
99059e56 11470 global offset table. */
252b5132
RH		 11471 if (sgot == NULL)
11472 return bfd_reloc_notsupported;
f21f3fe0 11473
34e77a92
RS		 11474 if (dynreloc_st_type == STT_GNU_IFUNC
11475 && plt_offset != (bfd_vma) -1
11476 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11477 {
11478 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11479 symbol, and the relocation resolves directly to the runtime
11480 target rather than to the .iplt entry. This means that any
11481 .got entry would be the same value as the .igot.plt entry,
11482 so there's no point creating both. */
11483 sgot = globals->root.igotplt;
11484 value = sgot->output_offset + gotplt_offset;
11485 }
11486 else if (h != NULL)
252b5132
RH		 11487 {
11488 bfd_vma off;
f21f3fe0 11489
252b5132
RH		 11490 off = h->got.offset;
11491 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11492 if ((off & 1) != 0)
252b5132 11493 {
b436d854
RS		 11494 /* We have already processsed one GOT relocation against
11495 this symbol. */
11496 off &= ~1;
11497 if (globals->root.dynamic_sections_created
11498 && !SYMBOL_REFERENCES_LOCAL (info, h))
11499 *unresolved_reloc_p = FALSE;
11500 }
11501 else
11502 {
11503 Elf_Internal_Rela outrel;
e8b09b87 11504 int isrofixup = 0;
b436d854 11505
e8b09b87
CL		 11506 if (((h->dynindx != -1) || globals->fdpic_p)
11507 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11508 {
11509 /* If the symbol doesn't resolve locally in a static
11510 object, we have an undefined reference. If the
11511 symbol doesn't resolve locally in a dynamic object,
11512 it should be resolved by the dynamic linker. */
11513 if (globals->root.dynamic_sections_created)
11514 {
11515 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11516 *unresolved_reloc_p = FALSE;
11517 }
11518 else
11519 outrel.r_info = 0;
11520 outrel.r_addend = 0;
11521 }
252b5132
RH		 11522 else
11523 {
34e77a92 11524 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11525 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c 11526 else if (bfd_link_pic (info)
7f026732 11527 && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
99059e56
RM		 11528 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11529 else
2376f038
EB		 11530 {
11531 outrel.r_info = 0;
11532 if (globals->fdpic_p)
11533 isrofixup = 1;
11534 }
34e77a92 11535 outrel.r_addend = dynreloc_value;
b436d854 11536 }
ee29b9fb 11537
b436d854
RS		 11538 /* The GOT entry is initialized to zero by default.
11539 See if we should install a different value. */
11540 if (outrel.r_addend != 0
2376f038 11541 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11542 {
11543 bfd_put_32 (output_bfd, outrel.r_addend,
11544 sgot->contents + off);
11545 outrel.r_addend = 0;
252b5132 11546 }
f21f3fe0 11547
2376f038
EB		 11548 if (isrofixup)
11549 arm_elf_add_rofixup (output_bfd,
11550 elf32_arm_hash_table(info)->srofixup,
11551 sgot->output_section->vma
11552 + sgot->output_offset + off);
11553
11554 else if (outrel.r_info != 0)
b436d854
RS		 11555 {
11556 outrel.r_offset = (sgot->output_section->vma
11557 + sgot->output_offset
11558 + off);
11559 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11560 }
2376f038 11561
b436d854
RS		 11562 h->got.offset |= 1;
11563 }
252b5132
RH		 11564 value = sgot->output_offset + off;
11565 }
11566 else
11567 {
11568 bfd_vma off;
f21f3fe0 11569
5025eb7c
AO		 11570 BFD_ASSERT (local_got_offsets != NULL
11571 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11572
252b5132 11573 off = local_got_offsets[r_symndx];
f21f3fe0 11574
252b5132
RH		 11575 /* The offset must always be a multiple of 4. We use the
11576 least significant bit to record whether we have already
9b485d32 11577 generated the necessary reloc. */
252b5132
RH		 11578 if ((off & 1) != 0)
11579 off &= ~1;
11580 else
11581 {
2376f038
EB		 11582 Elf_Internal_Rela outrel;
11583 int isrofixup = 0;
f21f3fe0 11584
2376f038
EB		 11585 if (dynreloc_st_type == STT_GNU_IFUNC)
11586 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11587 else if (bfd_link_pic (info))
11588 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11589 else
252b5132 11590 {
2376f038
EB		 11591 outrel.r_info = 0;
11592 if (globals->fdpic_p)
11593 isrofixup = 1;
11594 }
11595
11596 /* The GOT entry is initialized to zero by default.
11597 See if we should install a different value. */
11598 if (globals->use_rel || outrel.r_info == 0)
11599 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11600
11601 if (isrofixup)
11602 arm_elf_add_rofixup (output_bfd,
11603 globals->srofixup,
11604 sgot->output_section->vma
11605 + sgot->output_offset + off);
f21f3fe0 11606
2376f038
EB		 11607 else if (outrel.r_info != 0)
11608 {
34e77a92 11609 outrel.r_addend = addend + dynreloc_value;
252b5132 11610 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11611 + sgot->output_offset
252b5132 11612 + off);
47beaa6a 11613 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11614 }
f21f3fe0 11615
252b5132
RH		 11616 local_got_offsets[r_symndx] |= 1;
11617 }
f21f3fe0 11618
252b5132
RH		 11619 value = sgot->output_offset + off;
11620 }
eb043451
PB		 11621 if (r_type != R_ARM_GOT32)
11622 value += sgot->output_section->vma;
9a5aca8c 11623
f21f3fe0 11624 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11625 contents, rel->r_offset, value,
00a97672 11626 rel->r_addend);
f21f3fe0 11627
ba93b8ac
DJ		 11628 case R_ARM_TLS_LDO32:
11629 value = value - dtpoff_base (info);
11630
11631 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11632 contents, rel->r_offset, value,
11633 rel->r_addend);
ba93b8ac
DJ		 11634
11635 case R_ARM_TLS_LDM32:
5c5a4843 11636 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11637 {
11638 bfd_vma off;
11639
362d30a1 11640 if (sgot == NULL)
ba93b8ac
DJ		 11641 abort ();
11642
11643 off = globals->tls_ldm_got.offset;
11644
11645 if ((off & 1) != 0)
11646 off &= ~1;
11647 else
11648 {
11649 /* If we don't know the module number, create a relocation
11650 for it. */
9cb09e33 11651 if (bfd_link_dll (info))
ba93b8ac
DJ		 11652 {
11653 Elf_Internal_Rela outrel;
ba93b8ac 11654
362d30a1 11655 if (srelgot == NULL)
ba93b8ac
DJ		 11656 abort ();
11657
00a97672 11658 outrel.r_addend = 0;
362d30a1
RS		 11659 outrel.r_offset = (sgot->output_section->vma
11660 + sgot->output_offset + off);
ba93b8ac
DJ		 11661 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11662
00a97672
RS		 11663 if (globals->use_rel)
11664 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11665 sgot->contents + off);
ba93b8ac 11666
47beaa6a 11667 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11668 }
11669 else
362d30a1 11670 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11671
11672 globals->tls_ldm_got.offset |= 1;
11673 }
11674
5c5a4843 11675 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11676 {
11677 bfd_put_32(output_bfd,
11678 globals->root.sgot->output_offset + off,
11679 contents + rel->r_offset);
11680
11681 return bfd_reloc_ok;
11682 }
11683 else
11684 {
11685 value = sgot->output_section->vma + sgot->output_offset + off
11686 - (input_section->output_section->vma
11687 + input_section->output_offset + rel->r_offset);
ba93b8ac 11688
e8b09b87
CL		 11689 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11690 contents, rel->r_offset, value,
11691 rel->r_addend);
11692 }
ba93b8ac
DJ		 11693 }
11694
0855e32b
NS		 11695 case R_ARM_TLS_CALL:
11696 case R_ARM_THM_TLS_CALL:
ba93b8ac 11697 case R_ARM_TLS_GD32:
5c5a4843 11698 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11699 case R_ARM_TLS_IE32:
5c5a4843 11700 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11701 case R_ARM_TLS_GOTDESC:
11702 case R_ARM_TLS_DESCSEQ:
11703 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11704 {
0855e32b
NS		 11705 bfd_vma off, offplt;
11706 int indx = 0;
ba93b8ac
DJ		 11707 char tls_type;
11708
0855e32b 11709 BFD_ASSERT (sgot != NULL);
ba93b8ac 11710
ba93b8ac
DJ		 11711 if (h != NULL)
11712 {
11713 bfd_boolean dyn;
11714 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11715 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11716 bfd_link_pic (info),
11717 h)
11718 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11719 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11720 {
11721 *unresolved_reloc_p = FALSE;
11722 indx = h->dynindx;
11723 }
11724 off = h->got.offset;
0855e32b 11725 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11726 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11727 }
11728 else
11729 {
0855e32b 11730 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11731 off = local_got_offsets[r_symndx];
0855e32b 11732 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11733 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11734 }
11735
0855e32b 11736 /* Linker relaxations happens from one of the
b38cadfb 11737 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11738 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11739 tls_type = GOT_TLS_IE;
0855e32b
NS		 11740
11741 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11742
11743 if ((off & 1) != 0)
11744 off &= ~1;
11745 else
11746 {
11747 bfd_boolean need_relocs = FALSE;
11748 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11749 int cur_off = off;
11750
11751 /* The GOT entries have not been initialized yet. Do it
11752 now, and emit any relocations. If both an IE GOT and a
11753 GD GOT are necessary, we emit the GD first. */
11754
9cb09e33 11755 if ((bfd_link_dll (info) || indx != 0)
ba93b8ac 11756 && (h == NULL
95b03e4a
L		 11757 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11758 && !resolved_to_zero)
ba93b8ac
DJ		 11759 || h->root.type != bfd_link_hash_undefweak))
11760 {
11761 need_relocs = TRUE;
0855e32b 11762 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11763 }
11764
0855e32b
NS		 11765 if (tls_type & GOT_TLS_GDESC)
11766 {
47beaa6a
RS		 11767 bfd_byte *loc;
11768
0855e32b
NS		 11769 /* We should have relaxed, unless this is an undefined
11770 weak symbol. */
11771 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
9cb09e33 11772 || bfd_link_dll (info));
0855e32b 11773 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11774 <= globals->root.sgotplt->size);
0855e32b
NS		 11775
11776 outrel.r_addend = 0;
11777 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11778 + globals->root.sgotplt->output_offset
11779 + offplt
11780 + globals->sgotplt_jump_table_size);
b38cadfb 11781
0855e32b
NS		 11782 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11783 sreloc = globals->root.srelplt;
11784 loc = sreloc->contents;
11785 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11786 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11787 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11788
11789 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11790
11791 /* For globals, the first word in the relocation gets
11792 the relocation index and the top bit set, or zero,
11793 if we're binding now. For locals, it gets the
11794 symbol's offset in the tls section. */
99059e56 11795 bfd_put_32 (output_bfd,
0855e32b
NS		 11796 !h ? value - elf_hash_table (info)->tls_sec->vma
11797 : info->flags & DF_BIND_NOW ? 0
11798 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11799 globals->root.sgotplt->contents + offplt
11800 + globals->sgotplt_jump_table_size);
11801
0855e32b 11802 /* Second word in the relocation is always zero. */
99059e56 11803 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11804 globals->root.sgotplt->contents + offplt
11805 + globals->sgotplt_jump_table_size + 4);
0855e32b 11806 }
ba93b8ac
DJ		 11807 if (tls_type & GOT_TLS_GD)
11808 {
11809 if (need_relocs)
11810 {
00a97672 11811 outrel.r_addend = 0;
362d30a1
RS		 11812 outrel.r_offset = (sgot->output_section->vma
11813 + sgot->output_offset
00a97672 11814 + cur_off);
ba93b8ac 11815 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11816
00a97672
RS		 11817 if (globals->use_rel)
11818 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11819 sgot->contents + cur_off);
00a97672 11820
47beaa6a 11821 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11822
11823 if (indx == 0)
11824 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11825 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11826 else
11827 {
00a97672 11828 outrel.r_addend = 0;
ba93b8ac
DJ		 11829 outrel.r_info = ELF32_R_INFO (indx,
11830 R_ARM_TLS_DTPOFF32);
11831 outrel.r_offset += 4;
00a97672
RS		 11832
11833 if (globals->use_rel)
11834 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11835 sgot->contents + cur_off + 4);
00a97672 11836
47beaa6a
RS		 11837 elf32_arm_add_dynreloc (output_bfd, info,
11838 srelgot, &outrel);
ba93b8ac
DJ		 11839 }
11840 }
11841 else
11842 {
11843 /* If we are not emitting relocations for a
11844 general dynamic reference, then we must be in a
11845 static link or an executable link with the
11846 symbol binding locally. Mark it as belonging
11847 to module 1, the executable. */
11848 bfd_put_32 (output_bfd, 1,
362d30a1 11849 sgot->contents + cur_off);
ba93b8ac 11850 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11851 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11852 }
11853
11854 cur_off += 8;
11855 }
11856
11857 if (tls_type & GOT_TLS_IE)
11858 {
11859 if (need_relocs)
11860 {
00a97672
RS		 11861 if (indx == 0)
11862 outrel.r_addend = value - dtpoff_base (info);
11863 else
11864 outrel.r_addend = 0;
362d30a1
RS		 11865 outrel.r_offset = (sgot->output_section->vma
11866 + sgot->output_offset
ba93b8ac
DJ		 11867 + cur_off);
11868 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11869
00a97672
RS		 11870 if (globals->use_rel)
11871 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11872 sgot->contents + cur_off);
ba93b8ac 11873
47beaa6a 11874 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11875 }
11876 else
11877 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11878 sgot->contents + cur_off);
ba93b8ac
DJ		 11879 cur_off += 4;
11880 }
11881
11882 if (h != NULL)
11883 h->got.offset |= 1;
11884 else
11885 local_got_offsets[r_symndx] |= 1;
11886 }
11887
5c5a4843 11888 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11889 off += 8;
0855e32b
NS		 11890 else if (tls_type & GOT_TLS_GDESC)
11891 off = offplt;
11892
11893 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11894 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11895 {
11896 bfd_signed_vma offset;
12352d3f
PB		 11897 /* TLS stubs are arm mode. The original symbol is a
11898 data object, so branch_type is bogus. */
11899 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11900 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11901 = arm_type_of_stub (info, input_section, rel,
11902 st_type, &branch_type,
0855e32b
NS		 11903 (struct elf32_arm_link_hash_entry *)h,
11904 globals->tls_trampoline, globals->root.splt,
11905 input_bfd, sym_name);
11906
11907 if (stub_type != arm_stub_none)
11908 {
11909 struct elf32_arm_stub_hash_entry *stub_entry
11910 = elf32_arm_get_stub_entry
11911 (input_section, globals->root.splt, 0, rel,
11912 globals, stub_type);
11913 offset = (stub_entry->stub_offset
11914 + stub_entry->stub_sec->output_offset
11915 + stub_entry->stub_sec->output_section->vma);
11916 }
11917 else
11918 offset = (globals->root.splt->output_section->vma
11919 + globals->root.splt->output_offset
11920 + globals->tls_trampoline);
11921
11922 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11923 {
11924 unsigned long inst;
b38cadfb
NC		 11925
11926 offset -= (input_section->output_section->vma
11927 + input_section->output_offset
11928 + rel->r_offset + 8);
0855e32b
NS		 11929
11930 inst = offset >> 2;
11931 inst &= 0x00ffffff;
11932 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11933 }
11934 else
11935 {
11936 /* Thumb blx encodes the offset in a complicated
11937 fashion. */
11938 unsigned upper_insn, lower_insn;
11939 unsigned neg;
11940
b38cadfb
NC		 11941 offset -= (input_section->output_section->vma
11942 + input_section->output_offset
0855e32b 11943 + rel->r_offset + 4);
b38cadfb 11944
12352d3f
PB		 11945 if (stub_type != arm_stub_none
11946 && arm_stub_is_thumb (stub_type))
11947 {
11948 lower_insn = 0xd000;
11949 }
11950 else
11951 {
11952 lower_insn = 0xc000;
6a631e86 11953 /* Round up the offset to a word boundary. */
12352d3f
PB		 11954 offset = (offset + 2) & ~2;
11955 }
11956
0855e32b
NS		 11957 neg = offset < 0;
11958 upper_insn = (0xf000
11959 | ((offset >> 12) & 0x3ff)
11960 | (neg << 10));
12352d3f 11961 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11962 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11963 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11964 bfd_put_16 (input_bfd, upper_insn, hit_data);
11965 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11966 return bfd_reloc_ok;
11967 }
11968 }
11969 /* These relocations needs special care, as besides the fact
11970 they point somewhere in .gotplt, the addend must be
11971 adjusted accordingly depending on the type of instruction
6a631e86 11972 we refer to. */
0855e32b
NS		 11973 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11974 {
11975 unsigned long data, insn;
11976 unsigned thumb;
b38cadfb 11977
b627f562 11978 data = bfd_get_signed_32 (input_bfd, hit_data);
0855e32b 11979 thumb = data & 1;
b627f562 11980 data &= ~1ul;
b38cadfb 11981
0855e32b
NS		 11982 if (thumb)
11983 {
11984 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11985 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11986 insn = (insn << 16)
11987 | bfd_get_16 (input_bfd,
11988 contents + rel->r_offset - data + 2);
11989 if ((insn & 0xf800c000) == 0xf000c000)
11990 /* bl/blx */
11991 value = -6;
11992 else if ((insn & 0xffffff00) == 0x4400)
11993 /* add */
11994 value = -5;
11995 else
11996 {
4eca0228 11997 _bfd_error_handler
695344c0 11998 /* xgettext:c-format */
2dcf00ce 11999 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12000 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12001 "referenced by TLS_GOTDESC"),
12002 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12003 "Thumb", insn);
0855e32b
NS		 12004 return bfd_reloc_notsupported;
12005 }
12006 }
12007 else
12008 {
12009 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
12010
12011 switch (insn >> 24)
12012 {
12013 case 0xeb: /* bl */
12014 case 0xfa: /* blx */
12015 value = -4;
12016 break;
12017
12018 case 0xe0: /* add */
12019 value = -8;
12020 break;
b38cadfb 12021
0855e32b 12022 default:
4eca0228 12023 _bfd_error_handler
695344c0 12024 /* xgettext:c-format */
2dcf00ce 12025 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12026 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12027 "referenced by TLS_GOTDESC"),
12028 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12029 "ARM", insn);
0855e32b
NS		 12030 return bfd_reloc_notsupported;
12031 }
12032 }
b38cadfb 12033
0855e32b
NS		 12034 value += ((globals->root.sgotplt->output_section->vma
12035 + globals->root.sgotplt->output_offset + off)
12036 - (input_section->output_section->vma
12037 + input_section->output_offset
12038 + rel->r_offset)
12039 + globals->sgotplt_jump_table_size);
12040 }
12041 else
12042 value = ((globals->root.sgot->output_section->vma
12043 + globals->root.sgot->output_offset + off)
12044 - (input_section->output_section->vma
12045 + input_section->output_offset + rel->r_offset));
ba93b8ac 12046
5c5a4843
CL		 12047 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12048 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12049 {
12050 /* For FDPIC relocations, resolve to the offset of the GOT
12051 entry from the start of GOT. */
12052 bfd_put_32(output_bfd,
12053 globals->root.sgot->output_offset + off,
12054 contents + rel->r_offset);
12055
12056 return bfd_reloc_ok;
12057 }
12058 else
12059 {
12060 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12061 contents, rel->r_offset, value,
12062 rel->r_addend);
12063 }
ba93b8ac
DJ		 12064 }
12065
12066 case R_ARM_TLS_LE32:
3cbc1e5e 12067 if (bfd_link_dll (info))
ba93b8ac 12068 {
4eca0228 12069 _bfd_error_handler
695344c0 12070 /* xgettext:c-format */
2dcf00ce
AM		 12071 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12072 "in shared object"),
12073 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12074 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12075 }
12076 else
12077 value = tpoff (info, value);
906e58ca 12078
ba93b8ac 12079 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12080 contents, rel->r_offset, value,
12081 rel->r_addend);
ba93b8ac 12082
319850b4
JB		 12083 case R_ARM_V4BX:
12084 if (globals->fix_v4bx)
845b51d6
PB		 12085 {
12086 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12087
845b51d6
PB		 12088 /* Ensure that we have a BX instruction. */
12089 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12090
845b51d6
PB		 12091 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12092 {
12093 /* Branch to veneer. */
12094 bfd_vma glue_addr;
12095 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12096 glue_addr -= input_section->output_section->vma
12097 + input_section->output_offset
12098 + rel->r_offset + 8;
12099 insn = (insn & 0xf0000000) | 0x0a000000
12100 | ((glue_addr >> 2) & 0x00ffffff);
12101 }
12102 else
12103 {
12104 /* Preserve Rm (lowest four bits) and the condition code
12105 (highest four bits). Other bits encode MOV PC,Rm. */
12106 insn = (insn & 0xf000000f) | 0x01a0f000;
12107 }
319850b4 12108
845b51d6
PB		 12109 bfd_put_32 (input_bfd, insn, hit_data);
12110 }
319850b4
JB		 12111 return bfd_reloc_ok;
12112
b6895b4f
PB		 12113 case R_ARM_MOVW_ABS_NC:
12114 case R_ARM_MOVT_ABS:
12115 case R_ARM_MOVW_PREL_NC:
12116 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12117 /* Until we properly support segment-base-relative addressing then
12118 we assume the segment base to be zero, as for the group relocations.
12119 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12120 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12121 case R_ARM_MOVW_BREL_NC:
12122 case R_ARM_MOVW_BREL:
12123 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12124 {
12125 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12126
12127 if (globals->use_rel)
12128 {
12129 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12130 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12131 }
92f5d02b 12132
b6895b4f 12133 value += signed_addend;
b6895b4f
PB		 12134
12135 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12136 value -= (input_section->output_section->vma
12137 + input_section->output_offset + rel->r_offset);
12138
92f5d02b 12139 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12140 return bfd_reloc_overflow;
92f5d02b 12141
35fc36a8 12142 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12143 value |= 1;
12144
12145 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12146 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12147 value >>= 16;
12148
12149 insn &= 0xfff0f000;
12150 insn |= value & 0xfff;
12151 insn |= (value & 0xf000) << 4;
12152 bfd_put_32 (input_bfd, insn, hit_data);
12153 }
12154 return bfd_reloc_ok;
12155
12156 case R_ARM_THM_MOVW_ABS_NC:
12157 case R_ARM_THM_MOVT_ABS:
12158 case R_ARM_THM_MOVW_PREL_NC:
12159 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12160 /* Until we properly support segment-base-relative addressing then
12161 we assume the segment base to be zero, as for the above relocations.
12162 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12163 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12164 as R_ARM_THM_MOVT_ABS. */
12165 case R_ARM_THM_MOVW_BREL_NC:
12166 case R_ARM_THM_MOVW_BREL:
12167 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12168 {
12169 bfd_vma insn;
906e58ca 12170
b6895b4f
PB		 12171 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12172 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12173
12174 if (globals->use_rel)
12175 {
12176 addend = ((insn >> 4) & 0xf000)
12177 | ((insn >> 15) & 0x0800)
12178 | ((insn >> 4) & 0x0700)
07d6d2b8 12179 | (insn & 0x00ff);
39623e12 12180 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12181 }
92f5d02b 12182
b6895b4f 12183 value += signed_addend;
b6895b4f
PB		 12184
12185 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12186 value -= (input_section->output_section->vma
12187 + input_section->output_offset + rel->r_offset);
12188
92f5d02b 12189 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12190 return bfd_reloc_overflow;
92f5d02b 12191
35fc36a8 12192 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12193 value |= 1;
12194
12195 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12196 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12197 value >>= 16;
12198
12199 insn &= 0xfbf08f00;
12200 insn |= (value & 0xf000) << 4;
12201 insn |= (value & 0x0800) << 15;
12202 insn |= (value & 0x0700) << 4;
12203 insn |= (value & 0x00ff);
12204
12205 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12206 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12207 }
12208 return bfd_reloc_ok;
12209
4962c51a
MS		 12210 case R_ARM_ALU_PC_G0_NC:
12211 case R_ARM_ALU_PC_G1_NC:
12212 case R_ARM_ALU_PC_G0:
12213 case R_ARM_ALU_PC_G1:
12214 case R_ARM_ALU_PC_G2:
12215 case R_ARM_ALU_SB_G0_NC:
12216 case R_ARM_ALU_SB_G1_NC:
12217 case R_ARM_ALU_SB_G0:
12218 case R_ARM_ALU_SB_G1:
12219 case R_ARM_ALU_SB_G2:
12220 {
12221 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12222 bfd_vma pc = input_section->output_section->vma
4962c51a 12223 + input_section->output_offset + rel->r_offset;
31a91d61 12224 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12225 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12226 bfd_vma residual;
12227 bfd_vma g_n;
4962c51a 12228 bfd_signed_vma signed_value;
99059e56
RM		 12229 int group = 0;
12230
12231 /* Determine which group of bits to select. */
12232 switch (r_type)
12233 {
12234 case R_ARM_ALU_PC_G0_NC:
12235 case R_ARM_ALU_PC_G0:
12236 case R_ARM_ALU_SB_G0_NC:
12237 case R_ARM_ALU_SB_G0:
12238 group = 0;
12239 break;
12240
12241 case R_ARM_ALU_PC_G1_NC:
12242 case R_ARM_ALU_PC_G1:
12243 case R_ARM_ALU_SB_G1_NC:
12244 case R_ARM_ALU_SB_G1:
12245 group = 1;
12246 break;
12247
12248 case R_ARM_ALU_PC_G2:
12249 case R_ARM_ALU_SB_G2:
12250 group = 2;
12251 break;
12252
12253 default:
12254 abort ();
12255 }
12256
12257 /* If REL, extract the addend from the insn. If RELA, it will
12258 have already been fetched for us. */
4962c51a 12259 if (globals->use_rel)
99059e56
RM		 12260 {
12261 int negative;
12262 bfd_vma constant = insn & 0xff;
12263 bfd_vma rotation = (insn & 0xf00) >> 8;
12264
12265 if (rotation == 0)
12266 signed_addend = constant;
12267 else
12268 {
12269 /* Compensate for the fact that in the instruction, the
12270 rotation is stored in multiples of 2 bits. */
12271 rotation *= 2;
12272
12273 /* Rotate "constant" right by "rotation" bits. */
12274 signed_addend = (constant >> rotation) |
12275 (constant << (8 * sizeof (bfd_vma) - rotation));
12276 }
12277
12278 /* Determine if the instruction is an ADD or a SUB.
12279 (For REL, this determines the sign of the addend.) */
12280 negative = identify_add_or_sub (insn);
12281 if (negative == 0)
12282 {
4eca0228 12283 _bfd_error_handler
695344c0 12284 /* xgettext:c-format */
90b6238f 12285 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12286 "are allowed for ALU group relocations"),
12287 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12288 return bfd_reloc_overflow;
12289 }
12290
12291 signed_addend *= negative;
12292 }
4962c51a
MS		 12293
12294 /* Compute the value (X) to go in the place. */
99059e56
RM		 12295 if (r_type == R_ARM_ALU_PC_G0_NC
12296 || r_type == R_ARM_ALU_PC_G1_NC
12297 || r_type == R_ARM_ALU_PC_G0
12298 || r_type == R_ARM_ALU_PC_G1
12299 || r_type == R_ARM_ALU_PC_G2)
12300 /* PC relative. */
12301 signed_value = value - pc + signed_addend;
12302 else
12303 /* Section base relative. */
12304 signed_value = value - sb + signed_addend;
12305
12306 /* If the target symbol is a Thumb function, then set the
12307 Thumb bit in the address. */
35fc36a8 12308 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12309 signed_value |= 1;
12310
99059e56
RM		 12311 /* Calculate the value of the relevant G_n, in encoded
12312 constant-with-rotation format. */
b6518b38
NC		 12313 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12314 group, &residual);
99059e56
RM		 12315
12316 /* Check for overflow if required. */
12317 if ((r_type == R_ARM_ALU_PC_G0
12318 || r_type == R_ARM_ALU_PC_G1
12319 || r_type == R_ARM_ALU_PC_G2
12320 || r_type == R_ARM_ALU_SB_G0
12321 || r_type == R_ARM_ALU_SB_G1
12322 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12323 {
4eca0228 12324 _bfd_error_handler
695344c0 12325 /* xgettext:c-format */
90b6238f 12326 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12327 "splitting %#" PRIx64 " for group relocation %s"),
12328 input_bfd, input_section, (uint64_t) rel->r_offset,
12329 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12330 howto->name);
99059e56
RM		 12331 return bfd_reloc_overflow;
12332 }
12333
12334 /* Mask out the value and the ADD/SUB part of the opcode; take care
12335 not to destroy the S bit. */
12336 insn &= 0xff1ff000;
12337
12338 /* Set the opcode according to whether the value to go in the
12339 place is negative. */
12340 if (signed_value < 0)
12341 insn |= 1 << 22;
12342 else
12343 insn |= 1 << 23;
12344
12345 /* Encode the offset. */
12346 insn |= g_n;
4962c51a
MS		 12347
12348 bfd_put_32 (input_bfd, insn, hit_data);
12349 }
12350 return bfd_reloc_ok;
12351
12352 case R_ARM_LDR_PC_G0:
12353 case R_ARM_LDR_PC_G1:
12354 case R_ARM_LDR_PC_G2:
12355 case R_ARM_LDR_SB_G0:
12356 case R_ARM_LDR_SB_G1:
12357 case R_ARM_LDR_SB_G2:
12358 {
12359 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12360 bfd_vma pc = input_section->output_section->vma
4962c51a 12361 + input_section->output_offset + rel->r_offset;
31a91d61 12362 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12363 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12364 bfd_vma residual;
4962c51a 12365 bfd_signed_vma signed_value;
99059e56
RM		 12366 int group = 0;
12367
12368 /* Determine which groups of bits to calculate. */
12369 switch (r_type)
12370 {
12371 case R_ARM_LDR_PC_G0:
12372 case R_ARM_LDR_SB_G0:
12373 group = 0;
12374 break;
12375
12376 case R_ARM_LDR_PC_G1:
12377 case R_ARM_LDR_SB_G1:
12378 group = 1;
12379 break;
12380
12381 case R_ARM_LDR_PC_G2:
12382 case R_ARM_LDR_SB_G2:
12383 group = 2;
12384 break;
12385
12386 default:
12387 abort ();
12388 }
12389
12390 /* If REL, extract the addend from the insn. If RELA, it will
12391 have already been fetched for us. */
4962c51a 12392 if (globals->use_rel)
99059e56
RM		 12393 {
12394 int negative = (insn & (1 << 23)) ? 1 : -1;
12395 signed_addend = negative * (insn & 0xfff);
12396 }
4962c51a
MS		 12397
12398 /* Compute the value (X) to go in the place. */
99059e56
RM		 12399 if (r_type == R_ARM_LDR_PC_G0
12400 || r_type == R_ARM_LDR_PC_G1
12401 || r_type == R_ARM_LDR_PC_G2)
12402 /* PC relative. */
12403 signed_value = value - pc + signed_addend;
12404 else
12405 /* Section base relative. */
12406 signed_value = value - sb + signed_addend;
12407
12408 /* Calculate the value of the relevant G_{n-1} to obtain
12409 the residual at that stage. */
b6518b38
NC		 12410 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12411 group - 1, &residual);
99059e56
RM		 12412
12413 /* Check for overflow. */
12414 if (residual >= 0x1000)
12415 {
4eca0228 12416 _bfd_error_handler
695344c0 12417 /* xgettext:c-format */
90b6238f 12418 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12419 "splitting %#" PRIx64 " for group relocation %s"),
12420 input_bfd, input_section, (uint64_t) rel->r_offset,
12421 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12422 howto->name);
99059e56
RM		 12423 return bfd_reloc_overflow;
12424 }
12425
12426 /* Mask out the value and U bit. */
12427 insn &= 0xff7ff000;
12428
12429 /* Set the U bit if the value to go in the place is non-negative. */
12430 if (signed_value >= 0)
12431 insn |= 1 << 23;
12432
12433 /* Encode the offset. */
12434 insn |= residual;
4962c51a
MS		 12435
12436 bfd_put_32 (input_bfd, insn, hit_data);
12437 }
12438 return bfd_reloc_ok;
12439
12440 case R_ARM_LDRS_PC_G0:
12441 case R_ARM_LDRS_PC_G1:
12442 case R_ARM_LDRS_PC_G2:
12443 case R_ARM_LDRS_SB_G0:
12444 case R_ARM_LDRS_SB_G1:
12445 case R_ARM_LDRS_SB_G2:
12446 {
12447 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12448 bfd_vma pc = input_section->output_section->vma
4962c51a 12449 + input_section->output_offset + rel->r_offset;
31a91d61 12450 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12451 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12452 bfd_vma residual;
4962c51a 12453 bfd_signed_vma signed_value;
99059e56
RM		 12454 int group = 0;
12455
12456 /* Determine which groups of bits to calculate. */
12457 switch (r_type)
12458 {
12459 case R_ARM_LDRS_PC_G0:
12460 case R_ARM_LDRS_SB_G0:
12461 group = 0;
12462 break;
12463
12464 case R_ARM_LDRS_PC_G1:
12465 case R_ARM_LDRS_SB_G1:
12466 group = 1;
12467 break;
12468
12469 case R_ARM_LDRS_PC_G2:
12470 case R_ARM_LDRS_SB_G2:
12471 group = 2;
12472 break;
12473
12474 default:
12475 abort ();
12476 }
12477
12478 /* If REL, extract the addend from the insn. If RELA, it will
12479 have already been fetched for us. */
4962c51a 12480 if (globals->use_rel)
99059e56
RM		 12481 {
12482 int negative = (insn & (1 << 23)) ? 1 : -1;
12483 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12484 }
4962c51a
MS		 12485
12486 /* Compute the value (X) to go in the place. */
99059e56
RM		 12487 if (r_type == R_ARM_LDRS_PC_G0
12488 || r_type == R_ARM_LDRS_PC_G1
12489 || r_type == R_ARM_LDRS_PC_G2)
12490 /* PC relative. */
12491 signed_value = value - pc + signed_addend;
12492 else
12493 /* Section base relative. */
12494 signed_value = value - sb + signed_addend;
12495
12496 /* Calculate the value of the relevant G_{n-1} to obtain
12497 the residual at that stage. */
b6518b38
NC		 12498 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12499 group - 1, &residual);
99059e56
RM		 12500
12501 /* Check for overflow. */
12502 if (residual >= 0x100)
12503 {
4eca0228 12504 _bfd_error_handler
695344c0 12505 /* xgettext:c-format */
90b6238f 12506 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12507 "splitting %#" PRIx64 " for group relocation %s"),
12508 input_bfd, input_section, (uint64_t) rel->r_offset,
12509 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12510 howto->name);
99059e56
RM		 12511 return bfd_reloc_overflow;
12512 }
12513
12514 /* Mask out the value and U bit. */
12515 insn &= 0xff7ff0f0;
12516
12517 /* Set the U bit if the value to go in the place is non-negative. */
12518 if (signed_value >= 0)
12519 insn |= 1 << 23;
12520
12521 /* Encode the offset. */
12522 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12523
12524 bfd_put_32 (input_bfd, insn, hit_data);
12525 }
12526 return bfd_reloc_ok;
12527
12528 case R_ARM_LDC_PC_G0:
12529 case R_ARM_LDC_PC_G1:
12530 case R_ARM_LDC_PC_G2:
12531 case R_ARM_LDC_SB_G0:
12532 case R_ARM_LDC_SB_G1:
12533 case R_ARM_LDC_SB_G2:
12534 {
12535 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12536 bfd_vma pc = input_section->output_section->vma
4962c51a 12537 + input_section->output_offset + rel->r_offset;
31a91d61 12538 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12539 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12540 bfd_vma residual;
4962c51a 12541 bfd_signed_vma signed_value;
99059e56
RM		 12542 int group = 0;
12543
12544 /* Determine which groups of bits to calculate. */
12545 switch (r_type)
12546 {
12547 case R_ARM_LDC_PC_G0:
12548 case R_ARM_LDC_SB_G0:
12549 group = 0;
12550 break;
12551
12552 case R_ARM_LDC_PC_G1:
12553 case R_ARM_LDC_SB_G1:
12554 group = 1;
12555 break;
12556
12557 case R_ARM_LDC_PC_G2:
12558 case R_ARM_LDC_SB_G2:
12559 group = 2;
12560 break;
12561
12562 default:
12563 abort ();
12564 }
12565
12566 /* If REL, extract the addend from the insn. If RELA, it will
12567 have already been fetched for us. */
4962c51a 12568 if (globals->use_rel)
99059e56
RM		 12569 {
12570 int negative = (insn & (1 << 23)) ? 1 : -1;
12571 signed_addend = negative * ((insn & 0xff) << 2);
12572 }
4962c51a
MS		 12573
12574 /* Compute the value (X) to go in the place. */
99059e56
RM		 12575 if (r_type == R_ARM_LDC_PC_G0
12576 || r_type == R_ARM_LDC_PC_G1
12577 || r_type == R_ARM_LDC_PC_G2)
12578 /* PC relative. */
12579 signed_value = value - pc + signed_addend;
12580 else
12581 /* Section base relative. */
12582 signed_value = value - sb + signed_addend;
12583
12584 /* Calculate the value of the relevant G_{n-1} to obtain
12585 the residual at that stage. */
b6518b38
NC		 12586 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12587 group - 1, &residual);
99059e56
RM		 12588
12589 /* Check for overflow. (The absolute value to go in the place must be
12590 divisible by four and, after having been divided by four, must
12591 fit in eight bits.) */
12592 if ((residual & 0x3) != 0 || residual >= 0x400)
12593 {
4eca0228 12594 _bfd_error_handler
695344c0 12595 /* xgettext:c-format */
90b6238f 12596 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12597 "splitting %#" PRIx64 " for group relocation %s"),
12598 input_bfd, input_section, (uint64_t) rel->r_offset,
12599 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12600 howto->name);
99059e56
RM		 12601 return bfd_reloc_overflow;
12602 }
12603
12604 /* Mask out the value and U bit. */
12605 insn &= 0xff7fff00;
12606
12607 /* Set the U bit if the value to go in the place is non-negative. */
12608 if (signed_value >= 0)
12609 insn |= 1 << 23;
12610
12611 /* Encode the offset. */
12612 insn |= residual >> 2;
4962c51a
MS		 12613
12614 bfd_put_32 (input_bfd, insn, hit_data);
12615 }
12616 return bfd_reloc_ok;
12617
72d98d16
MG		 12618 case R_ARM_THM_ALU_ABS_G0_NC:
12619 case R_ARM_THM_ALU_ABS_G1_NC:
12620 case R_ARM_THM_ALU_ABS_G2_NC:
12621 case R_ARM_THM_ALU_ABS_G3_NC:
12622 {
12623 const int shift_array[4] = {0, 8, 16, 24};
12624 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12625 bfd_vma addr = value;
12626 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12627
12628 /* Compute address. */
12629 if (globals->use_rel)
12630 signed_addend = insn & 0xff;
12631 addr += signed_addend;
12632 if (branch_type == ST_BRANCH_TO_THUMB)
12633 addr |= 1;
12634 /* Clean imm8 insn. */
12635 insn &= 0xff00;
12636 /* And update with correct part of address. */
12637 insn |= (addr >> shift) & 0xff;
12638 /* Update insn. */
12639 bfd_put_16 (input_bfd, insn, hit_data);
12640 }
12641
12642 *unresolved_reloc_p = FALSE;
12643 return bfd_reloc_ok;
12644
e8b09b87
CL		 12645 case R_ARM_GOTOFFFUNCDESC:
12646 {
4b24dd1a 12647 if (h == NULL)
e8b09b87
CL		 12648 {
12649 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12650 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12651 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12652 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12653 bfd_vma seg = -1;
12654
12655 if (bfd_link_pic(info) && dynindx == 0)
12656 abort();
12657
12658 /* Resolve relocation. */
12659 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12660 , contents + rel->r_offset);
12661 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12662 not done yet. */
12663 arm_elf_fill_funcdesc(output_bfd, info,
12664 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12665 dynindx, offset, addr, dynreloc_value, seg);
12666 }
12667 else
12668 {
12669 int dynindx;
12670 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12671 bfd_vma addr;
12672 bfd_vma seg = -1;
12673
12674 /* For static binaries, sym_sec can be null. */
12675 if (sym_sec)
12676 {
12677 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12678 addr = dynreloc_value - sym_sec->output_section->vma;
12679 }
12680 else
12681 {
12682 dynindx = 0;
12683 addr = 0;
12684 }
12685
12686 if (bfd_link_pic(info) && dynindx == 0)
12687 abort();
12688
12689 /* This case cannot occur since funcdesc is allocated by
12690 the dynamic loader so we cannot resolve the relocation. */
12691 if (h->dynindx != -1)
12692 abort();
12693
12694 /* Resolve relocation. */
12695 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12696 contents + rel->r_offset);
12697 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12698 arm_elf_fill_funcdesc(output_bfd, info,
12699 &eh->fdpic_cnts.funcdesc_offset,
12700 dynindx, offset, addr, dynreloc_value, seg);
12701 }
12702 }
12703 *unresolved_reloc_p = FALSE;
12704 return bfd_reloc_ok;
12705
12706 case R_ARM_GOTFUNCDESC:
12707 {
4b24dd1a 12708 if (h != NULL)
e8b09b87
CL		 12709 {
12710 Elf_Internal_Rela outrel;
12711
12712 /* Resolve relocation. */
12713 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12714 + sgot->output_offset),
12715 contents + rel->r_offset);
12716 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12717 if(h->dynindx == -1)
12718 {
12719 int dynindx;
12720 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12721 bfd_vma addr;
12722 bfd_vma seg = -1;
12723
12724 /* For static binaries sym_sec can be null. */
12725 if (sym_sec)
12726 {
12727 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12728 addr = dynreloc_value - sym_sec->output_section->vma;
12729 }
12730 else
12731 {
12732 dynindx = 0;
12733 addr = 0;
12734 }
12735
12736 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12737 arm_elf_fill_funcdesc(output_bfd, info,
12738 &eh->fdpic_cnts.funcdesc_offset,
12739 dynindx, offset, addr, dynreloc_value, seg);
12740 }
12741
12742 /* Add a dynamic relocation on GOT entry if not already done. */
12743 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12744 {
12745 if (h->dynindx == -1)
12746 {
12747 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12748 if (h->root.type == bfd_link_hash_undefweak)
12749 bfd_put_32(output_bfd, 0, sgot->contents
12750 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12751 else
12752 bfd_put_32(output_bfd, sgot->output_section->vma
12753 + sgot->output_offset
12754 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12755 sgot->contents
12756 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12757 }
12758 else
12759 {
12760 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12761 }
12762 outrel.r_offset = sgot->output_section->vma
12763 + sgot->output_offset
12764 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12765 outrel.r_addend = 0;
12766 if (h->dynindx == -1 && !bfd_link_pic(info))
12767 if (h->root.type == bfd_link_hash_undefweak)
4b24dd1a 12768 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
e8b09b87 12769 else
4b24dd1a
AM		 12770 arm_elf_add_rofixup(output_bfd, globals->srofixup,
12771 outrel.r_offset);
e8b09b87
CL		 12772 else
12773 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12774 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12775 }
12776 }
12777 else
12778 {
12779 /* Such relocation on static function should not have been
12780 emitted by the compiler. */
12781 abort();
12782 }
12783 }
12784 *unresolved_reloc_p = FALSE;
12785 return bfd_reloc_ok;
12786
12787 case R_ARM_FUNCDESC:
12788 {
4b24dd1a 12789 if (h == NULL)
e8b09b87
CL		 12790 {
12791 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12792 Elf_Internal_Rela outrel;
12793 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12794 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12795 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12796 bfd_vma seg = -1;
12797
12798 if (bfd_link_pic(info) && dynindx == 0)
12799 abort();
12800
12801 /* Replace static FUNCDESC relocation with a
12802 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12803 executable. */
12804 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12805 outrel.r_offset = input_section->output_section->vma
12806 + input_section->output_offset + rel->r_offset;
12807 outrel.r_addend = 0;
12808 if (bfd_link_pic(info))
12809 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12810 else
12811 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12812
12813 bfd_put_32 (input_bfd, sgot->output_section->vma
12814 + sgot->output_offset + offset, hit_data);
12815
12816 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12817 arm_elf_fill_funcdesc(output_bfd, info,
12818 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12819 dynindx, offset, addr, dynreloc_value, seg);
12820 }
12821 else
12822 {
12823 if (h->dynindx == -1)
12824 {
12825 int dynindx;
12826 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12827 bfd_vma addr;
12828 bfd_vma seg = -1;
12829 Elf_Internal_Rela outrel;
12830
12831 /* For static binaries sym_sec can be null. */
12832 if (sym_sec)
12833 {
12834 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12835 addr = dynreloc_value - sym_sec->output_section->vma;
12836 }
12837 else
12838 {
12839 dynindx = 0;
12840 addr = 0;
12841 }
12842
12843 if (bfd_link_pic(info) && dynindx == 0)
12844 abort();
12845
12846 /* Replace static FUNCDESC relocation with a
12847 R_ARM_RELATIVE dynamic relocation. */
12848 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12849 outrel.r_offset = input_section->output_section->vma
12850 + input_section->output_offset + rel->r_offset;
12851 outrel.r_addend = 0;
12852 if (bfd_link_pic(info))
12853 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12854 else
12855 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12856
12857 bfd_put_32 (input_bfd, sgot->output_section->vma
12858 + sgot->output_offset + offset, hit_data);
12859
12860 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12861 arm_elf_fill_funcdesc(output_bfd, info,
12862 &eh->fdpic_cnts.funcdesc_offset,
12863 dynindx, offset, addr, dynreloc_value, seg);
12864 }
12865 else
12866 {
12867 Elf_Internal_Rela outrel;
12868
12869 /* Add a dynamic relocation. */
12870 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12871 outrel.r_offset = input_section->output_section->vma
12872 + input_section->output_offset + rel->r_offset;
12873 outrel.r_addend = 0;
12874 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12875 }
12876 }
12877 }
12878 *unresolved_reloc_p = FALSE;
12879 return bfd_reloc_ok;
12880
e5d6e09e
AV		 12881 case R_ARM_THM_BF16:
12882 {
12883 bfd_vma relocation;
12884 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12885 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12886
12887 if (globals->use_rel)
12888 {
12889 bfd_vma immA = (upper_insn & 0x001f);
12890 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12891 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12892 addend = (immA << 12);
12893 addend |= (immB << 2);
12894 addend |= (immC << 1);
12895 addend |= 1;
12896 /* Sign extend. */
e6f65e75 12897 signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
e5d6e09e
AV		 12898 }
12899
e6f65e75 12900 relocation = value + signed_addend;
e5d6e09e
AV		 12901 relocation -= (input_section->output_section->vma
12902 + input_section->output_offset
12903 + rel->r_offset);
12904
12905 /* Put RELOCATION back into the insn. */
12906 {
12907 bfd_vma immA = (relocation & 0x0001f000) >> 12;
12908 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12909 bfd_vma immC = (relocation & 0x00000002) >> 1;
12910
12911 upper_insn = (upper_insn & 0xffe0) | immA;
12912 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12913 }
12914
12915 /* Put the relocated value back in the object file: */
12916 bfd_put_16 (input_bfd, upper_insn, hit_data);
12917 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12918
12919 return bfd_reloc_ok;
12920 }
12921
1889da70
AV		 12922 case R_ARM_THM_BF12:
12923 {
12924 bfd_vma relocation;
12925 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12926 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12927
12928 if (globals->use_rel)
12929 {
12930 bfd_vma immA = (upper_insn & 0x0001);
12931 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12932 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12933 addend = (immA << 12);
12934 addend |= (immB << 2);
12935 addend |= (immC << 1);
12936 addend |= 1;
12937 /* Sign extend. */
12938 addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
e6f65e75 12939 signed_addend = addend;
1889da70
AV		 12940 }
12941
e6f65e75 12942 relocation = value + signed_addend;
1889da70
AV		 12943 relocation -= (input_section->output_section->vma
12944 + input_section->output_offset
12945 + rel->r_offset);
12946
12947 /* Put RELOCATION back into the insn. */
12948 {
12949 bfd_vma immA = (relocation & 0x00001000) >> 12;
12950 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12951 bfd_vma immC = (relocation & 0x00000002) >> 1;
12952
12953 upper_insn = (upper_insn & 0xfffe) | immA;
12954 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12955 }
12956
12957 /* Put the relocated value back in the object file: */
12958 bfd_put_16 (input_bfd, upper_insn, hit_data);
12959 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12960
12961 return bfd_reloc_ok;
12962 }
12963
1caf72a5
AV		 12964 case R_ARM_THM_BF18:
12965 {
12966 bfd_vma relocation;
12967 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12968 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12969
12970 if (globals->use_rel)
12971 {
12972 bfd_vma immA = (upper_insn & 0x007f);
12973 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12974 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12975 addend = (immA << 12);
12976 addend |= (immB << 2);
12977 addend |= (immC << 1);
12978 addend |= 1;
12979 /* Sign extend. */
12980 addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
e6f65e75 12981 signed_addend = addend;
1caf72a5
AV		 12982 }
12983
e6f65e75 12984 relocation = value + signed_addend;
1caf72a5
AV		 12985 relocation -= (input_section->output_section->vma
12986 + input_section->output_offset
12987 + rel->r_offset);
12988
12989 /* Put RELOCATION back into the insn. */
12990 {
12991 bfd_vma immA = (relocation & 0x0007f000) >> 12;
12992 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12993 bfd_vma immC = (relocation & 0x00000002) >> 1;
12994
12995 upper_insn = (upper_insn & 0xff80) | immA;
12996 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12997 }
12998
12999 /* Put the relocated value back in the object file: */
13000 bfd_put_16 (input_bfd, upper_insn, hit_data);
13001 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13002
13003 return bfd_reloc_ok;
13004 }
13005
252b5132
RH		 13006 default:
13007 return bfd_reloc_notsupported;
13008 }
13009}
13010
98c1d4aa
NC		 13011/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13012static void
07d6d2b8
AM		 13013arm_add_to_rel (bfd * abfd,
13014 bfd_byte * address,
57e8b36a 13015 reloc_howto_type * howto,
07d6d2b8 13016 bfd_signed_vma increment)
98c1d4aa 13017{
98c1d4aa
NC		 13018 bfd_signed_vma addend;
13019
bd97cb95
DJ		 13020 if (howto->type == R_ARM_THM_CALL
13021 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 13022 {
9a5aca8c
AM		 13023 int upper_insn, lower_insn;
13024 int upper, lower;
98c1d4aa 13025
9a5aca8c
AM		 13026 upper_insn = bfd_get_16 (abfd, address);
13027 lower_insn = bfd_get_16 (abfd, address + 2);
13028 upper = upper_insn & 0x7ff;
13029 lower = lower_insn & 0x7ff;
13030
13031 addend = (upper << 12) | (lower << 1);
ddda4409 13032 addend += increment;
9a5aca8c 13033 addend >>= 1;
98c1d4aa 13034
9a5aca8c
AM		 13035 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
13036 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
13037
dc810e39
AM		 13038 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
13039 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 13040 }
13041 else
13042 {
07d6d2b8 13043 bfd_vma contents;
9a5aca8c
AM		 13044
13045 contents = bfd_get_32 (abfd, address);
13046
13047 /* Get the (signed) value from the instruction. */
13048 addend = contents & howto->src_mask;
13049 if (addend & ((howto->src_mask + 1) >> 1))
13050 {
13051 bfd_signed_vma mask;
13052
13053 mask = -1;
13054 mask &= ~ howto->src_mask;
13055 addend |= mask;
13056 }
13057
13058 /* Add in the increment, (which is a byte value). */
13059 switch (howto->type)
13060 {
13061 default:
13062 addend += increment;
13063 break;
13064
13065 case R_ARM_PC24:
c6596c5e 13066 case R_ARM_PLT32:
5b5bb741
PB		 13067 case R_ARM_CALL:
13068 case R_ARM_JUMP24:
9a5aca8c 13069 addend <<= howto->size;
dc810e39 13070 addend += increment;
9a5aca8c
AM		 13071
13072 /* Should we check for overflow here ? */
13073
13074 /* Drop any undesired bits. */
13075 addend >>= howto->rightshift;
13076 break;
13077 }
13078
13079 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
13080
13081 bfd_put_32 (abfd, contents, address);
ddda4409 13082 }
98c1d4aa 13083}
252b5132 13084
ba93b8ac
DJ		 13085#define IS_ARM_TLS_RELOC(R_TYPE) \
13086 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 13087 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 13088 || (R_TYPE) == R_ARM_TLS_LDO32 \
13089 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 13090 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 13091 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13092 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13093 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13094 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 13095 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 13096 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 13097 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13098
13099/* Specific set of relocations for the gnu tls dialect. */
13100#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13101 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13102 || (R_TYPE) == R_ARM_TLS_CALL \
13103 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13104 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13105 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 13106
252b5132 13107/* Relocate an ARM ELF section. */
906e58ca 13108
b34976b6 13109static bfd_boolean
07d6d2b8 13110elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 13111 struct bfd_link_info * info,
07d6d2b8
AM		 13112 bfd * input_bfd,
13113 asection * input_section,
13114 bfd_byte * contents,
13115 Elf_Internal_Rela * relocs,
13116 Elf_Internal_Sym * local_syms,
13117 asection ** local_sections)
252b5132 13118{
b34976b6
AM		 13119 Elf_Internal_Shdr *symtab_hdr;
13120 struct elf_link_hash_entry **sym_hashes;
13121 Elf_Internal_Rela *rel;
13122 Elf_Internal_Rela *relend;
13123 const char *name;
b32d3aa2 13124 struct elf32_arm_link_hash_table * globals;
252b5132 13125
4e7fd91e 13126 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13127 if (globals == NULL)
13128 return FALSE;
b491616a 13129
0ffa91dd 13130 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 13131 sym_hashes = elf_sym_hashes (input_bfd);
13132
13133 rel = relocs;
13134 relend = relocs + input_section->reloc_count;
13135 for (; rel < relend; rel++)
13136 {
07d6d2b8
AM		 13137 int r_type;
13138 reloc_howto_type * howto;
13139 unsigned long r_symndx;
13140 Elf_Internal_Sym * sym;
13141 asection * sec;
252b5132 13142 struct elf_link_hash_entry * h;
07d6d2b8
AM		 13143 bfd_vma relocation;
13144 bfd_reloc_status_type r;
13145 arelent bfd_reloc;
13146 char sym_type;
13147 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 13148 char *error_message = NULL;
f21f3fe0 13149
252b5132 13150 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13151 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13152 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13153
ba96a88f 13154 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13155 || r_type == R_ARM_GNU_VTINHERIT)
13156 continue;
252b5132 13157
47aeb64c
NC		 13158 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13159
13160 if (howto == NULL)
13161 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13162
252b5132
RH		 13163 h = NULL;
13164 sym = NULL;
13165 sec = NULL;
9b485d32 13166
252b5132
RH		 13167 if (r_symndx < symtab_hdr->sh_info)
13168 {
13169 sym = local_syms + r_symndx;
ba93b8ac 13170 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13171 sec = local_sections[r_symndx];
ffcb4889
NS		 13172
13173 /* An object file might have a reference to a local
13174 undefined symbol. This is a daft object file, but we
13175 should at least do something about it. V4BX & NONE
13176 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13177 allowed to use the undefined symbol, so allow those.
13178 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13179 if (r_type != R_ARM_V4BX
13180 && r_type != R_ARM_NONE
77b4f08f 13181 && r_symndx != STN_UNDEF
ffcb4889
NS		 13182 && bfd_is_und_section (sec)
13183 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13184 (*info->callbacks->undefined_symbol)
13185 (info, bfd_elf_string_from_elf_section
13186 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13187 input_bfd, input_section,
13188 rel->r_offset, TRUE);
b38cadfb 13189
4e7fd91e 13190 if (globals->use_rel)
f8df10f4 13191 {
4e7fd91e
PB		 13192 relocation = (sec->output_section->vma
13193 + sec->output_offset
13194 + sym->st_value);
0e1862bb 13195 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13196 && (sec->flags & SEC_MERGE)
13197 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13198 {
4e7fd91e
PB		 13199 asection *msec;
13200 bfd_vma addend, value;
13201
39623e12 13202 switch (r_type)
4e7fd91e 13203 {
39623e12
PB		 13204 case R_ARM_MOVW_ABS_NC:
13205 case R_ARM_MOVT_ABS:
13206 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13207 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13208 addend = (addend ^ 0x8000) - 0x8000;
13209 break;
f8df10f4 13210
39623e12
PB		 13211 case R_ARM_THM_MOVW_ABS_NC:
13212 case R_ARM_THM_MOVT_ABS:
13213 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13214 << 16;
13215 value |= bfd_get_16 (input_bfd,
13216 contents + rel->r_offset + 2);
13217 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13218 | ((value & 0x04000000) >> 15);
13219 addend = (addend ^ 0x8000) - 0x8000;
13220 break;
f8df10f4 13221
39623e12
PB		 13222 default:
13223 if (howto->rightshift
13224 || (howto->src_mask & (howto->src_mask + 1)))
13225 {
4eca0228 13226 _bfd_error_handler
695344c0 13227 /* xgettext:c-format */
2dcf00ce
AM		 13228 (_("%pB(%pA+%#" PRIx64 "): "
13229 "%s relocation against SEC_MERGE section"),
39623e12 13230 input_bfd, input_section,
2dcf00ce 13231 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13232 return FALSE;
13233 }
13234
13235 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13236
13237 /* Get the (signed) value from the instruction. */
13238 addend = value & howto->src_mask;
13239 if (addend & ((howto->src_mask + 1) >> 1))
13240 {
13241 bfd_signed_vma mask;
13242
13243 mask = -1;
13244 mask &= ~ howto->src_mask;
13245 addend |= mask;
13246 }
13247 break;
4e7fd91e 13248 }
39623e12 13249
4e7fd91e
PB		 13250 msec = sec;
13251 addend =
13252 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13253 - relocation;
13254 addend += msec->output_section->vma + msec->output_offset;
39623e12 13255
cc643b88 13256 /* Cases here must match those in the preceding
39623e12
PB		 13257 switch statement. */
13258 switch (r_type)
13259 {
13260 case R_ARM_MOVW_ABS_NC:
13261 case R_ARM_MOVT_ABS:
13262 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13263 | (addend & 0xfff);
13264 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13265 break;
13266
13267 case R_ARM_THM_MOVW_ABS_NC:
13268 case R_ARM_THM_MOVT_ABS:
13269 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13270 | (addend & 0xff) | ((addend & 0x0800) << 15);
13271 bfd_put_16 (input_bfd, value >> 16,
13272 contents + rel->r_offset);
13273 bfd_put_16 (input_bfd, value,
13274 contents + rel->r_offset + 2);
13275 break;
13276
13277 default:
13278 value = (value & ~ howto->dst_mask)
13279 | (addend & howto->dst_mask);
13280 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13281 break;
13282 }
f8df10f4 13283 }
f8df10f4 13284 }
4e7fd91e
PB		 13285 else
13286 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13287 }
13288 else
13289 {
62d887d4 13290 bfd_boolean warned, ignored;
560e09e9 13291
b2a8e766
AM		 13292 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13293 r_symndx, symtab_hdr, sym_hashes,
13294 h, sec, relocation,
62d887d4 13295 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13296
13297 sym_type = h->type;
252b5132
RH		 13298 }
13299
dbaa2011 13300 if (sec != NULL && discarded_section (sec))
e4067dbb 13301 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13302 rel, 1, relend, howto, 0, contents);
ab96bf03 13303
0e1862bb 13304 if (bfd_link_relocatable (info))
ab96bf03
AM		 13305 {
13306 /* This is a relocatable link. We don't have to change
13307 anything, unless the reloc is against a section symbol,
13308 in which case we have to adjust according to where the
13309 section symbol winds up in the output section. */
13310 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13311 {
13312 if (globals->use_rel)
13313 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13314 howto, (bfd_signed_vma) sec->output_offset);
13315 else
13316 rel->r_addend += sec->output_offset;
13317 }
13318 continue;
13319 }
13320
252b5132
RH		 13321 if (h != NULL)
13322 name = h->root.root.string;
13323 else
13324 {
13325 name = (bfd_elf_string_from_elf_section
13326 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13327 if (name == NULL || *name == '\0')
fd361982 13328 name = bfd_section_name (sec);
252b5132 13329 }
f21f3fe0 13330
cf35638d 13331 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13332 && r_type != R_ARM_NONE
13333 && (h == NULL
13334 || h->root.type == bfd_link_hash_defined
13335 || h->root.type == bfd_link_hash_defweak)
13336 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13337 {
4eca0228 13338 _bfd_error_handler
ba93b8ac 13339 ((sym_type == STT_TLS
695344c0 13340 /* xgettext:c-format */
2dcf00ce 13341 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13342 /* xgettext:c-format */
2dcf00ce 13343 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13344 input_bfd,
13345 input_section,
2dcf00ce 13346 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13347 howto->name,
13348 name);
13349 }
13350
0855e32b 13351 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13352 done, i.e., the relaxation produced the final output we want,
13353 and we won't let anybody mess with it. Also, we have to do
13354 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13355 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13356 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13357 || (IS_ARM_TLS_GNU_RELOC (r_type)
13358 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13359 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13360 & GOT_TLS_GDESC)))
13361 {
13362 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13363 contents, rel, h == NULL);
13364 /* This may have been marked unresolved because it came from
13365 a shared library. But we've just dealt with that. */
13366 unresolved_reloc = 0;
13367 }
13368 else
13369 r = bfd_reloc_continue;
b38cadfb 13370
39d911fc
TP		 13371 if (r == bfd_reloc_continue)
13372 {
13373 unsigned char branch_type =
13374 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13375 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13376
13377 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13378 input_section, contents, rel,
13379 relocation, info, sec, name,
13380 sym_type, branch_type, h,
13381 &unresolved_reloc,
13382 &error_message);
13383 }
0945cdfd
DJ		 13384
13385 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13386 because such sections are not SEC_ALLOC and thus ld.so will
13387 not process them. */
13388 if (unresolved_reloc
99059e56
RM		 13389 && !((input_section->flags & SEC_DEBUGGING) != 0
13390 && h->def_dynamic)
1d5316ab
AM		 13391 && _bfd_elf_section_offset (output_bfd, info, input_section,
13392 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13393 {
4eca0228 13394 _bfd_error_handler
695344c0 13395 /* xgettext:c-format */
2dcf00ce
AM		 13396 (_("%pB(%pA+%#" PRIx64 "): "
13397 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13398 input_bfd,
13399 input_section,
2dcf00ce 13400 (uint64_t) rel->r_offset,
843fe662
L		 13401 howto->name,
13402 h->root.root.string);
0945cdfd
DJ		 13403 return FALSE;
13404 }
252b5132
RH		 13405
13406 if (r != bfd_reloc_ok)
13407 {
252b5132
RH		 13408 switch (r)
13409 {
13410 case bfd_reloc_overflow:
cf919dfd
PB		 13411 /* If the overflowing reloc was to an undefined symbol,
13412 we have already printed one error message and there
13413 is no point complaining again. */
1a72702b
AM		 13414 if (!h || h->root.type != bfd_link_hash_undefined)
13415 (*info->callbacks->reloc_overflow)
13416 (info, (h ? &h->root : NULL), name, howto->name,
13417 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13418 break;
13419
13420 case bfd_reloc_undefined:
1a72702b
AM		 13421 (*info->callbacks->undefined_symbol)
13422 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13423 break;
13424
13425 case bfd_reloc_outofrange:
f2a9dd69 13426 error_message = _("out of range");
252b5132
RH		 13427 goto common_error;
13428
13429 case bfd_reloc_notsupported:
f2a9dd69 13430 error_message = _("unsupported relocation");
252b5132
RH		 13431 goto common_error;
13432
13433 case bfd_reloc_dangerous:
f2a9dd69 13434 /* error_message should already be set. */
252b5132
RH		 13435 goto common_error;
13436
13437 default:
f2a9dd69 13438 error_message = _("unknown error");
8029a119 13439 /* Fall through. */
252b5132
RH		 13440
13441 common_error:
f2a9dd69 13442 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13443 (*info->callbacks->reloc_dangerous)
13444 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13445 break;
13446 }
13447 }
13448 }
13449
b34976b6 13450 return TRUE;
252b5132
RH		 13451}
13452
91d6fa6a 13453/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13454 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13455 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13456 maintaining that condition). */
13457
13458static void
13459add_unwind_table_edit (arm_unwind_table_edit **head,
13460 arm_unwind_table_edit **tail,
13461 arm_unwind_edit_type type,
13462 asection *linked_section,
91d6fa6a 13463 unsigned int tindex)
2468f9c9 13464{
21d799b5
NC		 13465 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13466 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13467
2468f9c9
PB		 13468 new_edit->type = type;
13469 new_edit->linked_section = linked_section;
91d6fa6a 13470 new_edit->index = tindex;
b38cadfb 13471
91d6fa6a 13472 if (tindex > 0)
2468f9c9
PB		 13473 {
13474 new_edit->next = NULL;
13475
13476 if (*tail)
13477 (*tail)->next = new_edit;
13478
13479 (*tail) = new_edit;
13480
13481 if (!*head)
13482 (*head) = new_edit;
13483 }
13484 else
13485 {
13486 new_edit->next = *head;
13487
13488 if (!*tail)
13489 *tail = new_edit;
13490
13491 *head = new_edit;
13492 }
13493}
13494
13495static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13496
13497/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13498static void
13499adjust_exidx_size(asection *exidx_sec, int adjust)
13500{
13501 asection *out_sec;
13502
13503 if (!exidx_sec->rawsize)
13504 exidx_sec->rawsize = exidx_sec->size;
13505
fd361982 13506 bfd_set_section_size (exidx_sec, exidx_sec->size + adjust);
2468f9c9
PB		 13507 out_sec = exidx_sec->output_section;
13508 /* Adjust size of output section. */
fd361982 13509 bfd_set_section_size (out_sec, out_sec->size +adjust);
2468f9c9
PB		 13510}
13511
13512/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13513static void
13514insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13515{
13516 struct _arm_elf_section_data *exidx_arm_data;
13517
13518 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13519 add_unwind_table_edit (
13520 &exidx_arm_data->u.exidx.unwind_edit_list,
13521 &exidx_arm_data->u.exidx.unwind_edit_tail,
13522 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13523
491d01d3
YU		 13524 exidx_arm_data->additional_reloc_count++;
13525
2468f9c9
PB		 13526 adjust_exidx_size(exidx_sec, 8);
13527}
13528
13529/* Scan .ARM.exidx tables, and create a list describing edits which should be
13530 made to those tables, such that:
b38cadfb 13531
2468f9c9
PB		 13532 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13533 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13534 codes which have been inlined into the index).
2468f9c9 13535
85fdf906
AH		 13536 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13537
2468f9c9 13538 The edits are applied when the tables are written
b38cadfb 13539 (in elf32_arm_write_section). */
2468f9c9
PB		 13540
13541bfd_boolean
13542elf32_arm_fix_exidx_coverage (asection **text_section_order,
13543 unsigned int num_text_sections,
85fdf906
AH		 13544 struct bfd_link_info *info,
13545 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13546{
13547 bfd *inp;
13548 unsigned int last_second_word = 0, i;
13549 asection *last_exidx_sec = NULL;
13550 asection *last_text_sec = NULL;
13551 int last_unwind_type = -1;
13552
13553 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13554 text sections. */
c72f2fb2 13555 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13556 {
13557 asection *sec;
b38cadfb 13558
2468f9c9 13559 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13560 {
2468f9c9
PB		 13561 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13562 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13563
dec9d5df 13564 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13565 continue;
b38cadfb 13566
2468f9c9
PB		 13567 if (elf_sec->linked_to)
13568 {
13569 Elf_Internal_Shdr *linked_hdr
99059e56 13570 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13571 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13572 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13573
13574 if (linked_sec_arm_data == NULL)
99059e56 13575 continue;
2468f9c9
PB		 13576
13577 /* Link this .ARM.exidx section back from the text section it
99059e56 13578 describes. */
2468f9c9
PB		 13579 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13580 }
13581 }
13582 }
13583
13584 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13585 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13586 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13587
13588 for (i = 0; i < num_text_sections; i++)
13589 {
13590 asection *sec = text_section_order[i];
13591 asection *exidx_sec;
13592 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13593 struct _arm_elf_section_data *exidx_arm_data;
13594 bfd_byte *contents = NULL;
13595 int deleted_exidx_bytes = 0;
13596 bfd_vma j;
13597 arm_unwind_table_edit *unwind_edit_head = NULL;
13598 arm_unwind_table_edit *unwind_edit_tail = NULL;
13599 Elf_Internal_Shdr *hdr;
13600 bfd *ibfd;
13601
13602 if (arm_data == NULL)
99059e56 13603 continue;
2468f9c9
PB		 13604
13605 exidx_sec = arm_data->u.text.arm_exidx_sec;
13606 if (exidx_sec == NULL)
13607 {
13608 /* Section has no unwind data. */
13609 if (last_unwind_type == 0 || !last_exidx_sec)
13610 continue;
13611
13612 /* Ignore zero sized sections. */
13613 if (sec->size == 0)
13614 continue;
13615
13616 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13617 last_unwind_type = 0;
13618 continue;
13619 }
13620
22a8f80e
PB		 13621 /* Skip /DISCARD/ sections. */
13622 if (bfd_is_abs_section (exidx_sec->output_section))
13623 continue;
13624
2468f9c9
PB		 13625 hdr = &elf_section_data (exidx_sec)->this_hdr;
13626 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13627 continue;
b38cadfb 13628
2468f9c9
PB		 13629 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13630 if (exidx_arm_data == NULL)
99059e56 13631 continue;
b38cadfb 13632
2468f9c9 13633 ibfd = exidx_sec->owner;
b38cadfb 13634
2468f9c9
PB		 13635 if (hdr->contents != NULL)
13636 contents = hdr->contents;
13637 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13638 /* An error? */
13639 continue;
13640
ac06903d
YU		 13641 if (last_unwind_type > 0)
13642 {
13643 unsigned int first_word = bfd_get_32 (ibfd, contents);
13644 /* Add cantunwind if first unwind item does not match section
13645 start. */
13646 if (first_word != sec->vma)
13647 {
13648 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13649 last_unwind_type = 0;
13650 }
13651 }
13652
2468f9c9
PB		 13653 for (j = 0; j < hdr->sh_size; j += 8)
13654 {
13655 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13656 int unwind_type;
13657 int elide = 0;
13658
13659 /* An EXIDX_CANTUNWIND entry. */
13660 if (second_word == 1)
13661 {
13662 if (last_unwind_type == 0)
13663 elide = 1;
13664 unwind_type = 0;
13665 }
13666 /* Inlined unwinding data. Merge if equal to previous. */
13667 else if ((second_word & 0x80000000) != 0)
13668 {
85fdf906
AH		 13669 if (merge_exidx_entries
13670 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13671 elide = 1;
13672 unwind_type = 1;
13673 last_second_word = second_word;
13674 }
13675 /* Normal table entry. In theory we could merge these too,
13676 but duplicate entries are likely to be much less common. */
13677 else
13678 unwind_type = 2;
13679
491d01d3 13680 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13681 {
13682 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13683 DELETE_EXIDX_ENTRY, NULL, j / 8);
13684
13685 deleted_exidx_bytes += 8;
13686 }
13687
13688 last_unwind_type = unwind_type;
13689 }
13690
13691 /* Free contents if we allocated it ourselves. */
13692 if (contents != hdr->contents)
99059e56 13693 free (contents);
2468f9c9
PB		 13694
13695 /* Record edits to be applied later (in elf32_arm_write_section). */
13696 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13697 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13698
2468f9c9
PB		 13699 if (deleted_exidx_bytes > 0)
13700 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13701
13702 last_exidx_sec = exidx_sec;
13703 last_text_sec = sec;
13704 }
13705
13706 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13707 if (!bfd_link_relocatable (info) && last_exidx_sec
13708 && last_unwind_type != 0)
2468f9c9
PB		 13709 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13710
13711 return TRUE;
13712}
13713
3e6b1042
DJ		 13714static bfd_boolean
13715elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13716 bfd *ibfd, const char *name)
13717{
13718 asection *sec, *osec;
13719
3d4d4302 13720 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13721 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13722 return TRUE;
13723
13724 osec = sec->output_section;
13725 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13726 return TRUE;
13727
13728 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13729 sec->output_offset, sec->size))
13730 return FALSE;
13731
13732 return TRUE;
13733}
13734
13735static bfd_boolean
13736elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13737{
13738 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13739 asection *sec, *osec;
3e6b1042 13740
4dfe6ac6
NC		 13741 if (globals == NULL)
13742 return FALSE;
13743
3e6b1042
DJ		 13744 /* Invoke the regular ELF backend linker to do all the work. */
13745 if (!bfd_elf_final_link (abfd, info))
13746 return FALSE;
13747
fe33d2fa
CL		 13748 /* Process stub sections (eg BE8 encoding, ...). */
13749 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13750 unsigned int i;
cdb21a0a
NS		 13751 for (i=0; i<htab->top_id; i++)
13752 {
13753 sec = htab->stub_group[i].stub_sec;
13754 /* Only process it once, in its link_sec slot. */
13755 if (sec && i == htab->stub_group[i].link_sec->id)
13756 {
13757 osec = sec->output_section;
13758 elf32_arm_write_section (abfd, info, sec, sec->contents);
13759 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13760 sec->output_offset, sec->size))
13761 return FALSE;
13762 }
fe33d2fa 13763 }
fe33d2fa 13764
3e6b1042
DJ		 13765 /* Write out any glue sections now that we have created all the
13766 stubs. */
13767 if (globals->bfd_of_glue_owner != NULL)
13768 {
13769 if (! elf32_arm_output_glue_section (info, abfd,
13770 globals->bfd_of_glue_owner,
13771 ARM2THUMB_GLUE_SECTION_NAME))
13772 return FALSE;
13773
13774 if (! elf32_arm_output_glue_section (info, abfd,
13775 globals->bfd_of_glue_owner,
13776 THUMB2ARM_GLUE_SECTION_NAME))
13777 return FALSE;
13778
13779 if (! elf32_arm_output_glue_section (info, abfd,
13780 globals->bfd_of_glue_owner,
13781 VFP11_ERRATUM_VENEER_SECTION_NAME))
13782 return FALSE;
13783
a504d23a
LA		 13784 if (! elf32_arm_output_glue_section (info, abfd,
13785 globals->bfd_of_glue_owner,
13786 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13787 return FALSE;
13788
3e6b1042
DJ		 13789 if (! elf32_arm_output_glue_section (info, abfd,
13790 globals->bfd_of_glue_owner,
13791 ARM_BX_GLUE_SECTION_NAME))
13792 return FALSE;
13793 }
13794
13795 return TRUE;
13796}
13797
5968a7b8
NC		 13798/* Return a best guess for the machine number based on the attributes. */
13799
13800static unsigned int
13801bfd_arm_get_mach_from_attributes (bfd * abfd)
13802{
13803 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13804
13805 switch (arch)
13806 {
c0c468d5 13807 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13808 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13809 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13810 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13811
13812 case TAG_CPU_ARCH_V5TE:
13813 {
13814 char * name;
13815
13816 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13817 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13818
13819 if (name)
13820 {
13821 if (strcmp (name, "IWMMXT2") == 0)
13822 return bfd_mach_arm_iWMMXt2;
13823
13824 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13825 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13826
13827 if (strcmp (name, "XSCALE") == 0)
13828 {
13829 int wmmx;
13830
13831 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13832 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13833 switch (wmmx)
13834 {
13835 case 1: return bfd_mach_arm_iWMMXt;
13836 case 2: return bfd_mach_arm_iWMMXt2;
13837 default: return bfd_mach_arm_XScale;
13838 }
13839 }
5968a7b8
NC		 13840 }
13841
13842 return bfd_mach_arm_5TE;
13843 }
13844
c0c468d5
TP		 13845 case TAG_CPU_ARCH_V5TEJ:
13846 return bfd_mach_arm_5TEJ;
13847 case TAG_CPU_ARCH_V6:
13848 return bfd_mach_arm_6;
13849 case TAG_CPU_ARCH_V6KZ:
13850 return bfd_mach_arm_6KZ;
13851 case TAG_CPU_ARCH_V6T2:
13852 return bfd_mach_arm_6T2;
13853 case TAG_CPU_ARCH_V6K:
13854 return bfd_mach_arm_6K;
13855 case TAG_CPU_ARCH_V7:
13856 return bfd_mach_arm_7;
13857 case TAG_CPU_ARCH_V6_M:
13858 return bfd_mach_arm_6M;
13859 case TAG_CPU_ARCH_V6S_M:
13860 return bfd_mach_arm_6SM;
13861 case TAG_CPU_ARCH_V7E_M:
13862 return bfd_mach_arm_7EM;
13863 case TAG_CPU_ARCH_V8:
13864 return bfd_mach_arm_8;
13865 case TAG_CPU_ARCH_V8R:
13866 return bfd_mach_arm_8R;
13867 case TAG_CPU_ARCH_V8M_BASE:
13868 return bfd_mach_arm_8M_BASE;
13869 case TAG_CPU_ARCH_V8M_MAIN:
13870 return bfd_mach_arm_8M_MAIN;
031254f2
AV		 13871 case TAG_CPU_ARCH_V8_1M_MAIN:
13872 return bfd_mach_arm_8_1M_MAIN;
c0c468d5 13873
5968a7b8 13874 default:
c0c468d5
TP		 13875 /* Force entry to be added for any new known Tag_CPU_arch value. */
13876 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13877
13878 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13879 return bfd_mach_arm_unknown;
13880 }
13881}
13882
c178919b
NC		 13883/* Set the right machine number. */
13884
13885static bfd_boolean
57e8b36a 13886elf32_arm_object_p (bfd *abfd)
c178919b 13887{
5a6c6817 13888 unsigned int mach;
57e8b36a 13889
5a6c6817 13890 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13891
5968a7b8
NC		 13892 if (mach == bfd_mach_arm_unknown)
13893 {
13894 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13895 mach = bfd_mach_arm_ep9312;
13896 else
13897 mach = bfd_arm_get_mach_from_attributes (abfd);
13898 }
c178919b 13899
5968a7b8 13900 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13901 return TRUE;
13902}
13903
fc830a83 13904/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13905
b34976b6 13906static bfd_boolean
57e8b36a 13907elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13908{
13909 if (elf_flags_init (abfd)
13910 && elf_elfheader (abfd)->e_flags != flags)
13911 {
fc830a83
NC		 13912 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13913 {
fd2ec330 13914 if (flags & EF_ARM_INTERWORK)
4eca0228 13915 _bfd_error_handler
90b6238f 13916 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13917 abfd);
fc830a83 13918 else
d003868e 13919 _bfd_error_handler
90b6238f 13920 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13921 abfd);
fc830a83 13922 }
252b5132
RH		 13923 }
13924 else
13925 {
13926 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13927 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13928 }
13929
b34976b6 13930 return TRUE;
252b5132
RH		 13931}
13932
fc830a83 13933/* Copy backend specific data from one object module to another. */
9b485d32 13934
b34976b6 13935static bfd_boolean
57e8b36a 13936elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13937{
13938 flagword in_flags;
13939 flagword out_flags;
13940
0ffa91dd 13941 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13942 return TRUE;
252b5132 13943
fc830a83 13944 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13945 out_flags = elf_elfheader (obfd)->e_flags;
13946
fc830a83
NC		 13947 if (elf_flags_init (obfd)
13948 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13949 && in_flags != out_flags)
252b5132 13950 {
252b5132 13951 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13952 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13953 return FALSE;
252b5132
RH		 13954
13955 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13956 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13957 return FALSE;
252b5132
RH		 13958
13959 /* If the src and dest have different interworking flags
99059e56 13960 then turn off the interworking bit. */
fd2ec330 13961 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13962 {
fd2ec330 13963 if (out_flags & EF_ARM_INTERWORK)
d003868e 13964 _bfd_error_handler
90b6238f 13965 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 13966 obfd, ibfd);
252b5132 13967
fd2ec330 13968 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13969 }
1006ba19
PB		 13970
13971 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13972 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13973 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13974 }
13975
13976 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13977 elf_flags_init (obfd) = TRUE;
252b5132 13978
e2349352 13979 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13980}
13981
13982/* Values for Tag_ABI_PCS_R9_use. */
13983enum
13984{
13985 AEABI_R9_V6,
13986 AEABI_R9_SB,
13987 AEABI_R9_TLS,
13988 AEABI_R9_unused
13989};
13990
13991/* Values for Tag_ABI_PCS_RW_data. */
13992enum
13993{
13994 AEABI_PCS_RW_data_absolute,
13995 AEABI_PCS_RW_data_PCrel,
13996 AEABI_PCS_RW_data_SBrel,
13997 AEABI_PCS_RW_data_unused
13998};
13999
14000/* Values for Tag_ABI_enum_size. */
14001enum
14002{
14003 AEABI_enum_unused,
14004 AEABI_enum_short,
14005 AEABI_enum_wide,
14006 AEABI_enum_forced_wide
14007};
14008
104d59d1
JM		 14009/* Determine whether an object attribute tag takes an integer, a
14010 string or both. */
906e58ca 14011
104d59d1
JM		 14012static int
14013elf32_arm_obj_attrs_arg_type (int tag)
14014{
14015 if (tag == Tag_compatibility)
3483fe2e 14016 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 14017 else if (tag == Tag_nodefaults)
3483fe2e
AS		 14018 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
14019 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
14020 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 14021 else if (tag < 32)
3483fe2e 14022 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 14023 else
3483fe2e 14024 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 14025}
14026
5aa6ff7c
AS		 14027/* The ABI defines that Tag_conformance should be emitted first, and that
14028 Tag_nodefaults should be second (if either is defined). This sets those
14029 two positions, and bumps up the position of all the remaining tags to
14030 compensate. */
14031static int
14032elf32_arm_obj_attrs_order (int num)
14033{
3de4a297 14034 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 14035 return Tag_conformance;
3de4a297 14036 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 14037 return Tag_nodefaults;
14038 if ((num - 2) < Tag_nodefaults)
14039 return num - 2;
14040 if ((num - 1) < Tag_conformance)
14041 return num - 1;
14042 return num;
14043}
14044
e8b36cd1
JM		 14045/* Attribute numbers >=64 (mod 128) can be safely ignored. */
14046static bfd_boolean
14047elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
14048{
14049 if ((tag & 127) < 64)
14050 {
14051 _bfd_error_handler
90b6238f 14052 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 14053 abfd, tag);
14054 bfd_set_error (bfd_error_bad_value);
14055 return FALSE;
14056 }
14057 else
14058 {
14059 _bfd_error_handler
90b6238f 14060 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 14061 abfd, tag);
14062 return TRUE;
14063 }
14064}
14065
91e22acd
AS		 14066/* Read the architecture from the Tag_also_compatible_with attribute, if any.
14067 Returns -1 if no architecture could be read. */
14068
14069static int
14070get_secondary_compatible_arch (bfd *abfd)
14071{
14072 obj_attribute *attr =
14073 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
14074
14075 /* Note: the tag and its argument below are uleb128 values, though
14076 currently-defined values fit in one byte for each. */
14077 if (attr->s
14078 && attr->s[0] == Tag_CPU_arch
14079 && (attr->s[1] & 128) != 128
14080 && attr->s[2] == 0)
14081 return attr->s[1];
14082
14083 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14084 return -1;
14085}
14086
14087/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14088 The tag is removed if ARCH is -1. */
14089
8e79c3df 14090static void
91e22acd 14091set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 14092{
91e22acd
AS		 14093 obj_attribute *attr =
14094 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 14095
91e22acd
AS		 14096 if (arch == -1)
14097 {
14098 attr->s = NULL;
14099 return;
8e79c3df 14100 }
91e22acd
AS		 14101
14102 /* Note: the tag and its argument below are uleb128 values, though
14103 currently-defined values fit in one byte for each. */
14104 if (!attr->s)
21d799b5 14105 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 14106 attr->s[0] = Tag_CPU_arch;
14107 attr->s[1] = arch;
14108 attr->s[2] = '\0';
8e79c3df
CM		 14109}
14110
91e22acd
AS		 14111/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14112 into account. */
14113
14114static int
14115tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
14116 int newtag, int secondary_compat)
8e79c3df 14117{
91e22acd
AS		 14118#define T(X) TAG_CPU_ARCH_##X
14119 int tagl, tagh, result;
14120 const int v6t2[] =
14121 {
14122 T(V6T2), /* PRE_V4. */
14123 T(V6T2), /* V4. */
14124 T(V6T2), /* V4T. */
14125 T(V6T2), /* V5T. */
14126 T(V6T2), /* V5TE. */
14127 T(V6T2), /* V5TEJ. */
14128 T(V6T2), /* V6. */
14129 T(V7), /* V6KZ. */
14130 T(V6T2) /* V6T2. */
14131 };
14132 const int v6k[] =
14133 {
14134 T(V6K), /* PRE_V4. */
14135 T(V6K), /* V4. */
14136 T(V6K), /* V4T. */
14137 T(V6K), /* V5T. */
14138 T(V6K), /* V5TE. */
14139 T(V6K), /* V5TEJ. */
14140 T(V6K), /* V6. */
14141 T(V6KZ), /* V6KZ. */
14142 T(V7), /* V6T2. */
14143 T(V6K) /* V6K. */
14144 };
14145 const int v7[] =
14146 {
14147 T(V7), /* PRE_V4. */
14148 T(V7), /* V4. */
14149 T(V7), /* V4T. */
14150 T(V7), /* V5T. */
14151 T(V7), /* V5TE. */
14152 T(V7), /* V5TEJ. */
14153 T(V7), /* V6. */
14154 T(V7), /* V6KZ. */
14155 T(V7), /* V6T2. */
14156 T(V7), /* V6K. */
14157 T(V7) /* V7. */
14158 };
14159 const int v6_m[] =
14160 {
07d6d2b8
AM		 14161 -1, /* PRE_V4. */
14162 -1, /* V4. */
91e22acd
AS		 14163 T(V6K), /* V4T. */
14164 T(V6K), /* V5T. */
14165 T(V6K), /* V5TE. */
14166 T(V6K), /* V5TEJ. */
14167 T(V6K), /* V6. */
14168 T(V6KZ), /* V6KZ. */
14169 T(V7), /* V6T2. */
14170 T(V6K), /* V6K. */
14171 T(V7), /* V7. */
14172 T(V6_M) /* V6_M. */
14173 };
14174 const int v6s_m[] =
14175 {
07d6d2b8
AM		 14176 -1, /* PRE_V4. */
14177 -1, /* V4. */
91e22acd
AS		 14178 T(V6K), /* V4T. */
14179 T(V6K), /* V5T. */
14180 T(V6K), /* V5TE. */
14181 T(V6K), /* V5TEJ. */
14182 T(V6K), /* V6. */
14183 T(V6KZ), /* V6KZ. */
14184 T(V7), /* V6T2. */
14185 T(V6K), /* V6K. */
14186 T(V7), /* V7. */
14187 T(V6S_M), /* V6_M. */
14188 T(V6S_M) /* V6S_M. */
14189 };
9e3c6df6
PB		 14190 const int v7e_m[] =
14191 {
07d6d2b8
AM		 14192 -1, /* PRE_V4. */
14193 -1, /* V4. */
9e3c6df6
PB		 14194 T(V7E_M), /* V4T. */
14195 T(V7E_M), /* V5T. */
14196 T(V7E_M), /* V5TE. */
14197 T(V7E_M), /* V5TEJ. */
14198 T(V7E_M), /* V6. */
14199 T(V7E_M), /* V6KZ. */
14200 T(V7E_M), /* V6T2. */
14201 T(V7E_M), /* V6K. */
14202 T(V7E_M), /* V7. */
14203 T(V7E_M), /* V6_M. */
14204 T(V7E_M), /* V6S_M. */
14205 T(V7E_M) /* V7E_M. */
14206 };
bca38921
MGD		 14207 const int v8[] =
14208 {
14209 T(V8), /* PRE_V4. */
14210 T(V8), /* V4. */
14211 T(V8), /* V4T. */
14212 T(V8), /* V5T. */
14213 T(V8), /* V5TE. */
14214 T(V8), /* V5TEJ. */
14215 T(V8), /* V6. */
14216 T(V8), /* V6KZ. */
14217 T(V8), /* V6T2. */
14218 T(V8), /* V6K. */
14219 T(V8), /* V7. */
14220 T(V8), /* V6_M. */
14221 T(V8), /* V6S_M. */
14222 T(V8), /* V7E_M. */
14223 T(V8) /* V8. */
14224 };
bff0500d
TP		 14225 const int v8r[] =
14226 {
14227 T(V8R), /* PRE_V4. */
14228 T(V8R), /* V4. */
14229 T(V8R), /* V4T. */
14230 T(V8R), /* V5T. */
14231 T(V8R), /* V5TE. */
14232 T(V8R), /* V5TEJ. */
14233 T(V8R), /* V6. */
14234 T(V8R), /* V6KZ. */
14235 T(V8R), /* V6T2. */
14236 T(V8R), /* V6K. */
14237 T(V8R), /* V7. */
14238 T(V8R), /* V6_M. */
14239 T(V8R), /* V6S_M. */
14240 T(V8R), /* V7E_M. */
14241 T(V8), /* V8. */
14242 T(V8R), /* V8R. */
14243 };
2fd158eb
TP		 14244 const int v8m_baseline[] =
14245 {
14246 -1, /* PRE_V4. */
14247 -1, /* V4. */
14248 -1, /* V4T. */
14249 -1, /* V5T. */
14250 -1, /* V5TE. */
14251 -1, /* V5TEJ. */
14252 -1, /* V6. */
14253 -1, /* V6KZ. */
14254 -1, /* V6T2. */
14255 -1, /* V6K. */
14256 -1, /* V7. */
14257 T(V8M_BASE), /* V6_M. */
14258 T(V8M_BASE), /* V6S_M. */
14259 -1, /* V7E_M. */
14260 -1, /* V8. */
bff0500d 14261 -1, /* V8R. */
2fd158eb
TP		 14262 T(V8M_BASE) /* V8-M BASELINE. */
14263 };
14264 const int v8m_mainline[] =
14265 {
14266 -1, /* PRE_V4. */
14267 -1, /* V4. */
14268 -1, /* V4T. */
14269 -1, /* V5T. */
14270 -1, /* V5TE. */
14271 -1, /* V5TEJ. */
14272 -1, /* V6. */
14273 -1, /* V6KZ. */
14274 -1, /* V6T2. */
14275 -1, /* V6K. */
14276 T(V8M_MAIN), /* V7. */
14277 T(V8M_MAIN), /* V6_M. */
14278 T(V8M_MAIN), /* V6S_M. */
14279 T(V8M_MAIN), /* V7E_M. */
14280 -1, /* V8. */
bff0500d 14281 -1, /* V8R. */
2fd158eb
TP		 14282 T(V8M_MAIN), /* V8-M BASELINE. */
14283 T(V8M_MAIN) /* V8-M MAINLINE. */
14284 };
031254f2
AV		 14285 const int v8_1m_mainline[] =
14286 {
14287 -1, /* PRE_V4. */
14288 -1, /* V4. */
14289 -1, /* V4T. */
14290 -1, /* V5T. */
14291 -1, /* V5TE. */
14292 -1, /* V5TEJ. */
14293 -1, /* V6. */
14294 -1, /* V6KZ. */
14295 -1, /* V6T2. */
14296 -1, /* V6K. */
14297 T(V8_1M_MAIN), /* V7. */
14298 T(V8_1M_MAIN), /* V6_M. */
14299 T(V8_1M_MAIN), /* V6S_M. */
14300 T(V8_1M_MAIN), /* V7E_M. */
14301 -1, /* V8. */
14302 -1, /* V8R. */
14303 T(V8_1M_MAIN), /* V8-M BASELINE. */
14304 T(V8_1M_MAIN), /* V8-M MAINLINE. */
14305 -1, /* Unused (18). */
14306 -1, /* Unused (19). */
14307 -1, /* Unused (20). */
14308 T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14309 };
91e22acd
AS		 14310 const int v4t_plus_v6_m[] =
14311 {
14312 -1, /* PRE_V4. */
14313 -1, /* V4. */
14314 T(V4T), /* V4T. */
14315 T(V5T), /* V5T. */
14316 T(V5TE), /* V5TE. */
14317 T(V5TEJ), /* V5TEJ. */
14318 T(V6), /* V6. */
14319 T(V6KZ), /* V6KZ. */
14320 T(V6T2), /* V6T2. */
14321 T(V6K), /* V6K. */
14322 T(V7), /* V7. */
14323 T(V6_M), /* V6_M. */
14324 T(V6S_M), /* V6S_M. */
9e3c6df6 14325 T(V7E_M), /* V7E_M. */
bca38921 14326 T(V8), /* V8. */
bff0500d 14327 -1, /* V8R. */
2fd158eb
TP		 14328 T(V8M_BASE), /* V8-M BASELINE. */
14329 T(V8M_MAIN), /* V8-M MAINLINE. */
031254f2
AV		 14330 -1, /* Unused (18). */
14331 -1, /* Unused (19). */
14332 -1, /* Unused (20). */
14333 T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
91e22acd
AS		 14334 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14335 };
14336 const int *comb[] =
14337 {
14338 v6t2,
14339 v6k,
14340 v7,
14341 v6_m,
14342 v6s_m,
9e3c6df6 14343 v7e_m,
bca38921 14344 v8,
bff0500d 14345 v8r,
2fd158eb
TP		 14346 v8m_baseline,
14347 v8m_mainline,
031254f2
AV		 14348 NULL,
14349 NULL,
14350 NULL,
14351 v8_1m_mainline,
91e22acd
AS		 14352 /* Pseudo-architecture. */
14353 v4t_plus_v6_m
14354 };
14355
14356 /* Check we've not got a higher architecture than we know about. */
14357
9e3c6df6 14358 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14359 {
90b6238f 14360 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14361 return -1;
14362 }
14363
14364 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14365
14366 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14367 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14368 oldtag = T(V4T_PLUS_V6_M);
14369
14370 /* And override the new tag if we have a Tag_also_compatible_with on the
14371 input. */
14372
14373 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14374 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14375 newtag = T(V4T_PLUS_V6_M);
14376
14377 tagl = (oldtag < newtag) ? oldtag : newtag;
14378 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14379
14380 /* Architectures before V6KZ add features monotonically. */
14381 if (tagh <= TAG_CPU_ARCH_V6KZ)
14382 return result;
14383
4ed7ed8d 14384 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14385
14386 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14387 as the canonical version. */
14388 if (result == T(V4T_PLUS_V6_M))
14389 {
14390 result = T(V4T);
14391 *secondary_compat_out = T(V6_M);
14392 }
14393 else
14394 *secondary_compat_out = -1;
14395
14396 if (result == -1)
14397 {
90b6238f 14398 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14399 ibfd, oldtag, newtag);
14400 return -1;
14401 }
14402
14403 return result;
14404#undef T
8e79c3df
CM		 14405}
14406
ac56ee8f
MGD		 14407/* Query attributes object to see if integer divide instructions may be
14408 present in an object. */
14409static bfd_boolean
14410elf32_arm_attributes_accept_div (const obj_attribute *attr)
14411{
14412 int arch = attr[Tag_CPU_arch].i;
14413 int profile = attr[Tag_CPU_arch_profile].i;
14414
14415 switch (attr[Tag_DIV_use].i)
14416 {
14417 case 0:
14418 /* Integer divide allowed if instruction contained in archetecture. */
14419 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14420 return TRUE;
14421 else if (arch >= TAG_CPU_ARCH_V7E_M)
14422 return TRUE;
14423 else
14424 return FALSE;
14425
14426 case 1:
14427 /* Integer divide explicitly prohibited. */
14428 return FALSE;
14429
14430 default:
14431 /* Unrecognised case - treat as allowing divide everywhere. */
14432 case 2:
14433 /* Integer divide allowed in ARM state. */
14434 return TRUE;
14435 }
14436}
14437
14438/* Query attributes object to see if integer divide instructions are
14439 forbidden to be in the object. This is not the inverse of
14440 elf32_arm_attributes_accept_div. */
14441static bfd_boolean
14442elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14443{
14444 return attr[Tag_DIV_use].i == 1;
14445}
14446
ee065d83
PB		 14447/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14448 are conflicting attributes. */
906e58ca 14449
ee065d83 14450static bfd_boolean
50e03d47 14451elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14452{
50e03d47 14453 bfd *obfd = info->output_bfd;
104d59d1
JM		 14454 obj_attribute *in_attr;
14455 obj_attribute *out_attr;
ee065d83
PB		 14456 /* Some tags have 0 = don't care, 1 = strong requirement,
14457 2 = weak requirement. */
91e22acd 14458 static const int order_021[3] = {0, 2, 1};
ee065d83 14459 int i;
91e22acd 14460 bfd_boolean result = TRUE;
9274e9de 14461 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14462
3e6b1042
DJ		 14463 /* Skip the linker stubs file. This preserves previous behavior
14464 of accepting unknown attributes in the first input file - but
14465 is that a bug? */
14466 if (ibfd->flags & BFD_LINKER_CREATED)
14467 return TRUE;
14468
9274e9de
TG		 14469 /* Skip any input that hasn't attribute section.
14470 This enables to link object files without attribute section with
14471 any others. */
14472 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14473 return TRUE;
14474
104d59d1 14475 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14476 {
14477 /* This is the first object. Copy the attributes. */
104d59d1 14478 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14479
cd21e546
MGD		 14480 out_attr = elf_known_obj_attributes_proc (obfd);
14481
004ae526
PB		 14482 /* Use the Tag_null value to indicate the attributes have been
14483 initialized. */
cd21e546 14484 out_attr[0].i = 1;
004ae526 14485
cd21e546
MGD		 14486 /* We do not output objects with Tag_MPextension_use_legacy - we move
14487 the attribute's value to Tag_MPextension_use. */
14488 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14489 {
14490 if (out_attr[Tag_MPextension_use].i != 0
14491 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14492 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14493 {
14494 _bfd_error_handler
871b3ab2 14495 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14496 "Tag_MPextension_use attributes"), ibfd);
14497 result = FALSE;
14498 }
14499
14500 out_attr[Tag_MPextension_use] =
14501 out_attr[Tag_MPextension_use_legacy];
14502 out_attr[Tag_MPextension_use_legacy].type = 0;
14503 out_attr[Tag_MPextension_use_legacy].i = 0;
14504 }
14505
14506 return result;
ee065d83
PB		 14507 }
14508
104d59d1
JM		 14509 in_attr = elf_known_obj_attributes_proc (ibfd);
14510 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14511 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14512 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14513 {
5c294fee
TG		 14514 /* Ignore mismatches if the object doesn't use floating point or is
14515 floating point ABI independent. */
14516 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14517 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14518 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14519 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14520 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14521 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14522 {
14523 _bfd_error_handler
871b3ab2 14524 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14525 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14526 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14527 result = FALSE;
ee065d83
PB		 14528 }
14529 }
14530
3de4a297 14531 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14532 {
14533 /* Merge this attribute with existing attributes. */
14534 switch (i)
14535 {
14536 case Tag_CPU_raw_name:
14537 case Tag_CPU_name:
6a631e86 14538 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14539 break;
14540
14541 case Tag_ABI_optimization_goals:
14542 case Tag_ABI_FP_optimization_goals:
14543 /* Use the first value seen. */
14544 break;
14545
14546 case Tag_CPU_arch:
91e22acd
AS		 14547 {
14548 int secondary_compat = -1, secondary_compat_out = -1;
14549 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14550 int arch_attr;
14551 static const char *name_table[] =
14552 {
91e22acd
AS		 14553 /* These aren't real CPU names, but we can't guess
14554 that from the architecture version alone. */
14555 "Pre v4",
14556 "ARM v4",
14557 "ARM v4T",
14558 "ARM v5T",
14559 "ARM v5TE",
14560 "ARM v5TEJ",
14561 "ARM v6",
14562 "ARM v6KZ",
14563 "ARM v6T2",
14564 "ARM v6K",
14565 "ARM v7",
14566 "ARM v6-M",
bca38921 14567 "ARM v6S-M",
2fd158eb
TP		 14568 "ARM v8",
14569 "",
14570 "ARM v8-M.baseline",
14571 "ARM v8-M.mainline",
91e22acd
AS		 14572 };
14573
14574 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14575 secondary_compat = get_secondary_compatible_arch (ibfd);
14576 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14577 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14578 &secondary_compat_out,
14579 in_attr[i].i,
14580 secondary_compat);
14581
14582 /* Return with error if failed to merge. */
14583 if (arch_attr == -1)
14584 return FALSE;
14585
14586 out_attr[i].i = arch_attr;
14587
91e22acd
AS		 14588 set_secondary_compatible_arch (obfd, secondary_compat_out);
14589
14590 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14591 if (out_attr[i].i == saved_out_attr)
14592 ; /* Leave the names alone. */
14593 else if (out_attr[i].i == in_attr[i].i)
14594 {
14595 /* The output architecture has been changed to match the
14596 input architecture. Use the input names. */
14597 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14598 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14599 : NULL;
14600 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14601 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14602 : NULL;
14603 }
14604 else
14605 {
14606 out_attr[Tag_CPU_name].s = NULL;
14607 out_attr[Tag_CPU_raw_name].s = NULL;
14608 }
14609
14610 /* If we still don't have a value for Tag_CPU_name,
14611 make one up now. Tag_CPU_raw_name remains blank. */
14612 if (out_attr[Tag_CPU_name].s == NULL
14613 && out_attr[i].i < ARRAY_SIZE (name_table))
14614 out_attr[Tag_CPU_name].s =
14615 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14616 }
14617 break;
14618
ee065d83
PB		 14619 case Tag_ARM_ISA_use:
14620 case Tag_THUMB_ISA_use:
ee065d83 14621 case Tag_WMMX_arch:
91e22acd
AS		 14622 case Tag_Advanced_SIMD_arch:
14623 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14624 case Tag_ABI_FP_rounding:
ee065d83
PB		 14625 case Tag_ABI_FP_exceptions:
14626 case Tag_ABI_FP_user_exceptions:
14627 case Tag_ABI_FP_number_model:
75375b3e 14628 case Tag_FP_HP_extension:
91e22acd
AS		 14629 case Tag_CPU_unaligned_access:
14630 case Tag_T2EE_use:
91e22acd 14631 case Tag_MPextension_use:
a7ad558c 14632 case Tag_MVE_arch:
ee065d83
PB		 14633 /* Use the largest value specified. */
14634 if (in_attr[i].i > out_attr[i].i)
14635 out_attr[i].i = in_attr[i].i;
14636 break;
14637
75375b3e 14638 case Tag_ABI_align_preserved:
91e22acd
AS		 14639 case Tag_ABI_PCS_RO_data:
14640 /* Use the smallest value specified. */
14641 if (in_attr[i].i < out_attr[i].i)
14642 out_attr[i].i = in_attr[i].i;
14643 break;
14644
75375b3e 14645 case Tag_ABI_align_needed:
91e22acd 14646 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14647 && (in_attr[Tag_ABI_align_preserved].i == 0
14648 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14649 {
91e22acd
AS		 14650 /* This error message should be enabled once all non-conformant
14651 binaries in the toolchain have had the attributes set
14652 properly.
ee065d83 14653 _bfd_error_handler
871b3ab2 14654 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14655 obfd, ibfd);
14656 result = FALSE; */
ee065d83 14657 }
91e22acd
AS		 14658 /* Fall through. */
14659 case Tag_ABI_FP_denormal:
14660 case Tag_ABI_PCS_GOT_use:
14661 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14662 value if greater than 2 (for future-proofing). */
14663 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14664 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14665 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14666 out_attr[i].i = in_attr[i].i;
14667 break;
91e22acd 14668
75375b3e
MGD		 14669 case Tag_Virtualization_use:
14670 /* The virtualization tag effectively stores two bits of
14671 information: the intended use of TrustZone (in bit 0), and the
14672 intended use of Virtualization (in bit 1). */
14673 if (out_attr[i].i == 0)
14674 out_attr[i].i = in_attr[i].i;
14675 else if (in_attr[i].i != 0
14676 && in_attr[i].i != out_attr[i].i)
14677 {
14678 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14679 out_attr[i].i = 3;
14680 else
14681 {
14682 _bfd_error_handler
871b3ab2
AM		 14683 (_("error: %pB: unable to merge virtualization attributes "
14684 "with %pB"),
75375b3e
MGD		 14685 obfd, ibfd);
14686 result = FALSE;
14687 }
14688 }
14689 break;
91e22acd
AS		 14690
14691 case Tag_CPU_arch_profile:
14692 if (out_attr[i].i != in_attr[i].i)
14693 {
14694 /* 0 will merge with anything.
14695 'A' and 'S' merge to 'A'.
14696 'R' and 'S' merge to 'R'.
99059e56 14697 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14698 if (out_attr[i].i == 0
14699 || (out_attr[i].i == 'S'
14700 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14701 out_attr[i].i = in_attr[i].i;
14702 else if (in_attr[i].i == 0
14703 || (in_attr[i].i == 'S'
14704 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14705 ; /* Do nothing. */
91e22acd
AS		 14706 else
14707 {
14708 _bfd_error_handler
90b6238f 14709 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14710 ibfd,
14711 in_attr[i].i ? in_attr[i].i : '0',
14712 out_attr[i].i ? out_attr[i].i : '0');
14713 result = FALSE;
14714 }
14715 }
14716 break;
15afaa63
TP		 14717
14718 case Tag_DSP_extension:
14719 /* No need to change output value if any of:
14720 - pre (<=) ARMv5T input architecture (do not have DSP)
14721 - M input profile not ARMv7E-M and do not have DSP. */
14722 if (in_attr[Tag_CPU_arch].i <= 3
14723 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14724 && in_attr[Tag_CPU_arch].i != 13
14725 && in_attr[i].i == 0))
14726 ; /* Do nothing. */
14727 /* Output value should be 0 if DSP part of architecture, ie.
14728 - post (>=) ARMv5te architecture output
14729 - A, R or S profile output or ARMv7E-M output architecture. */
14730 else if (out_attr[Tag_CPU_arch].i >= 4
14731 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14732 || out_attr[Tag_CPU_arch_profile].i == 'R'
14733 || out_attr[Tag_CPU_arch_profile].i == 'S'
14734 || out_attr[Tag_CPU_arch].i == 13))
14735 out_attr[i].i = 0;
14736 /* Otherwise, DSP instructions are added and not part of output
14737 architecture. */
14738 else
14739 out_attr[i].i = 1;
14740 break;
14741
75375b3e 14742 case Tag_FP_arch:
62f3b8c8 14743 {
4547cb56
NC		 14744 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14745 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14746 when it's 0. It might mean absence of FP hardware if
99654aaf 14747 Tag_FP_arch is zero. */
4547cb56 14748
a715796b 14749#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14750 static const struct
14751 {
14752 int ver;
14753 int regs;
bca38921 14754 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14755 {
14756 {0, 0},
14757 {1, 16},
14758 {2, 16},
14759 {3, 32},
14760 {3, 16},
14761 {4, 32},
bca38921 14762 {4, 16},
a715796b
TG		 14763 {8, 32},
14764 {8, 16}
62f3b8c8
PB		 14765 };
14766 int ver;
14767 int regs;
14768 int newval;
14769
4547cb56
NC		 14770 /* If the output has no requirement about FP hardware,
14771 follow the requirement of the input. */
14772 if (out_attr[i].i == 0)
14773 {
4ec192e6
RE		 14774 /* This assert is still reasonable, we shouldn't
14775 produce the suspicious build attribute
14776 combination (See below for in_attr). */
4547cb56
NC		 14777 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14778 out_attr[i].i = in_attr[i].i;
14779 out_attr[Tag_ABI_HardFP_use].i
14780 = in_attr[Tag_ABI_HardFP_use].i;
14781 break;
14782 }
14783 /* If the input has no requirement about FP hardware, do
14784 nothing. */
14785 else if (in_attr[i].i == 0)
14786 {
4ec192e6
RE		 14787 /* We used to assert that Tag_ABI_HardFP_use was
14788 zero here, but we should never assert when
14789 consuming an object file that has suspicious
14790 build attributes. The single precision variant
14791 of 'no FP architecture' is still 'no FP
14792 architecture', so we just ignore the tag in this
14793 case. */
4547cb56
NC		 14794 break;
14795 }
14796
14797 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14798 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14799
14800 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14801 do nothing. */
14802 if (in_attr[Tag_ABI_HardFP_use].i == 0
14803 && out_attr[Tag_ABI_HardFP_use].i == 0)
14804 ;
14805 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14806 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14807 else if (in_attr[Tag_ABI_HardFP_use].i
14808 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14809 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14810
14811 /* Now we can handle Tag_FP_arch. */
14812
bca38921
MGD		 14813 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14814 pick the biggest. */
14815 if (in_attr[i].i >= VFP_VERSION_COUNT
14816 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14817 {
14818 out_attr[i] = in_attr[i];
14819 break;
14820 }
14821 /* The output uses the superset of input features
14822 (ISA version) and registers. */
14823 ver = vfp_versions[in_attr[i].i].ver;
14824 if (ver < vfp_versions[out_attr[i].i].ver)
14825 ver = vfp_versions[out_attr[i].i].ver;
14826 regs = vfp_versions[in_attr[i].i].regs;
14827 if (regs < vfp_versions[out_attr[i].i].regs)
14828 regs = vfp_versions[out_attr[i].i].regs;
14829 /* This assumes all possible supersets are also a valid
99059e56 14830 options. */
bca38921 14831 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14832 {
14833 if (regs == vfp_versions[newval].regs
14834 && ver == vfp_versions[newval].ver)
14835 break;
14836 }
14837 out_attr[i].i = newval;
14838 }
b1cc4aeb 14839 break;
ee065d83
PB		 14840 case Tag_PCS_config:
14841 if (out_attr[i].i == 0)
14842 out_attr[i].i = in_attr[i].i;
b6009aca 14843 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14844 {
14845 /* It's sometimes ok to mix different configs, so this is only
99059e56 14846 a warning. */
ee065d83 14847 _bfd_error_handler
90b6238f 14848 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14849 }
14850 break;
14851 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14852 if (in_attr[i].i != out_attr[i].i
14853 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14854 && in_attr[i].i != AEABI_R9_unused)
14855 {
14856 _bfd_error_handler
90b6238f 14857 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14858 result = FALSE;
ee065d83
PB		 14859 }
14860 if (out_attr[i].i == AEABI_R9_unused)
14861 out_attr[i].i = in_attr[i].i;
14862 break;
14863 case Tag_ABI_PCS_RW_data:
14864 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14865 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14866 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14867 {
14868 _bfd_error_handler
871b3ab2 14869 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14870 ibfd);
91e22acd 14871 result = FALSE;
ee065d83
PB		 14872 }
14873 /* Use the smallest value specified. */
14874 if (in_attr[i].i < out_attr[i].i)
14875 out_attr[i].i = in_attr[i].i;
14876 break;
ee065d83 14877 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14878 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14879 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14880 {
14881 _bfd_error_handler
871b3ab2 14882 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14883 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14884 }
a9dc9481 14885 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14886 out_attr[i].i = in_attr[i].i;
14887 break;
ee065d83
PB		 14888 case Tag_ABI_enum_size:
14889 if (in_attr[i].i != AEABI_enum_unused)
14890 {
14891 if (out_attr[i].i == AEABI_enum_unused
14892 || out_attr[i].i == AEABI_enum_forced_wide)
14893 {
14894 /* The existing object is compatible with anything.
14895 Use whatever requirements the new object has. */
14896 out_attr[i].i = in_attr[i].i;
14897 }
14898 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14899 && out_attr[i].i != in_attr[i].i
0ffa91dd 14900 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14901 {
91e22acd 14902 static const char *aeabi_enum_names[] =
bf21ed78 14903 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14904 const char *in_name =
14905 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14906 ? aeabi_enum_names[in_attr[i].i]
14907 : "<unknown>";
14908 const char *out_name =
14909 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14910 ? aeabi_enum_names[out_attr[i].i]
14911 : "<unknown>";
ee065d83 14912 _bfd_error_handler
871b3ab2 14913 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14914 ibfd, in_name, out_name);
ee065d83
PB		 14915 }
14916 }
14917 break;
14918 case Tag_ABI_VFP_args:
14919 /* Aready done. */
14920 break;
14921 case Tag_ABI_WMMX_args:
14922 if (in_attr[i].i != out_attr[i].i)
14923 {
14924 _bfd_error_handler
871b3ab2 14925 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14926 ibfd, obfd);
91e22acd 14927 result = FALSE;
ee065d83
PB		 14928 }
14929 break;
7b86a9fa
AS		 14930 case Tag_compatibility:
14931 /* Merged in target-independent code. */
14932 break;
91e22acd 14933 case Tag_ABI_HardFP_use:
4547cb56 14934 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14935 break;
14936 case Tag_ABI_FP_16bit_format:
14937 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14938 {
14939 if (in_attr[i].i != out_attr[i].i)
14940 {
14941 _bfd_error_handler
871b3ab2 14942 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14943 ibfd, obfd);
14944 result = FALSE;
14945 }
14946 }
14947 if (in_attr[i].i != 0)
14948 out_attr[i].i = in_attr[i].i;
14949 break;
7b86a9fa 14950
cd21e546 14951 case Tag_DIV_use:
ac56ee8f
MGD		 14952 /* A value of zero on input means that the divide instruction may
14953 be used if available in the base architecture as specified via
14954 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14955 the user did not want divide instructions. A value of 2
14956 explicitly means that divide instructions were allowed in ARM
14957 and Thumb state. */
14958 if (in_attr[i].i == out_attr[i].i)
14959 /* Do nothing. */ ;
14960 else if (elf32_arm_attributes_forbid_div (in_attr)
14961 && !elf32_arm_attributes_accept_div (out_attr))
14962 out_attr[i].i = 1;
14963 else if (elf32_arm_attributes_forbid_div (out_attr)
14964 && elf32_arm_attributes_accept_div (in_attr))
14965 out_attr[i].i = in_attr[i].i;
14966 else if (in_attr[i].i == 2)
14967 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14968 break;
14969
14970 case Tag_MPextension_use_legacy:
14971 /* We don't output objects with Tag_MPextension_use_legacy - we
14972 move the value to Tag_MPextension_use. */
14973 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14974 {
14975 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14976 {
14977 _bfd_error_handler
871b3ab2 14978 (_("%pB has both the current and legacy "
b38cadfb 14979 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14980 ibfd);
14981 result = FALSE;
14982 }
14983 }
14984
14985 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14986 out_attr[Tag_MPextension_use] = in_attr[i];
14987
14988 break;
14989
91e22acd 14990 case Tag_nodefaults:
2d0bb761
AS		 14991 /* This tag is set if it exists, but the value is unused (and is
14992 typically zero). We don't actually need to do anything here -
14993 the merge happens automatically when the type flags are merged
14994 below. */
91e22acd
AS		 14995 break;
14996 case Tag_also_compatible_with:
14997 /* Already done in Tag_CPU_arch. */
14998 break;
14999 case Tag_conformance:
15000 /* Keep the attribute if it matches. Throw it away otherwise.
15001 No attribute means no claim to conform. */
15002 if (!in_attr[i].s || !out_attr[i].s
15003 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
15004 out_attr[i].s = NULL;
15005 break;
3cfad14c 15006
91e22acd 15007 default:
e8b36cd1
JM		 15008 result
15009 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 15010 }
15011
15012 /* If out_attr was copied from in_attr then it won't have a type yet. */
15013 if (in_attr[i].type && !out_attr[i].type)
15014 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 15015 }
15016
104d59d1 15017 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 15018 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 15019 return FALSE;
ee065d83 15020
104d59d1 15021 /* Check for any attributes not known on ARM. */
e8b36cd1 15022 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 15023
91e22acd 15024 return result;
252b5132
RH		 15025}
15026
3a4a14e9
PB		 15027
15028/* Return TRUE if the two EABI versions are incompatible. */
15029
15030static bfd_boolean
15031elf32_arm_versions_compatible (unsigned iver, unsigned over)
15032{
15033 /* v4 and v5 are the same spec before and after it was released,
15034 so allow mixing them. */
15035 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
15036 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
15037 return TRUE;
15038
15039 return (iver == over);
15040}
15041
252b5132
RH		 15042/* Merge backend specific data from an object file to the output
15043 object file when linking. */
9b485d32 15044
b34976b6 15045static bfd_boolean
50e03d47 15046elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 15047
9b485d32
NC		 15048/* Display the flags field. */
15049
b34976b6 15050static bfd_boolean
57e8b36a 15051elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 15052{
fc830a83
NC		 15053 FILE * file = (FILE *) ptr;
15054 unsigned long flags;
252b5132
RH		 15055
15056 BFD_ASSERT (abfd != NULL && ptr != NULL);
15057
15058 /* Print normal ELF private data. */
15059 _bfd_elf_print_private_bfd_data (abfd, ptr);
15060
fc830a83 15061 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 15062 /* Ignore init flag - it may not be set, despite the flags field
15063 containing valid data. */
252b5132 15064
9b485d32 15065 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 15066
fc830a83
NC		 15067 switch (EF_ARM_EABI_VERSION (flags))
15068 {
15069 case EF_ARM_EABI_UNKNOWN:
4cc11e76 15070 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 15071 official ARM ELF extended ABI. Hence they are only decoded if
15072 the EABI version is not set. */
fd2ec330 15073 if (flags & EF_ARM_INTERWORK)
9b485d32 15074 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 15075
fd2ec330 15076 if (flags & EF_ARM_APCS_26)
6c571f00 15077 fprintf (file, " [APCS-26]");
fc830a83 15078 else
6c571f00 15079 fprintf (file, " [APCS-32]");
9a5aca8c 15080
96a846ea
RE		 15081 if (flags & EF_ARM_VFP_FLOAT)
15082 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 15083 else if (flags & EF_ARM_MAVERICK_FLOAT)
15084 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 15085 else
15086 fprintf (file, _(" [FPA float format]"));
15087
fd2ec330 15088 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 15089 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 15090
fd2ec330 15091 if (flags & EF_ARM_PIC)
9b485d32 15092 fprintf (file, _(" [position independent]"));
fc830a83 15093
fd2ec330 15094 if (flags & EF_ARM_NEW_ABI)
9b485d32 15095 fprintf (file, _(" [new ABI]"));
9a5aca8c 15096
fd2ec330 15097 if (flags & EF_ARM_OLD_ABI)
9b485d32 15098 fprintf (file, _(" [old ABI]"));
9a5aca8c 15099
fd2ec330 15100 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 15101 fprintf (file, _(" [software FP]"));
9a5aca8c 15102
96a846ea
RE		 15103 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
15104 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 15105 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
15106 | EF_ARM_MAVERICK_FLOAT);
fc830a83 15107 break;
9a5aca8c 15108
fc830a83 15109 case EF_ARM_EABI_VER1:
9b485d32 15110 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 15111
fc830a83 15112 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 15113 fprintf (file, _(" [sorted symbol table]"));
fc830a83 15114 else
9b485d32 15115 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 15116
fc830a83
NC		 15117 flags &= ~ EF_ARM_SYMSARESORTED;
15118 break;
9a5aca8c 15119
fd2ec330
PB		 15120 case EF_ARM_EABI_VER2:
15121 fprintf (file, _(" [Version2 EABI]"));
15122
15123 if (flags & EF_ARM_SYMSARESORTED)
15124 fprintf (file, _(" [sorted symbol table]"));
15125 else
15126 fprintf (file, _(" [unsorted symbol table]"));
15127
15128 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
15129 fprintf (file, _(" [dynamic symbols use segment index]"));
15130
15131 if (flags & EF_ARM_MAPSYMSFIRST)
15132 fprintf (file, _(" [mapping symbols precede others]"));
15133
99e4ae17 15134 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 15135 | EF_ARM_MAPSYMSFIRST);
15136 break;
15137
d507cf36
PB		 15138 case EF_ARM_EABI_VER3:
15139 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 15140 break;
15141
15142 case EF_ARM_EABI_VER4:
15143 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 15144 goto eabi;
d507cf36 15145
3a4a14e9
PB		 15146 case EF_ARM_EABI_VER5:
15147 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 15148
15149 if (flags & EF_ARM_ABI_FLOAT_SOFT)
15150 fprintf (file, _(" [soft-float ABI]"));
15151
15152 if (flags & EF_ARM_ABI_FLOAT_HARD)
15153 fprintf (file, _(" [hard-float ABI]"));
15154
15155 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
15156
3a4a14e9 15157 eabi:
d507cf36
PB		 15158 if (flags & EF_ARM_BE8)
15159 fprintf (file, _(" [BE8]"));
15160
15161 if (flags & EF_ARM_LE8)
15162 fprintf (file, _(" [LE8]"));
15163
15164 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
15165 break;
15166
fc830a83 15167 default:
9b485d32 15168 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 15169 break;
15170 }
252b5132 15171
fc830a83 15172 flags &= ~ EF_ARM_EABIMASK;
252b5132 15173
fc830a83 15174 if (flags & EF_ARM_RELEXEC)
9b485d32 15175 fprintf (file, _(" [relocatable executable]"));
252b5132 15176
18a20338
CL		 15177 if (flags & EF_ARM_PIC)
15178 fprintf (file, _(" [position independent]"));
15179
15180 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
15181 fprintf (file, _(" [FDPIC ABI supplement]"));
15182
15183 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 15184
15185 if (flags)
9b485d32 15186 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15187
252b5132
RH		 15188 fputc ('\n', file);
15189
b34976b6 15190 return TRUE;
252b5132
RH		 15191}
15192
15193static int
57e8b36a 15194elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15195{
2f0ca46a
NC		 15196 switch (ELF_ST_TYPE (elf_sym->st_info))
15197 {
15198 case STT_ARM_TFUNC:
15199 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15200
2f0ca46a
NC		 15201 case STT_ARM_16BIT:
15202 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15203 This allows us to distinguish between data used by Thumb instructions
15204 and non-data (which is probably code) inside Thumb regions of an
15205 executable. */
1a0eb693 15206 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15207 return ELF_ST_TYPE (elf_sym->st_info);
15208 break;
9a5aca8c 15209
ce855c42
NC		 15210 default:
15211 break;
2f0ca46a
NC		 15212 }
15213
15214 return type;
252b5132 15215}
f21f3fe0 15216
252b5132 15217static asection *
07adf181
AM		 15218elf32_arm_gc_mark_hook (asection *sec,
15219 struct bfd_link_info *info,
15220 Elf_Internal_Rela *rel,
15221 struct elf_link_hash_entry *h,
15222 Elf_Internal_Sym *sym)
252b5132
RH		 15223{
15224 if (h != NULL)
07adf181 15225 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15226 {
15227 case R_ARM_GNU_VTINHERIT:
15228 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15229 return NULL;
15230 }
9ad5cbcf 15231
07adf181 15232 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15233}
15234
780a67af
NC		 15235/* Look through the relocs for a section during the first phase. */
15236
b34976b6 15237static bfd_boolean
57e8b36a
NC		 15238elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15239 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15240{
b34976b6
AM		 15241 Elf_Internal_Shdr *symtab_hdr;
15242 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15243 const Elf_Internal_Rela *rel;
15244 const Elf_Internal_Rela *rel_end;
15245 bfd *dynobj;
5e681ec4 15246 asection *sreloc;
5e681ec4 15247 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15248 bfd_boolean call_reloc_p;
15249 bfd_boolean may_become_dynamic_p;
15250 bfd_boolean may_need_local_target_p;
ce98a316 15251 unsigned long nsyms;
9a5aca8c 15252
0e1862bb 15253 if (bfd_link_relocatable (info))
b34976b6 15254 return TRUE;
9a5aca8c 15255
0ffa91dd
NC		 15256 BFD_ASSERT (is_arm_elf (abfd));
15257
5e681ec4 15258 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15259 if (htab == NULL)
15260 return FALSE;
15261
5e681ec4 15262 sreloc = NULL;
9a5aca8c 15263
67687978
PB		 15264 /* Create dynamic sections for relocatable executables so that we can
15265 copy relocations. */
15266 if (htab->root.is_relocatable_executable
15267 && ! htab->root.dynamic_sections_created)
15268 {
15269 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15270 return FALSE;
15271 }
15272
cbc704f3
RS		 15273 if (htab->root.dynobj == NULL)
15274 htab->root.dynobj = abfd;
34e77a92
RS		 15275 if (!create_ifunc_sections (info))
15276 return FALSE;
cbc704f3
RS		 15277
15278 dynobj = htab->root.dynobj;
15279
0ffa91dd 15280 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15281 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15282 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15283
252b5132
RH		 15284 rel_end = relocs + sec->reloc_count;
15285 for (rel = relocs; rel < rel_end; rel++)
15286 {
34e77a92 15287 Elf_Internal_Sym *isym;
252b5132 15288 struct elf_link_hash_entry *h;
b7693d02 15289 struct elf32_arm_link_hash_entry *eh;
d42c267e 15290 unsigned int r_symndx;
eb043451 15291 int r_type;
9a5aca8c 15292
252b5132 15293 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15294 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15295 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15296
ce98a316
NC		 15297 if (r_symndx >= nsyms
15298 /* PR 9934: It is possible to have relocations that do not
15299 refer to symbols, thus it is also possible to have an
15300 object file containing relocations but no symbol table. */
cf35638d 15301 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15302 {
871b3ab2 15303 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15304 r_symndx);
ba93b8ac
DJ		 15305 return FALSE;
15306 }
15307
34e77a92
RS		 15308 h = NULL;
15309 isym = NULL;
15310 if (nsyms > 0)
973a3492 15311 {
34e77a92
RS		 15312 if (r_symndx < symtab_hdr->sh_info)
15313 {
15314 /* A local symbol. */
f1dfbfdb 15315 isym = bfd_sym_from_r_symndx (&htab->root.sym_cache,
34e77a92
RS		 15316 abfd, r_symndx);
15317 if (isym == NULL)
15318 return FALSE;
15319 }
15320 else
15321 {
15322 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15323 while (h->root.type == bfd_link_hash_indirect
15324 || h->root.type == bfd_link_hash_warning)
15325 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15326 }
973a3492 15327 }
9a5aca8c 15328
b7693d02
DJ		 15329 eh = (struct elf32_arm_link_hash_entry *) h;
15330
f6e32f6d
RS		 15331 call_reloc_p = FALSE;
15332 may_become_dynamic_p = FALSE;
15333 may_need_local_target_p = FALSE;
15334
0855e32b
NS		 15335 /* Could be done earlier, if h were already available. */
15336 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15337 switch (r_type)
99059e56 15338 {
e8b09b87
CL		 15339 case R_ARM_GOTOFFFUNCDESC:
15340 {
15341 if (h == NULL)
15342 {
15343 if (!elf32_arm_allocate_local_sym_info (abfd))
15344 return FALSE;
15345 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15346 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15347 }
15348 else
15349 {
15350 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15351 }
15352 }
15353 break;
15354
15355 case R_ARM_GOTFUNCDESC:
15356 {
15357 if (h == NULL)
15358 {
15359 /* Such a relocation is not supposed to be generated
15360 by gcc on a static function. */
15361 /* Anyway if needed it could be handled. */
15362 abort();
15363 }
15364 else
15365 {
15366 eh->fdpic_cnts.gotfuncdesc_cnt++;
15367 }
15368 }
15369 break;
15370
15371 case R_ARM_FUNCDESC:
15372 {
15373 if (h == NULL)
15374 {
15375 if (!elf32_arm_allocate_local_sym_info (abfd))
15376 return FALSE;
15377 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15378 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15379 }
15380 else
15381 {
15382 eh->fdpic_cnts.funcdesc_cnt++;
15383 }
15384 }
15385 break;
15386
5e681ec4 15387 case R_ARM_GOT32:
eb043451 15388 case R_ARM_GOT_PREL:
ba93b8ac 15389 case R_ARM_TLS_GD32:
5c5a4843 15390 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15391 case R_ARM_TLS_IE32:
5c5a4843 15392 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15393 case R_ARM_TLS_GOTDESC:
15394 case R_ARM_TLS_DESCSEQ:
15395 case R_ARM_THM_TLS_DESCSEQ:
15396 case R_ARM_TLS_CALL:
15397 case R_ARM_THM_TLS_CALL:
5e681ec4 15398 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15399 {
15400 int tls_type, old_tls_type;
5e681ec4 15401
ba93b8ac
DJ		 15402 switch (r_type)
15403 {
15404 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15405 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15406
ba93b8ac 15407 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15408 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15409
0855e32b
NS		 15410 case R_ARM_TLS_GOTDESC:
15411 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15412 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15413 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15414
ba93b8ac
DJ		 15415 default: tls_type = GOT_NORMAL; break;
15416 }
252b5132 15417
0e1862bb 15418 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15419 info->flags |= DF_STATIC_TLS;
15420
ba93b8ac
DJ		 15421 if (h != NULL)
15422 {
15423 h->got.refcount++;
15424 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15425 }
15426 else
15427 {
ba93b8ac 15428 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15429 if (!elf32_arm_allocate_local_sym_info (abfd))
15430 return FALSE;
15431 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15432 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15433 }
15434
0855e32b 15435 /* If a variable is accessed with both tls methods, two
99059e56 15436 slots may be created. */
0855e32b
NS		 15437 if (GOT_TLS_GD_ANY_P (old_tls_type)
15438 && GOT_TLS_GD_ANY_P (tls_type))
15439 tls_type |= old_tls_type;
15440
15441 /* We will already have issued an error message if there
15442 is a TLS/non-TLS mismatch, based on the symbol
15443 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15444 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15445 && tls_type != GOT_NORMAL)
15446 tls_type |= old_tls_type;
15447
0855e32b 15448 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15449 method, we're able to relax. Turn off the GDESC flag,
15450 without messing up with any other kind of tls types
6a631e86 15451 that may be involved. */
0855e32b
NS		 15452 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15453 tls_type &= ~GOT_TLS_GDESC;
15454
ba93b8ac
DJ		 15455 if (old_tls_type != tls_type)
15456 {
15457 if (h != NULL)
15458 elf32_arm_hash_entry (h)->tls_type = tls_type;
15459 else
15460 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15461 }
15462 }
8029a119 15463 /* Fall through. */
ba93b8ac
DJ		 15464
15465 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15466 case R_ARM_TLS_LDM32_FDPIC:
15467 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15468 htab->tls_ldm_got.refcount++;
8029a119 15469 /* Fall through. */
252b5132 15470
c19d1205 15471 case R_ARM_GOTOFF32:
5e681ec4 15472 case R_ARM_GOTPC:
cbc704f3
RS		 15473 if (htab->root.sgot == NULL
15474 && !create_got_section (htab->root.dynobj, info))
15475 return FALSE;
252b5132
RH		 15476 break;
15477
252b5132 15478 case R_ARM_PC24:
7359ea65 15479 case R_ARM_PLT32:
5b5bb741
PB		 15480 case R_ARM_CALL:
15481 case R_ARM_JUMP24:
eb043451 15482 case R_ARM_PREL31:
c19d1205 15483 case R_ARM_THM_CALL:
bd97cb95
DJ		 15484 case R_ARM_THM_JUMP24:
15485 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15486 call_reloc_p = TRUE;
15487 may_need_local_target_p = TRUE;
15488 break;
15489
15490 case R_ARM_ABS12:
15491 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15492 ldr __GOTT_INDEX__ offsets. */
90c14f0c 15493 if (htab->root.target_os != is_vxworks)
f6e32f6d
RS		 15494 {
15495 may_need_local_target_p = TRUE;
15496 break;
15497 }
aebf9be7 15498 else goto jump_over;
9eaff861 15499
f6e32f6d 15500 /* Fall through. */
39623e12 15501
96c23d59
JM		 15502 case R_ARM_MOVW_ABS_NC:
15503 case R_ARM_MOVT_ABS:
15504 case R_ARM_THM_MOVW_ABS_NC:
15505 case R_ARM_THM_MOVT_ABS:
0e1862bb 15506 if (bfd_link_pic (info))
96c23d59 15507 {
4eca0228 15508 _bfd_error_handler
871b3ab2 15509 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15510 abfd, elf32_arm_howto_table_1[r_type].name,
15511 (h) ? h->root.root.string : "a local symbol");
15512 bfd_set_error (bfd_error_bad_value);
15513 return FALSE;
15514 }
15515
15516 /* Fall through. */
39623e12
PB		 15517 case R_ARM_ABS32:
15518 case R_ARM_ABS32_NOI:
aebf9be7 15519 jump_over:
0e1862bb 15520 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15521 {
15522 h->pointer_equality_needed = 1;
15523 }
15524 /* Fall through. */
39623e12
PB		 15525 case R_ARM_REL32:
15526 case R_ARM_REL32_NOI:
b6895b4f
PB		 15527 case R_ARM_MOVW_PREL_NC:
15528 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15529 case R_ARM_THM_MOVW_PREL_NC:
15530 case R_ARM_THM_MOVT_PREL:
39623e12 15531
b7693d02 15532 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15533 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15534 || htab->fdpic_p)
34e77a92
RS		 15535 && (sec->flags & SEC_ALLOC) != 0)
15536 {
15537 if (h == NULL
469a3493 15538 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15539 {
15540 /* In shared libraries and relocatable executables,
15541 we treat local relative references as calls;
15542 see the related SYMBOL_CALLS_LOCAL code in
15543 allocate_dynrelocs. */
15544 call_reloc_p = TRUE;
15545 may_need_local_target_p = TRUE;
15546 }
15547 else
15548 /* We are creating a shared library or relocatable
15549 executable, and this is a reloc against a global symbol,
15550 or a non-PC-relative reloc against a local symbol.
15551 We may need to copy the reloc into the output. */
15552 may_become_dynamic_p = TRUE;
15553 }
f6e32f6d
RS		 15554 else
15555 may_need_local_target_p = TRUE;
252b5132
RH		 15556 break;
15557
99059e56
RM		 15558 /* This relocation describes the C++ object vtable hierarchy.
15559 Reconstruct it for later use during GC. */
15560 case R_ARM_GNU_VTINHERIT:
15561 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15562 return FALSE;
15563 break;
15564
15565 /* This relocation describes which C++ vtable entries are actually
15566 used. Record for later use during GC. */
15567 case R_ARM_GNU_VTENTRY:
a0ea3a14 15568 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
99059e56
RM		 15569 return FALSE;
15570 break;
15571 }
f6e32f6d
RS		 15572
15573 if (h != NULL)
15574 {
15575 if (call_reloc_p)
15576 /* We may need a .plt entry if the function this reloc
15577 refers to is in a different object, regardless of the
15578 symbol's type. We can't tell for sure yet, because
15579 something later might force the symbol local. */
15580 h->needs_plt = 1;
15581 else if (may_need_local_target_p)
15582 /* If this reloc is in a read-only section, we might
15583 need a copy reloc. We can't check reliably at this
15584 stage whether the section is read-only, as input
15585 sections have not yet been mapped to output sections.
15586 Tentatively set the flag for now, and correct in
15587 adjust_dynamic_symbol. */
15588 h->non_got_ref = 1;
15589 }
15590
34e77a92
RS		 15591 if (may_need_local_target_p
15592 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15593 {
34e77a92
RS		 15594 union gotplt_union *root_plt;
15595 struct arm_plt_info *arm_plt;
15596 struct arm_local_iplt_info *local_iplt;
15597
15598 if (h != NULL)
15599 {
15600 root_plt = &h->plt;
15601 arm_plt = &eh->plt;
15602 }
15603 else
15604 {
15605 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15606 if (local_iplt == NULL)
15607 return FALSE;
15608 root_plt = &local_iplt->root;
15609 arm_plt = &local_iplt->arm;
15610 }
15611
f6e32f6d
RS		 15612 /* If the symbol is a function that doesn't bind locally,
15613 this relocation will need a PLT entry. */
a8c887dd
NC		 15614 if (root_plt->refcount != -1)
15615 root_plt->refcount += 1;
34e77a92
RS		 15616
15617 if (!call_reloc_p)
15618 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15619
15620 /* It's too early to use htab->use_blx here, so we have to
15621 record possible blx references separately from
15622 relocs that definitely need a thumb stub. */
15623
15624 if (r_type == R_ARM_THM_CALL)
34e77a92 15625 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15626
15627 if (r_type == R_ARM_THM_JUMP24
15628 || r_type == R_ARM_THM_JUMP19)
34e77a92 15629 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15630 }
15631
15632 if (may_become_dynamic_p)
15633 {
15634 struct elf_dyn_relocs *p, **head;
15635
15636 /* Create a reloc section in dynobj. */
15637 if (sreloc == NULL)
15638 {
15639 sreloc = _bfd_elf_make_dynamic_reloc_section
15640 (sec, dynobj, 2, abfd, ! htab->use_rel);
15641
15642 if (sreloc == NULL)
15643 return FALSE;
15644
15645 /* BPABI objects never have dynamic relocations mapped. */
90c14f0c 15646 if (htab->root.target_os == is_symbian)
f6e32f6d
RS		 15647 {
15648 flagword flags;
15649
fd361982 15650 flags = bfd_section_flags (sreloc);
f6e32f6d 15651 flags &= ~(SEC_LOAD | SEC_ALLOC);
fd361982 15652 bfd_set_section_flags (sreloc, flags);
f6e32f6d
RS		 15653 }
15654 }
15655
15656 /* If this is a global symbol, count the number of
15657 relocations we need for this symbol. */
15658 if (h != NULL)
190eb1dd 15659 head = &h->dyn_relocs;
f6e32f6d
RS		 15660 else
15661 {
34e77a92
RS		 15662 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15663 if (head == NULL)
f6e32f6d 15664 return FALSE;
f6e32f6d
RS		 15665 }
15666
15667 p = *head;
15668 if (p == NULL || p->sec != sec)
15669 {
986f0783 15670 size_t amt = sizeof *p;
f6e32f6d
RS		 15671
15672 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15673 if (p == NULL)
15674 return FALSE;
15675 p->next = *head;
15676 *head = p;
15677 p->sec = sec;
15678 p->count = 0;
15679 p->pc_count = 0;
15680 }
15681
469a3493 15682 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15683 p->pc_count += 1;
15684 p->count += 1;
e8b09b87
CL		 15685 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15686 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15687 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15688 that will become rofixup. */
15689 /* This is due to the fact that we suppose all will become rofixup. */
15690 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15691 _bfd_error_handler
15692 (_("FDPIC does not yet support %s relocation"
15693 " to become dynamic for executable"),
15694 elf32_arm_howto_table_1[r_type].name);
15695 abort();
15696 }
f6e32f6d 15697 }
252b5132 15698 }
f21f3fe0 15699
b34976b6 15700 return TRUE;
252b5132
RH		 15701}
15702
9eaff861
AO		 15703static void
15704elf32_arm_update_relocs (asection *o,
15705 struct bfd_elf_section_reloc_data *reldata)
15706{
15707 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15708 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15709 const struct elf_backend_data *bed;
15710 _arm_elf_section_data *eado;
15711 struct bfd_link_order *p;
15712 bfd_byte *erela_head, *erela;
15713 Elf_Internal_Rela *irela_head, *irela;
15714 Elf_Internal_Shdr *rel_hdr;
15715 bfd *abfd;
15716 unsigned int count;
15717
15718 eado = get_arm_elf_section_data (o);
15719
15720 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15721 return;
15722
15723 abfd = o->owner;
15724 bed = get_elf_backend_data (abfd);
15725 rel_hdr = reldata->hdr;
15726
15727 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15728 {
15729 swap_in = bed->s->swap_reloc_in;
15730 swap_out = bed->s->swap_reloc_out;
15731 }
15732 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15733 {
15734 swap_in = bed->s->swap_reloca_in;
15735 swap_out = bed->s->swap_reloca_out;
15736 }
15737 else
15738 abort ();
15739
15740 erela_head = rel_hdr->contents;
15741 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15742 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15743
15744 erela = erela_head;
15745 irela = irela_head;
15746 count = 0;
15747
15748 for (p = o->map_head.link_order; p; p = p->next)
15749 {
15750 if (p->type == bfd_section_reloc_link_order
15751 || p->type == bfd_symbol_reloc_link_order)
15752 {
15753 (*swap_in) (abfd, erela, irela);
15754 erela += rel_hdr->sh_entsize;
15755 irela++;
15756 count++;
15757 }
15758 else if (p->type == bfd_indirect_link_order)
15759 {
15760 struct bfd_elf_section_reloc_data *input_reldata;
15761 arm_unwind_table_edit *edit_list, *edit_tail;
15762 _arm_elf_section_data *eadi;
15763 bfd_size_type j;
15764 bfd_vma offset;
15765 asection *i;
15766
15767 i = p->u.indirect.section;
15768
15769 eadi = get_arm_elf_section_data (i);
15770 edit_list = eadi->u.exidx.unwind_edit_list;
15771 edit_tail = eadi->u.exidx.unwind_edit_tail;
539300fb 15772 offset = i->output_offset;
9eaff861
AO		 15773
15774 if (eadi->elf.rel.hdr &&
15775 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15776 input_reldata = &eadi->elf.rel;
15777 else if (eadi->elf.rela.hdr &&
15778 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15779 input_reldata = &eadi->elf.rela;
15780 else
15781 abort ();
15782
15783 if (edit_list)
15784 {
15785 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15786 {
15787 arm_unwind_table_edit *edit_node, *edit_next;
15788 bfd_vma bias;
c48182bf 15789 bfd_vma reloc_index;
9eaff861
AO		 15790
15791 (*swap_in) (abfd, erela, irela);
c48182bf 15792 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15793
15794 bias = 0;
15795 edit_node = edit_list;
15796 for (edit_next = edit_list;
c48182bf 15797 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15798 edit_next = edit_node->next)
15799 {
15800 bias++;
15801 edit_node = edit_next;
15802 }
15803
15804 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15805 || edit_node->index != reloc_index)
9eaff861
AO		 15806 {
15807 irela->r_offset -= bias * 8;
15808 irela++;
15809 count++;
15810 }
15811
15812 erela += rel_hdr->sh_entsize;
15813 }
15814
15815 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15816 {
15817 /* New relocation entity. */
15818 asection *text_sec = edit_tail->linked_section;
15819 asection *text_out = text_sec->output_section;
15820 bfd_vma exidx_offset = offset + i->size - 8;
15821
15822 irela->r_addend = 0;
15823 irela->r_offset = exidx_offset;
15824 irela->r_info = ELF32_R_INFO
15825 (text_out->target_index, R_ARM_PREL31);
15826 irela++;
15827 count++;
15828 }
15829 }
15830 else
15831 {
15832 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15833 {
15834 (*swap_in) (abfd, erela, irela);
15835 erela += rel_hdr->sh_entsize;
15836 irela++;
15837 }
15838
15839 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15840 }
15841 }
15842 }
15843
15844 reldata->count = count;
15845 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15846
15847 erela = erela_head;
15848 irela = irela_head;
15849 while (count > 0)
15850 {
15851 (*swap_out) (abfd, irela, erela);
15852 erela += rel_hdr->sh_entsize;
15853 irela++;
15854 count--;
15855 }
15856
15857 free (irela_head);
15858
15859 /* Hashes are no longer valid. */
15860 free (reldata->hashes);
15861 reldata->hashes = NULL;
15862}
15863
6a5bb875 15864/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15865 required if the corresponding code section is marked. Similarly, ARMv8-M
15866 secure entry functions can only be referenced by SG veneers which are
15867 created after the GC process. They need to be marked in case they reside in
15868 their own section (as would be the case if code was compiled with
15869 -ffunction-sections). */
6a5bb875
PB		 15870
15871static bfd_boolean
906e58ca
NC		 15872elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15873 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15874{
15875 bfd *sub;
15876 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15877 asection *cmse_sec;
15878 obj_attribute *out_attr;
15879 Elf_Internal_Shdr *symtab_hdr;
15880 unsigned i, sym_count, ext_start;
15881 const struct elf_backend_data *bed;
15882 struct elf_link_hash_entry **sym_hashes;
15883 struct elf32_arm_link_hash_entry *cmse_hash;
15884 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
bb32413f
SP		 15885 bfd_boolean debug_sec_need_to_be_marked = FALSE;
15886 asection *isec;
6a5bb875 15887
7f6ab9f8
AM		 15888 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15889
4ba2ef8f
TP		 15890 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15891 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15892 && out_attr[Tag_CPU_arch_profile].i == 'M';
15893
6a5bb875
PB		 15894 /* Marking EH data may cause additional code sections to be marked,
15895 requiring multiple passes. */
15896 again = TRUE;
15897 while (again)
15898 {
15899 again = FALSE;
c72f2fb2 15900 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15901 {
15902 asection *o;
15903
0ffa91dd 15904 if (! is_arm_elf (sub))
6a5bb875
PB		 15905 continue;
15906
15907 elf_shdrp = elf_elfsections (sub);
15908 for (o = sub->sections; o != NULL; o = o->next)
15909 {
15910 Elf_Internal_Shdr *hdr;
0ffa91dd 15911
6a5bb875 15912 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15913 if (hdr->sh_type == SHT_ARM_EXIDX
15914 && hdr->sh_link
15915 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15916 && !o->gc_mark
15917 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15918 {
15919 again = TRUE;
15920 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15921 return FALSE;
15922 }
15923 }
4ba2ef8f
TP		 15924
15925 /* Mark section holding ARMv8-M secure entry functions. We mark all
15926 of them so no need for a second browsing. */
15927 if (is_v8m && first_bfd_browse)
15928 {
15929 sym_hashes = elf_sym_hashes (sub);
15930 bed = get_elf_backend_data (sub);
15931 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15932 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15933 ext_start = symtab_hdr->sh_info;
15934
15935 /* Scan symbols. */
15936 for (i = ext_start; i < sym_count; i++)
15937 {
15938 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15939
15940 /* Assume it is a special symbol. If not, cmse_scan will
15941 warn about it and user can do something about it. */
baf46cd7
AM		 15942 if (CONST_STRNEQ (cmse_hash->root.root.root.string,
15943 CMSE_PREFIX))
4ba2ef8f
TP		 15944 {
15945 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15946 if (!cmse_sec->gc_mark
15947 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f 15948 return FALSE;
bb32413f
SP		 15949 /* The debug sections related to these secure entry
15950 functions are marked on enabling below flag. */
15951 debug_sec_need_to_be_marked = TRUE;
4ba2ef8f
TP		 15952 }
15953 }
bb32413f
SP		 15954
15955 if (debug_sec_need_to_be_marked)
15956 {
15957 /* Looping over all the sections of the object file containing
15958 Armv8-M secure entry functions and marking all the debug
15959 sections. */
15960 for (isec = sub->sections; isec != NULL; isec = isec->next)
15961 {
15962 /* If not a debug sections, skip it. */
15963 if (!isec->gc_mark && (isec->flags & SEC_DEBUGGING))
15964 isec->gc_mark = 1 ;
15965 }
15966 debug_sec_need_to_be_marked = FALSE;
15967 }
4ba2ef8f 15968 }
6a5bb875 15969 }
4ba2ef8f 15970 first_bfd_browse = FALSE;
6a5bb875
PB		 15971 }
15972
15973 return TRUE;
15974}
15975
3c9458e9
NC		 15976/* Treat mapping symbols as special target symbols. */
15977
15978static bfd_boolean
15979elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15980{
b0796911
PB		 15981 return bfd_is_arm_special_symbol_name (sym->name,
15982 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15983}
15984
e7679060
AM		 15985/* If the ELF symbol SYM might be a function in SEC, return the
15986 function size and set *CODE_OFF to the function's entry point,
15987 otherwise return zero. */
252b5132 15988
e7679060
AM		 15989static bfd_size_type
15990elf32_arm_maybe_function_sym (const asymbol *sym, asection *sec,
15991 bfd_vma *code_off)
15992{
15993 bfd_size_type size;
252b5132 15994
e7679060
AM		 15995 if ((sym->flags & (BSF_SECTION_SYM | BSF_FILE | BSF_OBJECT
15996 | BSF_THREAD_LOCAL | BSF_RELC | BSF_SRELC)) != 0
15997 || sym->section != sec)
15998 return 0;
252b5132 15999
e7679060
AM		 16000 if (!(sym->flags & BSF_SYNTHETIC))
16001 switch (ELF_ST_TYPE (((elf_symbol_type *) sym)->internal_elf_sym.st_info))
16002 {
252b5132
RH		 16003 case STT_FUNC:
16004 case STT_ARM_TFUNC:
9d2da7ca 16005 case STT_NOTYPE:
252b5132 16006 break;
e7679060
AM		 16007 default:
16008 return 0;
16009 }
0367ecfb 16010
e7679060
AM		 16011 if ((sym->flags & BSF_LOCAL)
16012 && bfd_is_arm_special_symbol_name (sym->name,
16013 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
16014 return 0;
0367ecfb 16015
e7679060
AM		 16016 *code_off = sym->value;
16017 size = 0;
16018 if (!(sym->flags & BSF_SYNTHETIC))
16019 size = ((elf_symbol_type *) sym)->internal_elf_sym.st_size;
16020 if (size == 0)
16021 size = 1;
16022 return size;
252b5132
RH		 16023}
16024
4ab527b0 16025static bfd_boolean
07d6d2b8 16026elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 16027 const char ** filename_ptr,
16028 const char ** functionname_ptr,
16029 unsigned int * line_ptr)
16030{
16031 bfd_boolean found;
16032 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
16033 functionname_ptr, line_ptr,
16034 & elf_tdata (abfd)->dwarf2_find_line_info);
16035 return found;
16036}
16037
252b5132
RH		 16038/* Adjust a symbol defined by a dynamic object and referenced by a
16039 regular object. The current definition is in some section of the
16040 dynamic object, but we're not including those sections. We have to
16041 change the definition to something the rest of the link can
16042 understand. */
16043
b34976b6 16044static bfd_boolean
57e8b36a
NC		 16045elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
16046 struct elf_link_hash_entry * h)
252b5132
RH		 16047{
16048 bfd * dynobj;
5474d94f 16049 asection *s, *srel;
b7693d02 16050 struct elf32_arm_link_hash_entry * eh;
67687978 16051 struct elf32_arm_link_hash_table *globals;
252b5132 16052
67687978 16053 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16054 if (globals == NULL)
16055 return FALSE;
16056
252b5132
RH		 16057 dynobj = elf_hash_table (info)->dynobj;
16058
16059 /* Make sure we know what is going on here. */
16060 BFD_ASSERT (dynobj != NULL
f5385ebf 16061 && (h->needs_plt
34e77a92 16062 || h->type == STT_GNU_IFUNC
60d67dc8 16063 || h->is_weakalias
f5385ebf
AM		 16064 || (h->def_dynamic
16065 && h->ref_regular
16066 && !h->def_regular)));
252b5132 16067
b7693d02
DJ		 16068 eh = (struct elf32_arm_link_hash_entry *) h;
16069
252b5132
RH		 16070 /* If this is a function, put it in the procedure linkage table. We
16071 will fill in the contents of the procedure linkage table later,
16072 when we know the address of the .got section. */
34e77a92 16073 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 16074 {
34e77a92
RS		 16075 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16076 symbol binds locally. */
5e681ec4 16077 if (h->plt.refcount <= 0
34e77a92
RS		 16078 || (h->type != STT_GNU_IFUNC
16079 && (SYMBOL_CALLS_LOCAL (info, h)
16080 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16081 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 16082 {
16083 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 16084 file, but the symbol was never referred to by a dynamic
16085 object, or if all references were garbage collected. In
16086 such a case, we don't actually need to build a procedure
16087 linkage table, and we can just do a PC24 reloc instead. */
16088 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16089 eh->plt.thumb_refcount = 0;
16090 eh->plt.maybe_thumb_refcount = 0;
16091 eh->plt.noncall_refcount = 0;
f5385ebf 16092 h->needs_plt = 0;
252b5132
RH		 16093 }
16094
b34976b6 16095 return TRUE;
252b5132 16096 }
5e681ec4 16097 else
b7693d02
DJ		 16098 {
16099 /* It's possible that we incorrectly decided a .plt reloc was
16100 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16101 in check_relocs. We can't decide accurately between function
16102 and non-function syms in check-relocs; Objects loaded later in
16103 the link may change h->type. So fix it now. */
16104 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16105 eh->plt.thumb_refcount = 0;
16106 eh->plt.maybe_thumb_refcount = 0;
16107 eh->plt.noncall_refcount = 0;
b7693d02 16108 }
252b5132
RH		 16109
16110 /* If this is a weak symbol, and there is a real definition, the
16111 processor independent code will have arranged for us to see the
16112 real definition first, and we can just use the same value. */
60d67dc8 16113 if (h->is_weakalias)
252b5132 16114 {
60d67dc8
AM		 16115 struct elf_link_hash_entry *def = weakdef (h);
16116 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16117 h->root.u.def.section = def->root.u.def.section;
16118 h->root.u.def.value = def->root.u.def.value;
b34976b6 16119 return TRUE;
252b5132
RH		 16120 }
16121
ba93b8ac
DJ		 16122 /* If there are no non-GOT references, we do not need a copy
16123 relocation. */
16124 if (!h->non_got_ref)
16125 return TRUE;
16126
252b5132
RH		 16127 /* This is a reference to a symbol defined by a dynamic object which
16128 is not a function. */
16129
16130 /* If we are creating a shared library, we must presume that the
16131 only references to the symbol are via the global offset table.
16132 For such cases we need not do anything here; the relocations will
67687978
PB		 16133 be handled correctly by relocate_section. Relocatable executables
16134 can reference data in shared objects directly, so we don't need to
16135 do anything here. */
0e1862bb 16136 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16137 return TRUE;
252b5132
RH		 16138
16139 /* We must allocate the symbol in our .dynbss section, which will
16140 become part of the .bss section of the executable. There will be
16141 an entry for this symbol in the .dynsym section. The dynamic
16142 object will contain position independent code, so all references
16143 from the dynamic object to this symbol will go through the global
16144 offset table. The dynamic linker will use the .dynsym entry to
16145 determine the address it must put in the global offset table, so
16146 both the dynamic object and the regular object will refer to the
16147 same memory location for the variable. */
5522f910
NC		 16148 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16149 linker to copy the initial value out of the dynamic object and into
16150 the runtime process image. We need to remember the offset into the
00a97672 16151 .rel(a).bss section we are going to use. */
5474d94f
AM		 16152 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16153 {
16154 s = globals->root.sdynrelro;
16155 srel = globals->root.sreldynrelro;
16156 }
16157 else
16158 {
16159 s = globals->root.sdynbss;
16160 srel = globals->root.srelbss;
16161 }
5522f910
NC		 16162 if (info->nocopyreloc == 0
16163 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16164 && h->size != 0)
252b5132 16165 {
47beaa6a 16166 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16167 h->needs_copy = 1;
252b5132
RH		 16168 }
16169
6cabe1ea 16170 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16171}
16172
5e681ec4
PB		 16173/* Allocate space in .plt, .got and associated reloc sections for
16174 dynamic relocs. */
16175
16176static bfd_boolean
47beaa6a 16177allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16178{
16179 struct bfd_link_info *info;
16180 struct elf32_arm_link_hash_table *htab;
16181 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16182 struct elf_dyn_relocs *p;
5e681ec4
PB		 16183
16184 if (h->root.type == bfd_link_hash_indirect)
16185 return TRUE;
16186
e6a6bb22
AM		 16187 eh = (struct elf32_arm_link_hash_entry *) h;
16188
5e681ec4
PB		 16189 info = (struct bfd_link_info *) inf;
16190 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16191 if (htab == NULL)
16192 return FALSE;
5e681ec4 16193
34e77a92 16194 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16195 && h->plt.refcount > 0)
16196 {
16197 /* Make sure this symbol is output as a dynamic symbol.
16198 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16199 if (h->dynindx == -1 && !h->forced_local
16200 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16201 {
c152c796 16202 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16203 return FALSE;
16204 }
16205
34e77a92
RS		 16206 /* If the call in the PLT entry binds locally, the associated
16207 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16208 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16209 than the .plt section. */
16210 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16211 {
16212 eh->is_iplt = 1;
16213 if (eh->plt.noncall_refcount == 0
16214 && SYMBOL_REFERENCES_LOCAL (info, h))
16215 /* All non-call references can be resolved directly.
16216 This means that they can (and in some cases, must)
16217 resolve directly to the run-time target, rather than
16218 to the PLT. That in turns means that any .got entry
16219 would be equal to the .igot.plt entry, so there's
16220 no point having both. */
16221 h->got.refcount = 0;
16222 }
16223
0e1862bb 16224 if (bfd_link_pic (info)
34e77a92 16225 || eh->is_iplt
7359ea65 16226 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16227 {
34e77a92 16228 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16229
5e681ec4
PB		 16230 /* If this symbol is not defined in a regular file, and we are
16231 not generating a shared library, then set the symbol to this
16232 location in the .plt. This is required to make function
16233 pointers compare as equal between the normal executable and
16234 the shared library. */
0e1862bb 16235 if (! bfd_link_pic (info)
f5385ebf 16236 && !h->def_regular)
5e681ec4 16237 {
34e77a92 16238 h->root.u.def.section = htab->root.splt;
5e681ec4 16239 h->root.u.def.value = h->plt.offset;
5e681ec4 16240
67d74e43
DJ		 16241 /* Make sure the function is not marked as Thumb, in case
16242 it is the target of an ABS32 relocation, which will
16243 point to the PLT entry. */
39d911fc 16244 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16245 }
022f8312 16246
00a97672
RS		 16247 /* VxWorks executables have a second set of relocations for
16248 each PLT entry. They go in a separate relocation section,
16249 which is processed by the kernel loader. */
90c14f0c 16250 if (htab->root.target_os == is_vxworks && !bfd_link_pic (info))
00a97672
RS		 16251 {
16252 /* There is a relocation for the initial PLT entry:
16253 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16254 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16255 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16256
16257 /* There are two extra relocations for each subsequent
16258 PLT entry: an R_ARM_32 relocation for the GOT entry,
16259 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16260 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16261 }
5e681ec4
PB		 16262 }
16263 else
16264 {
16265 h->plt.offset = (bfd_vma) -1;
f5385ebf 16266 h->needs_plt = 0;
5e681ec4
PB		 16267 }
16268 }
16269 else
16270 {
16271 h->plt.offset = (bfd_vma) -1;
f5385ebf 16272 h->needs_plt = 0;
5e681ec4
PB		 16273 }
16274
0855e32b
NS		 16275 eh = (struct elf32_arm_link_hash_entry *) h;
16276 eh->tlsdesc_got = (bfd_vma) -1;
16277
5e681ec4
PB		 16278 if (h->got.refcount > 0)
16279 {
16280 asection *s;
16281 bfd_boolean dyn;
ba93b8ac
DJ		 16282 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16283 int indx;
5e681ec4
PB		 16284
16285 /* Make sure this symbol is output as a dynamic symbol.
16286 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16287 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16288 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16289 {
c152c796 16290 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16291 return FALSE;
16292 }
16293
90c14f0c 16294 if (htab->root.target_os != is_symbian)
e5a52504 16295 {
362d30a1 16296 s = htab->root.sgot;
e5a52504 16297 h->got.offset = s->size;
ba93b8ac
DJ		 16298
16299 if (tls_type == GOT_UNKNOWN)
16300 abort ();
16301
16302 if (tls_type == GOT_NORMAL)
16303 /* Non-TLS symbols need one GOT slot. */
16304 s->size += 4;
16305 else
16306 {
99059e56
RM		 16307 if (tls_type & GOT_TLS_GDESC)
16308 {
0855e32b 16309 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16310 eh->tlsdesc_got
0855e32b
NS		 16311 = (htab->root.sgotplt->size
16312 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16313 htab->root.sgotplt->size += 8;
16314 h->got.offset = (bfd_vma) -2;
34e77a92 16315 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16316 reloc in the middle of .got.plt. */
99059e56
RM		 16317 htab->num_tls_desc++;
16318 }
0855e32b 16319
ba93b8ac 16320 if (tls_type & GOT_TLS_GD)
0855e32b 16321 {
5c5a4843
CL		 16322 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16323 consecutive GOT slots. If the symbol is both GD
16324 and GDESC, got.offset may have been
16325 overwritten. */
0855e32b
NS		 16326 h->got.offset = s->size;
16327 s->size += 8;
16328 }
16329
ba93b8ac 16330 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16331 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16332 slot. */
ba93b8ac
DJ		 16333 s->size += 4;
16334 }
16335
e5a52504 16336 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16337
16338 indx = 0;
0e1862bb
L		 16339 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16340 bfd_link_pic (info),
16341 h)
16342 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16343 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16344 indx = h->dynindx;
16345
16346 if (tls_type != GOT_NORMAL
9cb09e33 16347 && (bfd_link_dll (info) || indx != 0)
ba93b8ac
DJ		 16348 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16349 || h->root.type != bfd_link_hash_undefweak))
16350 {
16351 if (tls_type & GOT_TLS_IE)
47beaa6a 16352 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16353
16354 if (tls_type & GOT_TLS_GD)
47beaa6a 16355 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16356
b38cadfb 16357 if (tls_type & GOT_TLS_GDESC)
0855e32b 16358 {
47beaa6a 16359 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16360 /* GDESC needs a trampoline to jump to. */
16361 htab->tls_trampoline = -1;
16362 }
16363
16364 /* Only GD needs it. GDESC just emits one relocation per
16365 2 entries. */
b38cadfb 16366 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16367 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16368 }
e8b09b87
CL		 16369 else if (((indx != -1) || htab->fdpic_p)
16370 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16371 {
16372 if (htab->root.dynamic_sections_created)
16373 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16374 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16375 }
34e77a92
RS		 16376 else if (h->type == STT_GNU_IFUNC
16377 && eh->plt.noncall_refcount == 0)
16378 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16379 they all resolve dynamically instead. Reserve room for the
16380 GOT entry's R_ARM_IRELATIVE relocation. */
16381 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb 16382 else if (bfd_link_pic (info)
7f026732 16383 && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
b436d854 16384 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16385 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16386 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16387 /* Reserve room for rofixup for FDPIC executable. */
16388 /* TLS relocs do not need space since they are completely
16389 resolved. */
16390 htab->srofixup->size += 4;
e5a52504 16391 }
5e681ec4
PB		 16392 }
16393 else
16394 h->got.offset = (bfd_vma) -1;
16395
e8b09b87
CL		 16396 /* FDPIC support. */
16397 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16398 {
16399 /* Symbol musn't be exported. */
16400 if (h->dynindx != -1)
16401 abort();
16402
16403 /* We only allocate one function descriptor with its associated relocation. */
16404 if (eh->fdpic_cnts.funcdesc_offset == -1)
16405 {
16406 asection *s = htab->root.sgot;
16407
16408 eh->fdpic_cnts.funcdesc_offset = s->size;
16409 s->size += 8;
16410 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16411 if (bfd_link_pic(info))
16412 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16413 else
16414 htab->srofixup->size += 8;
16415 }
16416 }
16417
16418 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16419 {
16420 asection *s = htab->root.sgot;
16421
16422 if (htab->root.dynamic_sections_created && h->dynindx == -1
16423 && !h->forced_local)
16424 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16425 return FALSE;
16426
16427 if (h->dynindx == -1)
16428 {
16429 /* We only allocate one function descriptor with its associated relocation. q */
16430 if (eh->fdpic_cnts.funcdesc_offset == -1)
16431 {
16432
16433 eh->fdpic_cnts.funcdesc_offset = s->size;
16434 s->size += 8;
16435 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16436 if (bfd_link_pic(info))
16437 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16438 else
16439 htab->srofixup->size += 8;
16440 }
16441 }
16442
16443 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16444 R_ARM_RELATIVE/rofixup relocation on it. */
16445 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16446 s->size += 4;
16447 if (h->dynindx == -1 && !bfd_link_pic(info))
4b24dd1a 16448 htab->srofixup->size += 4;
e8b09b87 16449 else
4b24dd1a 16450 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16451 }
16452
16453 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16454 {
16455 if (htab->root.dynamic_sections_created && h->dynindx == -1
16456 && !h->forced_local)
16457 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16458 return FALSE;
16459
16460 if (h->dynindx == -1)
16461 {
16462 /* We only allocate one function descriptor with its associated relocation. */
16463 if (eh->fdpic_cnts.funcdesc_offset == -1)
16464 {
16465 asection *s = htab->root.sgot;
16466
16467 eh->fdpic_cnts.funcdesc_offset = s->size;
16468 s->size += 8;
16469 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16470 if (bfd_link_pic(info))
16471 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16472 else
16473 htab->srofixup->size += 8;
16474 }
16475 }
16476 if (h->dynindx == -1 && !bfd_link_pic(info))
16477 {
16478 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16479 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16480 }
16481 else
16482 {
16483 /* Will need one dynamic reloc per reference. will be either
16484 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16485 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16486 eh->fdpic_cnts.funcdesc_cnt);
16487 }
16488 }
16489
a4fd1a8e
PB		 16490 /* Allocate stubs for exported Thumb functions on v4t. */
16491 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16492 && h->def_regular
39d911fc 16493 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16494 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16495 {
16496 struct elf_link_hash_entry * th;
16497 struct bfd_link_hash_entry * bh;
16498 struct elf_link_hash_entry * myh;
16499 char name[1024];
16500 asection *s;
16501 bh = NULL;
16502 /* Create a new symbol to regist the real location of the function. */
16503 s = h->root.u.def.section;
906e58ca 16504 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16505 _bfd_generic_link_add_one_symbol (info, s->owner,
16506 name, BSF_GLOBAL, s,
16507 h->root.u.def.value,
16508 NULL, TRUE, FALSE, &bh);
16509
16510 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16511 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16512 myh->forced_local = 1;
39d911fc 16513 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16514 eh->export_glue = myh;
16515 th = record_arm_to_thumb_glue (info, h);
16516 /* Point the symbol at the stub. */
16517 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16518 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16519 h->root.u.def.section = th->root.u.def.section;
16520 h->root.u.def.value = th->root.u.def.value & ~1;
16521 }
16522
190eb1dd 16523 if (h->dyn_relocs == NULL)
5e681ec4
PB		 16524 return TRUE;
16525
16526 /* In the shared -Bsymbolic case, discard space allocated for
16527 dynamic pc-relative relocs against symbols which turn out to be
16528 defined in regular objects. For the normal shared case, discard
16529 space for pc-relative relocs that have become local due to symbol
16530 visibility changes. */
16531
e8b09b87 16532 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16533 {
469a3493
RM		 16534 /* Relocs that use pc_count are PC-relative forms, which will appear
16535 on something like ".long foo - ." or "movw REG, foo - .". We want
16536 calls to protected symbols to resolve directly to the function
16537 rather than going via the plt. If people want function pointer
16538 comparisons to work as expected then they should avoid writing
16539 assembly like ".long foo - .". */
ba93b8ac
DJ		 16540 if (SYMBOL_CALLS_LOCAL (info, h))
16541 {
0bdcacaf 16542 struct elf_dyn_relocs **pp;
ba93b8ac 16543
190eb1dd 16544 for (pp = &h->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16545 {
16546 p->count -= p->pc_count;
16547 p->pc_count = 0;
16548 if (p->count == 0)
16549 *pp = p->next;
16550 else
16551 pp = &p->next;
16552 }
16553 }
16554
90c14f0c 16555 if (htab->root.target_os == is_vxworks)
3348747a 16556 {
0bdcacaf 16557 struct elf_dyn_relocs **pp;
3348747a 16558
190eb1dd 16559 for (pp = &h->dyn_relocs; (p = *pp) != NULL; )
3348747a 16560 {
0bdcacaf 16561 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16562 *pp = p->next;
16563 else
16564 pp = &p->next;
16565 }
16566 }
16567
ba93b8ac 16568 /* Also discard relocs on undefined weak syms with non-default
99059e56 16569 visibility. */
190eb1dd 16570 if (h->dyn_relocs != NULL
5e681ec4 16571 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16572 {
95b03e4a
L		 16573 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16574 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
190eb1dd 16575 h->dyn_relocs = NULL;
22d606e9
AM		 16576
16577 /* Make sure undefined weak symbols are output as a dynamic
16578 symbol in PIEs. */
e8b09b87 16579 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16580 && !h->forced_local)
16581 {
16582 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16583 return FALSE;
16584 }
16585 }
16586
67687978
PB		 16587 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16588 && h->root.type == bfd_link_hash_new)
16589 {
16590 /* Output absolute symbols so that we can create relocations
16591 against them. For normal symbols we output a relocation
16592 against the section that contains them. */
16593 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16594 return FALSE;
16595 }
16596
5e681ec4
PB		 16597 }
16598 else
16599 {
16600 /* For the non-shared case, discard space for relocs against
16601 symbols which turn out to need copy relocs or are not
16602 dynamic. */
16603
f5385ebf
AM		 16604 if (!h->non_got_ref
16605 && ((h->def_dynamic
16606 && !h->def_regular)
5e681ec4
PB		 16607 || (htab->root.dynamic_sections_created
16608 && (h->root.type == bfd_link_hash_undefweak
16609 || h->root.type == bfd_link_hash_undefined))))
16610 {
16611 /* Make sure this symbol is output as a dynamic symbol.
16612 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16613 if (h->dynindx == -1 && !h->forced_local
16614 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16615 {
c152c796 16616 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16617 return FALSE;
16618 }
16619
16620 /* If that succeeded, we know we'll be keeping all the
16621 relocs. */
16622 if (h->dynindx != -1)
16623 goto keep;
16624 }
16625
190eb1dd 16626 h->dyn_relocs = NULL;
5e681ec4
PB		 16627
16628 keep: ;
16629 }
16630
16631 /* Finally, allocate space. */
190eb1dd 16632 for (p = h->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16633 {
0bdcacaf 16634 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16635
34e77a92
RS		 16636 if (h->type == STT_GNU_IFUNC
16637 && eh->plt.noncall_refcount == 0
16638 && SYMBOL_REFERENCES_LOCAL (info, h))
16639 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16640 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16641 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16642 else if (htab->fdpic_p && !bfd_link_pic(info))
16643 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16644 else
16645 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16646 }
16647
16648 return TRUE;
16649}
16650
d504ffc8
DJ		 16651void
16652bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16653 int byteswap_code)
16654{
16655 struct elf32_arm_link_hash_table *globals;
16656
16657 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16658 if (globals == NULL)
16659 return;
16660
d504ffc8
DJ		 16661 globals->byteswap_code = byteswap_code;
16662}
16663
252b5132
RH		 16664/* Set the sizes of the dynamic sections. */
16665
b34976b6 16666static bfd_boolean
57e8b36a
NC		 16667elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16668 struct bfd_link_info * info)
252b5132
RH		 16669{
16670 bfd * dynobj;
16671 asection * s;
b34976b6 16672 bfd_boolean relocs;
5e681ec4
PB		 16673 bfd *ibfd;
16674 struct elf32_arm_link_hash_table *htab;
252b5132 16675
5e681ec4 16676 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16677 if (htab == NULL)
16678 return FALSE;
16679
252b5132
RH		 16680 dynobj = elf_hash_table (info)->dynobj;
16681 BFD_ASSERT (dynobj != NULL);
39b41c9c 16682 check_use_blx (htab);
252b5132
RH		 16683
16684 if (elf_hash_table (info)->dynamic_sections_created)
16685 {
16686 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16687 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16688 {
3d4d4302 16689 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16690 BFD_ASSERT (s != NULL);
eea6121a 16691 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16692 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16693 }
16694 }
5e681ec4
PB		 16695
16696 /* Set up .got offsets for local syms, and space for local dynamic
16697 relocs. */
c72f2fb2 16698 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16699 {
5e681ec4
PB		 16700 bfd_signed_vma *local_got;
16701 bfd_signed_vma *end_local_got;
34e77a92 16702 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16703 char *local_tls_type;
0855e32b 16704 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16705 bfd_size_type locsymcount;
16706 Elf_Internal_Shdr *symtab_hdr;
16707 asection *srel;
34e77a92 16708 unsigned int symndx;
e8b09b87 16709 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16710
0ffa91dd 16711 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16712 continue;
16713
16714 for (s = ibfd->sections; s != NULL; s = s->next)
16715 {
0bdcacaf 16716 struct elf_dyn_relocs *p;
5e681ec4 16717
0bdcacaf 16718 for (p = (struct elf_dyn_relocs *)
99059e56 16719 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16720 {
0bdcacaf
RS		 16721 if (!bfd_is_abs_section (p->sec)
16722 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16723 {
16724 /* Input section has been discarded, either because
16725 it is a copy of a linkonce section or due to
16726 linker script /DISCARD/, so we'll be discarding
16727 the relocs too. */
16728 }
90c14f0c 16729 else if (htab->root.target_os == is_vxworks
0bdcacaf 16730 && strcmp (p->sec->output_section->name,
3348747a
NS		 16731 ".tls_vars") == 0)
16732 {
16733 /* Relocations in vxworks .tls_vars sections are
16734 handled specially by the loader. */
16735 }
5e681ec4
PB		 16736 else if (p->count != 0)
16737 {
0bdcacaf 16738 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16739 if (htab->fdpic_p && !bfd_link_pic(info))
16740 htab->srofixup->size += 4 * p->count;
16741 else
16742 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16743 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16744 info->flags |= DF_TEXTREL;
16745 }
16746 }
16747 }
16748
16749 local_got = elf_local_got_refcounts (ibfd);
16750 if (!local_got)
16751 continue;
16752
0ffa91dd 16753 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16754 locsymcount = symtab_hdr->sh_info;
16755 end_local_got = local_got + locsymcount;
34e77a92 16756 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16757 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16758 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16759 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16760 symndx = 0;
362d30a1
RS		 16761 s = htab->root.sgot;
16762 srel = htab->root.srelgot;
0855e32b 16763 for (; local_got < end_local_got;
34e77a92 16764 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16765 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16766 {
0855e32b 16767 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16768 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16769
16770 /* FDPIC support. */
16771 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16772 {
16773 if (local_fdpic_cnts->funcdesc_offset == -1)
16774 {
16775 local_fdpic_cnts->funcdesc_offset = s->size;
16776 s->size += 8;
16777
16778 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16779 if (bfd_link_pic(info))
16780 elf32_arm_allocate_dynrelocs (info, srel, 1);
16781 else
16782 htab->srofixup->size += 8;
16783 }
16784 }
16785
16786 if (local_fdpic_cnts->funcdesc_cnt > 0)
16787 {
16788 if (local_fdpic_cnts->funcdesc_offset == -1)
16789 {
16790 local_fdpic_cnts->funcdesc_offset = s->size;
16791 s->size += 8;
16792
16793 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16794 if (bfd_link_pic(info))
16795 elf32_arm_allocate_dynrelocs (info, srel, 1);
16796 else
16797 htab->srofixup->size += 8;
16798 }
16799
16800 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16801 if (bfd_link_pic(info))
16802 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16803 else
16804 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16805 }
16806
34e77a92
RS		 16807 if (local_iplt != NULL)
16808 {
16809 struct elf_dyn_relocs *p;
16810
16811 if (local_iplt->root.refcount > 0)
16812 {
16813 elf32_arm_allocate_plt_entry (info, TRUE,
16814 &local_iplt->root,
16815 &local_iplt->arm);
16816 if (local_iplt->arm.noncall_refcount == 0)
16817 /* All references to the PLT are calls, so all
16818 non-call references can resolve directly to the
16819 run-time target. This means that the .got entry
16820 would be the same as the .igot.plt entry, so there's
16821 no point creating both. */
16822 *local_got = 0;
16823 }
16824 else
16825 {
16826 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
16827 local_iplt->root.offset = (bfd_vma) -1;
16828 }
16829
16830 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
16831 {
16832 asection *psrel;
16833
16834 psrel = elf_section_data (p->sec)->sreloc;
16835 if (local_iplt->arm.noncall_refcount == 0)
16836 elf32_arm_allocate_irelocs (info, psrel, p->count);
16837 else
16838 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
16839 }
16840 }
5e681ec4
PB		 16841 if (*local_got > 0)
16842 {
34e77a92
RS		 16843 Elf_Internal_Sym *isym;
16844
eea6121a 16845 *local_got = s->size;
ba93b8ac
DJ		 16846 if (*local_tls_type & GOT_TLS_GD)
16847 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16848 s->size += 8;
0855e32b
NS		 16849 if (*local_tls_type & GOT_TLS_GDESC)
16850 {
16851 *local_tlsdesc_gotent = htab->root.sgotplt->size
16852 - elf32_arm_compute_jump_table_size (htab);
16853 htab->root.sgotplt->size += 8;
16854 *local_got = (bfd_vma) -2;
34e77a92 16855 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16856 reloc in the middle of .got.plt. */
99059e56 16857 htab->num_tls_desc++;
0855e32b 16858 }
ba93b8ac
DJ		 16859 if (*local_tls_type & GOT_TLS_IE)
16860 s->size += 4;
ba93b8ac 16861
0855e32b
NS		 16862 if (*local_tls_type & GOT_NORMAL)
16863 {
16864 /* If the symbol is both GD and GDESC, *local_got
16865 may have been overwritten. */
16866 *local_got = s->size;
16867 s->size += 4;
16868 }
16869
f1dfbfdb
L		 16870 isym = bfd_sym_from_r_symndx (&htab->root.sym_cache, ibfd,
16871 symndx);
34e77a92
RS		 16872 if (isym == NULL)
16873 return FALSE;
16874
16875 /* If all references to an STT_GNU_IFUNC PLT are calls,
16876 then all non-call references, including this GOT entry,
16877 resolve directly to the run-time target. */
16878 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
16879 && (local_iplt == NULL
16880 || local_iplt->arm.noncall_refcount == 0))
16881 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 16882 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 16883 {
e8b09b87 16884 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 16885 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 16886 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
16887 htab->srofixup->size += 4;
99059e56 16888
e8b09b87
CL		 16889 if ((bfd_link_pic (info) || htab->fdpic_p)
16890 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 16891 {
16892 elf32_arm_allocate_dynrelocs (info,
16893 htab->root.srelplt, 1);
16894 htab->tls_trampoline = -1;
16895 }
0855e32b 16896 }
5e681ec4
PB		 16897 }
16898 else
16899 *local_got = (bfd_vma) -1;
16900 }
252b5132
RH		 16901 }
16902
ba93b8ac
DJ		 16903 if (htab->tls_ldm_got.refcount > 0)
16904 {
16905 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 16906 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 16907 htab->tls_ldm_got.offset = htab->root.sgot->size;
16908 htab->root.sgot->size += 8;
0e1862bb 16909 if (bfd_link_pic (info))
47beaa6a 16910 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16911 }
16912 else
16913 htab->tls_ldm_got.offset = -1;
16914
e8b09b87
CL		 16915 /* At the very end of the .rofixup section is a pointer to the GOT,
16916 reserve space for it. */
16917 if (htab->fdpic_p && htab->srofixup != NULL)
16918 htab->srofixup->size += 4;
16919
5e681ec4
PB		 16920 /* Allocate global sym .plt and .got entries, and space for global
16921 sym dynamic relocs. */
47beaa6a 16922 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 16923
d504ffc8 16924 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 16925 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 16926 {
0ffa91dd 16927 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 16928 continue;
16929
c7b8f16e
JB		 16930 /* Initialise mapping tables for code/data. */
16931 bfd_elf32_arm_init_maps (ibfd);
906e58ca 16932
c7b8f16e 16933 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 16934 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
16935 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 16936 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 16937 }
d504ffc8 16938
3e6b1042
DJ		 16939 /* Allocate space for the glue sections now that we've sized them. */
16940 bfd_elf32_arm_allocate_interworking_sections (info);
16941
0855e32b
NS		 16942 /* For every jump slot reserved in the sgotplt, reloc_count is
16943 incremented. However, when we reserve space for TLS descriptors,
16944 it's not incremented, so in order to compute the space reserved
16945 for them, it suffices to multiply the reloc count by the jump
16946 slot size. */
16947 if (htab->root.srelplt)
16948 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
16949
16950 if (htab->tls_trampoline)
16951 {
16952 if (htab->root.splt->size == 0)
16953 htab->root.splt->size += htab->plt_header_size;
b38cadfb 16954
0855e32b
NS		 16955 htab->tls_trampoline = htab->root.splt->size;
16956 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16957
0855e32b 16958 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16959 PLT and GOT entries they require. */
9bcc30e4
L		 16960 if ((info->flags & DF_BIND_NOW))
16961 htab->root.tlsdesc_plt = 0;
16962 else
0855e32b 16963 {
9bcc30e4 16964 htab->root.tlsdesc_got = htab->root.sgot->size;
0855e32b
NS		 16965 htab->root.sgot->size += 4;
16966
9bcc30e4 16967 htab->root.tlsdesc_plt = htab->root.splt->size;
0855e32b
NS		 16968 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16969 }
16970 }
16971
252b5132
RH		 16972 /* The check_relocs and adjust_dynamic_symbol entry points have
16973 determined the sizes of the various dynamic sections. Allocate
16974 memory for them. */
b34976b6 16975 relocs = FALSE;
252b5132
RH		 16976 for (s = dynobj->sections; s != NULL; s = s->next)
16977 {
16978 const char * name;
252b5132
RH		 16979
16980 if ((s->flags & SEC_LINKER_CREATED) == 0)
16981 continue;
16982
16983 /* It's OK to base decisions on the section name, because none
16984 of the dynobj section names depend upon the input files. */
fd361982 16985 name = bfd_section_name (s);
252b5132 16986
34e77a92 16987 if (s == htab->root.splt)
252b5132 16988 {
c456f082 16989 /* Remember whether there is a PLT. */
3084d7a2 16990 ;
252b5132 16991 }
0112cd26 16992 else if (CONST_STRNEQ (name, ".rel"))
252b5132 16993 {
c456f082 16994 if (s->size != 0)
252b5132 16995 {
252b5132 16996 /* Remember whether there are any reloc sections other
00a97672 16997 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 16998 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 16999 relocs = TRUE;
252b5132
RH		 17000
17001 /* We use the reloc_count field as a counter if we need
17002 to copy relocs into the output file. */
17003 s->reloc_count = 0;
17004 }
17005 }
34e77a92
RS		 17006 else if (s != htab->root.sgot
17007 && s != htab->root.sgotplt
17008 && s != htab->root.iplt
17009 && s != htab->root.igotplt
5474d94f 17010 && s != htab->root.sdynbss
e8b09b87
CL		 17011 && s != htab->root.sdynrelro
17012 && s != htab->srofixup)
252b5132
RH		 17013 {
17014 /* It's not one of our sections, so don't allocate space. */
17015 continue;
17016 }
17017
c456f082 17018 if (s->size == 0)
252b5132 17019 {
c456f082 17020 /* If we don't need this section, strip it from the
00a97672
RS		 17021 output file. This is mostly to handle .rel(a).bss and
17022 .rel(a).plt. We must create both sections in
c456f082
AM		 17023 create_dynamic_sections, because they must be created
17024 before the linker maps input sections to output
17025 sections. The linker does that before
17026 adjust_dynamic_symbol is called, and it is that
17027 function which decides whether anything needs to go
17028 into these sections. */
8423293d 17029 s->flags |= SEC_EXCLUDE;
252b5132
RH		 17030 continue;
17031 }
17032
c456f082
AM		 17033 if ((s->flags & SEC_HAS_CONTENTS) == 0)
17034 continue;
17035
252b5132 17036 /* Allocate memory for the section contents. */
21d799b5 17037 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 17038 if (s->contents == NULL)
b34976b6 17039 return FALSE;
252b5132
RH		 17040 }
17041
3084d7a2
L		 17042 return _bfd_elf_maybe_vxworks_add_dynamic_tags (output_bfd, info,
17043 relocs);
252b5132
RH		 17044}
17045
0855e32b
NS		 17046/* Size sections even though they're not dynamic. We use it to setup
17047 _TLS_MODULE_BASE_, if needed. */
17048
17049static bfd_boolean
17050elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17051 struct bfd_link_info *info)
0855e32b
NS		 17052{
17053 asection *tls_sec;
cb10292c
CL		 17054 struct elf32_arm_link_hash_table *htab;
17055
17056 htab = elf32_arm_hash_table (info);
0855e32b 17057
0e1862bb 17058 if (bfd_link_relocatable (info))
0855e32b
NS		 17059 return TRUE;
17060
17061 tls_sec = elf_hash_table (info)->tls_sec;
17062
17063 if (tls_sec)
17064 {
17065 struct elf_link_hash_entry *tlsbase;
17066
17067 tlsbase = elf_link_hash_lookup
17068 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17069
17070 if (tlsbase)
99059e56
RM		 17071 {
17072 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17073 const struct elf_backend_data *bed
99059e56 17074 = get_elf_backend_data (output_bfd);
0855e32b 17075
99059e56 17076 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17077 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17078 tls_sec, 0, NULL, FALSE,
17079 bed->collect, &bh)))
17080 return FALSE;
b38cadfb 17081
99059e56
RM		 17082 tlsbase->type = STT_TLS;
17083 tlsbase = (struct elf_link_hash_entry *)bh;
17084 tlsbase->def_regular = 1;
17085 tlsbase->other = STV_HIDDEN;
17086 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17087 }
17088 }
cb10292c
CL		 17089
17090 if (htab->fdpic_p && !bfd_link_relocatable (info)
17091 && !bfd_elf_stack_segment_size (output_bfd, info,
17092 "__stacksize", DEFAULT_STACK_SIZE))
17093 return FALSE;
17094
0855e32b
NS		 17095 return TRUE;
17096}
17097
252b5132
RH		 17098/* Finish up dynamic symbol handling. We set the contents of various
17099 dynamic sections here. */
17100
b34976b6 17101static bfd_boolean
906e58ca
NC		 17102elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17103 struct bfd_link_info * info,
17104 struct elf_link_hash_entry * h,
17105 Elf_Internal_Sym * sym)
252b5132 17106{
e5a52504 17107 struct elf32_arm_link_hash_table *htab;
b7693d02 17108 struct elf32_arm_link_hash_entry *eh;
252b5132 17109
e5a52504 17110 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17111 if (htab == NULL)
17112 return FALSE;
17113
b7693d02 17114 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17115
17116 if (h->plt.offset != (bfd_vma) -1)
17117 {
34e77a92 17118 if (!eh->is_iplt)
e5a52504 17119 {
34e77a92 17120 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17121 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17122 h->dynindx, 0))
17123 return FALSE;
e5a52504 17124 }
57e8b36a 17125
f5385ebf 17126 if (!h->def_regular)
252b5132
RH		 17127 {
17128 /* Mark the symbol as undefined, rather than as defined in
3a635617 17129 the .plt section. */
252b5132 17130 sym->st_shndx = SHN_UNDEF;
3a635617 17131 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17132 Otherwise, the PLT entry would provide a definition for
17133 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17134 and so the symbol would never be NULL. Leave the value if
17135 there were any relocations where pointer equality matters
17136 (this is a clue for the dynamic linker, to make function
17137 pointer comparisons work between an application and shared
17138 library). */
97323ad1 17139 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17140 sym->st_value = 0;
252b5132 17141 }
34e77a92
RS		 17142 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17143 {
17144 /* At least one non-call relocation references this .iplt entry,
17145 so the .iplt entry is the function's canonical address. */
17146 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17147 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17148 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17149 (output_bfd, htab->root.iplt->output_section));
17150 sym->st_value = (h->plt.offset
17151 + htab->root.iplt->output_section->vma
17152 + htab->root.iplt->output_offset);
17153 }
252b5132
RH		 17154 }
17155
f5385ebf 17156 if (h->needs_copy)
252b5132
RH		 17157 {
17158 asection * s;
947216bf 17159 Elf_Internal_Rela rel;
252b5132
RH		 17160
17161 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17162 BFD_ASSERT (h->dynindx != -1
17163 && (h->root.type == bfd_link_hash_defined
17164 || h->root.type == bfd_link_hash_defweak));
17165
00a97672 17166 rel.r_addend = 0;
252b5132
RH		 17167 rel.r_offset = (h->root.u.def.value
17168 + h->root.u.def.section->output_section->vma
17169 + h->root.u.def.section->output_offset);
17170 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17171 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17172 s = htab->root.sreldynrelro;
17173 else
17174 s = htab->root.srelbss;
47beaa6a 17175 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17176 }
17177
00a97672 17178 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17179 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17180 it is relative to the ".got" section. */
9637f6ef 17181 if (h == htab->root.hdynamic
90c14f0c
L		 17182 || (!htab->fdpic_p
17183 && htab->root.target_os != is_vxworks
17184 && h == htab->root.hgot))
252b5132
RH		 17185 sym->st_shndx = SHN_ABS;
17186
b34976b6 17187 return TRUE;
252b5132
RH		 17188}
17189
0855e32b
NS		 17190static void
17191arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17192 void *contents,
17193 const unsigned long *template, unsigned count)
17194{
17195 unsigned ix;
b38cadfb 17196
0855e32b
NS		 17197 for (ix = 0; ix != count; ix++)
17198 {
17199 unsigned long insn = template[ix];
17200
17201 /* Emit mov pc,rx if bx is not permitted. */
17202 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17203 insn = (insn & 0xf000000f) | 0x01a0f000;
17204 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17205 }
17206}
17207
99059e56
RM		 17208/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17209 other variants, NaCl needs this entry in a static executable's
17210 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17211 zero. For .iplt really only the last bundle is useful, and .iplt
17212 could have a shorter first entry, with each individual PLT entry's
17213 relative branch calculated differently so it targets the last
17214 bundle instead of the instruction before it (labelled .Lplt_tail
17215 above). But it's simpler to keep the size and layout of PLT0
17216 consistent with the dynamic case, at the cost of some dead code at
17217 the start of .iplt and the one dead store to the stack at the start
17218 of .Lplt_tail. */
17219static void
17220arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17221 asection *plt, bfd_vma got_displacement)
17222{
17223 unsigned int i;
17224
17225 put_arm_insn (htab, output_bfd,
17226 elf32_arm_nacl_plt0_entry[0]
17227 | arm_movw_immediate (got_displacement),
17228 plt->contents + 0);
17229 put_arm_insn (htab, output_bfd,
17230 elf32_arm_nacl_plt0_entry[1]
17231 | arm_movt_immediate (got_displacement),
17232 plt->contents + 4);
17233
17234 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17235 put_arm_insn (htab, output_bfd,
17236 elf32_arm_nacl_plt0_entry[i],
17237 plt->contents + (i * 4));
17238}
17239
252b5132
RH		 17240/* Finish up the dynamic sections. */
17241
b34976b6 17242static bfd_boolean
57e8b36a 17243elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17244{
17245 bfd * dynobj;
17246 asection * sgot;
17247 asection * sdyn;
4dfe6ac6
NC		 17248 struct elf32_arm_link_hash_table *htab;
17249
17250 htab = elf32_arm_hash_table (info);
17251 if (htab == NULL)
17252 return FALSE;
252b5132
RH		 17253
17254 dynobj = elf_hash_table (info)->dynobj;
17255
362d30a1 17256 sgot = htab->root.sgotplt;
894891db
NC		 17257 /* A broken linker script might have discarded the dynamic sections.
17258 Catch this here so that we do not seg-fault later on. */
17259 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17260 return FALSE;
3d4d4302 17261 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17262
17263 if (elf_hash_table (info)->dynamic_sections_created)
17264 {
17265 asection *splt;
17266 Elf32_External_Dyn *dyncon, *dynconend;
17267
362d30a1 17268 splt = htab->root.splt;
24a1ba0f 17269 BFD_ASSERT (splt != NULL && sdyn != NULL);
90c14f0c 17270 BFD_ASSERT (htab->root.target_os == is_symbian || sgot != NULL);
252b5132
RH		 17271
17272 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17273 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17274
252b5132
RH		 17275 for (; dyncon < dynconend; dyncon++)
17276 {
17277 Elf_Internal_Dyn dyn;
17278 const char * name;
17279 asection * s;
17280
17281 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17282
17283 switch (dyn.d_tag)
17284 {
229fcec5
MM		 17285 unsigned int type;
17286
252b5132 17287 default:
90c14f0c 17288 if (htab->root.target_os == is_vxworks
7a2b07ff
NS		 17289 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17290 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17291 break;
17292
229fcec5
MM		 17293 case DT_HASH:
17294 name = ".hash";
17295 goto get_vma_if_bpabi;
17296 case DT_STRTAB:
17297 name = ".dynstr";
17298 goto get_vma_if_bpabi;
17299 case DT_SYMTAB:
17300 name = ".dynsym";
17301 goto get_vma_if_bpabi;
c0042f5d
MM		 17302 case DT_VERSYM:
17303 name = ".gnu.version";
17304 goto get_vma_if_bpabi;
17305 case DT_VERDEF:
17306 name = ".gnu.version_d";
17307 goto get_vma_if_bpabi;
17308 case DT_VERNEED:
17309 name = ".gnu.version_r";
17310 goto get_vma_if_bpabi;
17311
252b5132 17312 case DT_PLTGOT:
90c14f0c
L		 17313 name = (htab->root.target_os == is_symbian
17314 ? ".got" : ".got.plt");
252b5132
RH		 17315 goto get_vma;
17316 case DT_JMPREL:
00a97672 17317 name = RELOC_SECTION (htab, ".plt");
252b5132 17318 get_vma:
4ade44b7 17319 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17320 if (s == NULL)
17321 {
4eca0228 17322 _bfd_error_handler
4ade44b7 17323 (_("could not find section %s"), name);
05456594
NC		 17324 bfd_set_error (bfd_error_invalid_operation);
17325 return FALSE;
17326 }
90c14f0c 17327 if (htab->root.target_os != is_symbian)
4ade44b7 17328 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17329 else
17330 /* In the BPABI, tags in the PT_DYNAMIC section point
17331 at the file offset, not the memory address, for the
17332 convenience of the post linker. */
4ade44b7 17333 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17334 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17335 break;
17336
229fcec5 17337 get_vma_if_bpabi:
90c14f0c 17338 if (htab->root.target_os == is_symbian)
229fcec5
MM		 17339 goto get_vma;
17340 break;
17341
252b5132 17342 case DT_PLTRELSZ:
362d30a1 17343 s = htab->root.srelplt;
252b5132 17344 BFD_ASSERT (s != NULL);
eea6121a 17345 dyn.d_un.d_val = s->size;
252b5132
RH		 17346 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17347 break;
906e58ca 17348
252b5132 17349 case DT_RELSZ:
00a97672 17350 case DT_RELASZ:
229fcec5
MM		 17351 case DT_REL:
17352 case DT_RELA:
229fcec5
MM		 17353 /* In the BPABI, the DT_REL tag must point at the file
17354 offset, not the VMA, of the first relocation
17355 section. So, we use code similar to that in
17356 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17357 relocation section, since relocation sections are
17358 never allocated under the BPABI. PLT relocs are also
17359 included. */
90c14f0c 17360 if (htab->root.target_os == is_symbian)
229fcec5
MM		 17361 {
17362 unsigned int i;
17363 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17364 ? SHT_REL : SHT_RELA);
17365 dyn.d_un.d_val = 0;
17366 for (i = 1; i < elf_numsections (output_bfd); i++)
17367 {
906e58ca 17368 Elf_Internal_Shdr *hdr
229fcec5
MM		 17369 = elf_elfsections (output_bfd)[i];
17370 if (hdr->sh_type == type)
17371 {
906e58ca 17372 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17373 || dyn.d_tag == DT_RELASZ)
17374 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17375 else if ((ufile_ptr) hdr->sh_offset
17376 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17377 dyn.d_un.d_val = hdr->sh_offset;
17378 }
17379 }
17380 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17381 }
252b5132 17382 break;
88f7bcd5 17383
0855e32b 17384 case DT_TLSDESC_PLT:
99059e56 17385 s = htab->root.splt;
0855e32b 17386 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
9bcc30e4 17387 + htab->root.tlsdesc_plt);
0855e32b
NS		 17388 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17389 break;
17390
17391 case DT_TLSDESC_GOT:
99059e56 17392 s = htab->root.sgot;
0855e32b 17393 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
9bcc30e4 17394 + htab->root.tlsdesc_got);
0855e32b
NS		 17395 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17396 break;
17397
88f7bcd5
NC		 17398 /* Set the bottom bit of DT_INIT/FINI if the
17399 corresponding function is Thumb. */
17400 case DT_INIT:
17401 name = info->init_function;
17402 goto get_sym;
17403 case DT_FINI:
17404 name = info->fini_function;
17405 get_sym:
17406 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17407 then there is nothing to adjust. */
88f7bcd5
NC		 17408 if (dyn.d_un.d_val != 0)
17409 {
17410 struct elf_link_hash_entry * eh;
17411
17412 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17413 FALSE, FALSE, TRUE);
39d911fc
TP		 17414 if (eh != NULL
17415 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17416 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17417 {
17418 dyn.d_un.d_val |= 1;
b34976b6 17419 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17420 }
17421 }
17422 break;
252b5132
RH		 17423 }
17424 }
17425
24a1ba0f 17426 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17427 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17428 {
00a97672
RS		 17429 const bfd_vma *plt0_entry;
17430 bfd_vma got_address, plt_address, got_displacement;
17431
17432 /* Calculate the addresses of the GOT and PLT. */
17433 got_address = sgot->output_section->vma + sgot->output_offset;
17434 plt_address = splt->output_section->vma + splt->output_offset;
17435
90c14f0c 17436 if (htab->root.target_os == is_vxworks)
00a97672
RS		 17437 {
17438 /* The VxWorks GOT is relocated by the dynamic linker.
17439 Therefore, we must emit relocations rather than simply
17440 computing the values now. */
17441 Elf_Internal_Rela rel;
17442
17443 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17444 put_arm_insn (htab, output_bfd, plt0_entry[0],
17445 splt->contents + 0);
17446 put_arm_insn (htab, output_bfd, plt0_entry[1],
17447 splt->contents + 4);
17448 put_arm_insn (htab, output_bfd, plt0_entry[2],
17449 splt->contents + 8);
00a97672
RS		 17450 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17451
8029a119 17452 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17453 rel.r_offset = plt_address + 12;
17454 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17455 rel.r_addend = 0;
17456 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17457 htab->srelplt2->contents);
17458 }
90c14f0c 17459 else if (htab->root.target_os == is_nacl)
99059e56
RM		 17460 arm_nacl_put_plt0 (htab, output_bfd, splt,
17461 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17462 else if (using_thumb_only (htab))
17463 {
17464 got_displacement = got_address - (plt_address + 12);
17465
17466 plt0_entry = elf32_thumb2_plt0_entry;
17467 put_arm_insn (htab, output_bfd, plt0_entry[0],
17468 splt->contents + 0);
17469 put_arm_insn (htab, output_bfd, plt0_entry[1],
17470 splt->contents + 4);
17471 put_arm_insn (htab, output_bfd, plt0_entry[2],
17472 splt->contents + 8);
17473
17474 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17475 }
00a97672
RS		 17476 else
17477 {
17478 got_displacement = got_address - (plt_address + 16);
17479
17480 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17481 put_arm_insn (htab, output_bfd, plt0_entry[0],
17482 splt->contents + 0);
17483 put_arm_insn (htab, output_bfd, plt0_entry[1],
17484 splt->contents + 4);
17485 put_arm_insn (htab, output_bfd, plt0_entry[2],
17486 splt->contents + 8);
17487 put_arm_insn (htab, output_bfd, plt0_entry[3],
17488 splt->contents + 12);
5e681ec4 17489
5e681ec4 17490#ifdef FOUR_WORD_PLT
00a97672
RS		 17491 /* The displacement value goes in the otherwise-unused
17492 last word of the second entry. */
17493 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17494#else
00a97672 17495 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17496#endif
00a97672 17497 }
f7a74f8c 17498 }
252b5132
RH		 17499
17500 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17501 really seem like the right value. */
74541ad4
AM		 17502 if (splt->output_section->owner == output_bfd)
17503 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17504
9bcc30e4 17505 if (htab->root.tlsdesc_plt)
0855e32b
NS		 17506 {
17507 bfd_vma got_address
17508 = sgot->output_section->vma + sgot->output_offset;
17509 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17510 + htab->root.sgot->output_offset);
17511 bfd_vma plt_address
17512 = splt->output_section->vma + splt->output_offset;
17513
b38cadfb 17514 arm_put_trampoline (htab, output_bfd,
9bcc30e4 17515 splt->contents + htab->root.tlsdesc_plt,
0855e32b
NS		 17516 dl_tlsdesc_lazy_trampoline, 6);
17517
17518 bfd_put_32 (output_bfd,
9bcc30e4
L		 17519 gotplt_address + htab->root.tlsdesc_got
17520 - (plt_address + htab->root.tlsdesc_plt)
0855e32b 17521 - dl_tlsdesc_lazy_trampoline[6],
9bcc30e4 17522 splt->contents + htab->root.tlsdesc_plt + 24);
0855e32b 17523 bfd_put_32 (output_bfd,
9bcc30e4 17524 got_address - (plt_address + htab->root.tlsdesc_plt)
0855e32b 17525 - dl_tlsdesc_lazy_trampoline[7],
9bcc30e4 17526 splt->contents + htab->root.tlsdesc_plt + 24 + 4);
0855e32b
NS		 17527 }
17528
17529 if (htab->tls_trampoline)
17530 {
b38cadfb 17531 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17532 splt->contents + htab->tls_trampoline,
17533 tls_trampoline, 3);
17534#ifdef FOUR_WORD_PLT
17535 bfd_put_32 (output_bfd, 0x00000000,
17536 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17537#endif
0855e32b
NS		 17538 }
17539
90c14f0c 17540 if (htab->root.target_os == is_vxworks
0e1862bb
L		 17541 && !bfd_link_pic (info)
17542 && htab->root.splt->size > 0)
00a97672
RS		 17543 {
17544 /* Correct the .rel(a).plt.unloaded relocations. They will have
17545 incorrect symbol indexes. */
17546 int num_plts;
eed62c48 17547 unsigned char *p;
00a97672 17548
362d30a1 17549 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17550 / htab->plt_entry_size);
17551 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17552
17553 for (; num_plts; num_plts--)
17554 {
17555 Elf_Internal_Rela rel;
17556
17557 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17558 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17559 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17560 p += RELOC_SIZE (htab);
17561
17562 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17563 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17564 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17565 p += RELOC_SIZE (htab);
17566 }
17567 }
252b5132
RH		 17568 }
17569
90c14f0c
L		 17570 if (htab->root.target_os == is_nacl
17571 && htab->root.iplt != NULL
17572 && htab->root.iplt->size > 0)
99059e56
RM		 17573 /* NaCl uses a special first entry in .iplt too. */
17574 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17575
252b5132 17576 /* Fill in the first three entries in the global offset table. */
229fcec5 17577 if (sgot)
252b5132 17578 {
229fcec5
MM		 17579 if (sgot->size > 0)
17580 {
17581 if (sdyn == NULL)
17582 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17583 else
17584 bfd_put_32 (output_bfd,
17585 sdyn->output_section->vma + sdyn->output_offset,
17586 sgot->contents);
17587 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17588 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17589 }
252b5132 17590
229fcec5
MM		 17591 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17592 }
252b5132 17593
e8b09b87
CL		 17594 /* At the very end of the .rofixup section is a pointer to the GOT. */
17595 if (htab->fdpic_p && htab->srofixup != NULL)
17596 {
17597 struct elf_link_hash_entry *hgot = htab->root.hgot;
17598
17599 bfd_vma got_value = hgot->root.u.def.value
17600 + hgot->root.u.def.section->output_section->vma
17601 + hgot->root.u.def.section->output_offset;
17602
17603 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17604
17605 /* Make sure we allocated and generated the same number of fixups. */
17606 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17607 }
17608
b34976b6 17609 return TRUE;
252b5132
RH		 17610}
17611
ed7e9d0b
AM		 17612static bfd_boolean
17613elf32_arm_init_file_header (bfd *abfd, struct bfd_link_info *link_info)
ba96a88f 17614{
9b485d32 17615 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17616 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17617 struct elf_segment_map *m;
ba96a88f 17618
ed7e9d0b
AM		 17619 if (!_bfd_elf_init_file_header (abfd, link_info))
17620 return FALSE;
17621
ba96a88f
NC		 17622 i_ehdrp = elf_elfheader (abfd);
17623
94a3258f
PB		 17624 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17625 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
ba96a88f 17626 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17627
93204d3a
PB		 17628 if (link_info)
17629 {
17630 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17631 if (globals != NULL && globals->byteswap_code)
93204d3a 17632 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17633
17634 if (globals->fdpic_p)
17635 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17636 }
3bfcb652
NC		 17637
17638 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17639 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17640 {
17641 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17642 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17643 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17644 else
17645 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17646 }
ac4c9b04
MG		 17647
17648 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17649 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17650 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17651 {
17652 unsigned int j;
17653
17654 if (m->count == 0)
17655 continue;
17656 for (j = 0; j < m->count; j++)
17657 {
f0728ee3 17658 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17659 break;
17660 }
17661 if (j == m->count)
17662 {
17663 m->p_flags = PF_X;
17664 m->p_flags_valid = 1;
17665 }
17666 }
ed7e9d0b 17667 return TRUE;
ba96a88f
NC		 17668}
17669
99e4ae17 17670static enum elf_reloc_type_class
7e612e98
AM		 17671elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17672 const asection *rel_sec ATTRIBUTE_UNUSED,
17673 const Elf_Internal_Rela *rela)
99e4ae17 17674{
f51e552e 17675 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17676 {
17677 case R_ARM_RELATIVE:
17678 return reloc_class_relative;
17679 case R_ARM_JUMP_SLOT:
17680 return reloc_class_plt;
17681 case R_ARM_COPY:
17682 return reloc_class_copy;
109575d7
JW		 17683 case R_ARM_IRELATIVE:
17684 return reloc_class_ifunc;
99e4ae17
AJ		 17685 default:
17686 return reloc_class_normal;
17687 }
17688}
17689
e489d0ae 17690static void
cc364be6 17691arm_final_write_processing (bfd *abfd)
e16bb312 17692{
5a6c6817 17693 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17694}
17695
cc364be6
AM		 17696static bfd_boolean
17697elf32_arm_final_write_processing (bfd *abfd)
06f44071 17698{
cc364be6
AM		 17699 arm_final_write_processing (abfd);
17700 return _bfd_elf_final_write_processing (abfd);
06f44071
AM		 17701}
17702
40a18ebd
NC		 17703/* Return TRUE if this is an unwinding table entry. */
17704
17705static bfd_boolean
17706is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17707{
0112cd26
NC		 17708 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17709 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17710}
17711
17712
17713/* Set the type and flags for an ARM section. We do this by
17714 the section name, which is a hack, but ought to work. */
17715
17716static bfd_boolean
17717elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17718{
17719 const char * name;
17720
fd361982 17721 name = bfd_section_name (sec);
40a18ebd
NC		 17722
17723 if (is_arm_elf_unwind_section_name (abfd, name))
17724 {
17725 hdr->sh_type = SHT_ARM_EXIDX;
17726 hdr->sh_flags |= SHF_LINK_ORDER;
17727 }
ac4c9b04 17728
f0728ee3
AV		 17729 if (sec->flags & SEC_ELF_PURECODE)
17730 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17731
40a18ebd
NC		 17732 return TRUE;
17733}
17734
6dc132d9
L		 17735/* Handle an ARM specific section when reading an object file. This is
17736 called when bfd_section_from_shdr finds a section with an unknown
17737 type. */
40a18ebd
NC		 17738
17739static bfd_boolean
17740elf32_arm_section_from_shdr (bfd *abfd,
17741 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17742 const char *name,
17743 int shindex)
40a18ebd
NC		 17744{
17745 /* There ought to be a place to keep ELF backend specific flags, but
17746 at the moment there isn't one. We just keep track of the
17747 sections by their name, instead. Fortunately, the ABI gives
17748 names for all the ARM specific sections, so we will probably get
17749 away with this. */
17750 switch (hdr->sh_type)
17751 {
17752 case SHT_ARM_EXIDX:
0951f019
RE		 17753 case SHT_ARM_PREEMPTMAP:
17754 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17755 break;
17756
17757 default:
17758 return FALSE;
17759 }
17760
6dc132d9 17761 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17762 return FALSE;
17763
17764 return TRUE;
17765}
e489d0ae 17766
44444f50
NC		 17767static _arm_elf_section_data *
17768get_arm_elf_section_data (asection * sec)
17769{
47b2e99c
JZ		 17770 if (sec && sec->owner && is_arm_elf (sec->owner))
17771 return elf32_arm_section_data (sec);
44444f50
NC		 17772 else
17773 return NULL;
8e3de13a
NC		 17774}
17775
4e617b1e
PB		 17776typedef struct
17777{
57402f1e 17778 void *flaginfo;
4e617b1e 17779 struct bfd_link_info *info;
91a5743d
PB		 17780 asection *sec;
17781 int sec_shndx;
6e0b88f1
AM		 17782 int (*func) (void *, const char *, Elf_Internal_Sym *,
17783 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 17784} output_arch_syminfo;
17785
17786enum map_symbol_type
17787{
17788 ARM_MAP_ARM,
17789 ARM_MAP_THUMB,
17790 ARM_MAP_DATA
17791};
17792
17793
7413f23f 17794/* Output a single mapping symbol. */
4e617b1e
PB		 17795
17796static bfd_boolean
7413f23f
DJ		 17797elf32_arm_output_map_sym (output_arch_syminfo *osi,
17798 enum map_symbol_type type,
17799 bfd_vma offset)
4e617b1e
PB		 17800{
17801 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 17802 Elf_Internal_Sym sym;
17803
91a5743d
PB		 17804 sym.st_value = osi->sec->output_section->vma
17805 + osi->sec->output_offset
17806 + offset;
4e617b1e
PB		 17807 sym.st_size = 0;
17808 sym.st_other = 0;
17809 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 17810 sym.st_shndx = osi->sec_shndx;
35fc36a8 17811 sym.st_target_internal = 0;
fe33d2fa 17812 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 17813 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 17814}
17815
34e77a92
RS		 17816/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17817 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 17818
17819static bfd_boolean
34e77a92
RS		 17820elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
17821 bfd_boolean is_iplt_entry_p,
17822 union gotplt_union *root_plt,
17823 struct arm_plt_info *arm_plt)
4e617b1e 17824{
4e617b1e 17825 struct elf32_arm_link_hash_table *htab;
34e77a92 17826 bfd_vma addr, plt_header_size;
4e617b1e 17827
34e77a92 17828 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 17829 return TRUE;
17830
4dfe6ac6
NC		 17831 htab = elf32_arm_hash_table (osi->info);
17832 if (htab == NULL)
17833 return FALSE;
17834
34e77a92
RS		 17835 if (is_iplt_entry_p)
17836 {
17837 osi->sec = htab->root.iplt;
17838 plt_header_size = 0;
17839 }
17840 else
17841 {
17842 osi->sec = htab->root.splt;
17843 plt_header_size = htab->plt_header_size;
17844 }
17845 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
17846 (osi->info->output_bfd, osi->sec->output_section));
17847
17848 addr = root_plt->offset & -2;
90c14f0c 17849 if (htab->root.target_os == is_symbian)
4e617b1e 17850 {
7413f23f 17851 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17852 return FALSE;
7413f23f 17853 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 17854 return FALSE;
17855 }
90c14f0c 17856 else if (htab->root.target_os == is_vxworks)
4e617b1e 17857 {
7413f23f 17858 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17859 return FALSE;
7413f23f 17860 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 17861 return FALSE;
7413f23f 17862 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 17863 return FALSE;
7413f23f 17864 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 17865 return FALSE;
17866 }
90c14f0c 17867 else if (htab->root.target_os == is_nacl)
b38cadfb
NC		 17868 {
17869 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
17870 return FALSE;
17871 }
7801f98f
CL		 17872 else if (htab->fdpic_p)
17873 {
59029f57
CL		 17874 enum map_symbol_type type = using_thumb_only(htab)
17875 ? ARM_MAP_THUMB
17876 : ARM_MAP_ARM;
17877
7801f98f 17878 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
4b24dd1a
AM		 17879 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
17880 return FALSE;
59029f57 17881 if (!elf32_arm_output_map_sym (osi, type, addr))
4b24dd1a 17882 return FALSE;
7801f98f 17883 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
4b24dd1a 17884 return FALSE;
7801f98f 17885 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
4b24dd1a
AM		 17886 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
17887 return FALSE;
7801f98f 17888 }
eed94f8f
NC		 17889 else if (using_thumb_only (htab))
17890 {
17891 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
17892 return FALSE;
6a631e86 17893 }
4e617b1e
PB		 17894 else
17895 {
34e77a92 17896 bfd_boolean thumb_stub_p;
bd97cb95 17897
34e77a92
RS		 17898 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
17899 if (thumb_stub_p)
4e617b1e 17900 {
7413f23f 17901 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 17902 return FALSE;
17903 }
17904#ifdef FOUR_WORD_PLT
7413f23f 17905 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17906 return FALSE;
7413f23f 17907 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 17908 return FALSE;
17909#else
906e58ca 17910 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 17911 so only need to output a mapping symbol for the first PLT entry and
17912 entries with thumb thunks. */
34e77a92 17913 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 17914 {
7413f23f 17915 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 17916 return FALSE;
17917 }
17918#endif
17919 }
17920
17921 return TRUE;
17922}
17923
34e77a92
RS		 17924/* Output mapping symbols for PLT entries associated with H. */
17925
17926static bfd_boolean
17927elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
17928{
17929 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
17930 struct elf32_arm_link_hash_entry *eh;
17931
17932 if (h->root.type == bfd_link_hash_indirect)
17933 return TRUE;
17934
17935 if (h->root.type == bfd_link_hash_warning)
17936 /* When warning symbols are created, they **replace** the "real"
17937 entry in the hash table, thus we never get to see the real
17938 symbol in a hash traversal. So look at it now. */
17939 h = (struct elf_link_hash_entry *) h->root.u.i.link;
17940
17941 eh = (struct elf32_arm_link_hash_entry *) h;
17942 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
17943 &h->plt, &eh->plt);
17944}
17945
4f4faa4d
TP		 17946/* Bind a veneered symbol to its veneer identified by its hash entry
17947 STUB_ENTRY. The veneered location thus loose its symbol. */
17948
17949static void
17950arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17951{
17952 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17953
17954 BFD_ASSERT (hash);
17955 hash->root.root.u.def.section = stub_entry->stub_sec;
17956 hash->root.root.u.def.value = stub_entry->stub_offset;
17957 hash->root.size = stub_entry->stub_size;
17958}
17959
7413f23f
DJ		 17960/* Output a single local symbol for a generated stub. */
17961
17962static bfd_boolean
17963elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
17964 bfd_vma offset, bfd_vma size)
17965{
7413f23f
DJ		 17966 Elf_Internal_Sym sym;
17967
7413f23f
DJ		 17968 sym.st_value = osi->sec->output_section->vma
17969 + osi->sec->output_offset
17970 + offset;
17971 sym.st_size = size;
17972 sym.st_other = 0;
17973 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
17974 sym.st_shndx = osi->sec_shndx;
35fc36a8 17975 sym.st_target_internal = 0;
57402f1e 17976 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 17977}
4e617b1e 17978
da5938a2 17979static bfd_boolean
8029a119
NC		 17980arm_map_one_stub (struct bfd_hash_entry * gen_entry,
17981 void * in_arg)
da5938a2
NC		 17982{
17983 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 17984 asection *stub_sec;
17985 bfd_vma addr;
7413f23f 17986 char *stub_name;
9a008db3 17987 output_arch_syminfo *osi;
d3ce72d0 17988 const insn_sequence *template_sequence;
461a49ca
DJ		 17989 enum stub_insn_type prev_type;
17990 int size;
17991 int i;
17992 enum map_symbol_type sym_type;
da5938a2
NC		 17993
17994 /* Massage our args to the form they really have. */
17995 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 17996 osi = (output_arch_syminfo *) in_arg;
da5938a2 17997
da5938a2
NC		 17998 stub_sec = stub_entry->stub_sec;
17999
18000 /* Ensure this stub is attached to the current section being
7413f23f 18001 processed. */
da5938a2
NC		 18002 if (stub_sec != osi->sec)
18003 return TRUE;
18004
7413f23f 18005 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 18006 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 18007
18008 if (arm_stub_sym_claimed (stub_entry->stub_type))
18009 arm_stub_claim_sym (stub_entry);
18010 else
7413f23f 18011 {
4f4faa4d
TP		 18012 stub_name = stub_entry->output_name;
18013 switch (template_sequence[0].type)
18014 {
18015 case ARM_TYPE:
18016 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
18017 stub_entry->stub_size))
18018 return FALSE;
18019 break;
18020 case THUMB16_TYPE:
18021 case THUMB32_TYPE:
18022 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
18023 stub_entry->stub_size))
18024 return FALSE;
18025 break;
18026 default:
18027 BFD_FAIL ();
18028 return 0;
18029 }
7413f23f 18030 }
da5938a2 18031
461a49ca
DJ		 18032 prev_type = DATA_TYPE;
18033 size = 0;
18034 for (i = 0; i < stub_entry->stub_template_size; i++)
18035 {
d3ce72d0 18036 switch (template_sequence[i].type)
461a49ca
DJ		 18037 {
18038 case ARM_TYPE:
18039 sym_type = ARM_MAP_ARM;
18040 break;
18041
18042 case THUMB16_TYPE:
48229727 18043 case THUMB32_TYPE:
461a49ca
DJ		 18044 sym_type = ARM_MAP_THUMB;
18045 break;
18046
18047 case DATA_TYPE:
18048 sym_type = ARM_MAP_DATA;
18049 break;
18050
18051 default:
18052 BFD_FAIL ();
4e31c731 18053 return FALSE;
461a49ca
DJ		 18054 }
18055
d3ce72d0 18056 if (template_sequence[i].type != prev_type)
461a49ca 18057 {
d3ce72d0 18058 prev_type = template_sequence[i].type;
461a49ca
DJ		 18059 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18060 return FALSE;
18061 }
18062
d3ce72d0 18063 switch (template_sequence[i].type)
461a49ca
DJ		 18064 {
18065 case ARM_TYPE:
48229727 18066 case THUMB32_TYPE:
461a49ca
DJ		 18067 size += 4;
18068 break;
18069
18070 case THUMB16_TYPE:
18071 size += 2;
18072 break;
18073
18074 case DATA_TYPE:
18075 size += 4;
18076 break;
18077
18078 default:
18079 BFD_FAIL ();
4e31c731 18080 return FALSE;
461a49ca
DJ		 18081 }
18082 }
18083
da5938a2
NC		 18084 return TRUE;
18085}
18086
33811162
DG		 18087/* Output mapping symbols for linker generated sections,
18088 and for those data-only sections that do not have a
18089 $d. */
4e617b1e
PB		 18090
18091static bfd_boolean
18092elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18093 struct bfd_link_info *info,
57402f1e 18094 void *flaginfo,
6e0b88f1
AM		 18095 int (*func) (void *, const char *,
18096 Elf_Internal_Sym *,
18097 asection *,
18098 struct elf_link_hash_entry *))
4e617b1e
PB		 18099{
18100 output_arch_syminfo osi;
18101 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18102 bfd_vma offset;
18103 bfd_size_type size;
33811162 18104 bfd *input_bfd;
4e617b1e
PB		 18105
18106 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18107 if (htab == NULL)
18108 return FALSE;
18109
906e58ca 18110 check_use_blx (htab);
91a5743d 18111
57402f1e 18112 osi.flaginfo = flaginfo;
4e617b1e
PB		 18113 osi.info = info;
18114 osi.func = func;
906e58ca 18115
33811162
DG		 18116 /* Add a $d mapping symbol to data-only sections that
18117 don't have any mapping symbol. This may result in (harmless) redundant
18118 mapping symbols. */
18119 for (input_bfd = info->input_bfds;
18120 input_bfd != NULL;
c72f2fb2 18121 input_bfd = input_bfd->link.next)
33811162
DG		 18122 {
18123 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18124 for (osi.sec = input_bfd->sections;
18125 osi.sec != NULL;
18126 osi.sec = osi.sec->next)
18127 {
18128 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18129 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18130 != 0)
33811162
DG		 18131 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18132 == SEC_HAS_CONTENTS
18133 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18134 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18135 && osi.sec->size > 0
18136 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18137 {
18138 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18139 (output_bfd, osi.sec->output_section);
18140 if (osi.sec_shndx != (int)SHN_BAD)
18141 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18142 }
18143 }
18144 }
18145
91a5743d
PB		 18146 /* ARM->Thumb glue. */
18147 if (htab->arm_glue_size > 0)
18148 {
3d4d4302
AM		 18149 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18150 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18151
18152 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18153 (output_bfd, osi.sec->output_section);
0e1862bb 18154 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18155 || htab->pic_veneer)
18156 size = ARM2THUMB_PIC_GLUE_SIZE;
18157 else if (htab->use_blx)
18158 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18159 else
18160 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18161
91a5743d
PB		 18162 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18163 {
7413f23f
DJ		 18164 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18165 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18166 }
18167 }
18168
18169 /* Thumb->ARM glue. */
18170 if (htab->thumb_glue_size > 0)
18171 {
3d4d4302
AM		 18172 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18173 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18174
18175 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18176 (output_bfd, osi.sec->output_section);
18177 size = THUMB2ARM_GLUE_SIZE;
18178
18179 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18180 {
7413f23f
DJ		 18181 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18182 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18183 }
18184 }
18185
845b51d6
PB		 18186 /* ARMv4 BX veneers. */
18187 if (htab->bx_glue_size > 0)
18188 {
3d4d4302
AM		 18189 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18190 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18191
18192 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18193 (output_bfd, osi.sec->output_section);
18194
7413f23f 18195 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18196 }
18197
8029a119
NC		 18198 /* Long calls stubs. */
18199 if (htab->stub_bfd && htab->stub_bfd->sections)
18200 {
da5938a2 18201 asection* stub_sec;
8029a119 18202
da5938a2
NC		 18203 for (stub_sec = htab->stub_bfd->sections;
18204 stub_sec != NULL;
8029a119
NC		 18205 stub_sec = stub_sec->next)
18206 {
18207 /* Ignore non-stub sections. */
18208 if (!strstr (stub_sec->name, STUB_SUFFIX))
18209 continue;
da5938a2 18210
8029a119 18211 osi.sec = stub_sec;
da5938a2 18212
8029a119
NC		 18213 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18214 (output_bfd, osi.sec->output_section);
da5938a2 18215
8029a119
NC		 18216 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18217 }
18218 }
da5938a2 18219
91a5743d 18220 /* Finally, output mapping symbols for the PLT. */
34e77a92 18221 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18222 {
34e77a92
RS		 18223 osi.sec = htab->root.splt;
18224 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18225 (output_bfd, osi.sec->output_section));
18226
18227 /* Output mapping symbols for the plt header. SymbianOS does not have a
18228 plt header. */
90c14f0c 18229 if (htab->root.target_os == is_vxworks)
34e77a92
RS		 18230 {
18231 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18232 if (!bfd_link_pic (info))
34e77a92
RS		 18233 {
18234 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18235 return FALSE;
18236 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18237 return FALSE;
18238 }
18239 }
90c14f0c 18240 else if (htab->root.target_os == is_nacl)
b38cadfb
NC		 18241 {
18242 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18243 return FALSE;
18244 }
59029f57 18245 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18246 {
18247 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18248 return FALSE;
18249 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18250 return FALSE;
18251 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18252 return FALSE;
18253 }
90c14f0c 18254 else if (htab->root.target_os != is_symbian && !htab->fdpic_p)
4e617b1e 18255 {
7413f23f 18256 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18257 return FALSE;
34e77a92
RS		 18258#ifndef FOUR_WORD_PLT
18259 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18260 return FALSE;
34e77a92 18261#endif
4e617b1e
PB		 18262 }
18263 }
90c14f0c
L		 18264 if (htab->root.target_os == is_nacl
18265 && htab->root.iplt
18266 && htab->root.iplt->size > 0)
99059e56
RM		 18267 {
18268 /* NaCl uses a special first entry in .iplt too. */
18269 osi.sec = htab->root.iplt;
18270 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18271 (output_bfd, osi.sec->output_section));
18272 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18273 return FALSE;
18274 }
34e77a92
RS		 18275 if ((htab->root.splt && htab->root.splt->size > 0)
18276 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18277 {
34e77a92
RS		 18278 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18279 for (input_bfd = info->input_bfds;
18280 input_bfd != NULL;
c72f2fb2 18281 input_bfd = input_bfd->link.next)
34e77a92
RS		 18282 {
18283 struct arm_local_iplt_info **local_iplt;
18284 unsigned int i, num_syms;
4e617b1e 18285
34e77a92
RS		 18286 local_iplt = elf32_arm_local_iplt (input_bfd);
18287 if (local_iplt != NULL)
18288 {
18289 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18290 for (i = 0; i < num_syms; i++)
18291 if (local_iplt[i] != NULL
18292 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18293 &local_iplt[i]->root,
18294 &local_iplt[i]->arm))
18295 return FALSE;
18296 }
18297 }
18298 }
9bcc30e4 18299 if (htab->root.tlsdesc_plt != 0)
0855e32b
NS		 18300 {
18301 /* Mapping symbols for the lazy tls trampoline. */
9bcc30e4
L		 18302 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM,
18303 htab->root.tlsdesc_plt))
0855e32b 18304 return FALSE;
b38cadfb 18305
0855e32b 18306 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
9bcc30e4 18307 htab->root.tlsdesc_plt + 24))
0855e32b
NS		 18308 return FALSE;
18309 }
18310 if (htab->tls_trampoline != 0)
18311 {
18312 /* Mapping symbols for the tls trampoline. */
18313 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18314 return FALSE;
18315#ifdef FOUR_WORD_PLT
18316 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18317 htab->tls_trampoline + 12))
18318 return FALSE;
b38cadfb 18319#endif
0855e32b 18320 }
b38cadfb 18321
4e617b1e
PB		 18322 return TRUE;
18323}
18324
54ddd295
TP		 18325/* Filter normal symbols of CMSE entry functions of ABFD to include in
18326 the import library. All SYMCOUNT symbols of ABFD can be examined
18327 from their pointers in SYMS. Pointers of symbols to keep should be
18328 stored continuously at the beginning of that array.
18329
18330 Returns the number of symbols to keep. */
18331
18332static unsigned int
18333elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18334 struct bfd_link_info *info,
18335 asymbol **syms, long symcount)
18336{
18337 size_t maxnamelen;
18338 char *cmse_name;
18339 long src_count, dst_count = 0;
18340 struct elf32_arm_link_hash_table *htab;
18341
18342 htab = elf32_arm_hash_table (info);
18343 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18344 symcount = 0;
18345
18346 maxnamelen = 128;
18347 cmse_name = (char *) bfd_malloc (maxnamelen);
7a0fb7be
NC		 18348 BFD_ASSERT (cmse_name);
18349
54ddd295
TP		 18350 for (src_count = 0; src_count < symcount; src_count++)
18351 {
18352 struct elf32_arm_link_hash_entry *cmse_hash;
18353 asymbol *sym;
18354 flagword flags;
18355 char *name;
18356 size_t namelen;
18357
18358 sym = syms[src_count];
18359 flags = sym->flags;
18360 name = (char *) bfd_asymbol_name (sym);
18361
18362 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18363 continue;
18364 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18365 continue;
18366
18367 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18368 if (namelen > maxnamelen)
18369 {
18370 cmse_name = (char *)
18371 bfd_realloc (cmse_name, namelen);
18372 maxnamelen = namelen;
18373 }
18374 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18375 cmse_hash = (struct elf32_arm_link_hash_entry *)
18376 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18377
18378 if (!cmse_hash
18379 || (cmse_hash->root.root.type != bfd_link_hash_defined
18380 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18381 || cmse_hash->root.type != STT_FUNC)
18382 continue;
18383
54ddd295
TP		 18384 syms[dst_count++] = sym;
18385 }
18386 free (cmse_name);
18387
18388 syms[dst_count] = NULL;
18389
18390 return dst_count;
18391}
18392
18393/* Filter symbols of ABFD to include in the import library. All
18394 SYMCOUNT symbols of ABFD can be examined from their pointers in
18395 SYMS. Pointers of symbols to keep should be stored continuously at
18396 the beginning of that array.
18397
18398 Returns the number of symbols to keep. */
18399
18400static unsigned int
18401elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18402 struct bfd_link_info *info,
18403 asymbol **syms, long symcount)
18404{
18405 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18406
046734ff
TP		 18407 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18408 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18409 library to be a relocatable object file. */
18410 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18411 if (globals->cmse_implib)
18412 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18413 else
18414 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18415}
18416
e489d0ae
PB		 18417/* Allocate target specific section data. */
18418
18419static bfd_boolean
18420elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18421{
f592407e
AM		 18422 if (!sec->used_by_bfd)
18423 {
18424 _arm_elf_section_data *sdata;
986f0783 18425 size_t amt = sizeof (*sdata);
e489d0ae 18426
21d799b5 18427 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18428 if (sdata == NULL)
18429 return FALSE;
18430 sec->used_by_bfd = sdata;
18431 }
e489d0ae
PB		 18432
18433 return _bfd_elf_new_section_hook (abfd, sec);
18434}
18435
18436
18437/* Used to order a list of mapping symbols by address. */
18438
18439static int
18440elf32_arm_compare_mapping (const void * a, const void * b)
18441{
7f6a71ff
JM		 18442 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18443 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18444
18445 if (amap->vma > bmap->vma)
18446 return 1;
18447 else if (amap->vma < bmap->vma)
18448 return -1;
18449 else if (amap->type > bmap->type)
18450 /* Ensure results do not depend on the host qsort for objects with
18451 multiple mapping symbols at the same address by sorting on type
18452 after vma. */
18453 return 1;
18454 else if (amap->type < bmap->type)
18455 return -1;
18456 else
18457 return 0;
e489d0ae
PB		 18458}
18459
2468f9c9
PB		 18460/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18461
18462static unsigned long
18463offset_prel31 (unsigned long addr, bfd_vma offset)
18464{
18465 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18466}
18467
18468/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18469 relocations. */
18470
18471static void
18472copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18473{
18474 unsigned long first_word = bfd_get_32 (output_bfd, from);
18475 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18476
2468f9c9
PB		 18477 /* High bit of first word is supposed to be zero. */
18478 if ((first_word & 0x80000000ul) == 0)
18479 first_word = offset_prel31 (first_word, offset);
b38cadfb 18480
2468f9c9
PB		 18481 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18482 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18483 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18484 second_word = offset_prel31 (second_word, offset);
b38cadfb 18485
2468f9c9
PB		 18486 bfd_put_32 (output_bfd, first_word, to);
18487 bfd_put_32 (output_bfd, second_word, to + 4);
18488}
e489d0ae 18489
48229727
JB		 18490/* Data for make_branch_to_a8_stub(). */
18491
b38cadfb
NC		 18492struct a8_branch_to_stub_data
18493{
48229727
JB		 18494 asection *writing_section;
18495 bfd_byte *contents;
18496};
18497
18498
18499/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18500 places for a particular section. */
18501
18502static bfd_boolean
18503make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18504 void *in_arg)
48229727
JB		 18505{
18506 struct elf32_arm_stub_hash_entry *stub_entry;
18507 struct a8_branch_to_stub_data *data;
18508 bfd_byte *contents;
18509 unsigned long branch_insn;
18510 bfd_vma veneered_insn_loc, veneer_entry_loc;
18511 bfd_signed_vma branch_offset;
18512 bfd *abfd;
8d9d9490 18513 unsigned int loc;
48229727
JB		 18514
18515 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18516 data = (struct a8_branch_to_stub_data *) in_arg;
18517
18518 if (stub_entry->target_section != data->writing_section
4563a860 18519 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18520 return TRUE;
18521
18522 contents = data->contents;
18523
8d9d9490
TP		 18524 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18525 generated when both source and target are in the same section. */
48229727
JB		 18526 veneered_insn_loc = stub_entry->target_section->output_section->vma
18527 + stub_entry->target_section->output_offset
8d9d9490 18528 + stub_entry->source_value;
48229727
JB		 18529
18530 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18531 + stub_entry->stub_sec->output_offset
18532 + stub_entry->stub_offset;
18533
18534 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18535 veneered_insn_loc &= ~3u;
18536
18537 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18538
18539 abfd = stub_entry->target_section->owner;
8d9d9490 18540 loc = stub_entry->source_value;
48229727
JB		 18541
18542 /* We attempt to avoid this condition by setting stubs_always_after_branch
18543 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18544 This check is just to be on the safe side... */
18545 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18546 {
871b3ab2 18547 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18548 "allocated in unsafe location"), abfd);
48229727
JB		 18549 return FALSE;
18550 }
18551
18552 switch (stub_entry->stub_type)
18553 {
18554 case arm_stub_a8_veneer_b:
18555 case arm_stub_a8_veneer_b_cond:
18556 branch_insn = 0xf0009000;
18557 goto jump24;
18558
18559 case arm_stub_a8_veneer_blx:
18560 branch_insn = 0xf000e800;
18561 goto jump24;
18562
18563 case arm_stub_a8_veneer_bl:
18564 {
18565 unsigned int i1, j1, i2, j2, s;
18566
18567 branch_insn = 0xf000d000;
18568
18569 jump24:
18570 if (branch_offset < -16777216 || branch_offset > 16777214)
18571 {
18572 /* There's not much we can do apart from complain if this
18573 happens. */
871b3ab2 18574 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18575 "of range (input file too large)"), abfd);
48229727
JB		 18576 return FALSE;
18577 }
18578
18579 /* i1 = not(j1 eor s), so:
18580 not i1 = j1 eor s
18581 j1 = (not i1) eor s. */
18582
18583 branch_insn |= (branch_offset >> 1) & 0x7ff;
18584 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18585 i2 = (branch_offset >> 22) & 1;
18586 i1 = (branch_offset >> 23) & 1;
18587 s = (branch_offset >> 24) & 1;
18588 j1 = (!i1) ^ s;
18589 j2 = (!i2) ^ s;
18590 branch_insn |= j2 << 11;
18591 branch_insn |= j1 << 13;
18592 branch_insn |= s << 26;
18593 }
18594 break;
18595
18596 default:
18597 BFD_FAIL ();
18598 return FALSE;
18599 }
18600
8d9d9490
TP		 18601 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18602 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18603
18604 return TRUE;
18605}
18606
a504d23a
LA		 18607/* Beginning of stm32l4xx work-around. */
18608
18609/* Functions encoding instructions necessary for the emission of the
18610 fix-stm32l4xx-629360.
18611 Encoding is extracted from the
18612 ARM (C) Architecture Reference Manual
18613 ARMv7-A and ARMv7-R edition
18614 ARM DDI 0406C.b (ID072512). */
18615
18616static inline bfd_vma
82188b29 18617create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18618{
18619 /* A8.8.18 B (A8-334)
18620 B target_address (Encoding T4). */
18621 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18622 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18623 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18624
a504d23a
LA		 18625 int s = ((branch_offset & 0x1000000) >> 24);
18626 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18627 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18628
18629 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18630 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18631
18632 bfd_vma patched_inst = 0xf0009000
18633 | s << 26 /* S. */
18634 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18635 | j1 << 13 /* J1. */
18636 | j2 << 11 /* J2. */
18637 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18638
18639 return patched_inst;
18640}
18641
18642static inline bfd_vma
18643create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18644{
18645 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18646 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18647 bfd_vma patched_inst = 0xe8900000
18648 | (/*W=*/wback << 21)
18649 | (base_reg << 16)
18650 | (reg_mask & 0x0000ffff);
18651
18652 return patched_inst;
18653}
18654
18655static inline bfd_vma
18656create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18657{
18658 /* A8.8.60 LDMDB/LDMEA (A8-402)
18659 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18660 bfd_vma patched_inst = 0xe9100000
18661 | (/*W=*/wback << 21)
18662 | (base_reg << 16)
18663 | (reg_mask & 0x0000ffff);
18664
18665 return patched_inst;
18666}
18667
18668static inline bfd_vma
18669create_instruction_mov (int target_reg, int source_reg)
18670{
18671 /* A8.8.103 MOV (register) (A8-486)
18672 MOV Rd, Rm (Encoding T1). */
18673 bfd_vma patched_inst = 0x4600
18674 | (target_reg & 0x7)
18675 | ((target_reg & 0x8) >> 3) << 7
18676 | (source_reg << 3);
18677
18678 return patched_inst;
18679}
18680
18681static inline bfd_vma
18682create_instruction_sub (int target_reg, int source_reg, int value)
18683{
18684 /* A8.8.221 SUB (immediate) (A8-708)
18685 SUB Rd, Rn, #value (Encoding T3). */
18686 bfd_vma patched_inst = 0xf1a00000
18687 | (target_reg << 8)
18688 | (source_reg << 16)
18689 | (/*S=*/0 << 20)
18690 | ((value & 0x800) >> 11) << 26
18691 | ((value & 0x700) >> 8) << 12
18692 | (value & 0x0ff);
18693
18694 return patched_inst;
18695}
18696
18697static inline bfd_vma
9239bbd3 18698create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18699 int first_reg)
18700{
18701 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18702 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18703 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18704 | (/*W=*/wback << 21)
18705 | (base_reg << 16)
9239bbd3
CM		 18706 | (num_words & 0x000000ff)
18707 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18708 | (first_reg & 0x00000001) << 22;
18709
18710 return patched_inst;
18711}
18712
18713static inline bfd_vma
9239bbd3
CM		 18714create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18715 int first_reg)
a504d23a
LA		 18716{
18717 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18718 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18719 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18720 | (base_reg << 16)
9239bbd3
CM		 18721 | (num_words & 0x000000ff)
18722 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18723 | (first_reg & 0x00000001) << 22;
18724
18725 return patched_inst;
18726}
18727
18728static inline bfd_vma
18729create_instruction_udf_w (int value)
18730{
18731 /* A8.8.247 UDF (A8-758)
18732 Undefined (Encoding T2). */
18733 bfd_vma patched_inst = 0xf7f0a000
18734 | (value & 0x00000fff)
18735 | (value & 0x000f0000) << 16;
18736
18737 return patched_inst;
18738}
18739
18740static inline bfd_vma
18741create_instruction_udf (int value)
18742{
18743 /* A8.8.247 UDF (A8-758)
18744 Undefined (Encoding T1). */
18745 bfd_vma patched_inst = 0xde00
18746 | (value & 0xff);
18747
18748 return patched_inst;
18749}
18750
18751/* Functions writing an instruction in memory, returning the next
18752 memory position to write to. */
18753
18754static inline bfd_byte *
18755push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18756 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18757{
18758 put_thumb2_insn (htab, output_bfd, insn, pt);
18759 return pt + 4;
18760}
18761
18762static inline bfd_byte *
18763push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18764 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18765{
18766 put_thumb_insn (htab, output_bfd, insn, pt);
18767 return pt + 2;
18768}
18769
18770/* Function filling up a region in memory with T1 and T2 UDFs taking
18771 care of alignment. */
18772
18773static bfd_byte *
18774stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 18775 bfd * output_bfd,
18776 const bfd_byte * const base_stub_contents,
18777 bfd_byte * const from_stub_contents,
18778 const bfd_byte * const end_stub_contents)
a504d23a
LA		 18779{
18780 bfd_byte *current_stub_contents = from_stub_contents;
18781
18782 /* Fill the remaining of the stub with deterministic contents : UDF
18783 instructions.
18784 Check if realignment is needed on modulo 4 frontier using T1, to
18785 further use T2. */
18786 if ((current_stub_contents < end_stub_contents)
18787 && !((current_stub_contents - base_stub_contents) % 2)
18788 && ((current_stub_contents - base_stub_contents) % 4))
18789 current_stub_contents =
18790 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18791 create_instruction_udf (0));
18792
18793 for (; current_stub_contents < end_stub_contents;)
18794 current_stub_contents =
18795 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18796 create_instruction_udf_w (0));
18797
18798 return current_stub_contents;
18799}
18800
18801/* Functions writing the stream of instructions equivalent to the
18802 derived sequence for ldmia, ldmdb, vldm respectively. */
18803
18804static void
18805stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
18806 bfd * output_bfd,
18807 const insn32 initial_insn,
18808 const bfd_byte *const initial_insn_addr,
18809 bfd_byte *const base_stub_contents)
18810{
18811 int wback = (initial_insn & 0x00200000) >> 21;
18812 int ri, rn = (initial_insn & 0x000F0000) >> 16;
18813 int insn_all_registers = initial_insn & 0x0000ffff;
18814 int insn_low_registers, insn_high_registers;
18815 int usable_register_mask;
b25e998d 18816 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18817 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18818 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
18819 bfd_byte *current_stub_contents = base_stub_contents;
18820
18821 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
18822
18823 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18824 smaller than 8 registers load sequences that do not cause the
18825 hardware issue. */
18826 if (nb_registers <= 8)
18827 {
18828 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18829 current_stub_contents =
18830 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18831 initial_insn);
18832
18833 /* B initial_insn_addr+4. */
18834 if (!restore_pc)
18835 current_stub_contents =
18836 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18837 create_instruction_branch_absolute
82188b29 18838 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18839
18840 /* Fill the remaining of the stub with deterministic contents. */
18841 current_stub_contents =
18842 stm32l4xx_fill_stub_udf (htab, output_bfd,
18843 base_stub_contents, current_stub_contents,
18844 base_stub_contents +
18845 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18846
18847 return;
18848 }
18849
18850 /* - reg_list[13] == 0. */
18851 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
18852
18853 /* - reg_list[14] & reg_list[15] != 1. */
18854 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18855
18856 /* - if (wback==1) reg_list[rn] == 0. */
18857 BFD_ASSERT (!wback || !restore_rn);
18858
18859 /* - nb_registers > 8. */
b25e998d 18860 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18861
18862 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18863
18864 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
18865 - One with the 7 lowest registers (register mask 0x007F)
18866 This LDM will finally contain between 2 and 7 registers
18867 - One with the 7 highest registers (register mask 0xDF80)
18868 This ldm will finally contain between 2 and 7 registers. */
18869 insn_low_registers = insn_all_registers & 0x007F;
18870 insn_high_registers = insn_all_registers & 0xDF80;
18871
18872 /* A spare register may be needed during this veneer to temporarily
18873 handle the base register. This register will be restored with the
18874 last LDM operation.
18875 The usable register may be any general purpose register (that
18876 excludes PC, SP, LR : register mask is 0x1FFF). */
18877 usable_register_mask = 0x1FFF;
18878
18879 /* Generate the stub function. */
18880 if (wback)
18881 {
18882 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18883 current_stub_contents =
18884 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18885 create_instruction_ldmia
18886 (rn, /*wback=*/1, insn_low_registers));
18887
18888 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
18889 current_stub_contents =
18890 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18891 create_instruction_ldmia
18892 (rn, /*wback=*/1, insn_high_registers));
18893 if (!restore_pc)
18894 {
18895 /* B initial_insn_addr+4. */
18896 current_stub_contents =
18897 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18898 create_instruction_branch_absolute
82188b29 18899 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18900 }
18901 }
18902 else /* if (!wback). */
18903 {
18904 ri = rn;
18905
18906 /* If Rn is not part of the high-register-list, move it there. */
18907 if (!(insn_high_registers & (1 << rn)))
18908 {
18909 /* Choose a Ri in the high-register-list that will be restored. */
18910 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18911
18912 /* MOV Ri, Rn. */
18913 current_stub_contents =
18914 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18915 create_instruction_mov (ri, rn));
18916 }
18917
18918 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18919 current_stub_contents =
18920 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18921 create_instruction_ldmia
18922 (ri, /*wback=*/1, insn_low_registers));
18923
18924 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18925 current_stub_contents =
18926 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18927 create_instruction_ldmia
18928 (ri, /*wback=*/0, insn_high_registers));
18929
18930 if (!restore_pc)
18931 {
18932 /* B initial_insn_addr+4. */
18933 current_stub_contents =
18934 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18935 create_instruction_branch_absolute
82188b29 18936 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18937 }
18938 }
18939
18940 /* Fill the remaining of the stub with deterministic contents. */
18941 current_stub_contents =
18942 stm32l4xx_fill_stub_udf (htab, output_bfd,
18943 base_stub_contents, current_stub_contents,
18944 base_stub_contents +
18945 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18946}
18947
18948static void
18949stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
18950 bfd * output_bfd,
18951 const insn32 initial_insn,
18952 const bfd_byte *const initial_insn_addr,
18953 bfd_byte *const base_stub_contents)
18954{
18955 int wback = (initial_insn & 0x00200000) >> 21;
18956 int ri, rn = (initial_insn & 0x000f0000) >> 16;
18957 int insn_all_registers = initial_insn & 0x0000ffff;
18958 int insn_low_registers, insn_high_registers;
18959 int usable_register_mask;
18960 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18961 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 18962 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18963 bfd_byte *current_stub_contents = base_stub_contents;
18964
18965 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
18966
18967 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18968 smaller than 8 registers load sequences that do not cause the
18969 hardware issue. */
18970 if (nb_registers <= 8)
18971 {
18972 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18973 current_stub_contents =
18974 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18975 initial_insn);
18976
18977 /* B initial_insn_addr+4. */
18978 current_stub_contents =
18979 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18980 create_instruction_branch_absolute
82188b29 18981 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18982
18983 /* Fill the remaining of the stub with deterministic contents. */
18984 current_stub_contents =
18985 stm32l4xx_fill_stub_udf (htab, output_bfd,
18986 base_stub_contents, current_stub_contents,
18987 base_stub_contents +
18988 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18989
18990 return;
18991 }
18992
18993 /* - reg_list[13] == 0. */
18994 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
18995
18996 /* - reg_list[14] & reg_list[15] != 1. */
18997 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18998
18999 /* - if (wback==1) reg_list[rn] == 0. */
19000 BFD_ASSERT (!wback || !restore_rn);
19001
19002 /* - nb_registers > 8. */
b25e998d 19003 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19004
19005 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19006
19007 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19008 - One with the 7 lowest registers (register mask 0x007F)
19009 This LDM will finally contain between 2 and 7 registers
19010 - One with the 7 highest registers (register mask 0xDF80)
19011 This ldm will finally contain between 2 and 7 registers. */
19012 insn_low_registers = insn_all_registers & 0x007F;
19013 insn_high_registers = insn_all_registers & 0xDF80;
19014
19015 /* A spare register may be needed during this veneer to temporarily
19016 handle the base register. This register will be restored with
19017 the last LDM operation.
19018 The usable register may be any general purpose register (that excludes
19019 PC, SP, LR : register mask is 0x1FFF). */
19020 usable_register_mask = 0x1FFF;
19021
19022 /* Generate the stub function. */
19023 if (!wback && !restore_pc && !restore_rn)
19024 {
19025 /* Choose a Ri in the low-register-list that will be restored. */
19026 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19027
19028 /* MOV Ri, Rn. */
19029 current_stub_contents =
19030 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19031 create_instruction_mov (ri, rn));
19032
19033 /* LDMDB Ri!, {R-high-register-list}. */
19034 current_stub_contents =
19035 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19036 create_instruction_ldmdb
19037 (ri, /*wback=*/1, insn_high_registers));
19038
19039 /* LDMDB Ri, {R-low-register-list}. */
19040 current_stub_contents =
19041 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19042 create_instruction_ldmdb
19043 (ri, /*wback=*/0, insn_low_registers));
19044
19045 /* B initial_insn_addr+4. */
19046 current_stub_contents =
19047 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19048 create_instruction_branch_absolute
82188b29 19049 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19050 }
19051 else if (wback && !restore_pc && !restore_rn)
19052 {
19053 /* LDMDB Rn!, {R-high-register-list}. */
19054 current_stub_contents =
19055 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19056 create_instruction_ldmdb
19057 (rn, /*wback=*/1, insn_high_registers));
19058
19059 /* LDMDB Rn!, {R-low-register-list}. */
19060 current_stub_contents =
19061 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19062 create_instruction_ldmdb
19063 (rn, /*wback=*/1, insn_low_registers));
19064
19065 /* B initial_insn_addr+4. */
19066 current_stub_contents =
19067 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19068 create_instruction_branch_absolute
82188b29 19069 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19070 }
19071 else if (!wback && restore_pc && !restore_rn)
19072 {
19073 /* Choose a Ri in the high-register-list that will be restored. */
19074 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19075
19076 /* SUB Ri, Rn, #(4*nb_registers). */
19077 current_stub_contents =
19078 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19079 create_instruction_sub (ri, rn, (4 * nb_registers)));
19080
19081 /* LDMIA Ri!, {R-low-register-list}. */
19082 current_stub_contents =
19083 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19084 create_instruction_ldmia
19085 (ri, /*wback=*/1, insn_low_registers));
19086
19087 /* LDMIA Ri, {R-high-register-list}. */
19088 current_stub_contents =
19089 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19090 create_instruction_ldmia
19091 (ri, /*wback=*/0, insn_high_registers));
19092 }
19093 else if (wback && restore_pc && !restore_rn)
19094 {
19095 /* Choose a Ri in the high-register-list that will be restored. */
19096 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19097
19098 /* SUB Rn, Rn, #(4*nb_registers) */
19099 current_stub_contents =
19100 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19101 create_instruction_sub (rn, rn, (4 * nb_registers)));
19102
19103 /* MOV Ri, Rn. */
19104 current_stub_contents =
19105 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19106 create_instruction_mov (ri, rn));
19107
19108 /* LDMIA Ri!, {R-low-register-list}. */
19109 current_stub_contents =
19110 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19111 create_instruction_ldmia
19112 (ri, /*wback=*/1, insn_low_registers));
19113
19114 /* LDMIA Ri, {R-high-register-list}. */
19115 current_stub_contents =
19116 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19117 create_instruction_ldmia
19118 (ri, /*wback=*/0, insn_high_registers));
19119 }
19120 else if (!wback && !restore_pc && restore_rn)
19121 {
19122 ri = rn;
19123 if (!(insn_low_registers & (1 << rn)))
19124 {
19125 /* Choose a Ri in the low-register-list that will be restored. */
19126 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19127
19128 /* MOV Ri, Rn. */
19129 current_stub_contents =
19130 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19131 create_instruction_mov (ri, rn));
19132 }
19133
19134 /* LDMDB Ri!, {R-high-register-list}. */
19135 current_stub_contents =
19136 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19137 create_instruction_ldmdb
19138 (ri, /*wback=*/1, insn_high_registers));
19139
19140 /* LDMDB Ri, {R-low-register-list}. */
19141 current_stub_contents =
19142 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19143 create_instruction_ldmdb
19144 (ri, /*wback=*/0, insn_low_registers));
19145
19146 /* B initial_insn_addr+4. */
19147 current_stub_contents =
19148 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19149 create_instruction_branch_absolute
82188b29 19150 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19151 }
19152 else if (!wback && restore_pc && restore_rn)
19153 {
19154 ri = rn;
19155 if (!(insn_high_registers & (1 << rn)))
19156 {
19157 /* Choose a Ri in the high-register-list that will be restored. */
19158 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19159 }
19160
19161 /* SUB Ri, Rn, #(4*nb_registers). */
19162 current_stub_contents =
19163 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19164 create_instruction_sub (ri, rn, (4 * nb_registers)));
19165
19166 /* LDMIA Ri!, {R-low-register-list}. */
19167 current_stub_contents =
19168 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19169 create_instruction_ldmia
19170 (ri, /*wback=*/1, insn_low_registers));
19171
19172 /* LDMIA Ri, {R-high-register-list}. */
19173 current_stub_contents =
19174 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19175 create_instruction_ldmia
19176 (ri, /*wback=*/0, insn_high_registers));
19177 }
19178 else if (wback && restore_rn)
19179 {
19180 /* The assembler should not have accepted to encode this. */
19181 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19182 "undefined behavior.\n");
19183 }
19184
19185 /* Fill the remaining of the stub with deterministic contents. */
19186 current_stub_contents =
19187 stm32l4xx_fill_stub_udf (htab, output_bfd,
19188 base_stub_contents, current_stub_contents,
19189 base_stub_contents +
19190 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19191
19192}
19193
19194static void
19195stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19196 bfd * output_bfd,
19197 const insn32 initial_insn,
19198 const bfd_byte *const initial_insn_addr,
19199 bfd_byte *const base_stub_contents)
19200{
13c9c485 19201 int num_words = initial_insn & 0xff;
a504d23a
LA		 19202 bfd_byte *current_stub_contents = base_stub_contents;
19203
19204 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19205
19206 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19207 smaller than 8 words load sequences that do not cause the
a504d23a 19208 hardware issue. */
9239bbd3 19209 if (num_words <= 8)
a504d23a
LA		 19210 {
19211 /* Untouched instruction. */
19212 current_stub_contents =
19213 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19214 initial_insn);
19215
19216 /* B initial_insn_addr+4. */
19217 current_stub_contents =
19218 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19219 create_instruction_branch_absolute
82188b29 19220 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19221 }
19222 else
19223 {
9eaff861 19224 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19225 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19226 bfd_boolean is_ia_nobang = /* (IA without !). */
19227 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19228 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19229 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19230 bfd_boolean is_db_bang = /* (DB with !). */
19231 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19232 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19233 /* d = UInt (Vd:D);. */
9239bbd3 19234 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19235 | (((unsigned int)initial_insn << 9) >> 31);
19236
9239bbd3
CM		 19237 /* Compute the number of 8-words chunks needed to split. */
19238 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19239 int chunk;
19240
19241 /* The test coverage has been done assuming the following
19242 hypothesis that exactly one of the previous is_ predicates is
19243 true. */
9239bbd3
CM		 19244 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19245 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19246
9239bbd3 19247 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19248 cases, then we emit the adjustments:
19249
19250 vldm rx, {...}
19251 -> vldm rx!, {8_words_or_less} for each needed 8_word
19252 -> sub rx, rx, #size (list)
19253
19254 vldm rx!, {...}
19255 -> vldm rx!, {8_words_or_less} for each needed 8_word
19256 This also handles vpop instruction (when rx is sp)
19257
19258 vldmd rx!, {...}
19259 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19260 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19261 {
9239bbd3
CM		 19262 bfd_vma new_insn = 0;
19263
a504d23a
LA		 19264 if (is_ia_nobang || is_ia_bang)
19265 {
9239bbd3
CM		 19266 new_insn = create_instruction_vldmia
19267 (base_reg,
19268 is_dp,
19269 /*wback= . */1,
19270 chunks - (chunk + 1) ?
19271 8 : num_words - chunk * 8,
19272 first_reg + chunk * 8);
a504d23a
LA		 19273 }
19274 else if (is_db_bang)
19275 {
9239bbd3
CM		 19276 new_insn = create_instruction_vldmdb
19277 (base_reg,
19278 is_dp,
19279 chunks - (chunk + 1) ?
19280 8 : num_words - chunk * 8,
19281 first_reg + chunk * 8);
a504d23a 19282 }
9239bbd3
CM		 19283
19284 if (new_insn)
19285 current_stub_contents =
19286 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19287 new_insn);
a504d23a
LA		 19288 }
19289
19290 /* Only this case requires the base register compensation
19291 subtract. */
19292 if (is_ia_nobang)
19293 {
19294 current_stub_contents =
19295 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19296 create_instruction_sub
9239bbd3 19297 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19298 }
19299
19300 /* B initial_insn_addr+4. */
19301 current_stub_contents =
19302 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19303 create_instruction_branch_absolute
82188b29 19304 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19305 }
19306
19307 /* Fill the remaining of the stub with deterministic contents. */
19308 current_stub_contents =
19309 stm32l4xx_fill_stub_udf (htab, output_bfd,
19310 base_stub_contents, current_stub_contents,
19311 base_stub_contents +
19312 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19313}
19314
19315static void
19316stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19317 bfd * output_bfd,
19318 const insn32 wrong_insn,
19319 const bfd_byte *const wrong_insn_addr,
19320 bfd_byte *const stub_contents)
19321{
19322 if (is_thumb2_ldmia (wrong_insn))
19323 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19324 wrong_insn, wrong_insn_addr,
19325 stub_contents);
19326 else if (is_thumb2_ldmdb (wrong_insn))
19327 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19328 wrong_insn, wrong_insn_addr,
19329 stub_contents);
19330 else if (is_thumb2_vldm (wrong_insn))
19331 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19332 wrong_insn, wrong_insn_addr,
19333 stub_contents);
19334}
19335
19336/* End of stm32l4xx work-around. */
19337
19338
e489d0ae
PB		 19339/* Do code byteswapping. Return FALSE afterwards so that the section is
19340 written out as normal. */
19341
19342static bfd_boolean
c7b8f16e 19343elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19344 struct bfd_link_info *link_info,
19345 asection *sec,
e489d0ae
PB		 19346 bfd_byte *contents)
19347{
48229727 19348 unsigned int mapcount, errcount;
8e3de13a 19349 _arm_elf_section_data *arm_data;
c7b8f16e 19350 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19351 elf32_arm_section_map *map;
c7b8f16e 19352 elf32_vfp11_erratum_list *errnode;
a504d23a 19353 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19354 bfd_vma ptr;
19355 bfd_vma end;
c7b8f16e 19356 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19357 bfd_byte tmp;
48229727 19358 unsigned int i;
57e8b36a 19359
4dfe6ac6
NC		 19360 if (globals == NULL)
19361 return FALSE;
19362
8e3de13a
NC		 19363 /* If this section has not been allocated an _arm_elf_section_data
19364 structure then we cannot record anything. */
19365 arm_data = get_arm_elf_section_data (sec);
19366 if (arm_data == NULL)
19367 return FALSE;
19368
19369 mapcount = arm_data->mapcount;
19370 map = arm_data->map;
c7b8f16e
JB		 19371 errcount = arm_data->erratumcount;
19372
19373 if (errcount != 0)
19374 {
19375 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19376
19377 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19378 errnode = errnode->next)
19379 {
19380 bfd_vma target = errnode->vma - offset;
19381
19382 switch (errnode->type)
19383 {
19384 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19385 {
19386 bfd_vma branch_to_veneer;
19387 /* Original condition code of instruction, plus bit mask for
19388 ARM B instruction. */
19389 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19390 | 0x0a000000;
c7b8f16e
JB		 19391
19392 /* The instruction is before the label. */
91d6fa6a 19393 target -= 4;
c7b8f16e
JB		 19394
19395 /* Above offset included in -4 below. */
19396 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19397 - errnode->vma - 4;
c7b8f16e
JB		 19398
19399 if ((signed) branch_to_veneer < -(1 << 25)
19400 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19401 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19402 "range"), output_bfd);
c7b8f16e 19403
99059e56
RM		 19404 insn |= (branch_to_veneer >> 2) & 0xffffff;
19405 contents[endianflip ^ target] = insn & 0xff;
19406 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19407 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19408 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19409 }
19410 break;
c7b8f16e
JB		 19411
19412 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19413 {
19414 bfd_vma branch_from_veneer;
19415 unsigned int insn;
c7b8f16e 19416
99059e56
RM		 19417 /* Take size of veneer into account. */
19418 branch_from_veneer = errnode->u.v.branch->vma
19419 - errnode->vma - 12;
c7b8f16e
JB		 19420
19421 if ((signed) branch_from_veneer < -(1 << 25)
19422 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19423 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19424 "range"), output_bfd);
c7b8f16e 19425
99059e56
RM		 19426 /* Original instruction. */
19427 insn = errnode->u.v.branch->u.b.vfp_insn;
19428 contents[endianflip ^ target] = insn & 0xff;
19429 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19430 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19431 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19432
19433 /* Branch back to insn after original insn. */
19434 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19435 contents[endianflip ^ (target + 4)] = insn & 0xff;
19436 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19437 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19438 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19439 }
19440 break;
c7b8f16e 19441
99059e56
RM		 19442 default:
19443 abort ();
19444 }
19445 }
c7b8f16e 19446 }
e489d0ae 19447
a504d23a
LA		 19448 if (arm_data->stm32l4xx_erratumcount != 0)
19449 {
19450 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19451 stm32l4xx_errnode != 0;
19452 stm32l4xx_errnode = stm32l4xx_errnode->next)
19453 {
19454 bfd_vma target = stm32l4xx_errnode->vma - offset;
19455
19456 switch (stm32l4xx_errnode->type)
19457 {
19458 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19459 {
19460 unsigned int insn;
19461 bfd_vma branch_to_veneer =
19462 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19463
19464 if ((signed) branch_to_veneer < -(1 << 24)
19465 || (signed) branch_to_veneer >= (1 << 24))
19466 {
19467 bfd_vma out_of_range =
19468 ((signed) branch_to_veneer < -(1 << 24)) ?
19469 - branch_to_veneer - (1 << 24) :
19470 ((signed) branch_to_veneer >= (1 << 24)) ?
19471 branch_to_veneer - (1 << 24) : 0;
19472
4eca0228 19473 _bfd_error_handler
2dcf00ce 19474 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19475 "cannot create STM32L4XX veneer; "
19476 "jump out of range by %" PRId64 " bytes; "
19477 "cannot encode branch instruction"),
a504d23a 19478 output_bfd,
2dcf00ce
AM		 19479 (uint64_t) (stm32l4xx_errnode->vma - 4),
19480 (int64_t) out_of_range);
a504d23a
LA		 19481 continue;
19482 }
19483
19484 insn = create_instruction_branch_absolute
82188b29 19485 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a 19486
a2699ef2
AM		 19487 /* The instruction is before the label. */
19488 target -= 4;
19489
a504d23a
LA		 19490 put_thumb2_insn (globals, output_bfd,
19491 (bfd_vma) insn, contents + target);
19492 }
19493 break;
19494
19495 case STM32L4XX_ERRATUM_VENEER:
19496 {
82188b29
NC		 19497 bfd_byte * veneer;
19498 bfd_byte * veneer_r;
a504d23a
LA		 19499 unsigned int insn;
19500
82188b29
NC		 19501 veneer = contents + target;
19502 veneer_r = veneer
19503 + stm32l4xx_errnode->u.b.veneer->vma
19504 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19505
19506 if ((signed) (veneer_r - veneer -
19507 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19508 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19509 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19510 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19511 || (signed) (veneer_r - veneer) >= (1 << 24))
19512 {
90b6238f
AM		 19513 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19514 "veneer"), output_bfd);
a504d23a
LA		 19515 continue;
19516 }
19517
19518 /* Original instruction. */
19519 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19520
19521 stm32l4xx_create_replacing_stub
19522 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19523 }
19524 break;
19525
19526 default:
19527 abort ();
19528 }
19529 }
19530 }
19531
2468f9c9
PB		 19532 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19533 {
19534 arm_unwind_table_edit *edit_node
99059e56 19535 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19536 /* Now, sec->size is the size of the section we will write. The original
99059e56 19537 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19538 markers) was sec->rawsize. (This isn't the case if we perform no
19539 edits, then rawsize will be zero and we should use size). */
21d799b5 19540 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19541 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19542 unsigned int in_index, out_index;
19543 bfd_vma add_to_offsets = 0;
19544
7a0fb7be
NC		 19545 if (edited_contents == NULL)
19546 return FALSE;
2468f9c9 19547 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19548 {
2468f9c9
PB		 19549 if (edit_node)
19550 {
19551 unsigned int edit_index = edit_node->index;
b38cadfb 19552
2468f9c9 19553 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19554 {
2468f9c9
PB		 19555 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19556 contents + in_index * 8, add_to_offsets);
19557 out_index++;
19558 in_index++;
19559 }
19560 else if (in_index == edit_index
19561 || (in_index * 8 >= input_size
19562 && edit_index == UINT_MAX))
99059e56 19563 {
2468f9c9
PB		 19564 switch (edit_node->type)
19565 {
19566 case DELETE_EXIDX_ENTRY:
19567 in_index++;
19568 add_to_offsets += 8;
19569 break;
b38cadfb 19570
2468f9c9
PB		 19571 case INSERT_EXIDX_CANTUNWIND_AT_END:
19572 {
99059e56 19573 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19574 bfd_vma text_offset = text_sec->output_section->vma
19575 + text_sec->output_offset
19576 + text_sec->size;
19577 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19578 unsigned long prel31_offset;
2468f9c9
PB		 19579
19580 /* Note: this is meant to be equivalent to an
19581 R_ARM_PREL31 relocation. These synthetic
19582 EXIDX_CANTUNWIND markers are not relocated by the
19583 usual BFD method. */
19584 prel31_offset = (text_offset - exidx_offset)
19585 & 0x7ffffffful;
491d01d3
YU		 19586 if (bfd_link_relocatable (link_info))
19587 {
19588 /* Here relocation for new EXIDX_CANTUNWIND is
19589 created, so there is no need to
19590 adjust offset by hand. */
19591 prel31_offset = text_sec->output_offset
19592 + text_sec->size;
491d01d3 19593 }
2468f9c9
PB		 19594
19595 /* First address we can't unwind. */
19596 bfd_put_32 (output_bfd, prel31_offset,
19597 &edited_contents[out_index * 8]);
19598
19599 /* Code for EXIDX_CANTUNWIND. */
19600 bfd_put_32 (output_bfd, 0x1,
19601 &edited_contents[out_index * 8 + 4]);
19602
19603 out_index++;
19604 add_to_offsets -= 8;
19605 }
19606 break;
19607 }
b38cadfb 19608
2468f9c9
PB		 19609 edit_node = edit_node->next;
19610 }
19611 }
19612 else
19613 {
19614 /* No more edits, copy remaining entries verbatim. */
19615 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19616 contents + in_index * 8, add_to_offsets);
19617 out_index++;
19618 in_index++;
19619 }
19620 }
19621
19622 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19623 bfd_set_section_contents (output_bfd, sec->output_section,
19624 edited_contents,
19625 (file_ptr) sec->output_offset, sec->size);
19626
19627 return TRUE;
19628 }
19629
48229727
JB		 19630 /* Fix code to point to Cortex-A8 erratum stubs. */
19631 if (globals->fix_cortex_a8)
19632 {
19633 struct a8_branch_to_stub_data data;
19634
19635 data.writing_section = sec;
19636 data.contents = contents;
19637
a504d23a
LA		 19638 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19639 & data);
48229727
JB		 19640 }
19641
e489d0ae
PB		 19642 if (mapcount == 0)
19643 return FALSE;
19644
c7b8f16e 19645 if (globals->byteswap_code)
e489d0ae 19646 {
c7b8f16e 19647 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19648
c7b8f16e
JB		 19649 ptr = map[0].vma;
19650 for (i = 0; i < mapcount; i++)
99059e56
RM		 19651 {
19652 if (i == mapcount - 1)
c7b8f16e 19653 end = sec->size;
99059e56
RM		 19654 else
19655 end = map[i + 1].vma;
e489d0ae 19656
99059e56 19657 switch (map[i].type)
e489d0ae 19658 {
c7b8f16e
JB		 19659 case 'a':
19660 /* Byte swap code words. */
19661 while (ptr + 3 < end)
99059e56
RM		 19662 {
19663 tmp = contents[ptr];
19664 contents[ptr] = contents[ptr + 3];
19665 contents[ptr + 3] = tmp;
19666 tmp = contents[ptr + 1];
19667 contents[ptr + 1] = contents[ptr + 2];
19668 contents[ptr + 2] = tmp;
19669 ptr += 4;
19670 }
c7b8f16e 19671 break;
e489d0ae 19672
c7b8f16e
JB		 19673 case 't':
19674 /* Byte swap code halfwords. */
19675 while (ptr + 1 < end)
99059e56
RM		 19676 {
19677 tmp = contents[ptr];
19678 contents[ptr] = contents[ptr + 1];
19679 contents[ptr + 1] = tmp;
19680 ptr += 2;
19681 }
c7b8f16e
JB		 19682 break;
19683
19684 case 'd':
19685 /* Leave data alone. */
19686 break;
19687 }
99059e56
RM		 19688 ptr = end;
19689 }
e489d0ae 19690 }
8e3de13a 19691
93204d3a 19692 free (map);
47b2e99c 19693 arm_data->mapcount = -1;
c7b8f16e 19694 arm_data->mapsize = 0;
8e3de13a 19695 arm_data->map = NULL;
8e3de13a 19696
e489d0ae
PB		 19697 return FALSE;
19698}
19699
0beaef2b
PB		 19700/* Mangle thumb function symbols as we read them in. */
19701
8384fb8f 19702static bfd_boolean
0beaef2b
PB		 19703elf32_arm_swap_symbol_in (bfd * abfd,
19704 const void *psrc,
19705 const void *pshn,
19706 Elf_Internal_Sym *dst)
19707{
8384fb8f
AM		 19708 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19709 return FALSE;
39d911fc 19710 dst->st_target_internal = 0;
0beaef2b
PB		 19711
19712 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19713 the address. */
63e1a0fc
PB		 19714 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19715 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19716 {
63e1a0fc
PB		 19717 if (dst->st_value & 1)
19718 {
19719 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19720 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19721 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19722 }
19723 else
39d911fc 19724 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19725 }
19726 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19727 {
19728 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19729 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19730 }
35fc36a8 19731 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19732 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19733 else
39d911fc 19734 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19735
8384fb8f 19736 return TRUE;
0beaef2b
PB		 19737}
19738
19739
19740/* Mangle thumb function symbols as we write them out. */
19741
19742static void
19743elf32_arm_swap_symbol_out (bfd *abfd,
19744 const Elf_Internal_Sym *src,
19745 void *cdst,
19746 void *shndx)
19747{
19748 Elf_Internal_Sym newsym;
19749
19750 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19751 of the address set, as per the new EABI. We do this unconditionally
19752 because objcopy does not set the elf header flags until after
19753 it writes out the symbol table. */
39d911fc 19754 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19755 {
19756 newsym = *src;
34e77a92
RS		 19757 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19758 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19759 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 19760 {
19761 /* Do this only for defined symbols. At link type, the static
19762 linker will simulate the work of dynamic linker of resolving
19763 symbols and will carry over the thumbness of found symbols to
19764 the output symbol table. It's not clear how it happens, but
19765 the thumbness of undefined symbols can well be different at
19766 runtime, and writing '1' for them will be confusing for users
19767 and possibly for dynamic linker itself.
19768 */
19769 newsym.st_value |= 1;
19770 }
906e58ca 19771
0beaef2b
PB		 19772 src = &newsym;
19773 }
19774 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
19775}
19776
b294bdf8
MM		 19777/* Add the PT_ARM_EXIDX program header. */
19778
19779static bfd_boolean
906e58ca 19780elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 19781 struct bfd_link_info *info ATTRIBUTE_UNUSED)
19782{
19783 struct elf_segment_map *m;
19784 asection *sec;
19785
19786 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19787 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19788 {
19789 /* If there is already a PT_ARM_EXIDX header, then we do not
19790 want to add another one. This situation arises when running
19791 "strip"; the input binary already has the header. */
12bd6957 19792 m = elf_seg_map (abfd);
b294bdf8
MM		 19793 while (m && m->p_type != PT_ARM_EXIDX)
19794 m = m->next;
19795 if (!m)
19796 {
21d799b5 19797 m = (struct elf_segment_map *)
99059e56 19798 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 19799 if (m == NULL)
19800 return FALSE;
19801 m->p_type = PT_ARM_EXIDX;
19802 m->count = 1;
19803 m->sections[0] = sec;
19804
12bd6957
AM		 19805 m->next = elf_seg_map (abfd);
19806 elf_seg_map (abfd) = m;
b294bdf8
MM		 19807 }
19808 }
19809
19810 return TRUE;
19811}
19812
19813/* We may add a PT_ARM_EXIDX program header. */
19814
19815static int
a6b96beb
AM		 19816elf32_arm_additional_program_headers (bfd *abfd,
19817 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 19818{
19819 asection *sec;
19820
19821 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19822 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19823 return 1;
19824 else
19825 return 0;
19826}
19827
34e77a92
RS		 19828/* Hook called by the linker routine which adds symbols from an object
19829 file. */
19830
19831static bfd_boolean
19832elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
19833 Elf_Internal_Sym *sym, const char **namep,
19834 flagword *flagsp, asection **secp, bfd_vma *valp)
19835{
c792917c
NC		 19836 if (elf32_arm_hash_table (info) == NULL)
19837 return FALSE;
19838
90c14f0c 19839 if (elf32_arm_hash_table (info)->root.target_os == is_vxworks
34e77a92
RS		 19840 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
19841 flagsp, secp, valp))
19842 return FALSE;
19843
19844 return TRUE;
19845}
19846
0beaef2b 19847/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 19848const struct elf_size_info elf32_arm_size_info =
19849{
0beaef2b
PB		 19850 sizeof (Elf32_External_Ehdr),
19851 sizeof (Elf32_External_Phdr),
19852 sizeof (Elf32_External_Shdr),
19853 sizeof (Elf32_External_Rel),
19854 sizeof (Elf32_External_Rela),
19855 sizeof (Elf32_External_Sym),
19856 sizeof (Elf32_External_Dyn),
19857 sizeof (Elf_External_Note),
19858 4,
19859 1,
19860 32, 2,
19861 ELFCLASS32, EV_CURRENT,
19862 bfd_elf32_write_out_phdrs,
19863 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 19864 bfd_elf32_checksum_contents,
0beaef2b
PB		 19865 bfd_elf32_write_relocs,
19866 elf32_arm_swap_symbol_in,
19867 elf32_arm_swap_symbol_out,
19868 bfd_elf32_slurp_reloc_table,
19869 bfd_elf32_slurp_symbol_table,
19870 bfd_elf32_swap_dyn_in,
19871 bfd_elf32_swap_dyn_out,
19872 bfd_elf32_swap_reloc_in,
19873 bfd_elf32_swap_reloc_out,
19874 bfd_elf32_swap_reloca_in,
19875 bfd_elf32_swap_reloca_out
19876};
19877
685e70ae
VK		 19878static bfd_vma
19879read_code32 (const bfd *abfd, const bfd_byte *addr)
19880{
19881 /* V7 BE8 code is always little endian. */
19882 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19883 return bfd_getl32 (addr);
19884
19885 return bfd_get_32 (abfd, addr);
19886}
19887
19888static bfd_vma
19889read_code16 (const bfd *abfd, const bfd_byte *addr)
19890{
19891 /* V7 BE8 code is always little endian. */
19892 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19893 return bfd_getl16 (addr);
19894
19895 return bfd_get_16 (abfd, addr);
19896}
19897
6a631e86
YG		 19898/* Return size of plt0 entry starting at ADDR
19899 or (bfd_vma) -1 if size can not be determined. */
19900
19901static bfd_vma
19902elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
19903{
19904 bfd_vma first_word;
19905 bfd_vma plt0_size;
19906
685e70ae 19907 first_word = read_code32 (abfd, addr);
6a631e86
YG		 19908
19909 if (first_word == elf32_arm_plt0_entry[0])
19910 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19911 else if (first_word == elf32_thumb2_plt0_entry[0])
19912 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19913 else
19914 /* We don't yet handle this PLT format. */
19915 return (bfd_vma) -1;
19916
19917 return plt0_size;
19918}
19919
19920/* Return size of plt entry starting at offset OFFSET
19921 of plt section located at address START
19922 or (bfd_vma) -1 if size can not be determined. */
19923
19924static bfd_vma
19925elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
19926{
19927 bfd_vma first_insn;
19928 bfd_vma plt_size = 0;
19929 const bfd_byte *addr = start + offset;
19930
19931 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 19932 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 19933 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
19934
19935 /* Respect Thumb stub if necessary. */
685e70ae 19936 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 19937 {
19938 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
19939 }
19940
19941 /* Strip immediate from first add. */
685e70ae 19942 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 19943
19944#ifdef FOUR_WORD_PLT
19945 if (first_insn == elf32_arm_plt_entry[0])
19946 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
19947#else
19948 if (first_insn == elf32_arm_plt_entry_long[0])
19949 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
19950 else if (first_insn == elf32_arm_plt_entry_short[0])
19951 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
19952#endif
19953 else
19954 /* We don't yet handle this PLT format. */
19955 return (bfd_vma) -1;
19956
19957 return plt_size;
19958}
19959
19960/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19961
19962static long
19963elf32_arm_get_synthetic_symtab (bfd *abfd,
19964 long symcount ATTRIBUTE_UNUSED,
19965 asymbol **syms ATTRIBUTE_UNUSED,
19966 long dynsymcount,
19967 asymbol **dynsyms,
19968 asymbol **ret)
19969{
19970 asection *relplt;
19971 asymbol *s;
19972 arelent *p;
19973 long count, i, n;
19974 size_t size;
19975 Elf_Internal_Shdr *hdr;
19976 char *names;
19977 asection *plt;
19978 bfd_vma offset;
19979 bfd_byte *data;
19980
19981 *ret = NULL;
19982
19983 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
19984 return 0;
19985
19986 if (dynsymcount <= 0)
19987 return 0;
19988
19989 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
19990 if (relplt == NULL)
19991 return 0;
19992
19993 hdr = &elf_section_data (relplt)->this_hdr;
19994 if (hdr->sh_link != elf_dynsymtab (abfd)
19995 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
19996 return 0;
19997
19998 plt = bfd_get_section_by_name (abfd, ".plt");
19999 if (plt == NULL)
20000 return 0;
20001
20002 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
20003 return -1;
20004
20005 data = plt->contents;
20006 if (data == NULL)
20007 {
20008 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
20009 return -1;
20010 bfd_cache_section_contents((asection *) plt, data);
20011 }
20012
20013 count = relplt->size / hdr->sh_entsize;
20014 size = count * sizeof (asymbol);
20015 p = relplt->relocation;
20016 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20017 {
20018 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
20019 if (p->addend != 0)
20020 size += sizeof ("+0x") - 1 + 8;
20021 }
20022
20023 s = *ret = (asymbol *) bfd_malloc (size);
20024 if (s == NULL)
20025 return -1;
20026
20027 offset = elf32_arm_plt0_size (abfd, data);
20028 if (offset == (bfd_vma) -1)
20029 return -1;
20030
20031 names = (char *) (s + count);
20032 p = relplt->relocation;
20033 n = 0;
20034 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20035 {
20036 size_t len;
20037
20038 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20039 if (plt_size == (bfd_vma) -1)
20040 break;
20041
20042 *s = **p->sym_ptr_ptr;
20043 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20044 we are defining a symbol, ensure one of them is set. */
20045 if ((s->flags & BSF_LOCAL) == 0)
20046 s->flags |= BSF_GLOBAL;
20047 s->flags |= BSF_SYNTHETIC;
20048 s->section = plt;
20049 s->value = offset;
20050 s->name = names;
20051 s->udata.p = NULL;
20052 len = strlen ((*p->sym_ptr_ptr)->name);
20053 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20054 names += len;
20055 if (p->addend != 0)
20056 {
20057 char buf[30], *a;
20058
20059 memcpy (names, "+0x", sizeof ("+0x") - 1);
20060 names += sizeof ("+0x") - 1;
20061 bfd_sprintf_vma (abfd, buf, p->addend);
20062 for (a = buf; *a == '0'; ++a)
20063 ;
20064 len = strlen (a);
20065 memcpy (names, a, len);
20066 names += len;
20067 }
20068 memcpy (names, "@plt", sizeof ("@plt"));
20069 names += sizeof ("@plt");
20070 ++s, ++n;
20071 offset += plt_size;
20072 }
20073
20074 return n;
20075}
20076
ac4c9b04 20077static bfd_boolean
8c803a2d 20078elf32_arm_section_flags (const Elf_Internal_Shdr *hdr)
ac4c9b04 20079{
f0728ee3 20080 if (hdr->sh_flags & SHF_ARM_PURECODE)
8c803a2d 20081 hdr->bfd_section->flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20082 return TRUE;
20083}
20084
20085static flagword
20086elf32_arm_lookup_section_flags (char *flag_name)
20087{
f0728ee3
AV		 20088 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20089 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20090
20091 return SEC_NO_FLAGS;
20092}
20093
491d01d3
YU		 20094static unsigned int
20095elf32_arm_count_additional_relocs (asection *sec)
20096{
20097 struct _arm_elf_section_data *arm_data;
20098 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20099
6342be70 20100 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20101}
20102
5522f910 20103/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20104 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20105 FALSE otherwise. ISECTION is the best guess matching section from the
20106 input bfd IBFD, but it might be NULL. */
20107
20108static bfd_boolean
20109elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20110 bfd *obfd ATTRIBUTE_UNUSED,
20111 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20112 Elf_Internal_Shdr *osection)
20113{
20114 switch (osection->sh_type)
20115 {
20116 case SHT_ARM_EXIDX:
20117 {
20118 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20119 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20120 unsigned i = 0;
20121
20122 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20123 osection->sh_info = 0;
20124
20125 /* The sh_link field must be set to the text section associated with
20126 this index section. Unfortunately the ARM EHABI does not specify
20127 exactly how to determine this association. Our caller does try
20128 to match up OSECTION with its corresponding input section however
20129 so that is a good first guess. */
20130 if (isection != NULL
20131 && osection->bfd_section != NULL
20132 && isection->bfd_section != NULL
20133 && isection->bfd_section->output_section != NULL
20134 && isection->bfd_section->output_section == osection->bfd_section
20135 && iheaders != NULL
20136 && isection->sh_link > 0
20137 && isection->sh_link < elf_numsections (ibfd)
20138 && iheaders[isection->sh_link]->bfd_section != NULL
20139 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20140 )
20141 {
20142 for (i = elf_numsections (obfd); i-- > 0;)
20143 if (oheaders[i]->bfd_section
20144 == iheaders[isection->sh_link]->bfd_section->output_section)
20145 break;
20146 }
9eaff861 20147
5522f910
NC		 20148 if (i == 0)
20149 {
20150 /* Failing that we have to find a matching section ourselves. If
20151 we had the output section name available we could compare that
20152 with input section names. Unfortunately we don't. So instead
20153 we use a simple heuristic and look for the nearest executable
20154 section before this one. */
20155 for (i = elf_numsections (obfd); i-- > 0;)
20156 if (oheaders[i] == osection)
20157 break;
20158 if (i == 0)
20159 break;
20160
20161 while (i-- > 0)
20162 if (oheaders[i]->sh_type == SHT_PROGBITS
20163 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20164 == (SHF_ALLOC | SHF_EXECINSTR))
20165 break;
20166 }
20167
20168 if (i)
20169 {
20170 osection->sh_link = i;
20171 /* If the text section was part of a group
20172 then the index section should be too. */
20173 if (oheaders[i]->sh_flags & SHF_GROUP)
20174 osection->sh_flags |= SHF_GROUP;
20175 return TRUE;
20176 }
20177 }
20178 break;
20179
20180 case SHT_ARM_PREEMPTMAP:
20181 osection->sh_flags = SHF_ALLOC;
20182 break;
20183
20184 case SHT_ARM_ATTRIBUTES:
20185 case SHT_ARM_DEBUGOVERLAY:
20186 case SHT_ARM_OVERLAYSECTION:
20187 default:
20188 break;
20189 }
20190
20191 return FALSE;
20192}
20193
d691934d
NC		 20194/* Returns TRUE if NAME is an ARM mapping symbol.
20195 Traditionally the symbols $a, $d and $t have been used.
20196 The ARM ELF standard also defines $x (for A64 code). It also allows a
20197 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20198 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20199 not support them here. $t.x indicates the start of ThumbEE instructions. */
20200
20201static bfd_boolean
20202is_arm_mapping_symbol (const char * name)
20203{
20204 return name != NULL /* Paranoia. */
20205 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20206 the mapping symbols could have acquired a prefix.
20207 We do not support this here, since such symbols no
20208 longer conform to the ARM ELF ABI. */
20209 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20210 && (name[2] == 0 || name[2] == '.');
20211 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20212 any characters that follow the period are legal characters for the body
20213 of a symbol's name. For now we just assume that this is the case. */
20214}
20215
fca2a38f
NC		 20216/* Make sure that mapping symbols in object files are not removed via the
20217 "strip --strip-unneeded" tool. These symbols are needed in order to
20218 correctly generate interworking veneers, and for byte swapping code
20219 regions. Once an object file has been linked, it is safe to remove the
20220 symbols as they will no longer be needed. */
20221
20222static void
20223elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20224{
20225 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20226 && sym->section != bfd_abs_section_ptr
d691934d 20227 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20228 sym->flags |= BSF_KEEP;
20229}
20230
5522f910
NC		 20231#undef elf_backend_copy_special_section_fields
20232#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20233
252b5132 20234#define ELF_ARCH bfd_arch_arm
ae95ffa6 20235#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20236#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20237#ifdef __QNXTARGET__
20238#define ELF_MAXPAGESIZE 0x1000
20239#else
7572ca89 20240#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20241#endif
b1342370 20242#define ELF_MINPAGESIZE 0x1000
24718e3b 20243#define ELF_COMMONPAGESIZE 0x1000
252b5132 20244
07d6d2b8 20245#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20246
99e4ae17
AJ		 20247#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20248#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20249#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20250#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20251#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20252#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20253#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8 20254#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20255#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20256#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20257#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20258#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20259
07d6d2b8 20260#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
e7679060 20261#define elf_backend_maybe_function_sym elf32_arm_maybe_function_sym
07d6d2b8 20262#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20263#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20264#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20265#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20266#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20267#define elf_backend_write_section elf32_arm_write_section
252b5132 20268#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20269#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20270#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20271#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20272#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20273#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20274#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ed7e9d0b 20275#define elf_backend_init_file_header elf32_arm_init_file_header
99e4ae17 20276#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20277#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20278#define elf_backend_fake_sections elf32_arm_fake_sections
20279#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20280#define elf_backend_final_write_processing elf32_arm_final_write_processing
20281#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20282#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20283#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20284#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20285#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20286#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20287#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20288#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20289#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20290#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20291
20292#define elf_backend_can_refcount 1
20293#define elf_backend_can_gc_sections 1
20294#define elf_backend_plt_readonly 1
20295#define elf_backend_want_got_plt 1
20296#define elf_backend_want_plt_sym 0
5474d94f 20297#define elf_backend_want_dynrelro 1
906e58ca
NC		 20298#define elf_backend_may_use_rel_p 1
20299#define elf_backend_may_use_rela_p 0
4e7fd91e 20300#define elf_backend_default_use_rela_p 0
64f52338 20301#define elf_backend_dtrel_excludes_plt 1
252b5132 20302
04f7c78d 20303#define elf_backend_got_header_size 12
b68a20d6 20304#define elf_backend_extern_protected_data 1
04f7c78d 20305
07d6d2b8 20306#undef elf_backend_obj_attrs_vendor
906e58ca 20307#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20308#undef elf_backend_obj_attrs_section
906e58ca 20309#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20310#undef elf_backend_obj_attrs_arg_type
906e58ca 20311#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20312#undef elf_backend_obj_attrs_section_type
104d59d1 20313#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20314#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20315#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20316
07d6d2b8 20317#undef elf_backend_section_flags
ac4c9b04 20318#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20319#undef elf_backend_lookup_section_flags_hook
20320#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20321
a2f63b2e
MR		 20322#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20323
252b5132 20324#include "elf32-target.h"
7f266840 20325
b38cadfb
NC		 20326/* Native Client targets. */
20327
20328#undef TARGET_LITTLE_SYM
6d00b590 20329#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20330#undef TARGET_LITTLE_NAME
20331#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20332#undef TARGET_BIG_SYM
6d00b590 20333#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20334#undef TARGET_BIG_NAME
20335#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20336
20337/* Like elf32_arm_link_hash_table_create -- but overrides
20338 appropriately for NaCl. */
20339
20340static struct bfd_link_hash_table *
20341elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20342{
20343 struct bfd_link_hash_table *ret;
20344
20345 ret = elf32_arm_link_hash_table_create (abfd);
20346 if (ret)
20347 {
20348 struct elf32_arm_link_hash_table *htab
20349 = (struct elf32_arm_link_hash_table *) ret;
20350
b38cadfb
NC		 20351 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20352 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20353 }
20354 return ret;
20355}
20356
20357/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20358 really need to use elf32_arm_modify_segment_map. But we do it
20359 anyway just to reduce gratuitous differences with the stock ARM backend. */
20360
20361static bfd_boolean
20362elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20363{
20364 return (elf32_arm_modify_segment_map (abfd, info)
20365 && nacl_modify_segment_map (abfd, info));
20366}
20367
cc364be6
AM		 20368static bfd_boolean
20369elf32_arm_nacl_final_write_processing (bfd *abfd)
887badb3 20370{
cc364be6
AM		 20371 arm_final_write_processing (abfd);
20372 return nacl_final_write_processing (abfd);
887badb3
RM		 20373}
20374
6a631e86
YG		 20375static bfd_vma
20376elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20377 const arelent *rel ATTRIBUTE_UNUSED)
20378{
20379 return plt->vma
20380 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20381 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20382}
887badb3 20383
b38cadfb 20384#undef elf32_bed
6a631e86 20385#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20386#undef bfd_elf32_bfd_link_hash_table_create
20387#define bfd_elf32_bfd_link_hash_table_create \
20388 elf32_arm_nacl_link_hash_table_create
20389#undef elf_backend_plt_alignment
6a631e86 20390#define elf_backend_plt_alignment 4
b38cadfb
NC		 20391#undef elf_backend_modify_segment_map
20392#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
6d6c25c8
AM		 20393#undef elf_backend_modify_headers
20394#define elf_backend_modify_headers nacl_modify_headers
887badb3
RM		 20395#undef elf_backend_final_write_processing
20396#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20397#undef bfd_elf32_get_synthetic_symtab
20398#undef elf_backend_plt_sym_val
20399#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20400#undef elf_backend_copy_special_section_fields
b38cadfb 20401
887badb3
RM		 20402#undef ELF_MINPAGESIZE
20403#undef ELF_COMMONPAGESIZE
20404
90c14f0c
L		 20405#undef ELF_TARGET_OS
20406#define ELF_TARGET_OS is_nacl
b38cadfb
NC		 20407
20408#include "elf32-target.h"
20409
20410/* Reset to defaults. */
20411#undef elf_backend_plt_alignment
20412#undef elf_backend_modify_segment_map
20413#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
6d6c25c8 20414#undef elf_backend_modify_headers
887badb3
RM		 20415#undef elf_backend_final_write_processing
20416#define elf_backend_final_write_processing elf32_arm_final_write_processing
20417#undef ELF_MINPAGESIZE
20418#define ELF_MINPAGESIZE 0x1000
20419#undef ELF_COMMONPAGESIZE
20420#define ELF_COMMONPAGESIZE 0x1000
20421
b38cadfb 20422
617a5ada
CL		 20423/* FDPIC Targets. */
20424
20425#undef TARGET_LITTLE_SYM
20426#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20427#undef TARGET_LITTLE_NAME
20428#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20429#undef TARGET_BIG_SYM
20430#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20431#undef TARGET_BIG_NAME
20432#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20433#undef elf_match_priority
20434#define elf_match_priority 128
18a20338
CL		 20435#undef ELF_OSABI
20436#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20437
20438/* Like elf32_arm_link_hash_table_create -- but overrides
20439 appropriately for FDPIC. */
20440
20441static struct bfd_link_hash_table *
20442elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20443{
20444 struct bfd_link_hash_table *ret;
20445
20446 ret = elf32_arm_link_hash_table_create (abfd);
20447 if (ret)
20448 {
20449 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20450
20451 htab->fdpic_p = 1;
20452 }
20453 return ret;
20454}
20455
e8b09b87
CL		 20456/* We need dynamic symbols for every section, since segments can
20457 relocate independently. */
20458static bfd_boolean
20459elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20460 struct bfd_link_info *info
20461 ATTRIBUTE_UNUSED,
20462 asection *p ATTRIBUTE_UNUSED)
20463{
20464 switch (elf_section_data (p)->this_hdr.sh_type)
20465 {
20466 case SHT_PROGBITS:
20467 case SHT_NOBITS:
20468 /* If sh_type is yet undecided, assume it could be
20469 SHT_PROGBITS/SHT_NOBITS. */
20470 case SHT_NULL:
20471 return FALSE;
20472
20473 /* There shouldn't be section relative relocations
20474 against any other section. */
20475 default:
20476 return TRUE;
20477 }
20478}
20479
617a5ada
CL		 20480#undef elf32_bed
20481#define elf32_bed elf32_arm_fdpic_bed
20482
20483#undef bfd_elf32_bfd_link_hash_table_create
4b24dd1a 20484#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
617a5ada 20485
e8b09b87
CL		 20486#undef elf_backend_omit_section_dynsym
20487#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20488
90c14f0c
L		 20489#undef ELF_TARGET_OS
20490
617a5ada 20491#include "elf32-target.h"
e8b09b87 20492
617a5ada 20493#undef elf_match_priority
18a20338 20494#undef ELF_OSABI
e8b09b87 20495#undef elf_backend_omit_section_dynsym
617a5ada 20496
906e58ca 20497/* VxWorks Targets. */
4e7fd91e 20498
07d6d2b8
AM		 20499#undef TARGET_LITTLE_SYM
20500#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20501#undef TARGET_LITTLE_NAME
20502#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20503#undef TARGET_BIG_SYM
20504#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20505#undef TARGET_BIG_NAME
20506#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20507
20508/* Like elf32_arm_link_hash_table_create -- but overrides
20509 appropriately for VxWorks. */
906e58ca 20510
4e7fd91e
PB		 20511static struct bfd_link_hash_table *
20512elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20513{
20514 struct bfd_link_hash_table *ret;
20515
20516 ret = elf32_arm_link_hash_table_create (abfd);
20517 if (ret)
20518 {
20519 struct elf32_arm_link_hash_table *htab
00a97672 20520 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e
PB		 20521 htab->use_rel = 0;
20522 }
20523 return ret;
906e58ca 20524}
4e7fd91e 20525
cc364be6
AM		 20526static bfd_boolean
20527elf32_arm_vxworks_final_write_processing (bfd *abfd)
00a97672 20528{
cc364be6
AM		 20529 arm_final_write_processing (abfd);
20530 return elf_vxworks_final_write_processing (abfd);
00a97672
RS		 20531}
20532
906e58ca 20533#undef elf32_bed
4e7fd91e
PB		 20534#define elf32_bed elf32_arm_vxworks_bed
20535
906e58ca
NC		 20536#undef bfd_elf32_bfd_link_hash_table_create
20537#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20538#undef elf_backend_final_write_processing
20539#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20540#undef elf_backend_emit_relocs
9eaff861 20541#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20542
906e58ca 20543#undef elf_backend_may_use_rel_p
00a97672 20544#define elf_backend_may_use_rel_p 0
906e58ca 20545#undef elf_backend_may_use_rela_p
00a97672 20546#define elf_backend_may_use_rela_p 1
906e58ca 20547#undef elf_backend_default_use_rela_p
00a97672 20548#define elf_backend_default_use_rela_p 1
906e58ca 20549#undef elf_backend_want_plt_sym
00a97672 20550#define elf_backend_want_plt_sym 1
906e58ca 20551#undef ELF_MAXPAGESIZE
00a97672 20552#define ELF_MAXPAGESIZE 0x1000
90c14f0c
L		 20553#undef ELF_TARGET_OS
20554#define ELF_TARGET_OS is_vxworks
4e7fd91e
PB		 20555
20556#include "elf32-target.h"
20557
20558
21d799b5
NC		 20559/* Merge backend specific data from an object file to the output
20560 object file when linking. */
20561
20562static bfd_boolean
50e03d47 20563elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20564{
50e03d47 20565 bfd *obfd = info->output_bfd;
21d799b5
NC		 20566 flagword out_flags;
20567 flagword in_flags;
20568 bfd_boolean flags_compatible = TRUE;
20569 asection *sec;
20570
cc643b88 20571 /* Check if we have the same endianness. */
50e03d47 20572 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20573 return FALSE;
20574
20575 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20576 return TRUE;
20577
50e03d47 20578 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20579 return FALSE;
20580
20581 /* The input BFD must have had its flags initialised. */
20582 /* The following seems bogus to me -- The flags are initialized in
20583 the assembler but I don't think an elf_flags_init field is
20584 written into the object. */
20585 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20586
20587 in_flags = elf_elfheader (ibfd)->e_flags;
20588 out_flags = elf_elfheader (obfd)->e_flags;
20589
20590 /* In theory there is no reason why we couldn't handle this. However
20591 in practice it isn't even close to working and there is no real
20592 reason to want it. */
20593 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20594 && !(ibfd->flags & DYNAMIC)
20595 && (in_flags & EF_ARM_BE8))
20596 {
871b3ab2 20597 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20598 ibfd);
20599 return FALSE;
20600 }
20601
20602 if (!elf_flags_init (obfd))
20603 {
20604 /* If the input is the default architecture and had the default
20605 flags then do not bother setting the flags for the output
20606 architecture, instead allow future merges to do this. If no
20607 future merges ever set these flags then they will retain their
99059e56
RM		 20608 uninitialised values, which surprise surprise, correspond
20609 to the default values. */
21d799b5
NC		 20610 if (bfd_get_arch_info (ibfd)->the_default
20611 && elf_elfheader (ibfd)->e_flags == 0)
20612 return TRUE;
20613
20614 elf_flags_init (obfd) = TRUE;
20615 elf_elfheader (obfd)->e_flags = in_flags;
20616
20617 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20618 && bfd_get_arch_info (obfd)->the_default)
20619 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20620
20621 return TRUE;
20622 }
20623
20624 /* Determine what should happen if the input ARM architecture
20625 does not match the output ARM architecture. */
20626 if (! bfd_arm_merge_machines (ibfd, obfd))
20627 return FALSE;
20628
20629 /* Identical flags must be compatible. */
20630 if (in_flags == out_flags)
20631 return TRUE;
20632
20633 /* Check to see if the input BFD actually contains any sections. If
20634 not, its flags may not have been initialised either, but it
20635 cannot actually cause any incompatiblity. Do not short-circuit
20636 dynamic objects; their section list may be emptied by
20637 elf_link_add_object_symbols.
20638
20639 Also check to see if there are no code sections in the input.
20640 In this case there is no need to check for code specific flags.
20641 XXX - do we need to worry about floating-point format compatability
20642 in data sections ? */
20643 if (!(ibfd->flags & DYNAMIC))
20644 {
20645 bfd_boolean null_input_bfd = TRUE;
20646 bfd_boolean only_data_sections = TRUE;
20647
20648 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20649 {
20650 /* Ignore synthetic glue sections. */
20651 if (strcmp (sec->name, ".glue_7")
20652 && strcmp (sec->name, ".glue_7t"))
20653 {
fd361982 20654 if ((bfd_section_flags (sec)
21d799b5
NC		 20655 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20656 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20657 only_data_sections = FALSE;
21d799b5
NC		 20658
20659 null_input_bfd = FALSE;
20660 break;
20661 }
20662 }
20663
20664 if (null_input_bfd || only_data_sections)
20665 return TRUE;
20666 }
20667
20668 /* Complain about various flag mismatches. */
20669 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20670 EF_ARM_EABI_VERSION (out_flags)))
20671 {
20672 _bfd_error_handler
90b6238f 20673 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20674 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20675 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20676 return FALSE;
20677 }
20678
20679 /* Not sure what needs to be checked for EABI versions >= 1. */
20680 /* VxWorks libraries do not use these flags. */
20681 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20682 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20683 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20684 {
20685 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20686 {
20687 _bfd_error_handler
871b3ab2 20688 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20689 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20690 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20691 flags_compatible = FALSE;
20692 }
20693
20694 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20695 {
20696 if (in_flags & EF_ARM_APCS_FLOAT)
20697 _bfd_error_handler
871b3ab2 20698 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20699 ibfd, obfd);
20700 else
20701 _bfd_error_handler
871b3ab2 20702 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20703 ibfd, obfd);
20704
20705 flags_compatible = FALSE;
20706 }
20707
20708 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20709 {
20710 if (in_flags & EF_ARM_VFP_FLOAT)
20711 _bfd_error_handler
90b6238f
AM		 20712 (_("error: %pB uses %s instructions, whereas %pB does not"),
20713 ibfd, "VFP", obfd);
21d799b5
NC		 20714 else
20715 _bfd_error_handler
90b6238f
AM		 20716 (_("error: %pB uses %s instructions, whereas %pB does not"),
20717 ibfd, "FPA", obfd);
21d799b5
NC		 20718
20719 flags_compatible = FALSE;
20720 }
20721
20722 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20723 {
20724 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20725 _bfd_error_handler
90b6238f
AM		 20726 (_("error: %pB uses %s instructions, whereas %pB does not"),
20727 ibfd, "Maverick", obfd);
21d799b5
NC		 20728 else
20729 _bfd_error_handler
90b6238f
AM		 20730 (_("error: %pB does not use %s instructions, whereas %pB does"),
20731 ibfd, "Maverick", obfd);
21d799b5
NC		 20732
20733 flags_compatible = FALSE;
20734 }
20735
20736#ifdef EF_ARM_SOFT_FLOAT
20737 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20738 {
20739 /* We can allow interworking between code that is VFP format
20740 layout, and uses either soft float or integer regs for
20741 passing floating point arguments and results. We already
20742 know that the APCS_FLOAT flags match; similarly for VFP
20743 flags. */
20744 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20745 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20746 {
20747 if (in_flags & EF_ARM_SOFT_FLOAT)
20748 _bfd_error_handler
871b3ab2 20749 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20750 ibfd, obfd);
20751 else
20752 _bfd_error_handler
871b3ab2 20753 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20754 ibfd, obfd);
20755
20756 flags_compatible = FALSE;
20757 }
20758 }
20759#endif
20760
20761 /* Interworking mismatch is only a warning. */
20762 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20763 {
20764 if (in_flags & EF_ARM_INTERWORK)
20765 {
20766 _bfd_error_handler
90b6238f 20767 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 20768 ibfd, obfd);
20769 }
20770 else
20771 {
20772 _bfd_error_handler
90b6238f 20773 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 20774 ibfd, obfd);
20775 }
20776 }
20777 }
20778
20779 return flags_compatible;
20780}
20781
20782
906e58ca 20783/* Symbian OS Targets. */
7f266840 20784
07d6d2b8
AM		 20785#undef TARGET_LITTLE_SYM
20786#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
20787#undef TARGET_LITTLE_NAME
20788#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
20789#undef TARGET_BIG_SYM
20790#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
20791#undef TARGET_BIG_NAME
20792#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 20793
20794/* Like elf32_arm_link_hash_table_create -- but overrides
20795 appropriately for Symbian OS. */
906e58ca 20796
7f266840
DJ		 20797static struct bfd_link_hash_table *
20798elf32_arm_symbian_link_hash_table_create (bfd *abfd)
20799{
20800 struct bfd_link_hash_table *ret;
20801
20802 ret = elf32_arm_link_hash_table_create (abfd);
20803 if (ret)
20804 {
20805 struct elf32_arm_link_hash_table *htab
20806 = (struct elf32_arm_link_hash_table *)ret;
20807 /* There is no PLT header for Symbian OS. */
20808 htab->plt_header_size = 0;
95720a86
DJ		 20809 /* The PLT entries are each one instruction and one word. */
20810 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
33bfe774
JB		 20811 /* Symbian uses armv5t or above, so use_blx is always true. */
20812 htab->use_blx = 1;
67687978 20813 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 20814 }
20815 return ret;
906e58ca 20816}
7f266840 20817
b35d266b 20818static const struct bfd_elf_special_section
551b43fd 20819elf32_arm_symbian_special_sections[] =
7f266840 20820{
5cd3778d
MM		 20821 /* In a BPABI executable, the dynamic linking sections do not go in
20822 the loadable read-only segment. The post-linker may wish to
20823 refer to these sections, but they are not part of the final
20824 program image. */
07d6d2b8
AM		 20825 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
20826 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
20827 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
20828 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
20829 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 20830 /* These sections do not need to be writable as the SymbianOS
20831 postlinker will arrange things so that no dynamic relocation is
20832 required. */
07d6d2b8
AM		 20833 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
20834 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 20835 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 20836 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 20837};
20838
c3c76620 20839static void
906e58ca 20840elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 20841 struct bfd_link_info *link_info)
c3c76620
MM		 20842{
20843 /* BPABI objects are never loaded directly by an OS kernel; they are
20844 processed by a postlinker first, into an OS-specific format. If
20845 the D_PAGED bit is set on the file, BFD will align segments on
20846 page boundaries, so that an OS can directly map the file. With
20847 BPABI objects, that just results in wasted space. In addition,
20848 because we clear the D_PAGED bit, map_sections_to_segments will
20849 recognize that the program headers should not be mapped into any
20850 loadable segment. */
20851 abfd->flags &= ~D_PAGED;
906e58ca 20852 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 20853}
7f266840
DJ		 20854
20855static bfd_boolean
906e58ca 20856elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 20857 struct bfd_link_info *info)
7f266840
DJ		 20858{
20859 struct elf_segment_map *m;
20860 asection *dynsec;
20861
7f266840
DJ		 20862 /* BPABI shared libraries and executables should have a PT_DYNAMIC
20863 segment. However, because the .dynamic section is not marked
20864 with SEC_LOAD, the generic ELF code will not create such a
20865 segment. */
20866 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
20867 if (dynsec)
20868 {
12bd6957 20869 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 20870 if (m->p_type == PT_DYNAMIC)
20871 break;
20872
20873 if (m == NULL)
20874 {
20875 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 20876 m->next = elf_seg_map (abfd);
20877 elf_seg_map (abfd) = m;
8ded5a0f 20878 }
7f266840
DJ		 20879 }
20880
b294bdf8
MM		 20881 /* Also call the generic arm routine. */
20882 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 20883}
20884
95720a86
DJ		 20885/* Return address for Ith PLT stub in section PLT, for relocation REL
20886 or (bfd_vma) -1 if it should not be included. */
20887
20888static bfd_vma
20889elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
20890 const arelent *rel ATTRIBUTE_UNUSED)
20891{
20892 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
20893}
20894
8029a119 20895#undef elf32_bed
7f266840
DJ		 20896#define elf32_bed elf32_arm_symbian_bed
20897
20898/* The dynamic sections are not allocated on SymbianOS; the postlinker
20899 will process them and then discard them. */
906e58ca 20900#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 20901#define ELF_DYNAMIC_SEC_FLAGS \
20902 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
20903
9eaff861 20904#undef elf_backend_emit_relocs
c3c76620 20905
906e58ca
NC		 20906#undef bfd_elf32_bfd_link_hash_table_create
20907#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
20908#undef elf_backend_special_sections
07d6d2b8 20909#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 20910#undef elf_backend_begin_write_processing
20911#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
20912#undef elf_backend_final_write_processing
20913#define elf_backend_final_write_processing elf32_arm_final_write_processing
20914
20915#undef elf_backend_modify_segment_map
7f266840
DJ		 20916#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
20917
20918/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 20919#undef elf_backend_got_header_size
7f266840
DJ		 20920#define elf_backend_got_header_size 0
20921
20922/* Similarly, there is no .got.plt section. */
906e58ca 20923#undef elf_backend_want_got_plt
7f266840
DJ		 20924#define elf_backend_want_got_plt 0
20925
906e58ca 20926#undef elf_backend_plt_sym_val
95720a86
DJ		 20927#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
20928
906e58ca 20929#undef elf_backend_may_use_rel_p
00a97672 20930#define elf_backend_may_use_rel_p 1
906e58ca 20931#undef elf_backend_may_use_rela_p
00a97672 20932#define elf_backend_may_use_rela_p 0
906e58ca 20933#undef elf_backend_default_use_rela_p
00a97672 20934#define elf_backend_default_use_rela_p 0
906e58ca 20935#undef elf_backend_want_plt_sym
00a97672 20936#define elf_backend_want_plt_sym 0
64f52338
AM		 20937#undef elf_backend_dtrel_excludes_plt
20938#define elf_backend_dtrel_excludes_plt 0
906e58ca 20939#undef ELF_MAXPAGESIZE
00a97672 20940#define ELF_MAXPAGESIZE 0x8000
90c14f0c
L		 20941#undef ELF_TARGET_OS
20942#define ELF_TARGET_OS is_symbian
4e7fd91e 20943
7f266840 20944#include "elf32-target.h"
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