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[thirdparty/binutils-gdb.git] / bfd / elf32-msp430.c
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2469cfa2 1/* MSP430-specific support for 32-bit ELF
b3adc24a 2 Copyright (C) 2002-2020 Free Software Foundation, Inc.
2469cfa2
NC		 3 Contributed by Dmitry Diky <diwil@mail.ru>
4
5 This file is part of BFD, the Binary File Descriptor library.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
cd123cb7 9 the Free Software Foundation; either version 3 of the License, or
2469cfa2
NC		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
cd123cb7
NC		 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
2469cfa2 21
2469cfa2 22#include "sysdep.h"
3db64b00 23#include "bfd.h"
2469cfa2
NC		 24#include "libiberty.h"
25#include "libbfd.h"
26#include "elf-bfd.h"
27#include "elf/msp430.h"
28
bb294208
AM		 29/* All users of this file have bfd_octets_per_byte (abfd, sec) == 1. */
30#define OCTETS_PER_BYTE(ABFD, SEC) 1
31
1ade7175
NC		 32static bfd_reloc_status_type
33rl78_sym_diff_handler (bfd * abfd,
34 arelent * reloc,
35 asymbol * sym ATTRIBUTE_UNUSED,
36 void * addr ATTRIBUTE_UNUSED,
37 asection * input_sec,
38 bfd * out_bfd ATTRIBUTE_UNUSED,
39 char ** error_message ATTRIBUTE_UNUSED)
40{
41 bfd_size_type octets;
bb294208 42 octets = reloc->address * OCTETS_PER_BYTE (abfd, input_sec);
1ade7175
NC		 43
44 /* Catch the case where bfd_install_relocation would return
45 bfd_reloc_outofrange because the SYM_DIFF reloc is being used in a very
46 small section. It does not actually matter if this happens because all
47 that SYM_DIFF does is compute a (4-byte) value. A second reloc then uses
48 this value, and it is that reloc that must fit into the section.
49
50 This happens in eg, gcc/testsuite/gcc.c-torture/compile/labels-3.c. */
51 if ((octets + bfd_get_reloc_size (reloc->howto))
52 > bfd_get_section_limit_octets (abfd, input_sec))
53 return bfd_reloc_ok;
54 return bfd_reloc_continue;
55}
56
2469cfa2
NC		 57static reloc_howto_type elf_msp430_howto_table[] =
58{
59 HOWTO (R_MSP430_NONE, /* type */
60 0, /* rightshift */
6346d5ca
AM		 61 3, /* size (0 = byte, 1 = short, 2 = long) */
62 0, /* bitsize */
2469cfa2
NC		 63 FALSE, /* pc_relative */
64 0, /* bitpos */
6346d5ca 65 complain_overflow_dont,/* complain_on_overflow */
2469cfa2
NC		 66 bfd_elf_generic_reloc, /* special_function */
67 "R_MSP430_NONE", /* name */
68 FALSE, /* partial_inplace */
69 0, /* src_mask */
70 0, /* dst_mask */
71 FALSE), /* pcrel_offset */
72
73 HOWTO (R_MSP430_32, /* type */
74 0, /* rightshift */
75 2, /* size (0 = byte, 1 = short, 2 = long) */
76 32, /* bitsize */
77 FALSE, /* pc_relative */
78 0, /* bitpos */
b18c562e 79 complain_overflow_bitfield,/* complain_on_overflow */
2469cfa2
NC		 80 bfd_elf_generic_reloc, /* special_function */
81 "R_MSP430_32", /* name */
82 FALSE, /* partial_inplace */
83 0xffffffff, /* src_mask */
84 0xffffffff, /* dst_mask */
85 FALSE), /* pcrel_offset */
86
df301bfc 87 /* A 10 bit PC relative relocation. */
2469cfa2
NC		 88 HOWTO (R_MSP430_10_PCREL, /* type */
89 1, /* rightshift */
90 1, /* size (0 = byte, 1 = short, 2 = long) */
91 10, /* bitsize */
92 TRUE, /* pc_relative */
93 0, /* bitpos */
b18c562e 94 complain_overflow_bitfield,/* complain_on_overflow */
2469cfa2 95 bfd_elf_generic_reloc, /* special_function */
13761a11 96 "R_MSP430_10_PCREL", /* name */
2469cfa2 97 FALSE, /* partial_inplace */
df301bfc
NC		 98 0x3ff, /* src_mask */
99 0x3ff, /* dst_mask */
2469cfa2
NC		 100 TRUE), /* pcrel_offset */
101
102 /* A 16 bit absolute relocation. */
103 HOWTO (R_MSP430_16, /* type */
104 0, /* rightshift */
105 1, /* size (0 = byte, 1 = short, 2 = long) */
106 16, /* bitsize */
107 FALSE, /* pc_relative */
108 0, /* bitpos */
109 complain_overflow_dont,/* complain_on_overflow */
110 bfd_elf_generic_reloc, /* special_function */
111 "R_MSP430_16", /* name */
112 FALSE, /* partial_inplace */
b18c562e 113 0, /* src_mask */
2469cfa2
NC		 114 0xffff, /* dst_mask */
115 FALSE), /* pcrel_offset */
116
13761a11 117 /* A 16 bit PC relative relocation for command address. */
2469cfa2
NC		 118 HOWTO (R_MSP430_16_PCREL, /* type */
119 1, /* rightshift */
120 1, /* size (0 = byte, 1 = short, 2 = long) */
121 16, /* bitsize */
122 TRUE, /* pc_relative */
123 0, /* bitpos */
124 complain_overflow_dont,/* complain_on_overflow */
125 bfd_elf_generic_reloc, /* special_function */
126 "R_MSP430_16_PCREL", /* name */
127 FALSE, /* partial_inplace */
b18c562e 128 0, /* src_mask */
2469cfa2
NC		 129 0xffff, /* dst_mask */
130 TRUE), /* pcrel_offset */
131
132 /* A 16 bit absolute relocation, byte operations. */
133 HOWTO (R_MSP430_16_BYTE, /* type */
134 0, /* rightshift */
135 1, /* size (0 = byte, 1 = short, 2 = long) */
136 16, /* bitsize */
137 FALSE, /* pc_relative */
138 0, /* bitpos */
139 complain_overflow_dont,/* complain_on_overflow */
140 bfd_elf_generic_reloc, /* special_function */
141 "R_MSP430_16_BYTE", /* name */
142 FALSE, /* partial_inplace */
143 0xffff, /* src_mask */
144 0xffff, /* dst_mask */
145 FALSE), /* pcrel_offset */
146
147 /* A 16 bit absolute relocation for command address. */
148 HOWTO (R_MSP430_16_PCREL_BYTE,/* type */
149 1, /* rightshift */
150 1, /* size (0 = byte, 1 = short, 2 = long) */
151 16, /* bitsize */
152 TRUE, /* pc_relative */
153 0, /* bitpos */
154 complain_overflow_dont,/* complain_on_overflow */
155 bfd_elf_generic_reloc, /* special_function */
b18c562e 156 "R_MSP430_16_PCREL_BYTE",/* name */
2469cfa2
NC		 157 FALSE, /* partial_inplace */
158 0xffff, /* src_mask */
159 0xffff, /* dst_mask */
b18c562e
NC		 160 TRUE), /* pcrel_offset */
161
df301bfc 162 /* A 10 bit PC relative relocation for complicated polymorphs. */
b18c562e
NC		 163 HOWTO (R_MSP430_2X_PCREL, /* type */
164 1, /* rightshift */
165 2, /* size (0 = byte, 1 = short, 2 = long) */
166 10, /* bitsize */
167 TRUE, /* pc_relative */
168 0, /* bitpos */
169 complain_overflow_bitfield,/* complain_on_overflow */
170 bfd_elf_generic_reloc, /* special_function */
171 "R_MSP430_2X_PCREL", /* name */
172 FALSE, /* partial_inplace */
df301bfc
NC		 173 0x3ff, /* src_mask */
174 0x3ff, /* dst_mask */
b18c562e
NC		 175 TRUE), /* pcrel_offset */
176
177 /* A 16 bit relaxable relocation for command address. */
178 HOWTO (R_MSP430_RL_PCREL, /* type */
179 1, /* rightshift */
180 1, /* size (0 = byte, 1 = short, 2 = long) */
181 16, /* bitsize */
182 TRUE, /* pc_relative */
183 0, /* bitpos */
184 complain_overflow_dont,/* complain_on_overflow */
185 bfd_elf_generic_reloc, /* special_function */
186 "R_MSP430_RL_PCREL", /* name */
187 FALSE, /* partial_inplace */
188 0, /* src_mask */
189 0xffff, /* dst_mask */
2469cfa2 190 TRUE) /* pcrel_offset */
13761a11
NC		 191
192 /* A 8-bit absolute relocation. */
193 , HOWTO (R_MSP430_8, /* type */
194 0, /* rightshift */
195 0, /* size (0 = byte, 1 = short, 2 = long) */
196 8, /* bitsize */
197 FALSE, /* pc_relative */
198 0, /* bitpos */
199 complain_overflow_dont,/* complain_on_overflow */
200 bfd_elf_generic_reloc, /* special_function */
201 "R_MSP430_8", /* name */
202 FALSE, /* partial_inplace */
203 0, /* src_mask */
204 0xffff, /* dst_mask */
205 FALSE), /* pcrel_offset */
206
207 /* Together with a following reloc, allows for the difference
208 between two symbols to be the real addend of the second reloc. */
209 HOWTO (R_MSP430_SYM_DIFF, /* type */
210 0, /* rightshift */
211 2, /* size (0 = byte, 1 = short, 2 = long) */
212 32, /* bitsize */
213 FALSE, /* pc_relative */
214 0, /* bitpos */
215 complain_overflow_dont,/* complain_on_overflow */
1ade7175 216 rl78_sym_diff_handler, /* special handler. */
13761a11
NC		 217 "R_MSP430_SYM_DIFF", /* name */
218 FALSE, /* partial_inplace */
219 0xffffffff, /* src_mask */
220 0xffffffff, /* dst_mask */
1b786873 221 FALSE) /* pcrel_offset */
13761a11
NC		 222};
223
224static reloc_howto_type elf_msp430x_howto_table[] =
225{
226 HOWTO (R_MSP430_NONE, /* type */
227 0, /* rightshift */
6346d5ca
AM		 228 3, /* size (0 = byte, 1 = short, 2 = long) */
229 0, /* bitsize */
13761a11
NC		 230 FALSE, /* pc_relative */
231 0, /* bitpos */
6346d5ca 232 complain_overflow_dont,/* complain_on_overflow */
13761a11
NC		 233 bfd_elf_generic_reloc, /* special_function */
234 "R_MSP430_NONE", /* name */
235 FALSE, /* partial_inplace */
236 0, /* src_mask */
237 0, /* dst_mask */
238 FALSE), /* pcrel_offset */
239
240 HOWTO (R_MSP430_ABS32, /* type */
241 0, /* rightshift */
242 2, /* size (0 = byte, 1 = short, 2 = long) */
243 32, /* bitsize */
244 FALSE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_bitfield,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_MSP430_ABS32", /* name */
249 FALSE, /* partial_inplace */
250 0xffffffff, /* src_mask */
251 0xffffffff, /* dst_mask */
252 FALSE), /* pcrel_offset */
253
254 HOWTO (R_MSP430_ABS16, /* type */
255 0, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
257 16, /* bitsize */
258 FALSE, /* pc_relative */
259 0, /* bitpos */
260 complain_overflow_dont,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
262 "R_MSP430_ABS16", /* name */
263 FALSE, /* partial_inplace */
264 0, /* src_mask */
265 0xffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
267
268 HOWTO (R_MSP430_ABS8, /* type */
269 0, /* rightshift */
270 0, /* size (0 = byte, 1 = short, 2 = long) */
271 8, /* bitsize */
272 FALSE, /* pc_relative */
273 0, /* bitpos */
274 complain_overflow_bitfield,/* complain_on_overflow */
275 bfd_elf_generic_reloc, /* special_function */
276 "R_MSP430_ABS8", /* name */
277 FALSE, /* partial_inplace */
278 0xff, /* src_mask */
279 0xff, /* dst_mask */
280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_MSP430_PCR16, /* type */
283 1, /* rightshift */
284 1, /* size (0 = byte, 1 = short, 2 = long) */
285 16, /* bitsize */
286 TRUE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_dont,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_MSP430_PCR16", /* name */
291 FALSE, /* partial_inplace */
292 0, /* src_mask */
293 0xffff, /* dst_mask */
294 TRUE), /* pcrel_offset */
295
296 HOWTO (R_MSP430X_PCR20_EXT_SRC,/* type */
297 0, /* rightshift */
298 2, /* size (0 = byte, 1 = short, 2 = long) */
299 32, /* bitsize */
300 TRUE, /* pc_relative */
301 0, /* bitpos */
302 complain_overflow_dont,/* complain_on_overflow */
303 bfd_elf_generic_reloc, /* special_function */
304 "R_MSP430X_PCR20_EXT_SRC",/* name */
305 FALSE, /* partial_inplace */
306 0, /* src_mask */
307 0xffff, /* dst_mask */
308 TRUE), /* pcrel_offset */
309
310 HOWTO (R_MSP430X_PCR20_EXT_DST,/* type */
311 0, /* rightshift */
312 2, /* size (0 = byte, 1 = short, 2 = long) */
313 32, /* bitsize */
314 TRUE, /* pc_relative */
315 0, /* bitpos */
316 complain_overflow_dont,/* complain_on_overflow */
317 bfd_elf_generic_reloc, /* special_function */
318 "R_MSP430X_PCR20_EXT_DST",/* name */
319 FALSE, /* partial_inplace */
320 0, /* src_mask */
321 0xffff, /* dst_mask */
322 TRUE), /* pcrel_offset */
323
324 HOWTO (R_MSP430X_PCR20_EXT_ODST,/* type */
325 0, /* rightshift */
326 2, /* size (0 = byte, 1 = short, 2 = long) */
327 32, /* bitsize */
328 TRUE, /* pc_relative */
329 0, /* bitpos */
330 complain_overflow_dont,/* complain_on_overflow */
331 bfd_elf_generic_reloc, /* special_function */
332 "R_MSP430X_PCR20_EXT_ODST",/* name */
333 FALSE, /* partial_inplace */
334 0, /* src_mask */
335 0xffff, /* dst_mask */
336 TRUE), /* pcrel_offset */
337
338 HOWTO (R_MSP430X_ABS20_EXT_SRC,/* type */
339 0, /* rightshift */
340 2, /* size (0 = byte, 1 = short, 2 = long) */
341 32, /* bitsize */
342 TRUE, /* pc_relative */
343 0, /* bitpos */
344 complain_overflow_dont,/* complain_on_overflow */
345 bfd_elf_generic_reloc, /* special_function */
346 "R_MSP430X_ABS20_EXT_SRC",/* name */
347 FALSE, /* partial_inplace */
348 0, /* src_mask */
349 0xffff, /* dst_mask */
350 TRUE), /* pcrel_offset */
351
352 HOWTO (R_MSP430X_ABS20_EXT_DST,/* type */
353 0, /* rightshift */
354 2, /* size (0 = byte, 1 = short, 2 = long) */
355 32, /* bitsize */
356 TRUE, /* pc_relative */
357 0, /* bitpos */
358 complain_overflow_dont,/* complain_on_overflow */
359 bfd_elf_generic_reloc, /* special_function */
360 "R_MSP430X_ABS20_EXT_DST",/* name */
361 FALSE, /* partial_inplace */
362 0, /* src_mask */
363 0xffff, /* dst_mask */
364 TRUE), /* pcrel_offset */
365
366 HOWTO (R_MSP430X_ABS20_EXT_ODST,/* type */
367 0, /* rightshift */
368 2, /* size (0 = byte, 1 = short, 2 = long) */
369 32, /* bitsize */
370 TRUE, /* pc_relative */
371 0, /* bitpos */
372 complain_overflow_dont,/* complain_on_overflow */
373 bfd_elf_generic_reloc, /* special_function */
374 "R_MSP430X_ABS20_EXT_ODST",/* name */
375 FALSE, /* partial_inplace */
376 0, /* src_mask */
377 0xffff, /* dst_mask */
378 TRUE), /* pcrel_offset */
379
380 HOWTO (R_MSP430X_ABS20_ADR_SRC,/* type */
381 0, /* rightshift */
382 2, /* size (0 = byte, 1 = short, 2 = long) */
383 32, /* bitsize */
384 TRUE, /* pc_relative */
385 0, /* bitpos */
386 complain_overflow_dont,/* complain_on_overflow */
387 bfd_elf_generic_reloc, /* special_function */
388 "R_MSP430X_ABS20_ADR_SRC",/* name */
389 FALSE, /* partial_inplace */
390 0, /* src_mask */
391 0xffff, /* dst_mask */
392 TRUE), /* pcrel_offset */
393
394 HOWTO (R_MSP430X_ABS20_ADR_DST,/* type */
395 0, /* rightshift */
396 2, /* size (0 = byte, 1 = short, 2 = long) */
397 32, /* bitsize */
398 TRUE, /* pc_relative */
399 0, /* bitpos */
400 complain_overflow_dont,/* complain_on_overflow */
401 bfd_elf_generic_reloc, /* special_function */
402 "R_MSP430X_ABS20_ADR_DST",/* name */
403 FALSE, /* partial_inplace */
404 0, /* src_mask */
405 0xffff, /* dst_mask */
406 TRUE), /* pcrel_offset */
407
408 HOWTO (R_MSP430X_PCR16, /* type */
409 0, /* rightshift */
410 2, /* size (0 = byte, 1 = short, 2 = long) */
411 32, /* bitsize */
412 TRUE, /* pc_relative */
413 0, /* bitpos */
414 complain_overflow_dont,/* complain_on_overflow */
415 bfd_elf_generic_reloc, /* special_function */
416 "R_MSP430X_PCR16", /* name */
417 FALSE, /* partial_inplace */
418 0, /* src_mask */
419 0xffff, /* dst_mask */
420 TRUE), /* pcrel_offset */
421
422 HOWTO (R_MSP430X_PCR20_CALL, /* type */
423 0, /* rightshift */
424 2, /* size (0 = byte, 1 = short, 2 = long) */
425 32, /* bitsize */
426 TRUE, /* pc_relative */
427 0, /* bitpos */
428 complain_overflow_dont,/* complain_on_overflow */
429 bfd_elf_generic_reloc, /* special_function */
430 "R_MSP430X_PCR20_CALL",/* name */
431 FALSE, /* partial_inplace */
432 0, /* src_mask */
433 0xffff, /* dst_mask */
434 TRUE), /* pcrel_offset */
435
436 HOWTO (R_MSP430X_ABS16, /* type */
437 0, /* rightshift */
438 2, /* size (0 = byte, 1 = short, 2 = long) */
439 32, /* bitsize */
440 TRUE, /* pc_relative */
441 0, /* bitpos */
442 complain_overflow_dont,/* complain_on_overflow */
443 bfd_elf_generic_reloc, /* special_function */
444 "R_MSP430X_ABS16", /* name */
445 FALSE, /* partial_inplace */
446 0, /* src_mask */
447 0xffff, /* dst_mask */
448 TRUE), /* pcrel_offset */
449
450 HOWTO (R_MSP430_ABS_HI16, /* type */
451 0, /* rightshift */
452 2, /* size (0 = byte, 1 = short, 2 = long) */
453 32, /* bitsize */
454 TRUE, /* pc_relative */
455 0, /* bitpos */
456 complain_overflow_dont,/* complain_on_overflow */
457 bfd_elf_generic_reloc, /* special_function */
458 "R_MSP430_ABS_HI16", /* name */
459 FALSE, /* partial_inplace */
460 0, /* src_mask */
461 0xffff, /* dst_mask */
462 TRUE), /* pcrel_offset */
463
464 HOWTO (R_MSP430_PREL31, /* type */
465 0, /* rightshift */
466 2, /* size (0 = byte, 1 = short, 2 = long) */
467 32, /* bitsize */
468 TRUE, /* pc_relative */
469 0, /* bitpos */
470 complain_overflow_dont,/* complain_on_overflow */
471 bfd_elf_generic_reloc, /* special_function */
472 "R_MSP430_PREL31", /* name */
473 FALSE, /* partial_inplace */
474 0, /* src_mask */
475 0xffff, /* dst_mask */
07d6d2b8 476 TRUE), /* pcrel_offset */
13761a11
NC		 477
478 EMPTY_HOWTO (R_MSP430_EHTYPE),
1b786873 479
df301bfc 480 /* A 10 bit PC relative relocation. */
13761a11
NC		 481 HOWTO (R_MSP430X_10_PCREL, /* type */
482 1, /* rightshift */
483 1, /* size (0 = byte, 1 = short, 2 = long) */
484 10, /* bitsize */
485 TRUE, /* pc_relative */
486 0, /* bitpos */
487 complain_overflow_bitfield,/* complain_on_overflow */
488 bfd_elf_generic_reloc, /* special_function */
489 "R_MSP430X_10_PCREL", /* name */
490 FALSE, /* partial_inplace */
df301bfc
NC		 491 0x3ff, /* src_mask */
492 0x3ff, /* dst_mask */
07d6d2b8 493 TRUE), /* pcrel_offset */
13761a11 494
df301bfc 495 /* A 10 bit PC relative relocation for complicated polymorphs. */
13761a11
NC		 496 HOWTO (R_MSP430X_2X_PCREL, /* type */
497 1, /* rightshift */
498 2, /* size (0 = byte, 1 = short, 2 = long) */
499 10, /* bitsize */
500 TRUE, /* pc_relative */
501 0, /* bitpos */
502 complain_overflow_bitfield,/* complain_on_overflow */
503 bfd_elf_generic_reloc, /* special_function */
504 "R_MSP430X_2X_PCREL", /* name */
505 FALSE, /* partial_inplace */
df301bfc
NC		 506 0x3ff, /* src_mask */
507 0x3ff, /* dst_mask */
13761a11
NC		 508 TRUE), /* pcrel_offset */
509
510 /* Together with a following reloc, allows for the difference
511 between two symbols to be the real addend of the second reloc. */
512 HOWTO (R_MSP430X_SYM_DIFF, /* type */
513 0, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 32, /* bitsize */
516 FALSE, /* pc_relative */
517 0, /* bitpos */
518 complain_overflow_dont,/* complain_on_overflow */
1ade7175 519 rl78_sym_diff_handler, /* special handler. */
13761a11
NC		 520 "R_MSP430X_SYM_DIFF", /* name */
521 FALSE, /* partial_inplace */
522 0xffffffff, /* src_mask */
523 0xffffffff, /* dst_mask */
1b786873 524 FALSE) /* pcrel_offset */
2469cfa2
NC		 525};
526
527/* Map BFD reloc types to MSP430 ELF reloc types. */
528
529struct msp430_reloc_map
530{
531 bfd_reloc_code_real_type bfd_reloc_val;
532 unsigned int elf_reloc_val;
533};
534
535static const struct msp430_reloc_map msp430_reloc_map[] =
13761a11 536{
07d6d2b8
AM		 537 {BFD_RELOC_NONE, R_MSP430_NONE},
538 {BFD_RELOC_32, R_MSP430_32},
539 {BFD_RELOC_MSP430_10_PCREL, R_MSP430_10_PCREL},
540 {BFD_RELOC_16, R_MSP430_16_BYTE},
541 {BFD_RELOC_MSP430_16_PCREL, R_MSP430_16_PCREL},
542 {BFD_RELOC_MSP430_16, R_MSP430_16},
13761a11 543 {BFD_RELOC_MSP430_16_PCREL_BYTE, R_MSP430_16_PCREL_BYTE},
07d6d2b8
AM		 544 {BFD_RELOC_MSP430_16_BYTE, R_MSP430_16_BYTE},
545 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430_2X_PCREL},
546 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430_RL_PCREL},
547 {BFD_RELOC_8, R_MSP430_8},
548 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430_SYM_DIFF}
13761a11
NC		 549};
550
551static const struct msp430_reloc_map msp430x_reloc_map[] =
552{
07d6d2b8
AM		 553 {BFD_RELOC_NONE, R_MSP430_NONE},
554 {BFD_RELOC_32, R_MSP430_ABS32},
555 {BFD_RELOC_16, R_MSP430_ABS16},
556 {BFD_RELOC_8, R_MSP430_ABS8},
557 {BFD_RELOC_MSP430_ABS8, R_MSP430_ABS8},
13761a11
NC		 558 {BFD_RELOC_MSP430X_PCR20_EXT_SRC, R_MSP430X_PCR20_EXT_SRC},
559 {BFD_RELOC_MSP430X_PCR20_EXT_DST, R_MSP430X_PCR20_EXT_DST},
560 {BFD_RELOC_MSP430X_PCR20_EXT_ODST, R_MSP430X_PCR20_EXT_ODST},
561 {BFD_RELOC_MSP430X_ABS20_EXT_SRC, R_MSP430X_ABS20_EXT_SRC},
562 {BFD_RELOC_MSP430X_ABS20_EXT_DST, R_MSP430X_ABS20_EXT_DST},
563 {BFD_RELOC_MSP430X_ABS20_EXT_ODST, R_MSP430X_ABS20_EXT_ODST},
564 {BFD_RELOC_MSP430X_ABS20_ADR_SRC, R_MSP430X_ABS20_ADR_SRC},
565 {BFD_RELOC_MSP430X_ABS20_ADR_DST, R_MSP430X_ABS20_ADR_DST},
07d6d2b8 566 {BFD_RELOC_MSP430X_PCR16, R_MSP430X_PCR16},
13761a11 567 {BFD_RELOC_MSP430X_PCR20_CALL, R_MSP430X_PCR20_CALL},
07d6d2b8
AM		 568 {BFD_RELOC_MSP430X_ABS16, R_MSP430X_ABS16},
569 {BFD_RELOC_MSP430_ABS_HI16, R_MSP430_ABS_HI16},
570 {BFD_RELOC_MSP430_PREL31, R_MSP430_PREL31},
571 {BFD_RELOC_MSP430_10_PCREL, R_MSP430X_10_PCREL},
572 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430X_2X_PCREL},
573 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430X_PCR16},
574 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430X_SYM_DIFF}
13761a11
NC		 575};
576
577static inline bfd_boolean
578uses_msp430x_relocs (bfd * abfd)
579{
6d00b590 580 extern const bfd_target msp430_elf32_ti_vec;
13761a11
NC		 581
582 return bfd_get_mach (abfd) == bfd_mach_msp430x
6d00b590 583 || abfd->xvec == & msp430_elf32_ti_vec;
13761a11 584}
2469cfa2
NC		 585
586static reloc_howto_type *
b18c562e
NC		 587bfd_elf32_bfd_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
588 bfd_reloc_code_real_type code)
2469cfa2
NC		 589{
590 unsigned int i;
591
13761a11
NC		 592 if (uses_msp430x_relocs (abfd))
593 {
594 for (i = ARRAY_SIZE (msp430x_reloc_map); i--;)
595 if (msp430x_reloc_map[i].bfd_reloc_val == code)
596 return elf_msp430x_howto_table + msp430x_reloc_map[i].elf_reloc_val;
597 }
598 else
599 {
600 for (i = 0; i < ARRAY_SIZE (msp430_reloc_map); i++)
601 if (msp430_reloc_map[i].bfd_reloc_val == code)
602 return &elf_msp430_howto_table[msp430_reloc_map[i].elf_reloc_val];
603 }
2469cfa2
NC		 604
605 return NULL;
606}
607
157090f7
AM		 608static reloc_howto_type *
609bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
610 const char *r_name)
611{
612 unsigned int i;
613
13761a11
NC		 614 if (uses_msp430x_relocs (abfd))
615 {
616 for (i = ARRAY_SIZE (elf_msp430x_howto_table); i--;)
617 if (elf_msp430x_howto_table[i].name != NULL
618 && strcasecmp (elf_msp430x_howto_table[i].name, r_name) == 0)
619 return elf_msp430x_howto_table + i;
620 }
621 else
622 {
623 for (i = 0;
624 i < (sizeof (elf_msp430_howto_table)
625 / sizeof (elf_msp430_howto_table[0]));
626 i++)
627 if (elf_msp430_howto_table[i].name != NULL
628 && strcasecmp (elf_msp430_howto_table[i].name, r_name) == 0)
629 return &elf_msp430_howto_table[i];
630 }
157090f7
AM		 631
632 return NULL;
633}
634
2469cfa2
NC		 635/* Set the howto pointer for an MSP430 ELF reloc. */
636
f3185997 637static bfd_boolean
0aa13fee 638msp430_info_to_howto_rela (bfd * abfd,
b18c562e
NC		 639 arelent * cache_ptr,
640 Elf_Internal_Rela * dst)
2469cfa2
NC		 641{
642 unsigned int r_type;
643
644 r_type = ELF32_R_TYPE (dst->r_info);
13761a11
NC		 645
646 if (uses_msp430x_relocs (abfd))
647 {
5860e3f8
NC		 648 if (r_type >= (unsigned int) R_MSP430x_max)
649 {
695344c0 650 /* xgettext:c-format */
0aa13fee
AM		 651 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
652 abfd, r_type);
f3185997
NC		 653 bfd_set_error (bfd_error_bad_value);
654 return FALSE;
5860e3f8 655 }
13761a11 656 cache_ptr->howto = elf_msp430x_howto_table + r_type;
13761a11 657 }
f3185997 658 else if (r_type >= (unsigned int) R_MSP430_max)
5860e3f8 659 {
695344c0 660 /* xgettext:c-format */
0aa13fee
AM		 661 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
662 abfd, r_type);
f3185997
NC		 663 bfd_set_error (bfd_error_bad_value);
664 return FALSE;
5860e3f8 665 }
f3185997
NC		 666 else
667 cache_ptr->howto = &elf_msp430_howto_table[r_type];
668
669 return TRUE;
2469cfa2
NC		 670}
671
2469cfa2
NC		 672/* Look through the relocs for a section during the first phase.
673 Since we don't do .gots or .plts, we just need to consider the
674 virtual table relocs for gc. */
675
676static bfd_boolean
b18c562e
NC		 677elf32_msp430_check_relocs (bfd * abfd, struct bfd_link_info * info,
678 asection * sec, const Elf_Internal_Rela * relocs)
2469cfa2
NC		 679{
680 Elf_Internal_Shdr *symtab_hdr;
5582a088 681 struct elf_link_hash_entry **sym_hashes;
2469cfa2
NC		 682 const Elf_Internal_Rela *rel;
683 const Elf_Internal_Rela *rel_end;
684
0e1862bb 685 if (bfd_link_relocatable (info))
2469cfa2
NC		 686 return TRUE;
687
688 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
689 sym_hashes = elf_sym_hashes (abfd);
2469cfa2
NC		 690
691 rel_end = relocs + sec->reloc_count;
692 for (rel = relocs; rel < rel_end; rel++)
693 {
694 struct elf_link_hash_entry *h;
695 unsigned long r_symndx;
696
697 r_symndx = ELF32_R_SYM (rel->r_info);
698 if (r_symndx < symtab_hdr->sh_info)
699 h = NULL;
700 else
973a3492
L		 701 {
702 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
703 while (h->root.type == bfd_link_hash_indirect
704 || h->root.type == bfd_link_hash_warning)
705 h = (struct elf_link_hash_entry *) h->root.u.i.link;
706 }
2469cfa2
NC		 707 }
708
709 return TRUE;
710}
711
712/* Perform a single relocation. By default we use the standard BFD
713 routines, but a few relocs, we have to do them ourselves. */
714
715static bfd_reloc_status_type
07d6d2b8
AM		 716msp430_final_link_relocate (reloc_howto_type * howto,
717 bfd * input_bfd,
718 asection * input_section,
719 bfd_byte * contents,
720 Elf_Internal_Rela * rel,
721 bfd_vma relocation,
13761a11 722 struct bfd_link_info * info)
2469cfa2 723{
13761a11
NC		 724 static asection * sym_diff_section;
725 static bfd_vma sym_diff_value;
726
727 struct bfd_elf_section_data * esd = elf_section_data (input_section);
2469cfa2
NC		 728 bfd_reloc_status_type r = bfd_reloc_ok;
729 bfd_vma x;
730 bfd_signed_vma srel;
13761a11
NC		 731 bfd_boolean is_rel_reloc = FALSE;
732
733 if (uses_msp430x_relocs (input_bfd))
734 {
735 /* See if we have a REL type relocation. */
736 is_rel_reloc = (esd->rel.hdr != NULL);
737 /* Sanity check - only one type of relocation per section.
738 FIXME: Theoretically it is possible to have both types,
739 but if that happens how can we distinguish between the two ? */
740 BFD_ASSERT (! is_rel_reloc || ! esd->rela.hdr);
741 /* If we are using a REL relocation then the addend should be empty. */
742 BFD_ASSERT (! is_rel_reloc || rel->r_addend == 0);
743 }
2469cfa2 744
13761a11 745 if (sym_diff_section != NULL)
2469cfa2 746 {
13761a11 747 BFD_ASSERT (sym_diff_section == input_section);
1b786873 748
13761a11
NC		 749 if (uses_msp430x_relocs (input_bfd))
750 switch (howto->type)
751 {
752 case R_MSP430_ABS32:
753 /* If we are computing a 32-bit value for the location lists
754 and the result is 0 then we add one to the value. A zero
755 value can result because of linker relaxation deleteing
756 prologue instructions and using a value of 1 (for the begin
757 and end offsets in the location list entry) results in a
758 nul entry which does not prevent the following entries from
759 being parsed. */
760 if (relocation == sym_diff_value
761 && strcmp (input_section->name, ".debug_loc") == 0)
762 ++ relocation;
763 /* Fall through. */
764 case R_MSP430_ABS16:
765 case R_MSP430X_ABS16:
766 case R_MSP430_ABS8:
767 BFD_ASSERT (! is_rel_reloc);
768 relocation -= sym_diff_value;
769 break;
770
771 default:
772 return bfd_reloc_dangerous;
773 }
774 else
775 switch (howto->type)
776 {
777 case R_MSP430_32:
778 case R_MSP430_16:
779 case R_MSP430_16_BYTE:
780 case R_MSP430_8:
781 relocation -= sym_diff_value;
782 break;
783
784 default:
785 return bfd_reloc_dangerous;
786 }
1b786873 787
13761a11
NC		 788 sym_diff_section = NULL;
789 }
790
791 if (uses_msp430x_relocs (input_bfd))
792 switch (howto->type)
793 {
794 case R_MSP430X_SYM_DIFF:
795 /* Cache the input section and value.
796 The offset is unreliable, since relaxation may
797 have reduced the following reloc's offset. */
798 BFD_ASSERT (! is_rel_reloc);
799 sym_diff_section = input_section;
800 sym_diff_value = relocation;
801 return bfd_reloc_ok;
802
803 case R_MSP430_ABS16:
804 contents += rel->r_offset;
805 srel = (bfd_signed_vma) relocation;
806 if (is_rel_reloc)
807 srel += bfd_get_16 (input_bfd, contents);
808 else
809 srel += rel->r_addend;
810 bfd_put_16 (input_bfd, srel & 0xffff, contents);
811 break;
812
813 case R_MSP430X_10_PCREL:
814 contents += rel->r_offset;
815 srel = (bfd_signed_vma) relocation;
816 if (is_rel_reloc)
817 srel += bfd_get_16 (input_bfd, contents) & 0x3ff;
818 else
819 srel += rel->r_addend;
820 srel -= rel->r_offset;
821 srel -= 2; /* Branch instructions add 2 to the PC... */
822 srel -= (input_section->output_section->vma +
823 input_section->output_offset);
824 if (srel & 1)
825 return bfd_reloc_outofrange;
826
827 /* MSP430 addresses commands as words. */
828 srel >>= 1;
829
830 /* Check for an overflow. */
831 if (srel < -512 || srel > 511)
832 {
833 if (info->disable_target_specific_optimizations < 0)
834 {
835 static bfd_boolean warned = FALSE;
836 if (! warned)
837 {
838 info->callbacks->warning
839 (info,
38f14ab8 840 _("try enabling relaxation to avoid relocation truncations"),
13761a11
NC		 841 NULL, input_bfd, input_section, relocation);
842 warned = TRUE;
843 }
844 }
845 return bfd_reloc_overflow;
846 }
847
848 x = bfd_get_16 (input_bfd, contents);
849 x = (x & 0xfc00) | (srel & 0x3ff);
850 bfd_put_16 (input_bfd, x, contents);
851 break;
852
853 case R_MSP430X_PCR20_EXT_ODST:
3f307074 854 /* [0,4]+[48,16] = ---F ---- ---- FFFF */
13761a11
NC		 855 contents += rel->r_offset;
856 srel = (bfd_signed_vma) relocation;
857 if (is_rel_reloc)
858 {
859 bfd_vma addend;
860 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
3f307074 861 addend |= bfd_get_16 (input_bfd, contents + 6);
13761a11 862 srel += addend;
1b786873 863
13761a11
NC		 864 }
865 else
866 srel += rel->r_addend;
867 srel -= rel->r_offset;
868 srel -= (input_section->output_section->vma +
869 input_section->output_offset);
870 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6);
871 x = bfd_get_16 (input_bfd, contents);
872 x = (x & 0xfff0) | ((srel >> 16) & 0xf);
873 bfd_put_16 (input_bfd, x, contents);
874 break;
875
876 case R_MSP430X_ABS20_EXT_SRC:
3f307074 877 /* [7,4]+[32,16] = -78- ---- FFFF */
13761a11
NC		 878 contents += rel->r_offset;
879 srel = (bfd_signed_vma) relocation;
880 if (is_rel_reloc)
881 {
882 bfd_vma addend;
883 addend = (bfd_get_16 (input_bfd, contents) & 0x0780) << 9;
3f307074 884 addend |= bfd_get_16 (input_bfd, contents + 4);
13761a11
NC		 885 srel += addend;
886 }
887 else
888 srel += rel->r_addend;
889 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
890 srel >>= 16;
891 x = bfd_get_16 (input_bfd, contents);
892 x = (x & 0xf87f) | ((srel << 7) & 0x0780);
893 bfd_put_16 (input_bfd, x, contents);
894 break;
895
896 case R_MSP430_16_PCREL:
897 contents += rel->r_offset;
898 srel = (bfd_signed_vma) relocation;
899 if (is_rel_reloc)
900 srel += bfd_get_16 (input_bfd, contents);
901 else
902 srel += rel->r_addend;
903 srel -= rel->r_offset;
904 /* Only branch instructions add 2 to the PC... */
905 srel -= (input_section->output_section->vma +
906 input_section->output_offset);
907 if (srel & 1)
908 return bfd_reloc_outofrange;
909 bfd_put_16 (input_bfd, srel & 0xffff, contents);
910 break;
911
912 case R_MSP430X_PCR20_EXT_DST:
3f307074 913 /* [0,4]+[32,16] = ---F ---- FFFF */
13761a11
NC		 914 contents += rel->r_offset;
915 srel = (bfd_signed_vma) relocation;
916 if (is_rel_reloc)
917 {
918 bfd_vma addend;
919 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
3f307074 920 addend |= bfd_get_16 (input_bfd, contents + 4);
13761a11
NC		 921 srel += addend;
922 }
923 else
924 srel += rel->r_addend;
925 srel -= rel->r_offset;
926 srel -= (input_section->output_section->vma +
927 input_section->output_offset);
928 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
929 srel >>= 16;
930 x = bfd_get_16 (input_bfd, contents);
931 x = (x & 0xfff0) | (srel & 0xf);
932 bfd_put_16 (input_bfd, x, contents);
933 break;
934
935 case R_MSP430X_PCR20_EXT_SRC:
3f307074 936 /* [7,4]+[32,16] = -78- ---- FFFF */
13761a11
NC		 937 contents += rel->r_offset;
938 srel = (bfd_signed_vma) relocation;
939 if (is_rel_reloc)
940 {
941 bfd_vma addend;
942 addend = ((bfd_get_16 (input_bfd, contents) & 0x0780) << 9);
3f307074 943 addend |= bfd_get_16 (input_bfd, contents + 4);
13761a11
NC		 944 srel += addend;;
945 }
946 else
947 srel += rel->r_addend;
948 srel -= rel->r_offset;
949 /* Only branch instructions add 2 to the PC... */
950 srel -= (input_section->output_section->vma +
951 input_section->output_offset);
952 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
953 srel >>= 16;
954 x = bfd_get_16 (input_bfd, contents);
955 x = (x & 0xf87f) | ((srel << 7) & 0x0780);
956 bfd_put_16 (input_bfd, x, contents);
957 break;
958
959 case R_MSP430_ABS8:
960 contents += rel->r_offset;
961 srel = (bfd_signed_vma) relocation;
962 if (is_rel_reloc)
963 srel += bfd_get_8 (input_bfd, contents);
964 else
965 srel += rel->r_addend;
966 bfd_put_8 (input_bfd, srel & 0xff, contents);
967 break;
968
969 case R_MSP430X_ABS20_EXT_DST:
3f307074 970 /* [0,4]+[32,16] = ---F ---- FFFF */
13761a11
NC		 971 contents += rel->r_offset;
972 srel = (bfd_signed_vma) relocation;
973 if (is_rel_reloc)
3f307074
DD		 974 {
975 bfd_vma addend;
976 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
977 addend |= bfd_get_16 (input_bfd, contents + 4);
978 srel += addend;
979 }
13761a11
NC		 980 else
981 srel += rel->r_addend;
982 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
983 srel >>= 16;
984 x = bfd_get_16 (input_bfd, contents);
985 x = (x & 0xfff0) | (srel & 0xf);
986 bfd_put_16 (input_bfd, x, contents);
987 break;
988
989 case R_MSP430X_ABS20_EXT_ODST:
3f307074 990 /* [0,4]+[48,16] = ---F ---- ---- FFFF */
13761a11
NC		 991 contents += rel->r_offset;
992 srel = (bfd_signed_vma) relocation;
993 if (is_rel_reloc)
994 {
995 bfd_vma addend;
996 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
3f307074 997 addend |= bfd_get_16 (input_bfd, contents + 6);
13761a11
NC		 998 srel += addend;
999 }
1000 else
1001 srel += rel->r_addend;
1002 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6);
1003 srel >>= 16;
1004 x = bfd_get_16 (input_bfd, contents);
1005 x = (x & 0xfff0) | (srel & 0xf);
1006 bfd_put_16 (input_bfd, x, contents);
1007 break;
1008
1009 case R_MSP430X_ABS20_ADR_SRC:
3f307074 1010 /* [8,4]+[16,16] = -F-- FFFF */
13761a11
NC		 1011 contents += rel->r_offset;
1012 srel = (bfd_signed_vma) relocation;
1013 if (is_rel_reloc)
1014 {
1015 bfd_vma addend;
1016
1017 addend = ((bfd_get_16 (input_bfd, contents) & 0xf00) << 8);
3f307074 1018 addend |= bfd_get_16 (input_bfd, contents + 2);
13761a11
NC		 1019 srel += addend;
1020 }
1021 else
1022 srel += rel->r_addend;
1023 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2);
1024 srel >>= 16;
1025 x = bfd_get_16 (input_bfd, contents);
1026 x = (x & 0xf0ff) | ((srel << 8) & 0x0f00);
1027 bfd_put_16 (input_bfd, x, contents);
1028 break;
1029
1030 case R_MSP430X_ABS20_ADR_DST:
3f307074 1031 /* [0,4]+[16,16] = ---F FFFF */
13761a11
NC		 1032 contents += rel->r_offset;
1033 srel = (bfd_signed_vma) relocation;
1034 if (is_rel_reloc)
1035 {
1036 bfd_vma addend;
1037 addend = ((bfd_get_16 (input_bfd, contents) & 0xf) << 16);
3f307074 1038 addend |= bfd_get_16 (input_bfd, contents + 2);
13761a11
NC		 1039 srel += addend;
1040 }
1041 else
1042 srel += rel->r_addend;
1043 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2);
1044 srel >>= 16;
1045 x = bfd_get_16 (input_bfd, contents);
1046 x = (x & 0xfff0) | (srel & 0xf);
1047 bfd_put_16 (input_bfd, x, contents);
1048 break;
1049
1050 case R_MSP430X_ABS16:
1051 contents += rel->r_offset;
1052 srel = (bfd_signed_vma) relocation;
1053 if (is_rel_reloc)
1054 srel += bfd_get_16 (input_bfd, contents);
1055 else
1056 srel += rel->r_addend;
1057 x = srel;
1058 if (x > 0xffff)
1b786873 1059 return bfd_reloc_overflow;
13761a11
NC		 1060 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1061 break;
1062
1063 case R_MSP430_ABS_HI16:
1064 /* The EABI specifies that this must be a RELA reloc. */
1065 BFD_ASSERT (! is_rel_reloc);
1066 contents += rel->r_offset;
1067 srel = (bfd_signed_vma) relocation;
1068 srel += rel->r_addend;
1069 bfd_put_16 (input_bfd, (srel >> 16) & 0xffff, contents);
1070 break;
1b786873 1071
13761a11 1072 case R_MSP430X_PCR20_CALL:
3f307074 1073 /* [0,4]+[16,16] = ---F FFFF*/
13761a11
NC		 1074 contents += rel->r_offset;
1075 srel = (bfd_signed_vma) relocation;
1076 if (is_rel_reloc)
1077 {
1078 bfd_vma addend;
1079 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
3f307074 1080 addend |= bfd_get_16 (input_bfd, contents + 2);
13761a11
NC		 1081 srel += addend;
1082 }
1083 else
1084 srel += rel->r_addend;
1085 srel -= rel->r_offset;
1086 srel -= (input_section->output_section->vma +
1087 input_section->output_offset);
1088 bfd_put_16 (input_bfd, srel & 0xffff, contents + 2);
1089 srel >>= 16;
1090 x = bfd_get_16 (input_bfd, contents);
1091 x = (x & 0xfff0) | (srel & 0xf);
1092 bfd_put_16 (input_bfd, x, contents);
1093 break;
1b786873 1094
13761a11
NC		 1095 case R_MSP430X_PCR16:
1096 contents += rel->r_offset;
1097 srel = (bfd_signed_vma) relocation;
1098 if (is_rel_reloc)
1099 srel += bfd_get_16 (input_bfd, contents);
1100 else
1101 srel += rel->r_addend;
1102 srel -= rel->r_offset;
1103 srel -= (input_section->output_section->vma +
1104 input_section->output_offset);
1105 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1106 break;
1b786873 1107
13761a11
NC		 1108 case R_MSP430_PREL31:
1109 contents += rel->r_offset;
1110 srel = (bfd_signed_vma) relocation;
1111 if (is_rel_reloc)
1112 srel += (bfd_get_32 (input_bfd, contents) & 0x7fffffff);
1113 else
1114 srel += rel->r_addend;
1115 srel += rel->r_addend;
1116 x = bfd_get_32 (input_bfd, contents);
1117 x = (x & 0x80000000) | ((srel >> 31) & 0x7fffffff);
1118 bfd_put_32 (input_bfd, x, contents);
1119 break;
1b786873 1120
13761a11
NC		 1121 default:
1122 r = _bfd_final_link_relocate (howto, input_bfd, input_section,
1123 contents, rel->r_offset,
1124 relocation, rel->r_addend);
1125 }
1126 else
1127 switch (howto->type)
1128 {
2469cfa2
NC		 1129 case R_MSP430_10_PCREL:
1130 contents += rel->r_offset;
1131 srel = (bfd_signed_vma) relocation;
1132 srel += rel->r_addend;
1133 srel -= rel->r_offset;
1134 srel -= 2; /* Branch instructions add 2 to the PC... */
1135 srel -= (input_section->output_section->vma +
1136 input_section->output_offset);
1137
1138 if (srel & 1)
1139 return bfd_reloc_outofrange;
1140
1141 /* MSP430 addresses commands as words. */
1142 srel >>= 1;
1143
1144 /* Check for an overflow. */
1145 if (srel < -512 || srel > 511)
13761a11
NC		 1146 {
1147 if (info->disable_target_specific_optimizations < 0)
1148 {
1149 static bfd_boolean warned = FALSE;
1150 if (! warned)
1151 {
1152 info->callbacks->warning
1153 (info,
38f14ab8 1154 _("try enabling relaxation to avoid relocation truncations"),
13761a11
NC		 1155 NULL, input_bfd, input_section, relocation);
1156 warned = TRUE;
1157 }
1158 }
1159 return bfd_reloc_overflow;
1160 }
1b786873 1161
2469cfa2
NC		 1162 x = bfd_get_16 (input_bfd, contents);
1163 x = (x & 0xfc00) | (srel & 0x3ff);
1164 bfd_put_16 (input_bfd, x, contents);
1165 break;
1166
b18c562e
NC		 1167 case R_MSP430_2X_PCREL:
1168 contents += rel->r_offset;
1169 srel = (bfd_signed_vma) relocation;
1170 srel += rel->r_addend;
1171 srel -= rel->r_offset;
1172 srel -= 2; /* Branch instructions add 2 to the PC... */
1173 srel -= (input_section->output_section->vma +
1174 input_section->output_offset);
1175
1176 if (srel & 1)
1177 return bfd_reloc_outofrange;
1178
1179 /* MSP430 addresses commands as words. */
1180 srel >>= 1;
1181
1182 /* Check for an overflow. */
1183 if (srel < -512 || srel > 511)
1184 return bfd_reloc_overflow;
1185
1186 x = bfd_get_16 (input_bfd, contents);
1187 x = (x & 0xfc00) | (srel & 0x3ff);
1188 bfd_put_16 (input_bfd, x, contents);
1189 /* Handle second jump instruction. */
1190 x = bfd_get_16 (input_bfd, contents - 2);
1191 srel += 1;
1192 x = (x & 0xfc00) | (srel & 0x3ff);
1193 bfd_put_16 (input_bfd, x, contents - 2);
1194 break;
1195
b18c562e 1196 case R_MSP430_RL_PCREL:
77bf820f 1197 case R_MSP430_16_PCREL:
2469cfa2
NC		 1198 contents += rel->r_offset;
1199 srel = (bfd_signed_vma) relocation;
1200 srel += rel->r_addend;
1201 srel -= rel->r_offset;
1202 /* Only branch instructions add 2 to the PC... */
1203 srel -= (input_section->output_section->vma +
1204 input_section->output_offset);
1205
1206 if (srel & 1)
1207 return bfd_reloc_outofrange;
1208
1209 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1210 break;
1211
1212 case R_MSP430_16_PCREL_BYTE:
1213 contents += rel->r_offset;
1214 srel = (bfd_signed_vma) relocation;
1215 srel += rel->r_addend;
1216 srel -= rel->r_offset;
1217 /* Only branch instructions add 2 to the PC... */
1218 srel -= (input_section->output_section->vma +
1219 input_section->output_offset);
1220
1221 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1222 break;
1223
1224 case R_MSP430_16_BYTE:
1225 contents += rel->r_offset;
1226 srel = (bfd_signed_vma) relocation;
1227 srel += rel->r_addend;
1228 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1229 break;
1230
1231 case R_MSP430_16:
1232 contents += rel->r_offset;
1233 srel = (bfd_signed_vma) relocation;
1234 srel += rel->r_addend;
1235
1236 if (srel & 1)
1237 return bfd_reloc_notsupported;
1238
1239 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1240 break;
1241
13761a11
NC		 1242 case R_MSP430_8:
1243 contents += rel->r_offset;
1244 srel = (bfd_signed_vma) relocation;
1245 srel += rel->r_addend;
1246
1247 bfd_put_8 (input_bfd, srel & 0xff, contents);
1248 break;
1b786873 1249
13761a11
NC		 1250 case R_MSP430_SYM_DIFF:
1251 /* Cache the input section and value.
1252 The offset is unreliable, since relaxation may
1253 have reduced the following reloc's offset. */
1254 sym_diff_section = input_section;
1255 sym_diff_value = relocation;
1256 return bfd_reloc_ok;
1257
1258 default:
1259 r = _bfd_final_link_relocate (howto, input_bfd, input_section,
1260 contents, rel->r_offset,
1261 relocation, rel->r_addend);
1262 }
2469cfa2
NC		 1263
1264 return r;
1265}
1266
1267/* Relocate an MSP430 ELF section. */
1268
1269static bfd_boolean
b18c562e
NC		 1270elf32_msp430_relocate_section (bfd * output_bfd ATTRIBUTE_UNUSED,
1271 struct bfd_link_info * info,
1272 bfd * input_bfd,
1273 asection * input_section,
1274 bfd_byte * contents,
1275 Elf_Internal_Rela * relocs,
1276 Elf_Internal_Sym * local_syms,
1277 asection ** local_sections)
2469cfa2
NC		 1278{
1279 Elf_Internal_Shdr *symtab_hdr;
1280 struct elf_link_hash_entry **sym_hashes;
1281 Elf_Internal_Rela *rel;
1282 Elf_Internal_Rela *relend;
1283
1284 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
1285 sym_hashes = elf_sym_hashes (input_bfd);
1286 relend = relocs + input_section->reloc_count;
1287
1288 for (rel = relocs; rel < relend; rel++)
1289 {
1290 reloc_howto_type *howto;
1291 unsigned long r_symndx;
1292 Elf_Internal_Sym *sym;
1293 asection *sec;
1294 struct elf_link_hash_entry *h;
1295 bfd_vma relocation;
1296 bfd_reloc_status_type r;
1297 const char *name = NULL;
1298 int r_type;
1299
2469cfa2
NC		 1300 r_type = ELF32_R_TYPE (rel->r_info);
1301 r_symndx = ELF32_R_SYM (rel->r_info);
13761a11
NC		 1302
1303 if (uses_msp430x_relocs (input_bfd))
1304 howto = elf_msp430x_howto_table + r_type;
1305 else
1306 howto = elf_msp430_howto_table + r_type;
1307
2469cfa2
NC		 1308 h = NULL;
1309 sym = NULL;
1310 sec = NULL;
1311
1312 if (r_symndx < symtab_hdr->sh_info)
1313 {
1314 sym = local_syms + r_symndx;
1315 sec = local_sections[r_symndx];
8517fae7 1316 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
2469cfa2
NC		 1317
1318 name = bfd_elf_string_from_elf_section
1319 (input_bfd, symtab_hdr->sh_link, sym->st_name);
fd361982 1320 name = name == NULL || *name == 0 ? bfd_section_name (sec) : name;
2469cfa2
NC		 1321 }
1322 else
1323 {
62d887d4 1324 bfd_boolean unresolved_reloc, warned, ignored;
2469cfa2 1325
b2a8e766
AM		 1326 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
1327 r_symndx, symtab_hdr, sym_hashes,
1328 h, sec, relocation,
62d887d4 1329 unresolved_reloc, warned, ignored);
13761a11 1330 name = h->root.root.string;
2469cfa2
NC		 1331 }
1332
dbaa2011 1333 if (sec != NULL && discarded_section (sec))
e4067dbb 1334 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 1335 rel, 1, relend, howto, 0, contents);
ab96bf03 1336
0e1862bb 1337 if (bfd_link_relocatable (info))
ab96bf03
AM		 1338 continue;
1339
2469cfa2 1340 r = msp430_final_link_relocate (howto, input_bfd, input_section,
13761a11 1341 contents, rel, relocation, info);
2469cfa2
NC		 1342
1343 if (r != bfd_reloc_ok)
1344 {
1345 const char *msg = (const char *) NULL;
1346
1347 switch (r)
1348 {
1349 case bfd_reloc_overflow:
1a72702b 1350 (*info->callbacks->reloc_overflow)
13761a11 1351 (info, (h ? &h->root : NULL), name, howto->name,
1a72702b 1352 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
2469cfa2
NC		 1353 break;
1354
1355 case bfd_reloc_undefined:
1a72702b
AM		 1356 (*info->callbacks->undefined_symbol)
1357 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
2469cfa2
NC		 1358 break;
1359
1360 case bfd_reloc_outofrange:
13761a11 1361 msg = _("internal error: branch/jump to an odd address detected");
2469cfa2
NC		 1362 break;
1363
1364 case bfd_reloc_notsupported:
1365 msg = _("internal error: unsupported relocation error");
1366 break;
1367
1368 case bfd_reloc_dangerous:
1369 msg = _("internal error: dangerous relocation");
1370 break;
1371
1372 default:
1373 msg = _("internal error: unknown error");
1374 break;
1375 }
1376
1377 if (msg)
1a72702b
AM		 1378 (*info->callbacks->warning) (info, msg, name, input_bfd,
1379 input_section, rel->r_offset);
2469cfa2
NC		 1380 }
1381
1382 }
1383
1384 return TRUE;
1385}
1386
1387/* The final processing done just before writing out a MSP430 ELF object
1388 file. This gets the MSP430 architecture right based on the machine
1389 number. */
1390
cc364be6
AM		 1391static bfd_boolean
1392bfd_elf_msp430_final_write_processing (bfd *abfd)
2469cfa2
NC		 1393{
1394 unsigned long val;
1395
1396 switch (bfd_get_mach (abfd))
1397 {
1398 default:
13761a11
NC		 1399 case bfd_mach_msp110: val = E_MSP430_MACH_MSP430x11x1; break;
1400 case bfd_mach_msp11: val = E_MSP430_MACH_MSP430x11; break;
1401 case bfd_mach_msp12: val = E_MSP430_MACH_MSP430x12; break;
1402 case bfd_mach_msp13: val = E_MSP430_MACH_MSP430x13; break;
1403 case bfd_mach_msp14: val = E_MSP430_MACH_MSP430x14; break;
1404 case bfd_mach_msp15: val = E_MSP430_MACH_MSP430x15; break;
1405 case bfd_mach_msp16: val = E_MSP430_MACH_MSP430x16; break;
1406 case bfd_mach_msp31: val = E_MSP430_MACH_MSP430x31; break;
1407 case bfd_mach_msp32: val = E_MSP430_MACH_MSP430x32; break;
1408 case bfd_mach_msp33: val = E_MSP430_MACH_MSP430x33; break;
1409 case bfd_mach_msp41: val = E_MSP430_MACH_MSP430x41; break;
1410 case bfd_mach_msp42: val = E_MSP430_MACH_MSP430x42; break;
1411 case bfd_mach_msp43: val = E_MSP430_MACH_MSP430x43; break;
1412 case bfd_mach_msp44: val = E_MSP430_MACH_MSP430x44; break;
1413 case bfd_mach_msp20: val = E_MSP430_MACH_MSP430x20; break;
1414 case bfd_mach_msp22: val = E_MSP430_MACH_MSP430x22; break;
1415 case bfd_mach_msp23: val = E_MSP430_MACH_MSP430x23; break;
1416 case bfd_mach_msp24: val = E_MSP430_MACH_MSP430x24; break;
1417 case bfd_mach_msp26: val = E_MSP430_MACH_MSP430x26; break;
1418 case bfd_mach_msp46: val = E_MSP430_MACH_MSP430x46; break;
1419 case bfd_mach_msp47: val = E_MSP430_MACH_MSP430x47; break;
1420 case bfd_mach_msp54: val = E_MSP430_MACH_MSP430x54; break;
1421 case bfd_mach_msp430x: val = E_MSP430_MACH_MSP430X; break;
2469cfa2
NC		 1422 }
1423
1424 elf_elfheader (abfd)->e_machine = EM_MSP430;
1425 elf_elfheader (abfd)->e_flags &= ~EF_MSP430_MACH;
1426 elf_elfheader (abfd)->e_flags |= val;
cc364be6 1427 return _bfd_elf_final_write_processing (abfd);
2469cfa2
NC		 1428}
1429
1430/* Set the right machine number. */
1431
1432static bfd_boolean
b18c562e 1433elf32_msp430_object_p (bfd * abfd)
2469cfa2
NC		 1434{
1435 int e_set = bfd_mach_msp14;
1436
1437 if (elf_elfheader (abfd)->e_machine == EM_MSP430
1438 || elf_elfheader (abfd)->e_machine == EM_MSP430_OLD)
1439 {
1440 int e_mach = elf_elfheader (abfd)->e_flags & EF_MSP430_MACH;
1441
1442 switch (e_mach)
1443 {
1444 default:
13761a11
NC		 1445 case E_MSP430_MACH_MSP430x11: e_set = bfd_mach_msp11; break;
1446 case E_MSP430_MACH_MSP430x11x1: e_set = bfd_mach_msp110; break;
1447 case E_MSP430_MACH_MSP430x12: e_set = bfd_mach_msp12; break;
1448 case E_MSP430_MACH_MSP430x13: e_set = bfd_mach_msp13; break;
1449 case E_MSP430_MACH_MSP430x14: e_set = bfd_mach_msp14; break;
1450 case E_MSP430_MACH_MSP430x15: e_set = bfd_mach_msp15; break;
1451 case E_MSP430_MACH_MSP430x16: e_set = bfd_mach_msp16; break;
1452 case E_MSP430_MACH_MSP430x31: e_set = bfd_mach_msp31; break;
1453 case E_MSP430_MACH_MSP430x32: e_set = bfd_mach_msp32; break;
1454 case E_MSP430_MACH_MSP430x33: e_set = bfd_mach_msp33; break;
1455 case E_MSP430_MACH_MSP430x41: e_set = bfd_mach_msp41; break;
1456 case E_MSP430_MACH_MSP430x42: e_set = bfd_mach_msp42; break;
1457 case E_MSP430_MACH_MSP430x43: e_set = bfd_mach_msp43; break;
1458 case E_MSP430_MACH_MSP430x44: e_set = bfd_mach_msp44; break;
1459 case E_MSP430_MACH_MSP430x20: e_set = bfd_mach_msp20; break;
1460 case E_MSP430_MACH_MSP430x22: e_set = bfd_mach_msp22; break;
1461 case E_MSP430_MACH_MSP430x23: e_set = bfd_mach_msp23; break;
1462 case E_MSP430_MACH_MSP430x24: e_set = bfd_mach_msp24; break;
1463 case E_MSP430_MACH_MSP430x26: e_set = bfd_mach_msp26; break;
1464 case E_MSP430_MACH_MSP430x46: e_set = bfd_mach_msp46; break;
1465 case E_MSP430_MACH_MSP430x47: e_set = bfd_mach_msp47; break;
1466 case E_MSP430_MACH_MSP430x54: e_set = bfd_mach_msp54; break;
1467 case E_MSP430_MACH_MSP430X: e_set = bfd_mach_msp430x; break;
2469cfa2
NC		 1468 }
1469 }
1b786873 1470
2469cfa2
NC		 1471 return bfd_default_set_arch_mach (abfd, bfd_arch_msp430, e_set);
1472}
1473
b18c562e
NC		 1474/* These functions handle relaxing for the msp430.
1475 Relaxation required only in two cases:
1476 - Bad hand coding like jumps from one section to another or
1477 from file to file.
77bf820f 1478 - Sibling calls. This will affect only 'jump label' polymorph. Without
b18c562e
NC		 1479 relaxing this enlarges code by 2 bytes. Sibcalls implemented but
1480 do not work in gcc's port by the reason I do not know.
13761a11
NC		 1481 - To convert out of range conditional jump instructions (found inside
1482 a function) into inverted jumps over an unconditional branch instruction.
b18c562e
NC		 1483 Anyway, if a relaxation required, user should pass -relax option to the
1484 linker.
1485
1486 There are quite a few relaxing opportunities available on the msp430:
1487
1488 ================================================================
1489
1490 1. 3 words -> 1 word
1491
07d6d2b8
AM		 1492 eq == jeq label jne +4; br lab
1493 ne != jne label jeq +4; br lab
1494 lt < jl label jge +4; br lab
1495 ltu < jlo label lhs +4; br lab
1496 ge >= jge label jl +4; br lab
1497 geu >= jhs label jlo +4; br lab
b18c562e
NC		 1498
1499 2. 4 words -> 1 word
1500
07d6d2b8 1501 ltn < jn jn +2; jmp +4; br lab
b18c562e
NC		 1502
1503 3. 4 words -> 2 words
1504
07d6d2b8
AM		 1505 gt > jeq +2; jge label jeq +6; jl +4; br label
1506 gtu > jeq +2; jhs label jeq +6; jlo +4; br label
b18c562e
NC		 1507
1508 4. 4 words -> 2 words and 2 labels
1509
07d6d2b8
AM		 1510 leu <= jeq label; jlo label jeq +2; jhs +4; br label
1511 le <= jeq label; jl label jeq +2; jge +4; br label
b18c562e
NC		 1512 =================================================================
1513
1514 codemap for first cases is (labels masked ):
1515 eq: 0x2002,0x4010,0x0000 -> 0x2400
1516 ne: 0x2402,0x4010,0x0000 -> 0x2000
1517 lt: 0x3402,0x4010,0x0000 -> 0x3800
1518 ltu: 0x2c02,0x4010,0x0000 -> 0x2800
1519 ge: 0x3802,0x4010,0x0000 -> 0x3400
1520 geu: 0x2802,0x4010,0x0000 -> 0x2c00
1521
1522 second case:
1523 ltn: 0x3001,0x3c02,0x4010,0x0000 -> 0x3000
1524
1525 third case:
1526 gt: 0x2403,0x3802,0x4010,0x0000 -> 0x2401,0x3400
1527 gtu: 0x2403,0x2802,0x4010,0x0000 -> 0x2401,0x2c00
1528
1529 fourth case:
1530 leu: 0x2401,0x2c02,0x4010,0x0000 -> 0x2400,0x2800
1531 le: 0x2401,0x3402,0x4010,0x0000 -> 0x2400,0x3800
1532
1533 Unspecified case :)
1534 jump: 0x4010,0x0000 -> 0x3c00. */
1535
1536#define NUMB_RELAX_CODES 12
1537static struct rcodes_s
1538{
1539 int f0, f1; /* From code. */
1540 int t0, t1; /* To code. */
1541 int labels; /* Position of labels: 1 - one label at first
1542 word, 2 - one at second word, 3 - two
1543 labels at both. */
1544 int cdx; /* Words to match. */
1545 int bs; /* Shrink bytes. */
1546 int off; /* Offset from old label for new code. */
1547 int ncl; /* New code length. */
1548} rcode[] =
07d6d2b8 1549{/* lab,cdx,bs,off,ncl */
b18c562e
NC		 1550 { 0x0000, 0x0000, 0x3c00, 0x0000, 1, 0, 2, 2, 2}, /* jump */
1551 { 0x0000, 0x2002, 0x2400, 0x0000, 1, 1, 4, 4, 2}, /* eq */
1552 { 0x0000, 0x2402, 0x2000, 0x0000, 1, 1, 4, 4, 2}, /* ne */
1553 { 0x0000, 0x3402, 0x3800, 0x0000, 1, 1, 4, 4, 2}, /* lt */
1554 { 0x0000, 0x2c02, 0x2800, 0x0000, 1, 1, 4, 4, 2}, /* ltu */
1555 { 0x0000, 0x3802, 0x3400, 0x0000, 1, 1, 4, 4, 2}, /* ge */
1556 { 0x0000, 0x2802, 0x2c00, 0x0000, 1, 1, 4, 4, 2}, /* geu */
1557 { 0x3001, 0x3c02, 0x3000, 0x0000, 1, 2, 6, 6, 2}, /* ltn */
1558 { 0x2403, 0x3802, 0x2401, 0x3400, 2, 2, 4, 6, 4}, /* gt */
1559 { 0x2403, 0x2802, 0x2401, 0x2c00, 2, 2, 4, 6, 4}, /* gtu */
1560 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* leu , 2 labels */
1561 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* le , 2 labels */
07d6d2b8 1562 { 0, 0, 0, 0, 0, 0, 0, 0, 0}
b18c562e
NC		 1563};
1564
1565/* Return TRUE if a symbol exists at the given address. */
1566
1567static bfd_boolean
1568msp430_elf_symbol_address_p (bfd * abfd,
1569 asection * sec,
1570 Elf_Internal_Sym * isym,
1571 bfd_vma addr)
1572{
1573 Elf_Internal_Shdr *symtab_hdr;
1574 unsigned int sec_shndx;
1575 Elf_Internal_Sym *isymend;
1576 struct elf_link_hash_entry **sym_hashes;
1577 struct elf_link_hash_entry **end_hashes;
1578 unsigned int symcount;
1579
1580 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1581
1582 /* Examine all the local symbols. */
1583 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1584 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1585 if (isym->st_shndx == sec_shndx && isym->st_value == addr)
1586 return TRUE;
1587
1588 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1589 - symtab_hdr->sh_info);
1590 sym_hashes = elf_sym_hashes (abfd);
1591 end_hashes = sym_hashes + symcount;
1592 for (; sym_hashes < end_hashes; sym_hashes++)
1593 {
1594 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1595
1596 if ((sym_hash->root.type == bfd_link_hash_defined
1597 || sym_hash->root.type == bfd_link_hash_defweak)
1598 && sym_hash->root.u.def.section == sec
1599 && sym_hash->root.u.def.value == addr)
1600 return TRUE;
1601 }
1602
1603 return FALSE;
1604}
1605
13761a11
NC		 1606/* Adjust all local symbols defined as '.section + 0xXXXX' (.section has
1607 sec_shndx) referenced from current and other sections. */
1608
046aeb74 1609static bfd_boolean
13761a11
NC		 1610msp430_elf_relax_adjust_locals (bfd * abfd, asection * sec, bfd_vma addr,
1611 int count, unsigned int sec_shndx,
1612 bfd_vma toaddr)
046aeb74
DD		 1613{
1614 Elf_Internal_Shdr *symtab_hdr;
1615 Elf_Internal_Rela *irel;
1616 Elf_Internal_Rela *irelend;
1617 Elf_Internal_Sym *isym;
1618
1619 irel = elf_section_data (sec)->relocs;
13761a11
NC		 1620 if (irel == NULL)
1621 return TRUE;
1622
046aeb74
DD		 1623 irelend = irel + sec->reloc_count;
1624 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1625 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
bceec4b9 1626
13761a11 1627 for (;irel < irelend; irel++)
046aeb74 1628 {
bceec4b9 1629 unsigned int sidx = ELF32_R_SYM(irel->r_info);
046aeb74 1630 Elf_Internal_Sym *lsym = isym + sidx;
bceec4b9 1631
1ade7175 1632 /* Adjust symbols referenced by .sec+0xXX. */
bceec4b9
DD		 1633 if (irel->r_addend > addr && irel->r_addend < toaddr
1634 && sidx < symtab_hdr->sh_info
046aeb74
DD		 1635 && lsym->st_shndx == sec_shndx)
1636 irel->r_addend -= count;
1637 }
1b786873 1638
046aeb74
DD		 1639 return TRUE;
1640}
1641
b18c562e
NC		 1642/* Delete some bytes from a section while relaxing. */
1643
1644static bfd_boolean
1645msp430_elf_relax_delete_bytes (bfd * abfd, asection * sec, bfd_vma addr,
1646 int count)
1647{
1648 Elf_Internal_Shdr *symtab_hdr;
1649 unsigned int sec_shndx;
1650 bfd_byte *contents;
1651 Elf_Internal_Rela *irel;
1652 Elf_Internal_Rela *irelend;
b18c562e
NC		 1653 bfd_vma toaddr;
1654 Elf_Internal_Sym *isym;
1655 Elf_Internal_Sym *isymend;
1656 struct elf_link_hash_entry **sym_hashes;
1657 struct elf_link_hash_entry **end_hashes;
1658 unsigned int symcount;
046aeb74 1659 asection *p;
b18c562e
NC		 1660
1661 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1662
1663 contents = elf_section_data (sec)->this_hdr.contents;
1664
b18c562e
NC		 1665 toaddr = sec->size;
1666
1667 irel = elf_section_data (sec)->relocs;
1668 irelend = irel + sec->reloc_count;
1669
1670 /* Actually delete the bytes. */
1671 memmove (contents + addr, contents + addr + count,
1672 (size_t) (toaddr - addr - count));
1673 sec->size -= count;
1674
1675 /* Adjust all the relocs. */
fa9ee72b
DD		 1676 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1677 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
13761a11 1678 for (; irel < irelend; irel++)
fa9ee72b 1679 {
fa9ee72b
DD		 1680 /* Get the new reloc address. */
1681 if ((irel->r_offset > addr && irel->r_offset < toaddr))
1682 irel->r_offset -= count;
fa9ee72b 1683 }
b18c562e 1684
046aeb74 1685 for (p = abfd->sections; p != NULL; p = p->next)
13761a11 1686 msp430_elf_relax_adjust_locals (abfd,p,addr,count,sec_shndx,toaddr);
1b786873 1687
b18c562e
NC		 1688 /* Adjust the local symbols defined in this section. */
1689 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1690 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1691 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
0f8f0c57
NC		 1692 {
1693 const char * name;
1694
1695 name = bfd_elf_string_from_elf_section
1696 (abfd, symtab_hdr->sh_link, isym->st_name);
fd361982 1697 name = name == NULL || *name == 0 ? bfd_section_name (sec) : name;
0f8f0c57
NC		 1698
1699 if (isym->st_shndx != sec_shndx)
1700 continue;
1b786873 1701
0f8f0c57
NC		 1702 if (isym->st_value > addr
1703 && (isym->st_value < toaddr
1704 /* We also adjust a symbol at the end of the section if its name is
1705 on the list below. These symbols are used for debug info
1706 generation and they refer to the end of the current section, not
1707 the start of the next section. */
1708 || (isym->st_value == toaddr
1709 && name != NULL
1710 && (CONST_STRNEQ (name, ".Letext")
1711 || CONST_STRNEQ (name, ".LFE")))))
1712 {
1713 if (isym->st_value < addr + count)
1714 isym->st_value = addr;
1715 else
1716 isym->st_value -= count;
1717 }
1718 /* Adjust the function symbol's size as well. */
1719 else if (ELF_ST_TYPE (isym->st_info) == STT_FUNC
1720 && isym->st_value + isym->st_size > addr
1721 && isym->st_value + isym->st_size < toaddr)
1722 isym->st_size -= count;
1723 }
b18c562e
NC		 1724
1725 /* Now adjust the global symbols defined in this section. */
1726 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1727 - symtab_hdr->sh_info);
1728 sym_hashes = elf_sym_hashes (abfd);
1729 end_hashes = sym_hashes + symcount;
1730 for (; sym_hashes < end_hashes; sym_hashes++)
1731 {
1732 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1733
1734 if ((sym_hash->root.type == bfd_link_hash_defined
1735 || sym_hash->root.type == bfd_link_hash_defweak)
1736 && sym_hash->root.u.def.section == sec
1737 && sym_hash->root.u.def.value > addr
1738 && sym_hash->root.u.def.value < toaddr)
0f8f0c57
NC		 1739 {
1740 if (sym_hash->root.u.def.value < addr + count)
1741 sym_hash->root.u.def.value = addr;
1742 else
1743 sym_hash->root.u.def.value -= count;
1744 }
1745 /* Adjust the function symbol's size as well. */
1746 else if (sym_hash->root.type == bfd_link_hash_defined
1747 && sym_hash->root.u.def.section == sec
1748 && sym_hash->type == STT_FUNC
1749 && sym_hash->root.u.def.value + sym_hash->size > addr
1750 && sym_hash->root.u.def.value + sym_hash->size < toaddr)
1751 sym_hash->size -= count;
b18c562e
NC		 1752 }
1753
1754 return TRUE;
1755}
1756
13761a11
NC		 1757/* Insert two words into a section whilst relaxing. */
1758
1759static bfd_byte *
1760msp430_elf_relax_add_two_words (bfd * abfd, asection * sec, bfd_vma addr,
1761 int word1, int word2)
1762{
1763 Elf_Internal_Shdr *symtab_hdr;
1764 unsigned int sec_shndx;
1765 bfd_byte *contents;
1766 Elf_Internal_Rela *irel;
1767 Elf_Internal_Rela *irelend;
1768 Elf_Internal_Sym *isym;
1769 Elf_Internal_Sym *isymend;
1770 struct elf_link_hash_entry **sym_hashes;
1771 struct elf_link_hash_entry **end_hashes;
1772 unsigned int symcount;
1773 bfd_vma sec_end;
1774 asection *p;
1775
1776 contents = elf_section_data (sec)->this_hdr.contents;
1777 sec_end = sec->size;
1778
1779 /* Make space for the new words. */
1780 contents = bfd_realloc (contents, sec_end + 4);
1781 memmove (contents + addr + 4, contents + addr, sec_end - addr);
1782
1783 /* Insert the new words. */
1784 bfd_put_16 (abfd, word1, contents + addr);
1785 bfd_put_16 (abfd, word2, contents + addr + 2);
1786
1787 /* Update the section information. */
1788 sec->size += 4;
1b786873 1789 elf_section_data (sec)->this_hdr.contents = contents;
13761a11
NC		 1790
1791 /* Adjust all the relocs. */
1792 irel = elf_section_data (sec)->relocs;
1793 irelend = irel + sec->reloc_count;
1794
1795 for (; irel < irelend; irel++)
1796 if ((irel->r_offset >= addr && irel->r_offset < sec_end))
1797 irel->r_offset += 4;
1798
1799 /* Adjust the local symbols defined in this section. */
1800 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1801 for (p = abfd->sections; p != NULL; p = p->next)
1802 msp430_elf_relax_adjust_locals (abfd, p, addr, -4,
1803 sec_shndx, sec_end);
1804
1805 /* Adjust the global symbols affected by the move. */
1806 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1807 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1808 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1809 if (isym->st_shndx == sec_shndx
1810 && isym->st_value >= addr && isym->st_value < sec_end)
1811 isym->st_value += 4;
1812
1813 /* Now adjust the global symbols defined in this section. */
1814 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1815 - symtab_hdr->sh_info);
1816 sym_hashes = elf_sym_hashes (abfd);
1817 end_hashes = sym_hashes + symcount;
1818 for (; sym_hashes < end_hashes; sym_hashes++)
1819 {
1820 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1821
1822 if ((sym_hash->root.type == bfd_link_hash_defined
1823 || sym_hash->root.type == bfd_link_hash_defweak)
1824 && sym_hash->root.u.def.section == sec
1825 && sym_hash->root.u.def.value >= addr
1826 && sym_hash->root.u.def.value < sec_end)
1827 sym_hash->root.u.def.value += 4;
1828 }
1829
1830 return contents;
1831}
1b786873 1832
b18c562e
NC		 1833static bfd_boolean
1834msp430_elf_relax_section (bfd * abfd, asection * sec,
1835 struct bfd_link_info * link_info,
1836 bfd_boolean * again)
1837{
1838 Elf_Internal_Shdr * symtab_hdr;
1839 Elf_Internal_Rela * internal_relocs;
1840 Elf_Internal_Rela * irel;
1841 Elf_Internal_Rela * irelend;
07d6d2b8 1842 bfd_byte * contents = NULL;
b18c562e
NC		 1843 Elf_Internal_Sym * isymbuf = NULL;
1844
1845 /* Assume nothing changes. */
1846 *again = FALSE;
1847
1848 /* We don't have to do anything for a relocatable link, if
1849 this section does not have relocs, or if this is not a
1850 code section. */
0e1862bb 1851 if (bfd_link_relocatable (link_info)
13761a11
NC		 1852 || (sec->flags & SEC_RELOC) == 0
1853 || sec->reloc_count == 0 || (sec->flags & SEC_CODE) == 0)
b18c562e
NC		 1854 return TRUE;
1855
1856 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1857
1858 /* Get a copy of the native relocations. */
1859 internal_relocs =
1860 _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory);
1861 if (internal_relocs == NULL)
1862 goto error_return;
1863
1864 /* Walk through them looking for relaxing opportunities. */
1865 irelend = internal_relocs + sec->reloc_count;
13761a11
NC		 1866
1867 /* Do code size growing relocs first. */
b18c562e
NC		 1868 for (irel = internal_relocs; irel < irelend; irel++)
1869 {
1870 bfd_vma symval;
1871
1872 /* If this isn't something that can be relaxed, then ignore
07d6d2b8 1873 this reloc. */
13761a11 1874 if (uses_msp430x_relocs (abfd)
07d6d2b8 1875 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430X_10_PCREL)
13761a11
NC		 1876 ;
1877 else if (! uses_msp430x_relocs (abfd)
07d6d2b8 1878 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_10_PCREL)
13761a11
NC		 1879 ;
1880 else
b18c562e
NC		 1881 continue;
1882
1883 /* Get the section contents if we haven't done so already. */
1884 if (contents == NULL)
1885 {
1886 /* Get cached copy if it exists. */
1887 if (elf_section_data (sec)->this_hdr.contents != NULL)
1888 contents = elf_section_data (sec)->this_hdr.contents;
1889 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
1890 goto error_return;
1891 }
1892
1893 /* Read this BFD's local symbols if we haven't done so already. */
1894 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
1895 {
1896 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
1897 if (isymbuf == NULL)
1898 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
1899 symtab_hdr->sh_info, 0,
1900 NULL, NULL, NULL);
1901 if (isymbuf == NULL)
1902 goto error_return;
1903 }
1904
1905 /* Get the value of the symbol referred to by the reloc. */
1906 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
1907 {
1908 /* A local symbol. */
1909 Elf_Internal_Sym *isym;
1910 asection *sym_sec;
1911
1912 isym = isymbuf + ELF32_R_SYM (irel->r_info);
1913 if (isym->st_shndx == SHN_UNDEF)
1914 sym_sec = bfd_und_section_ptr;
1915 else if (isym->st_shndx == SHN_ABS)
1916 sym_sec = bfd_abs_section_ptr;
1917 else if (isym->st_shndx == SHN_COMMON)
1918 sym_sec = bfd_com_section_ptr;
1919 else
1920 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
1921 symval = (isym->st_value
1922 + sym_sec->output_section->vma + sym_sec->output_offset);
1923 }
1924 else
1925 {
1926 unsigned long indx;
1927 struct elf_link_hash_entry *h;
1928
1929 /* An external symbol. */
1930 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
1931 h = elf_sym_hashes (abfd)[indx];
1932 BFD_ASSERT (h != NULL);
1933
1934 if (h->root.type != bfd_link_hash_defined
1935 && h->root.type != bfd_link_hash_defweak)
1936 /* This appears to be a reference to an undefined
1937 symbol. Just ignore it--it will be caught by the
1938 regular reloc processing. */
1939 continue;
1940
1941 symval = (h->root.u.def.value
1942 + h->root.u.def.section->output_section->vma
1943 + h->root.u.def.section->output_offset);
1944 }
1945
1946 /* For simplicity of coding, we are going to modify the section
07d6d2b8
AM		 1947 contents, the section relocs, and the BFD symbol table. We
1948 must tell the rest of the code not to free up this
1949 information. It would be possible to instead create a table
1950 of changes which have to be made, as is done in coff-mips.c;
1951 that would be more work, but would require less memory when
1952 the linker is run. */
b18c562e 1953
13761a11
NC		 1954 bfd_signed_vma value = symval;
1955 int opcode;
b18c562e 1956
13761a11
NC		 1957 /* Compute the value that will be relocated. */
1958 value += irel->r_addend;
1959 /* Convert to PC relative. */
1960 value -= (sec->output_section->vma + sec->output_offset);
1961 value -= irel->r_offset;
1962 value -= 2;
1963 /* Scale. */
1964 value >>= 1;
b18c562e 1965
13761a11
NC		 1966 /* If it is in range then no modifications are needed. */
1967 if (value >= -512 && value <= 511)
1968 continue;
b18c562e 1969
13761a11
NC		 1970 /* Get the opcode. */
1971 opcode = bfd_get_16 (abfd, contents + irel->r_offset);
1b786873 1972
13761a11
NC		 1973 /* Compute the new opcode. We are going to convert:
1974 J<cond> label
1975 into:
1976 J<inv-cond> 1f
1977 BR[A] #label
07d6d2b8 1978 1: */
13761a11
NC		 1979 switch (opcode & 0xfc00)
1980 {
1b786873 1981 case 0x3800: opcode = 0x3402; break; /* Jl -> Jge +2 */
13761a11
NC		 1982 case 0x3400: opcode = 0x3802; break; /* Jge -> Jl +2 */
1983 case 0x2c00: opcode = 0x2802; break; /* Jhs -> Jlo +2 */
1984 case 0x2800: opcode = 0x2c02; break; /* Jlo -> Jhs +2 */
1985 case 0x2400: opcode = 0x2002; break; /* Jeq -> Jne +2 */
1986 case 0x2000: opcode = 0x2402; break; /* jne -> Jeq +2 */
1987 case 0x3000: /* jn */
1988 /* There is no direct inverse of the Jn insn.
1989 FIXME: we could do this as:
07d6d2b8
AM		 1990 Jn 1f
1991 br 2f
13761a11 1992 1: br label
07d6d2b8 1993 2: */
13761a11
NC		 1994 continue;
1995 default:
1996 /* Not a conditional branch instruction. */
1997 /* fprintf (stderr, "unrecog: %x\n", opcode); */
2d071cfc 1998 continue;
13761a11 1999 }
b18c562e 2000
13761a11
NC		 2001 /* Note that we've changed the relocs, section contents, etc. */
2002 elf_section_data (sec)->relocs = internal_relocs;
2003 elf_section_data (sec)->this_hdr.contents = contents;
2004 symtab_hdr->contents = (unsigned char *) isymbuf;
b18c562e 2005
13761a11
NC		 2006 /* Install the new opcode. */
2007 bfd_put_16 (abfd, opcode, contents + irel->r_offset);
b18c562e 2008
13761a11
NC		 2009 /* Insert the new branch instruction. */
2010 if (uses_msp430x_relocs (abfd))
2011 {
1b786873 2012 /* Insert an absolute branch (aka MOVA) instruction. */
13761a11
NC		 2013 contents = msp430_elf_relax_add_two_words
2014 (abfd, sec, irel->r_offset + 2, 0x0080, 0x0000);
2015
2016 /* Update the relocation to point to the inserted branch
2017 instruction. Note - we are changing a PC-relative reloc
2018 into an absolute reloc, but this is OK because we have
2019 arranged with the assembler to have the reloc's value be
2020 a (local) symbol, not a section+offset value. */
2021 irel->r_offset += 2;
2022 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2023 R_MSP430X_ABS20_ADR_SRC);
2024 }
2025 else
2026 {
2027 contents = msp430_elf_relax_add_two_words
2028 (abfd, sec, irel->r_offset + 2, 0x4030, 0x0000);
2029
2030 /* See comment above about converting a 10-bit PC-rel
2031 relocation into a 16-bit absolute relocation. */
2032 irel->r_offset += 4;
2033 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2034 R_MSP430_16);
2035 }
b18c562e 2036
13761a11
NC		 2037 /* Growing the section may mean that other
2038 conditional branches need to be fixed. */
2039 *again = TRUE;
2040 }
b18c562e 2041
13761a11
NC		 2042 for (irel = internal_relocs; irel < irelend; irel++)
2043 {
2044 bfd_vma symval;
2045
2046 /* Get the section contents if we haven't done so already. */
2047 if (contents == NULL)
2048 {
2049 /* Get cached copy if it exists. */
2050 if (elf_section_data (sec)->this_hdr.contents != NULL)
2051 contents = elf_section_data (sec)->this_hdr.contents;
2052 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
2053 goto error_return;
2054 }
2055
2056 /* Read this BFD's local symbols if we haven't done so already. */
2057 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
2058 {
2059 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
2060 if (isymbuf == NULL)
2061 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
2062 symtab_hdr->sh_info, 0,
2063 NULL, NULL, NULL);
2064 if (isymbuf == NULL)
2065 goto error_return;
2066 }
2067
2068 /* Get the value of the symbol referred to by the reloc. */
2069 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
2070 {
2071 /* A local symbol. */
2072 Elf_Internal_Sym *isym;
2073 asection *sym_sec;
2074
2075 isym = isymbuf + ELF32_R_SYM (irel->r_info);
2076 if (isym->st_shndx == SHN_UNDEF)
2077 sym_sec = bfd_und_section_ptr;
2078 else if (isym->st_shndx == SHN_ABS)
2079 sym_sec = bfd_abs_section_ptr;
2080 else if (isym->st_shndx == SHN_COMMON)
2081 sym_sec = bfd_com_section_ptr;
2082 else
2083 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
2084 symval = (isym->st_value
2085 + sym_sec->output_section->vma + sym_sec->output_offset);
2086 }
2087 else
2088 {
2089 unsigned long indx;
2090 struct elf_link_hash_entry *h;
2091
2092 /* An external symbol. */
2093 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
2094 h = elf_sym_hashes (abfd)[indx];
2095 BFD_ASSERT (h != NULL);
2096
2097 if (h->root.type != bfd_link_hash_defined
2098 && h->root.type != bfd_link_hash_defweak)
2099 /* This appears to be a reference to an undefined
2100 symbol. Just ignore it--it will be caught by the
2101 regular reloc processing. */
2102 continue;
2103
2104 symval = (h->root.u.def.value
2105 + h->root.u.def.section->output_section->vma
2106 + h->root.u.def.section->output_offset);
2107 }
2108
2109 /* For simplicity of coding, we are going to modify the section
2110 contents, the section relocs, and the BFD symbol table. We
2111 must tell the rest of the code not to free up this
2112 information. It would be possible to instead create a table
2113 of changes which have to be made, as is done in coff-mips.c;
2114 that would be more work, but would require less memory when
2115 the linker is run. */
2116
2117 /* Try to turn a 16bit pc-relative branch into a 10bit pc-relative
2118 branch. */
1b786873 2119 /* Paranoia? paranoia... */
23d4663e
NC		 2120 if (! uses_msp430x_relocs (abfd)
2121 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_RL_PCREL)
13761a11
NC		 2122 {
2123 bfd_vma value = symval;
2124
2125 /* Deal with pc-relative gunk. */
2126 value -= (sec->output_section->vma + sec->output_offset);
2127 value -= irel->r_offset;
2128 value += irel->r_addend;
2129
2130 /* See if the value will fit in 10 bits, note the high value is
2131 1016 as the target will be two bytes closer if we are
2132 able to relax. */
2133 if ((long) value < 1016 && (long) value > -1016)
2134 {
2135 int code0 = 0, code1 = 0, code2 = 0;
2136 int i;
2137 struct rcodes_s *rx;
2138
2139 /* Get the opcode. */
2140 if (irel->r_offset >= 6)
2141 code0 = bfd_get_16 (abfd, contents + irel->r_offset - 6);
2142
2143 if (irel->r_offset >= 4)
2144 code1 = bfd_get_16 (abfd, contents + irel->r_offset - 4);
2145
2146 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2);
2147
2148 if (code2 != 0x4010)
2149 continue;
2150
2151 /* Check r4 and r3. */
2152 for (i = NUMB_RELAX_CODES - 1; i >= 0; i--)
2153 {
2154 rx = &rcode[i];
2155 if (rx->cdx == 2 && rx->f0 == code0 && rx->f1 == code1)
2156 break;
2157 else if (rx->cdx == 1 && rx->f1 == code1)
2158 break;
2159 else if (rx->cdx == 0) /* This is an unconditional jump. */
2160 break;
2161 }
2162
2163 /* Check labels:
b18c562e 2164 .Label0: ; we do not care about this label
13761a11 2165 jeq +6
b18c562e 2166 .Label1: ; make sure there is no label here
13761a11 2167 jl +4
b18c562e 2168 .Label2: ; make sure there is no label here
13761a11
NC		 2169 br .Label_dst
2170
2171 So, if there is .Label1 or .Label2 we cannot relax this code.
2172 This actually should not happen, cause for relaxable
2173 instructions we use RL_PCREL reloc instead of 16_PCREL.
2174 Will change this in the future. */
2175
2176 if (rx->cdx > 0
2177 && msp430_elf_symbol_address_p (abfd, sec, isymbuf,
2178 irel->r_offset - 2))
2179 continue;
2180 if (rx->cdx > 1
2181 && msp430_elf_symbol_address_p (abfd, sec, isymbuf,
2182 irel->r_offset - 4))
2183 continue;
2184
2185 /* Note that we've changed the relocs, section contents, etc. */
2186 elf_section_data (sec)->relocs = internal_relocs;
2187 elf_section_data (sec)->this_hdr.contents = contents;
2188 symtab_hdr->contents = (unsigned char *) isymbuf;
2189
2190 /* Fix the relocation's type. */
2191 if (uses_msp430x_relocs (abfd))
2192 {
2193 if (rx->labels == 3) /* Handle special cases. */
2194 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2195 R_MSP430X_2X_PCREL);
2196 else
2197 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2198 R_MSP430X_10_PCREL);
2199 }
2200 else
2201 {
2202 if (rx->labels == 3) /* Handle special cases. */
2203 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2204 R_MSP430_2X_PCREL);
2205 else
2206 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2207 R_MSP430_10_PCREL);
2208 }
2209
2210 /* Fix the opcode right way. */
2211 bfd_put_16 (abfd, rx->t0, contents + irel->r_offset - rx->off);
2212 if (rx->t1)
2213 bfd_put_16 (abfd, rx->t1,
2214 contents + irel->r_offset - rx->off + 2);
2215
2216 /* Delete bytes. */
2217 if (!msp430_elf_relax_delete_bytes (abfd, sec,
2218 irel->r_offset - rx->off +
2219 rx->ncl, rx->bs))
2220 goto error_return;
2221
2222 /* Handle unconditional jumps. */
2223 if (rx->cdx == 0)
2224 irel->r_offset -= 2;
2225
2226 /* That will change things, so, we should relax again.
2227 Note that this is not required, and it may be slow. */
2228 *again = TRUE;
2229 }
2230 }
23d4663e
NC		 2231
2232 /* Try to turn a 16-bit absolute branch into a 10-bit pc-relative
2233 branch. */
133193b8
NC		 2234 if ((uses_msp430x_relocs (abfd)
2235 && ELF32_R_TYPE (irel->r_info) == R_MSP430X_ABS16)
2236 || (! uses_msp430x_relocs (abfd)
2237 && ELF32_R_TYPE (irel->r_info) == R_MSP430_16))
23d4663e
NC		 2238 {
2239 bfd_vma value = symval;
2240
2d071cfc 2241 value -= (sec->output_section->vma + sec->output_offset);
23d4663e
NC		 2242 value -= irel->r_offset;
2243 value += irel->r_addend;
1b786873 2244
23d4663e
NC		 2245 /* See if the value will fit in 10 bits, note the high value is
2246 1016 as the target will be two bytes closer if we are
2247 able to relax. */
2248 if ((long) value < 1016 && (long) value > -1016)
2249 {
2250 int code2;
2251
2252 /* Get the opcode. */
2253 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2);
2254 if (code2 != 0x4030)
2255 continue;
2256 /* FIXME: check r4 and r3 ? */
2257 /* FIXME: Handle 0x4010 as well ? */
2258
2259 /* Note that we've changed the relocs, section contents, etc. */
2260 elf_section_data (sec)->relocs = internal_relocs;
2261 elf_section_data (sec)->this_hdr.contents = contents;
2262 symtab_hdr->contents = (unsigned char *) isymbuf;
2263
2264 /* Fix the relocation's type. */
2265 if (uses_msp430x_relocs (abfd))
2266 {
2267 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2268 R_MSP430X_10_PCREL);
2269 }
2270 else
2271 {
2272 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2273 R_MSP430_10_PCREL);
2274 }
2275
2276 /* Fix the opcode right way. */
2277 bfd_put_16 (abfd, 0x3c00, contents + irel->r_offset - 2);
2278 irel->r_offset -= 2;
2279
2280 /* Delete bytes. */
2281 if (!msp430_elf_relax_delete_bytes (abfd, sec,
2282 irel->r_offset + 2, 2))
2283 goto error_return;
2284
2285 /* That will change things, so, we should relax again.
2286 Note that this is not required, and it may be slow. */
2287 *again = TRUE;
2288 }
2289 }
13761a11 2290 }
b18c562e
NC		 2291
2292 if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf)
2293 {
2294 if (!link_info->keep_memory)
2295 free (isymbuf);
2296 else
2297 {
2298 /* Cache the symbols for elf_link_input_bfd. */
2299 symtab_hdr->contents = (unsigned char *) isymbuf;
2300 }
2301 }
2302
2303 if (contents != NULL
2304 && elf_section_data (sec)->this_hdr.contents != contents)
2305 {
2306 if (!link_info->keep_memory)
2307 free (contents);
2308 else
2309 {
2310 /* Cache the section contents for elf_link_input_bfd. */
2311 elf_section_data (sec)->this_hdr.contents = contents;
2312 }
2313 }
2314
2315 if (internal_relocs != NULL
2316 && elf_section_data (sec)->relocs != internal_relocs)
2317 free (internal_relocs);
2318
2319 return TRUE;
2320
2321error_return:
2322 if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf)
2323 free (isymbuf);
2324 if (contents != NULL
2325 && elf_section_data (sec)->this_hdr.contents != contents)
2326 free (contents);
2327 if (internal_relocs != NULL
2328 && elf_section_data (sec)->relocs != internal_relocs)
2329 free (internal_relocs);
2330
2331 return FALSE;
2332}
2333
13761a11
NC		 2334/* Handle an MSP430 specific section when reading an object file.
2335 This is called when bfd_section_from_shdr finds a section with
2336 an unknown type. */
2337
2338static bfd_boolean
2339elf32_msp430_section_from_shdr (bfd *abfd,
2340 Elf_Internal_Shdr * hdr,
2341 const char *name,
2342 int shindex)
2343{
2344 switch (hdr->sh_type)
2345 {
2346 case SHT_MSP430_SEC_FLAGS:
2347 case SHT_MSP430_SYM_ALIASES:
2348 case SHT_MSP430_ATTRIBUTES:
2349 return _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex);
2350 default:
2351 return FALSE;
2352 }
2353}
2354
2355static bfd_boolean
2356elf32_msp430_obj_attrs_handle_unknown (bfd *abfd, int tag)
2357{
2358 _bfd_error_handler
695344c0 2359 /* xgettext:c-format */
38f14ab8 2360 (_("warning: %pB: unknown MSPABI object attribute %d"),
13761a11
NC		 2361 abfd, tag);
2362 return TRUE;
2363}
2364
2365/* Determine whether an object attribute tag takes an integer, a
2366 string or both. */
2367
2368static int
2369elf32_msp430_obj_attrs_arg_type (int tag)
2370{
2371 if (tag == Tag_compatibility)
2372 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2373
2374 if (tag < 32)
2375 return ATTR_TYPE_FLAG_INT_VAL;
2376
2377 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
2378}
2379
2380static inline const char *
2381isa_type (int isa)
2382{
2383 switch (isa)
2384 {
2385 case 1: return "MSP430";
2386 case 2: return "MSP430X";
2387 default: return "unknown";
2388 }
2389}
2390
2391static inline const char *
2392code_model (int model)
2393{
2394 switch (model)
2395 {
2396 case 1: return "small";
2397 case 2: return "large";
2398 default: return "unknown";
2399 }
2400}
2401
2402static inline const char *
2403data_model (int model)
2404{
2405 switch (model)
2406 {
2407 case 1: return "small";
2408 case 2: return "large";
2409 case 3: return "restricted large";
2410 default: return "unknown";
2411 }
2412}
2413
c0ea7c52 2414/* Merge MSPABI and GNU object attributes from IBFD into OBFD.
13761a11
NC		 2415 Raise an error if there are conflicting attributes. */
2416
2417static bfd_boolean
c0ea7c52 2418elf32_msp430_merge_msp430_attributes (bfd *ibfd, struct bfd_link_info *info)
13761a11 2419{
50e03d47 2420 bfd *obfd = info->output_bfd;
c0ea7c52
JL		 2421 obj_attribute *in_msp_attr, *in_gnu_attr;
2422 obj_attribute *out_msp_attr, *out_gnu_attr;
13761a11
NC		 2423 bfd_boolean result = TRUE;
2424 static bfd * first_input_bfd = NULL;
2425
2426 /* Skip linker created files. */
2427 if (ibfd->flags & BFD_LINKER_CREATED)
2428 return TRUE;
2429
ca94519e
JL		 2430 /* LTO can create temporary files for linking which may not have an attribute
2431 section. */
2432 if (ibfd->lto_output
2433 && bfd_get_section_by_name (ibfd, ".MSP430.attributes") == NULL)
2434 return TRUE;
2435
13761a11
NC		 2436 /* If this is the first real object just copy the attributes. */
2437 if (!elf_known_obj_attributes_proc (obfd)[0].i)
2438 {
2439 _bfd_elf_copy_obj_attributes (ibfd, obfd);
2440
c0ea7c52 2441 out_msp_attr = elf_known_obj_attributes_proc (obfd);
13761a11
NC		 2442
2443 /* Use the Tag_null value to indicate that
2444 the attributes have been initialized. */
c0ea7c52 2445 out_msp_attr[0].i = 1;
13761a11
NC		 2446
2447 first_input_bfd = ibfd;
2448 return TRUE;
2449 }
2450
c0ea7c52
JL		 2451 in_msp_attr = elf_known_obj_attributes_proc (ibfd);
2452 out_msp_attr = elf_known_obj_attributes_proc (obfd);
2453 in_gnu_attr = elf_known_obj_attributes (ibfd) [OBJ_ATTR_GNU];
2454 out_gnu_attr = elf_known_obj_attributes (obfd) [OBJ_ATTR_GNU];
13761a11
NC		 2455
2456 /* The ISAs must be the same. */
c0ea7c52 2457 if (in_msp_attr[OFBA_MSPABI_Tag_ISA].i != out_msp_attr[OFBA_MSPABI_Tag_ISA].i)
13761a11
NC		 2458 {
2459 _bfd_error_handler
695344c0 2460 /* xgettext:c-format */
871b3ab2 2461 (_("error: %pB uses %s instructions but %pB uses %s"),
c0ea7c52
JL		 2462 ibfd, isa_type (in_msp_attr[OFBA_MSPABI_Tag_ISA].i),
2463 first_input_bfd, isa_type (out_msp_attr[OFBA_MSPABI_Tag_ISA].i));
13761a11
NC		 2464 result = FALSE;
2465 }
2466
2467 /* The code models must be the same. */
c0ea7c52
JL		 2468 if (in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i
2469 != out_msp_attr[OFBA_MSPABI_Tag_Code_Model].i)
13761a11
NC		 2470 {
2471 _bfd_error_handler
695344c0 2472 /* xgettext:c-format */
871b3ab2 2473 (_("error: %pB uses the %s code model whereas %pB uses the %s code model"),
c0ea7c52
JL		 2474 ibfd, code_model (in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i),
2475 first_input_bfd,
2476 code_model (out_msp_attr[OFBA_MSPABI_Tag_Code_Model].i));
13761a11
NC		 2477 result = FALSE;
2478 }
2479
2480 /* The large code model is only supported by the MSP430X. */
c0ea7c52
JL		 2481 if (in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i == 2
2482 && out_msp_attr[OFBA_MSPABI_Tag_ISA].i != 2)
13761a11
NC		 2483 {
2484 _bfd_error_handler
695344c0 2485 /* xgettext:c-format */
871b3ab2 2486 (_("error: %pB uses the large code model but %pB uses MSP430 instructions"),
13761a11
NC		 2487 ibfd, first_input_bfd);
2488 result = FALSE;
2489 }
2490
2491 /* The data models must be the same. */
c0ea7c52
JL		 2492 if (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i
2493 != out_msp_attr[OFBA_MSPABI_Tag_Data_Model].i)
13761a11
NC		 2494 {
2495 _bfd_error_handler
695344c0 2496 /* xgettext:c-format */
871b3ab2 2497 (_("error: %pB uses the %s data model whereas %pB uses the %s data model"),
c0ea7c52
JL		 2498 ibfd, data_model (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i),
2499 first_input_bfd,
2500 data_model (out_msp_attr[OFBA_MSPABI_Tag_Data_Model].i));
13761a11
NC		 2501 result = FALSE;
2502 }
2503
2504 /* The small code model requires the use of the small data model. */
c0ea7c52
JL		 2505 if (in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i == 1
2506 && out_msp_attr[OFBA_MSPABI_Tag_Data_Model].i != 1)
13761a11
NC		 2507 {
2508 _bfd_error_handler
695344c0 2509 /* xgettext:c-format */
871b3ab2 2510 (_("error: %pB uses the small code model but %pB uses the %s data model"),
13761a11 2511 ibfd, first_input_bfd,
c0ea7c52 2512 data_model (out_msp_attr[OFBA_MSPABI_Tag_Data_Model].i));
13761a11
NC		 2513 result = FALSE;
2514 }
2515
2516 /* The large data models are only supported by the MSP430X. */
c0ea7c52
JL		 2517 if (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i > 1
2518 && out_msp_attr[OFBA_MSPABI_Tag_ISA].i != 2)
13761a11
NC		 2519 {
2520 _bfd_error_handler
695344c0 2521 /* xgettext:c-format */
871b3ab2 2522 (_("error: %pB uses the %s data model but %pB only uses MSP430 instructions"),
c0ea7c52 2523 ibfd, data_model (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i),
c08bb8dd 2524 first_input_bfd);
13761a11
NC		 2525 result = FALSE;
2526 }
1b786873 2527
c0ea7c52
JL		 2528 /* Just ignore the data region unless the large memory model is in use.
2529 We have already checked that ibfd and obfd use the same memory model. */
2530 if ((in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i
2531 == OFBA_MSPABI_Val_Code_Model_LARGE)
2532 && (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i
2533 == OFBA_MSPABI_Val_Data_Model_LARGE))
2534 {
2535 /* We cannot allow "lower region only" to be linked with any other
2536 values (i.e. ANY or NONE).
2537 Before this attribute existed, "ANY" region was the default. */
2538 bfd_boolean ibfd_lower_region_used
2539 = (in_gnu_attr[Tag_GNU_MSP430_Data_Region].i
2540 == Val_GNU_MSP430_Data_Region_Lower);
2541 bfd_boolean obfd_lower_region_used
2542 = (out_gnu_attr[Tag_GNU_MSP430_Data_Region].i
2543 == Val_GNU_MSP430_Data_Region_Lower);
2544 if (ibfd_lower_region_used != obfd_lower_region_used)
2545 {
2546 _bfd_error_handler
2547 (_("error: %pB can use the upper region for data, "
2548 "but %pB assumes data is exclusively in lower memory"),
2549 ibfd_lower_region_used ? obfd : ibfd,
2550 ibfd_lower_region_used ? ibfd : obfd);
2551 result = FALSE;
2552 }
2553 }
2554
13761a11
NC		 2555 return result;
2556}
2557
2558/* Merge backend specific data from an object file to the output
2559 object file when linking. */
2560
2561static bfd_boolean
50e03d47 2562elf32_msp430_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
13761a11 2563{
50e03d47 2564 bfd *obfd = info->output_bfd;
13761a11
NC		 2565 /* Make sure that the machine number reflects the most
2566 advanced version of the MSP architecture required. */
2567#define max(a,b) ((a) > (b) ? (a) : (b))
2568 if (bfd_get_mach (ibfd) != bfd_get_mach (obfd))
2569 bfd_default_set_arch_mach (obfd, bfd_get_arch (obfd),
2570 max (bfd_get_mach (ibfd), bfd_get_mach (obfd)));
2571#undef max
2572
c0ea7c52 2573 return elf32_msp430_merge_msp430_attributes (ibfd, info);
13761a11
NC		 2574}
2575
13761a11
NC		 2576static bfd_boolean
2577msp430_elf_is_target_special_symbol (bfd *abfd, asymbol *sym)
2578{
2579 return _bfd_elf_is_local_label_name (abfd, sym->name);
2580}
2581
79559014
NC		 2582static bfd_boolean
2583uses_large_model (bfd *abfd)
2584{
2585 obj_attribute * attr;
2586
2587 if (abfd->flags & BFD_LINKER_CREATED)
2588 return FALSE;
2589
2590 attr = elf_known_obj_attributes_proc (abfd);
2591 if (attr == NULL)
2592 return FALSE;
2593
2594 return attr[OFBA_MSPABI_Tag_Code_Model].i == 2;
2595}
2596
2597static unsigned int
76c20d54
AM		 2598elf32_msp430_eh_frame_address_size (bfd *abfd,
2599 const asection *sec ATTRIBUTE_UNUSED)
79559014
NC		 2600{
2601 return uses_large_model (abfd) ? 4 : 2;
2602}
2603
13761a11
NC		 2604/* This is gross. The MSP430 EABI says that (sec 11.5):
2605
2606 "An implementation may choose to use Rel or Rela
2607 type relocations for other relocations."
2608
2609 But it also says that:
1b786873 2610
13761a11
NC		 2611 "Certain relocations are identified as Rela only. [snip]
2612 Where Rela is specified, an implementation must honor
2613 this requirement."
2614
2615 There is one relocation marked as requiring RELA - R_MSP430_ABS_HI16 - but
2616 to keep things simple we choose to use RELA relocations throughout. The
2617 problem is that the TI compiler generates REL relocations, so we have to
2618 be able to accept those as well. */
2619
2620#define elf_backend_may_use_rel_p 1
2621#define elf_backend_may_use_rela_p 1
2622#define elf_backend_default_use_rela_p 1
2623
07d6d2b8 2624#undef elf_backend_obj_attrs_vendor
13761a11 2625#define elf_backend_obj_attrs_vendor "mspabi"
07d6d2b8 2626#undef elf_backend_obj_attrs_section
13761a11 2627#define elf_backend_obj_attrs_section ".MSP430.attributes"
07d6d2b8 2628#undef elf_backend_obj_attrs_section_type
13761a11 2629#define elf_backend_obj_attrs_section_type SHT_MSP430_ATTRIBUTES
07d6d2b8
AM		 2630#define elf_backend_section_from_shdr elf32_msp430_section_from_shdr
2631#define elf_backend_obj_attrs_handle_unknown elf32_msp430_obj_attrs_handle_unknown
2632#undef elf_backend_obj_attrs_arg_type
13761a11 2633#define elf_backend_obj_attrs_arg_type elf32_msp430_obj_attrs_arg_type
13761a11 2634#define bfd_elf32_bfd_merge_private_bfd_data elf32_msp430_merge_private_bfd_data
79559014 2635#define elf_backend_eh_frame_address_size elf32_msp430_eh_frame_address_size
2469cfa2
NC		 2636
2637#define ELF_ARCH bfd_arch_msp430
2638#define ELF_MACHINE_CODE EM_MSP430
2639#define ELF_MACHINE_ALT1 EM_MSP430_OLD
13761a11 2640#define ELF_MAXPAGESIZE 4
d1036acb 2641#define ELF_OSABI ELFOSABI_STANDALONE
2469cfa2 2642
07d6d2b8 2643#define TARGET_LITTLE_SYM msp430_elf32_vec
2469cfa2
NC		 2644#define TARGET_LITTLE_NAME "elf32-msp430"
2645
07d6d2b8
AM		 2646#define elf_info_to_howto msp430_info_to_howto_rela
2647#define elf_info_to_howto_rel NULL
2648#define elf_backend_relocate_section elf32_msp430_relocate_section
2649#define elf_backend_check_relocs elf32_msp430_check_relocs
2650#define elf_backend_can_gc_sections 1
2469cfa2
NC		 2651#define elf_backend_final_write_processing bfd_elf_msp430_final_write_processing
2652#define elf_backend_object_p elf32_msp430_object_p
b18c562e 2653#define bfd_elf32_bfd_relax_section msp430_elf_relax_section
13761a11
NC		 2654#define bfd_elf32_bfd_is_target_special_symbol msp430_elf_is_target_special_symbol
2655
07d6d2b8 2656#undef elf32_bed
13761a11
NC		 2657#define elf32_bed elf32_msp430_bed
2658
2659#include "elf32-target.h"
2660
2661/* The TI compiler sets the OSABI field to ELFOSABI_NONE. */
07d6d2b8
AM		 2662#undef TARGET_LITTLE_SYM
2663#define TARGET_LITTLE_SYM msp430_elf32_ti_vec
13761a11 2664
07d6d2b8 2665#undef elf32_bed
13761a11
NC		 2666#define elf32_bed elf32_msp430_ti_bed
2667
1b786873 2668#undef ELF_OSABI
13761a11
NC		 2669#define ELF_OSABI ELFOSABI_NONE
2670
2671static const struct bfd_elf_special_section msp430_ti_elf_special_sections[] =
2672{
07d6d2b8 2673 /* prefix, prefix_length, suffix_len, type, attributes. */
13761a11
NC		 2674 { STRING_COMMA_LEN (".TI.symbol.alias"), 0, SHT_MSP430_SYM_ALIASES, 0 },
2675 { STRING_COMMA_LEN (".TI.section.flags"), 0, SHT_MSP430_SEC_FLAGS, 0 },
2676 { STRING_COMMA_LEN ("_TI_build_attrib"), 0, SHT_MSP430_ATTRIBUTES, 0 },
07d6d2b8 2677 { NULL, 0, 0, 0, 0 }
13761a11 2678};
2469cfa2 2679
07d6d2b8
AM		 2680#undef elf_backend_special_sections
2681#define elf_backend_special_sections msp430_ti_elf_special_sections
b6518b38 2682
2469cfa2 2683#include "elf32-target.h"
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