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[thirdparty/binutils-gdb.git] / bfd / elf32-msp430.c
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2469cfa2 1/* MSP430-specific support for 32-bit ELF
fd67aa11 2 Copyright (C) 2002-2024 Free Software Foundation, Inc.
2469cfa2
NC		 3 Contributed by Dmitry Diky <diwil@mail.ru>
4
5 This file is part of BFD, the Binary File Descriptor library.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
cd123cb7 9 the Free Software Foundation; either version 3 of the License, or
2469cfa2
NC		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
cd123cb7
NC		 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
2469cfa2 21
2469cfa2 22#include "sysdep.h"
3db64b00 23#include "bfd.h"
2469cfa2
NC		 24#include "libiberty.h"
25#include "libbfd.h"
26#include "elf-bfd.h"
27#include "elf/msp430.h"
28
0a1b45a2 29static bool debug_relocs = 0;
d60f5448 30
bb294208
AM		 31/* All users of this file have bfd_octets_per_byte (abfd, sec) == 1. */
32#define OCTETS_PER_BYTE(ABFD, SEC) 1
33
1ade7175
NC		 34static bfd_reloc_status_type
35rl78_sym_diff_handler (bfd * abfd,
36 arelent * reloc,
37 asymbol * sym ATTRIBUTE_UNUSED,
38 void * addr ATTRIBUTE_UNUSED,
39 asection * input_sec,
40 bfd * out_bfd ATTRIBUTE_UNUSED,
41 char ** error_message ATTRIBUTE_UNUSED)
42{
43 bfd_size_type octets;
bb294208 44 octets = reloc->address * OCTETS_PER_BYTE (abfd, input_sec);
1ade7175
NC		 45
46 /* Catch the case where bfd_install_relocation would return
47 bfd_reloc_outofrange because the SYM_DIFF reloc is being used in a very
48 small section. It does not actually matter if this happens because all
49 that SYM_DIFF does is compute a (4-byte) value. A second reloc then uses
50 this value, and it is that reloc that must fit into the section.
51
52 This happens in eg, gcc/testsuite/gcc.c-torture/compile/labels-3.c. */
53 if ((octets + bfd_get_reloc_size (reloc->howto))
54 > bfd_get_section_limit_octets (abfd, input_sec))
55 return bfd_reloc_ok;
56 return bfd_reloc_continue;
57}
58
7d81bc93
JL		 59/* Special handler for relocations which don't have to be relocated.
60 This function just simply returns bfd_reloc_ok. */
61static bfd_reloc_status_type
62msp430_elf_ignore_reloc (bfd *abfd ATTRIBUTE_UNUSED, arelent *reloc_entry,
63 asymbol *symbol ATTRIBUTE_UNUSED,
64 void *data ATTRIBUTE_UNUSED, asection *input_section,
65 bfd *output_bfd, char **error_message ATTRIBUTE_UNUSED)
66{
67 if (output_bfd != NULL)
68 reloc_entry->address += input_section->output_offset;
69
70 return bfd_reloc_ok;
71}
72
2469cfa2
NC		 73static reloc_howto_type elf_msp430_howto_table[] =
74{
75 HOWTO (R_MSP430_NONE, /* type */
76 0, /* rightshift */
c94cb026 77 0, /* size */
6346d5ca 78 0, /* bitsize */
0a1b45a2 79 false, /* pc_relative */
2469cfa2 80 0, /* bitpos */
6346d5ca 81 complain_overflow_dont,/* complain_on_overflow */
2469cfa2
NC		 82 bfd_elf_generic_reloc, /* special_function */
83 "R_MSP430_NONE", /* name */
0a1b45a2 84 false, /* partial_inplace */
2469cfa2
NC		 85 0, /* src_mask */
86 0, /* dst_mask */
0a1b45a2 87 false), /* pcrel_offset */
2469cfa2
NC		 88
89 HOWTO (R_MSP430_32, /* type */
90 0, /* rightshift */
c94cb026 91 4, /* size */
2469cfa2 92 32, /* bitsize */
0a1b45a2 93 false, /* pc_relative */
2469cfa2 94 0, /* bitpos */
b18c562e 95 complain_overflow_bitfield,/* complain_on_overflow */
2469cfa2
NC		 96 bfd_elf_generic_reloc, /* special_function */
97 "R_MSP430_32", /* name */
0a1b45a2 98 false, /* partial_inplace */
2469cfa2
NC		 99 0xffffffff, /* src_mask */
100 0xffffffff, /* dst_mask */
0a1b45a2 101 false), /* pcrel_offset */
2469cfa2 102
df301bfc 103 /* A 10 bit PC relative relocation. */
2469cfa2
NC		 104 HOWTO (R_MSP430_10_PCREL, /* type */
105 1, /* rightshift */
c94cb026 106 2, /* size */
2469cfa2 107 10, /* bitsize */
0a1b45a2 108 true, /* pc_relative */
2469cfa2 109 0, /* bitpos */
b18c562e 110 complain_overflow_bitfield,/* complain_on_overflow */
2469cfa2 111 bfd_elf_generic_reloc, /* special_function */
13761a11 112 "R_MSP430_10_PCREL", /* name */
0a1b45a2 113 false, /* partial_inplace */
df301bfc
NC		 114 0x3ff, /* src_mask */
115 0x3ff, /* dst_mask */
0a1b45a2 116 true), /* pcrel_offset */
2469cfa2
NC		 117
118 /* A 16 bit absolute relocation. */
119 HOWTO (R_MSP430_16, /* type */
120 0, /* rightshift */
c94cb026 121 2, /* size */
2469cfa2 122 16, /* bitsize */
0a1b45a2 123 false, /* pc_relative */
2469cfa2
NC		 124 0, /* bitpos */
125 complain_overflow_dont,/* complain_on_overflow */
126 bfd_elf_generic_reloc, /* special_function */
127 "R_MSP430_16", /* name */
0a1b45a2 128 false, /* partial_inplace */
b18c562e 129 0, /* src_mask */
2469cfa2 130 0xffff, /* dst_mask */
0a1b45a2 131 false), /* pcrel_offset */
2469cfa2 132
13761a11 133 /* A 16 bit PC relative relocation for command address. */
2469cfa2
NC		 134 HOWTO (R_MSP430_16_PCREL, /* type */
135 1, /* rightshift */
c94cb026 136 2, /* size */
2469cfa2 137 16, /* bitsize */
0a1b45a2 138 true, /* pc_relative */
2469cfa2
NC		 139 0, /* bitpos */
140 complain_overflow_dont,/* complain_on_overflow */
141 bfd_elf_generic_reloc, /* special_function */
142 "R_MSP430_16_PCREL", /* name */
0a1b45a2 143 false, /* partial_inplace */
b18c562e 144 0, /* src_mask */
2469cfa2 145 0xffff, /* dst_mask */
0a1b45a2 146 true), /* pcrel_offset */
2469cfa2
NC		 147
148 /* A 16 bit absolute relocation, byte operations. */
149 HOWTO (R_MSP430_16_BYTE, /* type */
150 0, /* rightshift */
c94cb026 151 2, /* size */
2469cfa2 152 16, /* bitsize */
0a1b45a2 153 false, /* pc_relative */
2469cfa2
NC		 154 0, /* bitpos */
155 complain_overflow_dont,/* complain_on_overflow */
156 bfd_elf_generic_reloc, /* special_function */
157 "R_MSP430_16_BYTE", /* name */
0a1b45a2 158 false, /* partial_inplace */
2469cfa2
NC		 159 0xffff, /* src_mask */
160 0xffff, /* dst_mask */
0a1b45a2 161 false), /* pcrel_offset */
2469cfa2
NC		 162
163 /* A 16 bit absolute relocation for command address. */
164 HOWTO (R_MSP430_16_PCREL_BYTE,/* type */
165 1, /* rightshift */
c94cb026 166 2, /* size */
2469cfa2 167 16, /* bitsize */
0a1b45a2 168 true, /* pc_relative */
2469cfa2
NC		 169 0, /* bitpos */
170 complain_overflow_dont,/* complain_on_overflow */
171 bfd_elf_generic_reloc, /* special_function */
b18c562e 172 "R_MSP430_16_PCREL_BYTE",/* name */
0a1b45a2 173 false, /* partial_inplace */
2469cfa2
NC		 174 0xffff, /* src_mask */
175 0xffff, /* dst_mask */
0a1b45a2 176 true), /* pcrel_offset */
b18c562e 177
df301bfc 178 /* A 10 bit PC relative relocation for complicated polymorphs. */
b18c562e
NC		 179 HOWTO (R_MSP430_2X_PCREL, /* type */
180 1, /* rightshift */
c94cb026 181 4, /* size */
b18c562e 182 10, /* bitsize */
0a1b45a2 183 true, /* pc_relative */
b18c562e
NC		 184 0, /* bitpos */
185 complain_overflow_bitfield,/* complain_on_overflow */
186 bfd_elf_generic_reloc, /* special_function */
187 "R_MSP430_2X_PCREL", /* name */
0a1b45a2 188 false, /* partial_inplace */
df301bfc
NC		 189 0x3ff, /* src_mask */
190 0x3ff, /* dst_mask */
0a1b45a2 191 true), /* pcrel_offset */
b18c562e
NC		 192
193 /* A 16 bit relaxable relocation for command address. */
194 HOWTO (R_MSP430_RL_PCREL, /* type */
195 1, /* rightshift */
c94cb026 196 2, /* size */
b18c562e 197 16, /* bitsize */
0a1b45a2 198 true, /* pc_relative */
b18c562e
NC		 199 0, /* bitpos */
200 complain_overflow_dont,/* complain_on_overflow */
201 bfd_elf_generic_reloc, /* special_function */
202 "R_MSP430_RL_PCREL", /* name */
0a1b45a2 203 false, /* partial_inplace */
b18c562e
NC		 204 0, /* src_mask */
205 0xffff, /* dst_mask */
0a1b45a2 206 true) /* pcrel_offset */
13761a11
NC		 207
208 /* A 8-bit absolute relocation. */
209 , HOWTO (R_MSP430_8, /* type */
210 0, /* rightshift */
c94cb026 211 1, /* size */
13761a11 212 8, /* bitsize */
0a1b45a2 213 false, /* pc_relative */
13761a11
NC		 214 0, /* bitpos */
215 complain_overflow_dont,/* complain_on_overflow */
216 bfd_elf_generic_reloc, /* special_function */
217 "R_MSP430_8", /* name */
0a1b45a2 218 false, /* partial_inplace */
13761a11
NC		 219 0, /* src_mask */
220 0xffff, /* dst_mask */
0a1b45a2 221 false), /* pcrel_offset */
13761a11
NC		 222
223 /* Together with a following reloc, allows for the difference
224 between two symbols to be the real addend of the second reloc. */
225 HOWTO (R_MSP430_SYM_DIFF, /* type */
226 0, /* rightshift */
c94cb026 227 4, /* size */
13761a11 228 32, /* bitsize */
0a1b45a2 229 false, /* pc_relative */
13761a11
NC		 230 0, /* bitpos */
231 complain_overflow_dont,/* complain_on_overflow */
1ade7175 232 rl78_sym_diff_handler, /* special handler. */
13761a11 233 "R_MSP430_SYM_DIFF", /* name */
0a1b45a2 234 false, /* partial_inplace */
13761a11
NC		 235 0xffffffff, /* src_mask */
236 0xffffffff, /* dst_mask */
0a1b45a2 237 false), /* pcrel_offset */
7d81bc93
JL		 238
239 /* The length of unsigned-leb128 is variable, just assume the
240 size is one byte here. */
241 HOWTO (R_MSP430_GNU_SET_ULEB128, /* type */
242 0, /* rightshift */
c94cb026 243 1, /* size */
7d81bc93 244 0, /* bitsize */
0a1b45a2 245 false, /* pc_relative */
7d81bc93
JL		 246 0, /* bitpos */
247 complain_overflow_dont, /* complain_on_overflow */
248 msp430_elf_ignore_reloc, /* special handler. */
249 "R_MSP430_GNU_SET_ULEB128", /* name */
0a1b45a2 250 false, /* partial_inplace */
7d81bc93
JL		 251 0, /* src_mask */
252 0, /* dst_mask */
0a1b45a2 253 false), /* pcrel_offset */
7d81bc93
JL		 254
255 /* The length of unsigned-leb128 is variable, just assume the
256 size is one byte here. */
257 HOWTO (R_MSP430_GNU_SUB_ULEB128, /* type */
258 0, /* rightshift */
c94cb026 259 1, /* size */
7d81bc93 260 0, /* bitsize */
0a1b45a2 261 false, /* pc_relative */
7d81bc93
JL		 262 0, /* bitpos */
263 complain_overflow_dont, /* complain_on_overflow */
264 msp430_elf_ignore_reloc, /* special handler. */
265 "R_MSP430_GNU_SUB_ULEB128", /* name */
0a1b45a2 266 false, /* partial_inplace */
7d81bc93
JL		 267 0, /* src_mask */
268 0, /* dst_mask */
0a1b45a2 269 false), /* pcrel_offset */
7d81bc93 270
13761a11
NC		 271};
272
273static reloc_howto_type elf_msp430x_howto_table[] =
274{
275 HOWTO (R_MSP430_NONE, /* type */
276 0, /* rightshift */
c94cb026 277 0, /* size */
6346d5ca 278 0, /* bitsize */
0a1b45a2 279 false, /* pc_relative */
13761a11 280 0, /* bitpos */
6346d5ca 281 complain_overflow_dont,/* complain_on_overflow */
13761a11
NC		 282 bfd_elf_generic_reloc, /* special_function */
283 "R_MSP430_NONE", /* name */
0a1b45a2 284 false, /* partial_inplace */
13761a11
NC		 285 0, /* src_mask */
286 0, /* dst_mask */
0a1b45a2 287 false), /* pcrel_offset */
13761a11
NC		 288
289 HOWTO (R_MSP430_ABS32, /* type */
290 0, /* rightshift */
c94cb026 291 4, /* size */
13761a11 292 32, /* bitsize */
0a1b45a2 293 false, /* pc_relative */
13761a11
NC		 294 0, /* bitpos */
295 complain_overflow_bitfield,/* complain_on_overflow */
296 bfd_elf_generic_reloc, /* special_function */
297 "R_MSP430_ABS32", /* name */
0a1b45a2 298 false, /* partial_inplace */
13761a11
NC		 299 0xffffffff, /* src_mask */
300 0xffffffff, /* dst_mask */
0a1b45a2 301 false), /* pcrel_offset */
13761a11
NC		 302
303 HOWTO (R_MSP430_ABS16, /* type */
304 0, /* rightshift */
c94cb026 305 2, /* size */
13761a11 306 16, /* bitsize */
0a1b45a2 307 false, /* pc_relative */
13761a11
NC		 308 0, /* bitpos */
309 complain_overflow_dont,/* complain_on_overflow */
310 bfd_elf_generic_reloc, /* special_function */
311 "R_MSP430_ABS16", /* name */
0a1b45a2 312 false, /* partial_inplace */
13761a11
NC		 313 0, /* src_mask */
314 0xffff, /* dst_mask */
0a1b45a2 315 false), /* pcrel_offset */
13761a11
NC		 316
317 HOWTO (R_MSP430_ABS8, /* type */
318 0, /* rightshift */
c94cb026 319 1, /* size */
13761a11 320 8, /* bitsize */
0a1b45a2 321 false, /* pc_relative */
13761a11
NC		 322 0, /* bitpos */
323 complain_overflow_bitfield,/* complain_on_overflow */
324 bfd_elf_generic_reloc, /* special_function */
325 "R_MSP430_ABS8", /* name */
0a1b45a2 326 false, /* partial_inplace */
13761a11
NC		 327 0xff, /* src_mask */
328 0xff, /* dst_mask */
0a1b45a2 329 false), /* pcrel_offset */
13761a11
NC		 330
331 HOWTO (R_MSP430_PCR16, /* type */
332 1, /* rightshift */
c94cb026 333 2, /* size */
13761a11 334 16, /* bitsize */
0a1b45a2 335 true, /* pc_relative */
13761a11
NC		 336 0, /* bitpos */
337 complain_overflow_dont,/* complain_on_overflow */
338 bfd_elf_generic_reloc, /* special_function */
339 "R_MSP430_PCR16", /* name */
0a1b45a2 340 false, /* partial_inplace */
13761a11
NC		 341 0, /* src_mask */
342 0xffff, /* dst_mask */
0a1b45a2 343 true), /* pcrel_offset */
13761a11
NC		 344
345 HOWTO (R_MSP430X_PCR20_EXT_SRC,/* type */
346 0, /* rightshift */
c94cb026 347 4, /* size */
13761a11 348 32, /* bitsize */
0a1b45a2 349 true, /* pc_relative */
13761a11
NC		 350 0, /* bitpos */
351 complain_overflow_dont,/* complain_on_overflow */
352 bfd_elf_generic_reloc, /* special_function */
353 "R_MSP430X_PCR20_EXT_SRC",/* name */
0a1b45a2 354 false, /* partial_inplace */
13761a11
NC		 355 0, /* src_mask */
356 0xffff, /* dst_mask */
0a1b45a2 357 true), /* pcrel_offset */
13761a11
NC		 358
359 HOWTO (R_MSP430X_PCR20_EXT_DST,/* type */
360 0, /* rightshift */
c94cb026 361 4, /* size */
13761a11 362 32, /* bitsize */
0a1b45a2 363 true, /* pc_relative */
13761a11
NC		 364 0, /* bitpos */
365 complain_overflow_dont,/* complain_on_overflow */
366 bfd_elf_generic_reloc, /* special_function */
367 "R_MSP430X_PCR20_EXT_DST",/* name */
0a1b45a2 368 false, /* partial_inplace */
13761a11
NC		 369 0, /* src_mask */
370 0xffff, /* dst_mask */
0a1b45a2 371 true), /* pcrel_offset */
13761a11
NC		 372
373 HOWTO (R_MSP430X_PCR20_EXT_ODST,/* type */
374 0, /* rightshift */
c94cb026 375 4, /* size */
13761a11 376 32, /* bitsize */
0a1b45a2 377 true, /* pc_relative */
13761a11
NC		 378 0, /* bitpos */
379 complain_overflow_dont,/* complain_on_overflow */
380 bfd_elf_generic_reloc, /* special_function */
381 "R_MSP430X_PCR20_EXT_ODST",/* name */
0a1b45a2 382 false, /* partial_inplace */
13761a11
NC		 383 0, /* src_mask */
384 0xffff, /* dst_mask */
0a1b45a2 385 true), /* pcrel_offset */
13761a11
NC		 386
387 HOWTO (R_MSP430X_ABS20_EXT_SRC,/* type */
388 0, /* rightshift */
c94cb026 389 4, /* size */
13761a11 390 32, /* bitsize */
0a1b45a2 391 true, /* pc_relative */
13761a11
NC		 392 0, /* bitpos */
393 complain_overflow_dont,/* complain_on_overflow */
394 bfd_elf_generic_reloc, /* special_function */
395 "R_MSP430X_ABS20_EXT_SRC",/* name */
0a1b45a2 396 false, /* partial_inplace */
13761a11
NC		 397 0, /* src_mask */
398 0xffff, /* dst_mask */
0a1b45a2 399 true), /* pcrel_offset */
13761a11
NC		 400
401 HOWTO (R_MSP430X_ABS20_EXT_DST,/* type */
402 0, /* rightshift */
c94cb026 403 4, /* size */
13761a11 404 32, /* bitsize */
0a1b45a2 405 true, /* pc_relative */
13761a11
NC		 406 0, /* bitpos */
407 complain_overflow_dont,/* complain_on_overflow */
408 bfd_elf_generic_reloc, /* special_function */
409 "R_MSP430X_ABS20_EXT_DST",/* name */
0a1b45a2 410 false, /* partial_inplace */
13761a11
NC		 411 0, /* src_mask */
412 0xffff, /* dst_mask */
0a1b45a2 413 true), /* pcrel_offset */
13761a11
NC		 414
415 HOWTO (R_MSP430X_ABS20_EXT_ODST,/* type */
416 0, /* rightshift */
c94cb026 417 4, /* size */
13761a11 418 32, /* bitsize */
0a1b45a2 419 true, /* pc_relative */
13761a11
NC		 420 0, /* bitpos */
421 complain_overflow_dont,/* complain_on_overflow */
422 bfd_elf_generic_reloc, /* special_function */
423 "R_MSP430X_ABS20_EXT_ODST",/* name */
0a1b45a2 424 false, /* partial_inplace */
13761a11
NC		 425 0, /* src_mask */
426 0xffff, /* dst_mask */
0a1b45a2 427 true), /* pcrel_offset */
13761a11
NC		 428
429 HOWTO (R_MSP430X_ABS20_ADR_SRC,/* type */
430 0, /* rightshift */
c94cb026 431 4, /* size */
13761a11 432 32, /* bitsize */
0a1b45a2 433 true, /* pc_relative */
13761a11
NC		 434 0, /* bitpos */
435 complain_overflow_dont,/* complain_on_overflow */
436 bfd_elf_generic_reloc, /* special_function */
437 "R_MSP430X_ABS20_ADR_SRC",/* name */
0a1b45a2 438 false, /* partial_inplace */
13761a11
NC		 439 0, /* src_mask */
440 0xffff, /* dst_mask */
0a1b45a2 441 true), /* pcrel_offset */
13761a11
NC		 442
443 HOWTO (R_MSP430X_ABS20_ADR_DST,/* type */
444 0, /* rightshift */
c94cb026 445 4, /* size */
13761a11 446 32, /* bitsize */
0a1b45a2 447 true, /* pc_relative */
13761a11
NC		 448 0, /* bitpos */
449 complain_overflow_dont,/* complain_on_overflow */
450 bfd_elf_generic_reloc, /* special_function */
451 "R_MSP430X_ABS20_ADR_DST",/* name */
0a1b45a2 452 false, /* partial_inplace */
13761a11
NC		 453 0, /* src_mask */
454 0xffff, /* dst_mask */
0a1b45a2 455 true), /* pcrel_offset */
13761a11
NC		 456
457 HOWTO (R_MSP430X_PCR16, /* type */
458 0, /* rightshift */
c94cb026 459 4, /* size */
13761a11 460 32, /* bitsize */
0a1b45a2 461 true, /* pc_relative */
13761a11
NC		 462 0, /* bitpos */
463 complain_overflow_dont,/* complain_on_overflow */
464 bfd_elf_generic_reloc, /* special_function */
465 "R_MSP430X_PCR16", /* name */
0a1b45a2 466 false, /* partial_inplace */
13761a11
NC		 467 0, /* src_mask */
468 0xffff, /* dst_mask */
0a1b45a2 469 true), /* pcrel_offset */
13761a11
NC		 470
471 HOWTO (R_MSP430X_PCR20_CALL, /* type */
472 0, /* rightshift */
c94cb026 473 4, /* size */
13761a11 474 32, /* bitsize */
0a1b45a2 475 true, /* pc_relative */
13761a11
NC		 476 0, /* bitpos */
477 complain_overflow_dont,/* complain_on_overflow */
478 bfd_elf_generic_reloc, /* special_function */
479 "R_MSP430X_PCR20_CALL",/* name */
0a1b45a2 480 false, /* partial_inplace */
13761a11
NC		 481 0, /* src_mask */
482 0xffff, /* dst_mask */
0a1b45a2 483 true), /* pcrel_offset */
13761a11
NC		 484
485 HOWTO (R_MSP430X_ABS16, /* type */
486 0, /* rightshift */
c94cb026 487 4, /* size */
13761a11 488 32, /* bitsize */
0a1b45a2 489 true, /* pc_relative */
13761a11
NC		 490 0, /* bitpos */
491 complain_overflow_dont,/* complain_on_overflow */
492 bfd_elf_generic_reloc, /* special_function */
493 "R_MSP430X_ABS16", /* name */
0a1b45a2 494 false, /* partial_inplace */
13761a11
NC		 495 0, /* src_mask */
496 0xffff, /* dst_mask */
0a1b45a2 497 true), /* pcrel_offset */
13761a11
NC		 498
499 HOWTO (R_MSP430_ABS_HI16, /* type */
500 0, /* rightshift */
c94cb026 501 4, /* size */
13761a11 502 32, /* bitsize */
0a1b45a2 503 true, /* pc_relative */
13761a11
NC		 504 0, /* bitpos */
505 complain_overflow_dont,/* complain_on_overflow */
506 bfd_elf_generic_reloc, /* special_function */
507 "R_MSP430_ABS_HI16", /* name */
0a1b45a2 508 false, /* partial_inplace */
13761a11
NC		 509 0, /* src_mask */
510 0xffff, /* dst_mask */
0a1b45a2 511 true), /* pcrel_offset */
13761a11
NC		 512
513 HOWTO (R_MSP430_PREL31, /* type */
514 0, /* rightshift */
c94cb026 515 4, /* size */
13761a11 516 32, /* bitsize */
0a1b45a2 517 true, /* pc_relative */
13761a11
NC		 518 0, /* bitpos */
519 complain_overflow_dont,/* complain_on_overflow */
520 bfd_elf_generic_reloc, /* special_function */
521 "R_MSP430_PREL31", /* name */
0a1b45a2 522 false, /* partial_inplace */
13761a11
NC		 523 0, /* src_mask */
524 0xffff, /* dst_mask */
0a1b45a2 525 true), /* pcrel_offset */
13761a11
NC		 526
527 EMPTY_HOWTO (R_MSP430_EHTYPE),
1b786873 528
df301bfc 529 /* A 10 bit PC relative relocation. */
13761a11
NC		 530 HOWTO (R_MSP430X_10_PCREL, /* type */
531 1, /* rightshift */
c94cb026 532 2, /* size */
13761a11 533 10, /* bitsize */
0a1b45a2 534 true, /* pc_relative */
13761a11
NC		 535 0, /* bitpos */
536 complain_overflow_bitfield,/* complain_on_overflow */
537 bfd_elf_generic_reloc, /* special_function */
538 "R_MSP430X_10_PCREL", /* name */
0a1b45a2 539 false, /* partial_inplace */
df301bfc
NC		 540 0x3ff, /* src_mask */
541 0x3ff, /* dst_mask */
0a1b45a2 542 true), /* pcrel_offset */
13761a11 543
df301bfc 544 /* A 10 bit PC relative relocation for complicated polymorphs. */
13761a11
NC		 545 HOWTO (R_MSP430X_2X_PCREL, /* type */
546 1, /* rightshift */
c94cb026 547 4, /* size */
13761a11 548 10, /* bitsize */
0a1b45a2 549 true, /* pc_relative */
13761a11
NC		 550 0, /* bitpos */
551 complain_overflow_bitfield,/* complain_on_overflow */
552 bfd_elf_generic_reloc, /* special_function */
553 "R_MSP430X_2X_PCREL", /* name */
0a1b45a2 554 false, /* partial_inplace */
df301bfc
NC		 555 0x3ff, /* src_mask */
556 0x3ff, /* dst_mask */
0a1b45a2 557 true), /* pcrel_offset */
13761a11
NC		 558
559 /* Together with a following reloc, allows for the difference
560 between two symbols to be the real addend of the second reloc. */
561 HOWTO (R_MSP430X_SYM_DIFF, /* type */
562 0, /* rightshift */
c94cb026 563 4, /* size */
13761a11 564 32, /* bitsize */
0a1b45a2 565 false, /* pc_relative */
13761a11
NC		 566 0, /* bitpos */
567 complain_overflow_dont,/* complain_on_overflow */
1ade7175 568 rl78_sym_diff_handler, /* special handler. */
13761a11 569 "R_MSP430X_SYM_DIFF", /* name */
0a1b45a2 570 false, /* partial_inplace */
13761a11
NC		 571 0xffffffff, /* src_mask */
572 0xffffffff, /* dst_mask */
0a1b45a2 573 false), /* pcrel_offset */
7d81bc93
JL		 574
575 /* The length of unsigned-leb128 is variable, just assume the
576 size is one byte here. */
577 HOWTO (R_MSP430X_GNU_SET_ULEB128, /* type */
578 0, /* rightshift */
c94cb026 579 1, /* size */
7d81bc93 580 0, /* bitsize */
0a1b45a2 581 false, /* pc_relative */
7d81bc93
JL		 582 0, /* bitpos */
583 complain_overflow_dont, /* complain_on_overflow */
584 msp430_elf_ignore_reloc, /* special handler. */
585 "R_MSP430X_GNU_SET_ULEB128", /* name */
0a1b45a2 586 false, /* partial_inplace */
7d81bc93
JL		 587 0, /* src_mask */
588 0, /* dst_mask */
0a1b45a2 589 false), /* pcrel_offset */
7d81bc93
JL		 590
591 /* The length of unsigned-leb128 is variable, just assume the
592 size is one byte here. */
593 HOWTO (R_MSP430X_GNU_SUB_ULEB128, /* type */
594 0, /* rightshift */
c94cb026 595 1, /* size */
7d81bc93 596 0, /* bitsize */
0a1b45a2 597 false, /* pc_relative */
7d81bc93
JL		 598 0, /* bitpos */
599 complain_overflow_dont, /* complain_on_overflow */
600 msp430_elf_ignore_reloc, /* special handler. */
601 "R_MSP430X_GNU_SUB_ULEB128", /* name */
0a1b45a2 602 false, /* partial_inplace */
7d81bc93
JL		 603 0, /* src_mask */
604 0, /* dst_mask */
0a1b45a2 605 false), /* pcrel_offset */
7d81bc93 606
2469cfa2
NC		 607};
608
609/* Map BFD reloc types to MSP430 ELF reloc types. */
610
611struct msp430_reloc_map
612{
613 bfd_reloc_code_real_type bfd_reloc_val;
614 unsigned int elf_reloc_val;
615};
616
617static const struct msp430_reloc_map msp430_reloc_map[] =
13761a11 618{
07d6d2b8
AM		 619 {BFD_RELOC_NONE, R_MSP430_NONE},
620 {BFD_RELOC_32, R_MSP430_32},
621 {BFD_RELOC_MSP430_10_PCREL, R_MSP430_10_PCREL},
622 {BFD_RELOC_16, R_MSP430_16_BYTE},
623 {BFD_RELOC_MSP430_16_PCREL, R_MSP430_16_PCREL},
624 {BFD_RELOC_MSP430_16, R_MSP430_16},
13761a11 625 {BFD_RELOC_MSP430_16_PCREL_BYTE, R_MSP430_16_PCREL_BYTE},
07d6d2b8
AM		 626 {BFD_RELOC_MSP430_16_BYTE, R_MSP430_16_BYTE},
627 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430_2X_PCREL},
628 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430_RL_PCREL},
629 {BFD_RELOC_8, R_MSP430_8},
7d81bc93
JL		 630 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430_SYM_DIFF},
631 {BFD_RELOC_MSP430_SET_ULEB128, R_MSP430_GNU_SET_ULEB128 },
632 {BFD_RELOC_MSP430_SUB_ULEB128, R_MSP430_GNU_SUB_ULEB128 }
13761a11
NC		 633};
634
635static const struct msp430_reloc_map msp430x_reloc_map[] =
636{
07d6d2b8
AM		 637 {BFD_RELOC_NONE, R_MSP430_NONE},
638 {BFD_RELOC_32, R_MSP430_ABS32},
639 {BFD_RELOC_16, R_MSP430_ABS16},
640 {BFD_RELOC_8, R_MSP430_ABS8},
641 {BFD_RELOC_MSP430_ABS8, R_MSP430_ABS8},
13761a11
NC		 642 {BFD_RELOC_MSP430X_PCR20_EXT_SRC, R_MSP430X_PCR20_EXT_SRC},
643 {BFD_RELOC_MSP430X_PCR20_EXT_DST, R_MSP430X_PCR20_EXT_DST},
644 {BFD_RELOC_MSP430X_PCR20_EXT_ODST, R_MSP430X_PCR20_EXT_ODST},
645 {BFD_RELOC_MSP430X_ABS20_EXT_SRC, R_MSP430X_ABS20_EXT_SRC},
646 {BFD_RELOC_MSP430X_ABS20_EXT_DST, R_MSP430X_ABS20_EXT_DST},
647 {BFD_RELOC_MSP430X_ABS20_EXT_ODST, R_MSP430X_ABS20_EXT_ODST},
648 {BFD_RELOC_MSP430X_ABS20_ADR_SRC, R_MSP430X_ABS20_ADR_SRC},
649 {BFD_RELOC_MSP430X_ABS20_ADR_DST, R_MSP430X_ABS20_ADR_DST},
07d6d2b8 650 {BFD_RELOC_MSP430X_PCR16, R_MSP430X_PCR16},
13761a11 651 {BFD_RELOC_MSP430X_PCR20_CALL, R_MSP430X_PCR20_CALL},
07d6d2b8
AM		 652 {BFD_RELOC_MSP430X_ABS16, R_MSP430X_ABS16},
653 {BFD_RELOC_MSP430_ABS_HI16, R_MSP430_ABS_HI16},
654 {BFD_RELOC_MSP430_PREL31, R_MSP430_PREL31},
655 {BFD_RELOC_MSP430_10_PCREL, R_MSP430X_10_PCREL},
656 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430X_2X_PCREL},
657 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430X_PCR16},
7d81bc93
JL		 658 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430X_SYM_DIFF},
659 {BFD_RELOC_MSP430_SET_ULEB128, R_MSP430X_GNU_SET_ULEB128 },
660 {BFD_RELOC_MSP430_SUB_ULEB128, R_MSP430X_GNU_SUB_ULEB128 }
13761a11
NC		 661};
662
0a1b45a2 663static inline bool
13761a11
NC		 664uses_msp430x_relocs (bfd * abfd)
665{
6d00b590 666 extern const bfd_target msp430_elf32_ti_vec;
13761a11
NC		 667
668 return bfd_get_mach (abfd) == bfd_mach_msp430x
6d00b590 669 || abfd->xvec == & msp430_elf32_ti_vec;
13761a11 670}
2469cfa2
NC		 671
672static reloc_howto_type *
b18c562e
NC		 673bfd_elf32_bfd_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
674 bfd_reloc_code_real_type code)
2469cfa2
NC		 675{
676 unsigned int i;
677
13761a11
NC		 678 if (uses_msp430x_relocs (abfd))
679 {
680 for (i = ARRAY_SIZE (msp430x_reloc_map); i--;)
681 if (msp430x_reloc_map[i].bfd_reloc_val == code)
682 return elf_msp430x_howto_table + msp430x_reloc_map[i].elf_reloc_val;
683 }
684 else
685 {
686 for (i = 0; i < ARRAY_SIZE (msp430_reloc_map); i++)
687 if (msp430_reloc_map[i].bfd_reloc_val == code)
688 return &elf_msp430_howto_table[msp430_reloc_map[i].elf_reloc_val];
689 }
2469cfa2
NC		 690
691 return NULL;
692}
693
157090f7
AM		 694static reloc_howto_type *
695bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
696 const char *r_name)
697{
698 unsigned int i;
699
13761a11
NC		 700 if (uses_msp430x_relocs (abfd))
701 {
702 for (i = ARRAY_SIZE (elf_msp430x_howto_table); i--;)
703 if (elf_msp430x_howto_table[i].name != NULL
704 && strcasecmp (elf_msp430x_howto_table[i].name, r_name) == 0)
705 return elf_msp430x_howto_table + i;
706 }
707 else
708 {
709 for (i = 0;
710 i < (sizeof (elf_msp430_howto_table)
711 / sizeof (elf_msp430_howto_table[0]));
712 i++)
713 if (elf_msp430_howto_table[i].name != NULL
714 && strcasecmp (elf_msp430_howto_table[i].name, r_name) == 0)
715 return &elf_msp430_howto_table[i];
716 }
157090f7
AM		 717
718 return NULL;
719}
720
2469cfa2
NC		 721/* Set the howto pointer for an MSP430 ELF reloc. */
722
0a1b45a2 723static bool
0aa13fee 724msp430_info_to_howto_rela (bfd * abfd,
b18c562e
NC		 725 arelent * cache_ptr,
726 Elf_Internal_Rela * dst)
2469cfa2
NC		 727{
728 unsigned int r_type;
729
730 r_type = ELF32_R_TYPE (dst->r_info);
13761a11
NC		 731
732 if (uses_msp430x_relocs (abfd))
733 {
5860e3f8
NC		 734 if (r_type >= (unsigned int) R_MSP430x_max)
735 {
695344c0 736 /* xgettext:c-format */
0aa13fee
AM		 737 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
738 abfd, r_type);
f3185997 739 bfd_set_error (bfd_error_bad_value);
0a1b45a2 740 return false;
5860e3f8 741 }
13761a11 742 cache_ptr->howto = elf_msp430x_howto_table + r_type;
13761a11 743 }
f3185997 744 else if (r_type >= (unsigned int) R_MSP430_max)
5860e3f8 745 {
695344c0 746 /* xgettext:c-format */
0aa13fee
AM		 747 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
748 abfd, r_type);
f3185997 749 bfd_set_error (bfd_error_bad_value);
0a1b45a2 750 return false;
5860e3f8 751 }
f3185997
NC		 752 else
753 cache_ptr->howto = &elf_msp430_howto_table[r_type];
754
0a1b45a2 755 return true;
2469cfa2
NC		 756}
757
2469cfa2
NC		 758/* Look through the relocs for a section during the first phase.
759 Since we don't do .gots or .plts, we just need to consider the
760 virtual table relocs for gc. */
761
0a1b45a2 762static bool
b18c562e
NC		 763elf32_msp430_check_relocs (bfd * abfd, struct bfd_link_info * info,
764 asection * sec, const Elf_Internal_Rela * relocs)
2469cfa2
NC		 765{
766 Elf_Internal_Shdr *symtab_hdr;
5582a088 767 struct elf_link_hash_entry **sym_hashes;
2469cfa2
NC		 768 const Elf_Internal_Rela *rel;
769 const Elf_Internal_Rela *rel_end;
770
0e1862bb 771 if (bfd_link_relocatable (info))
0a1b45a2 772 return true;
2469cfa2
NC		 773
774 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
775 sym_hashes = elf_sym_hashes (abfd);
2469cfa2
NC		 776
777 rel_end = relocs + sec->reloc_count;
778 for (rel = relocs; rel < rel_end; rel++)
779 {
780 struct elf_link_hash_entry *h;
781 unsigned long r_symndx;
782
783 r_symndx = ELF32_R_SYM (rel->r_info);
784 if (r_symndx < symtab_hdr->sh_info)
785 h = NULL;
786 else
973a3492
L		 787 {
788 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
789 while (h->root.type == bfd_link_hash_indirect
790 || h->root.type == bfd_link_hash_warning)
791 h = (struct elf_link_hash_entry *) h->root.u.i.link;
792 }
2469cfa2
NC		 793 }
794
0a1b45a2 795 return true;
2469cfa2
NC		 796}
797
798/* Perform a single relocation. By default we use the standard BFD
799 routines, but a few relocs, we have to do them ourselves. */
800
801static bfd_reloc_status_type
07d6d2b8
AM		 802msp430_final_link_relocate (reloc_howto_type * howto,
803 bfd * input_bfd,
804 asection * input_section,
805 bfd_byte * contents,
806 Elf_Internal_Rela * rel,
807 bfd_vma relocation,
13761a11 808 struct bfd_link_info * info)
2469cfa2 809{
13761a11
NC		 810 static asection * sym_diff_section;
811 static bfd_vma sym_diff_value;
812
813 struct bfd_elf_section_data * esd = elf_section_data (input_section);
2469cfa2
NC		 814 bfd_reloc_status_type r = bfd_reloc_ok;
815 bfd_vma x;
816 bfd_signed_vma srel;
0a1b45a2 817 bool is_rel_reloc = false;
13761a11
NC		 818
819 if (uses_msp430x_relocs (input_bfd))
820 {
821 /* See if we have a REL type relocation. */
822 is_rel_reloc = (esd->rel.hdr != NULL);
823 /* Sanity check - only one type of relocation per section.
824 FIXME: Theoretically it is possible to have both types,
825 but if that happens how can we distinguish between the two ? */
826 BFD_ASSERT (! is_rel_reloc || ! esd->rela.hdr);
827 /* If we are using a REL relocation then the addend should be empty. */
828 BFD_ASSERT (! is_rel_reloc || rel->r_addend == 0);
829 }
2469cfa2 830
d60f5448
JL		 831 if (debug_relocs)
832 printf ("writing relocation (%p) at 0x%lx type: %d\n", rel,
c675ec1e
NC		 833 (long) (input_section->output_section->vma + input_section->output_offset
834 + rel->r_offset), howto->type);
13761a11 835 if (sym_diff_section != NULL)
2469cfa2 836 {
13761a11 837 BFD_ASSERT (sym_diff_section == input_section);
1b786873 838
13761a11
NC		 839 if (uses_msp430x_relocs (input_bfd))
840 switch (howto->type)
841 {
7d81bc93
JL		 842 case R_MSP430X_GNU_SET_ULEB128:
843 relocation += (!is_rel_reloc ? rel->r_addend : 0);
844 /* Fall through. */
13761a11
NC		 845 case R_MSP430_ABS32:
846 /* If we are computing a 32-bit value for the location lists
847 and the result is 0 then we add one to the value. A zero
848 value can result because of linker relaxation deleteing
849 prologue instructions and using a value of 1 (for the begin
850 and end offsets in the location list entry) results in a
851 nul entry which does not prevent the following entries from
852 being parsed. */
853 if (relocation == sym_diff_value
854 && strcmp (input_section->name, ".debug_loc") == 0)
855 ++ relocation;
856 /* Fall through. */
857 case R_MSP430_ABS16:
858 case R_MSP430X_ABS16:
859 case R_MSP430_ABS8:
860 BFD_ASSERT (! is_rel_reloc);
861 relocation -= sym_diff_value;
862 break;
863
864 default:
865 return bfd_reloc_dangerous;
866 }
867 else
868 switch (howto->type)
869 {
7d81bc93
JL		 870 case R_MSP430_GNU_SET_ULEB128:
871 relocation += (!is_rel_reloc ? rel->r_addend : 0);
872 /* Fall through. */
13761a11
NC		 873 case R_MSP430_32:
874 case R_MSP430_16:
875 case R_MSP430_16_BYTE:
876 case R_MSP430_8:
877 relocation -= sym_diff_value;
878 break;
879
880 default:
881 return bfd_reloc_dangerous;
882 }
1b786873 883
13761a11
NC		 884 sym_diff_section = NULL;
885 }
886
7d81bc93
JL		 887 if ((uses_msp430x_relocs (input_bfd)
888 && howto->type == R_MSP430X_GNU_SET_ULEB128)
889 || (!uses_msp430x_relocs (input_bfd)
890 && howto->type == R_MSP430_GNU_SET_ULEB128))
891 {
892 unsigned int len, new_len = 0;
893 bfd_byte *endp, *p;
894 unsigned int val = relocation;
895
896 _bfd_read_unsigned_leb128 (input_bfd, contents + rel->r_offset, &len);
897
898 /* Clean the contents value to zero. Do not reduce the length. */
899 p = contents + rel->r_offset;
900 endp = (p + len) - 1;
901 memset (p, 0x80, len - 1);
902 *(endp) = 0;
903
904 /* Get the length of the new uleb128 value. */
905 do
906 {
907 new_len++;
908 val >>= 7;
909 } while (val);
910
911 if (new_len > len)
912 {
913 _bfd_error_handler
914 (_("error: final size of uleb128 value at offset 0x%lx in %pA "
915 "from %pB exceeds available space"),
916 (long) rel->r_offset, input_section, input_bfd);
917 }
918 else
919 {
920 /* If the number of bytes required to store the new value has
921 decreased, "right align" the new value within the available space,
922 so the MSB side is padded with uleb128 zeros (0x80). */
923 p = _bfd_write_unsigned_leb128 (p + (len - new_len), endp,
924 relocation);
925 /* We checked there is enough space for the new value above, so this
926 should never be NULL. */
927 BFD_ASSERT (p);
928 }
929
930 return bfd_reloc_ok;
931 }
932 else if (uses_msp430x_relocs (input_bfd))
13761a11
NC		 933 switch (howto->type)
934 {
935 case R_MSP430X_SYM_DIFF:
7d81bc93 936 case R_MSP430X_GNU_SUB_ULEB128:
13761a11
NC		 937 /* Cache the input section and value.
938 The offset is unreliable, since relaxation may
939 have reduced the following reloc's offset. */
940 BFD_ASSERT (! is_rel_reloc);
941 sym_diff_section = input_section;
7d81bc93
JL		 942 sym_diff_value = relocation + (howto->type == R_MSP430X_GNU_SUB_ULEB128
943 ? rel->r_addend : 0);
13761a11
NC		 944 return bfd_reloc_ok;
945
946 case R_MSP430_ABS16:
947 contents += rel->r_offset;
948 srel = (bfd_signed_vma) relocation;
949 if (is_rel_reloc)
950 srel += bfd_get_16 (input_bfd, contents);
951 else
952 srel += rel->r_addend;
953 bfd_put_16 (input_bfd, srel & 0xffff, contents);
954 break;
955
956 case R_MSP430X_10_PCREL:
957 contents += rel->r_offset;
958 srel = (bfd_signed_vma) relocation;
959 if (is_rel_reloc)
960 srel += bfd_get_16 (input_bfd, contents) & 0x3ff;
961 else
962 srel += rel->r_addend;
963 srel -= rel->r_offset;
964 srel -= 2; /* Branch instructions add 2 to the PC... */
965 srel -= (input_section->output_section->vma +
966 input_section->output_offset);
967 if (srel & 1)
968 return bfd_reloc_outofrange;
969
970 /* MSP430 addresses commands as words. */
971 srel >>= 1;
972
973 /* Check for an overflow. */
974 if (srel < -512 || srel > 511)
975 {
976 if (info->disable_target_specific_optimizations < 0)
977 {
0a1b45a2 978 static bool warned = false;
13761a11
NC		 979 if (! warned)
980 {
981 info->callbacks->warning
982 (info,
38f14ab8 983 _("try enabling relaxation to avoid relocation truncations"),
13761a11 984 NULL, input_bfd, input_section, relocation);
0a1b45a2 985 warned = true;
13761a11
NC		 986 }
987 }
988 return bfd_reloc_overflow;
989 }
990
991 x = bfd_get_16 (input_bfd, contents);
992 x = (x & 0xfc00) | (srel & 0x3ff);
993 bfd_put_16 (input_bfd, x, contents);
994 break;
995
996 case R_MSP430X_PCR20_EXT_ODST:
3f307074 997 /* [0,4]+[48,16] = ---F ---- ---- FFFF */
13761a11
NC		 998 contents += rel->r_offset;
999 srel = (bfd_signed_vma) relocation;
1000 if (is_rel_reloc)
1001 {
1002 bfd_vma addend;
1003 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
3f307074 1004 addend |= bfd_get_16 (input_bfd, contents + 6);
13761a11 1005 srel += addend;
1b786873 1006
13761a11
NC		 1007 }
1008 else
1009 srel += rel->r_addend;
1010 srel -= rel->r_offset;
1011 srel -= (input_section->output_section->vma +
1012 input_section->output_offset);
1013 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6);
1014 x = bfd_get_16 (input_bfd, contents);
1015 x = (x & 0xfff0) | ((srel >> 16) & 0xf);
1016 bfd_put_16 (input_bfd, x, contents);
1017 break;
1018
1019 case R_MSP430X_ABS20_EXT_SRC:
3f307074 1020 /* [7,4]+[32,16] = -78- ---- FFFF */
13761a11
NC		 1021 contents += rel->r_offset;
1022 srel = (bfd_signed_vma) relocation;
1023 if (is_rel_reloc)
1024 {
1025 bfd_vma addend;
1026 addend = (bfd_get_16 (input_bfd, contents) & 0x0780) << 9;
3f307074 1027 addend |= bfd_get_16 (input_bfd, contents + 4);
13761a11
NC		 1028 srel += addend;
1029 }
1030 else
1031 srel += rel->r_addend;
1032 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
1033 srel >>= 16;
1034 x = bfd_get_16 (input_bfd, contents);
1035 x = (x & 0xf87f) | ((srel << 7) & 0x0780);
1036 bfd_put_16 (input_bfd, x, contents);
1037 break;
1038
1039 case R_MSP430_16_PCREL:
1040 contents += rel->r_offset;
1041 srel = (bfd_signed_vma) relocation;
1042 if (is_rel_reloc)
1043 srel += bfd_get_16 (input_bfd, contents);
1044 else
1045 srel += rel->r_addend;
1046 srel -= rel->r_offset;
1047 /* Only branch instructions add 2 to the PC... */
1048 srel -= (input_section->output_section->vma +
1049 input_section->output_offset);
1050 if (srel & 1)
1051 return bfd_reloc_outofrange;
1052 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1053 break;
1054
1055 case R_MSP430X_PCR20_EXT_DST:
3f307074 1056 /* [0,4]+[32,16] = ---F ---- FFFF */
13761a11
NC		 1057 contents += rel->r_offset;
1058 srel = (bfd_signed_vma) relocation;
1059 if (is_rel_reloc)
1060 {
1061 bfd_vma addend;
1062 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
3f307074 1063 addend |= bfd_get_16 (input_bfd, contents + 4);
13761a11
NC		 1064 srel += addend;
1065 }
1066 else
1067 srel += rel->r_addend;
1068 srel -= rel->r_offset;
1069 srel -= (input_section->output_section->vma +
1070 input_section->output_offset);
1071 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
1072 srel >>= 16;
1073 x = bfd_get_16 (input_bfd, contents);
1074 x = (x & 0xfff0) | (srel & 0xf);
1075 bfd_put_16 (input_bfd, x, contents);
1076 break;
1077
1078 case R_MSP430X_PCR20_EXT_SRC:
3f307074 1079 /* [7,4]+[32,16] = -78- ---- FFFF */
13761a11
NC		 1080 contents += rel->r_offset;
1081 srel = (bfd_signed_vma) relocation;
1082 if (is_rel_reloc)
1083 {
1084 bfd_vma addend;
1085 addend = ((bfd_get_16 (input_bfd, contents) & 0x0780) << 9);
3f307074 1086 addend |= bfd_get_16 (input_bfd, contents + 4);
13761a11
NC		 1087 srel += addend;;
1088 }
1089 else
1090 srel += rel->r_addend;
1091 srel -= rel->r_offset;
1092 /* Only branch instructions add 2 to the PC... */
1093 srel -= (input_section->output_section->vma +
1094 input_section->output_offset);
1095 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
1096 srel >>= 16;
1097 x = bfd_get_16 (input_bfd, contents);
1098 x = (x & 0xf87f) | ((srel << 7) & 0x0780);
1099 bfd_put_16 (input_bfd, x, contents);
1100 break;
1101
1102 case R_MSP430_ABS8:
1103 contents += rel->r_offset;
1104 srel = (bfd_signed_vma) relocation;
1105 if (is_rel_reloc)
1106 srel += bfd_get_8 (input_bfd, contents);
1107 else
1108 srel += rel->r_addend;
1109 bfd_put_8 (input_bfd, srel & 0xff, contents);
1110 break;
1111
1112 case R_MSP430X_ABS20_EXT_DST:
3f307074 1113 /* [0,4]+[32,16] = ---F ---- FFFF */
13761a11
NC		 1114 contents += rel->r_offset;
1115 srel = (bfd_signed_vma) relocation;
1116 if (is_rel_reloc)
3f307074
DD		 1117 {
1118 bfd_vma addend;
1119 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
1120 addend |= bfd_get_16 (input_bfd, contents + 4);
1121 srel += addend;
1122 }
13761a11
NC		 1123 else
1124 srel += rel->r_addend;
1125 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
1126 srel >>= 16;
1127 x = bfd_get_16 (input_bfd, contents);
1128 x = (x & 0xfff0) | (srel & 0xf);
1129 bfd_put_16 (input_bfd, x, contents);
1130 break;
1131
1132 case R_MSP430X_ABS20_EXT_ODST:
3f307074 1133 /* [0,4]+[48,16] = ---F ---- ---- FFFF */
13761a11
NC		 1134 contents += rel->r_offset;
1135 srel = (bfd_signed_vma) relocation;
1136 if (is_rel_reloc)
1137 {
1138 bfd_vma addend;
1139 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
3f307074 1140 addend |= bfd_get_16 (input_bfd, contents + 6);
13761a11
NC		 1141 srel += addend;
1142 }
1143 else
1144 srel += rel->r_addend;
1145 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6);
1146 srel >>= 16;
1147 x = bfd_get_16 (input_bfd, contents);
1148 x = (x & 0xfff0) | (srel & 0xf);
1149 bfd_put_16 (input_bfd, x, contents);
1150 break;
1151
1152 case R_MSP430X_ABS20_ADR_SRC:
3f307074 1153 /* [8,4]+[16,16] = -F-- FFFF */
13761a11
NC		 1154 contents += rel->r_offset;
1155 srel = (bfd_signed_vma) relocation;
1156 if (is_rel_reloc)
1157 {
1158 bfd_vma addend;
1159
1160 addend = ((bfd_get_16 (input_bfd, contents) & 0xf00) << 8);
3f307074 1161 addend |= bfd_get_16 (input_bfd, contents + 2);
13761a11
NC		 1162 srel += addend;
1163 }
1164 else
1165 srel += rel->r_addend;
1166 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2);
1167 srel >>= 16;
1168 x = bfd_get_16 (input_bfd, contents);
1169 x = (x & 0xf0ff) | ((srel << 8) & 0x0f00);
1170 bfd_put_16 (input_bfd, x, contents);
1171 break;
1172
1173 case R_MSP430X_ABS20_ADR_DST:
3f307074 1174 /* [0,4]+[16,16] = ---F FFFF */
13761a11
NC		 1175 contents += rel->r_offset;
1176 srel = (bfd_signed_vma) relocation;
1177 if (is_rel_reloc)
1178 {
1179 bfd_vma addend;
1180 addend = ((bfd_get_16 (input_bfd, contents) & 0xf) << 16);
3f307074 1181 addend |= bfd_get_16 (input_bfd, contents + 2);
13761a11
NC		 1182 srel += addend;
1183 }
1184 else
1185 srel += rel->r_addend;
1186 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2);
1187 srel >>= 16;
1188 x = bfd_get_16 (input_bfd, contents);
1189 x = (x & 0xfff0) | (srel & 0xf);
1190 bfd_put_16 (input_bfd, x, contents);
1191 break;
1192
1193 case R_MSP430X_ABS16:
1194 contents += rel->r_offset;
1195 srel = (bfd_signed_vma) relocation;
1196 if (is_rel_reloc)
1197 srel += bfd_get_16 (input_bfd, contents);
1198 else
1199 srel += rel->r_addend;
1200 x = srel;
1201 if (x > 0xffff)
1b786873 1202 return bfd_reloc_overflow;
13761a11
NC		 1203 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1204 break;
1205
1206 case R_MSP430_ABS_HI16:
1207 /* The EABI specifies that this must be a RELA reloc. */
1208 BFD_ASSERT (! is_rel_reloc);
1209 contents += rel->r_offset;
1210 srel = (bfd_signed_vma) relocation;
1211 srel += rel->r_addend;
1212 bfd_put_16 (input_bfd, (srel >> 16) & 0xffff, contents);
1213 break;
1b786873 1214
13761a11 1215 case R_MSP430X_PCR20_CALL:
3f307074 1216 /* [0,4]+[16,16] = ---F FFFF*/
13761a11
NC		 1217 contents += rel->r_offset;
1218 srel = (bfd_signed_vma) relocation;
1219 if (is_rel_reloc)
1220 {
1221 bfd_vma addend;
1222 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
3f307074 1223 addend |= bfd_get_16 (input_bfd, contents + 2);
13761a11
NC		 1224 srel += addend;
1225 }
1226 else
1227 srel += rel->r_addend;
1228 srel -= rel->r_offset;
1229 srel -= (input_section->output_section->vma +
1230 input_section->output_offset);
1231 bfd_put_16 (input_bfd, srel & 0xffff, contents + 2);
1232 srel >>= 16;
1233 x = bfd_get_16 (input_bfd, contents);
1234 x = (x & 0xfff0) | (srel & 0xf);
1235 bfd_put_16 (input_bfd, x, contents);
1236 break;
1b786873 1237
13761a11
NC		 1238 case R_MSP430X_PCR16:
1239 contents += rel->r_offset;
1240 srel = (bfd_signed_vma) relocation;
1241 if (is_rel_reloc)
1242 srel += bfd_get_16 (input_bfd, contents);
1243 else
1244 srel += rel->r_addend;
1245 srel -= rel->r_offset;
1246 srel -= (input_section->output_section->vma +
1247 input_section->output_offset);
1248 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1249 break;
1b786873 1250
13761a11
NC		 1251 case R_MSP430_PREL31:
1252 contents += rel->r_offset;
1253 srel = (bfd_signed_vma) relocation;
1254 if (is_rel_reloc)
1255 srel += (bfd_get_32 (input_bfd, contents) & 0x7fffffff);
1256 else
1257 srel += rel->r_addend;
1258 srel += rel->r_addend;
1259 x = bfd_get_32 (input_bfd, contents);
1260 x = (x & 0x80000000) | ((srel >> 31) & 0x7fffffff);
1261 bfd_put_32 (input_bfd, x, contents);
1262 break;
1b786873 1263
13761a11
NC		 1264 default:
1265 r = _bfd_final_link_relocate (howto, input_bfd, input_section,
1266 contents, rel->r_offset,
1267 relocation, rel->r_addend);
1268 }
1269 else
1270 switch (howto->type)
1271 {
2469cfa2
NC		 1272 case R_MSP430_10_PCREL:
1273 contents += rel->r_offset;
1274 srel = (bfd_signed_vma) relocation;
1275 srel += rel->r_addend;
1276 srel -= rel->r_offset;
1277 srel -= 2; /* Branch instructions add 2 to the PC... */
1278 srel -= (input_section->output_section->vma +
1279 input_section->output_offset);
1280
1281 if (srel & 1)
1282 return bfd_reloc_outofrange;
1283
1284 /* MSP430 addresses commands as words. */
1285 srel >>= 1;
1286
1287 /* Check for an overflow. */
1288 if (srel < -512 || srel > 511)
13761a11
NC		 1289 {
1290 if (info->disable_target_specific_optimizations < 0)
1291 {
0a1b45a2 1292 static bool warned = false;
13761a11
NC		 1293 if (! warned)
1294 {
1295 info->callbacks->warning
1296 (info,
38f14ab8 1297 _("try enabling relaxation to avoid relocation truncations"),
13761a11 1298 NULL, input_bfd, input_section, relocation);
0a1b45a2 1299 warned = true;
13761a11
NC		 1300 }
1301 }
1302 return bfd_reloc_overflow;
1303 }
1b786873 1304
2469cfa2
NC		 1305 x = bfd_get_16 (input_bfd, contents);
1306 x = (x & 0xfc00) | (srel & 0x3ff);
1307 bfd_put_16 (input_bfd, x, contents);
1308 break;
1309
b18c562e
NC		 1310 case R_MSP430_2X_PCREL:
1311 contents += rel->r_offset;
1312 srel = (bfd_signed_vma) relocation;
1313 srel += rel->r_addend;
1314 srel -= rel->r_offset;
1315 srel -= 2; /* Branch instructions add 2 to the PC... */
1316 srel -= (input_section->output_section->vma +
1317 input_section->output_offset);
1318
1319 if (srel & 1)
1320 return bfd_reloc_outofrange;
1321
1322 /* MSP430 addresses commands as words. */
1323 srel >>= 1;
1324
1325 /* Check for an overflow. */
1326 if (srel < -512 || srel > 511)
1327 return bfd_reloc_overflow;
1328
1329 x = bfd_get_16 (input_bfd, contents);
1330 x = (x & 0xfc00) | (srel & 0x3ff);
1331 bfd_put_16 (input_bfd, x, contents);
1332 /* Handle second jump instruction. */
1333 x = bfd_get_16 (input_bfd, contents - 2);
1334 srel += 1;
1335 x = (x & 0xfc00) | (srel & 0x3ff);
1336 bfd_put_16 (input_bfd, x, contents - 2);
1337 break;
1338
b18c562e 1339 case R_MSP430_RL_PCREL:
77bf820f 1340 case R_MSP430_16_PCREL:
2469cfa2
NC		 1341 contents += rel->r_offset;
1342 srel = (bfd_signed_vma) relocation;
1343 srel += rel->r_addend;
1344 srel -= rel->r_offset;
1345 /* Only branch instructions add 2 to the PC... */
1346 srel -= (input_section->output_section->vma +
1347 input_section->output_offset);
1348
1349 if (srel & 1)
1350 return bfd_reloc_outofrange;
1351
1352 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1353 break;
1354
1355 case R_MSP430_16_PCREL_BYTE:
1356 contents += rel->r_offset;
1357 srel = (bfd_signed_vma) relocation;
1358 srel += rel->r_addend;
1359 srel -= rel->r_offset;
1360 /* Only branch instructions add 2 to the PC... */
1361 srel -= (input_section->output_section->vma +
1362 input_section->output_offset);
1363
1364 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1365 break;
1366
1367 case R_MSP430_16_BYTE:
1368 contents += rel->r_offset;
1369 srel = (bfd_signed_vma) relocation;
1370 srel += rel->r_addend;
1371 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1372 break;
1373
1374 case R_MSP430_16:
1375 contents += rel->r_offset;
1376 srel = (bfd_signed_vma) relocation;
1377 srel += rel->r_addend;
1378
1379 if (srel & 1)
1380 return bfd_reloc_notsupported;
1381
1382 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1383 break;
1384
13761a11
NC		 1385 case R_MSP430_8:
1386 contents += rel->r_offset;
1387 srel = (bfd_signed_vma) relocation;
1388 srel += rel->r_addend;
1389
1390 bfd_put_8 (input_bfd, srel & 0xff, contents);
1391 break;
1b786873 1392
13761a11 1393 case R_MSP430_SYM_DIFF:
7d81bc93 1394 case R_MSP430_GNU_SUB_ULEB128:
13761a11
NC		 1395 /* Cache the input section and value.
1396 The offset is unreliable, since relaxation may
1397 have reduced the following reloc's offset. */
1398 sym_diff_section = input_section;
7d81bc93
JL		 1399 sym_diff_value = relocation + (howto->type == R_MSP430_GNU_SUB_ULEB128
1400 ? rel->r_addend : 0);
13761a11
NC		 1401 return bfd_reloc_ok;
1402
1403 default:
1404 r = _bfd_final_link_relocate (howto, input_bfd, input_section,
1405 contents, rel->r_offset,
1406 relocation, rel->r_addend);
1407 }
2469cfa2
NC		 1408
1409 return r;
1410}
1411
1412/* Relocate an MSP430 ELF section. */
1413
0f684201 1414static int
b18c562e
NC		 1415elf32_msp430_relocate_section (bfd * output_bfd ATTRIBUTE_UNUSED,
1416 struct bfd_link_info * info,
1417 bfd * input_bfd,
1418 asection * input_section,
1419 bfd_byte * contents,
1420 Elf_Internal_Rela * relocs,
1421 Elf_Internal_Sym * local_syms,
1422 asection ** local_sections)
2469cfa2
NC		 1423{
1424 Elf_Internal_Shdr *symtab_hdr;
1425 struct elf_link_hash_entry **sym_hashes;
1426 Elf_Internal_Rela *rel;
1427 Elf_Internal_Rela *relend;
1428
1429 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
1430 sym_hashes = elf_sym_hashes (input_bfd);
1431 relend = relocs + input_section->reloc_count;
1432
1433 for (rel = relocs; rel < relend; rel++)
1434 {
1435 reloc_howto_type *howto;
1436 unsigned long r_symndx;
1437 Elf_Internal_Sym *sym;
1438 asection *sec;
1439 struct elf_link_hash_entry *h;
1440 bfd_vma relocation;
1441 bfd_reloc_status_type r;
1442 const char *name = NULL;
1443 int r_type;
1444
2469cfa2
NC		 1445 r_type = ELF32_R_TYPE (rel->r_info);
1446 r_symndx = ELF32_R_SYM (rel->r_info);
13761a11
NC		 1447
1448 if (uses_msp430x_relocs (input_bfd))
1449 howto = elf_msp430x_howto_table + r_type;
1450 else
1451 howto = elf_msp430_howto_table + r_type;
1452
2469cfa2
NC		 1453 h = NULL;
1454 sym = NULL;
1455 sec = NULL;
1456
1457 if (r_symndx < symtab_hdr->sh_info)
1458 {
1459 sym = local_syms + r_symndx;
1460 sec = local_sections[r_symndx];
8517fae7 1461 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
2469cfa2
NC		 1462
1463 name = bfd_elf_string_from_elf_section
1464 (input_bfd, symtab_hdr->sh_link, sym->st_name);
fd361982 1465 name = name == NULL || *name == 0 ? bfd_section_name (sec) : name;
2469cfa2
NC		 1466 }
1467 else
1468 {
0a1b45a2 1469 bool unresolved_reloc, warned, ignored;
2469cfa2 1470
b2a8e766
AM		 1471 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
1472 r_symndx, symtab_hdr, sym_hashes,
1473 h, sec, relocation,
62d887d4 1474 unresolved_reloc, warned, ignored);
13761a11 1475 name = h->root.root.string;
2469cfa2
NC		 1476 }
1477
dbaa2011 1478 if (sec != NULL && discarded_section (sec))
e4067dbb 1479 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 1480 rel, 1, relend, howto, 0, contents);
ab96bf03 1481
0e1862bb 1482 if (bfd_link_relocatable (info))
ab96bf03
AM		 1483 continue;
1484
2469cfa2 1485 r = msp430_final_link_relocate (howto, input_bfd, input_section,
13761a11 1486 contents, rel, relocation, info);
2469cfa2
NC		 1487
1488 if (r != bfd_reloc_ok)
1489 {
1490 const char *msg = (const char *) NULL;
1491
1492 switch (r)
1493 {
1494 case bfd_reloc_overflow:
1a72702b 1495 (*info->callbacks->reloc_overflow)
13761a11 1496 (info, (h ? &h->root : NULL), name, howto->name,
1a72702b 1497 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
2469cfa2
NC		 1498 break;
1499
1500 case bfd_reloc_undefined:
1a72702b 1501 (*info->callbacks->undefined_symbol)
0a1b45a2 1502 (info, name, input_bfd, input_section, rel->r_offset, true);
2469cfa2
NC		 1503 break;
1504
1505 case bfd_reloc_outofrange:
13761a11 1506 msg = _("internal error: branch/jump to an odd address detected");
2469cfa2
NC		 1507 break;
1508
1509 case bfd_reloc_notsupported:
1510 msg = _("internal error: unsupported relocation error");
1511 break;
1512
1513 case bfd_reloc_dangerous:
1514 msg = _("internal error: dangerous relocation");
1515 break;
1516
1517 default:
1518 msg = _("internal error: unknown error");
1519 break;
1520 }
1521
1522 if (msg)
1a72702b
AM		 1523 (*info->callbacks->warning) (info, msg, name, input_bfd,
1524 input_section, rel->r_offset);
2469cfa2
NC		 1525 }
1526
1527 }
1528
0a1b45a2 1529 return true;
2469cfa2
NC		 1530}
1531
1532/* The final processing done just before writing out a MSP430 ELF object
1533 file. This gets the MSP430 architecture right based on the machine
1534 number. */
1535
0a1b45a2 1536static bool
cc364be6 1537bfd_elf_msp430_final_write_processing (bfd *abfd)
2469cfa2
NC		 1538{
1539 unsigned long val;
1540
1541 switch (bfd_get_mach (abfd))
1542 {
1543 default:
13761a11
NC		 1544 case bfd_mach_msp110: val = E_MSP430_MACH_MSP430x11x1; break;
1545 case bfd_mach_msp11: val = E_MSP430_MACH_MSP430x11; break;
1546 case bfd_mach_msp12: val = E_MSP430_MACH_MSP430x12; break;
1547 case bfd_mach_msp13: val = E_MSP430_MACH_MSP430x13; break;
1548 case bfd_mach_msp14: val = E_MSP430_MACH_MSP430x14; break;
1549 case bfd_mach_msp15: val = E_MSP430_MACH_MSP430x15; break;
1550 case bfd_mach_msp16: val = E_MSP430_MACH_MSP430x16; break;
1551 case bfd_mach_msp31: val = E_MSP430_MACH_MSP430x31; break;
1552 case bfd_mach_msp32: val = E_MSP430_MACH_MSP430x32; break;
1553 case bfd_mach_msp33: val = E_MSP430_MACH_MSP430x33; break;
1554 case bfd_mach_msp41: val = E_MSP430_MACH_MSP430x41; break;
1555 case bfd_mach_msp42: val = E_MSP430_MACH_MSP430x42; break;
1556 case bfd_mach_msp43: val = E_MSP430_MACH_MSP430x43; break;
1557 case bfd_mach_msp44: val = E_MSP430_MACH_MSP430x44; break;
1558 case bfd_mach_msp20: val = E_MSP430_MACH_MSP430x20; break;
1559 case bfd_mach_msp22: val = E_MSP430_MACH_MSP430x22; break;
1560 case bfd_mach_msp23: val = E_MSP430_MACH_MSP430x23; break;
1561 case bfd_mach_msp24: val = E_MSP430_MACH_MSP430x24; break;
1562 case bfd_mach_msp26: val = E_MSP430_MACH_MSP430x26; break;
1563 case bfd_mach_msp46: val = E_MSP430_MACH_MSP430x46; break;
1564 case bfd_mach_msp47: val = E_MSP430_MACH_MSP430x47; break;
1565 case bfd_mach_msp54: val = E_MSP430_MACH_MSP430x54; break;
1566 case bfd_mach_msp430x: val = E_MSP430_MACH_MSP430X; break;
2469cfa2
NC		 1567 }
1568
1569 elf_elfheader (abfd)->e_machine = EM_MSP430;
1570 elf_elfheader (abfd)->e_flags &= ~EF_MSP430_MACH;
1571 elf_elfheader (abfd)->e_flags |= val;
cc364be6 1572 return _bfd_elf_final_write_processing (abfd);
2469cfa2
NC		 1573}
1574
1575/* Set the right machine number. */
1576
0a1b45a2 1577static bool
b18c562e 1578elf32_msp430_object_p (bfd * abfd)
2469cfa2
NC		 1579{
1580 int e_set = bfd_mach_msp14;
1581
1582 if (elf_elfheader (abfd)->e_machine == EM_MSP430
1583 || elf_elfheader (abfd)->e_machine == EM_MSP430_OLD)
1584 {
1585 int e_mach = elf_elfheader (abfd)->e_flags & EF_MSP430_MACH;
1586
1587 switch (e_mach)
1588 {
1589 default:
13761a11
NC		 1590 case E_MSP430_MACH_MSP430x11: e_set = bfd_mach_msp11; break;
1591 case E_MSP430_MACH_MSP430x11x1: e_set = bfd_mach_msp110; break;
1592 case E_MSP430_MACH_MSP430x12: e_set = bfd_mach_msp12; break;
1593 case E_MSP430_MACH_MSP430x13: e_set = bfd_mach_msp13; break;
1594 case E_MSP430_MACH_MSP430x14: e_set = bfd_mach_msp14; break;
1595 case E_MSP430_MACH_MSP430x15: e_set = bfd_mach_msp15; break;
1596 case E_MSP430_MACH_MSP430x16: e_set = bfd_mach_msp16; break;
1597 case E_MSP430_MACH_MSP430x31: e_set = bfd_mach_msp31; break;
1598 case E_MSP430_MACH_MSP430x32: e_set = bfd_mach_msp32; break;
1599 case E_MSP430_MACH_MSP430x33: e_set = bfd_mach_msp33; break;
1600 case E_MSP430_MACH_MSP430x41: e_set = bfd_mach_msp41; break;
1601 case E_MSP430_MACH_MSP430x42: e_set = bfd_mach_msp42; break;
1602 case E_MSP430_MACH_MSP430x43: e_set = bfd_mach_msp43; break;
1603 case E_MSP430_MACH_MSP430x44: e_set = bfd_mach_msp44; break;
1604 case E_MSP430_MACH_MSP430x20: e_set = bfd_mach_msp20; break;
1605 case E_MSP430_MACH_MSP430x22: e_set = bfd_mach_msp22; break;
1606 case E_MSP430_MACH_MSP430x23: e_set = bfd_mach_msp23; break;
1607 case E_MSP430_MACH_MSP430x24: e_set = bfd_mach_msp24; break;
1608 case E_MSP430_MACH_MSP430x26: e_set = bfd_mach_msp26; break;
1609 case E_MSP430_MACH_MSP430x46: e_set = bfd_mach_msp46; break;
1610 case E_MSP430_MACH_MSP430x47: e_set = bfd_mach_msp47; break;
1611 case E_MSP430_MACH_MSP430x54: e_set = bfd_mach_msp54; break;
1612 case E_MSP430_MACH_MSP430X: e_set = bfd_mach_msp430x; break;
2469cfa2
NC		 1613 }
1614 }
1b786873 1615
2469cfa2
NC		 1616 return bfd_default_set_arch_mach (abfd, bfd_arch_msp430, e_set);
1617}
1618
b18c562e
NC		 1619/* These functions handle relaxing for the msp430.
1620 Relaxation required only in two cases:
1621 - Bad hand coding like jumps from one section to another or
1622 from file to file.
77bf820f 1623 - Sibling calls. This will affect only 'jump label' polymorph. Without
b18c562e
NC		 1624 relaxing this enlarges code by 2 bytes. Sibcalls implemented but
1625 do not work in gcc's port by the reason I do not know.
13761a11
NC		 1626 - To convert out of range conditional jump instructions (found inside
1627 a function) into inverted jumps over an unconditional branch instruction.
b18c562e
NC		 1628 Anyway, if a relaxation required, user should pass -relax option to the
1629 linker.
1630
1631 There are quite a few relaxing opportunities available on the msp430:
1632
1633 ================================================================
1634
1635 1. 3 words -> 1 word
1636
07d6d2b8
AM		 1637 eq == jeq label jne +4; br lab
1638 ne != jne label jeq +4; br lab
1639 lt < jl label jge +4; br lab
1640 ltu < jlo label lhs +4; br lab
1641 ge >= jge label jl +4; br lab
1642 geu >= jhs label jlo +4; br lab
b18c562e
NC		 1643
1644 2. 4 words -> 1 word
1645
07d6d2b8 1646 ltn < jn jn +2; jmp +4; br lab
b18c562e
NC		 1647
1648 3. 4 words -> 2 words
1649
07d6d2b8
AM		 1650 gt > jeq +2; jge label jeq +6; jl +4; br label
1651 gtu > jeq +2; jhs label jeq +6; jlo +4; br label
b18c562e
NC		 1652
1653 4. 4 words -> 2 words and 2 labels
1654
07d6d2b8
AM		 1655 leu <= jeq label; jlo label jeq +2; jhs +4; br label
1656 le <= jeq label; jl label jeq +2; jge +4; br label
b18c562e
NC		 1657 =================================================================
1658
1659 codemap for first cases is (labels masked ):
1660 eq: 0x2002,0x4010,0x0000 -> 0x2400
1661 ne: 0x2402,0x4010,0x0000 -> 0x2000
1662 lt: 0x3402,0x4010,0x0000 -> 0x3800
1663 ltu: 0x2c02,0x4010,0x0000 -> 0x2800
1664 ge: 0x3802,0x4010,0x0000 -> 0x3400
1665 geu: 0x2802,0x4010,0x0000 -> 0x2c00
1666
1667 second case:
1668 ltn: 0x3001,0x3c02,0x4010,0x0000 -> 0x3000
1669
1670 third case:
1671 gt: 0x2403,0x3802,0x4010,0x0000 -> 0x2401,0x3400
1672 gtu: 0x2403,0x2802,0x4010,0x0000 -> 0x2401,0x2c00
1673
1674 fourth case:
1675 leu: 0x2401,0x2c02,0x4010,0x0000 -> 0x2400,0x2800
1676 le: 0x2401,0x3402,0x4010,0x0000 -> 0x2400,0x3800
1677
1678 Unspecified case :)
1679 jump: 0x4010,0x0000 -> 0x3c00. */
1680
1681#define NUMB_RELAX_CODES 12
1682static struct rcodes_s
1683{
1684 int f0, f1; /* From code. */
1685 int t0, t1; /* To code. */
1686 int labels; /* Position of labels: 1 - one label at first
1687 word, 2 - one at second word, 3 - two
1688 labels at both. */
1689 int cdx; /* Words to match. */
1690 int bs; /* Shrink bytes. */
1691 int off; /* Offset from old label for new code. */
1692 int ncl; /* New code length. */
1693} rcode[] =
07d6d2b8 1694{/* lab,cdx,bs,off,ncl */
b18c562e
NC		 1695 { 0x0000, 0x0000, 0x3c00, 0x0000, 1, 0, 2, 2, 2}, /* jump */
1696 { 0x0000, 0x2002, 0x2400, 0x0000, 1, 1, 4, 4, 2}, /* eq */
1697 { 0x0000, 0x2402, 0x2000, 0x0000, 1, 1, 4, 4, 2}, /* ne */
1698 { 0x0000, 0x3402, 0x3800, 0x0000, 1, 1, 4, 4, 2}, /* lt */
1699 { 0x0000, 0x2c02, 0x2800, 0x0000, 1, 1, 4, 4, 2}, /* ltu */
1700 { 0x0000, 0x3802, 0x3400, 0x0000, 1, 1, 4, 4, 2}, /* ge */
1701 { 0x0000, 0x2802, 0x2c00, 0x0000, 1, 1, 4, 4, 2}, /* geu */
1702 { 0x3001, 0x3c02, 0x3000, 0x0000, 1, 2, 6, 6, 2}, /* ltn */
1703 { 0x2403, 0x3802, 0x2401, 0x3400, 2, 2, 4, 6, 4}, /* gt */
1704 { 0x2403, 0x2802, 0x2401, 0x2c00, 2, 2, 4, 6, 4}, /* gtu */
1705 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* leu , 2 labels */
1706 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* le , 2 labels */
07d6d2b8 1707 { 0, 0, 0, 0, 0, 0, 0, 0, 0}
b18c562e
NC		 1708};
1709
1710/* Return TRUE if a symbol exists at the given address. */
1711
0a1b45a2 1712static bool
b18c562e
NC		 1713msp430_elf_symbol_address_p (bfd * abfd,
1714 asection * sec,
1715 Elf_Internal_Sym * isym,
1716 bfd_vma addr)
1717{
1718 Elf_Internal_Shdr *symtab_hdr;
1719 unsigned int sec_shndx;
1720 Elf_Internal_Sym *isymend;
1721 struct elf_link_hash_entry **sym_hashes;
1722 struct elf_link_hash_entry **end_hashes;
1723 unsigned int symcount;
1724
1725 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1726
1727 /* Examine all the local symbols. */
1728 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1729 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1730 if (isym->st_shndx == sec_shndx && isym->st_value == addr)
0a1b45a2 1731 return true;
b18c562e
NC		 1732
1733 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1734 - symtab_hdr->sh_info);
1735 sym_hashes = elf_sym_hashes (abfd);
1736 end_hashes = sym_hashes + symcount;
1737 for (; sym_hashes < end_hashes; sym_hashes++)
1738 {
1739 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1740
1741 if ((sym_hash->root.type == bfd_link_hash_defined
1742 || sym_hash->root.type == bfd_link_hash_defweak)
1743 && sym_hash->root.u.def.section == sec
1744 && sym_hash->root.u.def.value == addr)
0a1b45a2 1745 return true;
b18c562e
NC		 1746 }
1747
0a1b45a2 1748 return false;
b18c562e
NC		 1749}
1750
13761a11
NC		 1751/* Adjust all local symbols defined as '.section + 0xXXXX' (.section has
1752 sec_shndx) referenced from current and other sections. */
1753
0a1b45a2 1754static bool
13761a11
NC		 1755msp430_elf_relax_adjust_locals (bfd * abfd, asection * sec, bfd_vma addr,
1756 int count, unsigned int sec_shndx,
1757 bfd_vma toaddr)
046aeb74
DD		 1758{
1759 Elf_Internal_Shdr *symtab_hdr;
1760 Elf_Internal_Rela *irel;
1761 Elf_Internal_Rela *irelend;
1762 Elf_Internal_Sym *isym;
1763
1764 irel = elf_section_data (sec)->relocs;
13761a11 1765 if (irel == NULL)
0a1b45a2 1766 return true;
13761a11 1767
046aeb74
DD		 1768 irelend = irel + sec->reloc_count;
1769 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1770 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
bceec4b9 1771
13761a11 1772 for (;irel < irelend; irel++)
046aeb74 1773 {
bceec4b9 1774 unsigned int sidx = ELF32_R_SYM(irel->r_info);
046aeb74 1775 Elf_Internal_Sym *lsym = isym + sidx;
bceec4b9 1776
1ade7175 1777 /* Adjust symbols referenced by .sec+0xXX. */
bceec4b9
DD		 1778 if (irel->r_addend > addr && irel->r_addend < toaddr
1779 && sidx < symtab_hdr->sh_info
046aeb74
DD		 1780 && lsym->st_shndx == sec_shndx)
1781 irel->r_addend -= count;
1782 }
1b786873 1783
0a1b45a2 1784 return true;
046aeb74
DD		 1785}
1786
b18c562e
NC		 1787/* Delete some bytes from a section while relaxing. */
1788
0a1b45a2 1789static bool
b18c562e
NC		 1790msp430_elf_relax_delete_bytes (bfd * abfd, asection * sec, bfd_vma addr,
1791 int count)
1792{
1793 Elf_Internal_Shdr *symtab_hdr;
1794 unsigned int sec_shndx;
1795 bfd_byte *contents;
1796 Elf_Internal_Rela *irel;
1797 Elf_Internal_Rela *irelend;
b18c562e
NC		 1798 bfd_vma toaddr;
1799 Elf_Internal_Sym *isym;
1800 Elf_Internal_Sym *isymend;
1801 struct elf_link_hash_entry **sym_hashes;
1802 struct elf_link_hash_entry **end_hashes;
1803 unsigned int symcount;
046aeb74 1804 asection *p;
b18c562e
NC		 1805
1806 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1807
1808 contents = elf_section_data (sec)->this_hdr.contents;
1809
b18c562e 1810 toaddr = sec->size;
d60f5448
JL		 1811 if (debug_relocs)
1812 printf (" deleting %d bytes between 0x%lx to 0x%lx\n",
c675ec1e 1813 count, (long) addr, (long) toaddr);
b18c562e
NC		 1814
1815 irel = elf_section_data (sec)->relocs;
1816 irelend = irel + sec->reloc_count;
1817
1818 /* Actually delete the bytes. */
1819 memmove (contents + addr, contents + addr + count,
1820 (size_t) (toaddr - addr - count));
1821 sec->size -= count;
1822
1823 /* Adjust all the relocs. */
fa9ee72b
DD		 1824 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1825 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
13761a11 1826 for (; irel < irelend; irel++)
fa9ee72b 1827 {
fa9ee72b
DD		 1828 /* Get the new reloc address. */
1829 if ((irel->r_offset > addr && irel->r_offset < toaddr))
1830 irel->r_offset -= count;
fa9ee72b 1831 }
b18c562e 1832
046aeb74 1833 for (p = abfd->sections; p != NULL; p = p->next)
13761a11 1834 msp430_elf_relax_adjust_locals (abfd,p,addr,count,sec_shndx,toaddr);
1b786873 1835
b18c562e
NC		 1836 /* Adjust the local symbols defined in this section. */
1837 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1838 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1839 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
0f8f0c57
NC		 1840 {
1841 const char * name;
1842
1843 name = bfd_elf_string_from_elf_section
1844 (abfd, symtab_hdr->sh_link, isym->st_name);
fd361982 1845 name = name == NULL || *name == 0 ? bfd_section_name (sec) : name;
0f8f0c57
NC		 1846
1847 if (isym->st_shndx != sec_shndx)
1848 continue;
1b786873 1849
0f8f0c57
NC		 1850 if (isym->st_value > addr
1851 && (isym->st_value < toaddr
1852 /* We also adjust a symbol at the end of the section if its name is
1853 on the list below. These symbols are used for debug info
1854 generation and they refer to the end of the current section, not
1855 the start of the next section. */
1856 || (isym->st_value == toaddr
1857 && name != NULL
08dedd66
ML		 1858 && (startswith (name, ".Letext")
1859 || startswith (name, ".LFE")))))
0f8f0c57 1860 {
d60f5448
JL		 1861 if (debug_relocs)
1862 printf (" adjusting value of local symbol %s from 0x%lx ",
c675ec1e 1863 name, (long) isym->st_value);
0f8f0c57
NC		 1864 if (isym->st_value < addr + count)
1865 isym->st_value = addr;
1866 else
1867 isym->st_value -= count;
d60f5448 1868 if (debug_relocs)
c675ec1e 1869 printf ("to 0x%lx\n", (long) isym->st_value);
0f8f0c57
NC		 1870 }
1871 /* Adjust the function symbol's size as well. */
1872 else if (ELF_ST_TYPE (isym->st_info) == STT_FUNC
1873 && isym->st_value + isym->st_size > addr
1874 && isym->st_value + isym->st_size < toaddr)
1875 isym->st_size -= count;
1876 }
b18c562e
NC		 1877
1878 /* Now adjust the global symbols defined in this section. */
1879 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1880 - symtab_hdr->sh_info);
1881 sym_hashes = elf_sym_hashes (abfd);
1882 end_hashes = sym_hashes + symcount;
1883 for (; sym_hashes < end_hashes; sym_hashes++)
1884 {
1885 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1886
1887 if ((sym_hash->root.type == bfd_link_hash_defined
1888 || sym_hash->root.type == bfd_link_hash_defweak)
1889 && sym_hash->root.u.def.section == sec
1890 && sym_hash->root.u.def.value > addr
1891 && sym_hash->root.u.def.value < toaddr)
0f8f0c57
NC		 1892 {
1893 if (sym_hash->root.u.def.value < addr + count)
1894 sym_hash->root.u.def.value = addr;
1895 else
1896 sym_hash->root.u.def.value -= count;
1897 }
1898 /* Adjust the function symbol's size as well. */
1899 else if (sym_hash->root.type == bfd_link_hash_defined
1900 && sym_hash->root.u.def.section == sec
1901 && sym_hash->type == STT_FUNC
1902 && sym_hash->root.u.def.value + sym_hash->size > addr
1903 && sym_hash->root.u.def.value + sym_hash->size < toaddr)
1904 sym_hash->size -= count;
b18c562e
NC		 1905 }
1906
0a1b45a2 1907 return true;
b18c562e
NC		 1908}
1909
8d6cb116 1910/* Insert one or two words into a section whilst relaxing. */
13761a11
NC		 1911
1912static bfd_byte *
8d6cb116
JL		 1913msp430_elf_relax_add_words (bfd * abfd, asection * sec, bfd_vma addr,
1914 int num_words, int word1, int word2)
13761a11
NC		 1915{
1916 Elf_Internal_Shdr *symtab_hdr;
1917 unsigned int sec_shndx;
1918 bfd_byte *contents;
1919 Elf_Internal_Rela *irel;
1920 Elf_Internal_Rela *irelend;
1921 Elf_Internal_Sym *isym;
1922 Elf_Internal_Sym *isymend;
1923 struct elf_link_hash_entry **sym_hashes;
1924 struct elf_link_hash_entry **end_hashes;
1925 unsigned int symcount;
1926 bfd_vma sec_end;
1927 asection *p;
d60f5448 1928 if (debug_relocs)
8d6cb116 1929 printf (" adding %d words at 0x%lx\n", num_words,
c675ec1e 1930 (long) (sec->output_section->vma + sec->output_offset + addr));
13761a11
NC		 1931
1932 contents = elf_section_data (sec)->this_hdr.contents;
1933 sec_end = sec->size;
8d6cb116 1934 int num_bytes = num_words * 2;
13761a11
NC		 1935
1936 /* Make space for the new words. */
8d6cb116
JL		 1937 contents = bfd_realloc (contents, sec_end + num_bytes);
1938 memmove (contents + addr + num_bytes, contents + addr, sec_end - addr);
13761a11
NC		 1939
1940 /* Insert the new words. */
1941 bfd_put_16 (abfd, word1, contents + addr);
8d6cb116
JL		 1942 if (num_words == 2)
1943 bfd_put_16 (abfd, word2, contents + addr + 2);
13761a11
NC		 1944
1945 /* Update the section information. */
8d6cb116 1946 sec->size += num_bytes;
1b786873 1947 elf_section_data (sec)->this_hdr.contents = contents;
13761a11
NC		 1948
1949 /* Adjust all the relocs. */
1950 irel = elf_section_data (sec)->relocs;
1951 irelend = irel + sec->reloc_count;
1952
1953 for (; irel < irelend; irel++)
1954 if ((irel->r_offset >= addr && irel->r_offset < sec_end))
8d6cb116 1955 irel->r_offset += num_bytes;
13761a11
NC		 1956
1957 /* Adjust the local symbols defined in this section. */
1958 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1959 for (p = abfd->sections; p != NULL; p = p->next)
8d6cb116 1960 msp430_elf_relax_adjust_locals (abfd, p, addr, -num_bytes,
13761a11
NC		 1961 sec_shndx, sec_end);
1962
1963 /* Adjust the global symbols affected by the move. */
1964 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1965 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1966 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1967 if (isym->st_shndx == sec_shndx
1968 && isym->st_value >= addr && isym->st_value < sec_end)
d60f5448
JL		 1969 {
1970 if (debug_relocs)
1971 printf (" adjusting value of local symbol %s from 0x%lx to "
1972 "0x%lx\n", bfd_elf_string_from_elf_section
1973 (abfd, symtab_hdr->sh_link, isym->st_name),
c675ec1e 1974 (long) isym->st_value, (long)(isym->st_value + num_bytes));
8d6cb116 1975 isym->st_value += num_bytes;
d60f5448 1976 }
13761a11
NC		 1977
1978 /* Now adjust the global symbols defined in this section. */
1979 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1980 - symtab_hdr->sh_info);
1981 sym_hashes = elf_sym_hashes (abfd);
1982 end_hashes = sym_hashes + symcount;
1983 for (; sym_hashes < end_hashes; sym_hashes++)
1984 {
1985 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1986
1987 if ((sym_hash->root.type == bfd_link_hash_defined
1988 || sym_hash->root.type == bfd_link_hash_defweak)
1989 && sym_hash->root.u.def.section == sec
1990 && sym_hash->root.u.def.value >= addr
1991 && sym_hash->root.u.def.value < sec_end)
8d6cb116 1992 sym_hash->root.u.def.value += num_bytes;
13761a11
NC		 1993 }
1994
1995 return contents;
1996}
1b786873 1997
0a1b45a2 1998static bool
b18c562e
NC		 1999msp430_elf_relax_section (bfd * abfd, asection * sec,
2000 struct bfd_link_info * link_info,
0a1b45a2 2001 bool * again)
b18c562e
NC		 2002{
2003 Elf_Internal_Shdr * symtab_hdr;
2004 Elf_Internal_Rela * internal_relocs;
2005 Elf_Internal_Rela * irel;
2006 Elf_Internal_Rela * irelend;
07d6d2b8 2007 bfd_byte * contents = NULL;
b18c562e
NC		 2008 Elf_Internal_Sym * isymbuf = NULL;
2009
2010 /* Assume nothing changes. */
0a1b45a2 2011 *again = false;
b18c562e
NC		 2012
2013 /* We don't have to do anything for a relocatable link, if
2014 this section does not have relocs, or if this is not a
2015 code section. */
0e1862bb 2016 if (bfd_link_relocatable (link_info)
3a574cce
AM		 2017 || sec->reloc_count == 0
2018 || (sec->flags & SEC_RELOC) == 0
2019 || (sec->flags & SEC_HAS_CONTENTS) == 0
2020 || (sec->flags & SEC_CODE) == 0)
0a1b45a2 2021 return true;
b18c562e 2022
d60f5448
JL		 2023 if (debug_relocs)
2024 printf ("Relaxing %s (%p), output_offset: 0x%lx sec size: 0x%lx\n",
c675ec1e 2025 sec->name, sec, (long) sec->output_offset, (long) sec->size);
d60f5448 2026
b18c562e
NC		 2027 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
2028
2029 /* Get a copy of the native relocations. */
2030 internal_relocs =
2031 _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory);
2032 if (internal_relocs == NULL)
2033 goto error_return;
2034
2035 /* Walk through them looking for relaxing opportunities. */
2036 irelend = internal_relocs + sec->reloc_count;
13761a11 2037
d60f5448
JL		 2038 if (debug_relocs)
2039 printf (" trying code size growing relocs\n");
13761a11 2040 /* Do code size growing relocs first. */
b18c562e
NC		 2041 for (irel = internal_relocs; irel < irelend; irel++)
2042 {
2043 bfd_vma symval;
2044
2045 /* If this isn't something that can be relaxed, then ignore
07d6d2b8 2046 this reloc. */
13761a11 2047 if (uses_msp430x_relocs (abfd)
07d6d2b8 2048 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430X_10_PCREL)
13761a11
NC		 2049 ;
2050 else if (! uses_msp430x_relocs (abfd)
07d6d2b8 2051 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_10_PCREL)
13761a11
NC		 2052 ;
2053 else
b18c562e
NC		 2054 continue;
2055
2056 /* Get the section contents if we haven't done so already. */
2057 if (contents == NULL)
2058 {
2059 /* Get cached copy if it exists. */
2060 if (elf_section_data (sec)->this_hdr.contents != NULL)
2061 contents = elf_section_data (sec)->this_hdr.contents;
2062 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
2063 goto error_return;
2064 }
2065
2066 /* Read this BFD's local symbols if we haven't done so already. */
2067 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
2068 {
2069 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
2070 if (isymbuf == NULL)
2071 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
2072 symtab_hdr->sh_info, 0,
2073 NULL, NULL, NULL);
2074 if (isymbuf == NULL)
2075 goto error_return;
2076 }
2077
2078 /* Get the value of the symbol referred to by the reloc. */
2079 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
2080 {
2081 /* A local symbol. */
2082 Elf_Internal_Sym *isym;
2083 asection *sym_sec;
2084
2085 isym = isymbuf + ELF32_R_SYM (irel->r_info);
2086 if (isym->st_shndx == SHN_UNDEF)
2087 sym_sec = bfd_und_section_ptr;
2088 else if (isym->st_shndx == SHN_ABS)
2089 sym_sec = bfd_abs_section_ptr;
2090 else if (isym->st_shndx == SHN_COMMON)
2091 sym_sec = bfd_com_section_ptr;
2092 else
2093 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
2094 symval = (isym->st_value
2095 + sym_sec->output_section->vma + sym_sec->output_offset);
d60f5448
JL		 2096
2097 if (debug_relocs)
2098 printf (" processing reloc at 0x%lx for local sym: %s "
c675ec1e
NC		 2099 "st_value: 0x%lx adj value: 0x%lx\n",
2100 (long) (sec->output_offset + sec->output_section->vma
2101 + irel->r_offset),
d60f5448
JL		 2102 bfd_elf_string_from_elf_section (abfd, symtab_hdr->sh_link,
2103 isym->st_name),
c675ec1e 2104 (long) isym->st_value, (long) symval);
b18c562e
NC		 2105 }
2106 else
2107 {
2108 unsigned long indx;
2109 struct elf_link_hash_entry *h;
2110
2111 /* An external symbol. */
2112 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
2113 h = elf_sym_hashes (abfd)[indx];
2114 BFD_ASSERT (h != NULL);
2115
2116 if (h->root.type != bfd_link_hash_defined
2117 && h->root.type != bfd_link_hash_defweak)
2118 /* This appears to be a reference to an undefined
2119 symbol. Just ignore it--it will be caught by the
2120 regular reloc processing. */
2121 continue;
2122
2123 symval = (h->root.u.def.value
2124 + h->root.u.def.section->output_section->vma
2125 + h->root.u.def.section->output_offset);
d60f5448
JL		 2126 if (debug_relocs)
2127 printf (" processing reloc at 0x%lx for global sym: %s "
c675ec1e
NC		 2128 "st_value: 0x%lx adj value: 0x%lx\n",
2129 (long) (sec->output_offset + sec->output_section->vma
2130 + irel->r_offset),
2131 h->root.root.string, (long) h->root.u.def.value,
2132 (long) symval);
b18c562e
NC		 2133 }
2134
2135 /* For simplicity of coding, we are going to modify the section
07d6d2b8
AM		 2136 contents, the section relocs, and the BFD symbol table. We
2137 must tell the rest of the code not to free up this
2138 information. It would be possible to instead create a table
2139 of changes which have to be made, as is done in coff-mips.c;
2140 that would be more work, but would require less memory when
2141 the linker is run. */
b18c562e 2142
13761a11
NC		 2143 bfd_signed_vma value = symval;
2144 int opcode;
b18c562e 2145
13761a11
NC		 2146 /* Compute the value that will be relocated. */
2147 value += irel->r_addend;
2148 /* Convert to PC relative. */
2149 value -= (sec->output_section->vma + sec->output_offset);
2150 value -= irel->r_offset;
2151 value -= 2;
d60f5448 2152
13761a11
NC		 2153 /* Scale. */
2154 value >>= 1;
b18c562e 2155
13761a11
NC		 2156 /* If it is in range then no modifications are needed. */
2157 if (value >= -512 && value <= 511)
2158 continue;
b18c562e 2159
13761a11
NC		 2160 /* Get the opcode. */
2161 opcode = bfd_get_16 (abfd, contents + irel->r_offset);
1b786873 2162
13761a11 2163 /* Compute the new opcode. We are going to convert:
8d6cb116
JL		 2164 JMP label
2165 into:
2166 BR[A] label
2167 or
13761a11 2168 J<cond> label
8d6cb116 2169 into:
13761a11
NC		 2170 J<inv-cond> 1f
2171 BR[A] #label
07d6d2b8 2172 1: */
13761a11
NC		 2173 switch (opcode & 0xfc00)
2174 {
1b786873 2175 case 0x3800: opcode = 0x3402; break; /* Jl -> Jge +2 */
13761a11
NC		 2176 case 0x3400: opcode = 0x3802; break; /* Jge -> Jl +2 */
2177 case 0x2c00: opcode = 0x2802; break; /* Jhs -> Jlo +2 */
2178 case 0x2800: opcode = 0x2c02; break; /* Jlo -> Jhs +2 */
2179 case 0x2400: opcode = 0x2002; break; /* Jeq -> Jne +2 */
2180 case 0x2000: opcode = 0x2402; break; /* jne -> Jeq +2 */
2181 case 0x3000: /* jn */
2182 /* There is no direct inverse of the Jn insn.
2183 FIXME: we could do this as:
07d6d2b8
AM		 2184 Jn 1f
2185 br 2f
13761a11 2186 1: br label
07d6d2b8 2187 2: */
13761a11 2188 continue;
8d6cb116
JL		 2189 case 0x3c00:
2190 if (uses_msp430x_relocs (abfd))
2191 opcode = 0x0080; /* JMP -> BRA */
2192 else
2193 opcode = 0x4030; /* JMP -> BR */
2194 break;
13761a11 2195 default:
8d6cb116 2196 /* Unhandled branch instruction. */
13761a11 2197 /* fprintf (stderr, "unrecog: %x\n", opcode); */
2d071cfc 2198 continue;
13761a11 2199 }
b18c562e 2200
13761a11
NC		 2201 /* Note that we've changed the relocs, section contents, etc. */
2202 elf_section_data (sec)->relocs = internal_relocs;
2203 elf_section_data (sec)->this_hdr.contents = contents;
2204 symtab_hdr->contents = (unsigned char *) isymbuf;
b18c562e 2205
13761a11
NC		 2206 /* Install the new opcode. */
2207 bfd_put_16 (abfd, opcode, contents + irel->r_offset);
b18c562e 2208
13761a11
NC		 2209 /* Insert the new branch instruction. */
2210 if (uses_msp430x_relocs (abfd))
2211 {
d60f5448
JL		 2212 if (debug_relocs)
2213 printf (" R_MSP430X_10_PCREL -> R_MSP430X_ABS20_ADR_SRC "
2214 "(growing with new opcode 0x%x)\n", opcode);
2215
8d6cb116
JL		 2216 /* Insert an absolute branch (aka MOVA) instruction.
2217 Note that bits 19:16 of the address are stored in the first word
2218 of the insn, so this is where r_offset will point to. */
2219 if (opcode == 0x0080)
2220 {
2221 /* If we're inserting a BRA because we are converting from a JMP,
2222 then only add one word for destination address; the BRA opcode
2223 has already been written. */
2224 contents = msp430_elf_relax_add_words
2225 (abfd, sec, irel->r_offset + 2, 1, 0x0000, 0);
2226 }
2227 else
2228 {
2229 contents = msp430_elf_relax_add_words
2230 (abfd, sec, irel->r_offset + 2, 2, 0x0080, 0x0000);
2231 /* Update the relocation to point to the inserted branch
2232 instruction. Note - we are changing a PC-relative reloc
2233 into an absolute reloc, but this is OK because we have
2234 arranged with the assembler to have the reloc's value be
2235 a (local) symbol, not a section+offset value. */
2236 irel->r_offset += 2;
2237 }
13761a11 2238
13761a11
NC		 2239 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2240 R_MSP430X_ABS20_ADR_SRC);
2241 }
2242 else
2243 {
d60f5448
JL		 2244 if (debug_relocs)
2245 printf (" R_MSP430_10_PCREL -> R_MSP430_16 "
2246 "(growing with new opcode 0x%x)\n", opcode);
8d6cb116
JL		 2247 if (opcode == 0x4030)
2248 {
2249 /* If we're inserting a BR because we are converting from a JMP,
2250 then only add one word for destination address; the BR opcode
2251 has already been written. */
2252 contents = msp430_elf_relax_add_words
2253 (abfd, sec, irel->r_offset + 2, 1, 0x0000, 0);
2254 irel->r_offset += 2;
2255 }
2256 else
2257 {
2258 contents = msp430_elf_relax_add_words
2259 (abfd, sec, irel->r_offset + 2, 2, 0x4030, 0x0000);
2260 /* See comment above about converting a 10-bit PC-rel
2261 relocation into a 16-bit absolute relocation. */
2262 irel->r_offset += 4;
2263 }
13761a11
NC		 2264 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2265 R_MSP430_16);
2266 }
b18c562e 2267
13761a11
NC		 2268 /* Growing the section may mean that other
2269 conditional branches need to be fixed. */
0a1b45a2 2270 *again = true;
13761a11 2271 }
b18c562e 2272
d60f5448
JL		 2273 if (debug_relocs)
2274 printf (" trying code size shrinking relocs\n");
2275
13761a11
NC		 2276 for (irel = internal_relocs; irel < irelend; irel++)
2277 {
2278 bfd_vma symval;
2279
2280 /* Get the section contents if we haven't done so already. */
2281 if (contents == NULL)
2282 {
2283 /* Get cached copy if it exists. */
2284 if (elf_section_data (sec)->this_hdr.contents != NULL)
2285 contents = elf_section_data (sec)->this_hdr.contents;
2286 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
2287 goto error_return;
2288 }
2289
2290 /* Read this BFD's local symbols if we haven't done so already. */
2291 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
2292 {
2293 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
2294 if (isymbuf == NULL)
2295 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
2296 symtab_hdr->sh_info, 0,
2297 NULL, NULL, NULL);
2298 if (isymbuf == NULL)
2299 goto error_return;
2300 }
2301
2302 /* Get the value of the symbol referred to by the reloc. */
2303 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
2304 {
2305 /* A local symbol. */
2306 Elf_Internal_Sym *isym;
2307 asection *sym_sec;
2308
2309 isym = isymbuf + ELF32_R_SYM (irel->r_info);
2310 if (isym->st_shndx == SHN_UNDEF)
2311 sym_sec = bfd_und_section_ptr;
2312 else if (isym->st_shndx == SHN_ABS)
2313 sym_sec = bfd_abs_section_ptr;
2314 else if (isym->st_shndx == SHN_COMMON)
2315 sym_sec = bfd_com_section_ptr;
2316 else
2317 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
2318 symval = (isym->st_value
2319 + sym_sec->output_section->vma + sym_sec->output_offset);
d60f5448
JL		 2320
2321 if (debug_relocs)
2322 printf (" processing reloc at 0x%lx for local sym: %s "
c675ec1e
NC		 2323 "st_value: 0x%lx adj value: 0x%lx\n",
2324 (long) (sec->output_offset + sec->output_section->vma
2325 + irel->r_offset),
d60f5448
JL		 2326 bfd_elf_string_from_elf_section
2327 (abfd, symtab_hdr->sh_link, isym->st_name),
c675ec1e 2328 (long) isym->st_value, (long) symval);
13761a11
NC		 2329 }
2330 else
2331 {
2332 unsigned long indx;
2333 struct elf_link_hash_entry *h;
2334
2335 /* An external symbol. */
2336 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
2337 h = elf_sym_hashes (abfd)[indx];
2338 BFD_ASSERT (h != NULL);
2339
2340 if (h->root.type != bfd_link_hash_defined
2341 && h->root.type != bfd_link_hash_defweak)
2342 /* This appears to be a reference to an undefined
2343 symbol. Just ignore it--it will be caught by the
2344 regular reloc processing. */
2345 continue;
2346
2347 symval = (h->root.u.def.value
2348 + h->root.u.def.section->output_section->vma
2349 + h->root.u.def.section->output_offset);
d60f5448
JL		 2350 if (debug_relocs)
2351 printf (" processing reloc at 0x%lx for global sym: %s "
c675ec1e
NC		 2352 "st_value: 0x%lx adj value: 0x%lx\n", (long)
2353 (sec->output_offset + sec->output_section->vma
2354 + irel->r_offset),
2355 h->root.root.string, (long) h->root.u.def.value,
2356 (long) symval);
13761a11
NC		 2357 }
2358
2359 /* For simplicity of coding, we are going to modify the section
2360 contents, the section relocs, and the BFD symbol table. We
2361 must tell the rest of the code not to free up this
2362 information. It would be possible to instead create a table
2363 of changes which have to be made, as is done in coff-mips.c;
2364 that would be more work, but would require less memory when
2365 the linker is run. */
2366
2367 /* Try to turn a 16bit pc-relative branch into a 10bit pc-relative
2368 branch. */
1b786873 2369 /* Paranoia? paranoia... */
23d4663e
NC		 2370 if (! uses_msp430x_relocs (abfd)
2371 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_RL_PCREL)
13761a11
NC		 2372 {
2373 bfd_vma value = symval;
2374
2375 /* Deal with pc-relative gunk. */
2376 value -= (sec->output_section->vma + sec->output_offset);
2377 value -= irel->r_offset;
2378 value += irel->r_addend;
2379
2380 /* See if the value will fit in 10 bits, note the high value is
2381 1016 as the target will be two bytes closer if we are
2382 able to relax. */
2383 if ((long) value < 1016 && (long) value > -1016)
2384 {
2385 int code0 = 0, code1 = 0, code2 = 0;
2386 int i;
2387 struct rcodes_s *rx;
2388
2389 /* Get the opcode. */
2390 if (irel->r_offset >= 6)
2391 code0 = bfd_get_16 (abfd, contents + irel->r_offset - 6);
2392
2393 if (irel->r_offset >= 4)
2394 code1 = bfd_get_16 (abfd, contents + irel->r_offset - 4);
2395
2396 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2);
2397
2398 if (code2 != 0x4010)
2399 continue;
2400
2401 /* Check r4 and r3. */
2402 for (i = NUMB_RELAX_CODES - 1; i >= 0; i--)
2403 {
2404 rx = &rcode[i];
2405 if (rx->cdx == 2 && rx->f0 == code0 && rx->f1 == code1)
2406 break;
2407 else if (rx->cdx == 1 && rx->f1 == code1)
2408 break;
2409 else if (rx->cdx == 0) /* This is an unconditional jump. */
2410 break;
2411 }
2412
2413 /* Check labels:
b18c562e 2414 .Label0: ; we do not care about this label
13761a11 2415 jeq +6
b18c562e 2416 .Label1: ; make sure there is no label here
13761a11 2417 jl +4
b18c562e 2418 .Label2: ; make sure there is no label here
13761a11
NC		 2419 br .Label_dst
2420
2421 So, if there is .Label1 or .Label2 we cannot relax this code.
2422 This actually should not happen, cause for relaxable
2423 instructions we use RL_PCREL reloc instead of 16_PCREL.
2424 Will change this in the future. */
2425
2426 if (rx->cdx > 0
2427 && msp430_elf_symbol_address_p (abfd, sec, isymbuf,
2428 irel->r_offset - 2))
2429 continue;
2430 if (rx->cdx > 1
2431 && msp430_elf_symbol_address_p (abfd, sec, isymbuf,
2432 irel->r_offset - 4))
2433 continue;
2434
2435 /* Note that we've changed the relocs, section contents, etc. */
2436 elf_section_data (sec)->relocs = internal_relocs;
2437 elf_section_data (sec)->this_hdr.contents = contents;
2438 symtab_hdr->contents = (unsigned char *) isymbuf;
2439
d60f5448
JL		 2440 if (debug_relocs)
2441 printf (" R_MSP430_RL_PCREL -> ");
13761a11
NC		 2442 /* Fix the relocation's type. */
2443 if (uses_msp430x_relocs (abfd))
2444 {
2445 if (rx->labels == 3) /* Handle special cases. */
2446 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2447 R_MSP430X_2X_PCREL);
2448 else
2449 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2450 R_MSP430X_10_PCREL);
2451 }
2452 else
2453 {
2454 if (rx->labels == 3) /* Handle special cases. */
d60f5448
JL		 2455 {
2456 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2457 R_MSP430_2X_PCREL);
2458 if (debug_relocs)
2459 printf ("R_MSP430_2X_PCREL (shrinking with new opcode"
2460 " 0x%x)\n", rx->t0);
2461 }
13761a11 2462 else
d60f5448
JL		 2463 {
2464 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2465 R_MSP430_10_PCREL);
2466 if (debug_relocs)
2467 printf ("R_MSP430_10_PCREL (shrinking with new opcode"
2468 " 0x%x)\n", rx->t0);
2469 }
13761a11
NC		 2470 }
2471
2472 /* Fix the opcode right way. */
2473 bfd_put_16 (abfd, rx->t0, contents + irel->r_offset - rx->off);
2474 if (rx->t1)
2475 bfd_put_16 (abfd, rx->t1,
2476 contents + irel->r_offset - rx->off + 2);
2477
2478 /* Delete bytes. */
2479 if (!msp430_elf_relax_delete_bytes (abfd, sec,
2480 irel->r_offset - rx->off +
2481 rx->ncl, rx->bs))
2482 goto error_return;
2483
2484 /* Handle unconditional jumps. */
2485 if (rx->cdx == 0)
2486 irel->r_offset -= 2;
2487
2488 /* That will change things, so, we should relax again.
2489 Note that this is not required, and it may be slow. */
0a1b45a2 2490 *again = true;
13761a11
NC		 2491 }
2492 }
23d4663e
NC		 2493
2494 /* Try to turn a 16-bit absolute branch into a 10-bit pc-relative
2495 branch. */
133193b8
NC		 2496 if ((uses_msp430x_relocs (abfd)
2497 && ELF32_R_TYPE (irel->r_info) == R_MSP430X_ABS16)
2498 || (! uses_msp430x_relocs (abfd)
2499 && ELF32_R_TYPE (irel->r_info) == R_MSP430_16))
23d4663e
NC		 2500 {
2501 bfd_vma value = symval;
2502
2d071cfc 2503 value -= (sec->output_section->vma + sec->output_offset);
23d4663e
NC		 2504 value -= irel->r_offset;
2505 value += irel->r_addend;
1b786873 2506
23d4663e
NC		 2507 /* See if the value will fit in 10 bits, note the high value is
2508 1016 as the target will be two bytes closer if we are
2509 able to relax. */
2510 if ((long) value < 1016 && (long) value > -1016)
2511 {
ac4280da 2512 int code1, code2, opcode;
23d4663e
NC		 2513
2514 /* Get the opcode. */
2515 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2);
ac4280da 2516 if (code2 != 0x4030) /* BR -> JMP */
23d4663e
NC		 2517 continue;
2518 /* FIXME: check r4 and r3 ? */
2519 /* FIXME: Handle 0x4010 as well ? */
2520
2521 /* Note that we've changed the relocs, section contents, etc. */
2522 elf_section_data (sec)->relocs = internal_relocs;
2523 elf_section_data (sec)->this_hdr.contents = contents;
2524 symtab_hdr->contents = (unsigned char *) isymbuf;
2525
2526 /* Fix the relocation's type. */
2527 if (uses_msp430x_relocs (abfd))
2528 {
2529 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2530 R_MSP430X_10_PCREL);
d60f5448
JL		 2531 if (debug_relocs)
2532 printf (" R_MSP430X_16 -> R_MSP430X_10_PCREL ");
23d4663e
NC		 2533 }
2534 else
2535 {
2536 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2537 R_MSP430_10_PCREL);
d60f5448
JL		 2538 if (debug_relocs)
2539 printf (" R_MSP430_16 -> R_MSP430_10_PCREL ");
23d4663e 2540 }
ac4280da
JL		 2541 /* If we're trying to shrink a BR[A] after previously having
2542 grown a JMP for this reloc, then we have a sequence like
2543 this:
2544 J<cond> 1f
2545 BR[A]
2546 1:
2547 The opcode for J<cond> has the target hard-coded as 2 words
2548 ahead of the insn, instead of using a reloc.
2549 This means we cannot rely on any of the helper functions to
2550 update this hard-coded jump destination if we remove the
2551 BR[A] insn, so we must explicitly update it here.
2552 This does mean that we can remove the entire branch
2553 instruction, and invert the conditional jump, saving us 4
2554 bytes rather than only 2 if we detected this in the normal
2555 way. */
2556 code1 = bfd_get_16 (abfd, contents + irel->r_offset - 4);
2557 switch (code1)
2558 {
2559 case 0x3802: opcode = 0x3401; break; /* Jl +2 -> Jge +1 */
2560 case 0x3402: opcode = 0x3801; break; /* Jge +2 -> Jl +1 */
2561 case 0x2c02: opcode = 0x2801; break; /* Jhs +2 -> Jlo +1 */
2562 case 0x2802: opcode = 0x2c01; break; /* Jlo +2 -> Jhs +1 */
2563 case 0x2402: opcode = 0x2001; break; /* Jeq +2 -> Jne +1 */
2564 case 0x2002: opcode = 0x2401; break; /* jne +2 -> Jeq +1 */
2565 case 0x3002: /* jn +2 */
2566 /* FIXME: There is no direct inverse of the Jn insn. */
2567 continue;
2568 default:
2569 /* The previous opcode does not have a hard-coded jump
2570 that we added when previously relaxing, so relax the
2571 current branch as normal. */
2572 opcode = 0x3c00;
2573 break;
2574 }
d60f5448 2575 if (debug_relocs)
ac4280da 2576 printf ("(shrinking with new opcode 0x%x)\n", opcode);
23d4663e 2577
ac4280da
JL		 2578 if (opcode != 0x3c00)
2579 {
2580 /* Invert the opcode of the conditional jump. */
2581 bfd_put_16 (abfd, opcode, contents + irel->r_offset - 4);
2582 irel->r_offset -= 4;
2583
2584 /* Delete 4 bytes - the full BR insn. */
2585 if (!msp430_elf_relax_delete_bytes (abfd, sec,
2586 irel->r_offset + 2, 4))
2587 goto error_return;
2588 }
2589 else
2590 {
2591 /* Fix the opcode right way. */
2592 bfd_put_16 (abfd, opcode, contents + irel->r_offset - 2);
2593 irel->r_offset -= 2;
2594
2595 /* Delete bytes. */
2596 if (!msp430_elf_relax_delete_bytes (abfd, sec,
2597 irel->r_offset + 2, 2))
2598 goto error_return;
2599 }
23d4663e
NC		 2600
2601 /* That will change things, so, we should relax again.
2602 Note that this is not required, and it may be slow. */
0a1b45a2 2603 *again = true;
23d4663e
NC		 2604 }
2605 }
13761a11 2606 }
b18c562e
NC		 2607
2608 if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf)
2609 {
2610 if (!link_info->keep_memory)
2611 free (isymbuf);
2612 else
2613 {
2614 /* Cache the symbols for elf_link_input_bfd. */
2615 symtab_hdr->contents = (unsigned char *) isymbuf;
2616 }
2617 }
2618
2619 if (contents != NULL
2620 && elf_section_data (sec)->this_hdr.contents != contents)
2621 {
2622 if (!link_info->keep_memory)
2623 free (contents);
2624 else
2625 {
2626 /* Cache the section contents for elf_link_input_bfd. */
2627 elf_section_data (sec)->this_hdr.contents = contents;
2628 }
2629 }
2630
c9594989 2631 if (elf_section_data (sec)->relocs != internal_relocs)
b18c562e
NC		 2632 free (internal_relocs);
2633
0a1b45a2 2634 return true;
b18c562e 2635
dc1e8a47 2636 error_return:
c9594989 2637 if (symtab_hdr->contents != (unsigned char *) isymbuf)
b18c562e 2638 free (isymbuf);
c9594989 2639 if (elf_section_data (sec)->this_hdr.contents != contents)
b18c562e 2640 free (contents);
c9594989 2641 if (elf_section_data (sec)->relocs != internal_relocs)
b18c562e
NC		 2642 free (internal_relocs);
2643
0a1b45a2 2644 return false;
b18c562e
NC		 2645}
2646
13761a11
NC		 2647/* Handle an MSP430 specific section when reading an object file.
2648 This is called when bfd_section_from_shdr finds a section with
2649 an unknown type. */
2650
0a1b45a2 2651static bool
13761a11
NC		 2652elf32_msp430_section_from_shdr (bfd *abfd,
2653 Elf_Internal_Shdr * hdr,
2654 const char *name,
2655 int shindex)
2656{
2657 switch (hdr->sh_type)
2658 {
2659 case SHT_MSP430_SEC_FLAGS:
2660 case SHT_MSP430_SYM_ALIASES:
2661 case SHT_MSP430_ATTRIBUTES:
2662 return _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex);
2663 default:
0a1b45a2 2664 return false;
13761a11
NC		 2665 }
2666}
2667
0a1b45a2 2668static bool
13761a11
NC		 2669elf32_msp430_obj_attrs_handle_unknown (bfd *abfd, int tag)
2670{
2671 _bfd_error_handler
695344c0 2672 /* xgettext:c-format */
38f14ab8 2673 (_("warning: %pB: unknown MSPABI object attribute %d"),
13761a11 2674 abfd, tag);
0a1b45a2 2675 return true;
13761a11
NC		 2676}
2677
2678/* Determine whether an object attribute tag takes an integer, a
2679 string or both. */
2680
2681static int
2682elf32_msp430_obj_attrs_arg_type (int tag)
2683{
2684 if (tag == Tag_compatibility)
2685 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2686
2687 if (tag < 32)
2688 return ATTR_TYPE_FLAG_INT_VAL;
2689
2690 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
2691}
2692
2693static inline const char *
2694isa_type (int isa)
2695{
2696 switch (isa)
2697 {
2698 case 1: return "MSP430";
2699 case 2: return "MSP430X";
2700 default: return "unknown";
2701 }
2702}
2703
2704static inline const char *
2705code_model (int model)
2706{
2707 switch (model)
2708 {
2709 case 1: return "small";
2710 case 2: return "large";
2711 default: return "unknown";
2712 }
2713}
2714
2715static inline const char *
2716data_model (int model)
2717{
2718 switch (model)
2719 {
2720 case 1: return "small";
2721 case 2: return "large";
2722 case 3: return "restricted large";
2723 default: return "unknown";
2724 }
2725}
2726
c0ea7c52 2727/* Merge MSPABI and GNU object attributes from IBFD into OBFD.
13761a11
NC		 2728 Raise an error if there are conflicting attributes. */
2729
0a1b45a2 2730static bool
c0ea7c52 2731elf32_msp430_merge_msp430_attributes (bfd *ibfd, struct bfd_link_info *info)
13761a11 2732{
50e03d47 2733 bfd *obfd = info->output_bfd;
c0ea7c52
JL		 2734 obj_attribute *in_msp_attr, *in_gnu_attr;
2735 obj_attribute *out_msp_attr, *out_gnu_attr;
0a1b45a2 2736 bool result = true;
13761a11
NC		 2737 static bfd * first_input_bfd = NULL;
2738
2739 /* Skip linker created files. */
2740 if (ibfd->flags & BFD_LINKER_CREATED)
0a1b45a2 2741 return true;
13761a11 2742
ca94519e
JL		 2743 /* LTO can create temporary files for linking which may not have an attribute
2744 section. */
2745 if (ibfd->lto_output
2746 && bfd_get_section_by_name (ibfd, ".MSP430.attributes") == NULL)
0a1b45a2 2747 return true;
ca94519e 2748
13761a11
NC		 2749 /* If this is the first real object just copy the attributes. */
2750 if (!elf_known_obj_attributes_proc (obfd)[0].i)
2751 {
2752 _bfd_elf_copy_obj_attributes (ibfd, obfd);
2753
c0ea7c52 2754 out_msp_attr = elf_known_obj_attributes_proc (obfd);
13761a11
NC		 2755
2756 /* Use the Tag_null value to indicate that
2757 the attributes have been initialized. */
c0ea7c52 2758 out_msp_attr[0].i = 1;
13761a11
NC		 2759
2760 first_input_bfd = ibfd;
0a1b45a2 2761 return true;
13761a11
NC		 2762 }
2763
c0ea7c52
JL		 2764 in_msp_attr = elf_known_obj_attributes_proc (ibfd);
2765 out_msp_attr = elf_known_obj_attributes_proc (obfd);
2766 in_gnu_attr = elf_known_obj_attributes (ibfd) [OBJ_ATTR_GNU];
2767 out_gnu_attr = elf_known_obj_attributes (obfd) [OBJ_ATTR_GNU];
13761a11
NC		 2768
2769 /* The ISAs must be the same. */
c0ea7c52 2770 if (in_msp_attr[OFBA_MSPABI_Tag_ISA].i != out_msp_attr[OFBA_MSPABI_Tag_ISA].i)
13761a11
NC		 2771 {
2772 _bfd_error_handler
695344c0 2773 /* xgettext:c-format */
871b3ab2 2774 (_("error: %pB uses %s instructions but %pB uses %s"),
c0ea7c52
JL		 2775 ibfd, isa_type (in_msp_attr[OFBA_MSPABI_Tag_ISA].i),
2776 first_input_bfd, isa_type (out_msp_attr[OFBA_MSPABI_Tag_ISA].i));
0a1b45a2 2777 result = false;
13761a11
NC		 2778 }
2779
2780 /* The code models must be the same. */
c0ea7c52
JL		 2781 if (in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i
2782 != out_msp_attr[OFBA_MSPABI_Tag_Code_Model].i)
13761a11
NC		 2783 {
2784 _bfd_error_handler
695344c0 2785 /* xgettext:c-format */
871b3ab2 2786 (_("error: %pB uses the %s code model whereas %pB uses the %s code model"),
c0ea7c52
JL		 2787 ibfd, code_model (in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i),
2788 first_input_bfd,
2789 code_model (out_msp_attr[OFBA_MSPABI_Tag_Code_Model].i));
0a1b45a2 2790 result = false;
13761a11
NC		 2791 }
2792
2793 /* The large code model is only supported by the MSP430X. */
c0ea7c52
JL		 2794 if (in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i == 2
2795 && out_msp_attr[OFBA_MSPABI_Tag_ISA].i != 2)
13761a11
NC		 2796 {
2797 _bfd_error_handler
695344c0 2798 /* xgettext:c-format */
871b3ab2 2799 (_("error: %pB uses the large code model but %pB uses MSP430 instructions"),
13761a11 2800 ibfd, first_input_bfd);
0a1b45a2 2801 result = false;
13761a11
NC		 2802 }
2803
2804 /* The data models must be the same. */
c0ea7c52
JL		 2805 if (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i
2806 != out_msp_attr[OFBA_MSPABI_Tag_Data_Model].i)
13761a11
NC		 2807 {
2808 _bfd_error_handler
695344c0 2809 /* xgettext:c-format */
871b3ab2 2810 (_("error: %pB uses the %s data model whereas %pB uses the %s data model"),
c0ea7c52
JL		 2811 ibfd, data_model (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i),
2812 first_input_bfd,
2813 data_model (out_msp_attr[OFBA_MSPABI_Tag_Data_Model].i));
0a1b45a2 2814 result = false;
13761a11
NC		 2815 }
2816
2817 /* The small code model requires the use of the small data model. */
c0ea7c52
JL		 2818 if (in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i == 1
2819 && out_msp_attr[OFBA_MSPABI_Tag_Data_Model].i != 1)
13761a11
NC		 2820 {
2821 _bfd_error_handler
695344c0 2822 /* xgettext:c-format */
871b3ab2 2823 (_("error: %pB uses the small code model but %pB uses the %s data model"),
13761a11 2824 ibfd, first_input_bfd,
c0ea7c52 2825 data_model (out_msp_attr[OFBA_MSPABI_Tag_Data_Model].i));
0a1b45a2 2826 result = false;
13761a11
NC		 2827 }
2828
2829 /* The large data models are only supported by the MSP430X. */
c0ea7c52
JL		 2830 if (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i > 1
2831 && out_msp_attr[OFBA_MSPABI_Tag_ISA].i != 2)
13761a11
NC		 2832 {
2833 _bfd_error_handler
695344c0 2834 /* xgettext:c-format */
871b3ab2 2835 (_("error: %pB uses the %s data model but %pB only uses MSP430 instructions"),
c0ea7c52 2836 ibfd, data_model (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i),
c08bb8dd 2837 first_input_bfd);
0a1b45a2 2838 result = false;
13761a11 2839 }
1b786873 2840
c0ea7c52
JL		 2841 /* Just ignore the data region unless the large memory model is in use.
2842 We have already checked that ibfd and obfd use the same memory model. */
2843 if ((in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i
2844 == OFBA_MSPABI_Val_Code_Model_LARGE)
2845 && (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i
2846 == OFBA_MSPABI_Val_Data_Model_LARGE))
2847 {
2848 /* We cannot allow "lower region only" to be linked with any other
2849 values (i.e. ANY or NONE).
2850 Before this attribute existed, "ANY" region was the default. */
0a1b45a2 2851 bool ibfd_lower_region_used
c0ea7c52
JL		 2852 = (in_gnu_attr[Tag_GNU_MSP430_Data_Region].i
2853 == Val_GNU_MSP430_Data_Region_Lower);
0a1b45a2 2854 bool obfd_lower_region_used
c0ea7c52
JL		 2855 = (out_gnu_attr[Tag_GNU_MSP430_Data_Region].i
2856 == Val_GNU_MSP430_Data_Region_Lower);
2857 if (ibfd_lower_region_used != obfd_lower_region_used)
2858 {
2859 _bfd_error_handler
2860 (_("error: %pB can use the upper region for data, "
2861 "but %pB assumes data is exclusively in lower memory"),
2862 ibfd_lower_region_used ? obfd : ibfd,
2863 ibfd_lower_region_used ? ibfd : obfd);
0a1b45a2 2864 result = false;
c0ea7c52
JL		 2865 }
2866 }
2867
13761a11
NC		 2868 return result;
2869}
2870
2871/* Merge backend specific data from an object file to the output
2872 object file when linking. */
2873
0a1b45a2 2874static bool
50e03d47 2875elf32_msp430_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
13761a11 2876{
50e03d47 2877 bfd *obfd = info->output_bfd;
13761a11
NC		 2878 /* Make sure that the machine number reflects the most
2879 advanced version of the MSP architecture required. */
2880#define max(a,b) ((a) > (b) ? (a) : (b))
2881 if (bfd_get_mach (ibfd) != bfd_get_mach (obfd))
2882 bfd_default_set_arch_mach (obfd, bfd_get_arch (obfd),
2883 max (bfd_get_mach (ibfd), bfd_get_mach (obfd)));
2884#undef max
2885
c0ea7c52 2886 return elf32_msp430_merge_msp430_attributes (ibfd, info);
13761a11
NC		 2887}
2888
0a1b45a2 2889static bool
13761a11
NC		 2890msp430_elf_is_target_special_symbol (bfd *abfd, asymbol *sym)
2891{
2892 return _bfd_elf_is_local_label_name (abfd, sym->name);
2893}
2894
0a1b45a2 2895static bool
79559014
NC		 2896uses_large_model (bfd *abfd)
2897{
2898 obj_attribute * attr;
2899
2900 if (abfd->flags & BFD_LINKER_CREATED)
0a1b45a2 2901 return false;
79559014
NC		 2902
2903 attr = elf_known_obj_attributes_proc (abfd);
2904 if (attr == NULL)
0a1b45a2 2905 return false;
79559014
NC		 2906
2907 return attr[OFBA_MSPABI_Tag_Code_Model].i == 2;
2908}
2909
2910static unsigned int
76c20d54
AM		 2911elf32_msp430_eh_frame_address_size (bfd *abfd,
2912 const asection *sec ATTRIBUTE_UNUSED)
79559014
NC		 2913{
2914 return uses_large_model (abfd) ? 4 : 2;
2915}
2916
13761a11
NC		 2917/* This is gross. The MSP430 EABI says that (sec 11.5):
2918
2919 "An implementation may choose to use Rel or Rela
2920 type relocations for other relocations."
2921
2922 But it also says that:
1b786873 2923
13761a11
NC		 2924 "Certain relocations are identified as Rela only. [snip]
2925 Where Rela is specified, an implementation must honor
2926 this requirement."
2927
2928 There is one relocation marked as requiring RELA - R_MSP430_ABS_HI16 - but
2929 to keep things simple we choose to use RELA relocations throughout. The
2930 problem is that the TI compiler generates REL relocations, so we have to
2931 be able to accept those as well. */
2932
2933#define elf_backend_may_use_rel_p 1
2934#define elf_backend_may_use_rela_p 1
2935#define elf_backend_default_use_rela_p 1
2936
07d6d2b8 2937#undef elf_backend_obj_attrs_vendor
13761a11 2938#define elf_backend_obj_attrs_vendor "mspabi"
07d6d2b8 2939#undef elf_backend_obj_attrs_section
13761a11 2940#define elf_backend_obj_attrs_section ".MSP430.attributes"
07d6d2b8 2941#undef elf_backend_obj_attrs_section_type
13761a11 2942#define elf_backend_obj_attrs_section_type SHT_MSP430_ATTRIBUTES
07d6d2b8
AM		 2943#define elf_backend_section_from_shdr elf32_msp430_section_from_shdr
2944#define elf_backend_obj_attrs_handle_unknown elf32_msp430_obj_attrs_handle_unknown
2945#undef elf_backend_obj_attrs_arg_type
13761a11 2946#define elf_backend_obj_attrs_arg_type elf32_msp430_obj_attrs_arg_type
13761a11 2947#define bfd_elf32_bfd_merge_private_bfd_data elf32_msp430_merge_private_bfd_data
79559014 2948#define elf_backend_eh_frame_address_size elf32_msp430_eh_frame_address_size
2469cfa2
NC		 2949
2950#define ELF_ARCH bfd_arch_msp430
2951#define ELF_MACHINE_CODE EM_MSP430
2952#define ELF_MACHINE_ALT1 EM_MSP430_OLD
13761a11 2953#define ELF_MAXPAGESIZE 4
d1036acb 2954#define ELF_OSABI ELFOSABI_STANDALONE
2469cfa2 2955
07d6d2b8 2956#define TARGET_LITTLE_SYM msp430_elf32_vec
2469cfa2
NC		 2957#define TARGET_LITTLE_NAME "elf32-msp430"
2958
07d6d2b8
AM		 2959#define elf_info_to_howto msp430_info_to_howto_rela
2960#define elf_info_to_howto_rel NULL
2961#define elf_backend_relocate_section elf32_msp430_relocate_section
2962#define elf_backend_check_relocs elf32_msp430_check_relocs
2963#define elf_backend_can_gc_sections 1
2469cfa2
NC		 2964#define elf_backend_final_write_processing bfd_elf_msp430_final_write_processing
2965#define elf_backend_object_p elf32_msp430_object_p
b18c562e 2966#define bfd_elf32_bfd_relax_section msp430_elf_relax_section
13761a11
NC		 2967#define bfd_elf32_bfd_is_target_special_symbol msp430_elf_is_target_special_symbol
2968
07d6d2b8 2969#undef elf32_bed
13761a11
NC		 2970#define elf32_bed elf32_msp430_bed
2971
2972#include "elf32-target.h"
2973
2974/* The TI compiler sets the OSABI field to ELFOSABI_NONE. */
07d6d2b8
AM		 2975#undef TARGET_LITTLE_SYM
2976#define TARGET_LITTLE_SYM msp430_elf32_ti_vec
13761a11 2977
07d6d2b8 2978#undef elf32_bed
13761a11
NC		 2979#define elf32_bed elf32_msp430_ti_bed
2980
1b786873 2981#undef ELF_OSABI
13761a11
NC		 2982#define ELF_OSABI ELFOSABI_NONE
2983
2984static const struct bfd_elf_special_section msp430_ti_elf_special_sections[] =
2985{
07d6d2b8 2986 /* prefix, prefix_length, suffix_len, type, attributes. */
13761a11
NC		 2987 { STRING_COMMA_LEN (".TI.symbol.alias"), 0, SHT_MSP430_SYM_ALIASES, 0 },
2988 { STRING_COMMA_LEN (".TI.section.flags"), 0, SHT_MSP430_SEC_FLAGS, 0 },
2989 { STRING_COMMA_LEN ("_TI_build_attrib"), 0, SHT_MSP430_ATTRIBUTES, 0 },
07d6d2b8 2990 { NULL, 0, 0, 0, 0 }
13761a11 2991};
2469cfa2 2992
07d6d2b8
AM		 2993#undef elf_backend_special_sections
2994#define elf_backend_special_sections msp430_ti_elf_special_sections
b6518b38 2995
2469cfa2 2996#include "elf32-target.h"
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