[thirdparty/binutils-gdb.git] / bfd / verilog.c

/* BFD back-end for verilog hex memory dump files.
   Copyright (C) 2009-2021 Free Software Foundation, Inc.
   Written by Anthony Green <green@moxielogic.com>

   This file is part of BFD, the Binary File Descriptor library.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */


/* SUBSECTION
	Verilog hex memory file handling

   DESCRIPTION

	Verilog hex memory files cannot hold anything but addresses
	and data, so that's all that we implement.

	The syntax of the text file is described in the IEEE standard
	for Verilog.  Briefly, the file contains two types of tokens:
	data and optional addresses.  The tokens are separated by
	whitespace and comments.  Comments may be single line or
	multiline, using syntax similar to C++.  Addresses are
	specified by a leading "at" character (@) and are always
	hexadecimal strings.  Data and addresses may contain
	underscore (_) characters.

	If no address is specified, the data is assumed to start at
	address 0.  Similarly, if data exists before the first
	specified address, then that data is assumed to start at
	address 0.


   EXAMPLE
	@1000
	01 ae 3f 45 12

   DESCRIPTION
	@1000 specifies the starting address for the memory data.
	The following characters describe the 5 bytes at 0x1000.  */


#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
#include "libiberty.h"
#include "safe-ctype.h"

/* Modified by obcopy.c
   Data width in bytes.  */
unsigned int VerilogDataWidth = 1;

/* Macros for converting between hex and binary.  */

static const char digs[] = "0123456789ABCDEF";

#define NIBBLE(x)    hex_value (x)
#define HEX(buffer) ((NIBBLE ((buffer)[0]) << 4) + NIBBLE ((buffer)[1]))
#define TOHEX(d, x) \
	d[1] = digs[(x) & 0xf]; \
	d[0] = digs[((x) >> 4) & 0xf];

/* When writing a verilog memory dump file, we write them in the order
   in which they appear in memory. This structure is used to hold them
   in memory.  */

struct verilog_data_list_struct
{
  struct verilog_data_list_struct *next;
  bfd_byte * data;
  bfd_vma where;
  bfd_size_type size;
};

typedef struct verilog_data_list_struct verilog_data_list_type;

/* The verilog tdata information.  */

typedef struct verilog_data_struct
{
  verilog_data_list_type *head;
  verilog_data_list_type *tail;
}
tdata_type;

static bfd_boolean
verilog_set_arch_mach (bfd *abfd, enum bfd_architecture arch, unsigned long mach)
{
  if (arch != bfd_arch_unknown)
    return bfd_default_set_arch_mach (abfd, arch, mach);

  abfd->arch_info = & bfd_default_arch_struct;
  return TRUE;
}

/* We have to save up all the outpu for a splurge before output.  */

static bfd_boolean
verilog_set_section_contents (bfd *abfd,
			      sec_ptr section,
			      const void * location,
			      file_ptr offset,
			      bfd_size_type bytes_to_do)
{
  tdata_type *tdata = abfd->tdata.verilog_data;
  verilog_data_list_type *entry;

  entry = (verilog_data_list_type *) bfd_alloc (abfd, sizeof (* entry));
  if (entry == NULL)
    return FALSE;

  if (bytes_to_do
      && (section->flags & SEC_ALLOC)
      && (section->flags & SEC_LOAD))
    {
      bfd_byte *data;

      data = (bfd_byte *) bfd_alloc (abfd, bytes_to_do);
      if (data == NULL)
	return FALSE;
      memcpy ((void *) data, location, (size_t) bytes_to_do);

      entry->data = data;
      entry->where = section->lma + offset;
      entry->size = bytes_to_do;

      /* Sort the records by address.  Optimize for the common case of
	 adding a record to the end of the list.  */
      if (tdata->tail != NULL
	  && entry->where >= tdata->tail->where)
	{
	  tdata->tail->next = entry;
	  entry->next = NULL;
	  tdata->tail = entry;
	}
      else
	{
	  verilog_data_list_type **look;

	  for (look = &tdata->head;
	       *look != NULL && (*look)->where < entry->where;
	       look = &(*look)->next)
	    ;
	  entry->next = *look;
	  *look = entry;
	  if (entry->next == NULL)
	    tdata->tail = entry;
	}
    }
  return TRUE;
}

static bfd_boolean
verilog_write_address (bfd *abfd, bfd_vma address)
{
  char buffer[20];
  char *dst = buffer;
  bfd_size_type wrlen;

  /* Write the address.  */
  *dst++ = '@';
#ifdef BFD64
  if (address >= (bfd_vma)1 << 32)
    {
      TOHEX (dst, (address >> 56));
      dst += 2;
      TOHEX (dst, (address >> 48));
      dst += 2;
      TOHEX (dst, (address >> 40));
      dst += 2;
      TOHEX (dst, (address >> 32));
      dst += 2;
    }
#endif
  TOHEX (dst, (address >> 24));
  dst += 2;
  TOHEX (dst, (address >> 16));
  dst += 2;
  TOHEX (dst, (address >> 8));
  dst += 2;
  TOHEX (dst, (address));
  dst += 2;
  *dst++ = '\r';
  *dst++ = '\n';
  wrlen = dst - buffer;

  return bfd_bwrite ((void *) buffer, wrlen, abfd) == wrlen;
}

/* Write a record of type, of the supplied number of bytes. The
   supplied bytes and length don't have a checksum.  That's worked
   out here.  */

static bfd_boolean
verilog_write_record (bfd *abfd,
		      const bfd_byte *data,
		      const bfd_byte *end)
{
  char buffer[52];
  const bfd_byte *src = data;
  char *dst = buffer;
  bfd_size_type wrlen;

  /* Paranoia - check that we will not overflow "buffer".  */
  if (((end - data) * 2) /* Number of hex characters we want to emit.  */
      + ((end - data) / VerilogDataWidth) /* Number of spaces we want to emit.  */
      + 2 /* The carriage return & line feed characters.  */
      > (long) sizeof (buffer))
    {
      /* FIXME: Should we generate an error message ?  */
      return FALSE;
    }

  /* Write the data.
     FIXME: Under some circumstances we can emit a space at the end of
     the line.  This is not really necessary, but catching these cases
     would make the code more complicated.  */
  if (VerilogDataWidth == 1)
    {
      for (src = data; src < end;)
	{
	  TOHEX (dst, *src);
	  dst += 2;
	  src ++;
	  if (src < end)
	    *dst++ = ' ';
	}
    }
  else if (bfd_little_endian (abfd))
    {
      /* If the input byte stream contains:
	   05 04 03 02 01 00
	 and VerilogDataWidth is 4 then we want to emit:
           02030405 0001  */
      int i;

      for (src = data; src < (end - VerilogDataWidth); src += VerilogDataWidth)
	{
	  for (i = VerilogDataWidth - 1; i >= 0; i--)
	    {
	      TOHEX (dst, src[i]);
	      dst += 2;
	    }
	  *dst++ = ' ';
	}

      /* Emit any remaining bytes.  Be careful not to read beyond "end".  */
      while (end > src)
	{
	  -- end;
	  TOHEX (dst, *end);
	  dst += 2;
	}
    }
  else
    {
      for (src = data; src < end;)
	{
	  TOHEX (dst, *src);
	  dst += 2;
	  ++ src;
	  if ((src - data) % VerilogDataWidth == 0)
	    *dst++ = ' ';
	}
    }

  *dst++ = '\r';
  *dst++ = '\n';
  wrlen = dst - buffer;

  return bfd_bwrite ((void *) buffer, wrlen, abfd) == wrlen;
}

static bfd_boolean
verilog_write_section (bfd *abfd,
		       tdata_type *tdata ATTRIBUTE_UNUSED,
		       verilog_data_list_type *list)
{
  unsigned int octets_written = 0;
  bfd_byte *location = list->data;

  verilog_write_address (abfd, list->where);
  while (octets_written < list->size)
    {
      unsigned int octets_this_chunk = list->size - octets_written;

      if (octets_this_chunk > 16)
	octets_this_chunk = 16;

      if (! verilog_write_record (abfd,
				  location,
				  location + octets_this_chunk))
	return FALSE;

      octets_written += octets_this_chunk;
      location += octets_this_chunk;
    }

  return TRUE;
}

static bfd_boolean
verilog_write_object_contents (bfd *abfd)
{
  tdata_type *tdata = abfd->tdata.verilog_data;
  verilog_data_list_type *list;

  /* Now wander though all the sections provided and output them.  */
  list = tdata->head;

  while (list != (verilog_data_list_type *) NULL)
    {
      if (! verilog_write_section (abfd, tdata, list))
	return FALSE;
      list = list->next;
    }
  return TRUE;
}

/* Initialize by filling in the hex conversion array.  */

static void
verilog_init (void)
{
  static bfd_boolean inited = FALSE;

  if (! inited)
    {
      inited = TRUE;
      hex_init ();
    }
}

/* Set up the verilog tdata information.  */

static bfd_boolean
verilog_mkobject (bfd *abfd)
{
  tdata_type *tdata;

  verilog_init ();

  tdata = (tdata_type *) bfd_alloc (abfd, sizeof (tdata_type));
  if (tdata == NULL)
    return FALSE;

  abfd->tdata.verilog_data = tdata;
  tdata->head = NULL;
  tdata->tail = NULL;

  return TRUE;
}

#define verilog_close_and_cleanup		     _bfd_generic_close_and_cleanup
#define verilog_bfd_free_cached_info		     _bfd_generic_bfd_free_cached_info
#define verilog_new_section_hook		     _bfd_generic_new_section_hook
#define verilog_bfd_is_target_special_symbol	     _bfd_bool_bfd_asymbol_false
#define verilog_bfd_is_local_label_name		     bfd_generic_is_local_label_name
#define verilog_get_lineno			     _bfd_nosymbols_get_lineno
#define verilog_find_nearest_line		     _bfd_nosymbols_find_nearest_line
#define verilog_find_inliner_info		     _bfd_nosymbols_find_inliner_info
#define verilog_make_empty_symbol		     _bfd_generic_make_empty_symbol
#define verilog_bfd_make_debug_symbol		     _bfd_nosymbols_bfd_make_debug_symbol
#define verilog_read_minisymbols		     _bfd_generic_read_minisymbols
#define verilog_minisymbol_to_symbol		     _bfd_generic_minisymbol_to_symbol
#define verilog_get_section_contents_in_window	     _bfd_generic_get_section_contents_in_window
#define verilog_bfd_get_relocated_section_contents   bfd_generic_get_relocated_section_contents
#define verilog_bfd_relax_section		     bfd_generic_relax_section
#define verilog_bfd_gc_sections			     bfd_generic_gc_sections
#define verilog_bfd_merge_sections		     bfd_generic_merge_sections
#define verilog_bfd_is_group_section		     bfd_generic_is_group_section
#define verilog_bfd_group_name			     bfd_generic_group_name
#define verilog_bfd_discard_group		     bfd_generic_discard_group
#define verilog_section_already_linked		     _bfd_generic_section_already_linked
#define verilog_bfd_link_hash_table_create	     _bfd_generic_link_hash_table_create
#define verilog_bfd_link_add_symbols		     _bfd_generic_link_add_symbols
#define verilog_bfd_link_just_syms		     _bfd_generic_link_just_syms
#define verilog_bfd_final_link			     _bfd_generic_final_link
#define verilog_bfd_link_split_section		     _bfd_generic_link_split_section

const bfd_target verilog_vec =
{
  "verilog",			/* Name.  */
  bfd_target_verilog_flavour,
  BFD_ENDIAN_UNKNOWN,		/* Target byte order.  */
  BFD_ENDIAN_UNKNOWN,		/* Target headers byte order.  */
  (HAS_RELOC | EXEC_P |		/* Object flags.  */
   HAS_LINENO | HAS_DEBUG |
   HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED),
  (SEC_CODE | SEC_DATA | SEC_ROM | SEC_HAS_CONTENTS
   | SEC_ALLOC | SEC_LOAD | SEC_RELOC),	/* Section flags.  */
  0,				/* Leading underscore.  */
  ' ',				/* AR_pad_char.  */
  16,				/* AR_max_namelen.  */
  0,				/* match priority.  */
  bfd_getb64, bfd_getb_signed_64, bfd_putb64,
  bfd_getb32, bfd_getb_signed_32, bfd_putb32,
  bfd_getb16, bfd_getb_signed_16, bfd_putb16,	/* Data.  */
  bfd_getb64, bfd_getb_signed_64, bfd_putb64,
  bfd_getb32, bfd_getb_signed_32, bfd_putb32,
  bfd_getb16, bfd_getb_signed_16, bfd_putb16,	/* Hdrs.  */

  {
    _bfd_dummy_target,
    _bfd_dummy_target,
    _bfd_dummy_target,
    _bfd_dummy_target,
  },
  {
    _bfd_bool_bfd_false_error,
    verilog_mkobject,
    _bfd_bool_bfd_false_error,
    _bfd_bool_bfd_false_error,
  },
  {				/* bfd_write_contents.  */
    _bfd_bool_bfd_false_error,
    verilog_write_object_contents,
    _bfd_bool_bfd_false_error,
    _bfd_bool_bfd_false_error,
  },

  BFD_JUMP_TABLE_GENERIC (_bfd_generic),
  BFD_JUMP_TABLE_COPY (_bfd_generic),
  BFD_JUMP_TABLE_CORE (_bfd_nocore),
  BFD_JUMP_TABLE_ARCHIVE (_bfd_noarchive),
  BFD_JUMP_TABLE_SYMBOLS (_bfd_nosymbols),
  BFD_JUMP_TABLE_RELOCS (_bfd_norelocs),
  BFD_JUMP_TABLE_WRITE (verilog),
  BFD_JUMP_TABLE_LINK (_bfd_nolink),
  BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),

  NULL,

  NULL
};
Commit	Line	Data
c067354b	1	/* BFD back-end for verilog hex memory dump files.
250d07de	2	Copyright (C) 2009-2021 Free Software Foundation, Inc.
c067354b NC	3	Written by Anthony Green <green@moxielogic.com>
	4
	5	This file is part of BFD, the Binary File Descriptor library.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 3 of the License, or
	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program; if not, write to the Free Software
	19	Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
	20	MA 02110-1301, USA. */
	21
	22
	23	/* SUBSECTION
	24	Verilog hex memory file handling
	25
	26	DESCRIPTION
	27
	28	Verilog hex memory files cannot hold anything but addresses
	29	and data, so that's all that we implement.
	30
	31	The syntax of the text file is described in the IEEE standard
	32	for Verilog. Briefly, the file contains two types of tokens:
	33	data and optional addresses. The tokens are separated by
	34	whitespace and comments. Comments may be single line or
	35	multiline, using syntax similar to C++. Addresses are
	36	specified by a leading "at" character (@) and are always
	37	hexadecimal strings. Data and addresses may contain
	38	underscore (_) characters.
	39
	40	If no address is specified, the data is assumed to start at
	41	address 0. Similarly, if data exists before the first
	42	specified address, then that data is assumed to start at
	43	address 0.
	44
	45
	46	EXAMPLE
	47	@1000
07d6d2b8	48	01 ae 3f 45 12
c067354b NC	49
	50	DESCRIPTION
	51	@1000 specifies the starting address for the memory data.
	52	The following characters describe the 5 bytes at 0x1000. */
	53
	54
	55	#include "sysdep.h"
	56	#include "bfd.h"
	57	#include "libbfd.h"
	58	#include "libiberty.h"
	59	#include "safe-ctype.h"
	60
37d0d091 JH	61	/* Modified by obcopy.c
	62	Data width in bytes. */
	63	unsigned int VerilogDataWidth = 1;
	64
c067354b NC	65	/* Macros for converting between hex and binary. */
	66
	67	static const char digs[] = "0123456789ABCDEF";
	68
37d0d091 JH	69	#define NIBBLE(x) hex_value (x)
37d0d091 JH	70	#define HEX(buffer) ((NIBBLE ((buffer)[0]) << 4) + NIBBLE ((buffer)[1]))
c067354b NC	71	#define TOHEX(d, x) \
	72	d[1] = digs[(x) & 0xf]; \
	73	d[0] = digs[((x) >> 4) & 0xf];
	74
	75	/* When writing a verilog memory dump file, we write them in the order
	76	in which they appear in memory. This structure is used to hold them
	77	in memory. */
	78
	79	struct verilog_data_list_struct
	80	{
	81	struct verilog_data_list_struct *next;
	82	bfd_byte * data;
	83	bfd_vma where;
	84	bfd_size_type size;
	85	};
	86
	87	typedef struct verilog_data_list_struct verilog_data_list_type;
	88
	89	/* The verilog tdata information. */
	90
	91	typedef struct verilog_data_struct
	92	{
	93	verilog_data_list_type *head;
	94	verilog_data_list_type *tail;
	95	}
	96	tdata_type;
	97
	98	static bfd_boolean
	99	verilog_set_arch_mach (bfd *abfd, enum bfd_architecture arch, unsigned long mach)
	100	{
	101	if (arch != bfd_arch_unknown)
	102	return bfd_default_set_arch_mach (abfd, arch, mach);
	103
	104	abfd->arch_info = & bfd_default_arch_struct;
	105	return TRUE;
	106	}
	107
	108	/* We have to save up all the outpu for a splurge before output. */
	109
	110	static bfd_boolean
	111	verilog_set_section_contents (bfd *abfd,
	112	sec_ptr section,
	113	const void * location,
	114	file_ptr offset,
	115	bfd_size_type bytes_to_do)
	116	{
	117	tdata_type *tdata = abfd->tdata.verilog_data;
	118	verilog_data_list_type *entry;
	119
a50b1753	120	entry = (verilog_data_list_type ) bfd_alloc (abfd, sizeof ( entry));
c067354b NC	121	if (entry == NULL)
	122	return FALSE;
	123
	124	if (bytes_to_do
	125	&& (section->flags & SEC_ALLOC)
	126	&& (section->flags & SEC_LOAD))
	127	{
	128	bfd_byte *data;
	129
a50b1753	130	data = (bfd_byte *) bfd_alloc (abfd, bytes_to_do);
c067354b NC	131	if (data == NULL)
	132	return FALSE;
	133	memcpy ((void *) data, location, (size_t) bytes_to_do);
	134
	135	entry->data = data;
	136	entry->where = section->lma + offset;
	137	entry->size = bytes_to_do;
	138
	139	/* Sort the records by address. Optimize for the common case of
	140	adding a record to the end of the list. */
	141	if (tdata->tail != NULL
	142	&& entry->where >= tdata->tail->where)
	143	{
	144	tdata->tail->next = entry;
	145	entry->next = NULL;
	146	tdata->tail = entry;
	147	}
	148	else
	149	{
	150	verilog_data_list_type **look;
	151
	152	for (look = &tdata->head;
	153	look != NULL && (look)->where < entry->where;
	154	look = &(*look)->next)
	155	;
	156	entry->next = *look;
	157	*look = entry;
	158	if (entry->next == NULL)
	159	tdata->tail = entry;
	160	}
	161	}
	162	return TRUE;
	163	}
	164
	165	static bfd_boolean
	166	verilog_write_address (bfd *abfd, bfd_vma address)
	167	{
7def0865	168	char buffer[20];
c067354b NC	169	char *dst = buffer;
	170	bfd_size_type wrlen;
	171
	172	/* Write the address. */
	173	*dst++ = '@';
7def0865 NC	174	#ifdef BFD64
	175	if (address >= (bfd_vma)1 << 32)
	176	{
	177	TOHEX (dst, (address >> 56));
	178	dst += 2;
	179	TOHEX (dst, (address >> 48));
	180	dst += 2;
	181	TOHEX (dst, (address >> 40));
	182	dst += 2;
	183	TOHEX (dst, (address >> 32));
	184	dst += 2;
	185	}
	186	#endif
c067354b NC	187	TOHEX (dst, (address >> 24));
	188	dst += 2;
	189	TOHEX (dst, (address >> 16));
	190	dst += 2;
	191	TOHEX (dst, (address >> 8));
	192	dst += 2;
	193	TOHEX (dst, (address));
	194	dst += 2;
	195	*dst++ = '\r';
	196	*dst++ = '\n';
	197	wrlen = dst - buffer;
	198
	199	return bfd_bwrite ((void *) buffer, wrlen, abfd) == wrlen;
	200	}
	201
	202	/* Write a record of type, of the supplied number of bytes. The
37d0d091 JH	203	supplied bytes and length don't have a checksum. That's worked
37d0d091 JH	204	out here. */
c067354b NC	205
	206	static bfd_boolean
	207	verilog_write_record (bfd *abfd,
	208	const bfd_byte *data,
	209	const bfd_byte *end)
	210	{
37d0d091	211	char buffer[52];
c067354b NC	212	const bfd_byte *src = data;
	213	char *dst = buffer;
	214	bfd_size_type wrlen;
	215
37d0d091 JH	216	/* Paranoia - check that we will not overflow "buffer". */
	217	if (((end - data) * 2) /* Number of hex characters we want to emit. */
	218	+ ((end - data) / VerilogDataWidth) /* Number of spaces we want to emit. */
	219	+ 2 /* The carriage return & line feed characters. */
	220	> (long) sizeof (buffer))
c067354b	221	{
37d0d091 JH	222	/* FIXME: Should we generate an error message ? */
	223	return FALSE;
	224	}
	225
	226	/* Write the data.
	227	FIXME: Under some circumstances we can emit a space at the end of
	228	the line. This is not really necessary, but catching these cases
	229	would make the code more complicated. */
	230	if (VerilogDataWidth == 1)
	231	{
	232	for (src = data; src < end;)
	233	{
	234	TOHEX (dst, *src);
	235	dst += 2;
	236	src ++;
	237	if (src < end)
	238	*dst++ = ' ';
	239	}
c067354b	240	}
37d0d091 JH	241	else if (bfd_little_endian (abfd))
	242	{
	243	/* If the input byte stream contains:
	244	05 04 03 02 01 00
	245	and VerilogDataWidth is 4 then we want to emit:
	246	02030405 0001 */
	247	int i;
	248
	249	for (src = data; src < (end - VerilogDataWidth); src += VerilogDataWidth)
	250	{
	251	for (i = VerilogDataWidth - 1; i >= 0; i--)
	252	{
	253	TOHEX (dst, src[i]);
	254	dst += 2;
	255	}
	256	*dst++ = ' ';
	257	}
	258
	259	/* Emit any remaining bytes. Be careful not to read beyond "end". */
	260	while (end > src)
	261	{
	262	-- end;
	263	TOHEX (dst, *end);
	264	dst += 2;
	265	}
	266	}
	267	else
	268	{
	269	for (src = data; src < end;)
	270	{
	271	TOHEX (dst, *src);
	272	dst += 2;
	273	++ src;
	274	if ((src - data) % VerilogDataWidth == 0)
	275	*dst++ = ' ';
	276	}
	277	}
	278
c067354b NC	279	*dst++ = '\r';
	280	*dst++ = '\n';
	281	wrlen = dst - buffer;
	282
	283	return bfd_bwrite ((void *) buffer, wrlen, abfd) == wrlen;
	284	}
	285
	286	static bfd_boolean
	287	verilog_write_section (bfd *abfd,
	288	tdata_type *tdata ATTRIBUTE_UNUSED,
	289	verilog_data_list_type *list)
	290	{
	291	unsigned int octets_written = 0;
	292	bfd_byte *location = list->data;
	293
	294	verilog_write_address (abfd, list->where);
	295	while (octets_written < list->size)
	296	{
c067354b NC	297	unsigned int octets_this_chunk = list->size - octets_written;
	298
	299	if (octets_this_chunk > 16)
	300	octets_this_chunk = 16;
	301
c067354b NC	302	if (! verilog_write_record (abfd,
	303	location,
	304	location + octets_this_chunk))
	305	return FALSE;
	306
	307	octets_written += octets_this_chunk;
	308	location += octets_this_chunk;
	309	}
	310
	311	return TRUE;
	312	}
	313
	314	static bfd_boolean
	315	verilog_write_object_contents (bfd *abfd)
	316	{
	317	tdata_type *tdata = abfd->tdata.verilog_data;
	318	verilog_data_list_type *list;
	319
	320	/* Now wander though all the sections provided and output them. */
	321	list = tdata->head;
	322
	323	while (list != (verilog_data_list_type *) NULL)
	324	{
	325	if (! verilog_write_section (abfd, tdata, list))
	326	return FALSE;
	327	list = list->next;
	328	}
	329	return TRUE;
	330	}
	331
	332	/* Initialize by filling in the hex conversion array. */
	333
	334	static void
	335	verilog_init (void)
	336	{
	337	static bfd_boolean inited = FALSE;
	338
	339	if (! inited)
	340	{
	341	inited = TRUE;
	342	hex_init ();
	343	}
	344	}
	345
	346	/* Set up the verilog tdata information. */
	347
	348	static bfd_boolean
	349	verilog_mkobject (bfd *abfd)
	350	{
	351	tdata_type *tdata;
	352
	353	verilog_init ();
	354
a50b1753	355	tdata = (tdata_type *) bfd_alloc (abfd, sizeof (tdata_type));
c067354b NC	356	if (tdata == NULL)
	357	return FALSE;
	358
	359	abfd->tdata.verilog_data = tdata;
	360	tdata->head = NULL;
	361	tdata->tail = NULL;
	362
	363	return TRUE;
	364	}
	365
07d6d2b8 AM	366	#define verilog_close_and_cleanup _bfd_generic_close_and_cleanup
	367	#define verilog_bfd_free_cached_info _bfd_generic_bfd_free_cached_info
	368	#define verilog_new_section_hook _bfd_generic_new_section_hook
d00dd7dc	369	#define verilog_bfd_is_target_special_symbol _bfd_bool_bfd_asymbol_false
07d6d2b8 AM	370	#define verilog_bfd_is_local_label_name bfd_generic_is_local_label_name
	371	#define verilog_get_lineno _bfd_nosymbols_get_lineno
	372	#define verilog_find_nearest_line _bfd_nosymbols_find_nearest_line
	373	#define verilog_find_inliner_info _bfd_nosymbols_find_inliner_info
	374	#define verilog_make_empty_symbol _bfd_generic_make_empty_symbol
	375	#define verilog_bfd_make_debug_symbol _bfd_nosymbols_bfd_make_debug_symbol
	376	#define verilog_read_minisymbols _bfd_generic_read_minisymbols
	377	#define verilog_minisymbol_to_symbol _bfd_generic_minisymbol_to_symbol
	378	#define verilog_get_section_contents_in_window _bfd_generic_get_section_contents_in_window
c067354b	379	#define verilog_bfd_get_relocated_section_contents bfd_generic_get_relocated_section_contents
07d6d2b8 AM	380	#define verilog_bfd_relax_section bfd_generic_relax_section
	381	#define verilog_bfd_gc_sections bfd_generic_gc_sections
	382	#define verilog_bfd_merge_sections bfd_generic_merge_sections
	383	#define verilog_bfd_is_group_section bfd_generic_is_group_section
cb7f4b29	384	#define verilog_bfd_group_name bfd_generic_group_name
07d6d2b8 AM	385	#define verilog_bfd_discard_group bfd_generic_discard_group
	386	#define verilog_section_already_linked _bfd_generic_section_already_linked
	387	#define verilog_bfd_link_hash_table_create _bfd_generic_link_hash_table_create
	388	#define verilog_bfd_link_add_symbols _bfd_generic_link_add_symbols
	389	#define verilog_bfd_link_just_syms _bfd_generic_link_just_syms
	390	#define verilog_bfd_final_link _bfd_generic_final_link
	391	#define verilog_bfd_link_split_section _bfd_generic_link_split_section
c067354b NC	392
	393	const bfd_target verilog_vec =
	394	{
	395	"verilog", /* Name. */
	396	bfd_target_verilog_flavour,
	397	BFD_ENDIAN_UNKNOWN, /* Target byte order. */
	398	BFD_ENDIAN_UNKNOWN, /* Target headers byte order. */
	399	(HAS_RELOC \| EXEC_P \| /* Object flags. */
	400	HAS_LINENO \| HAS_DEBUG \|
	401	HAS_SYMS \| HAS_LOCALS \| WP_TEXT \| D_PAGED),
	402	(SEC_CODE \| SEC_DATA \| SEC_ROM \| SEC_HAS_CONTENTS
	403	\| SEC_ALLOC \| SEC_LOAD \| SEC_RELOC), /* Section flags. */
	404	0, /* Leading underscore. */
	405	' ', /* AR_pad_char. */
	406	16, /* AR_max_namelen. */
0aabe54e	407	0, /* match priority. */
c067354b NC	408	bfd_getb64, bfd_getb_signed_64, bfd_putb64,
	409	bfd_getb32, bfd_getb_signed_32, bfd_putb32,
	410	bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* Data. */
	411	bfd_getb64, bfd_getb_signed_64, bfd_putb64,
	412	bfd_getb32, bfd_getb_signed_32, bfd_putb32,
	413	bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* Hdrs. */
	414
	415	{
	416	_bfd_dummy_target,
	417	_bfd_dummy_target,
	418	_bfd_dummy_target,
	419	_bfd_dummy_target,
	420	},
	421	{
d00dd7dc	422	_bfd_bool_bfd_false_error,
c067354b	423	verilog_mkobject,
d00dd7dc AM	424	_bfd_bool_bfd_false_error,
d00dd7dc AM	425	_bfd_bool_bfd_false_error,
c067354b NC	426	},
c067354b NC	427	{ /* bfd_write_contents. */
d00dd7dc	428	_bfd_bool_bfd_false_error,
c067354b	429	verilog_write_object_contents,
d00dd7dc AM	430	_bfd_bool_bfd_false_error,
d00dd7dc AM	431	_bfd_bool_bfd_false_error,
c067354b NC	432	},
	433
	434	BFD_JUMP_TABLE_GENERIC (_bfd_generic),
	435	BFD_JUMP_TABLE_COPY (_bfd_generic),
	436	BFD_JUMP_TABLE_CORE (_bfd_nocore),
	437	BFD_JUMP_TABLE_ARCHIVE (_bfd_noarchive),
	438	BFD_JUMP_TABLE_SYMBOLS (_bfd_nosymbols),
	439	BFD_JUMP_TABLE_RELOCS (_bfd_norelocs),
	440	BFD_JUMP_TABLE_WRITE (verilog),
	441	BFD_JUMP_TABLE_LINK (_bfd_nolink),
	442	BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
	443
	444	NULL,
	445
	446	NULL
	447	};