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Commit | Line | Data |
---|---|---|
252b5132 | 1 | -*- text -*- |
299b91cd | 2 | |
83b972fc NC |
3 | * Assembler macros can now use the syntax \+ to access the number of times a |
4 | given macro has been executed. This is similar to the already existing \@ | |
5 | syntax, except that the count is maintained on a per-macro basis. | |
6 | ||
dd74a603 CL |
7 | * Support the NF feature in Intel APX. |
8 | ||
8963a60d CL |
9 | * Remove KEYLOCKER and SHA promotions from EVEX MAP4. |
10 | ||
226749d5 JB |
11 | * References to FB and dollar labels, when supported, are no longer permitted |
12 | in a radix other than 10. (Note that definitions of such labels were already | |
13 | thus restricted, except that leading zeroes were permitted.) | |
14 | ||
8e60ff82 NC |
15 | * Remove support for RISC-V privileged spec 1.9.1, but linker can still |
16 | recognize it in case of linking old objects. | |
17 | ||
9132c815 J |
18 | * Add support for RISC-V Zcmp extension with version 1.0. |
19 | ||
aacf780b JR |
20 | * The base register operand in D(X,B) and D(L,B) may be explicitly omitted |
21 | in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0) | |
22 | D(X,%r0), D(L,0), and D(L,%r0). | |
23 | ||
dfa4ac97 JR |
24 | * Warn when a register name type does not match the operand type on s390. |
25 | Add support for s390-specific option "warn-regtype-mismatch=[strict|relaxed| | |
26 | no]" to override the register name type check behavior. The default | |
27 | is "relaxed", which allows floating-point and vector register names to be | |
28 | used interchangeably. | |
29 | ||
b47cef7c CB |
30 | * Add support for 'armv9.5-a' for -march in Arm GAS. |
31 | ||
299b91cd NC |
32 | Changes in 2.42: |
33 | ||
249e5420 NC |
34 | * Add support for AMD znver5 processor. |
35 | ||
4201dd33 AC |
36 | * Add support for the AArch64 Reliability, Availability and Serviceability |
37 | extension v2 (RASv2). | |
b3b647dc | 38 | |
4201dd33 | 39 | * Add support for the AArch64 128-bit Atomic Instructions (LSE128). |
5e2f0c9a | 40 | |
4201dd33 | 41 | * Add support for the AArch64 Guarded Control Stack (GCS). |
27b33966 | 42 | |
4201dd33 | 43 | * Add support for the AArch64 Check Feature Status Extension (CHK). |
311276f1 | 44 | |
4201dd33 AC |
45 | * Add support for the AArch64 Enhanced Speculation Restriction Instructions |
46 | (SPECRES2). | |
f3f6c0df | 47 | |
4201dd33 | 48 | * Add support for the AArch64 Load-Acquire RCpc instructions version 3 (LRCPC3). |
f985c251 | 49 | |
4201dd33 AC |
50 | * Add support for the AArch64 Translation Hardening Extension (THE). |
51 | ||
52 | * Add support for the AArch64 Instruction Trace Extension (ITE). | |
53 | ||
54 | * Add support for the AArch64 Translation Hardening Extension (THE). | |
55 | ||
56 | * Add support for the AArch64 128-bit page table descriptors (D128). | |
57 | ||
58 | * Add support for the AArch64 XS memory attribute (XS). | |
59 | ||
60 | * Add support for '+fcma', '+jscvt', '+frintts', '+flagm2', '+rcpc2' and | |
61 | '+wfxt' flags to enable existing AArch64 instructions. | |
6c0ecdba | 62 | |
8cee11ca | 63 | * Add support for 'armv8.9-a' and 'armv9.4-a' for -march in AArch64 GAS. |
64 | ||
4201dd33 AC |
65 | * Add support for 'armv8.9-a' and 'armv9.4-a' for -march in Arm GAS. |
66 | ||
67 | * Add support for Cortex-A520, Cortex-A720, Cortex-X3 and Cortex-X4 for | |
68 | AArch64. | |
69 | ||
70 | * Experimental support in GAS to synthesize CFI for ABI-conformant, | |
71 | hand-written asm using the new command line option --scfi=experimental on | |
72 | x86-64. Only System V AMD64 ABI is supported. | |
73 | ||
74 | * Initial support for Intel APX: 32 GPRs, NDD, PUSH2/POP2 and PUSHP/POPP. | |
75 | ||
8170af78 HL |
76 | * Add support for Intel USER_MSR instructions. |
77 | ||
4fc85f37 JB |
78 | * Add support for Intel AVX10.1. |
79 | ||
b5c37946 SJ |
80 | * Add support for Intel PBNDKB instructions. |
81 | ||
82 | * Add support for Intel SM4 instructions. | |
83 | ||
84 | * Add support for Intel SM3 instructions. | |
85 | ||
86 | * Add support for Intel SHA512 instructions. | |
87 | ||
88 | * Add support for Intel AVX-VNNI-INT16 instructions. | |
89 | ||
4201dd33 AC |
90 | * On RISC-V macro instructions expanding to AUIPC and a load, store, or branch |
91 | no longer accept x0 as an intermediate and/or destination register. | |
0515a7b6 | 92 | |
8321007a | 93 | * Add support for RISC-V T-Head extensions (XTheadVector, XTheadZvlsseg |
86fbfedd JM |
94 | and XTheadZvamo) from version 2.3.0 of the T-Head ISA manual. |
95 | ||
8321007a NC |
96 | * Add support for RISC-V CORE-V extensions (XCVmac, XCValu) with version 1.0. |
97 | ||
248bf6de NC |
98 | * Add support for RISC-V SiFive VCIX extension (XSfVcp) with version 1.0. |
99 | ||
927d9ccf JM |
100 | * The BPF assembler now uses semi-colon (;) to separate statements, and |
101 | therefore they cannot longer be used to begin line comments. This matches the | |
102 | behavior of the clang/LLVM BPF assembler. | |
103 | ||
dd2947e7 JM |
104 | * The BPF assembler now allows using both hash (#) and double slash (//) to |
105 | begin line comments. | |
106 | ||
36176c5d XR |
107 | * Add support for LoongArch v1.10 new instructions: estimated reciprocal |
108 | instructions, sub-word atomic instructions, atomic CAS instructions, | |
109 | 16-byte store-conditional instruction, load-linked instructions with | |
110 | acquire semantics, and store-conditional instructions with release | |
111 | semantics. | |
112 | ||
113 | * The %call36 relocation operator, along with the pseudo-instructions | |
114 | call36 and tail36, are now usable with the LoongArch "medium" code | |
115 | model, allowing text sections up to 128 GiB. | |
116 | ||
117 | * TLS descriptors (TLSDESC) are now supported on LoongArch. This includes | |
118 | the following new relocation operators: %desc_pc_hi20, %desc_pc_lo12, | |
119 | %desc_ld, and %desc_call, and the la.tls.desc pseudo-instruction. | |
120 | ||
121 | * TLS LE relaxation is now supported on LoongArch. New relocation | |
122 | operators %le_hi20_r, %le_lo12r, and %le_add_r are now available. | |
123 | ||
124 | * Add support for LoongArch branch relaxation: a conditional branch with | |
125 | destination out of its immediate operand range, but still within | |
126 | a "b"'s range, is now assembled as an inverted branch and a "b". This | |
127 | works around the unreliable branch offset estimation of the compiler | |
128 | when .align directive is encoded into a long NOP sequence with an | |
129 | R_LARCH_RELAX by the assembler. | |
130 | ||
131 | * Symbol or label names in LoongArch assembly can now be spelled with | |
132 | double-quotes. | |
133 | ||
d501d384 NC |
134 | Changes in 2.41: |
135 | ||
6e712424 PI |
136 | * Add support for the KVX instruction set. |
137 | ||
c88ed92f ZJ |
138 | * Add support for Intel FRED instructions. |
139 | ||
140 | * Add support for Intel LKGS instructions. | |
141 | ||
d100d8c1 HJ |
142 | * Add support for Intel AMX-COMPLEX instructions. |
143 | ||
60336e19 RS |
144 | * Add SME2 support to the AArch64 port. |
145 | ||
695a8c34 JB |
146 | * A new .insn directive is recognized by x86 gas. |
147 | ||
3863e5e4 WX |
148 | * Add support for LoongArch LSX instructions. |
149 | ||
150 | * Add support for LoongArch LASX instructions. | |
151 | ||
152 | * Add support for LoongArch LVZ instructions. | |
153 | ||
154 | * Add support for LoongArch LBT instructions. | |
155 | ||
156 | * Initial LoongArch support for linker relaxation has been added. | |
157 | ||
158 | * Deprecate the LoongArch register aliases $v0, $v1, $x, $fv0 and $fv1. | |
159 | ||
a72b0718 NC |
160 | Changes in 2.40: |
161 | ||
b06311ad KL |
162 | * Add support for Intel RAO-INT instructions. |
163 | ||
01d8ce74 | 164 | * Add support for Intel AVX-NE-CONVERT instructions. |
165 | ||
2188d6ea HL |
166 | * Add support for Intel MSRLIST instructions. |
167 | ||
941f0833 HL |
168 | * Add support for Intel WRMSRNS instructions. |
169 | ||
a93e3234 HJ |
170 | * Add support for Intel CMPccXADD instructions. |
171 | ||
23ae61ad CL |
172 | * Add support for Intel AVX-VNNI-INT8 instructions. |
173 | ||
4321af3e HW |
174 | * Add support for Intel AVX-IFMA instructions. |
175 | ||
ef07be45 CL |
176 | * Add support for Intel PREFETCHI instructions. |
177 | ||
68830fba CL |
178 | * Add support for Intel AMX-FP16 instructions. |
179 | ||
2cac01e3 FS |
180 | * gas now supports --compress-debug-sections=zstd to compress |
181 | debug sections with zstd. | |
d846c35e | 182 | |
b0c295e1 ML |
183 | * Add --enable-default-compressed-debug-sections-algorithm={zlib,zstd} |
184 | that selects the default compression algorithm | |
185 | for --enable-compressed-debug-sections. | |
2cac01e3 | 186 | |
27e60212 | 187 | * Add support for various T-Head extensions (XTheadBa, XTheadBb, XTheadBs, |
01804a09 | 188 | XTheadCmo, XTheadCondMov, XTheadFMemIdx, XTheadFmv, XTheadInt, XTheadMemIdx, |
4a3bc79b CM |
189 | XTheadMemPair, XTheadMac, and XTheadSync) from version 2.0 of the T-Head |
190 | ISA manual, which are implemented in the Allwinner D1. | |
27e60212 | 191 | |
f262d2df PD |
192 | * Add support for the RISC-V Zawrs extension, version 1.0-rc4. |
193 | ||
cafdb713 SP |
194 | * Add support for Cortex-X1C for Arm. |
195 | ||
b2cb03d5 IB |
196 | * New command line option --gsframe to generate SFrame unwind information |
197 | on x86_64 and aarch64 targets. | |
198 | ||
0bd09323 NC |
199 | Changes in 2.39: |
200 | ||
c085ab00 JB |
201 | * Remove (rudimentary) support for the x86-64 sub-architectures Intel L1OM and |
202 | Intel K1OM. | |
203 | ||
5a3ca6e3 PD |
204 | * Add support for the RISC-V Zicbop, Zicbom, and Zicboz extensions, version |
205 | 1.0-fd39d01. | |
206 | ||
207 | * Add support for the RISC-V Zfh extension, version 1.0. | |
208 | ||
209 | * Add support for the Zhinx extension, version 1.0.0-rc. | |
210 | ||
211 | * Add support for the RISC-V H extension. | |
212 | ||
213 | * Add support for the RISC-V Zfhmin extension, version 1.0, and Zhinxmin | |
214 | extension, version 1.0.0-rc. | |
215 | ||
a74e1cb3 NC |
216 | Changes in 2.38: |
217 | ||
36cb9e7e RS |
218 | * Add support for AArch64 system registers that were missing in previous |
219 | releases. | |
220 | ||
4462d7c4 | 221 | * Add support for the LoongArch instruction set. |
222 | ||
c8480b58 L |
223 | * Add a command-line option, -muse-unaligned-vector-move, for x86 target |
224 | to encode aligned vector move as unaligned vector move. | |
225 | ||
80cfde76 PW |
226 | * Add support for Cortex-R52+ for Arm. |
227 | ||
50aaf5e6 | 228 | * Add support for Cortex-A510, Cortex-A710, Cortex-X2 for AArch64. |
98ab23ab | 229 | |
14f45859 PW |
230 | * Add support for Cortex-A710 for Arm. |
231 | ||
57f02370 PW |
232 | * Add support for Scalable Matrix Extension (SME) for AArch64. |
233 | ||
578c64a4 NC |
234 | * The --multibyte-handling=[allow|warn|warn-sym-only] option tells the |
235 | assembler what to when it encoutners multibyte characters in the input. The | |
236 | default is to allow them. Setting the option to "warn" will generate a | |
237 | warning message whenever any multibyte character is encountered. Using the | |
238 | option to "warn-sym-only" will make the assembler generate a warning whenever a | |
239 | symbol is defined containing multibyte characters. (References to undefined | |
240 | symbols will not generate warnings). | |
241 | ||
ff01bb6c L |
242 | * Outputs of .ds.x directive and .tfloat directive with hex input from |
243 | x86 assembler have been reduced from 12 bytes to 10 bytes to match the | |
244 | output of .tfloat directive. | |
245 | ||
35180222 RS |
246 | * Add support for 'armv8.8-a', 'armv9-a', 'armv9.1-a', 'armv9.2-a' and |
247 | 'armv9.3-a' for -march in AArch64 GAS. | |
d5007f02 | 248 | |
a2b1ea81 RS |
249 | * Add support for 'armv8.7-a', 'armv8.8-a', 'armv9-a', 'armv9.1-a', |
250 | 'armv9.2-a' and 'armv9.3-a' for -march in Arm GAS. | |
3197e593 | 251 | |
0cc78721 CL |
252 | * Add support for Intel AVX512_FP16 instructions. |
253 | ||
6b60a1ec PD |
254 | * Add support for the RISC-V scalar crypto extension, version 1.0.0. |
255 | ||
256 | * Add support for the RISC-V vector extension, version 1.0. | |
257 | ||
258 | * Add support for the Z{f,d,q}inx extensions, version 1.0.0-rc. | |
259 | ||
260 | * Add support for the RISC-V svinval extension, version 1.0. | |
261 | ||
262 | * Add support for the RISC-V hypervisor extension, as defined by Privileged | |
263 | Specification 1.12. | |
264 | ||
51419248 NC |
265 | Changes in 2.37: |
266 | ||
933feaf3 AM |
267 | * arm-symbianelf support removed. |
268 | ||
02202574 PW |
269 | * Add support for Realm Management Extension (RME) for AArch64. |
270 | ||
157a088c PD |
271 | * Add support for the Zba, Zbb, Zbc, and Zbs subsets of the RISC-V |
272 | bit manipulation extension, version 0.93. | |
273 | ||
055bc77a NC |
274 | Changes in 2.36: |
275 | ||
58bf9b6a L |
276 | * Add support for Intel AVX VNNI instructions. |
277 | ||
c1fa250a LC |
278 | * Add support for Intel HRESET instruction. |
279 | ||
f64c42a9 LC |
280 | * Add support for Intel UINTR instructions. |
281 | ||
6d96a594 C |
282 | * Support non-absolute segment values for i386 lcall and ljmp. |
283 | ||
b71702f1 NC |
284 | * When setting the link order attribute of ELF sections, it is now possible to |
285 | use a numeric section index instead of symbol name. | |
42c36b73 | 286 | |
a3a02fe8 PW |
287 | * Add support for Cortex-A78, Cortex-A78AE, Cortex-A78C and Cortex-X1 for |
288 | AArch64 and ARM. | |
b71702f1 | 289 | Add support for Cortex-R82, Neoverse V1, and Neoverse N2 for ARM. |
77718e5b | 290 | |
b71702f1 | 291 | * Add support for ETMv4 (Embedded Trace Macrocell), ETE (Embedded Trace |
82c70b08 KT |
292 | Extension), TRBE (Trace Buffer Extension)and BRBE (Branch Record Buffer |
293 | Extension) system registers for AArch64. | |
c81946ef | 294 | |
8926e54e | 295 | * Add support for Armv8-R and Armv8.7-A AArch64. |
c81946ef | 296 | |
a984d94a | 297 | * Add support for DSB memory nXS barrier, WFET and WFIT instruction for Armv8.7 |
82503ca7 | 298 | AArch64. |
fd195909 | 299 | |
e64441b1 | 300 | * Add support for +flagm feature for -march in Armv8.4 AArch64. |
dd4a72c8 | 301 | |
fd65497d PW |
302 | * Add support for +ls64 feature for -march in Armv8.7 AArch64. Add atomic |
303 | 64-byte load/store instructions for this feature. | |
304 | ||
3f4ff088 PW |
305 | * Add support for +pauth (Pointer Authentication) feature for -march in |
306 | AArch64. | |
307 | ||
81d54bb7 | 308 | * Add support for Intel TDX instructions. |
96a84ea3 | 309 | |
c4694f17 TG |
310 | * Add support for Intel Key Locker instructions. |
311 | ||
b1766e7c NC |
312 | * Added a .nop directive to generate a single no-op instruction in a target |
313 | neutral manner. This instruction does have an effect on DWARF line number | |
314 | generation, if that is active. | |
315 | ||
a0522545 ML |
316 | * Removed --reduce-memory-overheads and --hash-size as gas now |
317 | uses hash tables that can be expand and shrink automatically. | |
318 | ||
789198ca L |
319 | * Add {disp16} pseudo prefix to x86 assembler. |
320 | ||
260cd341 LC |
321 | * Add support for Intel AMX instructions. |
322 | ||
939b95c7 L |
323 | * Configure with --enable-x86-used-note by default for Linux/x86. |
324 | ||
99fabbc9 JL |
325 | * Add support for the SHF_GNU_RETAIN flag, which can be applied to |
326 | sections using the 'R' flag in the .section directive. | |
327 | SHF_GNU_RETAIN specifies that the section should not be garbage | |
328 | collected by the linker. It requires the GNU or FreeBSD ELF OSABIs. | |
329 | ||
c17cf68c PD |
330 | * Add support for the RISC-V Zihintpause extension. |
331 | ||
b115b9fd NC |
332 | Changes in 2.35: |
333 | ||
bbd19b19 L |
334 | * X86 NaCl target support is removed. |
335 | ||
6914be53 L |
336 | * Extend .symver directive to update visibility of the original symbol |
337 | and assign one original symbol to different versioned symbols. | |
338 | ||
6e0e8b45 L |
339 | * Add support for Intel SERIALIZE and TSXLDTRK instructions. |
340 | ||
9e8f1c90 L |
341 | * Add -mlfence-after-load=, -mlfence-before-indirect-branch= and |
342 | -mlfence-before-ret= options to x86 assembler to help mitigate | |
343 | CVE-2020-0551. | |
344 | ||
5496f3c6 NC |
345 | * Add --gdwarf-5 option to the assembler to generate DWARF 5 debug output |
346 | (if such output is being generated). Added the ability to generate | |
347 | version 5 .debug_line sections. | |
348 | ||
251dae91 TC |
349 | * Add -mbig-obj support to i386 MingW targets. |
350 | ||
4362996c PD |
351 | * Add support for the -mriscv-isa-version argument, to select the version of |
352 | the RISC-V ISA specification used when assembling. | |
353 | ||
354 | * Remove support for the RISC-V privileged specification, version 1.9. | |
355 | ||
ae774686 NC |
356 | Changes in 2.34: |
357 | ||
5eb617a7 L |
358 | * Add -malign-branch-boundary=NUM, -malign-branch=TYPE[+TYPE...], |
359 | -malign-branch-prefix-size=NUM and -mbranches-within-32B-boundaries | |
360 | options to x86 assembler to align branches within a fixed boundary | |
361 | with segment prefixes or NOPs. | |
362 | ||
6655dba2 SB |
363 | * Add support for Zilog eZ80 and Zilog Z180 CPUs. |
364 | ||
365 | * Add support for z80-elf target. | |
366 | ||
367 | * Add support for relocation of each byte or word of multibyte value to Z80 | |
368 | targets (just use right shift to 0, 8, 16, or 24 bits or AND operation | |
369 | with 0xff/0xffff mask): ld a, label >> 16 \ ld hl, label & 0xffff | |
370 | ||
371 | * Add SDCC support for Z80 targets. | |
372 | ||
60391a25 PB |
373 | Changes in 2.33: |
374 | ||
7738ddb4 MM |
375 | * Add support for the Arm Scalable Vector Extension version 2 (SVE2) |
376 | instructions. | |
377 | ||
378 | * Add support for the Arm Transactional Memory Extension (TME) | |
379 | instructions. | |
380 | ||
514bbb0f AV |
381 | * Add support for the Armv8.1-M Mainline and M-profile Vector Extension (MVE) |
382 | instructions. | |
383 | ||
b20d3859 BW |
384 | * For MIPS, Add -m[no-]fix-loongson3-llsc option to fix (or not) Loongson3 |
385 | LLSC Errata. Add a --enable-mips-fix-loongson3-llsc=[yes|no] configure | |
386 | time option to set the default behavior. Set the default if the configure | |
387 | option is not used to "no". | |
6f2117ba | 388 | |
546053ac DZ |
389 | * Add support for the Arm Cortex-A76AE, Cortex-A77 and Cortex-M35P |
390 | processors. | |
391 | ||
392 | * Add support for the AArch64 Cortex-A34, Cortex-A65, Cortex-A65AE, | |
393 | Cortex-A76AE, and Cortex-A77 processors. | |
394 | ||
b20d3859 BW |
395 | * Add .float16 directive for both Arm and AArch64 to allow encoding of 16-bit |
396 | floating point literals. Add .float16_format directive and | |
397 | -mfp16-format=[ieee|alternative] option for Arm to control the format of the | |
398 | encoding. | |
399 | ||
66f8b2cb AB |
400 | * Add --gdwarf-cie-version command line flag. This allows control over which |
401 | version of DWARF CIE the assembler creates. | |
402 | ||
f974f26c NC |
403 | Changes in 2.32: |
404 | ||
03751133 L |
405 | * Add -mvexwig=[0|1] option to x86 assembler to control encoding of |
406 | VEX.W-ignored (WIG) VEX instructions. | |
407 | ||
b4a3a7b4 L |
408 | * Add -mx86-used-note=[yes|no] option to generate (or not) x86 GNU property |
409 | notes. Add a --enable-x86-used-note configure time option to set the | |
410 | default behavior. Set the default if the configure option is not used | |
411 | to "no". | |
412 | ||
a693765e CX |
413 | * Add support for the MIPS Loongson EXTensions R2 (EXT2) instructions. |
414 | ||
bdc6c06e CX |
415 | * Add support for the MIPS Loongson EXTensions (EXT) instructions. |
416 | ||
716c08de CX |
417 | * Add support for the MIPS Loongson Content Address Memory (CAM) ASE. |
418 | ||
b8891f8d AJ |
419 | * Add support for the C-SKY processor series. |
420 | ||
8095d2f7 CX |
421 | * Add support for the MIPS Loongson MultiMedia extensions Instructions (MMI) |
422 | ASE. | |
423 | ||
719d8288 NC |
424 | Changes in 2.31: |
425 | ||
fc6141f0 NC |
426 | * The ADR and ADRL pseudo-instructions supported by the ARM assembler |
427 | now only set the bottom bit of the address of thumb function symbols | |
428 | if the -mthumb-interwork command line option is active. | |
429 | ||
6f20c942 FS |
430 | * Add support for the MIPS Global INValidate (GINV) ASE. |
431 | ||
730c3174 SE |
432 | * Add support for the MIPS Cyclic Redudancy Check (CRC) ASE. |
433 | ||
7b4ae824 JD |
434 | * Add support for the Freescale S12Z architecture. |
435 | ||
0df8ad28 NC |
436 | * Add --generate-missing-build-notes=[yes|no] option to create (or not) GNU |
437 | Build Attribute notes if none are present in the input sources. Add a | |
438 | --enable-generate-build-notes=[yes|no] configure time option to set the | |
439 | default behaviour. Set the default if the configure option is not used | |
440 | to "no". | |
441 | ||
bd5dea88 L |
442 | * Remove -mold-gcc command-line option for x86 targets. |
443 | ||
b6f8c7c4 L |
444 | * Add -O[2|s] command-line options to x86 assembler to enable alternate |
445 | shorter instruction encoding. | |
446 | ||
8f065d3b | 447 | * Add support for .nops directive. It is currently supported only for |
62a02d25 L |
448 | x86 targets. |
449 | ||
64411043 PD |
450 | * Add support for the .insn directive on RISC-V targets. |
451 | ||
9176ac5b NC |
452 | Changes in 2.30: |
453 | ||
ba8826a8 AO |
454 | * Add support for loaction views in DWARF debug line information. |
455 | ||
55a09eb6 TG |
456 | Changes in 2.29: |
457 | ||
a91e1603 L |
458 | * Add support for ELF SHF_GNU_MBIND. |
459 | ||
f96bd6c2 PC |
460 | * Add support for the WebAssembly file format and wasm32 ELF conversion. |
461 | ||
7e0de605 | 462 | * PowerPC gas now checks that the correct register class is used in |
ece5dcc1 AM |
463 | instructions. For instance, "addi %f4,%cr3,%r31" warns three times |
464 | that the registers are invalid. | |
7e0de605 | 465 | |
93f11b16 DD |
466 | * Add support for the Texas Instruments PRU processor. |
467 | ||
0cda1e19 TP |
468 | * Support for the ARMv8-R architecture and Cortex-R52 processor has been |
469 | added to the ARM port. | |
ced40572 | 470 | |
9703a4ef TG |
471 | Changes in 2.28: |
472 | ||
e23eba97 NC |
473 | * Add support for the RISC-V architecture. |
474 | ||
b19ea8d2 | 475 | * Add support for the ARM Cortex-M23 and Cortex-M33 processors. |
ce1b0a45 | 476 | |
96a84ea3 TG |
477 | Changes in 2.27: |
478 | ||
4e3e1fdf L |
479 | * Default to --enable-compressed-debug-sections=gas for Linux/x86 targets. |
480 | ||
2edb36e7 NC |
481 | * Add --no-pad-sections to stop the assembler from padding the end of output |
482 | sections up to their alignment boundary. | |
483 | ||
15afaa63 TP |
484 | * Support for the ARMv8-M architecture has been added to the ARM port. Support |
485 | for the ARMv8-M Security and DSP Extensions has also been added to the ARM | |
486 | port. | |
487 | ||
f36e33da CZ |
488 | * ARC backend accepts .extInstruction, .extCondCode, .extAuxRegister, and |
489 | .extCoreRegister pseudo-ops that allow an user to define custom | |
490 | instructions, conditional codes, auxiliary and core registers. | |
491 | ||
b8871f35 L |
492 | * Add a configure option --enable-elf-stt-common to decide whether ELF |
493 | assembler should generate common symbols with the STT_COMMON type by | |
494 | default. Default to no. | |
495 | ||
a05a5b64 | 496 | * New command-line option --elf-stt-common= for ELF targets to control |
b8871f35 L |
497 | whether to generate common symbols with the STT_COMMON type. |
498 | ||
9fb71ee4 NC |
499 | * Add ability to set section flags and types via numeric values for ELF |
500 | based targets. | |
81c23f82 | 501 | |
0cb4071e L |
502 | * Add a configure option --enable-x86-relax-relocations to decide whether |
503 | x86 assembler should generate relax relocations by default. Default to | |
504 | yes, except for x86 Solaris targets older than Solaris 12. | |
505 | ||
a05a5b64 | 506 | * New command-line option -mrelax-relocations= for x86 target to control |
0cb4071e L |
507 | whether to generate relax relocations. |
508 | ||
a05a5b64 | 509 | * New command-line option -mfence-as-lock-add=yes for x86 target to encode |
9d3fc4e1 L |
510 | lfence, mfence and sfence as "lock addl $0x0, (%[re]sp)". |
511 | ||
4670103e CZ |
512 | * Add assembly-time relaxation option for ARC cpus. |
513 | ||
9004b6bd AB |
514 | * Add --with-cpu=TYPE configure option for ARC gas. This allows the default |
515 | cpu type to be adjusted at configure time. | |
516 | ||
7feec526 TG |
517 | Changes in 2.26: |
518 | ||
edeefb67 L |
519 | * Add a configure option --enable-compressed-debug-sections={all,gas} to |
520 | decide whether DWARF debug sections should be compressed by default. | |
e12fe555 | 521 | |
886a2506 NC |
522 | * Add support for the ARC EM/HS, and ARC600/700 architectures. Remove |
523 | assembler support for Argonaut RISC architectures. | |
524 | ||
d02603dc NC |
525 | * Symbol and label names can now be enclosed in double quotes (") which allows |
526 | them to contain characters that are not part of valid symbol names in high | |
527 | level languages. | |
528 | ||
f33026a9 MW |
529 | * Added the correctly spelled -march=armv6kz, for ARMv6KZ support. The |
530 | previous spelling, -march=armv6zk, is still accepted. | |
531 | ||
88f0ea34 MW |
532 | * Support for the ARMv8.1 architecture has been added to the Aarch64 port. |
533 | Support for the individual ARMv8.1 Adv.SIMD, LOR and PAN architecture | |
534 | extensions has also been added to the Aarch64 port. | |
535 | ||
a5932920 MW |
536 | * Support for the ARMv8.1 architecture has been added to the ARM port. Support |
537 | for the individual ARMv8.1 Adv.SIMD and PAN architecture extensions has also | |
538 | been added to the ARM port. | |
539 | ||
ea556d25 L |
540 | * Extend --compress-debug-sections option to support |
541 | --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF | |
542 | targets. | |
543 | ||
0d2b51ad L |
544 | * --compress-debug-sections is turned on for Linux/x86 by default. |
545 | ||
c50415e2 TG |
546 | Changes in 2.25: |
547 | ||
f36e8886 BS |
548 | * Add support for the AVR Tiny microcontrollers. |
549 | ||
73589c9d CS |
550 | * Replace support for openrisc and or32 with support for or1k. |
551 | ||
2e6976a8 | 552 | * Enhanced the ARM port to accept the assembler output from the CodeComposer |
a05a5b64 | 553 | Studio tool. Support is enabled via the new command-line option -mccs. |
2e6976a8 | 554 | |
35c08157 KLC |
555 | * Add support for the Andes NDS32. |
556 | ||
58ca03a2 TG |
557 | Changes in 2.24: |
558 | ||
13761a11 NC |
559 | * Add support for the Texas Instruments MSP430X processor. |
560 | ||
a05a5b64 | 561 | * Add -gdwarf-sections command-line option to enable per-code-section |
b40bf0a2 NC |
562 | generation of DWARF .debug_line sections. |
563 | ||
36591ba1 SL |
564 | * Add support for Altera Nios II. |
565 | ||
a3c62988 NC |
566 | * Add support for the Imagination Technologies Meta processor. |
567 | ||
5bf135a7 NC |
568 | * Add support for the v850e3v5. |
569 | ||
e8044f35 RS |
570 | * Remove assembler support for MIPS ECOFF targets. |
571 | ||
af18cb59 TG |
572 | Changes in 2.23: |
573 | ||
da2bb560 NC |
574 | * Add support for the 64-bit ARM architecture: AArch64. |
575 | ||
6927f982 NC |
576 | * Add support for S12X processor. |
577 | ||
b9c361e0 JL |
578 | * Add support for the VLE extension to the PowerPC architecture. |
579 | ||
f6c1a2d5 NC |
580 | * Add support for the Freescale XGATE architecture. |
581 | ||
fa94de6b RM |
582 | * Add support for .bundle_align_mode, .bundle_lock, and .bundle_unlock |
583 | directives. These are currently available only for x86 and ARM targets. | |
584 | ||
99c513f6 DD |
585 | * Add support for the Renesas RL78 architecture. |
586 | ||
cfb8c092 NC |
587 | * Add support for the Adapteva EPIPHANY architecture. |
588 | ||
fe13e45b | 589 | * For x86, allow 'rep bsf', 'rep bsr', and 'rep ret' syntax. |
29c048b6 | 590 | |
a7142d94 TG |
591 | Changes in 2.22: |
592 | ||
69f56ae1 | 593 | * Add support for the Tilera TILEPro and TILE-Gx architectures. |
44f45767 | 594 | |
90b3661c | 595 | Changes in 2.21: |
44f45767 | 596 | |
5fec8599 L |
597 | * Gas no longer requires doubling of ampersands in macros. |
598 | ||
40b36596 JM |
599 | * Add support for the TMS320C6000 (TI C6X) processor family. |
600 | ||
31907d5e DK |
601 | * GAS now understands an extended syntax in the .section directive flags |
602 | for COFF targets that allows the section's alignment to be specified. This | |
603 | feature has also been backported to the 2.20 release series, starting with | |
604 | 2.20.1. | |
605 | ||
c7927a3c NC |
606 | * Add support for the Renesas RX processor. |
607 | ||
a05a5b64 | 608 | * New command-line option, --compress-debug-sections, which requests |
700c4060 CC |
609 | compression of DWARF debug information sections in the relocatable output |
610 | file. Compressed debug sections are supported by readelf, objdump, and | |
611 | gold, but not currently by Gnu ld. | |
612 | ||
81c23f82 TG |
613 | Changes in 2.20: |
614 | ||
1cd986c5 NC |
615 | * Added support for v850e2 and v850e2v3. |
616 | ||
3e7a7d11 NC |
617 | * GNU/Linux targets now supports "gnu_unique_object" as a value in the .type |
618 | pseudo op. It marks the symbol as being globally unique in the entire | |
619 | process. | |
620 | ||
c921be7d NC |
621 | * ARM assembler now supports .inst[.nw] pseudo-ops to insert opcodes specified |
622 | in binary rather than text. | |
6e33da12 | 623 | |
c1711530 DK |
624 | * Add support for common symbol alignment to PE formats. |
625 | ||
92846e72 CC |
626 | * Add support for the new discriminator column in the DWARF line table, |
627 | with a discriminator operand for the .loc directive. | |
628 | ||
c3b7224a NC |
629 | * Add support for Sunplus score architecture. |
630 | ||
d8045f23 NC |
631 | * The .type pseudo-op now accepts a type of STT_GNU_IFUNC which can be used to |
632 | indicate that if the symbol is the target of a relocation, its value should | |
633 | not be use. Instead the function should be invoked and its result used as | |
634 | the value. | |
fa94de6b | 635 | |
84e94c90 NC |
636 | * Add support for Lattice Mico32 (lm32) architecture. |
637 | ||
fa94de6b | 638 | * Add support for Xilinx MicroBlaze architecture. |
caa03924 | 639 | |
6e33da12 TG |
640 | Changes in 2.19: |
641 | ||
4f6d9c90 DJ |
642 | * New pseudo op .cfi_val_encoded_addr, to record constant addresses in unwind |
643 | tables without runtime relocation. | |
644 | ||
a05a5b64 | 645 | * New command-line option, -h-tick-hex, for sh, m32c, and h8/300 targets, which |
6fd4f6cc DD |
646 | adds compatibility with H'00 style hex constants. |
647 | ||
a05a5b64 | 648 | * New command-line option, -msse-check=[none|error|warning], for x86 |
daf50ae7 L |
649 | targets. |
650 | ||
a05a5b64 | 651 | * New sub-option added to the assembler's -a command-line switch to |
83f10cb2 NC |
652 | generate a listing output. The 'g' sub-option will insert into the listing |
653 | various information about the assembly, such as assembler version, the | |
a05a5b64 | 654 | command-line options used, and a time stamp. |
83f10cb2 | 655 | |
a05a5b64 | 656 | * New command-line option -msse2avx for x86 target to encode SSE |
c0f3af97 L |
657 | instructions with VEX prefix. |
658 | ||
f1f8f695 | 659 | * Add Intel XSAVE, EPT, MOVBE, AES, PCLMUL, AVX/FMA support for x86 target. |
c0f3af97 | 660 | |
a05a5b64 | 661 | * New command-line options, -march=CPU[,+EXTENSION...], -mtune=CPU, |
ae40c993 L |
662 | -mmnemonic=[att|intel], -msyntax=[att|intel], -mindex-reg, |
663 | -mnaked-reg and -mold-gcc, for x86 targets. | |
664 | ||
38a57ae7 NC |
665 | * Support for generating wide character strings has been added via the new |
666 | pseudo ops: .string16, .string32 and .string64. | |
667 | ||
85f10a01 MM |
668 | * Support for SSE5 has been added to the i386 port. |
669 | ||
7c3d153f NC |
670 | Changes in 2.18: |
671 | ||
ec2655a6 NC |
672 | * The GAS sources are now released under the GPLv3. |
673 | ||
3d3d428f NC |
674 | * Support for the National Semiconductor CR16 target has been added. |
675 | ||
3f9ce309 AM |
676 | * Added gas .reloc pseudo. This is a low-level interface for creating |
677 | relocations. | |
678 | ||
99ad8390 NC |
679 | * Add support for x86_64 PE+ target. |
680 | ||
1c0d3aa6 | 681 | * Add support for Score target. |
83518699 | 682 | |
ec2655a6 NC |
683 | Changes in 2.17: |
684 | ||
d70c5fc7 NC |
685 | * Support for the Infineon XC16X has been added by KPIT Cummins Infosystems. |
686 | ||
08333dc4 NS |
687 | * Support for ms2 architecture has been added. |
688 | ||
b7b8fb1d NC |
689 | * Support for the Z80 processor family has been added. |
690 | ||
3e8a519c MM |
691 | * Add support for the "@<file>" syntax to the command line, so that extra |
692 | switches can be read from <file>. | |
693 | ||
a05a5b64 | 694 | * The SH target supports a new command-line switch --enable-reg-prefix which, |
37dedf66 NC |
695 | if enabled, will allow register names to be optionally prefixed with a $ |
696 | character. This allows register names to be distinguished from label names. | |
fa94de6b | 697 | |
6eaeac8a JB |
698 | * Macros with a variable number of arguments are now supported. See the |
699 | documentation for how this works. | |
700 | ||
4bdd3565 NC |
701 | * Added --reduce-memory-overheads switch to reduce the size of the hash |
702 | tables used, at the expense of longer assembly times, and | |
703 | --hash-size=<NUMBER> to set the size of the hash tables used by gas. | |
704 | ||
5e75c3ab JB |
705 | * Macro names and macro parameter names can now be any identifier that would |
706 | also be legal as a symbol elsewhere. For macro parameter names, this is | |
707 | known to cause problems in certain sources when the respective target uses | |
708 | characters inconsistently, and thus macro parameter references may no longer | |
709 | be recognized as such (see the documentation for details). | |
fa94de6b | 710 | |
d2c5f73e NC |
711 | * Support the .f_floating, .d_floating, .g_floating and .h_floating directives |
712 | for the VAX target in order to be more compatible with the VAX MACRO | |
713 | assembler. | |
714 | ||
a05a5b64 | 715 | * New command-line option -mtune=[itanium1|itanium2] for IA64 targets. |
8c2fda1d | 716 | |
957d91c1 NC |
717 | Changes in 2.16: |
718 | ||
fffeaa5f JB |
719 | * Redefinition of macros now results in an error. |
720 | ||
a05a5b64 | 721 | * New command-line option -mhint.b=[ok|warning|error] for IA64 targets. |
91d777ee | 722 | |
a05a5b64 | 723 | * New command-line option -munwind-check=[warning|error] for IA64 |
970d6792 L |
724 | targets. |
725 | ||
f1dab70d JB |
726 | * The IA64 port now uses automatic dependency violation removal as its default |
727 | mode. | |
728 | ||
7499d566 NC |
729 | * Port to MAXQ processor contributed by HCL Tech. |
730 | ||
7ed4c4c5 NC |
731 | * Added support for generating unwind tables for ARM ELF targets. |
732 | ||
a05a5b64 | 733 | * Add a -g command-line option to generate debug information in the target's |
329e276d NC |
734 | preferred debug format. |
735 | ||
1fe1f39c NC |
736 | * Support for the crx-elf target added. |
737 | ||
1a320fbb | 738 | * Support for the sh-symbianelf target added. |
1fe1f39c | 739 | |
0503b355 BF |
740 | * Added a pseudo-op (.secrel32) to generate 32 bit section relative relocations |
741 | on pe[i]-i386; required for this target's DWARF 2 support. | |
742 | ||
6b6e92f4 NC |
743 | * Support for Motorola MCF521x/5249/547x/548x added. |
744 | ||
fd99574b NC |
745 | * Support for ColdFire EMAC instructions added and Motorola syntax for MAC/EMAC |
746 | instrucitons. | |
747 | ||
a05a5b64 | 748 | * New command-line option -mno-shared for MIPS ELF targets. |
aa6975fb | 749 | |
a05a5b64 | 750 | * New command-line option --alternate and pseudo-ops .altmacro and .noaltmacro |
caa32fe5 NC |
751 | added to enter (and leave) alternate macro syntax mode. |
752 | ||
0477af35 NC |
753 | Changes in 2.15: |
754 | ||
7a7f4e42 CD |
755 | * The MIPS -membedded-pic option (Embedded-PIC code generation) is |
756 | deprecated and will be removed in a future release. | |
757 | ||
6edf0760 NC |
758 | * Added PIC m32r Linux (ELF) and support to M32R assembler. |
759 | ||
09d92015 MM |
760 | * Added support for ARM V6. |
761 | ||
88da98f3 MS |
762 | * Added support for sh4a and variants. |
763 | ||
eb764db8 NC |
764 | * Support for Renesas M32R2 added. |
765 | ||
88da98f3 MS |
766 | * Limited support for Mapping Symbols as specified in the ARM ELF |
767 | specification has been added to the arm assembler. | |
ed769ec1 | 768 | |
0bbf2aa4 NC |
769 | * On ARM architectures, added a new gas directive ".unreq" that undoes |
770 | definitions created by ".req". | |
771 | ||
3e602632 NC |
772 | * Support for Motorola ColdFire MCF528x added. |
773 | ||
05da4302 NC |
774 | * Added --gstabs+ switch to enable the generation of STABS debug format |
775 | information with GNU extensions. | |
fa94de6b | 776 | |
6a265366 CD |
777 | * Added support for MIPS64 Release 2. |
778 | ||
8ad30312 NC |
779 | * Added support for v850e1. |
780 | ||
12b55ccc L |
781 | * Added -n switch for x86 assembler. By default, x86 GAS replaces |
782 | multiple nop instructions used for alignment within code sections | |
783 | with multi-byte nop instructions such as leal 0(%esi,1),%esi. This | |
784 | switch disables the optimization. | |
785 | ||
78849248 ILT |
786 | * Removed -n option from MIPS assembler. It was not useful, and confused the |
787 | existing -non_shared option. | |
788 | ||
43c58ae6 CD |
789 | Changes in 2.14: |
790 | ||
69be0a2b CD |
791 | * Added support for MIPS32 Release 2. |
792 | ||
e8fd7476 NC |
793 | * Added support for Xtensa architecture. |
794 | ||
e16bb312 NC |
795 | * Support for Intel's iWMMXt processor (an ARM variant) added. |
796 | ||
cce4814f NC |
797 | * An assembler test generator has been contributed and an example file that |
798 | uses it (gas/testsuite/gas/all/test-gen.c and test-exmaple.c). | |
fa94de6b | 799 | |
5177500f NC |
800 | * Support for SH2E added. |
801 | ||
fea17916 NC |
802 | * GASP has now been removed. |
803 | ||
004d9caf NC |
804 | * Support for Texas Instruments TMS320C4x and TMS320C3x series of |
805 | DSP's contributed by Michael Hayes and Svein E. Seldal. | |
fa94de6b | 806 | |
a40cbfa3 NC |
807 | * Support for the Ubicom IP2xxx microcontroller added. |
808 | ||
2cbb2eef NC |
809 | Changes in 2.13: |
810 | ||
a40cbfa3 NC |
811 | * Support for the Fujitsu FRV architecture added by Red Hat. Models for FR400 |
812 | and FR500 included. | |
0ebb9a87 | 813 | |
a40cbfa3 | 814 | * Support for DLX processor added. |
52216602 | 815 | |
a40cbfa3 NC |
816 | * GASP has now been deprecated and will be removed in a future release. Use |
817 | the macro facilities in GAS instead. | |
3f965e60 | 818 | |
a40cbfa3 NC |
819 | * GASP now correctly parses floating point numbers. Unless the base is |
820 | explicitly specified, they are interpreted as decimal numbers regardless of | |
821 | the currently specified base. | |
1ac57253 | 822 | |
9a66911f NC |
823 | Changes in 2.12: |
824 | ||
a40cbfa3 | 825 | * Support for Don Knuth's MMIX, by Hans-Peter Nilsson. |
49fda6c8 | 826 | |
a40cbfa3 | 827 | * Support for the OpenRISC 32-bit embedded processor by OpenCores. |
3b16e843 | 828 | |
fa94de6b RM |
829 | * The ARM assembler now accepts -march=..., -mcpu=... and -mfpu=... for |
830 | specifying the target instruction set. The old method of specifying the | |
a40cbfa3 NC |
831 | target processor has been deprecated, but is still accepted for |
832 | compatibility. | |
03b1477f | 833 | |
a40cbfa3 NC |
834 | * Support for the VFP floating-point instruction set has been added to |
835 | the ARM assembler. | |
252b5132 | 836 | |
a40cbfa3 NC |
837 | * New psuedo op: .incbin to include a set of binary data at a given point |
838 | in the assembly. Contributed by Anders Norlander. | |
7e005732 | 839 | |
a40cbfa3 NC |
840 | * The MIPS assembler now accepts -march/-mtune. -mcpu has been deprecated |
841 | but still works for compatability. | |
ec68c924 | 842 | |
fa94de6b | 843 | * The MIPS assembler no longer issues a warning by default when it |
a05a5b64 | 844 | generates a nop instruction from a macro. The new command-line option |
a40cbfa3 | 845 | -n will turn on the warning. |
63486801 | 846 | |
2dac7317 JW |
847 | Changes in 2.11: |
848 | ||
500800ca NC |
849 | * Support for PDP-11 and 2.11BSD a.out format, by Lars Brinkhoff. |
850 | ||
a40cbfa3 | 851 | * x86 gas now supports the full Pentium4 instruction set. |
a167610d | 852 | |
a40cbfa3 | 853 | * Support for AMD x86-64 architecture, by Jan Hubicka, SuSE Labs. |
c0d8940f | 854 | |
a40cbfa3 | 855 | * Support for Motorola 68HC11 and 68HC12. |
df86943d | 856 | |
a40cbfa3 | 857 | * Support for Texas Instruments TMS320C54x (tic54x). |
39bec121 | 858 | |
a40cbfa3 | 859 | * Support for IA-64. |
2dac7317 | 860 | |
a40cbfa3 | 861 | * Support for i860, by Jason Eckhardt. |
22b36938 | 862 | |
a40cbfa3 | 863 | * Support for CRIS (Axis Communications ETRAX series). |
5bcac8a4 | 864 | |
a40cbfa3 | 865 | * x86 gas has a new .arch pseudo op to specify the target CPU architecture. |
a38cf1db | 866 | |
a05a5b64 | 867 | * x86 gas -q command-line option quietens warnings about register size changes |
a40cbfa3 NC |
868 | due to suffix, indirect jmp/call without `*', stand-alone prefixes, and |
869 | translating various deprecated floating point instructions. | |
a38cf1db | 870 | |
252b5132 RH |
871 | Changes in 2.10: |
872 | ||
a40cbfa3 NC |
873 | * Support for the ARM msr instruction was changed to only allow an immediate |
874 | operand when altering the flags field. | |
d14442f4 | 875 | |
a40cbfa3 | 876 | * Support for ATMEL AVR. |
adde6300 | 877 | |
a40cbfa3 | 878 | * Support for IBM 370 ELF. Somewhat experimental. |
b5ebe70e | 879 | |
a40cbfa3 | 880 | * Support for numbers with suffixes. |
3fd9f047 | 881 | |
a40cbfa3 | 882 | * Added support for breaking to the end of repeat loops. |
6a6987a9 | 883 | |
a40cbfa3 | 884 | * Added support for parallel instruction syntax (DOUBLEBAR_PARALLEL). |
6a6987a9 | 885 | |
a40cbfa3 | 886 | * New .elseif pseudo-op added. |
3fd9f047 | 887 | |
a40cbfa3 | 888 | * New --fatal-warnings option. |
1f776aa5 | 889 | |
a40cbfa3 | 890 | * picoJava architecture support added. |
252b5132 | 891 | |
a40cbfa3 | 892 | * Motorola MCore 210 processor support added. |
041dd5a9 | 893 | |
fa94de6b | 894 | * A new pseudo-op .intel_syntax has been implemented to allow gas to parse i386 |
a40cbfa3 | 895 | assembly programs with intel syntax. |
252b5132 | 896 | |
a40cbfa3 | 897 | * New pseudo-ops .func,.endfunc to aid in debugging user-written assembler code. |
252b5132 | 898 | |
a40cbfa3 | 899 | * Added -gdwarf2 option to generate DWARF 2 debugging information. |
041dd5a9 | 900 | |
a40cbfa3 | 901 | * Full 16-bit mode support for i386. |
252b5132 | 902 | |
fa94de6b | 903 | * Greatly improved instruction operand checking for i386. This change will |
a40cbfa3 NC |
904 | produce errors or warnings on incorrect assembly code that previous versions |
905 | of gas accepted. If you get unexpected messages from code that worked with | |
906 | older versions of gas, please double check the code before reporting a bug. | |
252b5132 | 907 | |
a40cbfa3 | 908 | * Weak symbol support added for COFF targets. |
252b5132 | 909 | |
a40cbfa3 | 910 | * Mitsubishi D30V support added. |
252b5132 | 911 | |
a40cbfa3 | 912 | * Texas Instruments c80 (tms320c80) support added. |
252b5132 | 913 | |
a40cbfa3 | 914 | * i960 ELF support added. |
bedf545c | 915 | |
a40cbfa3 | 916 | * ARM ELF support added. |
a057431b | 917 | |
252b5132 RH |
918 | Changes in 2.9: |
919 | ||
a40cbfa3 | 920 | * Texas Instruments c30 (tms320c30) support added. |
252b5132 | 921 | |
fa94de6b | 922 | * The assembler now optimizes the exception frame information generated by egcs |
a40cbfa3 | 923 | and gcc 2.8. The new --traditional-format option disables this optimization. |
252b5132 | 924 | |
a40cbfa3 | 925 | * Added --gstabs option to generate stabs debugging information. |
252b5132 | 926 | |
fa94de6b | 927 | * The -a option takes a new suboption, m (e.g., -alm) to expand macros in a |
a40cbfa3 | 928 | listing. |
252b5132 | 929 | |
a40cbfa3 | 930 | * Added -MD option to print dependencies. |
252b5132 RH |
931 | |
932 | Changes in 2.8: | |
933 | ||
a40cbfa3 | 934 | * BeOS support added. |
252b5132 | 935 | |
a40cbfa3 | 936 | * MIPS16 support added. |
252b5132 | 937 | |
a40cbfa3 | 938 | * Motorola ColdFire 5200 support added (configure for m68k and use -m5200). |
252b5132 | 939 | |
a40cbfa3 | 940 | * Alpha/VMS support added. |
252b5132 | 941 | |
a40cbfa3 NC |
942 | * m68k options --base-size-default-16, --base-size-default-32, |
943 | --disp-size-default-16, and --disp-size-default-32 added. | |
252b5132 | 944 | |
a40cbfa3 NC |
945 | * The alignment directives now take an optional third argument, which is the |
946 | maximum number of bytes to skip. If doing the alignment would require | |
947 | skipping more than the given number of bytes, the alignment is not done at | |
948 | all. | |
252b5132 | 949 | |
a40cbfa3 | 950 | * The ELF assembler has a new pseudo-op, .symver, used for symbol versioning. |
252b5132 | 951 | |
a40cbfa3 NC |
952 | * The -a option takes a new suboption, c (e.g., -alc), to skip false |
953 | conditionals in listings. | |
252b5132 | 954 | |
a40cbfa3 NC |
955 | * Added new pseudo-op, .equiv; it's like .equ, except that it is an error if |
956 | the symbol is already defined. | |
252b5132 RH |
957 | |
958 | Changes in 2.7: | |
959 | ||
a40cbfa3 NC |
960 | * The PowerPC assembler now allows the use of symbolic register names (r0, |
961 | etc.) if -mregnames is used. Symbolic names preceded by a '%' (%r0, etc.) | |
962 | can be used any time. PowerPC 860 move to/from SPR instructions have been | |
963 | added. | |
252b5132 | 964 | |
a40cbfa3 | 965 | * Alpha Linux (ELF) support added. |
252b5132 | 966 | |
a40cbfa3 | 967 | * PowerPC ELF support added. |
252b5132 | 968 | |
a40cbfa3 | 969 | * m68k Linux (ELF) support added. |
252b5132 | 970 | |
a40cbfa3 | 971 | * i960 Hx/Jx support added. |
252b5132 | 972 | |
a40cbfa3 | 973 | * i386/PowerPC gnu-win32 support added. |
252b5132 | 974 | |
a40cbfa3 NC |
975 | * SCO ELF support added. For OpenServer 5 targets (i386-unknown-sco3.2v5) the |
976 | default is to build COFF-only support. To get a set of tools that generate | |
fa94de6b | 977 | ELF (they'll understand both COFF and ELF), you must configure with |
a40cbfa3 | 978 | target=i386-unknown-sco3.2v5elf. |
252b5132 | 979 | |
a40cbfa3 | 980 | * m88k-motorola-sysv3* support added. |
252b5132 RH |
981 | |
982 | Changes in 2.6: | |
983 | ||
a40cbfa3 | 984 | * Gas now directly supports macros, without requiring GASP. |
252b5132 | 985 | |
a40cbfa3 NC |
986 | * Gas now has an MRI assembler compatibility mode. Use -M or --mri to select |
987 | MRI mode. The pseudo-op ``.mri 1'' will switch into the MRI mode until the | |
988 | ``.mri 0'' is seen; this can be convenient for inline assembler code. | |
252b5132 | 989 | |
a40cbfa3 | 990 | * Added --defsym SYM=VALUE option. |
252b5132 | 991 | |
a40cbfa3 | 992 | * Added -mips4 support to MIPS assembler. |
252b5132 | 993 | |
a40cbfa3 | 994 | * Added PIC support to Solaris and SPARC SunOS 4 assembler. |
252b5132 RH |
995 | |
996 | Changes in 2.4: | |
997 | ||
a40cbfa3 | 998 | * Converted this directory to use an autoconf-generated configure script. |
252b5132 | 999 | |
a40cbfa3 | 1000 | * ARM support, from Richard Earnshaw. |
252b5132 | 1001 | |
a40cbfa3 NC |
1002 | * Updated VMS support, from Pat Rankin, including considerably improved |
1003 | debugging support. | |
252b5132 | 1004 | |
a40cbfa3 | 1005 | * Support for the control registers in the 68060. |
252b5132 | 1006 | |
a40cbfa3 | 1007 | * Handles (ignores) a new directive ".this_GCC_requires_the_GNU_assembler", to |
fa94de6b RM |
1008 | provide for possible future gcc changes, for targets where gas provides some |
1009 | features not available in the native assembler. If the native assembler is | |
a40cbfa3 | 1010 | used, it should become obvious pretty quickly what the problem is. |
252b5132 | 1011 | |
a40cbfa3 | 1012 | * Usage message is available with "--help". |
252b5132 | 1013 | |
fa94de6b | 1014 | * The GNU Assembler Preprocessor (gasp) is included. (Actually, it was in 2.3 |
a40cbfa3 | 1015 | also, but didn't get into the NEWS file.) |
252b5132 | 1016 | |
a40cbfa3 | 1017 | * Weak symbol support for a.out. |
252b5132 | 1018 | |
fa94de6b | 1019 | * A bug in the listing code which could cause an infinite loop has been fixed. |
a40cbfa3 | 1020 | Bugs in listings when generating a COFF object file have also been fixed. |
252b5132 | 1021 | |
a40cbfa3 NC |
1022 | * Initial i386-svr4 PIC implementation from Eric Youngdale, based on code by |
1023 | Paul Kranenburg. | |
252b5132 | 1024 | |
a40cbfa3 NC |
1025 | * Improved Alpha support. Immediate constants can have a much larger range |
1026 | now. Support for the 21164 has been contributed by Digital. | |
252b5132 | 1027 | |
a40cbfa3 | 1028 | * Updated ns32k (pc532-mach, netbsd532) support from Ian Dall. |
252b5132 RH |
1029 | |
1030 | Changes in 2.3: | |
1031 | ||
a40cbfa3 | 1032 | * Mach i386 support, by David Mackenzie and Ken Raeburn. |
252b5132 | 1033 | |
a40cbfa3 | 1034 | * RS/6000 and PowerPC support by Ian Taylor. |
252b5132 | 1035 | |
a40cbfa3 NC |
1036 | * VMS command scripts (make-gas.com, config-gas.com) have been worked on a bit, |
1037 | based on mail received from various people. The `-h#' option should work | |
1038 | again too. | |
252b5132 | 1039 | |
a40cbfa3 | 1040 | * HP-PA work, by Jeff Law. Note, for the PA, gas-2.3 has been designed to work |
fa94de6b | 1041 | with gdb-4.12 and gcc-2.6. As gcc-2.6 has not been released yet, a special |
a40cbfa3 NC |
1042 | version of gcc-2.5.8 has been patched to work with gas-2.3. You can retrieve |
1043 | this special version of gcc-2.5.8 via anonymous ftp from jaguar.cs.utah.edu | |
1044 | in the "dist" directory. | |
252b5132 | 1045 | |
a40cbfa3 NC |
1046 | * Vax support in gas fixed for BSD, so it builds and seems to run a couple |
1047 | simple tests okay. I haven't put it through extensive testing. (GNU make is | |
1048 | currently required for BSD 4.3 builds.) | |
252b5132 | 1049 | |
fa94de6b | 1050 | * Support for the DEC Alpha, running OSF/1 (ECOFF format). The gas support is |
a40cbfa3 NC |
1051 | based on code donated by CMU, which used an a.out-based format. I'm afraid |
1052 | the alpha-a.out support is pretty badly mangled, and much of it removed; | |
1053 | making it work will require rewriting it as BFD support for the format anyways. | |
252b5132 | 1054 | |
a40cbfa3 | 1055 | * Irix 5 support. |
252b5132 | 1056 | |
fa94de6b | 1057 | * The test suites have been fixed up a bit, so that they should work with a |
a40cbfa3 | 1058 | couple different versions of expect and dejagnu. |
252b5132 | 1059 | |
fa94de6b RM |
1060 | * Symbols' values are now handled internally as expressions, permitting more |
1061 | flexibility in evaluating them in some cases. Some details of relocation | |
a40cbfa3 NC |
1062 | handling have also changed, and simple constant pool management has been |
1063 | added, to make the Alpha port easier. | |
252b5132 | 1064 | |
a40cbfa3 NC |
1065 | * New option "--statistics" for printing out program run times. This is |
1066 | intended to be used with the gcc "-Q" option, which prints out times spent in | |
1067 | various phases of compilation. (You should be able to get all of them | |
1068 | printed out with "gcc -Q -Wa,--statistics", I think.) | |
252b5132 RH |
1069 | |
1070 | Changes in 2.2: | |
1071 | ||
a40cbfa3 | 1072 | * RS/6000 AIX and MIPS SGI Irix 5 support has been added. |
252b5132 | 1073 | |
fa94de6b RM |
1074 | * Configurations that are still in development (and therefore are convenient to |
1075 | have listed in configure.in) still get rejected without a minor change to | |
a40cbfa3 NC |
1076 | gas/Makefile.in, so people not doing development work shouldn't get the |
1077 | impression that support for such configurations is actually believed to be | |
1078 | reliable. | |
252b5132 | 1079 | |
fa94de6b | 1080 | * The program name (usually "as") is printed when a fatal error message is |
a40cbfa3 NC |
1081 | displayed. This should prevent some confusion about the source of occasional |
1082 | messages about "internal errors". | |
252b5132 | 1083 | |
fa94de6b | 1084 | * ELF support is falling into place. Support for the 386 should be working. |
a40cbfa3 | 1085 | Support for SPARC Solaris is in. HPPA support from Utah is being integrated. |
252b5132 | 1086 | |
a40cbfa3 NC |
1087 | * Symbol values are maintained as expressions instead of being immediately |
1088 | boiled down to add-symbol, sub-symbol, and constant. This permits slightly | |
1089 | more complex calculations involving symbols whose values are not alreadey | |
1090 | known. | |
252b5132 | 1091 | |
a40cbfa3 | 1092 | * DBX-style debugging info ("stabs") is now supported for COFF formats. |
fa94de6b RM |
1093 | If any stabs directives are seen in the source, GAS will create two new |
1094 | sections: a ".stab" and a ".stabstr" section. The format of the .stab | |
a40cbfa3 NC |
1095 | section is nearly identical to the a.out symbol format, and .stabstr is |
1096 | its string table. For this to be useful, you must have configured GCC | |
1097 | to generate stabs (by defining DBX_DEBUGGING_INFO), and must have a GDB | |
1098 | that can use the stab sections (4.11 or later). | |
252b5132 | 1099 | |
fa94de6b | 1100 | * LynxOS, on i386 and m68k platforms, is now supported. SPARC LynxOS |
a40cbfa3 | 1101 | support is in progress. |
252b5132 RH |
1102 | |
1103 | Changes in 2.1: | |
1104 | ||
fa94de6b | 1105 | * Several small fixes for i386-aix (PS/2) support from Minh Tran-Le have been |
a40cbfa3 | 1106 | incorporated, but not well tested yet. |
252b5132 | 1107 | |
fa94de6b | 1108 | * Altered the opcode table split for m68k; it should require less VM to compile |
a40cbfa3 | 1109 | with gcc now. |
252b5132 | 1110 | |
a40cbfa3 NC |
1111 | * Some minor adjustments to add (Convergent Technologies') Miniframe support, |
1112 | suggested by Ronald Cole. | |
252b5132 | 1113 | |
a40cbfa3 NC |
1114 | * HPPA support (running OSF only, not HPUX) has been contributed by Utah. This |
1115 | includes improved ELF support, which I've started adapting for SPARC Solaris | |
1116 | 2.x. Integration isn't completely, so it probably won't work. | |
252b5132 | 1117 | |
a40cbfa3 | 1118 | * HP9000/300 support, donated by HP, has been merged in. |
252b5132 | 1119 | |
a40cbfa3 | 1120 | * Ian Taylor has finished the MIPS ECOFF (Ultrix, Irix) support. |
252b5132 | 1121 | |
a40cbfa3 | 1122 | * Better error messages for unsupported configurations (e.g., hppa-hpux). |
252b5132 | 1123 | |
a40cbfa3 | 1124 | * Test suite framework is starting to become reasonable. |
252b5132 RH |
1125 | |
1126 | Changes in 2.0: | |
1127 | ||
a40cbfa3 | 1128 | * Mostly bug fixes. |
252b5132 | 1129 | |
a40cbfa3 | 1130 | * Some more merging of BFD and ELF code, but ELF still doesn't work. |
252b5132 RH |
1131 | |
1132 | Changes in 1.94: | |
1133 | ||
a40cbfa3 NC |
1134 | * BFD merge is partly done. Adventurous souls may try giving configure the |
1135 | "--with-bfd-assembler" option. Currently, ELF format requires it, a.out | |
1136 | format accepts it; SPARC CPU accepts it. It's the default only for OS "elf" | |
1137 | or "solaris". (ELF isn't really supported yet. It needs work. I've got | |
1138 | some code from Utah for HP-PA ELF, and from DG for m88k ELF, but they're not | |
1139 | fully merged yet.) | |
252b5132 | 1140 | |
a40cbfa3 NC |
1141 | * The 68K opcode table has been split in half. It should now compile under gcc |
1142 | without consuming ridiculous amounts of memory. | |
252b5132 | 1143 | |
a40cbfa3 NC |
1144 | * A couple data structures have been reduced in size. This should result in |
1145 | saving a little bit of space at runtime. | |
252b5132 | 1146 | |
a40cbfa3 NC |
1147 | * Support for MIPS, from OSF and Ralph Campbell, has been merged in. The OSF |
1148 | code provided ROSE format support, which I haven't merged in yet. (I can | |
1149 | make it available, if anyone wants to try it out.) Ralph's code, for BSD | |
1150 | 4.4, supports a.out format. We don't have ECOFF support in just yet; it's | |
1151 | coming. | |
252b5132 | 1152 | |
a40cbfa3 | 1153 | * Support for the Hitachi H8/500 has been added. |
252b5132 | 1154 | |
a40cbfa3 NC |
1155 | * VMS host and target support should be working now, thanks chiefly to Eric |
1156 | Youngdale. | |
252b5132 RH |
1157 | |
1158 | Changes in 1.93.01: | |
1159 | ||
a40cbfa3 | 1160 | * For m68k, support for more processors has been added: 68040, CPU32, 68851. |
252b5132 | 1161 | |
a40cbfa3 | 1162 | * For i386, .align is now power-of-two; was number-of-bytes. |
252b5132 | 1163 | |
a40cbfa3 NC |
1164 | * For m68k, "%" is now accepted before register names. For COFF format, which |
1165 | doesn't use underscore prefixes for C labels, it is required, so variable "a0" | |
1166 | can be distinguished from the register. | |
252b5132 | 1167 | |
a40cbfa3 NC |
1168 | * Last public release was 1.38. Lots of configuration changes since then, lots |
1169 | of new CPUs and formats, lots of bugs fixed. | |
252b5132 RH |
1170 | |
1171 | \f | |
fd67aa11 | 1172 | Copyright (C) 2012-2024 Free Software Foundation, Inc. |
5bf135a7 NC |
1173 | |
1174 | Copying and distribution of this file, with or without modification, | |
1175 | are permitted in any medium without royalty provided the copyright | |
1176 | notice and this notice are preserved. | |
1177 | ||
252b5132 RH |
1178 | Local variables: |
1179 | fill-column: 79 | |
1180 | End: |