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Rearrange symbol_create parameters
[thirdparty/binutils-gdb.git] / gas / config / tc-arc.c
CommitLineData
252b5132 1/* tc-arc.c -- Assembler for the ARC
b3adc24a 2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19203624 19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
252b5132 23#include "as.h"
886a2506 24#include "subsegs.h"
886a2506 25#include "dwarf2dbg.h"
726c18e1 26#include "dw2gencfi.h"
3882b010 27#include "safe-ctype.h"
886a2506 28
252b5132 29#include "opcode/arc.h"
53a346d8 30#include "opcode/arc-attrs.h"
252b5132 31#include "elf/arc.h"
b99747ae 32#include "../opcodes/arc-ext.h"
252b5132 33
886a2506 34/* Defines section. */
0d2bcfaf 35
886a2506
NC		 36#define MAX_INSN_FIXUPS 2
37#define MAX_CONSTR_STR 20
4670103e 38#define FRAG_MAX_GROWTH 8
0d2bcfaf 39
886a2506
NC		 40#ifdef DEBUG
41# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
42#else
43# define pr_debug(fmt, args...)
44#endif
45
46#define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47#define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
db18dbab
GM		 48#define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
49 && (SUB_OPCODE (x) == 0x28))
886a2506 50
9004b6bd
AB		 51#ifndef TARGET_WITH_CPU
52#define TARGET_WITH_CPU "arc700"
53#endif /* TARGET_WITH_CPU */
54
53a346d8
CZ		 55#define ARC_GET_FLAG(s) (*symbol_get_tc (s))
56#define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
57#define streq(a, b) (strcmp (a, b) == 0)
58
4670103e
CZ		 59/* Enum used to enumerate the relaxable ins operands. */
60enum rlx_operand_type
61{
62 EMPTY = 0,
63 REGISTER,
64 REGISTER_S, /* Register for short instruction(s). */
65 REGISTER_NO_GP, /* Is a register but not gp register specifically. */
66 REGISTER_DUP, /* Duplication of previous operand of type register. */
67 IMMEDIATE,
68 BRACKET
69};
70
71enum arc_rlx_types
72{
73 ARC_RLX_NONE = 0,
74 ARC_RLX_BL_S,
75 ARC_RLX_BL,
76 ARC_RLX_B_S,
77 ARC_RLX_B,
78 ARC_RLX_ADD_U3,
79 ARC_RLX_ADD_U6,
80 ARC_RLX_ADD_LIMM,
81 ARC_RLX_LD_U7,
82 ARC_RLX_LD_S9,
83 ARC_RLX_LD_LIMM,
84 ARC_RLX_MOV_U8,
85 ARC_RLX_MOV_S12,
86 ARC_RLX_MOV_LIMM,
87 ARC_RLX_SUB_U3,
88 ARC_RLX_SUB_U6,
89 ARC_RLX_SUB_LIMM,
90 ARC_RLX_MPY_U6,
91 ARC_RLX_MPY_LIMM,
92 ARC_RLX_MOV_RU6,
93 ARC_RLX_MOV_RLIMM,
94 ARC_RLX_ADD_RRU6,
95 ARC_RLX_ADD_RRLIMM,
96};
97
886a2506
NC		 98/* Macros section. */
99
100#define regno(x) ((x) & 0x3F)
101#define is_ir_num(x) (((x) & ~0x3F) == 0)
8ddf6b2a
CZ		 102#define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
103#define is_spfp_p(op) (((sc) == SPX))
104#define is_dpfp_p(op) (((sc) == DPX))
105#define is_fpuda_p(op) (((sc) == DPA))
cf9bdae9 106#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
107 || (op)->insn_class == JUMP \
108 || (op)->insn_class == BRCC \
109 || (op)->insn_class == BBIT0 \
110 || (op)->insn_class == BBIT1 \
111 || (op)->insn_class == BI \
112 || (op)->insn_class == EI \
113 || (op)->insn_class == ENTER \
114 || (op)->insn_class == JLI \
115 || (op)->insn_class == LOOP \
116 || (op)->insn_class == LEAVE \
117 ))
c810e0b8 118#define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
bdd582db 119#define is_nps400_p(op) (((sc) == NPS400))
0d2bcfaf 120
886a2506
NC		 121/* Generic assembler global variables which must be defined by all
122 targets. */
0d2bcfaf 123
886a2506 124/* Characters which always start a comment. */
252b5132
RH		 125const char comment_chars[] = "#;";
126
886a2506 127/* Characters which start a comment at the beginning of a line. */
252b5132
RH		 128const char line_comment_chars[] = "#";
129
886a2506
NC		 130/* Characters which may be used to separate multiple commands on a
131 single line. */
132const char line_separator_chars[] = "`";
252b5132 133
886a2506
NC		 134/* Characters which are used to indicate an exponent in a floating
135 point number. */
252b5132
RH		 136const char EXP_CHARS[] = "eE";
137
bcee8eb8
AM		 138/* Chars that mean this number is a floating point constant
139 As in 0f12.456 or 0d1.2345e12. */
252b5132
RH		 140const char FLT_CHARS[] = "rRsSfFdD";
141
142/* Byte order. */
143extern int target_big_endian;
144const char *arc_target_format = DEFAULT_TARGET_FORMAT;
145static int byte_order = DEFAULT_BYTE_ORDER;
146
b99747ae
CZ		 147/* Arc extension section. */
148static segT arcext_section;
149
4670103e
CZ		 150/* By default relaxation is disabled. */
151static int relaxation_state = 0;
152
886a2506 153extern int arc_get_mach (char *);
0d2bcfaf 154
4670103e 155/* Forward declarations. */
886a2506
NC		 156static void arc_lcomm (int);
157static void arc_option (int);
158static void arc_extra_reloc (int);
b99747ae 159static void arc_extinsn (int);
f36e33da 160static void arc_extcorereg (int);
53a346d8 161static void arc_attribute (int);
4670103e 162
886a2506 163const pseudo_typeS md_pseudo_table[] =
6f4b1afc
CM		 164{
165 /* Make sure that .word is 32 bits. */
166 { "word", cons, 4 },
886a2506 167
6f4b1afc
CM		 168 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
169 { "lcomm", arc_lcomm, 0 },
170 { "lcommon", arc_lcomm, 0 },
171 { "cpu", arc_option, 0 },
252b5132 172
53a346d8 173 { "arc_attribute", arc_attribute, 0 },
f36e33da
CZ		 174 { "extinstruction", arc_extinsn, 0 },
175 { "extcoreregister", arc_extcorereg, EXT_CORE_REGISTER },
176 { "extauxregister", arc_extcorereg, EXT_AUX_REGISTER },
177 { "extcondcode", arc_extcorereg, EXT_COND_CODE },
b99747ae 178
6f4b1afc
CM		 179 { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
180 { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
886a2506 181
6f4b1afc
CM		 182 { NULL, NULL, 0 }
183};
252b5132 184
252b5132 185const char *md_shortopts = "";
ea1562b3
NC		 186
187enum options
6f4b1afc
CM		 188{
189 OPTION_EB = OPTION_MD_BASE,
190 OPTION_EL,
191
192 OPTION_ARC600,
193 OPTION_ARC601,
194 OPTION_ARC700,
195 OPTION_ARCEM,
196 OPTION_ARCHS,
197
198 OPTION_MCPU,
199 OPTION_CD,
4670103e 200 OPTION_RELAX,
bdd582db 201 OPTION_NPS400,
6f4b1afc 202
ce440d63
GM		 203 OPTION_SPFP,
204 OPTION_DPFP,
205 OPTION_FPUDA,
206
6f4b1afc
CM		 207 /* The following options are deprecated and provided here only for
208 compatibility reasons. */
209 OPTION_USER_MODE,
210 OPTION_LD_EXT_MASK,
211 OPTION_SWAP,
212 OPTION_NORM,
213 OPTION_BARREL_SHIFT,
214 OPTION_MIN_MAX,
215 OPTION_NO_MPY,
216 OPTION_EA,
217 OPTION_MUL64,
218 OPTION_SIMD,
6f4b1afc
CM		 219 OPTION_XMAC_D16,
220 OPTION_XMAC_24,
221 OPTION_DSP_PACKA,
222 OPTION_CRC,
223 OPTION_DVBF,
224 OPTION_TELEPHONY,
225 OPTION_XYMEMORY,
226 OPTION_LOCK,
227 OPTION_SWAPE,
ce440d63 228 OPTION_RTSC
6f4b1afc 229};
ea1562b3
NC		 230
231struct option md_longopts[] =
6f4b1afc
CM		 232{
233 { "EB", no_argument, NULL, OPTION_EB },
234 { "EL", no_argument, NULL, OPTION_EL },
235 { "mcpu", required_argument, NULL, OPTION_MCPU },
236 { "mA6", no_argument, NULL, OPTION_ARC600 },
24b368f8
CZ		 237 { "mARC600", no_argument, NULL, OPTION_ARC600 },
238 { "mARC601", no_argument, NULL, OPTION_ARC601 },
239 { "mARC700", no_argument, NULL, OPTION_ARC700 },
6f4b1afc
CM		 240 { "mA7", no_argument, NULL, OPTION_ARC700 },
241 { "mEM", no_argument, NULL, OPTION_ARCEM },
242 { "mHS", no_argument, NULL, OPTION_ARCHS },
243 { "mcode-density", no_argument, NULL, OPTION_CD },
4670103e 244 { "mrelax", no_argument, NULL, OPTION_RELAX },
bdd582db 245 { "mnps400", no_argument, NULL, OPTION_NPS400 },
6f4b1afc 246
ce440d63
GM		 247 /* Floating point options */
248 { "mspfp", no_argument, NULL, OPTION_SPFP},
249 { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
250 { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
251 { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
252 { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
253 { "mdpfp", no_argument, NULL, OPTION_DPFP},
254 { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
255 { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
256 { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
257 { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
258 { "mfpuda", no_argument, NULL, OPTION_FPUDA},
259
6f4b1afc
CM		 260 /* The following options are deprecated and provided here only for
261 compatibility reasons. */
262 { "mav2em", no_argument, NULL, OPTION_ARCEM },
263 { "mav2hs", no_argument, NULL, OPTION_ARCHS },
264 { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
265 { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
266 { "mswap", no_argument, NULL, OPTION_SWAP },
267 { "mnorm", no_argument, NULL, OPTION_NORM },
268 { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
269 { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
270 { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
271 { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
272 { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
273 { "mea", no_argument, NULL, OPTION_EA },
274 { "mEA", no_argument, NULL, OPTION_EA },
275 { "mmul64", no_argument, NULL, OPTION_MUL64 },
276 { "msimd", no_argument, NULL, OPTION_SIMD},
6f4b1afc
CM		 277 { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
278 { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
279 { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
280 { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
281 { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
282 { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
283 { "mcrc", no_argument, NULL, OPTION_CRC},
284 { "mdvbf", no_argument, NULL, OPTION_DVBF},
285 { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
286 { "mxy", no_argument, NULL, OPTION_XYMEMORY},
287 { "mlock", no_argument, NULL, OPTION_LOCK},
288 { "mswape", no_argument, NULL, OPTION_SWAPE},
289 { "mrtsc", no_argument, NULL, OPTION_RTSC},
6f4b1afc
CM		 290
291 { NULL, no_argument, NULL, 0 }
292};
252b5132 293
886a2506 294size_t md_longopts_size = sizeof (md_longopts);
0d2bcfaf 295
886a2506 296/* Local data and data types. */
252b5132 297
886a2506
NC		 298/* Used since new relocation types are introduced in this
299 file (DUMMY_RELOC_LITUSE_*). */
300typedef int extended_bfd_reloc_code_real_type;
252b5132 301
886a2506 302struct arc_fixup
252b5132 303{
886a2506 304 expressionS exp;
252b5132 305
886a2506 306 extended_bfd_reloc_code_real_type reloc;
252b5132 307
886a2506
NC		 308 /* index into arc_operands. */
309 unsigned int opindex;
252b5132 310
886a2506
NC		 311 /* PC-relative, used by internals fixups. */
312 unsigned char pcrel;
252b5132 313
886a2506
NC		 314 /* TRUE if this fixup is for LIMM operand. */
315 bfd_boolean islong;
316};
252b5132 317
886a2506
NC		 318struct arc_insn
319{
bdfe53e3 320 unsigned long long int insn;
886a2506
NC		 321 int nfixups;
322 struct arc_fixup fixups[MAX_INSN_FIXUPS];
323 long limm;
91fdca6f 324 unsigned int len; /* Length of instruction in bytes. */
886a2506
NC		 325 bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
326 valid. */
4670103e
CZ		 327 bfd_boolean relax; /* Boolean value: TRUE if needs
328 relaxation. */
886a2506 329};
ea1562b3 330
886a2506
NC		 331/* Structure to hold any last two instructions. */
332static struct arc_last_insn
252b5132 333{
886a2506
NC		 334 /* Saved instruction opcode. */
335 const struct arc_opcode *opcode;
252b5132 336
886a2506
NC		 337 /* Boolean value: TRUE if current insn is short. */
338 bfd_boolean has_limm;
252b5132 339
886a2506
NC		 340 /* Boolean value: TRUE if current insn has delay slot. */
341 bfd_boolean has_delay_slot;
342} arc_last_insns[2];
252b5132 343
b99747ae
CZ		 344/* Extension instruction suffix classes. */
345typedef struct
346{
347 const char *name;
348 int len;
c810e0b8 349 int attr_class;
b99747ae
CZ		 350} attributes_t;
351
352static const attributes_t suffixclass[] =
353{
354 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG },
355 { "SUFFIX_COND", 11, ARC_SUFFIX_COND },
356 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE }
357};
358
359/* Extension instruction syntax classes. */
360static const attributes_t syntaxclass[] =
361{
362 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP },
945e0f82
CZ		 363 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP },
364 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP },
365 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP }
b99747ae
CZ		 366};
367
368/* Extension instruction syntax classes modifiers. */
369static const attributes_t syntaxclassmod[] =
370{
371 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED },
372 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM }
373};
374
f36e33da
CZ		 375/* Extension register type. */
376typedef struct
377{
378 char *name;
379 int number;
380 int imode;
381} extRegister_t;
382
383/* A structure to hold the additional conditional codes. */
384static struct
385{
386 struct arc_flag_operand *arc_ext_condcode;
387 int size;
388} ext_condcode = { NULL, 0 };
389
da5be039
AB		 390/* Structure to hold an entry in ARC_OPCODE_HASH. */
391struct arc_opcode_hash_entry
392{
393 /* The number of pointers in the OPCODE list. */
394 size_t count;
395
396 /* Points to a list of opcode pointers. */
397 const struct arc_opcode **opcode;
398};
399
1328504b
AB		 400/* Structure used for iterating through an arc_opcode_hash_entry. */
401struct arc_opcode_hash_entry_iterator
402{
403 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
404 size_t index;
405
406 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
407 returned by this iterator. */
408 const struct arc_opcode *opcode;
409};
410
4670103e
CZ		 411/* Forward declaration. */
412static void assemble_insn
413 (const struct arc_opcode *, const expressionS *, int,
414 const struct arc_flags *, int, struct arc_insn *);
415
bb65a718
AB		 416/* The selection of the machine type can come from different sources. This
417 enum is used to track how the selection was made in order to perform
418 error checks. */
419enum mach_selection_type
420 {
421 MACH_SELECTION_NONE,
422 MACH_SELECTION_FROM_DEFAULT,
423 MACH_SELECTION_FROM_CPU_DIRECTIVE,
424 MACH_SELECTION_FROM_COMMAND_LINE
425 };
426
427/* How the current machine type was selected. */
428static enum mach_selection_type mach_selection_mode = MACH_SELECTION_NONE;
0d2bcfaf 429
886a2506 430/* The hash table of instruction opcodes. */
629310ab 431static htab_t arc_opcode_hash;
0d2bcfaf 432
886a2506 433/* The hash table of register symbols. */
629310ab 434static htab_t arc_reg_hash;
252b5132 435
f36e33da 436/* The hash table of aux register symbols. */
629310ab 437static htab_t arc_aux_hash;
f36e33da 438
db18dbab 439/* The hash table of address types. */
629310ab 440static htab_t arc_addrtype_hash;
db18dbab 441
a9752fdf
CZ		 442#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
443 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
444 E_ARC_MACH_ARC600, EXTRA}
445#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
446 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
447 E_ARC_MACH_ARC700, EXTRA}
448#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
449 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
450 EF_ARC_CPU_ARCV2EM, EXTRA}
451#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
452 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
453 EF_ARC_CPU_ARCV2HS, EXTRA}
940171d0
AK		 454#define ARC_CPU_TYPE_NONE \
455 { 0, 0, 0, 0, 0 }
a9752fdf 456
886a2506
NC		 457/* A table of CPU names and opcode sets. */
458static const struct cpu_type
459{
460 const char *name;
461 unsigned flags;
462 int mach;
463 unsigned eflags;
464 unsigned features;
252b5132 465}
886a2506 466 cpu_types[] =
252b5132 467{
940171d0 468 #include "elf/arc-cpu.def"
886a2506 469};
252b5132 470
bb65a718 471/* Information about the cpu/variant we're assembling for. */
53a346d8 472static struct cpu_type selected_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
bb050a69 473
63741043 474/* TRUE if current assembly code uses RF16 only registers. */
475static bfd_boolean rf16_only = TRUE;
476
53a346d8
CZ		 477/* MPY option. */
478static unsigned mpy_option = 0;
479
480/* Use PIC. */
481static unsigned pic_option = 0;
482
483/* Use small data. */
484static unsigned sda_option = 0;
485
486/* Use TLS. */
487static unsigned tls_option = 0;
bb65a718 488
a9752fdf
CZ		 489/* Command line given features. */
490static unsigned cl_features = 0;
491
886a2506
NC		 492/* Used by the arc_reloc_op table. Order is important. */
493#define O_gotoff O_md1 /* @gotoff relocation. */
494#define O_gotpc O_md2 /* @gotpc relocation. */
495#define O_plt O_md3 /* @plt relocation. */
496#define O_sda O_md4 /* @sda relocation. */
497#define O_pcl O_md5 /* @pcl relocation. */
498#define O_tlsgd O_md6 /* @tlsgd relocation. */
499#define O_tlsie O_md7 /* @tlsie relocation. */
500#define O_tpoff9 O_md8 /* @tpoff9 relocation. */
501#define O_tpoff O_md9 /* @tpoff relocation. */
502#define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
503#define O_dtpoff O_md11 /* @dtpoff relocation. */
504#define O_last O_dtpoff
505
506/* Used to define a bracket as operand in tokens. */
507#define O_bracket O_md32
508
db18dbab
GM		 509/* Used to define a colon as an operand in tokens. */
510#define O_colon O_md31
511
512/* Used to define address types in nps400. */
513#define O_addrtype O_md30
514
886a2506
NC		 515/* Dummy relocation, to be sorted out. */
516#define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
517
518#define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
519
520/* A table to map the spelling of a relocation operand into an appropriate
521 bfd_reloc_code_real_type type. The table is assumed to be ordered such
522 that op-O_literal indexes into it. */
523#define ARC_RELOC_TABLE(op) \
524 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
525 ? (abort (), 0) \
526 : (int) (op) - (int) O_gotoff) ])
527
528#define DEF(NAME, RELOC, REQ) \
529 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
530
531static const struct arc_reloc_op_tag
532{
533 /* String to lookup. */
534 const char *name;
535 /* Size of the string. */
536 size_t length;
537 /* Which operator to use. */
538 operatorT op;
539 extended_bfd_reloc_code_real_type reloc;
540 /* Allows complex relocation expression like identifier@reloc +
541 const. */
542 unsigned int complex_expr : 1;
543}
544 arc_reloc_op[] =
6f4b1afc
CM		 545{
546 DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1),
547 DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0),
548 DEF (plt, BFD_RELOC_ARC_PLT32, 0),
549 DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1),
550 DEF (pcl, BFD_RELOC_ARC_PC32, 1),
551 DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0),
552 DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0),
553 DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
b125bd17 554 DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
6f4b1afc 555 DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
05bbf016 556 DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 1),
6f4b1afc 557};
252b5132 558
886a2506
NC		 559static const int arc_num_reloc_op
560= sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
561
4670103e
CZ		 562/* Structure for relaxable instruction that have to be swapped with a
563 smaller alternative instruction. */
564struct arc_relaxable_ins
565{
566 /* Mnemonic that should be checked. */
567 const char *mnemonic_r;
568
569 /* Operands that should be checked.
570 Indexes of operands from operand array. */
571 enum rlx_operand_type operands[6];
572
573 /* Flags that should be checked. */
574 unsigned flag_classes[5];
575
576 /* Mnemonic (smaller) alternative to be used later for relaxation. */
577 const char *mnemonic_alt;
578
579 /* Index of operand that generic relaxation has to check. */
580 unsigned opcheckidx;
581
582 /* Base subtype index used. */
583 enum arc_rlx_types subtype;
584};
585
586#define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
587 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
588 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
589 (SIZE), \
590 (NEXT) } \
591
592#define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
593 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
594 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
595 (SIZE), \
596 (NEXT) } \
597
598
599/* ARC relaxation table. */
600const relax_typeS md_relax_table[] =
601{
602 /* Fake entry. */
603 {0, 0, 0, 0},
604
605 /* BL_S s13 ->
606 BL s25. */
db18dbab
GM		 607 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL),
608 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 609
610 /* B_S s10 ->
611 B s25. */
db18dbab
GM		 612 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B),
613 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 614
615 /* ADD_S c,b, u3 ->
616 ADD<.f> a,b,u6 ->
617 ADD<.f> a,b,limm. */
db18dbab
GM		 618 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6),
619 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM),
620 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 621
622 /* LD_S a, [b, u7] ->
623 LD<zz><.x><.aa><.di> a, [b, s9] ->
624 LD<zz><.x><.aa><.di> a, [b, limm] */
db18dbab
GM		 625 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9),
626 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM),
627 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE),
4670103e
CZ		 628
629 /* MOV_S b, u8 ->
630 MOV<.f> b, s12 ->
631 MOV<.f> b, limm. */
db18dbab
GM		 632 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12),
633 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM),
634 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 635
636 /* SUB_S c, b, u3 ->
637 SUB<.f> a, b, u6 ->
638 SUB<.f> a, b, limm. */
db18dbab
GM		 639 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6),
640 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM),
641 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 642
643 /* MPY<.f> a, b, u6 ->
644 MPY<.f> a, b, limm. */
db18dbab
GM		 645 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM),
646 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 647
648 /* MOV<.f><.cc> b, u6 ->
649 MOV<.f><.cc> b, limm. */
db18dbab
GM		 650 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM),
651 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 652
653 /* ADD<.f><.cc> b, b, u6 ->
654 ADD<.f><.cc> b, b, limm. */
db18dbab
GM		 655 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM),
656 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 657};
658
659/* Order of this table's entries matters! */
660const struct arc_relaxable_ins arc_relaxable_insns[] =
661{
662 { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S },
663 { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S },
664 { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add",
665 2, ARC_RLX_ADD_RRU6},
666 { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2,
667 ARC_RLX_ADD_U3 },
668 { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2,
669 ARC_RLX_ADD_U6 },
670 { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET },
671 { 0 }, "ld_s", 3, ARC_RLX_LD_U7 },
672 { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET },
673 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 },
674 { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 },
675 { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 },
676 { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 },
677 { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2,
678 ARC_RLX_SUB_U3 },
679 { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2,
680 ARC_RLX_SUB_U6 },
681 { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2,
682 ARC_RLX_MPY_U6 },
683};
684
685const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
686
886a2506
NC		 687/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
688symbolS * GOT_symbol = 0;
689
690/* Set to TRUE when we assemble instructions. */
691static bfd_boolean assembling_insn = FALSE;
692
53a346d8
CZ		 693/* List with attributes set explicitly. */
694static bfd_boolean attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
695
886a2506
NC		 696/* Functions implementation. */
697
b9b47ab7
AB		 698/* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
699 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
700 are no matching entries in ARC_OPCODE_HASH. */
da5be039 701
b9b47ab7 702static const struct arc_opcode_hash_entry *
da5be039
AB		 703arc_find_opcode (const char *name)
704{
705 const struct arc_opcode_hash_entry *entry;
da5be039 706
629310ab 707 entry = str_hash_find (arc_opcode_hash, name);
b9b47ab7 708 return entry;
da5be039
AB		 709}
710
1328504b
AB		 711/* Initialise the iterator ITER. */
712
713static void
714arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter)
715{
716 iter->index = 0;
717 iter->opcode = NULL;
718}
719
720/* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
721 calls to this function. Return NULL when all ARC_OPCODE entries have
722 been returned. */
723
724static const struct arc_opcode *
725arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry,
726 struct arc_opcode_hash_entry_iterator *iter)
727{
728 if (iter->opcode == NULL && iter->index == 0)
729 {
730 gas_assert (entry->count > 0);
731 iter->opcode = entry->opcode[iter->index];
732 }
733 else if (iter->opcode != NULL)
734 {
735 const char *old_name = iter->opcode->name;
736
737 iter->opcode++;
fe779266
AB		 738 if (iter->opcode->name == NULL
739 || strcmp (old_name, iter->opcode->name) != 0)
1328504b
AB		 740 {
741 iter->index++;
742 if (iter->index == entry->count)
743 iter->opcode = NULL;
744 else
745 iter->opcode = entry->opcode[iter->index];
746 }
747 }
748
749 return iter->opcode;
750}
751
b99747ae
CZ		 752/* Insert an opcode into opcode hash structure. */
753
754static void
755arc_insert_opcode (const struct arc_opcode *opcode)
756{
629310ab 757 const char *name;
b99747ae
CZ		 758 struct arc_opcode_hash_entry *entry;
759 name = opcode->name;
760
629310ab 761 entry = str_hash_find (arc_opcode_hash, name);
b99747ae
CZ		 762 if (entry == NULL)
763 {
add39d23 764 entry = XNEW (struct arc_opcode_hash_entry);
b99747ae
CZ		 765 entry->count = 0;
766 entry->opcode = NULL;
767
629310ab 768 str_hash_insert (arc_opcode_hash, name, (void *) entry);
b99747ae
CZ		 769 }
770
add39d23
TS		 771 entry->opcode = XRESIZEVEC (const struct arc_opcode *, entry->opcode,
772 entry->count + 1);
b99747ae
CZ		 773
774 if (entry->opcode == NULL)
775 as_fatal (_("Virtual memory exhausted"));
776
777 entry->opcode[entry->count] = opcode;
778 entry->count++;
779}
780
781
bdfe53e3
AB		 782/* Like md_number_to_chars but for middle-endian values. The 4-byte limm
783 value, is encoded as 'middle-endian' for a little-endian target. This
784 function is used for regular 4, 6, and 8 byte instructions as well. */
886a2506
NC		 785
786static void
bdfe53e3 787md_number_to_chars_midend (char *buf, unsigned long long val, int n)
886a2506 788{
bdfe53e3 789 switch (n)
886a2506 790 {
bdfe53e3
AB		 791 case 2:
792 md_number_to_chars (buf, val, n);
793 break;
794 case 6:
53b6d6f5 795 md_number_to_chars (buf, (val & 0xffff00000000ull) >> 32, 2);
bdfe53e3
AB		 796 md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4);
797 break;
798 case 4:
886a2506
NC		 799 md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
800 md_number_to_chars (buf + 2, (val & 0xffff), 2);
bdfe53e3
AB		 801 break;
802 case 8:
53b6d6f5 803 md_number_to_chars_midend (buf, (val & 0xffffffff00000000ull) >> 32, 4);
bdfe53e3
AB		 804 md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4);
805 break;
806 default:
807 abort ();
886a2506 808 }
252b5132
RH		 809}
810
bb050a69
CZ		 811/* Check if a feature is allowed for a specific CPU. */
812
813static void
814arc_check_feature (void)
815{
816 unsigned i;
817
818 if (!selected_cpu.features
819 || !selected_cpu.name)
820 return;
53a346d8
CZ		 821
822 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
823 if ((selected_cpu.features & feature_list[i].feature)
824 && !(selected_cpu.flags & feature_list[i].cpus))
825 as_bad (_("invalid %s option for %s cpu"), feature_list[i].name,
826 selected_cpu.name);
827
828 for (i = 0; i < ARRAY_SIZE (conflict_list); i++)
829 if ((selected_cpu.features & conflict_list[i]) == conflict_list[i])
830 as_bad(_("conflicting ISA extension attributes."));
bb050a69
CZ		 831}
832
24740d83 833/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
bb65a718
AB		 834 the relevant static global variables. Parameter SEL describes where
835 this selection originated from. */
24740d83
AB		 836
837static void
bb65a718 838arc_select_cpu (const char *arg, enum mach_selection_type sel)
24740d83 839{
24740d83 840 int i;
5e4f7e05 841 static struct cpu_type old_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
24740d83 842
bb65a718
AB		 843 /* We should only set a default if we've not made a selection from some
844 other source. */
845 gas_assert (sel != MACH_SELECTION_FROM_DEFAULT
846 || mach_selection_mode == MACH_SELECTION_NONE);
847
bb050a69
CZ		 848 if ((mach_selection_mode == MACH_SELECTION_FROM_CPU_DIRECTIVE)
849 && (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE))
850 as_bad (_("Multiple .cpu directives found"));
851
bb65a718 852 /* Look for a matching entry in CPU_TYPES array. */
24740d83
AB		 853 for (i = 0; cpu_types[i].name; ++i)
854 {
855 if (!strcasecmp (cpu_types[i].name, arg))
856 {
bb65a718
AB		 857 /* If a previous selection was made on the command line, then we
858 allow later selections on the command line to override earlier
859 ones. However, a selection from a '.cpu NAME' directive must
860 match the command line selection, or we give a warning. */
861 if (mach_selection_mode == MACH_SELECTION_FROM_COMMAND_LINE)
862 {
863 gas_assert (sel == MACH_SELECTION_FROM_COMMAND_LINE
864 || sel == MACH_SELECTION_FROM_CPU_DIRECTIVE);
865 if (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE
866 && selected_cpu.mach != cpu_types[i].mach)
867 {
868 as_warn (_("Command-line value overrides \".cpu\" directive"));
bb65a718 869 }
bb050a69 870 return;
bb65a718 871 }
bb050a69
CZ		 872 /* Initialise static global data about selected machine type. */
873 selected_cpu.flags = cpu_types[i].flags;
874 selected_cpu.name = cpu_types[i].name;
a9752fdf 875 selected_cpu.features = cpu_types[i].features | cl_features;
bb050a69 876 selected_cpu.mach = cpu_types[i].mach;
53a346d8
CZ		 877 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_MACH_MSK)
878 | cpu_types[i].eflags);
24740d83
AB		 879 break;
880 }
881 }
882
883 if (!cpu_types[i].name)
884 as_fatal (_("unknown architecture: %s\n"), arg);
bb050a69
CZ		 885
886 /* Check if set features are compatible with the chosen CPU. */
887 arc_check_feature ();
53a346d8 888
5e4f7e05
CZ		 889 /* If we change the CPU, we need to re-init the bfd. */
890 if (mach_selection_mode != MACH_SELECTION_NONE
891 && (old_cpu.mach != selected_cpu.mach))
892 {
893 bfd_find_target (arc_target_format, stdoutput);
894 if (! bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
895 as_warn (_("Could not set architecture and machine"));
896 }
897
bb65a718 898 mach_selection_mode = sel;
5e4f7e05 899 old_cpu = selected_cpu;
24740d83
AB		 900}
901
886a2506
NC		 902/* Here ends all the ARCompact extension instruction assembling
903 stuff. */
252b5132 904
886a2506
NC		 905static void
906arc_extra_reloc (int r_type)
ea1562b3 907{
886a2506
NC		 908 char *sym_name, c;
909 symbolS *sym, *lab = NULL;
910
911 if (*input_line_pointer == '@')
912 input_line_pointer++;
913 c = get_symbol_name (&sym_name);
914 sym = symbol_find_or_make (sym_name);
915 restore_line_pointer (c);
916 if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
917 {
918 ++input_line_pointer;
919 char *lab_name;
920 c = get_symbol_name (&lab_name);
921 lab = symbol_find_or_make (lab_name);
922 restore_line_pointer (c);
923 }
841fdfcd
CZ		 924
925 /* These relocations exist as a mechanism for the compiler to tell the
926 linker how to patch the code if the tls model is optimised. However,
927 the relocation itself does not require any space within the assembler
928 fragment, and so we pass a size of 0.
929
930 The lines that generate these relocations look like this:
931
932 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
933
934 The '.tls_gd_ld @.tdata' is processed first and generates the
935 additional relocation, while the 'bl __tls_get_addr@plt' is processed
936 second and generates the additional branch.
937
938 It is possible that the additional relocation generated by the
939 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
940 while the 'bl __tls_get_addr@plt' will be generated as the first thing
941 in the next fragment. This will be fine; both relocations will still
942 appear to be at the same address in the generated object file.
943 However, this only works as the additional relocation is generated
944 with size of 0 bytes. */
886a2506
NC		 945 fixS *fixP
946 = fix_new (frag_now, /* Which frag? */
947 frag_now_fix (), /* Where in that frag? */
841fdfcd 948 0, /* size: 1, 2, or 4 usually. */
886a2506
NC		 949 sym, /* X_add_symbol. */
950 0, /* X_add_number. */
951 FALSE, /* TRUE if PC-relative relocation. */
952 r_type /* Relocation type. */);
953 fixP->fx_subsy = lab;
954}
252b5132 955
886a2506
NC		 956static symbolS *
957arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
958 symbolS *symbolP, addressT size)
959{
960 addressT align = 0;
961 SKIP_WHITESPACE ();
252b5132 962
886a2506
NC		 963 if (*input_line_pointer == ',')
964 {
965 align = parse_align (1);
252b5132 966
886a2506
NC		 967 if (align == (addressT) -1)
968 return NULL;
969 }
970 else
971 {
972 if (size >= 8)
973 align = 3;
974 else if (size >= 4)
975 align = 2;
976 else if (size >= 2)
977 align = 1;
978 else
979 align = 0;
980 }
252b5132 981
886a2506
NC		 982 bss_alloc (symbolP, size, align);
983 S_CLEAR_EXTERNAL (symbolP);
ea1562b3 984
886a2506
NC		 985 return symbolP;
986}
ea1562b3 987
886a2506
NC		 988static void
989arc_lcomm (int ignore)
990{
991 symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
ea1562b3 992
886a2506
NC		 993 if (symbolP)
994 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
995}
ea1562b3 996
886a2506 997/* Select the cpu we're assembling for. */
ea1562b3 998
886a2506
NC		 999static void
1000arc_option (int ignore ATTRIBUTE_UNUSED)
252b5132 1001{
886a2506
NC		 1002 char c;
1003 char *cpu;
bb65a718 1004 const char *cpu_name;
252b5132 1005
886a2506 1006 c = get_symbol_name (&cpu);
252b5132 1007
a9752fdf 1008 cpu_name = cpu;
bb65a718
AB		 1009 if ((!strcmp ("ARC600", cpu))
1010 || (!strcmp ("ARC601", cpu))
1011 || (!strcmp ("A6", cpu)))
1012 cpu_name = "arc600";
1013 else if ((!strcmp ("ARC700", cpu))
1014 || (!strcmp ("A7", cpu)))
1015 cpu_name = "arc700";
1016 else if (!strcmp ("EM", cpu))
1017 cpu_name = "arcem";
1018 else if (!strcmp ("HS", cpu))
1019 cpu_name = "archs";
1020 else if (!strcmp ("NPS400", cpu))
1021 cpu_name = "nps400";
886a2506 1022
a9752fdf 1023 arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
24b368f8 1024
24b368f8 1025 restore_line_pointer (c);
886a2506 1026 demand_empty_rest_of_line ();
ea1562b3 1027}
252b5132 1028
886a2506
NC		 1029/* Smartly print an expression. */
1030
ea1562b3 1031static void
886a2506 1032debug_exp (expressionS *t)
ea1562b3 1033{
886a2506
NC		 1034 const char *name ATTRIBUTE_UNUSED;
1035 const char *namemd ATTRIBUTE_UNUSED;
252b5132 1036
886a2506 1037 pr_debug ("debug_exp: ");
252b5132 1038
886a2506 1039 switch (t->X_op)
252b5132 1040 {
886a2506
NC		 1041 default: name = "unknown"; break;
1042 case O_illegal: name = "O_illegal"; break;
1043 case O_absent: name = "O_absent"; break;
1044 case O_constant: name = "O_constant"; break;
1045 case O_symbol: name = "O_symbol"; break;
1046 case O_symbol_rva: name = "O_symbol_rva"; break;
1047 case O_register: name = "O_register"; break;
1048 case O_big: name = "O_big"; break;
1049 case O_uminus: name = "O_uminus"; break;
1050 case O_bit_not: name = "O_bit_not"; break;
1051 case O_logical_not: name = "O_logical_not"; break;
1052 case O_multiply: name = "O_multiply"; break;
1053 case O_divide: name = "O_divide"; break;
1054 case O_modulus: name = "O_modulus"; break;
1055 case O_left_shift: name = "O_left_shift"; break;
1056 case O_right_shift: name = "O_right_shift"; break;
1057 case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break;
1058 case O_bit_or_not: name = "O_bit_or_not"; break;
1059 case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break;
1060 case O_bit_and: name = "O_bit_and"; break;
1061 case O_add: name = "O_add"; break;
1062 case O_subtract: name = "O_subtract"; break;
1063 case O_eq: name = "O_eq"; break;
1064 case O_ne: name = "O_ne"; break;
1065 case O_lt: name = "O_lt"; break;
1066 case O_le: name = "O_le"; break;
1067 case O_ge: name = "O_ge"; break;
1068 case O_gt: name = "O_gt"; break;
1069 case O_logical_and: name = "O_logical_and"; break;
1070 case O_logical_or: name = "O_logical_or"; break;
1071 case O_index: name = "O_index"; break;
1072 case O_bracket: name = "O_bracket"; break;
db18dbab
GM		 1073 case O_colon: name = "O_colon"; break;
1074 case O_addrtype: name = "O_addrtype"; break;
ea1562b3 1075 }
252b5132 1076
886a2506 1077 switch (t->X_md)
ea1562b3 1078 {
886a2506
NC		 1079 default: namemd = "unknown"; break;
1080 case O_gotoff: namemd = "O_gotoff"; break;
1081 case O_gotpc: namemd = "O_gotpc"; break;
1082 case O_plt: namemd = "O_plt"; break;
1083 case O_sda: namemd = "O_sda"; break;
1084 case O_pcl: namemd = "O_pcl"; break;
1085 case O_tlsgd: namemd = "O_tlsgd"; break;
1086 case O_tlsie: namemd = "O_tlsie"; break;
1087 case O_tpoff9: namemd = "O_tpoff9"; break;
1088 case O_tpoff: namemd = "O_tpoff"; break;
1089 case O_dtpoff9: namemd = "O_dtpoff9"; break;
1090 case O_dtpoff: namemd = "O_dtpoff"; break;
ea1562b3 1091 }
252b5132 1092
886a2506
NC		 1093 pr_debug ("%s (%s, %s, %d, %s)", name,
1094 (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
1095 (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
1096 (int) t->X_add_number,
1097 (t->X_md) ? namemd : "--");
1098 pr_debug ("\n");
1099 fflush (stderr);
1100}
252b5132 1101
2a1ebfb2
CZ		 1102/* Helper for parsing an argument, used for sorting out the relocation
1103 type. */
1104
1105static void
1106parse_reloc_symbol (expressionS *resultP)
1107{
1108 char *reloc_name, c, *sym_name;
1109 size_t len;
1110 int i;
1111 const struct arc_reloc_op_tag *r;
1112 expressionS right;
1113 symbolS *base;
1114
1115 /* A relocation operand has the following form
1116 @identifier@relocation_type. The identifier is already in
1117 tok! */
1118 if (resultP->X_op != O_symbol)
1119 {
1120 as_bad (_("No valid label relocation operand"));
1121 resultP->X_op = O_illegal;
1122 return;
1123 }
1124
1125 /* Parse @relocation_type. */
1126 input_line_pointer++;
1127 c = get_symbol_name (&reloc_name);
1128 len = input_line_pointer - reloc_name;
1129 if (len == 0)
1130 {
1131 as_bad (_("No relocation operand"));
1132 resultP->X_op = O_illegal;
1133 return;
1134 }
1135
1136 /* Go through known relocation and try to find a match. */
1137 r = &arc_reloc_op[0];
1138 for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
1139 if (len == r->length
1140 && memcmp (reloc_name, r->name, len) == 0)
1141 break;
1142 if (i < 0)
1143 {
1144 as_bad (_("Unknown relocation operand: @%s"), reloc_name);
1145 resultP->X_op = O_illegal;
1146 return;
1147 }
1148
1149 *input_line_pointer = c;
1150 SKIP_WHITESPACE_AFTER_NAME ();
1151 /* Extra check for TLS: base. */
1152 if (*input_line_pointer == '@')
1153 {
1154 if (resultP->X_op_symbol != NULL
1155 || resultP->X_op != O_symbol)
1156 {
1157 as_bad (_("Unable to parse TLS base: %s"),
1158 input_line_pointer);
1159 resultP->X_op = O_illegal;
1160 return;
1161 }
1162 input_line_pointer++;
1163 c = get_symbol_name (&sym_name);
1164 base = symbol_find_or_make (sym_name);
1165 resultP->X_op = O_subtract;
1166 resultP->X_op_symbol = base;
1167 restore_line_pointer (c);
1168 right.X_add_number = 0;
1169 }
1170
1171 if ((*input_line_pointer != '+')
1172 && (*input_line_pointer != '-'))
1173 right.X_add_number = 0;
1174 else
1175 {
1176 /* Parse the constant of a complex relocation expression
1177 like @identifier@reloc +/- const. */
1178 if (! r->complex_expr)
1179 {
1180 as_bad (_("@%s is not a complex relocation."), r->name);
1181 resultP->X_op = O_illegal;
1182 return;
1183 }
1184 expression (&right);
1185 if (right.X_op != O_constant)
1186 {
1187 as_bad (_("Bad expression: @%s + %s."),
1188 r->name, input_line_pointer);
1189 resultP->X_op = O_illegal;
1190 return;
1191 }
1192 }
1193
1194 resultP->X_md = r->op;
1195 resultP->X_add_number = right.X_add_number;
1196}
1197
886a2506
NC		 1198/* Parse the arguments to an opcode. */
1199
1200static int
1201tokenize_arguments (char *str,
1202 expressionS *tok,
1203 int ntok)
1204{
1205 char *old_input_line_pointer;
1206 bfd_boolean saw_comma = FALSE;
1207 bfd_boolean saw_arg = FALSE;
1208 int brk_lvl = 0;
1209 int num_args = 0;
886a2506
NC		 1210
1211 memset (tok, 0, sizeof (*tok) * ntok);
1212
1213 /* Save and restore input_line_pointer around this function. */
1214 old_input_line_pointer = input_line_pointer;
1215 input_line_pointer = str;
ea1562b3 1216
886a2506 1217 while (*input_line_pointer)
ea1562b3
NC		 1218 {
1219 SKIP_WHITESPACE ();
886a2506 1220 switch (*input_line_pointer)
252b5132 1221 {
886a2506
NC		 1222 case '\0':
1223 goto fini;
1224
1225 case ',':
1226 input_line_pointer++;
1227 if (saw_comma || !saw_arg)
1228 goto err;
1229 saw_comma = TRUE;
1230 break;
252b5132 1231
886a2506
NC		 1232 case '}':
1233 case ']':
1234 ++input_line_pointer;
1235 --brk_lvl;
3b889a78 1236 if (!saw_arg || num_args == ntok)
886a2506
NC		 1237 goto err;
1238 tok->X_op = O_bracket;
1239 ++tok;
1240 ++num_args;
1241 break;
ea1562b3 1242
886a2506
NC		 1243 case '{':
1244 case '[':
1245 input_line_pointer++;
3b889a78 1246 if (brk_lvl || num_args == ntok)
886a2506
NC		 1247 goto err;
1248 ++brk_lvl;
1249 tok->X_op = O_bracket;
1250 ++tok;
1251 ++num_args;
1252 break;
1253
db18dbab
GM		 1254 case ':':
1255 input_line_pointer++;
1256 if (!saw_arg || num_args == ntok)
1257 goto err;
1258 tok->X_op = O_colon;
1259 saw_arg = FALSE;
1260 ++tok;
1261 ++num_args;
1262 break;
1263
886a2506
NC		 1264 case '@':
1265 /* We have labels, function names and relocations, all
1266 starting with @ symbol. Sort them out. */
3b889a78 1267 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506
NC		 1268 goto err;
1269
1270 /* Parse @label. */
2a1ebfb2 1271 input_line_pointer++;
886a2506
NC		 1272 tok->X_op = O_symbol;
1273 tok->X_md = O_absent;
1274 expression (tok);
886a2506 1275
886a2506 1276 if (*input_line_pointer == '@')
2a1ebfb2 1277 parse_reloc_symbol (tok);
1e07b820 1278
886a2506 1279 debug_exp (tok);
ea1562b3 1280
2a1ebfb2
CZ		 1281 if (tok->X_op == O_illegal
1282 || tok->X_op == O_absent
1283 || num_args == ntok)
1284 goto err;
1285
886a2506
NC		 1286 saw_comma = FALSE;
1287 saw_arg = TRUE;
1288 tok++;
1289 num_args++;
1290 break;
252b5132 1291
886a2506
NC		 1292 case '%':
1293 /* Can be a register. */
1294 ++input_line_pointer;
1295 /* Fall through. */
1296 default:
252b5132 1297
3b889a78 1298 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506 1299 goto err;
252b5132 1300
886a2506 1301 tok->X_op = O_absent;
6f4b1afc 1302 tok->X_md = O_absent;
886a2506 1303 expression (tok);
252b5132 1304
6f4b1afc
CM		 1305 /* Legacy: There are cases when we have
1306 identifier@relocation_type, if it is the case parse the
1307 relocation type as well. */
1308 if (*input_line_pointer == '@')
2a1ebfb2 1309 parse_reloc_symbol (tok);
6f4b1afc 1310
886a2506 1311 debug_exp (tok);
252b5132 1312
3b889a78
AB		 1313 if (tok->X_op == O_illegal
1314 || tok->X_op == O_absent
1315 || num_args == ntok)
886a2506 1316 goto err;
252b5132 1317
886a2506
NC		 1318 saw_comma = FALSE;
1319 saw_arg = TRUE;
1320 tok++;
1321 num_args++;
1322 break;
1323 }
ea1562b3 1324 }
252b5132 1325
886a2506
NC		 1326 fini:
1327 if (saw_comma || brk_lvl)
1328 goto err;
1329 input_line_pointer = old_input_line_pointer;
252b5132 1330
886a2506 1331 return num_args;
252b5132 1332
886a2506
NC		 1333 err:
1334 if (brk_lvl)
1335 as_bad (_("Brackets in operand field incorrect"));
1336 else if (saw_comma)
1337 as_bad (_("extra comma"));
1338 else if (!saw_arg)
1339 as_bad (_("missing argument"));
1340 else
1341 as_bad (_("missing comma or colon"));
1342 input_line_pointer = old_input_line_pointer;
1343 return -1;
252b5132 1344}
ea1562b3 1345
886a2506
NC		 1346/* Parse the flags to a structure. */
1347
1348static int
1349tokenize_flags (const char *str,
1350 struct arc_flags flags[],
1351 int nflg)
252b5132 1352{
886a2506
NC		 1353 char *old_input_line_pointer;
1354 bfd_boolean saw_flg = FALSE;
1355 bfd_boolean saw_dot = FALSE;
1356 int num_flags = 0;
1357 size_t flgnamelen;
252b5132 1358
886a2506 1359 memset (flags, 0, sizeof (*flags) * nflg);
0d2bcfaf 1360
886a2506
NC		 1361 /* Save and restore input_line_pointer around this function. */
1362 old_input_line_pointer = input_line_pointer;
1363 input_line_pointer = (char *) str;
0d2bcfaf 1364
886a2506
NC		 1365 while (*input_line_pointer)
1366 {
1367 switch (*input_line_pointer)
1368 {
1369 case ' ':
1370 case '\0':
1371 goto fini;
1372
1373 case '.':
1374 input_line_pointer++;
1375 if (saw_dot)
1376 goto err;
1377 saw_dot = TRUE;
1378 saw_flg = FALSE;
1379 break;
ea1562b3 1380
886a2506
NC		 1381 default:
1382 if (saw_flg && !saw_dot)
1383 goto err;
0d2bcfaf 1384
886a2506
NC		 1385 if (num_flags >= nflg)
1386 goto err;
0d2bcfaf 1387
692166c2
AB		 1388 flgnamelen = strspn (input_line_pointer,
1389 "abcdefghijklmnopqrstuvwxyz0123456789");
83cda17b 1390 if (flgnamelen > MAX_FLAG_NAME_LENGTH)
886a2506 1391 goto err;
0d2bcfaf 1392
886a2506 1393 memcpy (flags->name, input_line_pointer, flgnamelen);
0d2bcfaf 1394
886a2506
NC		 1395 input_line_pointer += flgnamelen;
1396 flags++;
1397 saw_dot = FALSE;
1398 saw_flg = TRUE;
1399 num_flags++;
1400 break;
1e07b820 1401 }
0d2bcfaf
NC		 1402 }
1403
886a2506
NC		 1404 fini:
1405 input_line_pointer = old_input_line_pointer;
1406 return num_flags;
0d2bcfaf 1407
886a2506
NC		 1408 err:
1409 if (saw_dot)
1410 as_bad (_("extra dot"));
1411 else if (!saw_flg)
1412 as_bad (_("unrecognized flag"));
1413 else
1414 as_bad (_("failed to parse flags"));
1415 input_line_pointer = old_input_line_pointer;
1416 return -1;
1417}
0d2bcfaf 1418
4670103e 1419/* Apply the fixups in order. */
0d2bcfaf 1420
4670103e
CZ		 1421static void
1422apply_fixups (struct arc_insn *insn, fragS *fragP, int fix)
886a2506 1423{
4670103e 1424 int i;
0d2bcfaf 1425
4670103e 1426 for (i = 0; i < insn->nfixups; i++)
252b5132 1427 {
4670103e
CZ		 1428 struct arc_fixup *fixup = &insn->fixups[i];
1429 int size, pcrel, offset = 0;
0d2bcfaf 1430
4670103e
CZ		 1431 /* FIXME! the reloc size is wrong in the BFD file.
1432 When it is fixed please delete me. */
91fdca6f 1433 size = ((insn->len == 2) && !fixup->islong) ? 2 : 4;
0d2bcfaf 1434
4670103e 1435 if (fixup->islong)
91fdca6f 1436 offset = insn->len;
252b5132 1437
4670103e
CZ		 1438 /* Some fixups are only used internally, thus no howto. */
1439 if ((int) fixup->reloc == 0)
1440 as_fatal (_("Unhandled reloc type"));
886a2506 1441
4670103e
CZ		 1442 if ((int) fixup->reloc < 0)
1443 {
1444 /* FIXME! the reloc size is wrong in the BFD file.
1445 When it is fixed please enable me.
91fdca6f 1446 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
4670103e
CZ		 1447 pcrel = fixup->pcrel;
1448 }
1449 else
1450 {
1451 reloc_howto_type *reloc_howto =
1452 bfd_reloc_type_lookup (stdoutput,
1453 (bfd_reloc_code_real_type) fixup->reloc);
1454 gas_assert (reloc_howto);
0d2bcfaf 1455
4670103e
CZ		 1456 /* FIXME! the reloc size is wrong in the BFD file.
1457 When it is fixed please enable me.
1458 size = bfd_get_reloc_size (reloc_howto); */
1459 pcrel = reloc_howto->pc_relative;
1460 }
0d2bcfaf 1461
4670103e
CZ		 1462 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1463offset %d + %d\n",
1464 fragP->fr_file, fragP->fr_line,
1465 (fixup->reloc < 0) ? "Internal" :
1466 bfd_get_reloc_code_name (fixup->reloc),
1467 pcrel ? "Y" : "N",
1468 size, fix, offset);
1469 fix_new_exp (fragP, fix + offset,
1470 size, &fixup->exp, pcrel, fixup->reloc);
0d2bcfaf 1471
4670103e
CZ		 1472 /* Check for ZOLs, and update symbol info if any. */
1473 if (LP_INSN (insn->insn))
886a2506 1474 {
4670103e
CZ		 1475 gas_assert (fixup->exp.X_add_symbol);
1476 ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
886a2506
NC		 1477 }
1478 }
252b5132
RH		 1479}
1480
4670103e 1481/* Actually output an instruction with its fixup. */
886a2506 1482
4670103e
CZ		 1483static void
1484emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax)
252b5132 1485{
4670103e 1486 char *f = where;
91fdca6f 1487 size_t total_len;
252b5132 1488
bdfe53e3
AB		 1489 pr_debug ("Emit insn : 0x%llx\n", insn->insn);
1490 pr_debug ("\tLength : 0x%d\n", insn->len);
4670103e 1491 pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
0d2bcfaf 1492
4670103e 1493 /* Write out the instruction. */
91fdca6f
GM		 1494 total_len = insn->len + (insn->has_limm ? 4 : 0);
1495 if (!relax)
1496 f = frag_more (total_len);
1497
1498 md_number_to_chars_midend(f, insn->insn, insn->len);
1499
1500 if (insn->has_limm)
1501 md_number_to_chars_midend (f + insn->len, insn->limm, 4);
1502 dwarf2_emit_insn (total_len);
252b5132 1503
4670103e
CZ		 1504 if (!relax)
1505 apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
1506}
252b5132 1507
4670103e
CZ		 1508static void
1509emit_insn1 (struct arc_insn *insn)
1510{
1511 /* How frag_var's args are currently configured:
1512 - rs_machine_dependent, to dictate it's a relaxation frag.
1513 - FRAG_MAX_GROWTH, maximum size of instruction
1514 - 0, variable size that might grow...unused by generic relaxation.
1515 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1516 - s, opand expression.
1517 - 0, offset but it's unused.
1518 - 0, opcode but it's unused. */
1519 symbolS *s = make_expr_symbol (&insn->fixups[0].exp);
1520 frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel;
1521
1522 if (frag_room () < FRAG_MAX_GROWTH)
1523 {
1524 /* Handle differently when frag literal memory is exhausted.
1525 This is used because when there's not enough memory left in
1526 the current frag, a new frag is created and the information
1527 we put into frag_now->tc_frag_data is disregarded. */
252b5132 1528
4670103e
CZ		 1529 struct arc_relax_type relax_info_copy;
1530 relax_substateT subtype = frag_now->fr_subtype;
252b5132 1531
4670103e
CZ		 1532 memcpy (&relax_info_copy, &frag_now->tc_frag_data,
1533 sizeof (struct arc_relax_type));
0d2bcfaf 1534
4670103e
CZ		 1535 frag_wane (frag_now);
1536 frag_grow (FRAG_MAX_GROWTH);
0d2bcfaf 1537
4670103e
CZ		 1538 memcpy (&frag_now->tc_frag_data, &relax_info_copy,
1539 sizeof (struct arc_relax_type));
252b5132 1540
4670103e
CZ		 1541 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1542 subtype, s, 0, 0);
1543 }
1544 else
1545 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1546 frag_now->fr_subtype, s, 0, 0);
1547}
252b5132 1548
4670103e
CZ		 1549static void
1550emit_insn (struct arc_insn *insn)
252b5132 1551{
4670103e
CZ		 1552 if (insn->relax)
1553 emit_insn1 (insn);
252b5132 1554 else
4670103e 1555 emit_insn0 (insn, NULL, FALSE);
252b5132
RH		 1556}
1557
4670103e 1558/* Check whether a symbol involves a register. */
252b5132 1559
4670103e
CZ		 1560static bfd_boolean
1561contains_register (symbolS *sym)
252b5132 1562{
4670103e
CZ		 1563 if (sym)
1564 {
1565 expressionS *ex = symbol_get_value_expression (sym);
252b5132 1566
4670103e
CZ		 1567 return ((O_register == ex->X_op)
1568 && !contains_register (ex->X_add_symbol)
1569 && !contains_register (ex->X_op_symbol));
1570 }
1571
1572 return FALSE;
252b5132
RH		 1573}
1574
4670103e 1575/* Returns the register number within a symbol. */
252b5132 1576
4670103e
CZ		 1577static int
1578get_register (symbolS *sym)
252b5132 1579{
4670103e
CZ		 1580 if (!contains_register (sym))
1581 return -1;
0d2bcfaf 1582
4670103e
CZ		 1583 expressionS *ex = symbol_get_value_expression (sym);
1584 return regno (ex->X_add_number);
1585}
252b5132 1586
4670103e
CZ		 1587/* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1588 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
f17c130b 1589
4670103e
CZ		 1590static bfd_boolean
1591generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
1592{
1593 if (!reloc)
1594 return FALSE;
886a2506 1595
4670103e
CZ		 1596 switch (reloc)
1597 {
1598 case BFD_RELOC_ARC_SDA_LDST:
1599 case BFD_RELOC_ARC_SDA_LDST1:
1600 case BFD_RELOC_ARC_SDA_LDST2:
1601 case BFD_RELOC_ARC_SDA16_LD:
1602 case BFD_RELOC_ARC_SDA16_LD1:
1603 case BFD_RELOC_ARC_SDA16_LD2:
1604 case BFD_RELOC_ARC_SDA16_ST2:
1605 case BFD_RELOC_ARC_SDA32_ME:
1606 return FALSE;
1607 default:
1608 return TRUE;
f17c130b 1609 }
252b5132
RH		 1610}
1611
4670103e 1612/* Allocates a tok entry. */
252b5132 1613
4670103e
CZ		 1614static int
1615allocate_tok (expressionS *tok, int ntok, int cidx)
252b5132 1616{
4670103e
CZ		 1617 if (ntok > MAX_INSN_ARGS - 2)
1618 return 0; /* No space left. */
252b5132 1619
4670103e 1620 if (cidx > ntok)
33eaf5de 1621 return 0; /* Incorrect args. */
252b5132 1622
4670103e 1623 memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
252b5132 1624
4670103e
CZ		 1625 if (cidx == ntok)
1626 return 1; /* Success. */
1627 return allocate_tok (tok, ntok - 1, cidx);
1628}
886a2506 1629
8ddf6b2a
CZ		 1630/* Check if an particular ARC feature is enabled. */
1631
1632static bfd_boolean
1633check_cpu_feature (insn_subclass_t sc)
1634{
53a346d8 1635 if (is_code_density_p (sc) && !(selected_cpu.features & CD))
8ddf6b2a
CZ		 1636 return FALSE;
1637
53a346d8 1638 if (is_spfp_p (sc) && !(selected_cpu.features & SPX))
8ddf6b2a
CZ		 1639 return FALSE;
1640
53a346d8 1641 if (is_dpfp_p (sc) && !(selected_cpu.features & DPX))
8ddf6b2a
CZ		 1642 return FALSE;
1643
53a346d8 1644 if (is_fpuda_p (sc) && !(selected_cpu.features & DPA))
bdd582db
GM		 1645 return FALSE;
1646
53a346d8 1647 if (is_nps400_p (sc) && !(selected_cpu.features & NPS400))
8ddf6b2a
CZ		 1648 return FALSE;
1649
1650 return TRUE;
1651}
1652
4eb6f892
AB		 1653/* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1654 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1655 array and returns TRUE if the flag operands all match, otherwise,
1656 returns FALSE, in which case the FIRST_PFLAG array may have been
1657 modified. */
1658
1659static bfd_boolean
1660parse_opcode_flags (const struct arc_opcode *opcode,
1661 int nflgs,
1662 struct arc_flags *first_pflag)
1663{
1664 int lnflg, i;
1665 const unsigned char *flgidx;
1666
1667 lnflg = nflgs;
1668 for (i = 0; i < nflgs; i++)
1669 first_pflag[i].flgp = NULL;
1670
1671 /* Check the flags. Iterate over the valid flag classes. */
1672 for (flgidx = opcode->flags; *flgidx; ++flgidx)
1673 {
1674 /* Get a valid flag class. */
1675 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
1676 const unsigned *flgopridx;
1677 int cl_matches = 0;
1678 struct arc_flags *pflag = NULL;
1679
6ec7c1ae
CZ		 1680 /* Check if opcode has implicit flag classes. */
1681 if (cl_flags->flag_class & F_CLASS_IMPLICIT)
1682 continue;
1683
4eb6f892
AB		 1684 /* Check for extension conditional codes. */
1685 if (ext_condcode.arc_ext_condcode
1686 && cl_flags->flag_class & F_CLASS_EXTEND)
1687 {
1688 struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode;
1689 while (pf->name)
1690 {
1691 pflag = first_pflag;
1692 for (i = 0; i < nflgs; i++, pflag++)
1693 {
1694 if (!strcmp (pf->name, pflag->name))
1695 {
1696 if (pflag->flgp != NULL)
1697 return FALSE;
1698 /* Found it. */
1699 cl_matches++;
1700 pflag->flgp = pf;
1701 lnflg--;
1702 break;
1703 }
1704 }
1705 pf++;
1706 }
1707 }
1708
1709 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
1710 {
1711 const struct arc_flag_operand *flg_operand;
1712
1713 pflag = first_pflag;
1714 flg_operand = &arc_flag_operands[*flgopridx];
1715 for (i = 0; i < nflgs; i++, pflag++)
1716 {
1717 /* Match against the parsed flags. */
1718 if (!strcmp (flg_operand->name, pflag->name))
1719 {
1720 if (pflag->flgp != NULL)
1721 return FALSE;
1722 cl_matches++;
1723 pflag->flgp = flg_operand;
1724 lnflg--;
1725 break; /* goto next flag class and parsed flag. */
1726 }
1727 }
1728 }
1729
1730 if ((cl_flags->flag_class & F_CLASS_REQUIRED) && cl_matches == 0)
1731 return FALSE;
1732 if ((cl_flags->flag_class & F_CLASS_OPTIONAL) && cl_matches > 1)
1733 return FALSE;
1734 }
1735
1736 /* Did I check all the parsed flags? */
1737 return lnflg ? FALSE : TRUE;
1738}
1739
1740
4670103e
CZ		 1741/* Search forward through all variants of an opcode looking for a
1742 syntax match. */
886a2506 1743
4670103e 1744static const struct arc_opcode *
b9b47ab7 1745find_opcode_match (const struct arc_opcode_hash_entry *entry,
4670103e
CZ		 1746 expressionS *tok,
1747 int *pntok,
1748 struct arc_flags *first_pflag,
1749 int nflgs,
abe7c33b
CZ		 1750 int *pcpumatch,
1751 const char **errmsg)
4670103e 1752{
1328504b
AB		 1753 const struct arc_opcode *opcode;
1754 struct arc_opcode_hash_entry_iterator iter;
4670103e
CZ		 1755 int ntok = *pntok;
1756 int got_cpu_match = 0;
1757 expressionS bktok[MAX_INSN_ARGS];
3128916d 1758 int bkntok, maxerridx = 0;
4670103e 1759 expressionS emptyE;
3128916d 1760 const char *tmpmsg = NULL;
886a2506 1761
1328504b 1762 arc_opcode_hash_entry_iterator_init (&iter);
4670103e
CZ		 1763 memset (&emptyE, 0, sizeof (emptyE));
1764 memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
1765 bkntok = ntok;
a161fe53 1766
1328504b
AB		 1767 for (opcode = arc_opcode_hash_entry_iterator_next (entry, &iter);
1768 opcode != NULL;
1769 opcode = arc_opcode_hash_entry_iterator_next (entry, &iter))
252b5132 1770 {
4670103e 1771 const unsigned char *opidx;
4eb6f892 1772 int tokidx = 0;
4670103e 1773 const expressionS *t = &emptyE;
252b5132 1774
bdfe53e3 1775 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
4670103e 1776 frag_now->fr_file, frag_now->fr_line, opcode->opcode);
886a2506 1777
4670103e
CZ		 1778 /* Don't match opcodes that don't exist on this
1779 architecture. */
bb65a718 1780 if (!(opcode->cpu & selected_cpu.flags))
4670103e 1781 goto match_failed;
886a2506 1782
8ddf6b2a 1783 if (!check_cpu_feature (opcode->subclass))
4670103e 1784 goto match_failed;
886a2506 1785
4670103e
CZ		 1786 got_cpu_match = 1;
1787 pr_debug ("cpu ");
886a2506 1788
4670103e
CZ		 1789 /* Check the operands. */
1790 for (opidx = opcode->operands; *opidx; ++opidx)
252b5132 1791 {
4670103e 1792 const struct arc_operand *operand = &arc_operands[*opidx];
252b5132 1793
4670103e 1794 /* Only take input from real operands. */
db18dbab 1795 if (ARC_OPERAND_IS_FAKE (operand))
4670103e 1796 continue;
252b5132 1797
4670103e
CZ		 1798 /* When we expect input, make sure we have it. */
1799 if (tokidx >= ntok)
1800 goto match_failed;
6f4b1afc 1801
4670103e
CZ		 1802 /* Match operand type with expression type. */
1803 switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
1804 {
db18dbab 1805 case ARC_OPERAND_ADDRTYPE:
b437d035 1806 {
3128916d 1807 tmpmsg = NULL;
b437d035
AB		 1808
1809 /* Check to be an address type. */
1810 if (tok[tokidx].X_op != O_addrtype)
1811 goto match_failed;
1812
1813 /* All address type operands need to have an insert
1814 method in order to check that we have the correct
1815 address type. */
1816 gas_assert (operand->insert != NULL);
1817 (*operand->insert) (0, tok[tokidx].X_add_number,
3128916d
CZ		 1818 &tmpmsg);
1819 if (tmpmsg != NULL)
b437d035
AB		 1820 goto match_failed;
1821 }
db18dbab
GM		 1822 break;
1823
4670103e
CZ		 1824 case ARC_OPERAND_IR:
1825 /* Check to be a register. */
1826 if ((tok[tokidx].X_op != O_register
1827 || !is_ir_num (tok[tokidx].X_add_number))
1828 && !(operand->flags & ARC_OPERAND_IGNORE))
1829 goto match_failed;
1830
1831 /* If expect duplicate, make sure it is duplicate. */
1832 if (operand->flags & ARC_OPERAND_DUPLICATE)
1833 {
1834 /* Check for duplicate. */
1835 if (t->X_op != O_register
1836 || !is_ir_num (t->X_add_number)
1837 || (regno (t->X_add_number) !=
1838 regno (tok[tokidx].X_add_number)))
1839 goto match_failed;
1840 }
1841
1842 /* Special handling? */
1843 if (operand->insert)
1844 {
3128916d 1845 tmpmsg = NULL;
4670103e
CZ		 1846 (*operand->insert)(0,
1847 regno (tok[tokidx].X_add_number),
3128916d
CZ		 1848 &tmpmsg);
1849 if (tmpmsg)
4670103e
CZ		 1850 {
1851 if (operand->flags & ARC_OPERAND_IGNORE)
1852 {
1853 /* Missing argument, create one. */
1854 if (!allocate_tok (tok, ntok - 1, tokidx))
1855 goto match_failed;
1856
1857 tok[tokidx].X_op = O_absent;
1858 ++ntok;
1859 }
1860 else
1861 goto match_failed;
1862 }
1863 }
1864
1865 t = &tok[tokidx];
1866 break;
1867
1868 case ARC_OPERAND_BRAKET:
1869 /* Check if bracket is also in opcode table as
1870 operand. */
1871 if (tok[tokidx].X_op != O_bracket)
1872 goto match_failed;
1873 break;
1874
db18dbab
GM		 1875 case ARC_OPERAND_COLON:
1876 /* Check if colon is also in opcode table as operand. */
1877 if (tok[tokidx].X_op != O_colon)
1878 goto match_failed;
1879 break;
1880
4670103e
CZ		 1881 case ARC_OPERAND_LIMM:
1882 case ARC_OPERAND_SIGNED:
1883 case ARC_OPERAND_UNSIGNED:
1884 switch (tok[tokidx].X_op)
1885 {
1886 case O_illegal:
1887 case O_absent:
1888 case O_register:
1889 goto match_failed;
1890
1891 case O_bracket:
1892 /* Got an (too) early bracket, check if it is an
1893 ignored operand. N.B. This procedure works only
1894 when bracket is the last operand! */
1895 if (!(operand->flags & ARC_OPERAND_IGNORE))
1896 goto match_failed;
1897 /* Insert the missing operand. */
1898 if (!allocate_tok (tok, ntok - 1, tokidx))
1899 goto match_failed;
1900
1901 tok[tokidx].X_op = O_absent;
1902 ++ntok;
1903 break;
1904
22b92fc4
AB		 1905 case O_symbol:
1906 {
1907 const char *p;
b6523c37 1908 char *tmpp, *pp;
22b92fc4 1909 const struct arc_aux_reg *auxr;
22b92fc4 1910
c810e0b8 1911 if (opcode->insn_class != AUXREG)
22b92fc4
AB		 1912 goto de_fault;
1913 p = S_GET_NAME (tok[tokidx].X_add_symbol);
f36e33da 1914
b6523c37 1915 /* For compatibility reasons, an aux register can
1916 be spelled with upper or lower case
1917 letters. */
1918 tmpp = strdup (p);
1919 for (pp = tmpp; *pp; ++pp) *pp = TOLOWER (*pp);
1920
629310ab 1921 auxr = str_hash_find (arc_aux_hash, tmpp);
f36e33da
CZ		 1922 if (auxr)
1923 {
1924 /* We modify the token array here, safe in the
1925 knowledge, that if this was the wrong
1926 choice then the original contents will be
1927 restored from BKTOK. */
1928 tok[tokidx].X_op = O_constant;
1929 tok[tokidx].X_add_number = auxr->address;
1930 ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
1931 }
b6523c37 1932 free (tmpp);
22b92fc4
AB		 1933
1934 if (tok[tokidx].X_op != O_constant)
1935 goto de_fault;
1936 }
1a0670f3 1937 /* Fall through. */
4670103e
CZ		 1938 case O_constant:
1939 /* Check the range. */
1940 if (operand->bits != 32
1941 && !(operand->flags & ARC_OPERAND_NCHK))
1942 {
1943 offsetT min, max, val;
1944 val = tok[tokidx].X_add_number;
1945
1946 if (operand->flags & ARC_OPERAND_SIGNED)
1947 {
1948 max = (1 << (operand->bits - 1)) - 1;
1949 min = -(1 << (operand->bits - 1));
1950 }
1951 else
1952 {
1953 max = (1 << operand->bits) - 1;
1954 min = 0;
1955 }
1956
1957 if (val < min || val > max)
3128916d
CZ		 1958 {
1959 tmpmsg = _("immediate is out of bounds");
1960 goto match_failed;
1961 }
4670103e 1962
33eaf5de 1963 /* Check alignments. */
4670103e
CZ		 1964 if ((operand->flags & ARC_OPERAND_ALIGNED32)
1965 && (val & 0x03))
3128916d
CZ		 1966 {
1967 tmpmsg = _("immediate is not 32bit aligned");
1968 goto match_failed;
1969 }
4670103e
CZ		 1970
1971 if ((operand->flags & ARC_OPERAND_ALIGNED16)
1972 && (val & 0x01))
3128916d
CZ		 1973 {
1974 tmpmsg = _("immediate is not 16bit aligned");
1975 goto match_failed;
1976 }
4670103e
CZ		 1977 }
1978 else if (operand->flags & ARC_OPERAND_NCHK)
1979 {
1980 if (operand->insert)
1981 {
3128916d 1982 tmpmsg = NULL;
4670103e
CZ		 1983 (*operand->insert)(0,
1984 tok[tokidx].X_add_number,
3128916d
CZ		 1985 &tmpmsg);
1986 if (tmpmsg)
4670103e
CZ		 1987 goto match_failed;
1988 }
4eb6f892 1989 else if (!(operand->flags & ARC_OPERAND_IGNORE))
4670103e
CZ		 1990 goto match_failed;
1991 }
1992 break;
1993
1994 case O_subtract:
1995 /* Check if it is register range. */
1996 if ((tok[tokidx].X_add_number == 0)
1997 && contains_register (tok[tokidx].X_add_symbol)
1998 && contains_register (tok[tokidx].X_op_symbol))
1999 {
2000 int regs;
2001
2002 regs = get_register (tok[tokidx].X_add_symbol);
2003 regs <<= 16;
2004 regs |= get_register (tok[tokidx].X_op_symbol);
2005 if (operand->insert)
2006 {
3128916d 2007 tmpmsg = NULL;
4670103e
CZ		 2008 (*operand->insert)(0,
2009 regs,
3128916d
CZ		 2010 &tmpmsg);
2011 if (tmpmsg)
4670103e
CZ		 2012 goto match_failed;
2013 }
2014 else
2015 goto match_failed;
2016 break;
2017 }
1a0670f3 2018 /* Fall through. */
4670103e 2019 default:
22b92fc4 2020 de_fault:
4670103e
CZ		 2021 if (operand->default_reloc == 0)
2022 goto match_failed; /* The operand needs relocation. */
2023
2024 /* Relocs requiring long immediate. FIXME! make it
2025 generic and move it to a function. */
2026 switch (tok[tokidx].X_md)
2027 {
2028 case O_gotoff:
2029 case O_gotpc:
2030 case O_pcl:
2031 case O_tpoff:
2032 case O_dtpoff:
2033 case O_tlsgd:
2034 case O_tlsie:
2035 if (!(operand->flags & ARC_OPERAND_LIMM))
2036 goto match_failed;
1a0670f3 2037 /* Fall through. */
4670103e
CZ		 2038 case O_absent:
2039 if (!generic_reloc_p (operand->default_reloc))
2040 goto match_failed;
2b804145 2041 break;
4670103e
CZ		 2042 default:
2043 break;
2044 }
2045 break;
2046 }
2047 /* If expect duplicate, make sure it is duplicate. */
2048 if (operand->flags & ARC_OPERAND_DUPLICATE)
2049 {
2050 if (t->X_op == O_illegal
2051 || t->X_op == O_absent
2052 || t->X_op == O_register
2053 || (t->X_add_number != tok[tokidx].X_add_number))
3128916d
CZ		 2054 {
2055 tmpmsg = _("operand is not duplicate of the "
2056 "previous one");
2057 goto match_failed;
2058 }
4670103e
CZ		 2059 }
2060 t = &tok[tokidx];
2061 break;
2062
2063 default:
2064 /* Everything else should have been fake. */
2065 abort ();
2066 }
2067
2068 ++tokidx;
2069 }
2070 pr_debug ("opr ");
2071
1ae8ab47 2072 /* Setup ready for flag parsing. */
4eb6f892 2073 if (!parse_opcode_flags (opcode, nflgs, first_pflag))
3128916d
CZ		 2074 {
2075 tmpmsg = _("flag mismatch");
2076 goto match_failed;
2077 }
4670103e
CZ		 2078
2079 pr_debug ("flg");
2080 /* Possible match -- did we use all of our input? */
2081 if (tokidx == ntok)
2082 {
2083 *pntok = ntok;
2084 pr_debug ("\n");
2085 return opcode;
2086 }
3128916d 2087 tmpmsg = _("too many arguments");
4670103e
CZ		 2088
2089 match_failed:;
2090 pr_debug ("\n");
2091 /* Restore the original parameters. */
2092 memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
2093 ntok = bkntok;
3128916d
CZ		 2094 if (tokidx >= maxerridx
2095 && tmpmsg)
2096 {
2097 maxerridx = tokidx;
2098 *errmsg = tmpmsg;
2099 }
4670103e 2100 }
4670103e
CZ		 2101
2102 if (*pcpumatch)
2103 *pcpumatch = got_cpu_match;
2104
2105 return NULL;
2106}
2107
2108/* Swap operand tokens. */
2109
2110static void
2111swap_operand (expressionS *operand_array,
2112 unsigned source,
2113 unsigned destination)
2114{
2115 expressionS cpy_operand;
2116 expressionS *src_operand;
2117 expressionS *dst_operand;
2118 size_t size;
2119
2120 if (source == destination)
2121 return;
2122
2123 src_operand = &operand_array[source];
2124 dst_operand = &operand_array[destination];
2125 size = sizeof (expressionS);
2126
2127 /* Make copy of operand to swap with and swap. */
2128 memcpy (&cpy_operand, dst_operand, size);
2129 memcpy (dst_operand, src_operand, size);
2130 memcpy (src_operand, &cpy_operand, size);
2131}
2132
2133/* Check if *op matches *tok type.
2134 Returns FALSE if they don't match, TRUE if they match. */
2135
2136static bfd_boolean
2137pseudo_operand_match (const expressionS *tok,
2138 const struct arc_operand_operation *op)
2139{
2140 offsetT min, max, val;
2141 bfd_boolean ret;
2142 const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
2143
2144 ret = FALSE;
2145 switch (tok->X_op)
2146 {
2147 case O_constant:
2148 if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
2149 ret = 1;
2150 else if (!(operand_real->flags & ARC_OPERAND_IR))
2151 {
2152 val = tok->X_add_number + op->count;
2153 if (operand_real->flags & ARC_OPERAND_SIGNED)
2154 {
2155 max = (1 << (operand_real->bits - 1)) - 1;
2156 min = -(1 << (operand_real->bits - 1));
2157 }
2158 else
2159 {
2160 max = (1 << operand_real->bits) - 1;
2161 min = 0;
2162 }
2163 if (min <= val && val <= max)
2164 ret = TRUE;
2165 }
6f4b1afc
CM		 2166 break;
2167
4670103e
CZ		 2168 case O_symbol:
2169 /* Handle all symbols as long immediates or signed 9. */
db18dbab
GM		 2170 if (operand_real->flags & ARC_OPERAND_LIMM
2171 || ((operand_real->flags & ARC_OPERAND_SIGNED)
2172 && operand_real->bits == 9))
4670103e 2173 ret = TRUE;
6f4b1afc
CM		 2174 break;
2175
4670103e
CZ		 2176 case O_register:
2177 if (operand_real->flags & ARC_OPERAND_IR)
2178 ret = TRUE;
2179 break;
2180
2181 case O_bracket:
2182 if (operand_real->flags & ARC_OPERAND_BRAKET)
2183 ret = TRUE;
6f4b1afc
CM		 2184 break;
2185
2186 default:
4670103e 2187 /* Unknown. */
6f4b1afc
CM		 2188 break;
2189 }
4670103e
CZ		 2190 return ret;
2191}
6f4b1afc 2192
4670103e
CZ		 2193/* Find pseudo instruction in array. */
2194
2195static const struct arc_pseudo_insn *
2196find_pseudo_insn (const char *opname,
2197 int ntok,
2198 const expressionS *tok)
2199{
2200 const struct arc_pseudo_insn *pseudo_insn = NULL;
2201 const struct arc_operand_operation *op;
2202 unsigned int i;
2203 int j;
2204
2205 for (i = 0; i < arc_num_pseudo_insn; ++i)
6f4b1afc 2206 {
4670103e
CZ		 2207 pseudo_insn = &arc_pseudo_insns[i];
2208 if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
2209 {
2210 op = pseudo_insn->operand;
2211 for (j = 0; j < ntok; ++j)
2212 if (!pseudo_operand_match (&tok[j], &op[j]))
2213 break;
2214
2215 /* Found the right instruction. */
2216 if (j == ntok)
2217 return pseudo_insn;
2218 }
6f4b1afc 2219 }
4670103e
CZ		 2220 return NULL;
2221}
252b5132 2222
4670103e 2223/* Assumes the expressionS *tok is of sufficient size. */
252b5132 2224
b9b47ab7 2225static const struct arc_opcode_hash_entry *
4670103e
CZ		 2226find_special_case_pseudo (const char *opname,
2227 int *ntok,
2228 expressionS *tok,
2229 int *nflgs,
2230 struct arc_flags *pflags)
2231{
2232 const struct arc_pseudo_insn *pseudo_insn = NULL;
2233 const struct arc_operand_operation *operand_pseudo;
2234 const struct arc_operand *operand_real;
2235 unsigned i;
2236 char construct_operand[MAX_CONSTR_STR];
886a2506 2237
4670103e
CZ		 2238 /* Find whether opname is in pseudo instruction array. */
2239 pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
2240
2241 if (pseudo_insn == NULL)
2242 return NULL;
2243
2244 /* Handle flag, Limited to one flag at the moment. */
2245 if (pseudo_insn->flag_r != NULL)
2246 *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
2247 MAX_INSN_FLGS - *nflgs);
2248
2249 /* Handle operand operations. */
2250 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
252b5132 2251 {
4670103e
CZ		 2252 operand_pseudo = &pseudo_insn->operand[i];
2253 operand_real = &arc_operands[operand_pseudo->operand_idx];
886a2506 2254
db18dbab
GM		 2255 if (operand_real->flags & ARC_OPERAND_BRAKET
2256 && !operand_pseudo->needs_insert)
4670103e 2257 continue;
b125bd17 2258
4670103e
CZ		 2259 /* Has to be inserted (i.e. this token does not exist yet). */
2260 if (operand_pseudo->needs_insert)
2261 {
2262 if (operand_real->flags & ARC_OPERAND_BRAKET)
2263 {
2264 tok[i].X_op = O_bracket;
2265 ++(*ntok);
2266 continue;
2267 }
b125bd17 2268
4670103e
CZ		 2269 /* Check if operand is a register or constant and handle it
2270 by type. */
2271 if (operand_real->flags & ARC_OPERAND_IR)
2272 snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
2273 operand_pseudo->count);
2274 else
2275 snprintf (construct_operand, MAX_CONSTR_STR, "%d",
2276 operand_pseudo->count);
886a2506 2277
4670103e
CZ		 2278 tokenize_arguments (construct_operand, &tok[i], 1);
2279 ++(*ntok);
2280 }
2281
2282 else if (operand_pseudo->count)
2283 {
2284 /* Operand number has to be adjusted accordingly (by operand
2285 type). */
2286 switch (tok[i].X_op)
2287 {
2288 case O_constant:
2289 tok[i].X_add_number += operand_pseudo->count;
2290 break;
2291
2292 case O_symbol:
2293 break;
2294
2295 default:
2296 /* Ignored. */
2297 break;
2298 }
2299 }
2300 }
2301
2302 /* Swap operands if necessary. Only supports one swap at the
2303 moment. */
2304 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2305 {
2306 operand_pseudo = &pseudo_insn->operand[i];
2307
2308 if (operand_pseudo->swap_operand_idx == i)
2309 continue;
2310
2311 swap_operand (tok, i, operand_pseudo->swap_operand_idx);
2312
2313 /* Prevent a swap back later by breaking out. */
2314 break;
2315 }
2316
da5be039 2317 return arc_find_opcode (pseudo_insn->mnemonic_r);
4670103e
CZ		 2318}
2319
b9b47ab7 2320static const struct arc_opcode_hash_entry *
4670103e
CZ		 2321find_special_case_flag (const char *opname,
2322 int *nflgs,
2323 struct arc_flags *pflags)
2324{
2325 unsigned int i;
2326 const char *flagnm;
2327 unsigned flag_idx, flag_arr_idx;
2328 size_t flaglen, oplen;
2329 const struct arc_flag_special *arc_flag_special_opcode;
b9b47ab7 2330 const struct arc_opcode_hash_entry *entry;
4670103e
CZ		 2331
2332 /* Search for special case instruction. */
2333 for (i = 0; i < arc_num_flag_special; i++)
2334 {
2335 arc_flag_special_opcode = &arc_flag_special_cases[i];
2336 oplen = strlen (arc_flag_special_opcode->name);
2337
2338 if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
2339 continue;
2340
2341 /* Found a potential special case instruction, now test for
2342 flags. */
2343 for (flag_arr_idx = 0;; ++flag_arr_idx)
2344 {
2345 flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
2346 if (flag_idx == 0)
2347 break; /* End of array, nothing found. */
886a2506 2348
4670103e
CZ		 2349 flagnm = arc_flag_operands[flag_idx].name;
2350 flaglen = strlen (flagnm);
2351 if (strcmp (opname + oplen, flagnm) == 0)
2352 {
b9b47ab7 2353 entry = arc_find_opcode (arc_flag_special_opcode->name);
886a2506 2354
4670103e
CZ		 2355 if (*nflgs + 1 > MAX_INSN_FLGS)
2356 break;
2357 memcpy (pflags[*nflgs].name, flagnm, flaglen);
2358 pflags[*nflgs].name[flaglen] = '\0';
2359 (*nflgs)++;
b9b47ab7 2360 return entry;
4670103e
CZ		 2361 }
2362 }
2363 }
2364 return NULL;
2365}
886a2506 2366
4670103e 2367/* Used to find special case opcode. */
886a2506 2368
b9b47ab7 2369static const struct arc_opcode_hash_entry *
4670103e
CZ		 2370find_special_case (const char *opname,
2371 int *nflgs,
2372 struct arc_flags *pflags,
2373 expressionS *tok,
2374 int *ntok)
2375{
b9b47ab7 2376 const struct arc_opcode_hash_entry *entry;
886a2506 2377
b9b47ab7 2378 entry = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
886a2506 2379
b9b47ab7
AB		 2380 if (entry == NULL)
2381 entry = find_special_case_flag (opname, nflgs, pflags);
886a2506 2382
b9b47ab7 2383 return entry;
4670103e 2384}
886a2506 2385
53a346d8
CZ		 2386/* Autodetect cpu attribute list. */
2387
2388static void
2389autodetect_attributes (const struct arc_opcode *opcode,
2390 const expressionS *tok,
2391 int ntok)
2392{
2393 unsigned i;
2394 struct mpy_type
2395 {
2396 unsigned feature;
2397 unsigned encoding;
2398 } mpy_list[] = {{ MPY1E, 1 }, { MPY6E, 6 }, { MPY7E, 7 }, { MPY8E, 8 },
2399 { MPY9E, 9 }};
2400
2401 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
2402 if (opcode->subclass == feature_list[i].feature)
2403 selected_cpu.features |= feature_list[i].feature;
2404
2405 for (i = 0; i < ARRAY_SIZE (mpy_list); i++)
2406 if (opcode->subclass == mpy_list[i].feature)
2407 mpy_option = mpy_list[i].encoding;
2408
2409 for (i = 0; i < (unsigned) ntok; i++)
2410 {
2411 switch (tok[i].X_md)
2412 {
2413 case O_gotoff:
2414 case O_gotpc:
2415 case O_plt:
2416 pic_option = 2;
2417 break;
2418 case O_sda:
2419 sda_option = 2;
2420 break;
2421 case O_tlsgd:
2422 case O_tlsie:
2423 case O_tpoff9:
2424 case O_tpoff:
2425 case O_dtpoff9:
2426 case O_dtpoff:
2427 tls_option = 1;
2428 break;
2429 default:
2430 break;
2431 }
63741043 2432
2433 switch (tok[i].X_op)
2434 {
2435 case O_register:
2436 if ((tok[i].X_add_number >= 4 && tok[i].X_add_number <= 9)
2437 || (tok[i].X_add_number >= 16 && tok[i].X_add_number <= 25))
2438 rf16_only = FALSE;
2439 break;
2440 default:
2441 break;
2442 }
53a346d8
CZ		 2443 }
2444}
2445
2446/* Given an opcode name, pre-tockenized set of argumenst and the
4670103e 2447 opcode flags, take it all the way through emission. */
886a2506 2448
4670103e
CZ		 2449static void
2450assemble_tokens (const char *opname,
2451 expressionS *tok,
2452 int ntok,
2453 struct arc_flags *pflags,
2454 int nflgs)
2455{
2456 bfd_boolean found_something = FALSE;
b9b47ab7 2457 const struct arc_opcode_hash_entry *entry;
4670103e 2458 int cpumatch = 1;
abe7c33b 2459 const char *errmsg = NULL;
886a2506 2460
4670103e 2461 /* Search opcodes. */
b9b47ab7 2462 entry = arc_find_opcode (opname);
886a2506 2463
4670103e 2464 /* Couldn't find opcode conventional way, try special cases. */
b9b47ab7
AB		 2465 if (entry == NULL)
2466 entry = find_special_case (opname, &nflgs, pflags, tok, &ntok);
886a2506 2467
b9b47ab7 2468 if (entry != NULL)
4670103e 2469 {
b9b47ab7
AB		 2470 const struct arc_opcode *opcode;
2471
1328504b
AB		 2472 pr_debug ("%s:%d: assemble_tokens: %s\n",
2473 frag_now->fr_file, frag_now->fr_line, opname);
4670103e 2474 found_something = TRUE;
b9b47ab7 2475 opcode = find_opcode_match (entry, tok, &ntok, pflags,
abe7c33b 2476 nflgs, &cpumatch, &errmsg);
b9b47ab7 2477 if (opcode != NULL)
4670103e
CZ		 2478 {
2479 struct arc_insn insn;
b9b47ab7 2480
53a346d8 2481 autodetect_attributes (opcode, tok, ntok);
4670103e
CZ		 2482 assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
2483 emit_insn (&insn);
2484 return;
2485 }
2486 }
886a2506 2487
4670103e
CZ		 2488 if (found_something)
2489 {
2490 if (cpumatch)
abe7c33b
CZ		 2491 if (errmsg)
2492 as_bad (_("%s for instruction '%s'"), errmsg, opname);
2493 else
2494 as_bad (_("inappropriate arguments for opcode '%s'"), opname);
4670103e
CZ		 2495 else
2496 as_bad (_("opcode '%s' not supported for target %s"), opname,
bb65a718 2497 selected_cpu.name);
4670103e
CZ		 2498 }
2499 else
2500 as_bad (_("unknown opcode '%s'"), opname);
886a2506
NC		 2501}
2502
4670103e 2503/* The public interface to the instruction assembler. */
886a2506 2504
4670103e
CZ		 2505void
2506md_assemble (char *str)
886a2506 2507{
4670103e
CZ		 2508 char *opname;
2509 expressionS tok[MAX_INSN_ARGS];
2510 int ntok, nflg;
2511 size_t opnamelen;
2512 struct arc_flags flags[MAX_INSN_FLGS];
886a2506 2513
4670103e
CZ		 2514 /* Split off the opcode. */
2515 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
29a2809e 2516 opname = xmemdup0 (str, opnamelen);
886a2506 2517
33eaf5de 2518 /* Signalize we are assembling the instructions. */
4670103e 2519 assembling_insn = TRUE;
886a2506 2520
4670103e
CZ		 2521 /* Tokenize the flags. */
2522 if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
2523 {
2524 as_bad (_("syntax error"));
2525 return;
2526 }
886a2506 2527
4670103e
CZ		 2528 /* Scan up to the end of the mnemonic which must end in space or end
2529 of string. */
2530 str += opnamelen;
2531 for (; *str != '\0'; str++)
2532 if (*str == ' ')
2533 break;
886a2506 2534
4670103e
CZ		 2535 /* Tokenize the rest of the line. */
2536 if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
886a2506 2537 {
4670103e
CZ		 2538 as_bad (_("syntax error"));
2539 return;
252b5132
RH		 2540 }
2541
4670103e
CZ		 2542 /* Finish it off. */
2543 assemble_tokens (opname, tok, ntok, flags, nflg);
2544 assembling_insn = FALSE;
2545}
2546
2547/* Callback to insert a register into the hash table. */
2548
2549static void
f86f5863 2550declare_register (const char *name, int number)
4670103e 2551{
4670103e 2552 symbolS *regS = symbol_create (name, reg_section,
e01e1cee 2553 &zero_address_frag, number);
4670103e 2554
629310ab 2555 str_hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS);
4670103e 2556}
252b5132 2557
4670103e 2558/* Construct symbols for each of the general registers. */
252b5132 2559
4670103e
CZ		 2560static void
2561declare_register_set (void)
2562{
2563 int i;
2564 for (i = 0; i < 64; ++i)
886a2506 2565 {
4670103e
CZ		 2566 char name[7];
2567
2568 sprintf (name, "r%d", i);
2569 declare_register (name, i);
2570 if ((i & 0x01) == 0)
886a2506 2571 {
4670103e
CZ		 2572 sprintf (name, "r%dr%d", i, i+1);
2573 declare_register (name, i);
886a2506
NC		 2574 }
2575 }
252b5132 2576}
ea1562b3 2577
db18dbab
GM		 2578/* Construct a symbol for an address type. */
2579
2580static void
2581declare_addrtype (const char *name, int number)
2582{
db18dbab 2583 symbolS *addrtypeS = symbol_create (name, undefined_section,
e01e1cee 2584 &zero_address_frag, number);
db18dbab 2585
629310ab
ML		 2586 str_hash_insert (arc_addrtype_hash, S_GET_NAME (addrtypeS),
2587 (void *) addrtypeS);
db18dbab
GM		 2588}
2589
4670103e
CZ		 2590/* Port-specific assembler initialization. This function is called
2591 once, at assembler startup time. */
ea1562b3
NC		 2592
2593void
4670103e 2594md_begin (void)
ea1562b3 2595{
b99747ae 2596 const struct arc_opcode *opcode = arc_opcodes;
886a2506 2597
bb65a718
AB		 2598 if (mach_selection_mode == MACH_SELECTION_NONE)
2599 arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT);
24740d83 2600
4670103e
CZ		 2601 /* The endianness can be chosen "at the factory". */
2602 target_big_endian = byte_order == BIG_ENDIAN;
886a2506 2603
bb65a718 2604 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
4670103e
CZ		 2605 as_warn (_("could not set architecture and machine"));
2606
2607 /* Set elf header flags. */
bb65a718 2608 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
4670103e
CZ		 2609
2610 /* Set up a hash table for the instructions. */
629310ab 2611 arc_opcode_hash = str_htab_create ();
4670103e
CZ		 2612 if (arc_opcode_hash == NULL)
2613 as_fatal (_("Virtual memory exhausted"));
2614
2615 /* Initialize the hash table with the insns. */
b99747ae 2616 do
ea1562b3 2617 {
b99747ae 2618 const char *name = opcode->name;
da5be039 2619
b99747ae 2620 arc_insert_opcode (opcode);
4670103e 2621
b99747ae
CZ		 2622 while (++opcode && opcode->name
2623 && (opcode->name == name
2624 || !strcmp (opcode->name, name)))
4670103e 2625 continue;
b99747ae 2626 }while (opcode->name);
4670103e
CZ		 2627
2628 /* Register declaration. */
629310ab 2629 arc_reg_hash = str_htab_create ();
4670103e
CZ		 2630 if (arc_reg_hash == NULL)
2631 as_fatal (_("Virtual memory exhausted"));
2632
2633 declare_register_set ();
2634 declare_register ("gp", 26);
2635 declare_register ("fp", 27);
2636 declare_register ("sp", 28);
2637 declare_register ("ilink", 29);
2638 declare_register ("ilink1", 29);
2639 declare_register ("ilink2", 30);
2640 declare_register ("blink", 31);
2641
87789e08
CZ		 2642 /* XY memory registers. */
2643 declare_register ("x0_u0", 32);
2644 declare_register ("x0_u1", 33);
2645 declare_register ("x1_u0", 34);
2646 declare_register ("x1_u1", 35);
2647 declare_register ("x2_u0", 36);
2648 declare_register ("x2_u1", 37);
2649 declare_register ("x3_u0", 38);
2650 declare_register ("x3_u1", 39);
2651 declare_register ("y0_u0", 40);
2652 declare_register ("y0_u1", 41);
2653 declare_register ("y1_u0", 42);
2654 declare_register ("y1_u1", 43);
2655 declare_register ("y2_u0", 44);
2656 declare_register ("y2_u1", 45);
2657 declare_register ("y3_u0", 46);
2658 declare_register ("y3_u1", 47);
2659 declare_register ("x0_nu", 48);
2660 declare_register ("x1_nu", 49);
2661 declare_register ("x2_nu", 50);
2662 declare_register ("x3_nu", 51);
2663 declare_register ("y0_nu", 52);
2664 declare_register ("y1_nu", 53);
2665 declare_register ("y2_nu", 54);
2666 declare_register ("y3_nu", 55);
2667
4670103e
CZ		 2668 declare_register ("mlo", 57);
2669 declare_register ("mmid", 58);
2670 declare_register ("mhi", 59);
2671
2672 declare_register ("acc1", 56);
2673 declare_register ("acc2", 57);
2674
2675 declare_register ("lp_count", 60);
2676 declare_register ("pcl", 63);
2677
2678 /* Initialize the last instructions. */
2679 memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
f36e33da
CZ		 2680
2681 /* Aux register declaration. */
629310ab 2682 arc_aux_hash = str_htab_create ();
f36e33da
CZ		 2683 if (arc_aux_hash == NULL)
2684 as_fatal (_("Virtual memory exhausted"));
2685
2686 const struct arc_aux_reg *auxr = &arc_aux_regs[0];
2687 unsigned int i;
2688 for (i = 0; i < arc_num_aux_regs; i++, auxr++)
2689 {
bb65a718 2690 if (!(auxr->cpu & selected_cpu.flags))
f36e33da
CZ		 2691 continue;
2692
2693 if ((auxr->subclass != NONE)
2694 && !check_cpu_feature (auxr->subclass))
2695 continue;
2696
629310ab 2697 str_hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
f36e33da 2698 }
db18dbab
GM		 2699
2700 /* Address type declaration. */
629310ab 2701 arc_addrtype_hash = str_htab_create ();
db18dbab
GM		 2702 if (arc_addrtype_hash == NULL)
2703 as_fatal (_("Virtual memory exhausted"));
2704
2705 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD);
2706 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID);
2707 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD);
2708 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD);
2709 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD);
2710 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM);
2711 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA);
2712 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD);
2713 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD);
2714 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD);
2715 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID);
2716 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD);
2717 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM);
2718 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD);
2719 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA);
2720 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD);
886a2506 2721}
ea1562b3 2722
4670103e
CZ		 2723/* Write a value out to the object file, using the appropriate
2724 endianness. */
ea1562b3 2725
4670103e
CZ		 2726void
2727md_number_to_chars (char *buf,
2728 valueT val,
2729 int n)
886a2506 2730{
4670103e
CZ		 2731 if (target_big_endian)
2732 number_to_chars_bigendian (buf, val, n);
2733 else
2734 number_to_chars_littleendian (buf, val, n);
886a2506 2735}
ea1562b3 2736
4670103e 2737/* Round up a section size to the appropriate boundary. */
ea1562b3 2738
4670103e
CZ		 2739valueT
2740md_section_align (segT segment,
2741 valueT size)
886a2506 2742{
fd361982 2743 int align = bfd_section_alignment (segment);
4670103e
CZ		 2744
2745 return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
886a2506 2746}
ea1562b3 2747
4670103e
CZ		 2748/* The location from which a PC relative jump should be calculated,
2749 given a PC relative reloc. */
ea1562b3 2750
4670103e
CZ		 2751long
2752md_pcrel_from_section (fixS *fixP,
2753 segT sec)
886a2506 2754{
4670103e 2755 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
ea1562b3 2756
4670103e 2757 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
ea1562b3 2758
4670103e
CZ		 2759 if (fixP->fx_addsy != (symbolS *) NULL
2760 && (!S_IS_DEFINED (fixP->fx_addsy)
2761 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
2762 {
2763 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
ea1562b3 2764
4670103e
CZ		 2765 /* The symbol is undefined (or is defined but not in this section).
2766 Let the linker figure it out. */
2767 return 0;
2768 }
2769
2770 if ((int) fixP->fx_r_type < 0)
886a2506 2771 {
4670103e
CZ		 2772 /* These are the "internal" relocations. Align them to
2773 32 bit boundary (PCL), for the moment. */
2774 base &= ~3;
886a2506 2775 }
4670103e
CZ		 2776 else
2777 {
2778 switch (fixP->fx_r_type)
2779 {
2780 case BFD_RELOC_ARC_PC32:
2781 /* The hardware calculates relative to the start of the
2782 insn, but this relocation is relative to location of the
2783 LIMM, compensate. The base always needs to be
2b0f3761 2784 subtracted by 4 as we do not support this type of PCrel
4670103e
CZ		 2785 relocation for short instructions. */
2786 base -= 4;
2787 /* Fall through. */
2788 case BFD_RELOC_ARC_PLT32:
2789 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2790 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2791 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2792 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2793
2794 case BFD_RELOC_ARC_S21H_PCREL:
2795 case BFD_RELOC_ARC_S25H_PCREL:
2796 case BFD_RELOC_ARC_S13_PCREL:
2797 case BFD_RELOC_ARC_S21W_PCREL:
2798 case BFD_RELOC_ARC_S25W_PCREL:
2799 base &= ~3;
2800 break;
2801 default:
2802 as_bad_where (fixP->fx_file, fixP->fx_line,
2803 _("unhandled reloc %s in md_pcrel_from_section"),
2804 bfd_get_reloc_code_name (fixP->fx_r_type));
2805 break;
2806 }
2807 }
2808
9e32d9ae
AB		 2809 pr_debug ("pcrel from %"BFD_VMA_FMT"x + %lx = %"BFD_VMA_FMT"x, "
2810 "symbol: %s (%"BFD_VMA_FMT"x)\n",
4670103e
CZ		 2811 fixP->fx_frag->fr_address, fixP->fx_where, base,
2812 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
2813 fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
2814
2815 return base;
886a2506 2816}
ea1562b3 2817
33eaf5de 2818/* Given a BFD relocation find the corresponding operand. */
ea1562b3 2819
4670103e
CZ		 2820static const struct arc_operand *
2821find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
2822{
2823 unsigned i;
ea1562b3 2824
4670103e
CZ		 2825 for (i = 0; i < arc_num_operands; i++)
2826 if (arc_operands[i].default_reloc == reloc)
2827 return &arc_operands[i];
2828 return NULL;
2829}
ea1562b3 2830
4670103e 2831/* Insert an operand value into an instruction. */
ea1562b3 2832
bdfe53e3
AB		 2833static unsigned long long
2834insert_operand (unsigned long long insn,
4670103e 2835 const struct arc_operand *operand,
bdfe53e3 2836 long long val,
3b4dbbbf 2837 const char *file,
4670103e 2838 unsigned line)
886a2506 2839{
4670103e 2840 offsetT min = 0, max = 0;
ea1562b3 2841
4670103e
CZ		 2842 if (operand->bits != 32
2843 && !(operand->flags & ARC_OPERAND_NCHK)
2844 && !(operand->flags & ARC_OPERAND_FAKE))
886a2506 2845 {
4670103e
CZ		 2846 if (operand->flags & ARC_OPERAND_SIGNED)
2847 {
2848 max = (1 << (operand->bits - 1)) - 1;
2849 min = -(1 << (operand->bits - 1));
2850 }
2851 else
2852 {
2853 max = (1 << operand->bits) - 1;
2854 min = 0;
2855 }
886a2506 2856
4670103e
CZ		 2857 if (val < min || val > max)
2858 as_bad_value_out_of_range (_("operand"),
2859 val, min, max, file, line);
2860 }
ea1562b3 2861
cc07cda6 2862 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
4670103e 2863 min, val, max, insn);
ea1562b3 2864
4670103e
CZ		 2865 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2866 && (val & 0x03))
2867 as_bad_where (file, line,
2868 _("Unaligned operand. Needs to be 32bit aligned"));
ea1562b3 2869
4670103e
CZ		 2870 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2871 && (val & 0x01))
2872 as_bad_where (file, line,
2873 _("Unaligned operand. Needs to be 16bit aligned"));
ea1562b3 2874
4670103e
CZ		 2875 if (operand->insert)
2876 {
2877 const char *errmsg = NULL;
ea1562b3 2878
4670103e
CZ		 2879 insn = (*operand->insert) (insn, val, &errmsg);
2880 if (errmsg)
2881 as_warn_where (file, line, "%s", errmsg);
2882 }
2883 else
2884 {
2885 if (operand->flags & ARC_OPERAND_TRUNCATE)
2886 {
2887 if (operand->flags & ARC_OPERAND_ALIGNED32)
2888 val >>= 2;
2889 if (operand->flags & ARC_OPERAND_ALIGNED16)
2890 val >>= 1;
886a2506 2891 }
4670103e
CZ		 2892 insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
2893 }
2894 return insn;
2895}
ea1562b3 2896
4670103e
CZ		 2897/* Apply a fixup to the object code. At this point all symbol values
2898 should be fully resolved, and we attempt to completely resolve the
2899 reloc. If we can not do that, we determine the correct reloc code
2900 and put it back in the fixup. To indicate that a fixup has been
2901 eliminated, set fixP->fx_done. */
ea1562b3 2902
4670103e
CZ		 2903void
2904md_apply_fix (fixS *fixP,
2905 valueT *valP,
2906 segT seg)
2907{
2908 char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
2909 valueT value = *valP;
2910 unsigned insn = 0;
2911 symbolS *fx_addsy, *fx_subsy;
2912 offsetT fx_offset;
2913 segT add_symbol_segment = absolute_section;
2914 segT sub_symbol_segment = absolute_section;
2915 const struct arc_operand *operand = NULL;
2916 extended_bfd_reloc_code_real_type reloc;
886a2506 2917
4670103e
CZ		 2918 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2919 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2920 ((int) fixP->fx_r_type < 0) ? "Internal":
2921 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2922 fixP->fx_offset);
886a2506 2923
4670103e
CZ		 2924 fx_addsy = fixP->fx_addsy;
2925 fx_subsy = fixP->fx_subsy;
2926 fx_offset = 0;
886a2506 2927
4670103e
CZ		 2928 if (fx_addsy)
2929 {
2930 add_symbol_segment = S_GET_SEGMENT (fx_addsy);
886a2506
NC		 2931 }
2932
4670103e
CZ		 2933 if (fx_subsy
2934 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
2935 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
2936 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
2937 {
2938 resolve_symbol_value (fx_subsy);
2939 sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
886a2506 2940
4670103e
CZ		 2941 if (sub_symbol_segment == absolute_section)
2942 {
2943 /* The symbol is really a constant. */
2944 fx_offset -= S_GET_VALUE (fx_subsy);
2945 fx_subsy = NULL;
2946 }
2947 else
2948 {
2949 as_bad_where (fixP->fx_file, fixP->fx_line,
2950 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2951 fx_addsy ? S_GET_NAME (fx_addsy) : "0",
2952 segment_name (add_symbol_segment),
2953 S_GET_NAME (fx_subsy),
2954 segment_name (sub_symbol_segment));
2955 return;
2956 }
2957 }
886a2506 2958
4670103e
CZ		 2959 if (fx_addsy
2960 && !S_IS_WEAK (fx_addsy))
2961 {
2962 if (add_symbol_segment == seg
2963 && fixP->fx_pcrel)
2964 {
2965 value += S_GET_VALUE (fx_addsy);
2966 value -= md_pcrel_from_section (fixP, seg);
2967 fx_addsy = NULL;
2968 fixP->fx_pcrel = FALSE;
2969 }
2970 else if (add_symbol_segment == absolute_section)
2971 {
2972 value = fixP->fx_offset;
2973 fx_offset += S_GET_VALUE (fixP->fx_addsy);
2974 fx_addsy = NULL;
2975 fixP->fx_pcrel = FALSE;
2976 }
2977 }
886a2506 2978
4670103e
CZ		 2979 if (!fx_addsy)
2980 fixP->fx_done = TRUE;
886a2506 2981
4670103e 2982 if (fixP->fx_pcrel)
886a2506 2983 {
4670103e
CZ		 2984 if (fx_addsy
2985 && ((S_IS_DEFINED (fx_addsy)
2986 && S_GET_SEGMENT (fx_addsy) != seg)
2987 || S_IS_WEAK (fx_addsy)))
2988 value += md_pcrel_from_section (fixP, seg);
886a2506 2989
4670103e
CZ		 2990 switch (fixP->fx_r_type)
2991 {
2992 case BFD_RELOC_ARC_32_ME:
2993 /* This is a pc-relative value in a LIMM. Adjust it to the
2994 address of the instruction not to the address of the
33eaf5de 2995 LIMM. Note: it is not any longer valid this affirmation as
4670103e
CZ		 2996 the linker consider ARC_PC32 a fixup to entire 64 bit
2997 insn. */
2998 fixP->fx_offset += fixP->fx_frag->fr_address;
2999 /* Fall through. */
3000 case BFD_RELOC_32:
3001 fixP->fx_r_type = BFD_RELOC_ARC_PC32;
3002 /* Fall through. */
3003 case BFD_RELOC_ARC_PC32:
3004 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
886a2506
NC		 3005 break;
3006 default:
4670103e 3007 if ((int) fixP->fx_r_type < 0)
6e3f3473 3008 as_bad_where (fixP->fx_file, fixP->fx_line,
3009 _("PC relative relocation not allowed for (internal)"
3010 " type %d"),
3011 fixP->fx_r_type);
886a2506 3012 break;
ea1562b3
NC		 3013 }
3014 }
3015
4670103e
CZ		 3016 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
3017 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
3018 ((int) fixP->fx_r_type < 0) ? "Internal":
3019 bfd_get_reloc_code_name (fixP->fx_r_type), value,
3020 fixP->fx_offset);
886a2506 3021
886a2506 3022
4670103e
CZ		 3023 /* Now check for TLS relocations. */
3024 reloc = fixP->fx_r_type;
3025 switch (reloc)
886a2506 3026 {
4670103e
CZ		 3027 case BFD_RELOC_ARC_TLS_DTPOFF:
3028 case BFD_RELOC_ARC_TLS_LE_32:
3029 if (fixP->fx_done)
3030 break;
3031 /* Fall through. */
3032 case BFD_RELOC_ARC_TLS_GD_GOT:
3033 case BFD_RELOC_ARC_TLS_IE_GOT:
3034 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3035 break;
886a2506 3036
4670103e
CZ		 3037 case BFD_RELOC_ARC_TLS_GD_LD:
3038 gas_assert (!fixP->fx_offset);
3039 if (fixP->fx_subsy)
3040 fixP->fx_offset
3041 = (S_GET_VALUE (fixP->fx_subsy)
3042 - fixP->fx_frag->fr_address- fixP->fx_where);
3043 fixP->fx_subsy = NULL;
3044 /* Fall through. */
3045 case BFD_RELOC_ARC_TLS_GD_CALL:
3046 /* These two relocs are there just to allow ld to change the tls
3047 model for this symbol, by patching the code. The offset -
3048 and scale, if any - will be installed by the linker. */
3049 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3050 break;
886a2506 3051
4670103e
CZ		 3052 case BFD_RELOC_ARC_TLS_LE_S9:
3053 case BFD_RELOC_ARC_TLS_DTPOFF_S9:
3054 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3055 break;
3056
3057 default:
3058 break;
886a2506
NC		 3059 }
3060
4670103e 3061 if (!fixP->fx_done)
886a2506 3062 {
4670103e 3063 return;
886a2506 3064 }
886a2506 3065
33eaf5de 3066 /* Adjust the value if we have a constant. */
4670103e 3067 value += fx_offset;
886a2506 3068
4670103e
CZ		 3069 /* For hosts with longs bigger than 32-bits make sure that the top
3070 bits of a 32-bit negative value read in by the parser are set,
3071 so that the correct comparisons are made. */
3072 if (value & 0x80000000)
69c9e028 3073 value |= (-1UL << 31);
886a2506 3074
4670103e
CZ		 3075 reloc = fixP->fx_r_type;
3076 switch (reloc)
3077 {
3078 case BFD_RELOC_8:
3079 case BFD_RELOC_16:
3080 case BFD_RELOC_24:
3081 case BFD_RELOC_32:
3082 case BFD_RELOC_64:
3083 case BFD_RELOC_ARC_32_PCREL:
3084 md_number_to_chars (fixpos, value, fixP->fx_size);
3085 return;
886a2506 3086
4670103e
CZ		 3087 case BFD_RELOC_ARC_GOTPC32:
3088 /* I cannot fix an GOTPC relocation because I need to relax it
3089 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3090 as_bad (_("Unsupported operation on reloc"));
3091 return;
886a2506 3092
4670103e
CZ		 3093 case BFD_RELOC_ARC_TLS_DTPOFF:
3094 case BFD_RELOC_ARC_TLS_LE_32:
3095 gas_assert (!fixP->fx_addsy);
3096 gas_assert (!fixP->fx_subsy);
1a0670f3 3097 /* Fall through. */
886a2506 3098
4670103e
CZ		 3099 case BFD_RELOC_ARC_GOTOFF:
3100 case BFD_RELOC_ARC_32_ME:
3101 case BFD_RELOC_ARC_PC32:
3102 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3103 return;
886a2506 3104
4670103e
CZ		 3105 case BFD_RELOC_ARC_PLT32:
3106 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3107 return;
886a2506 3108
4670103e
CZ		 3109 case BFD_RELOC_ARC_S25H_PCREL_PLT:
3110 reloc = BFD_RELOC_ARC_S25W_PCREL;
3111 goto solve_plt;
886a2506 3112
4670103e
CZ		 3113 case BFD_RELOC_ARC_S21H_PCREL_PLT:
3114 reloc = BFD_RELOC_ARC_S21H_PCREL;
3115 goto solve_plt;
886a2506 3116
4670103e
CZ		 3117 case BFD_RELOC_ARC_S25W_PCREL_PLT:
3118 reloc = BFD_RELOC_ARC_S25W_PCREL;
3119 goto solve_plt;
886a2506 3120
4670103e
CZ		 3121 case BFD_RELOC_ARC_S21W_PCREL_PLT:
3122 reloc = BFD_RELOC_ARC_S21W_PCREL;
1a0670f3 3123 /* Fall through. */
886a2506 3124
4670103e
CZ		 3125 case BFD_RELOC_ARC_S25W_PCREL:
3126 case BFD_RELOC_ARC_S21W_PCREL:
3127 case BFD_RELOC_ARC_S21H_PCREL:
3128 case BFD_RELOC_ARC_S25H_PCREL:
3129 case BFD_RELOC_ARC_S13_PCREL:
3130 solve_plt:
3131 operand = find_operand_for_reloc (reloc);
3132 gas_assert (operand);
886a2506
NC		 3133 break;
3134
3135 default:
4670103e
CZ		 3136 {
3137 if ((int) fixP->fx_r_type >= 0)
3138 as_fatal (_("unhandled relocation type %s"),
3139 bfd_get_reloc_code_name (fixP->fx_r_type));
886a2506 3140
4670103e
CZ		 3141 /* The rest of these fixups needs to be completely resolved as
3142 constants. */
3143 if (fixP->fx_addsy != 0
3144 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
3145 as_bad_where (fixP->fx_file, fixP->fx_line,
3146 _("non-absolute expression in constant field"));
886a2506 3147
4670103e
CZ		 3148 gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
3149 operand = &arc_operands[-(int) fixP->fx_r_type];
3150 break;
3151 }
3152 }
886a2506 3153
4670103e 3154 if (target_big_endian)
886a2506 3155 {
4670103e 3156 switch (fixP->fx_size)
886a2506 3157 {
4670103e
CZ		 3158 case 4:
3159 insn = bfd_getb32 (fixpos);
3160 break;
3161 case 2:
3162 insn = bfd_getb16 (fixpos);
3163 break;
3164 default:
3165 as_bad_where (fixP->fx_file, fixP->fx_line,
3166 _("unknown fixup size"));
3167 }
3168 }
3169 else
3170 {
3171 insn = 0;
3172 switch (fixP->fx_size)
3173 {
3174 case 4:
3175 insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
3176 break;
3177 case 2:
3178 insn = bfd_getl16 (fixpos);
3179 break;
3180 default:
3181 as_bad_where (fixP->fx_file, fixP->fx_line,
3182 _("unknown fixup size"));
886a2506
NC		 3183 }
3184 }
886a2506 3185
4670103e
CZ		 3186 insn = insert_operand (insn, operand, (offsetT) value,
3187 fixP->fx_file, fixP->fx_line);
886a2506 3188
4670103e
CZ		 3189 md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
3190}
886a2506 3191
4670103e 3192/* Prepare machine-dependent frags for relaxation.
886a2506 3193
4670103e
CZ		 3194 Called just before relaxation starts. Any symbol that is now undefined
3195 will not become defined.
886a2506 3196
4670103e 3197 Return the correct fr_subtype in the frag.
886a2506 3198
4670103e
CZ		 3199 Return the initial "guess for fr_var" to caller. The guess for fr_var
3200 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3201 or fr_var contributes to our returned value.
886a2506 3202
4670103e
CZ		 3203 Although it may not be explicit in the frag, pretend
3204 fr_var starts with a value. */
886a2506 3205
4670103e
CZ		 3206int
3207md_estimate_size_before_relax (fragS *fragP,
3208 segT segment)
3209{
3210 int growth;
3211
3212 /* If the symbol is not located within the same section AND it's not
3213 an absolute section, use the maximum. OR if the symbol is a
3214 constant AND the insn is by nature not pc-rel, use the maximum.
3215 OR if the symbol is being equated against another symbol, use the
3216 maximum. OR if the symbol is weak use the maximum. */
3217 if ((S_GET_SEGMENT (fragP->fr_symbol) != segment
3218 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
3219 || (symbol_constant_p (fragP->fr_symbol)
3220 && !fragP->tc_frag_data.pcrel)
3221 || symbol_equated_p (fragP->fr_symbol)
3222 || S_IS_WEAK (fragP->fr_symbol))
3223 {
3224 while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE)
3225 ++fragP->fr_subtype;
3226 }
886a2506 3227
4670103e
CZ		 3228 growth = md_relax_table[fragP->fr_subtype].rlx_length;
3229 fragP->fr_var = growth;
886a2506 3230
4670103e
CZ		 3231 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3232 fragP->fr_file, fragP->fr_line, growth);
886a2506 3233
4670103e
CZ		 3234 return growth;
3235}
886a2506 3236
4670103e
CZ		 3237/* Translate internal representation of relocation info to BFD target
3238 format. */
886a2506 3239
4670103e
CZ		 3240arelent *
3241tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
3242 fixS *fixP)
3243{
3244 arelent *reloc;
3245 bfd_reloc_code_real_type code;
886a2506 3246
add39d23
TS		 3247 reloc = XNEW (arelent);
3248 reloc->sym_ptr_ptr = XNEW (asymbol *);
4670103e
CZ		 3249 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
3250 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
886a2506 3251
4670103e
CZ		 3252 /* Make sure none of our internal relocations make it this far.
3253 They'd better have been fully resolved by this point. */
3254 gas_assert ((int) fixP->fx_r_type > 0);
886a2506 3255
4670103e 3256 code = fixP->fx_r_type;
886a2506 3257
4670103e
CZ		 3258 /* if we have something like add gp, pcl,
3259 _GLOBAL_OFFSET_TABLE_@gotpc. */
3260 if (code == BFD_RELOC_ARC_GOTPC32
3261 && GOT_symbol
3262 && fixP->fx_addsy == GOT_symbol)
3263 code = BFD_RELOC_ARC_GOTPC;
886a2506 3264
4670103e
CZ		 3265 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3266 if (reloc->howto == NULL)
886a2506 3267 {
4670103e
CZ		 3268 as_bad_where (fixP->fx_file, fixP->fx_line,
3269 _("cannot represent `%s' relocation in object file"),
3270 bfd_get_reloc_code_name (code));
3271 return NULL;
3272 }
886a2506 3273
4670103e
CZ		 3274 if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
3275 as_fatal (_("internal error? cannot generate `%s' relocation"),
3276 bfd_get_reloc_code_name (code));
886a2506 3277
4670103e 3278 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
886a2506 3279
05bbf016 3280 reloc->addend = fixP->fx_offset;
4670103e
CZ		 3281
3282 return reloc;
886a2506
NC		 3283}
3284
4670103e
CZ		 3285/* Perform post-processing of machine-dependent frags after relaxation.
3286 Called after relaxation is finished.
3287 In: Address of frag.
3288 fr_type == rs_machine_dependent.
3289 fr_subtype is what the address relaxed to.
886a2506 3290
4670103e
CZ		 3291 Out: Any fixS:s and constants are set up. */
3292
3293void
3294md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
3295 segT segment ATTRIBUTE_UNUSED,
3296 fragS *fragP)
886a2506 3297{
4670103e
CZ		 3298 const relax_typeS *table_entry;
3299 char *dest;
3300 const struct arc_opcode *opcode;
3301 struct arc_insn insn;
3302 int size, fix;
3303 struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
886a2506 3304
871a6bd2 3305 fix = fragP->fr_fix;
4670103e
CZ		 3306 dest = fragP->fr_literal + fix;
3307 table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
886a2506 3308
9e32d9ae
AB		 3309 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3310 "var: %"BFD_VMA_FMT"d\n",
4670103e
CZ		 3311 fragP->fr_file, fragP->fr_line,
3312 fragP->fr_subtype, fix, fragP->fr_var);
886a2506 3313
4670103e
CZ		 3314 if (fragP->fr_subtype <= 0
3315 && fragP->fr_subtype >= arc_num_relax_opcodes)
3316 as_fatal (_("no relaxation found for this instruction."));
886a2506 3317
4670103e 3318 opcode = &arc_relax_opcodes[fragP->fr_subtype];
886a2506 3319
4670103e
CZ		 3320 assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags,
3321 relax_arg->nflg, &insn);
886a2506 3322
4670103e 3323 apply_fixups (&insn, fragP, fix);
886a2506 3324
91fdca6f 3325 size = insn.len + (insn.has_limm ? 4 : 0);
4670103e
CZ		 3326 gas_assert (table_entry->rlx_length == size);
3327 emit_insn0 (&insn, dest, TRUE);
886a2506 3328
4670103e
CZ		 3329 fragP->fr_fix += table_entry->rlx_length;
3330 fragP->fr_var = 0;
886a2506
NC		 3331}
3332
4670103e
CZ		 3333/* We have no need to default values of symbols. We could catch
3334 register names here, but that is handled by inserting them all in
3335 the symbol table to begin with. */
886a2506 3336
4670103e
CZ		 3337symbolS *
3338md_undefined_symbol (char *name)
886a2506 3339{
4670103e
CZ		 3340 /* The arc abi demands that a GOT[0] should be referencible as
3341 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3342 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3343 if (((*name == '_')
3344 && (*(name+1) == 'G')
7ef0acc1 3345 && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)))
886a2506 3346 {
4670103e
CZ		 3347 if (!GOT_symbol)
3348 {
3349 if (symbol_find (name))
3350 as_bad ("GOT already in symbol table");
3351
3352 GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
e01e1cee 3353 &zero_address_frag, 0);
4670103e
CZ		 3354 };
3355 return GOT_symbol;
886a2506 3356 }
4670103e 3357 return NULL;
886a2506
NC		 3358}
3359
4670103e
CZ		 3360/* Turn a string in input_line_pointer into a floating point constant
3361 of type type, and store the appropriate bytes in *litP. The number
3362 of LITTLENUMS emitted is stored in *sizeP. An error message is
3363 returned, or NULL on OK. */
886a2506 3364
6d4af3c2 3365const char *
4670103e 3366md_atof (int type, char *litP, int *sizeP)
886a2506 3367{
4670103e
CZ		 3368 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3369}
886a2506 3370
4670103e
CZ		 3371/* Called for any expression that can not be recognized. When the
3372 function is called, `input_line_pointer' will point to the start of
2a1ebfb2
CZ		 3373 the expression. We use it when we have complex operations like
3374 @label1 - @label2. */
886a2506 3375
4670103e 3376void
2a1ebfb2 3377md_operand (expressionS *expressionP)
4670103e
CZ		 3378{
3379 char *p = input_line_pointer;
3380 if (*p == '@')
886a2506 3381 {
4670103e
CZ		 3382 input_line_pointer++;
3383 expressionP->X_op = O_symbol;
2a1ebfb2 3384 expressionP->X_md = O_absent;
4670103e
CZ		 3385 expression (expressionP);
3386 }
3387}
886a2506 3388
4670103e
CZ		 3389/* This function is called from the function 'expression', it attempts
3390 to parse special names (in our case register names). It fills in
3391 the expression with the identified register. It returns TRUE if
3392 it is a register and FALSE otherwise. */
886a2506 3393
4670103e
CZ		 3394bfd_boolean
3395arc_parse_name (const char *name,
3396 struct expressionS *e)
3397{
3398 struct symbol *sym;
886a2506 3399
4670103e
CZ		 3400 if (!assembling_insn)
3401 return FALSE;
886a2506 3402
2a1ebfb2
CZ		 3403 if (e->X_op == O_symbol
3404 && e->X_md == O_absent)
4670103e 3405 return FALSE;
886a2506 3406
629310ab 3407 sym = str_hash_find (arc_reg_hash, name);
4670103e
CZ		 3408 if (sym)
3409 {
3410 e->X_op = O_register;
3411 e->X_add_number = S_GET_VALUE (sym);
3412 return TRUE;
3413 }
db18dbab 3414
629310ab 3415 sym = str_hash_find (arc_addrtype_hash, name);
db18dbab
GM		 3416 if (sym)
3417 {
3418 e->X_op = O_addrtype;
3419 e->X_add_number = S_GET_VALUE (sym);
3420 return TRUE;
3421 }
3422
4670103e
CZ		 3423 return FALSE;
3424}
886a2506 3425
4670103e
CZ		 3426/* md_parse_option
3427 Invocation line includes a switch not recognized by the base assembler.
3428 See if it's a processor-specific option.
886a2506 3429
4670103e 3430 New options (supported) are:
886a2506 3431
4670103e
CZ		 3432 -mcpu=<cpu name> Assemble for selected processor
3433 -EB/-mbig-endian Big-endian
3434 -EL/-mlittle-endian Little-endian
3435 -mrelax Enable relaxation
886a2506 3436
4670103e 3437 The following CPU names are recognized:
ce440d63 3438 arc600, arc700, arcem, archs, nps400. */
886a2506 3439
4670103e 3440int
17b9d67d 3441md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
4670103e 3442{
4670103e
CZ		 3443 switch (c)
3444 {
3445 case OPTION_ARC600:
3446 case OPTION_ARC601:
3447 return md_parse_option (OPTION_MCPU, "arc600");
886a2506 3448
4670103e
CZ		 3449 case OPTION_ARC700:
3450 return md_parse_option (OPTION_MCPU, "arc700");
886a2506 3451
4670103e
CZ		 3452 case OPTION_ARCEM:
3453 return md_parse_option (OPTION_MCPU, "arcem");
886a2506 3454
4670103e
CZ		 3455 case OPTION_ARCHS:
3456 return md_parse_option (OPTION_MCPU, "archs");
886a2506 3457
4670103e
CZ		 3458 case OPTION_MCPU:
3459 {
bb65a718 3460 arc_select_cpu (arg, MACH_SELECTION_FROM_COMMAND_LINE);
4670103e
CZ		 3461 break;
3462 }
886a2506 3463
4670103e
CZ		 3464 case OPTION_EB:
3465 arc_target_format = "elf32-bigarc";
3466 byte_order = BIG_ENDIAN;
3467 break;
886a2506 3468
4670103e
CZ		 3469 case OPTION_EL:
3470 arc_target_format = "elf32-littlearc";
3471 byte_order = LITTLE_ENDIAN;
3472 break;
886a2506 3473
4670103e 3474 case OPTION_CD:
53a346d8
CZ		 3475 selected_cpu.features |= CD;
3476 cl_features |= CD;
bb050a69 3477 arc_check_feature ();
4670103e 3478 break;
886a2506 3479
4670103e
CZ		 3480 case OPTION_RELAX:
3481 relaxation_state = 1;
3482 break;
886a2506 3483
bdd582db 3484 case OPTION_NPS400:
53a346d8
CZ		 3485 selected_cpu.features |= NPS400;
3486 cl_features |= NPS400;
bb050a69 3487 arc_check_feature ();
ce440d63 3488 break;
bdd582db 3489
ce440d63 3490 case OPTION_SPFP:
53a346d8
CZ		 3491 selected_cpu.features |= SPX;
3492 cl_features |= SPX;
bb050a69 3493 arc_check_feature ();
ce440d63
GM		 3494 break;
3495
3496 case OPTION_DPFP:
53a346d8
CZ		 3497 selected_cpu.features |= DPX;
3498 cl_features |= DPX;
bb050a69 3499 arc_check_feature ();
ce440d63
GM		 3500 break;
3501
3502 case OPTION_FPUDA:
53a346d8
CZ		 3503 selected_cpu.features |= DPA;
3504 cl_features |= DPA;
bb050a69 3505 arc_check_feature ();
ce440d63
GM		 3506 break;
3507
3508 /* Dummy options are accepted but have no effect. */
4670103e
CZ		 3509 case OPTION_USER_MODE:
3510 case OPTION_LD_EXT_MASK:
3511 case OPTION_SWAP:
3512 case OPTION_NORM:
3513 case OPTION_BARREL_SHIFT:
3514 case OPTION_MIN_MAX:
3515 case OPTION_NO_MPY:
3516 case OPTION_EA:
3517 case OPTION_MUL64:
3518 case OPTION_SIMD:
4670103e
CZ		 3519 case OPTION_XMAC_D16:
3520 case OPTION_XMAC_24:
3521 case OPTION_DSP_PACKA:
3522 case OPTION_CRC:
3523 case OPTION_DVBF:
3524 case OPTION_TELEPHONY:
3525 case OPTION_XYMEMORY:
3526 case OPTION_LOCK:
3527 case OPTION_SWAPE:
3528 case OPTION_RTSC:
8ddf6b2a
CZ		 3529 break;
3530
4670103e
CZ		 3531 default:
3532 return 0;
3533 }
886a2506 3534
4670103e
CZ		 3535 return 1;
3536}
886a2506 3537
a9752fdf
CZ		 3538/* Display the list of cpu names for use in the help text. */
3539
3540static void
3541arc_show_cpu_list (FILE *stream)
3542{
3543 int i, offset;
731f7c4e 3544 static const char *space_buf = " ";
a9752fdf 3545
731f7c4e
MR		 3546 fprintf (stream, "%s", space_buf);
3547 offset = strlen (space_buf);
a9752fdf
CZ		 3548 for (i = 0; cpu_types[i].name != NULL; ++i)
3549 {
3550 bfd_boolean last = (cpu_types[i + 1].name == NULL);
3551
3552 /* If displaying the new cpu name string, and the ', ' (for all
3553 but the last one) will take us past a target width of 80
3554 characters, then it's time for a new line. */
3555 if (offset + strlen (cpu_types[i].name) + (last ? 0 : 2) > 80)
3556 {
731f7c4e
MR		 3557 fprintf (stream, "\n%s", space_buf);
3558 offset = strlen (space_buf);
a9752fdf
CZ		 3559 }
3560
3561 fprintf (stream, "%s%s", cpu_types[i].name, (last ? "\n" : ", "));
3562 offset += strlen (cpu_types [i].name) + (last ? 0 : 2);
3563 }
3564}
3565
4670103e
CZ		 3566void
3567md_show_usage (FILE *stream)
3568{
3569 fprintf (stream, _("ARC-specific assembler options:\n"));
886a2506 3570
a9752fdf
CZ		 3571 fprintf (stream, " -mcpu=<cpu name>\t (default: %s), assemble for"
3572 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU);
3573 arc_show_cpu_list (stream);
3574 fprintf (stream, "\n");
bdd582db
GM		 3575 fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3576 fprintf (stream, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3577 fprintf (stream, " -mEM\t\t\t same as -mcpu=arcem\n");
3578 fprintf (stream, " -mHS\t\t\t same as -mcpu=archs\n");
3579
3580 fprintf (stream, " -mnps400\t\t enable NPS-400 extended instructions\n");
a9752fdf
CZ		 3581 fprintf (stream, " -mspfp\t\t enable single-precision floating point"
3582 " instructions\n");
3583 fprintf (stream, " -mdpfp\t\t enable double-precision floating point"
3584 " instructions\n");
bdd582db
GM		 3585 fprintf (stream, " -mfpuda\t\t enable double-precision assist floating "
3586 "point\n\t\t\t instructions for ARC EM\n");
3587
4670103e
CZ		 3588 fprintf (stream,
3589 " -mcode-density\t enable code density option for ARC EM\n");
3590
3591 fprintf (stream, _("\
3592 -EB assemble code for a big-endian cpu\n"));
3593 fprintf (stream, _("\
3594 -EL assemble code for a little-endian cpu\n"));
3595 fprintf (stream, _("\
bdd582db
GM		 3596 -mrelax enable relaxation\n"));
3597
3598 fprintf (stream, _("The following ARC-specific assembler options are "
3599 "deprecated and are accepted\nfor compatibility only:\n"));
3600
3601 fprintf (stream, _(" -mEA\n"
3602 " -mbarrel-shifter\n"
3603 " -mbarrel_shifter\n"
3604 " -mcrc\n"
3605 " -mdsp-packa\n"
3606 " -mdsp_packa\n"
3607 " -mdvbf\n"
3608 " -mld-extension-reg-mask\n"
3609 " -mlock\n"
3610 " -mmac-24\n"
3611 " -mmac-d16\n"
3612 " -mmac_24\n"
3613 " -mmac_d16\n"
3614 " -mmin-max\n"
3615 " -mmin_max\n"
3616 " -mmul64\n"
3617 " -mno-mpy\n"
3618 " -mnorm\n"
3619 " -mrtsc\n"
3620 " -msimd\n"
3621 " -mswap\n"
3622 " -mswape\n"
3623 " -mtelephony\n"
3624 " -muser-mode-only\n"
3625 " -mxy\n"));
886a2506
NC		 3626}
3627
3628/* Find the proper relocation for the given opcode. */
3629
3630static extended_bfd_reloc_code_real_type
3631find_reloc (const char *name,
3632 const char *opcodename,
3633 const struct arc_flags *pflags,
3634 int nflg,
3635 extended_bfd_reloc_code_real_type reloc)
3636{
3637 unsigned int i;
3638 int j;
24b368f8 3639 bfd_boolean found_flag, tmp;
886a2506
NC		 3640 extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
3641
3642 for (i = 0; i < arc_num_equiv_tab; i++)
3643 {
3644 const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
3645
3646 /* Find the entry. */
3647 if (strcmp (name, r->name))
3648 continue;
3649 if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
3650 continue;
24b368f8 3651 if (r->flags[0])
886a2506
NC		 3652 {
3653 if (!nflg)
3654 continue;
3655 found_flag = FALSE;
24b368f8
CZ		 3656 unsigned * psflg = (unsigned *)r->flags;
3657 do
3658 {
3659 tmp = FALSE;
3660 for (j = 0; j < nflg; j++)
3661 if (!strcmp (pflags[j].name,
3662 arc_flag_operands[*psflg].name))
3663 {
3664 tmp = TRUE;
3665 break;
3666 }
3667 if (!tmp)
3668 {
3669 found_flag = FALSE;
3670 break;
3671 }
3672 else
3673 {
3674 found_flag = TRUE;
3675 }
3676 ++ psflg;
3677 } while (*psflg);
3678
886a2506
NC		 3679 if (!found_flag)
3680 continue;
3681 }
3682
3683 if (reloc != r->oldreloc)
3684 continue;
3685 /* Found it. */
3686 ret = r->newreloc;
3687 break;
3688 }
3689
3690 if (ret == BFD_RELOC_UNUSED)
3691 as_bad (_("Unable to find %s relocation for instruction %s"),
3692 name, opcodename);
3693 return ret;
3694}
3695
4670103e
CZ		 3696/* All the symbol types that are allowed to be used for
3697 relaxation. */
3698
3699static bfd_boolean
3700may_relax_expr (expressionS tok)
3701{
3702 /* Check if we have unrelaxable relocs. */
3703 switch (tok.X_md)
3704 {
3705 default:
3706 break;
3707 case O_plt:
3708 return FALSE;
3709 }
3710
3711 switch (tok.X_op)
3712 {
3713 case O_symbol:
3714 case O_multiply:
3715 case O_divide:
3716 case O_modulus:
3717 case O_add:
3718 case O_subtract:
3719 break;
3720
3721 default:
3722 return FALSE;
3723 }
3724 return TRUE;
3725}
3726
3727/* Checks if flags are in line with relaxable insn. */
3728
3729static bfd_boolean
3730relaxable_flag (const struct arc_relaxable_ins *ins,
3731 const struct arc_flags *pflags,
3732 int nflgs)
3733{
3734 unsigned flag_class,
3735 flag,
3736 flag_class_idx = 0,
3737 flag_idx = 0;
3738
3739 const struct arc_flag_operand *flag_opand;
3740 int i, counttrue = 0;
3741
3742 /* Iterate through flags classes. */
3743 while ((flag_class = ins->flag_classes[flag_class_idx]) != 0)
3744 {
3745 /* Iterate through flags in flag class. */
3746 while ((flag = arc_flag_classes[flag_class].flags[flag_idx])
3747 != 0)
3748 {
3749 flag_opand = &arc_flag_operands[flag];
3750 /* Iterate through flags in ins to compare. */
3751 for (i = 0; i < nflgs; ++i)
3752 {
3753 if (strcmp (flag_opand->name, pflags[i].name) == 0)
3754 ++counttrue;
3755 }
3756
3757 ++flag_idx;
3758 }
3759
3760 ++flag_class_idx;
3761 flag_idx = 0;
3762 }
3763
3764 /* If counttrue == nflgs, then all flags have been found. */
3765 return (counttrue == nflgs ? TRUE : FALSE);
3766}
3767
3768/* Checks if operands are in line with relaxable insn. */
3769
3770static bfd_boolean
3771relaxable_operand (const struct arc_relaxable_ins *ins,
3772 const expressionS *tok,
3773 int ntok)
3774{
3775 const enum rlx_operand_type *operand = &ins->operands[0];
3776 int i = 0;
3777
3778 while (*operand != EMPTY)
3779 {
3780 const expressionS *epr = &tok[i];
3781
3782 if (i != 0 && i >= ntok)
3783 return FALSE;
3784
3785 switch (*operand)
3786 {
3787 case IMMEDIATE:
3788 if (!(epr->X_op == O_multiply
3789 || epr->X_op == O_divide
3790 || epr->X_op == O_modulus
3791 || epr->X_op == O_add
3792 || epr->X_op == O_subtract
3793 || epr->X_op == O_symbol))
3794 return FALSE;
3795 break;
3796
3797 case REGISTER_DUP:
3798 if ((i <= 0)
3799 || (epr->X_add_number != tok[i - 1].X_add_number))
3800 return FALSE;
3801 /* Fall through. */
3802 case REGISTER:
3803 if (epr->X_op != O_register)
3804 return FALSE;
3805 break;
3806
3807 case REGISTER_S:
3808 if (epr->X_op != O_register)
3809 return FALSE;
3810
3811 switch (epr->X_add_number)
3812 {
3813 case 0: case 1: case 2: case 3:
3814 case 12: case 13: case 14: case 15:
3815 break;
3816 default:
3817 return FALSE;
3818 }
3819 break;
3820
3821 case REGISTER_NO_GP:
3822 if ((epr->X_op != O_register)
3823 || (epr->X_add_number == 26)) /* 26 is the gp register. */
3824 return FALSE;
3825 break;
3826
3827 case BRACKET:
3828 if (epr->X_op != O_bracket)
3829 return FALSE;
3830 break;
3831
3832 default:
3833 /* Don't understand, bail out. */
3834 return FALSE;
3835 break;
3836 }
3837
3838 ++i;
3839 operand = &ins->operands[i];
3840 }
3841
3842 return (i == ntok ? TRUE : FALSE);
3843}
3844
3845/* Return TRUE if this OPDCODE is a candidate for relaxation. */
3846
3847static bfd_boolean
3848relax_insn_p (const struct arc_opcode *opcode,
3849 const expressionS *tok,
3850 int ntok,
3851 const struct arc_flags *pflags,
3852 int nflg)
3853{
3854 unsigned i;
3855 bfd_boolean rv = FALSE;
3856
3857 /* Check the relaxation table. */
3858 for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
3859 {
3860 const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i];
3861
3862 if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0)
3863 && may_relax_expr (tok[arc_rlx_ins->opcheckidx])
3864 && relaxable_operand (arc_rlx_ins, tok, ntok)
3865 && relaxable_flag (arc_rlx_ins, pflags, nflg))
3866 {
3867 rv = TRUE;
3868 frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
3869 memcpy (&frag_now->tc_frag_data.tok, tok,
3870 sizeof (expressionS) * ntok);
3871 memcpy (&frag_now->tc_frag_data.pflags, pflags,
3872 sizeof (struct arc_flags) * nflg);
3873 frag_now->tc_frag_data.nflg = nflg;
3874 frag_now->tc_frag_data.ntok = ntok;
3875 break;
3876 }
3877 }
3878
3879 return rv;
3880}
3881
886a2506
NC		 3882/* Turn an opcode description and a set of arguments into
3883 an instruction and a fixup. */
3884
3885static void
3886assemble_insn (const struct arc_opcode *opcode,
3887 const expressionS *tok,
3888 int ntok,
3889 const struct arc_flags *pflags,
3890 int nflg,
3891 struct arc_insn *insn)
3892{
3893 const expressionS *reloc_exp = NULL;
bdfe53e3 3894 unsigned long long image;
886a2506
NC		 3895 const unsigned char *argidx;
3896 int i;
3897 int tokidx = 0;
3898 unsigned char pcrel = 0;
3899 bfd_boolean needGOTSymbol;
3900 bfd_boolean has_delay_slot = FALSE;
3901 extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
3902
3903 memset (insn, 0, sizeof (*insn));
3904 image = opcode->opcode;
3905
bdfe53e3 3906 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
886a2506
NC		 3907 frag_now->fr_file, frag_now->fr_line, opcode->name,
3908 opcode->opcode);
3909
3910 /* Handle operands. */
3911 for (argidx = opcode->operands; *argidx; ++argidx)
3912 {
3913 const struct arc_operand *operand = &arc_operands[*argidx];
3914 const expressionS *t = (const expressionS *) 0;
3915
db18dbab 3916 if (ARC_OPERAND_IS_FAKE (operand))
886a2506
NC		 3917 continue;
3918
3919 if (operand->flags & ARC_OPERAND_DUPLICATE)
3920 {
3921 /* Duplicate operand, already inserted. */
3922 tokidx ++;
3923 continue;
3924 }
3925
3926 if (tokidx >= ntok)
3927 {
3928 abort ();
3929 }
3930 else
3931 t = &tok[tokidx++];
3932
3933 /* Regardless if we have a reloc or not mark the instruction
3934 limm if it is the case. */
3935 if (operand->flags & ARC_OPERAND_LIMM)
3936 insn->has_limm = TRUE;
3937
3938 switch (t->X_op)
3939 {
3940 case O_register:
3941 image = insert_operand (image, operand, regno (t->X_add_number),
3942 NULL, 0);
3943 break;
3944
3945 case O_constant:
3946 image = insert_operand (image, operand, t->X_add_number, NULL, 0);
3947 reloc_exp = t;
3948 if (operand->flags & ARC_OPERAND_LIMM)
3949 insn->limm = t->X_add_number;
3950 break;
3951
3952 case O_bracket:
db18dbab
GM		 3953 case O_colon:
3954 case O_addrtype:
3955 /* Ignore brackets, colons, and address types. */
886a2506
NC		 3956 break;
3957
3958 case O_absent:
3959 gas_assert (operand->flags & ARC_OPERAND_IGNORE);
3960 break;
3961
3962 case O_subtract:
3963 /* Maybe register range. */
3964 if ((t->X_add_number == 0)
3965 && contains_register (t->X_add_symbol)
3966 && contains_register (t->X_op_symbol))
3967 {
3968 int regs;
3969
3970 regs = get_register (t->X_add_symbol);
3971 regs <<= 16;
3972 regs |= get_register (t->X_op_symbol);
3973 image = insert_operand (image, operand, regs, NULL, 0);
3974 break;
3975 }
1a0670f3 3976 /* Fall through. */
886a2506
NC		 3977
3978 default:
3979 /* This operand needs a relocation. */
3980 needGOTSymbol = FALSE;
3981
3982 switch (t->X_md)
3983 {
3984 case O_plt:
c810e0b8 3985 if (opcode->insn_class == JUMP)
6e3f3473 3986 as_bad (_("Unable to use @plt relocation for insn %s"),
3987 opcode->name);
886a2506
NC		 3988 needGOTSymbol = TRUE;
3989 reloc = find_reloc ("plt", opcode->name,
3990 pflags, nflg,
3991 operand->default_reloc);
3992 break;
3993
3994 case O_gotoff:
3995 case O_gotpc:
3996 needGOTSymbol = TRUE;
3997 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3998 break;
3999 case O_pcl:
cc07cda6
CZ		 4000 if (operand->flags & ARC_OPERAND_LIMM)
4001 {
4002 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
4003 if (arc_opcode_len (opcode) == 2
4004 || opcode->insn_class == JUMP)
6e3f3473 4005 as_bad (_("Unable to use @pcl relocation for insn %s"),
4006 opcode->name);
cc07cda6
CZ		 4007 }
4008 else
4009 {
4010 /* This is a relaxed operand which initially was
4011 limm, choose whatever we have defined in the
4012 opcode as reloc. */
4013 reloc = operand->default_reloc;
4014 }
886a2506
NC		 4015 break;
4016 case O_sda:
4017 reloc = find_reloc ("sda", opcode->name,
4018 pflags, nflg,
4019 operand->default_reloc);
4020 break;
4021 case O_tlsgd:
4022 case O_tlsie:
4023 needGOTSymbol = TRUE;
4024 /* Fall-through. */
4025
4026 case O_tpoff:
4027 case O_dtpoff:
4028 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
4029 break;
4030
4031 case O_tpoff9: /*FIXME! Check for the conditionality of
4032 the insn. */
4033 case O_dtpoff9: /*FIXME! Check for the conditionality of
4034 the insn. */
4035 as_bad (_("TLS_*_S9 relocs are not supported yet"));
4036 break;
4037
4038 default:
4039 /* Just consider the default relocation. */
4040 reloc = operand->default_reloc;
4041 break;
4042 }
4043
4044 if (needGOTSymbol && (GOT_symbol == NULL))
4045 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4046
4047 reloc_exp = t;
4048
4049#if 0
4050 if (reloc > 0)
4051 {
4052 /* sanity checks. */
4053 reloc_howto_type *reloc_howto
4054 = bfd_reloc_type_lookup (stdoutput,
4055 (bfd_reloc_code_real_type) reloc);
4056 unsigned reloc_bitsize = reloc_howto->bitsize;
4057 if (reloc_howto->rightshift)
4058 reloc_bitsize -= reloc_howto->rightshift;
4059 if (reloc_bitsize != operand->bits)
4060 {
4061 as_bad (_("invalid relocation %s for field"),
4062 bfd_get_reloc_code_name (reloc));
4063 return;
4064 }
4065 }
4066#endif
4067 if (insn->nfixups >= MAX_INSN_FIXUPS)
4068 as_fatal (_("too many fixups"));
4069
4070 struct arc_fixup *fixup;
4071 fixup = &insn->fixups[insn->nfixups++];
4072 fixup->exp = *t;
4073 fixup->reloc = reloc;
cc07cda6
CZ		 4074 if ((int) reloc < 0)
4075 pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
4076 else
4077 {
4078 reloc_howto_type *reloc_howto =
4079 bfd_reloc_type_lookup (stdoutput,
4080 (bfd_reloc_code_real_type) fixup->reloc);
4081 pcrel = reloc_howto->pc_relative;
4082 }
886a2506
NC		 4083 fixup->pcrel = pcrel;
4084 fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ?
4085 TRUE : FALSE;
4086 break;
4087 }
4088 }
4089
4090 /* Handle flags. */
4091 for (i = 0; i < nflg; i++)
4092 {
f36e33da 4093 const struct arc_flag_operand *flg_operand = pflags[i].flgp;
886a2506
NC		 4094
4095 /* Check if the instruction has a delay slot. */
4096 if (!strcmp (flg_operand->name, "d"))
4097 has_delay_slot = TRUE;
4098
2c52e2e8
RZ		 4099 /* There is an exceptional case when we cannot insert a flag just as
4100 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4101 relation with the relative address. Unfortunately, some of the
4102 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4103 handled in the normal way.
4104
4105 Flag operands don't have an architecture field, so we can't
4106 directly validate that FLAG_OPERAND is valid for the current
4107 architecture, what we do instead is just validate that we're
4108 assembling for an ARCv2 architecture. */
4109 if ((selected_cpu.flags & ARC_OPCODE_ARCV2)
4110 && (!strcmp (flg_operand->name, "t")
4111 || !strcmp (flg_operand->name, "nt")))
886a2506
NC		 4112 {
4113 unsigned bitYoperand = 0;
4114 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4115 if (!strcmp (flg_operand->name, "t"))
4116 if (!strcmp (opcode->name, "bbit0")
4117 || !strcmp (opcode->name, "bbit1"))
4118 bitYoperand = arc_NToperand;
4119 else
4120 bitYoperand = arc_Toperand;
4121 else
4122 if (!strcmp (opcode->name, "bbit0")
4123 || !strcmp (opcode->name, "bbit1"))
4124 bitYoperand = arc_Toperand;
4125 else
4126 bitYoperand = arc_NToperand;
4127
4128 gas_assert (reloc_exp != NULL);
4129 if (reloc_exp->X_op == O_constant)
4130 {
4131 /* Check if we have a constant and solved it
4132 immediately. */
4133 offsetT val = reloc_exp->X_add_number;
4134 image |= insert_operand (image, &arc_operands[bitYoperand],
4135 val, NULL, 0);
4136 }
4137 else
4138 {
4139 struct arc_fixup *fixup;
4140
4141 if (insn->nfixups >= MAX_INSN_FIXUPS)
4142 as_fatal (_("too many fixups"));
4143
4144 fixup = &insn->fixups[insn->nfixups++];
4145 fixup->exp = *reloc_exp;
4146 fixup->reloc = -bitYoperand;
4147 fixup->pcrel = pcrel;
4148 fixup->islong = FALSE;
4149 }
4150 }
4151 else
4152 image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
4153 << flg_operand->shift;
4154 }
4155
4670103e
CZ		 4156 insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
4157
91fdca6f 4158 /* Instruction length. */
06fe285f 4159 insn->len = arc_opcode_len (opcode);
886a2506
NC		 4160
4161 insn->insn = image;
4162
4163 /* Update last insn status. */
4164 arc_last_insns[1] = arc_last_insns[0];
4165 arc_last_insns[0].opcode = opcode;
4166 arc_last_insns[0].has_limm = insn->has_limm;
4167 arc_last_insns[0].has_delay_slot = has_delay_slot;
4168
4169 /* Check if the current instruction is legally used. */
4170 if (arc_last_insns[1].has_delay_slot
4171 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
6e3f3473 4172 as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
4173 arc_last_insns[1].opcode->name,
4174 arc_last_insns[0].opcode->name);
cf9bdae9 4175 if (arc_last_insns[1].has_delay_slot
4176 && arc_last_insns[0].has_limm)
4177 as_bad (_("Insn %s has an instruction %s with limm in its delay slot."),
4178 arc_last_insns[1].opcode->name,
4179 arc_last_insns[0].opcode->name);
886a2506
NC		 4180}
4181
886a2506
NC		 4182void
4183arc_handle_align (fragS* fragP)
4184{
4185 if ((fragP)->fr_type == rs_align_code)
4186 {
4187 char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
4188 valueT count = ((fragP)->fr_next->fr_address
4189 - (fragP)->fr_address - (fragP)->fr_fix);
4190
4191 (fragP)->fr_var = 2;
4192
4193 if (count & 1)/* Padding in the gap till the next 2-byte
4194 boundary with 0s. */
4195 {
4196 (fragP)->fr_fix++;
4197 *dest++ = 0;
4198 }
4199 /* Writing nop_s. */
4200 md_number_to_chars (dest, NOP_OPCODE_S, 2);
4201 }
4202}
4203
4204/* Here we decide which fixups can be adjusted to make them relative
4205 to the beginning of the section instead of the symbol. Basically
4206 we need to make sure that the dynamic relocations are done
4207 correctly, so in some cases we force the original symbol to be
4208 used. */
4209
4210int
4211tc_arc_fix_adjustable (fixS *fixP)
4212{
4213
4214 /* Prevent all adjustments to global symbols. */
4215 if (S_IS_EXTERNAL (fixP->fx_addsy))
4216 return 0;
4217 if (S_IS_WEAK (fixP->fx_addsy))
4218 return 0;
4219
4220 /* Adjust_reloc_syms doesn't know about the GOT. */
4221 switch (fixP->fx_r_type)
4222 {
4223 case BFD_RELOC_ARC_GOTPC32:
4224 case BFD_RELOC_ARC_PLT32:
4225 case BFD_RELOC_ARC_S25H_PCREL_PLT:
4226 case BFD_RELOC_ARC_S21H_PCREL_PLT:
4227 case BFD_RELOC_ARC_S25W_PCREL_PLT:
4228 case BFD_RELOC_ARC_S21W_PCREL_PLT:
4229 return 0;
4230
4231 default:
4232 break;
4233 }
4234
841fdfcd 4235 return 1;
886a2506
NC		 4236}
4237
4238/* Compute the reloc type of an expression EXP. */
4239
4240static void
4241arc_check_reloc (expressionS *exp,
4242 bfd_reloc_code_real_type *r_type_p)
4243{
4244 if (*r_type_p == BFD_RELOC_32
4245 && exp->X_op == O_subtract
4246 && exp->X_op_symbol != NULL
8d1015a8 4247 && S_GET_SEGMENT (exp->X_op_symbol) == now_seg)
6f4b1afc 4248 *r_type_p = BFD_RELOC_ARC_32_PCREL;
886a2506
NC		 4249}
4250
4251
4252/* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4253
4254void
4255arc_cons_fix_new (fragS *frag,
4256 int off,
4257 int size,
4258 expressionS *exp,
4259 bfd_reloc_code_real_type r_type)
4260{
4261 r_type = BFD_RELOC_UNUSED;
4262
4263 switch (size)
4264 {
4265 case 1:
4266 r_type = BFD_RELOC_8;
4267 break;
4268
4269 case 2:
4270 r_type = BFD_RELOC_16;
4271 break;
4272
4273 case 3:
4274 r_type = BFD_RELOC_24;
4275 break;
4276
4277 case 4:
4278 r_type = BFD_RELOC_32;
4279 arc_check_reloc (exp, &r_type);
4280 break;
4281
4282 case 8:
4283 r_type = BFD_RELOC_64;
4284 break;
4285
4286 default:
4287 as_bad (_("unsupported BFD relocation size %u"), size);
4288 r_type = BFD_RELOC_UNUSED;
4289 }
4290
4291 fix_new_exp (frag, off, size, exp, 0, r_type);
4292}
4293
4294/* The actual routine that checks the ZOL conditions. */
4295
4296static void
4297check_zol (symbolS *s)
4298{
bb65a718 4299 switch (selected_cpu.mach)
886a2506
NC		 4300 {
4301 case bfd_mach_arc_arcv2:
bb65a718 4302 if (selected_cpu.flags & ARC_OPCODE_ARCv2EM)
886a2506
NC		 4303 return;
4304
4305 if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
4306 || arc_last_insns[1].has_delay_slot)
4307 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4308 S_GET_NAME (s));
4309
4310 break;
4311 case bfd_mach_arc_arc600:
4312
4313 if (is_kernel_insn_p (arc_last_insns[0].opcode))
4314 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4315 S_GET_NAME (s));
4316
4317 if (arc_last_insns[0].has_limm
4318 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
4319 as_bad (_("A jump instruction with long immediate detected at the \
4320end of the ZOL label @%s"), S_GET_NAME (s));
4321
4322 /* Fall through. */
4323 case bfd_mach_arc_arc700:
4324 if (arc_last_insns[0].has_delay_slot)
4325 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4326 S_GET_NAME (s));
4327
4328 break;
4329 default:
4330 break;
4331 }
4332}
4333
4334/* If ZOL end check the last two instruction for illegals. */
4335void
4336arc_frob_label (symbolS * sym)
4337{
4338 if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
4339 check_zol (sym);
4340
4341 dwarf2_emit_label (sym);
ea1562b3 4342}
4670103e
CZ		 4343
4344/* Used because generic relaxation assumes a pc-rel value whilst we
4345 also relax instructions that use an absolute value resolved out of
4346 relative values (if that makes any sense). An example: 'add r1,
4347 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4348 but if they're in the same section we can subtract the section
4349 offset relocation which ends up in a resolved value. So if @.L2 is
4350 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4351 .text + 0x40 = 0x10. */
4352int
4353arc_pcrel_adjust (fragS *fragP)
4354{
cc07cda6
CZ		 4355 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4356 fragP->fr_address, fragP->fr_fix,
4357 fragP->tc_frag_data.pcrel ? "Y" : "N");
4358
4670103e
CZ		 4359 if (!fragP->tc_frag_data.pcrel)
4360 return fragP->fr_address + fragP->fr_fix;
4361
cc07cda6
CZ		 4362 /* Take into account the PCL rounding. */
4363 return (fragP->fr_address + fragP->fr_fix) & 0x03;
4670103e 4364}
726c18e1
CZ		 4365
4366/* Initialize the DWARF-2 unwind information for this procedure. */
4367
4368void
4369tc_arc_frame_initial_instructions (void)
4370{
4371 /* Stack pointer is register 28. */
45a54ee5 4372 cfi_add_CFA_def_cfa (28, 0);
726c18e1
CZ		 4373}
4374
4375int
4376tc_arc_regname_to_dw2regnum (char *regname)
4377{
4378 struct symbol *sym;
4379
629310ab 4380 sym = str_hash_find (arc_reg_hash, regname);
726c18e1
CZ		 4381 if (sym)
4382 return S_GET_VALUE (sym);
4383
4384 return -1;
4385}
37ab9779
CZ		 4386
4387/* Adjust the symbol table. Delete found AUX register symbols. */
4388
4389void
4390arc_adjust_symtab (void)
4391{
4392 symbolS * sym;
4393
4394 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4395 {
4396 /* I've created a symbol during parsing process. Now, remove
4397 the symbol as it is found to be an AUX register. */
4398 if (ARC_GET_FLAG (sym) & ARC_FLAG_AUX)
4399 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
4400 }
4401
4402 /* Now do generic ELF adjustments. */
4403 elf_adjust_symtab ();
4404}
b99747ae
CZ		 4405
4406static void
4407tokenize_extinsn (extInstruction_t *einsn)
4408{
4409 char *p, c;
4410 char *insn_name;
4411 unsigned char major_opcode;
4412 unsigned char sub_opcode;
4413 unsigned char syntax_class = 0;
4414 unsigned char syntax_class_modifiers = 0;
4415 unsigned char suffix_class = 0;
4416 unsigned int i;
4417
4418 SKIP_WHITESPACE ();
4419
4420 /* 1st: get instruction name. */
4421 p = input_line_pointer;
4422 c = get_symbol_name (&p);
4423
4424 insn_name = xstrdup (p);
4425 restore_line_pointer (c);
4426
f02806be 4427 /* Convert to lower case. */
4428 for (p = insn_name; *p; ++p)
4429 *p = TOLOWER (*p);
4430
b99747ae
CZ		 4431 /* 2nd: get major opcode. */
4432 if (*input_line_pointer != ',')
4433 {
4434 as_bad (_("expected comma after instruction name"));
4435 ignore_rest_of_line ();
4436 return;
4437 }
4438 input_line_pointer++;
4439 major_opcode = get_absolute_expression ();
4440
4441 /* 3rd: get sub-opcode. */
4442 SKIP_WHITESPACE ();
4443
4444 if (*input_line_pointer != ',')
4445 {
4446 as_bad (_("expected comma after major opcode"));
4447 ignore_rest_of_line ();
4448 return;
4449 }
4450 input_line_pointer++;
4451 sub_opcode = get_absolute_expression ();
4452
4453 /* 4th: get suffix class. */
4454 SKIP_WHITESPACE ();
4455
4456 if (*input_line_pointer != ',')
4457 {
4458 as_bad ("expected comma after sub opcode");
4459 ignore_rest_of_line ();
4460 return;
4461 }
4462 input_line_pointer++;
4463
4464 while (1)
4465 {
4466 SKIP_WHITESPACE ();
4467
4468 for (i = 0; i < ARRAY_SIZE (suffixclass); i++)
4469 {
4470 if (!strncmp (suffixclass[i].name, input_line_pointer,
4471 suffixclass[i].len))
4472 {
c810e0b8 4473 suffix_class |= suffixclass[i].attr_class;
b99747ae
CZ		 4474 input_line_pointer += suffixclass[i].len;
4475 break;
4476 }
4477 }
4478
4479 if (i == ARRAY_SIZE (suffixclass))
4480 {
4481 as_bad ("invalid suffix class");
4482 ignore_rest_of_line ();
4483 return;
4484 }
4485
4486 SKIP_WHITESPACE ();
4487
4488 if (*input_line_pointer == '|')
4489 input_line_pointer++;
4490 else
4491 break;
4492 }
4493
4494 /* 5th: get syntax class and syntax class modifiers. */
4495 if (*input_line_pointer != ',')
4496 {
4497 as_bad ("expected comma after suffix class");
4498 ignore_rest_of_line ();
4499 return;
4500 }
4501 input_line_pointer++;
4502
4503 while (1)
4504 {
4505 SKIP_WHITESPACE ();
4506
4507 for (i = 0; i < ARRAY_SIZE (syntaxclassmod); i++)
4508 {
4509 if (!strncmp (syntaxclassmod[i].name,
4510 input_line_pointer,
4511 syntaxclassmod[i].len))
4512 {
c810e0b8 4513 syntax_class_modifiers |= syntaxclassmod[i].attr_class;
b99747ae
CZ		 4514 input_line_pointer += syntaxclassmod[i].len;
4515 break;
4516 }
4517 }
4518
4519 if (i == ARRAY_SIZE (syntaxclassmod))
4520 {
4521 for (i = 0; i < ARRAY_SIZE (syntaxclass); i++)
4522 {
4523 if (!strncmp (syntaxclass[i].name,
4524 input_line_pointer,
4525 syntaxclass[i].len))
4526 {
c810e0b8 4527 syntax_class |= syntaxclass[i].attr_class;
b99747ae
CZ		 4528 input_line_pointer += syntaxclass[i].len;
4529 break;
4530 }
4531 }
4532
4533 if (i == ARRAY_SIZE (syntaxclass))
4534 {
4535 as_bad ("missing syntax class");
4536 ignore_rest_of_line ();
4537 return;
4538 }
4539 }
4540
4541 SKIP_WHITESPACE ();
4542
4543 if (*input_line_pointer == '|')
4544 input_line_pointer++;
4545 else
4546 break;
4547 }
4548
4549 demand_empty_rest_of_line ();
4550
4551 einsn->name = insn_name;
4552 einsn->major = major_opcode;
4553 einsn->minor = sub_opcode;
4554 einsn->syntax = syntax_class;
4555 einsn->modsyn = syntax_class_modifiers;
4556 einsn->suffix = suffix_class;
4557 einsn->flags = syntax_class
4558 | (syntax_class_modifiers & ARC_OP1_IMM_IMPLIED ? 0x10 : 0);
4559}
4560
4561/* Generate an extension section. */
4562
4563static int
4564arc_set_ext_seg (void)
4565{
4566 if (!arcext_section)
4567 {
4568 arcext_section = subseg_new (".arcextmap", 0);
fd361982 4569 bfd_set_section_flags (arcext_section, SEC_READONLY | SEC_HAS_CONTENTS);
b99747ae
CZ		 4570 }
4571 else
4572 subseg_set (arcext_section, 0);
4573 return 1;
4574}
4575
4576/* Create an extension instruction description in the arc extension
4577 section of the output file.
4578 The structure for an instruction is like this:
4579 [0]: Length of the record.
4580 [1]: Type of the record.
4581
4582 [2]: Major opcode.
4583 [3]: Sub-opcode.
4584 [4]: Syntax (flags).
4585 [5]+ Name instruction.
4586
4587 The sequence is terminated by an empty entry. */
4588
4589static void
4590create_extinst_section (extInstruction_t *einsn)
4591{
4592
4593 segT old_sec = now_seg;
4594 int old_subsec = now_subseg;
4595 char *p;
4596 int name_len = strlen (einsn->name);
4597
4598 arc_set_ext_seg ();
4599
4600 p = frag_more (1);
4601 *p = 5 + name_len + 1;
4602 p = frag_more (1);
4603 *p = EXT_INSTRUCTION;
4604 p = frag_more (1);
4605 *p = einsn->major;
4606 p = frag_more (1);
4607 *p = einsn->minor;
4608 p = frag_more (1);
4609 *p = einsn->flags;
4610 p = frag_more (name_len + 1);
4611 strcpy (p, einsn->name);
4612
4613 subseg_set (old_sec, old_subsec);
4614}
4615
4616/* Handler .extinstruction pseudo-op. */
4617
4618static void
4619arc_extinsn (int ignore ATTRIBUTE_UNUSED)
4620{
4621 extInstruction_t einsn;
4622 struct arc_opcode *arc_ext_opcodes;
4623 const char *errmsg = NULL;
4624 unsigned char moplow, mophigh;
4625
4626 memset (&einsn, 0, sizeof (einsn));
4627 tokenize_extinsn (&einsn);
4628
4629 /* Check if the name is already used. */
4630 if (arc_find_opcode (einsn.name))
4631 as_warn (_("Pseudocode already used %s"), einsn.name);
4632
4633 /* Check the opcode ranges. */
4634 moplow = 0x05;
bb65a718
AB		 4635 mophigh = (selected_cpu.flags & (ARC_OPCODE_ARCv2EM
4636 | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
b99747ae
CZ		 4637
4638 if ((einsn.major > mophigh) || (einsn.major < moplow))
4639 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh);
4640
4641 if ((einsn.minor > 0x3f) && (einsn.major != 0x0a)
4642 && (einsn.major != 5) && (einsn.major != 9))
4643 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4644
945e0f82 4645 switch (einsn.syntax & ARC_SYNTAX_MASK)
b99747ae
CZ		 4646 {
4647 case ARC_SYNTAX_3OP:
4648 if (einsn.modsyn & ARC_OP1_IMM_IMPLIED)
4649 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4650 break;
4651 case ARC_SYNTAX_2OP:
945e0f82
CZ		 4652 case ARC_SYNTAX_1OP:
4653 case ARC_SYNTAX_NOP:
b99747ae
CZ		 4654 if (einsn.modsyn & ARC_OP1_MUST_BE_IMM)
4655 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4656 break;
4657 default:
4658 break;
4659 }
4660
bb65a718 4661 arc_ext_opcodes = arcExtMap_genOpcode (&einsn, selected_cpu.flags, &errmsg);
b99747ae
CZ		 4662 if (arc_ext_opcodes == NULL)
4663 {
4664 if (errmsg)
4665 as_fatal ("%s", errmsg);
4666 else
4667 as_fatal (_("Couldn't generate extension instruction opcodes"));
4668 }
4669 else if (errmsg)
4670 as_warn ("%s", errmsg);
4671
4672 /* Insert the extension instruction. */
4673 arc_insert_opcode ((const struct arc_opcode *) arc_ext_opcodes);
4674
4675 create_extinst_section (&einsn);
4676}
4677
06911889 4678static bfd_boolean
f36e33da
CZ		 4679tokenize_extregister (extRegister_t *ereg, int opertype)
4680{
4681 char *name;
4682 char *mode;
4683 char c;
4684 char *p;
4685 int number, imode = 0;
4686 bfd_boolean isCore_p = (opertype == EXT_CORE_REGISTER) ? TRUE : FALSE;
4687 bfd_boolean isReg_p = (opertype == EXT_CORE_REGISTER
4688 || opertype == EXT_AUX_REGISTER) ? TRUE : FALSE;
4689
4690 /* 1st: get register name. */
4691 SKIP_WHITESPACE ();
4692 p = input_line_pointer;
4693 c = get_symbol_name (&p);
4694
4695 name = xstrdup (p);
4696 restore_line_pointer (c);
4697
4698 /* 2nd: get register number. */
4699 SKIP_WHITESPACE ();
4700
4701 if (*input_line_pointer != ',')
4702 {
06911889 4703 as_bad (_("expected comma after name"));
f36e33da
CZ		 4704 ignore_rest_of_line ();
4705 free (name);
06911889 4706 return FALSE;
f36e33da
CZ		 4707 }
4708 input_line_pointer++;
4709 number = get_absolute_expression ();
4710
06911889
CZ		 4711 if ((number < 0)
4712 && (opertype != EXT_AUX_REGISTER))
f36e33da 4713 {
06911889
CZ		 4714 as_bad (_("%s second argument cannot be a negative number %d"),
4715 isCore_p ? "extCoreRegister's" : "extCondCode's",
4716 number);
f36e33da
CZ		 4717 ignore_rest_of_line ();
4718 free (name);
06911889 4719 return FALSE;
f36e33da
CZ		 4720 }
4721
4722 if (isReg_p)
4723 {
4724 /* 3rd: get register mode. */
4725 SKIP_WHITESPACE ();
4726
4727 if (*input_line_pointer != ',')
4728 {
4729 as_bad (_("expected comma after register number"));
4730 ignore_rest_of_line ();
4731 free (name);
06911889 4732 return FALSE;
f36e33da
CZ		 4733 }
4734
4735 input_line_pointer++;
4736 mode = input_line_pointer;
4737
4738 if (!strncmp (mode, "r|w", 3))
4739 {
4740 imode = 0;
4741 input_line_pointer += 3;
4742 }
4743 else if (!strncmp (mode, "r", 1))
4744 {
4745 imode = ARC_REGISTER_READONLY;
4746 input_line_pointer += 1;
4747 }
4748 else if (strncmp (mode, "w", 1))
4749 {
4750 as_bad (_("invalid mode"));
4751 ignore_rest_of_line ();
4752 free (name);
06911889 4753 return FALSE;
f36e33da
CZ		 4754 }
4755 else
4756 {
4757 imode = ARC_REGISTER_WRITEONLY;
4758 input_line_pointer += 1;
4759 }
4760 }
4761
4762 if (isCore_p)
4763 {
4764 /* 4th: get core register shortcut. */
4765 SKIP_WHITESPACE ();
4766 if (*input_line_pointer != ',')
4767 {
4768 as_bad (_("expected comma after register mode"));
4769 ignore_rest_of_line ();
4770 free (name);
06911889 4771 return FALSE;
f36e33da
CZ		 4772 }
4773
4774 input_line_pointer++;
4775
4776 if (!strncmp (input_line_pointer, "cannot_shortcut", 15))
4777 {
4778 imode |= ARC_REGISTER_NOSHORT_CUT;
4779 input_line_pointer += 15;
4780 }
4781 else if (strncmp (input_line_pointer, "can_shortcut", 12))
4782 {
4783 as_bad (_("shortcut designator invalid"));
4784 ignore_rest_of_line ();
4785 free (name);
06911889 4786 return FALSE;
f36e33da
CZ		 4787 }
4788 else
4789 {
4790 input_line_pointer += 12;
4791 }
4792 }
4793 demand_empty_rest_of_line ();
4794
4795 ereg->name = name;
4796 ereg->number = number;
4797 ereg->imode = imode;
06911889 4798 return TRUE;
f36e33da
CZ		 4799}
4800
4801/* Create an extension register/condition description in the arc
4802 extension section of the output file.
4803
4804 The structure for an instruction is like this:
4805 [0]: Length of the record.
4806 [1]: Type of the record.
4807
4808 For core regs and condition codes:
4809 [2]: Value.
4810 [3]+ Name.
4811
33eaf5de 4812 For auxiliary registers:
f36e33da
CZ		 4813 [2..5]: Value.
4814 [6]+ Name
4815
4816 The sequence is terminated by an empty entry. */
4817
4818static void
4819create_extcore_section (extRegister_t *ereg, int opertype)
4820{
4821 segT old_sec = now_seg;
4822 int old_subsec = now_subseg;
4823 char *p;
4824 int name_len = strlen (ereg->name);
4825
4826 arc_set_ext_seg ();
4827
4828 switch (opertype)
4829 {
4830 case EXT_COND_CODE:
4831 case EXT_CORE_REGISTER:
4832 p = frag_more (1);
4833 *p = 3 + name_len + 1;
4834 p = frag_more (1);
4835 *p = opertype;
4836 p = frag_more (1);
4837 *p = ereg->number;
4838 break;
4839 case EXT_AUX_REGISTER:
4840 p = frag_more (1);
4841 *p = 6 + name_len + 1;
4842 p = frag_more (1);
4843 *p = EXT_AUX_REGISTER;
4844 p = frag_more (1);
4845 *p = (ereg->number >> 24) & 0xff;
4846 p = frag_more (1);
4847 *p = (ereg->number >> 16) & 0xff;
4848 p = frag_more (1);
4849 *p = (ereg->number >> 8) & 0xff;
4850 p = frag_more (1);
4851 *p = (ereg->number) & 0xff;
4852 break;
4853 default:
4854 break;
4855 }
4856
4857 p = frag_more (name_len + 1);
4858 strcpy (p, ereg->name);
4859
4860 subseg_set (old_sec, old_subsec);
4861}
4862
4863/* Handler .extCoreRegister pseudo-op. */
4864
4865static void
4866arc_extcorereg (int opertype)
4867{
4868 extRegister_t ereg;
4869 struct arc_aux_reg *auxr;
f36e33da
CZ		 4870 struct arc_flag_operand *ccode;
4871
4872 memset (&ereg, 0, sizeof (ereg));
06911889
CZ		 4873 if (!tokenize_extregister (&ereg, opertype))
4874 return;
f36e33da
CZ		 4875
4876 switch (opertype)
4877 {
4878 case EXT_CORE_REGISTER:
4879 /* Core register. */
4880 if (ereg.number > 60)
4881 as_bad (_("core register %s value (%d) too large"), ereg.name,
4882 ereg.number);
4883 declare_register (ereg.name, ereg.number);
4884 break;
4885 case EXT_AUX_REGISTER:
4886 /* Auxiliary register. */
add39d23 4887 auxr = XNEW (struct arc_aux_reg);
f36e33da 4888 auxr->name = ereg.name;
bb65a718 4889 auxr->cpu = selected_cpu.flags;
f36e33da
CZ		 4890 auxr->subclass = NONE;
4891 auxr->address = ereg.number;
629310ab 4892 str_hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
f36e33da
CZ		 4893 break;
4894 case EXT_COND_CODE:
4895 /* Condition code. */
4896 if (ereg.number > 31)
4897 as_bad (_("condition code %s value (%d) too large"), ereg.name,
4898 ereg.number);
4899 ext_condcode.size ++;
4900 ext_condcode.arc_ext_condcode =
add39d23
TS		 4901 XRESIZEVEC (struct arc_flag_operand, ext_condcode.arc_ext_condcode,
4902 ext_condcode.size + 1);
f36e33da
CZ		 4903 if (ext_condcode.arc_ext_condcode == NULL)
4904 as_fatal (_("Virtual memory exhausted"));
4905
4906 ccode = ext_condcode.arc_ext_condcode + ext_condcode.size - 1;
4907 ccode->name = ereg.name;
4908 ccode->code = ereg.number;
4909 ccode->bits = 5;
4910 ccode->shift = 0;
4911 ccode->favail = 0; /* not used. */
4912 ccode++;
4913 memset (ccode, 0, sizeof (struct arc_flag_operand));
4914 break;
4915 default:
4916 as_bad (_("Unknown extension"));
4917 break;
4918 }
4919 create_extcore_section (&ereg, opertype);
4920}
4921
53a346d8
CZ		 4922/* Parse a .arc_attribute directive. */
4923
4924static void
4925arc_attribute (int ignored ATTRIBUTE_UNUSED)
4926{
4927 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4928
4929 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4930 attributes_set_explicitly[tag] = TRUE;
4931}
4932
4933/* Set an attribute if it has not already been set by the user. */
4934
4935static void
4936arc_set_attribute_int (int tag, int value)
4937{
4938 if (tag < 1
4939 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4940 || !attributes_set_explicitly[tag])
4941 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
4942}
4943
4944static void
4945arc_set_attribute_string (int tag, const char *value)
4946{
4947 if (tag < 1
4948 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4949 || !attributes_set_explicitly[tag])
4950 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
4951}
4952
4953/* Allocate and concatenate two strings. s1 can be NULL but not
4954 s2. s1 pointer is freed at end of this procedure. */
4955
4956static char *
4957arc_stralloc (char * s1, const char * s2)
4958{
4959 char * p;
4960 int len = 0;
4961
4962 if (s1)
4963 len = strlen (s1) + 1;
4964
4965 /* Only s1 can be null. */
4966 gas_assert (s2);
4967 len += strlen (s2) + 1;
4968
4969 p = (char *) xmalloc (len);
4970 if (p == NULL)
4971 as_fatal (_("Virtual memory exhausted"));
4972
4973 if (s1)
4974 {
4975 strcpy (p, s1);
4976 strcat (p, ",");
4977 strcat (p, s2);
4978 free (s1);
4979 }
4980 else
4981 strcpy (p, s2);
4982
4983 return p;
4984}
4985
4986/* Set the public ARC object attributes. */
4987
4988static void
4989arc_set_public_attributes (void)
4990{
4991 int base = 0;
4992 char *s = NULL;
4993 unsigned int i;
4994
4995 /* Tag_ARC_CPU_name. */
4996 arc_set_attribute_string (Tag_ARC_CPU_name, selected_cpu.name);
4997
4998 /* Tag_ARC_CPU_base. */
4999 switch (selected_cpu.eflags & EF_ARC_MACH_MSK)
5000 {
5001 case E_ARC_MACH_ARC600:
5002 case E_ARC_MACH_ARC601:
5003 base = TAG_CPU_ARC6xx;
5004 break;
5005 case E_ARC_MACH_ARC700:
5006 base = TAG_CPU_ARC7xx;
5007 break;
5008 case EF_ARC_CPU_ARCV2EM:
5009 base = TAG_CPU_ARCEM;
5010 break;
5011 case EF_ARC_CPU_ARCV2HS:
5012 base = TAG_CPU_ARCHS;
5013 break;
5014 default:
5015 base = 0;
5016 break;
5017 }
5018 if (attributes_set_explicitly[Tag_ARC_CPU_base]
5019 && (base != bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
5020 Tag_ARC_CPU_base)))
5021 as_warn (_("Overwrite explicitly set Tag_ARC_CPU_base"));
5022 bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_CPU_base, base);
5023
5024 /* Tag_ARC_ABI_osver. */
5025 if (attributes_set_explicitly[Tag_ARC_ABI_osver])
5026 {
5027 int val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
5028 Tag_ARC_ABI_osver);
5029
5030 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_OSABI_MSK)
5031 | (val & 0x0f << 8));
5032 }
5033 else
5034 {
5035 arc_set_attribute_int (Tag_ARC_ABI_osver, E_ARC_OSABI_CURRENT >> 8);
5036 }
5037
5038 /* Tag_ARC_ISA_config. */
5039 arc_check_feature();
5040
5041 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
5042 if (selected_cpu.features & feature_list[i].feature)
5043 s = arc_stralloc (s, feature_list[i].attr);
5044
5045 if (s)
5046 arc_set_attribute_string (Tag_ARC_ISA_config, s);
5047
5048 /* Tag_ARC_ISA_mpy_option. */
5049 arc_set_attribute_int (Tag_ARC_ISA_mpy_option, mpy_option);
5050
5051 /* Tag_ARC_ABI_pic. */
5052 arc_set_attribute_int (Tag_ARC_ABI_pic, pic_option);
5053
5054 /* Tag_ARC_ABI_sda. */
5055 arc_set_attribute_int (Tag_ARC_ABI_sda, sda_option);
5056
5057 /* Tag_ARC_ABI_tls. */
5058 arc_set_attribute_int (Tag_ARC_ABI_tls, tls_option);
db1e1b45 5059
5060 /* Tag_ARC_ATR_version. */
5061 arc_set_attribute_int (Tag_ARC_ATR_version, 1);
63741043 5062
5063 /* Tag_ARC_ABI_rf16. */
5064 if (attributes_set_explicitly[Tag_ARC_ABI_rf16]
5065 && bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
5066 Tag_ARC_ABI_rf16)
5067 && !rf16_only)
5068 {
5069 as_warn (_("Overwrite explicitly set Tag_ARC_ABI_rf16 to full "
5070 "register file"));
5071 bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_ABI_rf16, 0);
5072 }
53a346d8
CZ		 5073}
5074
5075/* Add the default contents for the .ARC.attributes section. */
5076
5077void
5078arc_md_end (void)
5079{
5080 arc_set_public_attributes ();
5081
5082 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
5083 as_fatal (_("could not set architecture and machine"));
5084
5085 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
5086}
5087
5088void arc_copy_symbol_attributes (symbolS *dest, symbolS *src)
5089{
5090 ARC_GET_FLAG (dest) = ARC_GET_FLAG (src);
5091}
5092
5093int arc_convert_symbolic_attribute (const char *name)
5094{
5095 static const struct
5096 {
5097 const char * name;
5098 const int tag;
5099 }
5100 attribute_table[] =
5101 {
5102#define T(tag) {#tag, tag}
5103 T (Tag_ARC_PCS_config),
5104 T (Tag_ARC_CPU_base),
5105 T (Tag_ARC_CPU_variation),
5106 T (Tag_ARC_CPU_name),
5107 T (Tag_ARC_ABI_rf16),
5108 T (Tag_ARC_ABI_osver),
5109 T (Tag_ARC_ABI_sda),
5110 T (Tag_ARC_ABI_pic),
5111 T (Tag_ARC_ABI_tls),
5112 T (Tag_ARC_ABI_enumsize),
5113 T (Tag_ARC_ABI_exceptions),
5114 T (Tag_ARC_ABI_double_size),
5115 T (Tag_ARC_ISA_config),
5116 T (Tag_ARC_ISA_apex),
db1e1b45 5117 T (Tag_ARC_ISA_mpy_option),
5118 T (Tag_ARC_ATR_version)
53a346d8
CZ		 5119#undef T
5120 };
5121 unsigned int i;
5122
5123 if (name == NULL)
5124 return -1;
5125
5126 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
5127 if (streq (name, attribute_table[i].name))
5128 return attribute_table[i].tag;
5129
5130 return -1;
5131}
5132
b99747ae
CZ		 5133/* Local variables:
5134 eval: (c-set-style "gnu")
5135 indent-tabs-mode: t
5136 End: */
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