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b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
f17c130b AM |
2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, |
3 | 2004, 2005 | |
b99bd4ef NC |
4 | Free Software Foundation, Inc. |
5 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) | |
6 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 7 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
8 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
9 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
10 | |
11 | This file is part of GAS, the GNU Assembler. | |
12 | ||
13 | GAS is free software; you can redistribute it and/or modify | |
14 | it under the terms of the GNU General Public License as published by | |
15 | the Free Software Foundation; either version 2, or (at your option) | |
16 | any later version. | |
17 | ||
18 | GAS is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
21 | GNU General Public License for more details. |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
24 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
25 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
26 | 02110-1301, USA. */ | |
b99bd4ef | 27 | |
b99bd4ef | 28 | #include <string.h> |
c19d1205 | 29 | #define NO_RELOC 0 |
b99bd4ef | 30 | #include "as.h" |
3882b010 | 31 | #include "safe-ctype.h" |
b99bd4ef NC |
32 | |
33 | /* Need TARGET_CPU. */ | |
34 | #include "config.h" | |
35 | #include "subsegs.h" | |
36 | #include "obstack.h" | |
37 | #include "symbols.h" | |
38 | #include "listing.h" | |
39 | ||
f263249b RE |
40 | #include "opcode/arm.h" |
41 | ||
b99bd4ef NC |
42 | #ifdef OBJ_ELF |
43 | #include "elf/arm.h" | |
44 | #include "dwarf2dbg.h" | |
a394c00f | 45 | #include "dw2gencfi.h" |
b99bd4ef NC |
46 | #endif |
47 | ||
7ed4c4c5 | 48 | /* XXX Set this to 1 after the next binutils release. */ |
03b1477f RE |
49 | #define WARN_DEPRECATED 0 |
50 | ||
7ed4c4c5 NC |
51 | #ifdef OBJ_ELF |
52 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
53 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
54 | ||
55 | /* This structure holds the unwinding state. */ | |
56 | ||
57 | static struct | |
58 | { | |
c19d1205 ZW |
59 | symbolS * proc_start; |
60 | symbolS * table_entry; | |
61 | symbolS * personality_routine; | |
62 | int personality_index; | |
7ed4c4c5 | 63 | /* The segment containing the function. */ |
c19d1205 ZW |
64 | segT saved_seg; |
65 | subsegT saved_subseg; | |
7ed4c4c5 NC |
66 | /* Opcodes generated from this function. */ |
67 | unsigned char * opcodes; | |
c19d1205 ZW |
68 | int opcode_count; |
69 | int opcode_alloc; | |
7ed4c4c5 | 70 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 71 | offsetT frame_size; |
7ed4c4c5 NC |
72 | /* We don't add stack adjustment opcodes immediately so that we can merge |
73 | multiple adjustments. We can also omit the final adjustment | |
74 | when using a frame pointer. */ | |
c19d1205 | 75 | offsetT pending_offset; |
7ed4c4c5 | 76 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
77 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
78 | offsetT fp_offset; | |
79 | int fp_reg; | |
7ed4c4c5 | 80 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 81 | unsigned fp_used:1; |
7ed4c4c5 | 82 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 83 | unsigned sp_restored:1; |
7ed4c4c5 NC |
84 | } unwind; |
85 | ||
84798bd6 JB |
86 | /* Bit N indicates that an R_ARM_NONE relocation has been output for |
87 | __aeabi_unwind_cpp_prN already if set. This enables dependencies to be | |
88 | emitted only once per section, to save unnecessary bloat. */ | |
89 | static unsigned int marked_pr_dependency = 0; | |
90 | ||
7ed4c4c5 NC |
91 | #endif /* OBJ_ELF */ |
92 | ||
33a392fb PB |
93 | enum arm_float_abi |
94 | { | |
95 | ARM_FLOAT_ABI_HARD, | |
96 | ARM_FLOAT_ABI_SOFTFP, | |
97 | ARM_FLOAT_ABI_SOFT | |
98 | }; | |
99 | ||
c19d1205 | 100 | /* Types of processor to assemble for. */ |
b89dddec RE |
101 | #define ARM_1 ARM_ARCH_V1 |
102 | #define ARM_2 ARM_ARCH_V2 | |
103 | #define ARM_3 ARM_ARCH_V2S | |
104 | #define ARM_250 ARM_ARCH_V2S | |
105 | #define ARM_6 ARM_ARCH_V3 | |
106 | #define ARM_7 ARM_ARCH_V3 | |
107 | #define ARM_8 ARM_ARCH_V4 | |
108 | #define ARM_9 ARM_ARCH_V4T | |
109 | #define ARM_STRONG ARM_ARCH_V4 | |
c19d1205 | 110 | #define ARM_CPU_MASK 0x0000000f /* XXX? */ |
b99bd4ef NC |
111 | |
112 | #ifndef CPU_DEFAULT | |
113 | #if defined __XSCALE__ | |
b89dddec | 114 | #define CPU_DEFAULT (ARM_ARCH_XSCALE) |
b99bd4ef NC |
115 | #else |
116 | #if defined __thumb__ | |
c19d1205 | 117 | #define CPU_DEFAULT (ARM_ARCH_V5T) |
b99bd4ef | 118 | #else |
c19d1205 | 119 | #define CPU_DEFAULT ARM_ANY |
b99bd4ef NC |
120 | #endif |
121 | #endif | |
122 | #endif | |
123 | ||
124 | #ifndef FPU_DEFAULT | |
c820d418 MM |
125 | # ifdef TE_LINUX |
126 | # define FPU_DEFAULT FPU_ARCH_FPA | |
127 | # elif defined (TE_NetBSD) | |
128 | # ifdef OBJ_ELF | |
129 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
130 | # else | |
131 | /* Legacy a.out format. */ | |
132 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
133 | # endif | |
4e7fd91e PB |
134 | # elif defined (TE_VXWORKS) |
135 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
136 | # else |
137 | /* For backwards compatibility, default to FPA. */ | |
138 | # define FPU_DEFAULT FPU_ARCH_FPA | |
139 | # endif | |
140 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 141 | |
c19d1205 | 142 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 143 | |
03b1477f | 144 | static unsigned long cpu_variant; |
b99bd4ef | 145 | |
b99bd4ef | 146 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
147 | static int uses_apcs_26 = FALSE; |
148 | static int atpcs = FALSE; | |
b34976b6 AM |
149 | static int support_interwork = FALSE; |
150 | static int uses_apcs_float = FALSE; | |
c19d1205 | 151 | static int pic_code = FALSE; |
03b1477f RE |
152 | |
153 | /* Variables that we set while parsing command-line options. Once all | |
154 | options have been read we re-process these values to set the real | |
155 | assembly flags. */ | |
156 | static int legacy_cpu = -1; | |
157 | static int legacy_fpu = -1; | |
158 | ||
159 | static int mcpu_cpu_opt = -1; | |
160 | static int mcpu_fpu_opt = -1; | |
161 | static int march_cpu_opt = -1; | |
162 | static int march_fpu_opt = -1; | |
163 | static int mfpu_opt = -1; | |
33a392fb | 164 | static int mfloat_abi_opt = -1; |
7cc69913 | 165 | #ifdef OBJ_ELF |
deeaaff8 DJ |
166 | # ifdef EABI_DEFAULT |
167 | static int meabi_flags = EABI_DEFAULT; | |
168 | # else | |
d507cf36 | 169 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 170 | # endif |
7cc69913 | 171 | #endif |
b99bd4ef | 172 | |
b99bd4ef | 173 | #ifdef OBJ_ELF |
c19d1205 | 174 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
175 | symbolS * GOT_symbol; |
176 | #endif | |
177 | ||
b99bd4ef NC |
178 | /* 0: assemble for ARM, |
179 | 1: assemble for Thumb, | |
180 | 2: assemble for Thumb even though target CPU does not support thumb | |
181 | instructions. */ | |
182 | static int thumb_mode = 0; | |
183 | ||
c19d1205 ZW |
184 | /* If unified_syntax is true, we are processing the new unified |
185 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
186 | ||
187 | - Immediate operands do not require a # prefix. | |
188 | - Conditional affixes always appear at the end of the | |
189 | instruction. (For backward compatibility, those instructions | |
190 | that formerly had them in the middle, continue to accept them | |
191 | there.) | |
192 | - The IT instruction may appear, and if it does is validated | |
193 | against subsequent conditional affixes. It does not generate | |
194 | machine code. | |
195 | ||
196 | Important differences from the old Thumb mode: | |
197 | ||
198 | - Immediate operands do not require a # prefix. | |
199 | - Most of the V6T2 instructions are only available in unified mode. | |
200 | - The .N and .W suffixes are recognized and honored (it is an error | |
201 | if they cannot be honored). | |
202 | - All instructions set the flags if and only if they have an 's' affix. | |
203 | - Conditional affixes may be used. They are validated against | |
204 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
205 | conditional affix except in the scope of an IT instruction. */ | |
206 | ||
207 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef NC |
208 | |
209 | struct arm_it | |
210 | { | |
c19d1205 | 211 | const char * error; |
b99bd4ef | 212 | unsigned long instruction; |
c19d1205 ZW |
213 | int size; |
214 | int size_req; | |
215 | int cond; | |
0110f2b8 PB |
216 | /* Set to the opcode if the instruction needs relaxation. |
217 | Zero if the instruction is not relaxed. */ | |
218 | unsigned long relax; | |
b99bd4ef NC |
219 | struct |
220 | { | |
221 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
222 | expressionS exp; |
223 | int pc_rel; | |
b99bd4ef | 224 | } reloc; |
b99bd4ef | 225 | |
c19d1205 ZW |
226 | struct |
227 | { | |
228 | unsigned reg; | |
ca3f61f7 NC |
229 | signed int imm; |
230 | unsigned present : 1; /* Operand present. */ | |
231 | unsigned isreg : 1; /* Operand was a register. */ | |
232 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
233 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ | |
234 | unsigned writeback : 1; /* Operand has trailing ! */ | |
235 | unsigned preind : 1; /* Preindexed address. */ | |
236 | unsigned postind : 1; /* Postindexed address. */ | |
237 | unsigned negative : 1; /* Index register was negated. */ | |
238 | unsigned shifted : 1; /* Shift applied to operation. */ | |
239 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
c19d1205 | 240 | } operands[6]; |
b99bd4ef NC |
241 | }; |
242 | ||
c19d1205 | 243 | static struct arm_it inst; |
b99bd4ef NC |
244 | |
245 | #define NUM_FLOAT_VALS 8 | |
246 | ||
05d2d07e | 247 | const char * fp_const[] = |
b99bd4ef NC |
248 | { |
249 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
250 | }; | |
251 | ||
c19d1205 | 252 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
253 | #define MAX_LITTLENUMS 6 |
254 | ||
255 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
256 | ||
257 | #define FAIL (-1) | |
258 | #define SUCCESS (0) | |
259 | ||
260 | #define SUFF_S 1 | |
261 | #define SUFF_D 2 | |
262 | #define SUFF_E 3 | |
263 | #define SUFF_P 4 | |
264 | ||
c19d1205 ZW |
265 | #define CP_T_X 0x00008000 |
266 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 267 | |
c19d1205 ZW |
268 | #define CONDS_BIT 0x00100000 |
269 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
270 | |
271 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
272 | ||
273 | struct asm_cond | |
274 | { | |
c19d1205 | 275 | const char * template; |
b99bd4ef NC |
276 | unsigned long value; |
277 | }; | |
278 | ||
c19d1205 | 279 | #define COND_ALWAYS 0xE |
b99bd4ef | 280 | |
b99bd4ef NC |
281 | struct asm_psr |
282 | { | |
b34976b6 | 283 | const char *template; |
b99bd4ef NC |
284 | unsigned long field; |
285 | }; | |
286 | ||
2d2255b5 | 287 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
288 | #define SPSR_BIT (1 << 22) |
289 | ||
c19d1205 ZW |
290 | /* The individual PSR flag bits. */ |
291 | #define PSR_c (1 << 16) | |
292 | #define PSR_x (1 << 17) | |
293 | #define PSR_s (1 << 18) | |
294 | #define PSR_f (1 << 19) | |
b99bd4ef | 295 | |
c19d1205 | 296 | struct reloc_entry |
bfae80f2 | 297 | { |
c19d1205 ZW |
298 | char *name; |
299 | bfd_reloc_code_real_type reloc; | |
bfae80f2 RE |
300 | }; |
301 | ||
302 | enum vfp_sp_reg_pos | |
303 | { | |
304 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn | |
305 | }; | |
306 | ||
307 | enum vfp_ldstm_type | |
308 | { | |
309 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
310 | }; | |
311 | ||
c19d1205 ZW |
312 | /* ARM register categories. This includes coprocessor numbers and various |
313 | architecture extensions' registers. */ | |
314 | enum arm_reg_type | |
bfae80f2 | 315 | { |
c19d1205 ZW |
316 | REG_TYPE_RN, |
317 | REG_TYPE_CP, | |
318 | REG_TYPE_CN, | |
319 | REG_TYPE_FN, | |
320 | REG_TYPE_VFS, | |
321 | REG_TYPE_VFD, | |
322 | REG_TYPE_VFC, | |
323 | REG_TYPE_MVF, | |
324 | REG_TYPE_MVD, | |
325 | REG_TYPE_MVFX, | |
326 | REG_TYPE_MVDX, | |
327 | REG_TYPE_MVAX, | |
328 | REG_TYPE_DSPSC, | |
329 | REG_TYPE_MMXWR, | |
330 | REG_TYPE_MMXWC, | |
331 | REG_TYPE_MMXWCG, | |
332 | REG_TYPE_XSCALE, | |
bfae80f2 RE |
333 | }; |
334 | ||
6c43fab6 RE |
335 | /* Structure for a hash table entry for a register. */ |
336 | struct reg_entry | |
337 | { | |
c19d1205 ZW |
338 | const char *name; |
339 | unsigned char number; | |
340 | unsigned char type; | |
341 | unsigned char builtin; | |
6c43fab6 RE |
342 | }; |
343 | ||
c19d1205 ZW |
344 | /* Diagnostics used when we don't get a register of the expected type. */ |
345 | const char *const reg_expected_msgs[] = | |
346 | { | |
347 | N_("ARM register expected"), | |
348 | N_("bad or missing co-processor number"), | |
349 | N_("co-processor register expected"), | |
350 | N_("FPA register expected"), | |
351 | N_("VFP single precision register expected"), | |
352 | N_("VFP double precision register expected"), | |
353 | N_("VFP system register expected"), | |
354 | N_("Maverick MVF register expected"), | |
355 | N_("Maverick MVD register expected"), | |
356 | N_("Maverick MVFX register expected"), | |
357 | N_("Maverick MVDX register expected"), | |
358 | N_("Maverick MVAX register expected"), | |
359 | N_("Maverick DSPSC register expected"), | |
360 | N_("iWMMXt data register expected"), | |
361 | N_("iWMMXt control register expected"), | |
362 | N_("iWMMXt scalar register expected"), | |
363 | N_("XScale accumulator register expected"), | |
6c43fab6 RE |
364 | }; |
365 | ||
c19d1205 ZW |
366 | /* Some well known registers that we refer to directly elsewhere. */ |
367 | #define REG_SP 13 | |
368 | #define REG_LR 14 | |
369 | #define REG_PC 15 | |
404ff6b5 | 370 | |
b99bd4ef NC |
371 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
372 | take 2: */ | |
c19d1205 | 373 | #define INSN_SIZE 4 |
b99bd4ef NC |
374 | |
375 | struct asm_opcode | |
376 | { | |
377 | /* Basic string to match. */ | |
c19d1205 ZW |
378 | const char *template; |
379 | ||
380 | /* Parameters to instruction. */ | |
381 | unsigned char operands[8]; | |
382 | ||
383 | /* Conditional tag - see opcode_lookup. */ | |
384 | unsigned int tag : 4; | |
b99bd4ef NC |
385 | |
386 | /* Basic instruction code. */ | |
c19d1205 | 387 | unsigned int avalue : 28; |
b99bd4ef | 388 | |
c19d1205 ZW |
389 | /* Thumb-format instruction code. */ |
390 | unsigned int tvalue; | |
b99bd4ef | 391 | |
90e4755a | 392 | /* Which architecture variant provides this instruction. */ |
c19d1205 ZW |
393 | unsigned long avariant; |
394 | unsigned long tvariant; | |
395 | ||
396 | /* Function to call to encode instruction in ARM format. */ | |
397 | void (* aencode) (void); | |
b99bd4ef | 398 | |
c19d1205 ZW |
399 | /* Function to call to encode instruction in Thumb format. */ |
400 | void (* tencode) (void); | |
b99bd4ef NC |
401 | }; |
402 | ||
a737bd4d NC |
403 | /* Defines for various bits that we will want to toggle. */ |
404 | #define INST_IMMEDIATE 0x02000000 | |
405 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 406 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
407 | #define SHIFT_BY_REG 0x00000010 |
408 | #define PRE_INDEX 0x01000000 | |
409 | #define INDEX_UP 0x00800000 | |
410 | #define WRITE_BACK 0x00200000 | |
411 | #define LDM_TYPE_2_OR_3 0x00400000 | |
90e4755a | 412 | |
a737bd4d NC |
413 | #define LITERAL_MASK 0xf000f000 |
414 | #define OPCODE_MASK 0xfe1fffff | |
415 | #define V4_STR_BIT 0x00000020 | |
90e4755a | 416 | |
a737bd4d | 417 | #define DATA_OP_SHIFT 21 |
90e4755a | 418 | |
a737bd4d NC |
419 | /* Codes to distinguish the arithmetic instructions. */ |
420 | #define OPCODE_AND 0 | |
421 | #define OPCODE_EOR 1 | |
422 | #define OPCODE_SUB 2 | |
423 | #define OPCODE_RSB 3 | |
424 | #define OPCODE_ADD 4 | |
425 | #define OPCODE_ADC 5 | |
426 | #define OPCODE_SBC 6 | |
427 | #define OPCODE_RSC 7 | |
428 | #define OPCODE_TST 8 | |
429 | #define OPCODE_TEQ 9 | |
430 | #define OPCODE_CMP 10 | |
431 | #define OPCODE_CMN 11 | |
432 | #define OPCODE_ORR 12 | |
433 | #define OPCODE_MOV 13 | |
434 | #define OPCODE_BIC 14 | |
435 | #define OPCODE_MVN 15 | |
90e4755a | 436 | |
a737bd4d NC |
437 | #define T_OPCODE_MUL 0x4340 |
438 | #define T_OPCODE_TST 0x4200 | |
439 | #define T_OPCODE_CMN 0x42c0 | |
440 | #define T_OPCODE_NEG 0x4240 | |
441 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 442 | |
a737bd4d NC |
443 | #define T_OPCODE_ADD_R3 0x1800 |
444 | #define T_OPCODE_SUB_R3 0x1a00 | |
445 | #define T_OPCODE_ADD_HI 0x4400 | |
446 | #define T_OPCODE_ADD_ST 0xb000 | |
447 | #define T_OPCODE_SUB_ST 0xb080 | |
448 | #define T_OPCODE_ADD_SP 0xa800 | |
449 | #define T_OPCODE_ADD_PC 0xa000 | |
450 | #define T_OPCODE_ADD_I8 0x3000 | |
451 | #define T_OPCODE_SUB_I8 0x3800 | |
452 | #define T_OPCODE_ADD_I3 0x1c00 | |
453 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 454 | |
a737bd4d NC |
455 | #define T_OPCODE_ASR_R 0x4100 |
456 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
457 | #define T_OPCODE_LSR_R 0x40c0 |
458 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
459 | #define T_OPCODE_ASR_I 0x1000 |
460 | #define T_OPCODE_LSL_I 0x0000 | |
461 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 462 | |
a737bd4d NC |
463 | #define T_OPCODE_MOV_I8 0x2000 |
464 | #define T_OPCODE_CMP_I8 0x2800 | |
465 | #define T_OPCODE_CMP_LR 0x4280 | |
466 | #define T_OPCODE_MOV_HR 0x4600 | |
467 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 468 | |
a737bd4d NC |
469 | #define T_OPCODE_LDR_PC 0x4800 |
470 | #define T_OPCODE_LDR_SP 0x9800 | |
471 | #define T_OPCODE_STR_SP 0x9000 | |
472 | #define T_OPCODE_LDR_IW 0x6800 | |
473 | #define T_OPCODE_STR_IW 0x6000 | |
474 | #define T_OPCODE_LDR_IH 0x8800 | |
475 | #define T_OPCODE_STR_IH 0x8000 | |
476 | #define T_OPCODE_LDR_IB 0x7800 | |
477 | #define T_OPCODE_STR_IB 0x7000 | |
478 | #define T_OPCODE_LDR_RW 0x5800 | |
479 | #define T_OPCODE_STR_RW 0x5000 | |
480 | #define T_OPCODE_LDR_RH 0x5a00 | |
481 | #define T_OPCODE_STR_RH 0x5200 | |
482 | #define T_OPCODE_LDR_RB 0x5c00 | |
483 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 484 | |
a737bd4d NC |
485 | #define T_OPCODE_PUSH 0xb400 |
486 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 487 | |
2fc8bdac | 488 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 489 | |
a737bd4d | 490 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 491 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 ZW |
492 | #define THUMB_LOAD_BIT 0x0800 |
493 | ||
494 | #define BAD_ARGS _("bad arguments to instruction") | |
495 | #define BAD_PC _("r15 not allowed here") | |
496 | #define BAD_COND _("instruction cannot be conditional") | |
497 | #define BAD_OVERLAP _("registers may not be the same") | |
498 | #define BAD_HIREG _("lo register required") | |
499 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
500 | ||
501 | static struct hash_control *arm_ops_hsh; | |
502 | static struct hash_control *arm_cond_hsh; | |
503 | static struct hash_control *arm_shift_hsh; | |
504 | static struct hash_control *arm_psr_hsh; | |
505 | static struct hash_control *arm_reg_hsh; | |
506 | static struct hash_control *arm_reloc_hsh; | |
b99bd4ef | 507 | |
b99bd4ef NC |
508 | /* Stuff needed to resolve the label ambiguity |
509 | As: | |
510 | ... | |
511 | label: <insn> | |
512 | may differ from: | |
513 | ... | |
514 | label: | |
c19d1205 | 515 | <insn> |
b99bd4ef NC |
516 | */ |
517 | ||
518 | symbolS * last_label_seen; | |
b34976b6 | 519 | static int label_is_thumb_function_name = FALSE; |
a737bd4d | 520 | \f |
3d0c9500 NC |
521 | /* Literal pool structure. Held on a per-section |
522 | and per-sub-section basis. */ | |
a737bd4d | 523 | |
c19d1205 | 524 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 525 | typedef struct literal_pool |
b99bd4ef | 526 | { |
c19d1205 ZW |
527 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
528 | unsigned int next_free_entry; | |
529 | unsigned int id; | |
530 | symbolS * symbol; | |
531 | segT section; | |
532 | subsegT sub_section; | |
61b5f74b | 533 | struct literal_pool * next; |
3d0c9500 | 534 | } literal_pool; |
b99bd4ef | 535 | |
3d0c9500 NC |
536 | /* Pointer to a linked list of literal pools. */ |
537 | literal_pool * list_of_pools = NULL; | |
e27ec89e PB |
538 | |
539 | /* State variables for IT block handling. */ | |
540 | static bfd_boolean current_it_mask = 0; | |
541 | static int current_cc; | |
542 | ||
c19d1205 ZW |
543 | \f |
544 | /* Pure syntax. */ | |
b99bd4ef | 545 | |
c19d1205 ZW |
546 | /* This array holds the chars that always start a comment. If the |
547 | pre-processor is disabled, these aren't very useful. */ | |
548 | const char comment_chars[] = "@"; | |
3d0c9500 | 549 | |
c19d1205 ZW |
550 | /* This array holds the chars that only start a comment at the beginning of |
551 | a line. If the line seems to have the form '# 123 filename' | |
552 | .line and .file directives will appear in the pre-processed output. */ | |
553 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
554 | first line of the input file. This is because the compiler outputs | |
555 | #NO_APP at the beginning of its output. */ | |
556 | /* Also note that comments like this one will always work. */ | |
557 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 558 | |
c19d1205 | 559 | const char line_separator_chars[] = ";"; |
b99bd4ef | 560 | |
c19d1205 ZW |
561 | /* Chars that can be used to separate mant |
562 | from exp in floating point numbers. */ | |
563 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 564 | |
c19d1205 ZW |
565 | /* Chars that mean this number is a floating point constant. */ |
566 | /* As in 0f12.456 */ | |
567 | /* or 0d1.2345e12 */ | |
b99bd4ef | 568 | |
c19d1205 | 569 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 570 | |
c19d1205 ZW |
571 | /* Prefix characters that indicate the start of an immediate |
572 | value. */ | |
573 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 574 | |
c19d1205 ZW |
575 | /* Separator character handling. */ |
576 | ||
577 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
578 | ||
579 | static inline int | |
580 | skip_past_char (char ** str, char c) | |
581 | { | |
582 | if (**str == c) | |
583 | { | |
584 | (*str)++; | |
585 | return SUCCESS; | |
3d0c9500 | 586 | } |
c19d1205 ZW |
587 | else |
588 | return FAIL; | |
589 | } | |
590 | #define skip_past_comma(str) skip_past_char (str, ',') | |
3d0c9500 | 591 | |
c19d1205 ZW |
592 | /* Arithmetic expressions (possibly involving symbols). */ |
593 | ||
594 | /* Return TRUE if anything in the expression is a bignum. */ | |
595 | ||
596 | static int | |
597 | walk_no_bignums (symbolS * sp) | |
598 | { | |
599 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
600 | return 1; | |
601 | ||
602 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 603 | { |
c19d1205 ZW |
604 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
605 | || (symbol_get_value_expression (sp)->X_op_symbol | |
606 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
607 | } |
608 | ||
c19d1205 | 609 | return 0; |
3d0c9500 NC |
610 | } |
611 | ||
c19d1205 ZW |
612 | static int in_my_get_expression = 0; |
613 | ||
614 | /* Third argument to my_get_expression. */ | |
615 | #define GE_NO_PREFIX 0 | |
616 | #define GE_IMM_PREFIX 1 | |
617 | #define GE_OPT_PREFIX 2 | |
a737bd4d | 618 | |
b99bd4ef | 619 | static int |
c19d1205 | 620 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 621 | { |
c19d1205 ZW |
622 | char * save_in; |
623 | segT seg; | |
b99bd4ef | 624 | |
c19d1205 ZW |
625 | /* In unified syntax, all prefixes are optional. */ |
626 | if (unified_syntax) | |
627 | prefix_mode = GE_OPT_PREFIX; | |
b99bd4ef | 628 | |
c19d1205 | 629 | switch (prefix_mode) |
b99bd4ef | 630 | { |
c19d1205 ZW |
631 | case GE_NO_PREFIX: break; |
632 | case GE_IMM_PREFIX: | |
633 | if (!is_immediate_prefix (**str)) | |
634 | { | |
635 | inst.error = _("immediate expression requires a # prefix"); | |
636 | return FAIL; | |
637 | } | |
638 | (*str)++; | |
639 | break; | |
640 | case GE_OPT_PREFIX: | |
641 | if (is_immediate_prefix (**str)) | |
642 | (*str)++; | |
643 | break; | |
644 | default: abort (); | |
645 | } | |
b99bd4ef | 646 | |
c19d1205 | 647 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 648 | |
c19d1205 ZW |
649 | save_in = input_line_pointer; |
650 | input_line_pointer = *str; | |
651 | in_my_get_expression = 1; | |
652 | seg = expression (ep); | |
653 | in_my_get_expression = 0; | |
654 | ||
655 | if (ep->X_op == O_illegal) | |
b99bd4ef | 656 | { |
c19d1205 ZW |
657 | /* We found a bad expression in md_operand(). */ |
658 | *str = input_line_pointer; | |
659 | input_line_pointer = save_in; | |
660 | if (inst.error == NULL) | |
661 | inst.error = _("bad expression"); | |
662 | return 1; | |
663 | } | |
b99bd4ef | 664 | |
c19d1205 ZW |
665 | #ifdef OBJ_AOUT |
666 | if (seg != absolute_section | |
667 | && seg != text_section | |
668 | && seg != data_section | |
669 | && seg != bss_section | |
670 | && seg != undefined_section) | |
671 | { | |
672 | inst.error = _("bad segment"); | |
673 | *str = input_line_pointer; | |
674 | input_line_pointer = save_in; | |
675 | return 1; | |
b99bd4ef | 676 | } |
c19d1205 | 677 | #endif |
b99bd4ef | 678 | |
c19d1205 ZW |
679 | /* Get rid of any bignums now, so that we don't generate an error for which |
680 | we can't establish a line number later on. Big numbers are never valid | |
681 | in instructions, which is where this routine is always called. */ | |
682 | if (ep->X_op == O_big | |
683 | || (ep->X_add_symbol | |
684 | && (walk_no_bignums (ep->X_add_symbol) | |
685 | || (ep->X_op_symbol | |
686 | && walk_no_bignums (ep->X_op_symbol))))) | |
687 | { | |
688 | inst.error = _("invalid constant"); | |
689 | *str = input_line_pointer; | |
690 | input_line_pointer = save_in; | |
691 | return 1; | |
692 | } | |
b99bd4ef | 693 | |
c19d1205 ZW |
694 | *str = input_line_pointer; |
695 | input_line_pointer = save_in; | |
696 | return 0; | |
b99bd4ef NC |
697 | } |
698 | ||
c19d1205 ZW |
699 | /* Turn a string in input_line_pointer into a floating point constant |
700 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
701 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
702 | returned, or NULL on OK. | |
b99bd4ef | 703 | |
c19d1205 ZW |
704 | Note that fp constants aren't represent in the normal way on the ARM. |
705 | In big endian mode, things are as expected. However, in little endian | |
706 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
707 | within the words. For example, (double) 1.1 in big endian mode is | |
708 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
709 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 710 | |
c19d1205 | 711 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 712 | |
c19d1205 ZW |
713 | char * |
714 | md_atof (int type, char * litP, int * sizeP) | |
715 | { | |
716 | int prec; | |
717 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
718 | char *t; | |
719 | int i; | |
b99bd4ef | 720 | |
c19d1205 ZW |
721 | switch (type) |
722 | { | |
723 | case 'f': | |
724 | case 'F': | |
725 | case 's': | |
726 | case 'S': | |
727 | prec = 2; | |
728 | break; | |
b99bd4ef | 729 | |
c19d1205 ZW |
730 | case 'd': |
731 | case 'D': | |
732 | case 'r': | |
733 | case 'R': | |
734 | prec = 4; | |
735 | break; | |
b99bd4ef | 736 | |
c19d1205 ZW |
737 | case 'x': |
738 | case 'X': | |
739 | prec = 6; | |
740 | break; | |
b99bd4ef | 741 | |
c19d1205 ZW |
742 | case 'p': |
743 | case 'P': | |
744 | prec = 6; | |
745 | break; | |
a737bd4d | 746 | |
c19d1205 ZW |
747 | default: |
748 | *sizeP = 0; | |
749 | return _("bad call to MD_ATOF()"); | |
750 | } | |
b99bd4ef | 751 | |
c19d1205 ZW |
752 | t = atof_ieee (input_line_pointer, type, words); |
753 | if (t) | |
754 | input_line_pointer = t; | |
755 | *sizeP = prec * 2; | |
b99bd4ef | 756 | |
c19d1205 ZW |
757 | if (target_big_endian) |
758 | { | |
759 | for (i = 0; i < prec; i++) | |
760 | { | |
761 | md_number_to_chars (litP, (valueT) words[i], 2); | |
762 | litP += 2; | |
763 | } | |
764 | } | |
765 | else | |
766 | { | |
767 | if (cpu_variant & FPU_ARCH_VFP) | |
768 | for (i = prec - 1; i >= 0; i--) | |
769 | { | |
770 | md_number_to_chars (litP, (valueT) words[i], 2); | |
771 | litP += 2; | |
772 | } | |
773 | else | |
774 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
775 | For an 8 byte float the order is 1 0 3 2. */ | |
776 | for (i = 0; i < prec; i += 2) | |
777 | { | |
778 | md_number_to_chars (litP, (valueT) words[i + 1], 2); | |
779 | md_number_to_chars (litP + 2, (valueT) words[i], 2); | |
780 | litP += 4; | |
781 | } | |
782 | } | |
b99bd4ef | 783 | |
c19d1205 ZW |
784 | return 0; |
785 | } | |
b99bd4ef | 786 | |
c19d1205 ZW |
787 | /* We handle all bad expressions here, so that we can report the faulty |
788 | instruction in the error message. */ | |
789 | void | |
790 | md_operand (expressionS * expr) | |
791 | { | |
792 | if (in_my_get_expression) | |
793 | expr->X_op = O_illegal; | |
b99bd4ef NC |
794 | } |
795 | ||
c19d1205 | 796 | /* Immediate values. */ |
b99bd4ef | 797 | |
c19d1205 ZW |
798 | /* Generic immediate-value read function for use in directives. |
799 | Accepts anything that 'expression' can fold to a constant. | |
800 | *val receives the number. */ | |
801 | #ifdef OBJ_ELF | |
802 | static int | |
803 | immediate_for_directive (int *val) | |
b99bd4ef | 804 | { |
c19d1205 ZW |
805 | expressionS exp; |
806 | exp.X_op = O_illegal; | |
b99bd4ef | 807 | |
c19d1205 ZW |
808 | if (is_immediate_prefix (*input_line_pointer)) |
809 | { | |
810 | input_line_pointer++; | |
811 | expression (&exp); | |
812 | } | |
b99bd4ef | 813 | |
c19d1205 ZW |
814 | if (exp.X_op != O_constant) |
815 | { | |
816 | as_bad (_("expected #constant")); | |
817 | ignore_rest_of_line (); | |
818 | return FAIL; | |
819 | } | |
820 | *val = exp.X_add_number; | |
821 | return SUCCESS; | |
b99bd4ef | 822 | } |
c19d1205 | 823 | #endif |
b99bd4ef | 824 | |
c19d1205 | 825 | /* Register parsing. */ |
b99bd4ef | 826 | |
c19d1205 ZW |
827 | /* Generic register parser. CCP points to what should be the |
828 | beginning of a register name. If it is indeed a valid register | |
829 | name, advance CCP over it and return the reg_entry structure; | |
830 | otherwise return NULL. Does not issue diagnostics. */ | |
831 | ||
832 | static struct reg_entry * | |
833 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 834 | { |
c19d1205 ZW |
835 | char *start = *ccp; |
836 | char *p; | |
837 | struct reg_entry *reg; | |
b99bd4ef | 838 | |
c19d1205 ZW |
839 | #ifdef REGISTER_PREFIX |
840 | if (*start != REGISTER_PREFIX) | |
841 | return FAIL; | |
842 | start++; | |
843 | #endif | |
844 | #ifdef OPTIONAL_REGISTER_PREFIX | |
845 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
846 | start++; | |
847 | #endif | |
b99bd4ef | 848 | |
c19d1205 ZW |
849 | p = start; |
850 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
851 | return NULL; | |
b99bd4ef | 852 | |
c19d1205 ZW |
853 | do |
854 | p++; | |
855 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
856 | ||
857 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
858 | ||
859 | if (!reg) | |
860 | return NULL; | |
861 | ||
862 | *ccp = p; | |
863 | return reg; | |
b99bd4ef NC |
864 | } |
865 | ||
c19d1205 ZW |
866 | /* As above, but the register must be of type TYPE, and the return |
867 | value is the register number or NULL. */ | |
868 | ||
b99bd4ef | 869 | static int |
c19d1205 | 870 | arm_reg_parse (char **ccp, enum arm_reg_type type) |
b99bd4ef | 871 | { |
c19d1205 ZW |
872 | char *start = *ccp; |
873 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
b99bd4ef | 874 | |
c19d1205 ZW |
875 | if (reg && reg->type == type) |
876 | return reg->number; | |
6057a28f | 877 | |
c19d1205 ZW |
878 | /* Alternative syntaxes are accepted for a few register classes. */ |
879 | switch (type) | |
880 | { | |
881 | case REG_TYPE_MVF: | |
882 | case REG_TYPE_MVD: | |
883 | case REG_TYPE_MVFX: | |
884 | case REG_TYPE_MVDX: | |
885 | /* Generic coprocessor register names are allowed for these. */ | |
886 | if (reg->type == REG_TYPE_CN) | |
887 | return reg->number; | |
888 | break; | |
69b97547 | 889 | |
c19d1205 ZW |
890 | case REG_TYPE_CP: |
891 | /* For backward compatibility, a bare number is valid here. */ | |
892 | { | |
893 | unsigned long processor = strtoul (start, ccp, 10); | |
894 | if (*ccp != start && processor <= 15) | |
895 | return processor; | |
896 | } | |
6057a28f | 897 | |
c19d1205 ZW |
898 | case REG_TYPE_MMXWC: |
899 | /* WC includes WCG. ??? I'm not sure this is true for all | |
900 | instructions that take WC registers. */ | |
901 | if (reg->type == REG_TYPE_MMXWCG) | |
902 | return reg->number; | |
6057a28f | 903 | break; |
c19d1205 | 904 | |
6057a28f | 905 | default: |
c19d1205 | 906 | break; |
6057a28f NC |
907 | } |
908 | ||
c19d1205 ZW |
909 | *ccp = start; |
910 | return FAIL; | |
911 | } | |
69b97547 | 912 | |
c19d1205 ZW |
913 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
914 | static long | |
915 | parse_reg_list (char ** strp) | |
916 | { | |
917 | char * str = * strp; | |
918 | long range = 0; | |
919 | int another_range; | |
a737bd4d | 920 | |
c19d1205 ZW |
921 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
922 | do | |
6057a28f | 923 | { |
c19d1205 | 924 | another_range = 0; |
a737bd4d | 925 | |
c19d1205 ZW |
926 | if (*str == '{') |
927 | { | |
928 | int in_range = 0; | |
929 | int cur_reg = -1; | |
a737bd4d | 930 | |
c19d1205 ZW |
931 | str++; |
932 | do | |
933 | { | |
934 | int reg; | |
6057a28f | 935 | |
c19d1205 ZW |
936 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
937 | { | |
938 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
939 | return FAIL; | |
940 | } | |
a737bd4d | 941 | |
c19d1205 ZW |
942 | if (in_range) |
943 | { | |
944 | int i; | |
a737bd4d | 945 | |
c19d1205 ZW |
946 | if (reg <= cur_reg) |
947 | { | |
948 | inst.error = _("bad range in register list"); | |
949 | return FAIL; | |
950 | } | |
40a18ebd | 951 | |
c19d1205 ZW |
952 | for (i = cur_reg + 1; i < reg; i++) |
953 | { | |
954 | if (range & (1 << i)) | |
955 | as_tsktsk | |
956 | (_("Warning: duplicated register (r%d) in register list"), | |
957 | i); | |
958 | else | |
959 | range |= 1 << i; | |
960 | } | |
961 | in_range = 0; | |
962 | } | |
a737bd4d | 963 | |
c19d1205 ZW |
964 | if (range & (1 << reg)) |
965 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
966 | reg); | |
967 | else if (reg <= cur_reg) | |
968 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 969 | |
c19d1205 ZW |
970 | range |= 1 << reg; |
971 | cur_reg = reg; | |
972 | } | |
973 | while (skip_past_comma (&str) != FAIL | |
974 | || (in_range = 1, *str++ == '-')); | |
975 | str--; | |
a737bd4d | 976 | |
c19d1205 ZW |
977 | if (*str++ != '}') |
978 | { | |
979 | inst.error = _("missing `}'"); | |
980 | return FAIL; | |
981 | } | |
982 | } | |
983 | else | |
984 | { | |
985 | expressionS expr; | |
40a18ebd | 986 | |
c19d1205 ZW |
987 | if (my_get_expression (&expr, &str, GE_NO_PREFIX)) |
988 | return FAIL; | |
40a18ebd | 989 | |
c19d1205 ZW |
990 | if (expr.X_op == O_constant) |
991 | { | |
992 | if (expr.X_add_number | |
993 | != (expr.X_add_number & 0x0000ffff)) | |
994 | { | |
995 | inst.error = _("invalid register mask"); | |
996 | return FAIL; | |
997 | } | |
a737bd4d | 998 | |
c19d1205 ZW |
999 | if ((range & expr.X_add_number) != 0) |
1000 | { | |
1001 | int regno = range & expr.X_add_number; | |
a737bd4d | 1002 | |
c19d1205 ZW |
1003 | regno &= -regno; |
1004 | regno = (1 << regno) - 1; | |
1005 | as_tsktsk | |
1006 | (_("Warning: duplicated register (r%d) in register list"), | |
1007 | regno); | |
1008 | } | |
a737bd4d | 1009 | |
c19d1205 ZW |
1010 | range |= expr.X_add_number; |
1011 | } | |
1012 | else | |
1013 | { | |
1014 | if (inst.reloc.type != 0) | |
1015 | { | |
1016 | inst.error = _("expression too complex"); | |
1017 | return FAIL; | |
1018 | } | |
a737bd4d | 1019 | |
c19d1205 ZW |
1020 | memcpy (&inst.reloc.exp, &expr, sizeof (expressionS)); |
1021 | inst.reloc.type = BFD_RELOC_ARM_MULTI; | |
1022 | inst.reloc.pc_rel = 0; | |
1023 | } | |
1024 | } | |
a737bd4d | 1025 | |
c19d1205 ZW |
1026 | if (*str == '|' || *str == '+') |
1027 | { | |
1028 | str++; | |
1029 | another_range = 1; | |
1030 | } | |
a737bd4d | 1031 | } |
c19d1205 | 1032 | while (another_range); |
a737bd4d | 1033 | |
c19d1205 ZW |
1034 | *strp = str; |
1035 | return range; | |
a737bd4d NC |
1036 | } |
1037 | ||
c19d1205 ZW |
1038 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1039 | Otherwise return the number of registers, and set PBASE to the first | |
1040 | register. Double precision registers are matched if DP is nonzero. */ | |
6057a28f | 1041 | |
c19d1205 | 1042 | static int |
ca3f61f7 | 1043 | parse_vfp_reg_list (char **str, unsigned int *pbase, int dp) |
6057a28f | 1044 | { |
c19d1205 ZW |
1045 | int base_reg; |
1046 | int new_base; | |
1047 | int regtype; | |
1048 | int max_regs; | |
1049 | int count = 0; | |
1050 | int warned = 0; | |
1051 | unsigned long mask = 0; | |
a737bd4d | 1052 | int i; |
6057a28f | 1053 | |
c19d1205 ZW |
1054 | if (**str != '{') |
1055 | return FAIL; | |
6057a28f | 1056 | |
c19d1205 | 1057 | (*str)++; |
6057a28f | 1058 | |
c19d1205 | 1059 | if (dp) |
a737bd4d | 1060 | { |
c19d1205 ZW |
1061 | regtype = REG_TYPE_VFD; |
1062 | max_regs = 16; | |
1063 | } | |
1064 | else | |
1065 | { | |
1066 | regtype = REG_TYPE_VFS; | |
1067 | max_regs = 32; | |
1068 | } | |
6057a28f | 1069 | |
c19d1205 | 1070 | base_reg = max_regs; |
a737bd4d | 1071 | |
c19d1205 ZW |
1072 | do |
1073 | { | |
1074 | new_base = arm_reg_parse (str, regtype); | |
1075 | if (new_base == FAIL) | |
a737bd4d | 1076 | { |
c19d1205 ZW |
1077 | inst.error = gettext (reg_expected_msgs[regtype]); |
1078 | return FAIL; | |
1079 | } | |
a737bd4d | 1080 | |
c19d1205 ZW |
1081 | if (new_base < base_reg) |
1082 | base_reg = new_base; | |
a737bd4d | 1083 | |
c19d1205 ZW |
1084 | if (mask & (1 << new_base)) |
1085 | { | |
1086 | inst.error = _("invalid register list"); | |
1087 | return FAIL; | |
a737bd4d | 1088 | } |
a737bd4d | 1089 | |
c19d1205 ZW |
1090 | if ((mask >> new_base) != 0 && ! warned) |
1091 | { | |
1092 | as_tsktsk (_("register list not in ascending order")); | |
1093 | warned = 1; | |
1094 | } | |
0bbf2aa4 | 1095 | |
c19d1205 ZW |
1096 | mask |= 1 << new_base; |
1097 | count++; | |
0bbf2aa4 | 1098 | |
c19d1205 ZW |
1099 | if (**str == '-') /* We have the start of a range expression */ |
1100 | { | |
1101 | int high_range; | |
0bbf2aa4 | 1102 | |
c19d1205 | 1103 | (*str)++; |
0bbf2aa4 | 1104 | |
c19d1205 ZW |
1105 | if ((high_range = arm_reg_parse (str, regtype)) == FAIL) |
1106 | { | |
1107 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1108 | return FAIL; | |
1109 | } | |
0bbf2aa4 | 1110 | |
c19d1205 ZW |
1111 | if (high_range <= new_base) |
1112 | { | |
1113 | inst.error = _("register range not in ascending order"); | |
1114 | return FAIL; | |
1115 | } | |
0bbf2aa4 | 1116 | |
c19d1205 | 1117 | for (new_base++; new_base <= high_range; new_base++) |
0bbf2aa4 | 1118 | { |
c19d1205 | 1119 | if (mask & (1 << new_base)) |
0bbf2aa4 | 1120 | { |
c19d1205 ZW |
1121 | inst.error = _("invalid register list"); |
1122 | return FAIL; | |
0bbf2aa4 | 1123 | } |
c19d1205 ZW |
1124 | |
1125 | mask |= 1 << new_base; | |
1126 | count++; | |
0bbf2aa4 | 1127 | } |
0bbf2aa4 | 1128 | } |
0bbf2aa4 | 1129 | } |
c19d1205 | 1130 | while (skip_past_comma (str) != FAIL); |
0bbf2aa4 | 1131 | |
c19d1205 | 1132 | (*str)++; |
0bbf2aa4 | 1133 | |
c19d1205 ZW |
1134 | /* Sanity check -- should have raised a parse error above. */ |
1135 | if (count == 0 || count > max_regs) | |
1136 | abort (); | |
1137 | ||
1138 | *pbase = base_reg; | |
1139 | ||
1140 | /* Final test -- the registers must be consecutive. */ | |
1141 | mask >>= base_reg; | |
1142 | for (i = 0; i < count; i++) | |
1143 | { | |
1144 | if ((mask & (1u << i)) == 0) | |
1145 | { | |
1146 | inst.error = _("non-contiguous register range"); | |
1147 | return FAIL; | |
1148 | } | |
1149 | } | |
1150 | ||
1151 | return count; | |
b99bd4ef NC |
1152 | } |
1153 | ||
c19d1205 ZW |
1154 | /* Parse an explicit relocation suffix on an expression. This is |
1155 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
1156 | arm_reloc_hsh contains no entries, so this function can only | |
1157 | succeed if there is no () after the word. Returns -1 on error, | |
1158 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
1159 | static int | |
1160 | parse_reloc (char **str) | |
b99bd4ef | 1161 | { |
c19d1205 ZW |
1162 | struct reloc_entry *r; |
1163 | char *p, *q; | |
b99bd4ef | 1164 | |
c19d1205 ZW |
1165 | if (**str != '(') |
1166 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 1167 | |
c19d1205 ZW |
1168 | p = *str + 1; |
1169 | q = p; | |
1170 | ||
1171 | while (*q && *q != ')' && *q != ',') | |
1172 | q++; | |
1173 | if (*q != ')') | |
1174 | return -1; | |
1175 | ||
1176 | if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
1177 | return -1; | |
1178 | ||
1179 | *str = q + 1; | |
1180 | return r->reloc; | |
b99bd4ef NC |
1181 | } |
1182 | ||
c19d1205 ZW |
1183 | /* Directives: register aliases. */ |
1184 | ||
b99bd4ef | 1185 | static void |
c19d1205 | 1186 | insert_reg_alias (char *str, int number, int type) |
b99bd4ef | 1187 | { |
c19d1205 ZW |
1188 | struct reg_entry *new; |
1189 | const char *name; | |
b99bd4ef | 1190 | |
c19d1205 ZW |
1191 | if ((new = hash_find (arm_reg_hsh, str)) != 0) |
1192 | { | |
1193 | if (new->builtin) | |
1194 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); | |
b99bd4ef | 1195 | |
c19d1205 ZW |
1196 | /* Only warn about a redefinition if it's not defined as the |
1197 | same register. */ | |
1198 | else if (new->number != number || new->type != type) | |
1199 | as_warn (_("ignoring redefinition of register alias '%s'"), str); | |
69b97547 | 1200 | |
c19d1205 ZW |
1201 | return; |
1202 | } | |
b99bd4ef | 1203 | |
c19d1205 ZW |
1204 | name = xstrdup (str); |
1205 | new = xmalloc (sizeof (struct reg_entry)); | |
b99bd4ef | 1206 | |
c19d1205 ZW |
1207 | new->name = name; |
1208 | new->number = number; | |
1209 | new->type = type; | |
1210 | new->builtin = FALSE; | |
b99bd4ef | 1211 | |
c19d1205 ZW |
1212 | if (hash_insert (arm_reg_hsh, name, (PTR) new)) |
1213 | abort (); | |
1214 | } | |
b99bd4ef | 1215 | |
c19d1205 | 1216 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 1217 | |
c19d1205 | 1218 | new_register_name .req existing_register_name |
b99bd4ef | 1219 | |
c19d1205 ZW |
1220 | If we find one, or if it looks sufficiently like one that we want to |
1221 | handle any error here, return non-zero. Otherwise return zero. */ | |
b99bd4ef | 1222 | |
c19d1205 ZW |
1223 | static int |
1224 | create_register_alias (char * newname, char *p) | |
1225 | { | |
1226 | struct reg_entry *old; | |
1227 | char *oldname, *nbuf; | |
1228 | size_t nlen; | |
b99bd4ef | 1229 | |
c19d1205 ZW |
1230 | /* The input scrubber ensures that whitespace after the mnemonic is |
1231 | collapsed to single spaces. */ | |
1232 | oldname = p; | |
1233 | if (strncmp (oldname, " .req ", 6) != 0) | |
1234 | return 0; | |
b99bd4ef | 1235 | |
c19d1205 ZW |
1236 | oldname += 6; |
1237 | if (*oldname == '\0') | |
1238 | return 0; | |
b99bd4ef | 1239 | |
c19d1205 ZW |
1240 | old = hash_find (arm_reg_hsh, oldname); |
1241 | if (!old) | |
b99bd4ef | 1242 | { |
c19d1205 ZW |
1243 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
1244 | return 1; | |
b99bd4ef NC |
1245 | } |
1246 | ||
c19d1205 ZW |
1247 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
1248 | the desired alias name, and p points to its end. If not, then | |
1249 | the desired alias name is in the global original_case_string. */ | |
1250 | #ifdef TC_CASE_SENSITIVE | |
1251 | nlen = p - newname; | |
1252 | #else | |
1253 | newname = original_case_string; | |
1254 | nlen = strlen (newname); | |
1255 | #endif | |
b99bd4ef | 1256 | |
c19d1205 ZW |
1257 | nbuf = alloca (nlen + 1); |
1258 | memcpy (nbuf, newname, nlen); | |
1259 | nbuf[nlen] = '\0'; | |
b99bd4ef | 1260 | |
c19d1205 ZW |
1261 | /* Create aliases under the new name as stated; an all-lowercase |
1262 | version of the new name; and an all-uppercase version of the new | |
1263 | name. */ | |
1264 | insert_reg_alias (nbuf, old->number, old->type); | |
b99bd4ef | 1265 | |
c19d1205 ZW |
1266 | for (p = nbuf; *p; p++) |
1267 | *p = TOUPPER (*p); | |
1268 | ||
1269 | if (strncmp (nbuf, newname, nlen)) | |
1270 | insert_reg_alias (nbuf, old->number, old->type); | |
1271 | ||
1272 | for (p = nbuf; *p; p++) | |
1273 | *p = TOLOWER (*p); | |
1274 | ||
1275 | if (strncmp (nbuf, newname, nlen)) | |
1276 | insert_reg_alias (nbuf, old->number, old->type); | |
1277 | ||
1278 | return 1; | |
b99bd4ef NC |
1279 | } |
1280 | ||
c19d1205 ZW |
1281 | /* Should never be called, as .req goes between the alias and the |
1282 | register name, not at the beginning of the line. */ | |
b99bd4ef | 1283 | static void |
c19d1205 | 1284 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 1285 | { |
c19d1205 ZW |
1286 | as_bad (_("invalid syntax for .req directive")); |
1287 | } | |
b99bd4ef | 1288 | |
c19d1205 ZW |
1289 | /* The .unreq directive deletes an alias which was previously defined |
1290 | by .req. For example: | |
b99bd4ef | 1291 | |
c19d1205 ZW |
1292 | my_alias .req r11 |
1293 | .unreq my_alias */ | |
b99bd4ef NC |
1294 | |
1295 | static void | |
c19d1205 | 1296 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 1297 | { |
c19d1205 ZW |
1298 | char * name; |
1299 | char saved_char; | |
b99bd4ef | 1300 | |
c19d1205 ZW |
1301 | name = input_line_pointer; |
1302 | ||
1303 | while (*input_line_pointer != 0 | |
1304 | && *input_line_pointer != ' ' | |
1305 | && *input_line_pointer != '\n') | |
1306 | ++input_line_pointer; | |
1307 | ||
1308 | saved_char = *input_line_pointer; | |
1309 | *input_line_pointer = 0; | |
1310 | ||
1311 | if (!*name) | |
1312 | as_bad (_("invalid syntax for .unreq directive")); | |
1313 | else | |
1314 | { | |
1315 | struct reg_entry *reg = hash_find (arm_reg_hsh, name); | |
1316 | ||
1317 | if (!reg) | |
1318 | as_bad (_("unknown register alias '%s'"), name); | |
1319 | else if (reg->builtin) | |
1320 | as_warn (_("ignoring attempt to undefine built-in register '%s'"), | |
1321 | name); | |
1322 | else | |
1323 | { | |
1324 | hash_delete (arm_reg_hsh, name); | |
1325 | free ((char *) reg->name); | |
1326 | free (reg); | |
1327 | } | |
1328 | } | |
b99bd4ef | 1329 | |
c19d1205 | 1330 | *input_line_pointer = saved_char; |
b99bd4ef NC |
1331 | demand_empty_rest_of_line (); |
1332 | } | |
1333 | ||
c19d1205 ZW |
1334 | /* Directives: Instruction set selection. */ |
1335 | ||
1336 | #ifdef OBJ_ELF | |
1337 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
1338 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
1339 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
1340 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
1341 | ||
1342 | static enum mstate mapstate = MAP_UNDEFINED; | |
b99bd4ef NC |
1343 | |
1344 | static void | |
c19d1205 | 1345 | mapping_state (enum mstate state) |
b99bd4ef | 1346 | { |
a737bd4d | 1347 | symbolS * symbolP; |
c19d1205 ZW |
1348 | const char * symname; |
1349 | int type; | |
b99bd4ef | 1350 | |
c19d1205 ZW |
1351 | if (mapstate == state) |
1352 | /* The mapping symbol has already been emitted. | |
1353 | There is nothing else to do. */ | |
1354 | return; | |
b99bd4ef | 1355 | |
c19d1205 | 1356 | mapstate = state; |
b99bd4ef | 1357 | |
c19d1205 | 1358 | switch (state) |
b99bd4ef | 1359 | { |
c19d1205 ZW |
1360 | case MAP_DATA: |
1361 | symname = "$d"; | |
1362 | type = BSF_NO_FLAGS; | |
1363 | break; | |
1364 | case MAP_ARM: | |
1365 | symname = "$a"; | |
1366 | type = BSF_NO_FLAGS; | |
1367 | break; | |
1368 | case MAP_THUMB: | |
1369 | symname = "$t"; | |
1370 | type = BSF_NO_FLAGS; | |
1371 | break; | |
1372 | case MAP_UNDEFINED: | |
1373 | return; | |
1374 | default: | |
1375 | abort (); | |
1376 | } | |
1377 | ||
1378 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; | |
1379 | ||
1380 | symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now); | |
1381 | symbol_table_insert (symbolP); | |
1382 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; | |
1383 | ||
1384 | switch (state) | |
1385 | { | |
1386 | case MAP_ARM: | |
1387 | THUMB_SET_FUNC (symbolP, 0); | |
1388 | ARM_SET_THUMB (symbolP, 0); | |
1389 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
1390 | break; | |
1391 | ||
1392 | case MAP_THUMB: | |
1393 | THUMB_SET_FUNC (symbolP, 1); | |
1394 | ARM_SET_THUMB (symbolP, 1); | |
1395 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
1396 | break; | |
1397 | ||
1398 | case MAP_DATA: | |
1399 | default: | |
1400 | return; | |
1401 | } | |
1402 | } | |
1403 | #else | |
1404 | #define mapping_state(x) /* nothing */ | |
1405 | #endif | |
1406 | ||
1407 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
1408 | ||
1409 | static symbolS * | |
1410 | find_real_start (symbolS * symbolP) | |
1411 | { | |
1412 | char * real_start; | |
1413 | const char * name = S_GET_NAME (symbolP); | |
1414 | symbolS * new_target; | |
1415 | ||
1416 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
1417 | #define STUB_NAME ".real_start_of" | |
1418 | ||
1419 | if (name == NULL) | |
1420 | abort (); | |
1421 | ||
37f6032b ZW |
1422 | /* The compiler may generate BL instructions to local labels because |
1423 | it needs to perform a branch to a far away location. These labels | |
1424 | do not have a corresponding ".real_start_of" label. We check | |
1425 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
1426 | the ".real_start_of" convention for nonlocal branches. */ | |
1427 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
1428 | return symbolP; |
1429 | ||
37f6032b | 1430 | real_start = ACONCAT ((STUB_NAME, name, NULL)); |
c19d1205 ZW |
1431 | new_target = symbol_find (real_start); |
1432 | ||
1433 | if (new_target == NULL) | |
1434 | { | |
1435 | as_warn ("Failed to find real start of function: %s\n", name); | |
1436 | new_target = symbolP; | |
1437 | } | |
1438 | ||
c19d1205 ZW |
1439 | return new_target; |
1440 | } | |
1441 | ||
1442 | static void | |
1443 | opcode_select (int width) | |
1444 | { | |
1445 | switch (width) | |
1446 | { | |
1447 | case 16: | |
1448 | if (! thumb_mode) | |
1449 | { | |
1450 | if (! (cpu_variant & ARM_EXT_V4T)) | |
1451 | as_bad (_("selected processor does not support THUMB opcodes")); | |
1452 | ||
1453 | thumb_mode = 1; | |
1454 | /* No need to force the alignment, since we will have been | |
1455 | coming from ARM mode, which is word-aligned. */ | |
1456 | record_alignment (now_seg, 1); | |
1457 | } | |
1458 | mapping_state (MAP_THUMB); | |
1459 | break; | |
1460 | ||
1461 | case 32: | |
1462 | if (thumb_mode) | |
1463 | { | |
1464 | if ((cpu_variant & ARM_ALL) == ARM_EXT_V4T) | |
1465 | as_bad (_("selected processor does not support ARM opcodes")); | |
1466 | ||
1467 | thumb_mode = 0; | |
1468 | ||
1469 | if (!need_pass_2) | |
1470 | frag_align (2, 0, 0); | |
1471 | ||
1472 | record_alignment (now_seg, 1); | |
1473 | } | |
1474 | mapping_state (MAP_ARM); | |
1475 | break; | |
1476 | ||
1477 | default: | |
1478 | as_bad (_("invalid instruction size selected (%d)"), width); | |
1479 | } | |
1480 | } | |
1481 | ||
1482 | static void | |
1483 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
1484 | { | |
1485 | opcode_select (32); | |
1486 | demand_empty_rest_of_line (); | |
1487 | } | |
1488 | ||
1489 | static void | |
1490 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
1491 | { | |
1492 | opcode_select (16); | |
1493 | demand_empty_rest_of_line (); | |
1494 | } | |
1495 | ||
1496 | static void | |
1497 | s_code (int unused ATTRIBUTE_UNUSED) | |
1498 | { | |
1499 | int temp; | |
1500 | ||
1501 | temp = get_absolute_expression (); | |
1502 | switch (temp) | |
1503 | { | |
1504 | case 16: | |
1505 | case 32: | |
1506 | opcode_select (temp); | |
1507 | break; | |
1508 | ||
1509 | default: | |
1510 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
1511 | } | |
1512 | } | |
1513 | ||
1514 | static void | |
1515 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
1516 | { | |
1517 | /* If we are not already in thumb mode go into it, EVEN if | |
1518 | the target processor does not support thumb instructions. | |
1519 | This is used by gcc/config/arm/lib1funcs.asm for example | |
1520 | to compile interworking support functions even if the | |
1521 | target processor should not support interworking. */ | |
1522 | if (! thumb_mode) | |
1523 | { | |
1524 | thumb_mode = 2; | |
1525 | record_alignment (now_seg, 1); | |
1526 | } | |
1527 | ||
1528 | demand_empty_rest_of_line (); | |
1529 | } | |
1530 | ||
1531 | static void | |
1532 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
1533 | { | |
1534 | s_thumb (0); | |
1535 | ||
1536 | /* The following label is the name/address of the start of a Thumb function. | |
1537 | We need to know this for the interworking support. */ | |
1538 | label_is_thumb_function_name = TRUE; | |
1539 | } | |
1540 | ||
1541 | /* Perform a .set directive, but also mark the alias as | |
1542 | being a thumb function. */ | |
1543 | ||
1544 | static void | |
1545 | s_thumb_set (int equiv) | |
1546 | { | |
1547 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
1548 | We cannot just call that code as we need to get at the symbol that | |
1549 | is created. */ | |
1550 | char * name; | |
1551 | char delim; | |
1552 | char * end_name; | |
1553 | symbolS * symbolP; | |
1554 | ||
1555 | /* Especial apologies for the random logic: | |
1556 | This just grew, and could be parsed much more simply! | |
1557 | Dean - in haste. */ | |
1558 | name = input_line_pointer; | |
1559 | delim = get_symbol_end (); | |
1560 | end_name = input_line_pointer; | |
1561 | *end_name = delim; | |
1562 | ||
1563 | if (*input_line_pointer != ',') | |
1564 | { | |
1565 | *end_name = 0; | |
1566 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
1567 | *end_name = delim; |
1568 | ignore_rest_of_line (); | |
1569 | return; | |
1570 | } | |
1571 | ||
1572 | input_line_pointer++; | |
1573 | *end_name = 0; | |
1574 | ||
1575 | if (name[0] == '.' && name[1] == '\0') | |
1576 | { | |
1577 | /* XXX - this should not happen to .thumb_set. */ | |
1578 | abort (); | |
1579 | } | |
1580 | ||
1581 | if ((symbolP = symbol_find (name)) == NULL | |
1582 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
1583 | { | |
1584 | #ifndef NO_LISTING | |
1585 | /* When doing symbol listings, play games with dummy fragments living | |
1586 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 1587 | for this symbol. */ |
b99bd4ef NC |
1588 | if (listing & LISTING_SYMBOLS) |
1589 | { | |
1590 | extern struct list_info_struct * listing_tail; | |
a737bd4d | 1591 | fragS * dummy_frag = xmalloc (sizeof (fragS)); |
b99bd4ef NC |
1592 | |
1593 | memset (dummy_frag, 0, sizeof (fragS)); | |
1594 | dummy_frag->fr_type = rs_fill; | |
1595 | dummy_frag->line = listing_tail; | |
1596 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
1597 | dummy_frag->fr_symbol = symbolP; | |
1598 | } | |
1599 | else | |
1600 | #endif | |
1601 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
1602 | ||
1603 | #ifdef OBJ_COFF | |
1604 | /* "set" symbols are local unless otherwise specified. */ | |
1605 | SF_SET_LOCAL (symbolP); | |
1606 | #endif /* OBJ_COFF */ | |
1607 | } /* Make a new symbol. */ | |
1608 | ||
1609 | symbol_table_insert (symbolP); | |
1610 | ||
1611 | * end_name = delim; | |
1612 | ||
1613 | if (equiv | |
1614 | && S_IS_DEFINED (symbolP) | |
1615 | && S_GET_SEGMENT (symbolP) != reg_section) | |
1616 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
1617 | ||
1618 | pseudo_set (symbolP); | |
1619 | ||
1620 | demand_empty_rest_of_line (); | |
1621 | ||
c19d1205 | 1622 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
1623 | |
1624 | THUMB_SET_FUNC (symbolP, 1); | |
1625 | ARM_SET_THUMB (symbolP, 1); | |
1626 | #if defined OBJ_ELF || defined OBJ_COFF | |
1627 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
1628 | #endif | |
1629 | } | |
1630 | ||
c19d1205 | 1631 | /* Directives: Mode selection. */ |
b99bd4ef | 1632 | |
c19d1205 ZW |
1633 | /* .syntax [unified|divided] - choose the new unified syntax |
1634 | (same for Arm and Thumb encoding, modulo slight differences in what | |
1635 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 1636 | static void |
c19d1205 | 1637 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 1638 | { |
c19d1205 ZW |
1639 | char *name, delim; |
1640 | ||
1641 | name = input_line_pointer; | |
1642 | delim = get_symbol_end (); | |
1643 | ||
1644 | if (!strcasecmp (name, "unified")) | |
1645 | unified_syntax = TRUE; | |
1646 | else if (!strcasecmp (name, "divided")) | |
1647 | unified_syntax = FALSE; | |
1648 | else | |
1649 | { | |
1650 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
1651 | return; | |
1652 | } | |
1653 | *input_line_pointer = delim; | |
b99bd4ef NC |
1654 | demand_empty_rest_of_line (); |
1655 | } | |
1656 | ||
c19d1205 ZW |
1657 | /* Directives: sectioning and alignment. */ |
1658 | ||
1659 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
1660 | ||
b99bd4ef | 1661 | static void |
c19d1205 | 1662 | s_align (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 1663 | { |
a737bd4d | 1664 | int temp; |
c19d1205 ZW |
1665 | long temp_fill; |
1666 | long max_alignment = 15; | |
b99bd4ef NC |
1667 | |
1668 | temp = get_absolute_expression (); | |
c19d1205 ZW |
1669 | if (temp > max_alignment) |
1670 | as_bad (_("alignment too large: %d assumed"), temp = max_alignment); | |
1671 | else if (temp < 0) | |
b99bd4ef | 1672 | { |
c19d1205 ZW |
1673 | as_bad (_("alignment negative. 0 assumed.")); |
1674 | temp = 0; | |
1675 | } | |
b99bd4ef | 1676 | |
c19d1205 ZW |
1677 | if (*input_line_pointer == ',') |
1678 | { | |
1679 | input_line_pointer++; | |
1680 | temp_fill = get_absolute_expression (); | |
b99bd4ef | 1681 | } |
c19d1205 ZW |
1682 | else |
1683 | temp_fill = 0; | |
b99bd4ef | 1684 | |
c19d1205 ZW |
1685 | if (!temp) |
1686 | temp = 2; | |
b99bd4ef | 1687 | |
c19d1205 ZW |
1688 | /* Only make a frag if we HAVE to. */ |
1689 | if (temp && !need_pass_2) | |
1690 | frag_align (temp, (int) temp_fill, 0); | |
1691 | demand_empty_rest_of_line (); | |
1692 | ||
1693 | record_alignment (now_seg, temp); | |
b99bd4ef NC |
1694 | } |
1695 | ||
c19d1205 ZW |
1696 | static void |
1697 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 1698 | { |
c19d1205 ZW |
1699 | /* We don't support putting frags in the BSS segment, we fake it by |
1700 | marking in_bss, then looking at s_skip for clues. */ | |
1701 | subseg_set (bss_section, 0); | |
1702 | demand_empty_rest_of_line (); | |
1703 | mapping_state (MAP_DATA); | |
1704 | } | |
b99bd4ef | 1705 | |
c19d1205 ZW |
1706 | static void |
1707 | s_even (int ignore ATTRIBUTE_UNUSED) | |
1708 | { | |
1709 | /* Never make frag if expect extra pass. */ | |
1710 | if (!need_pass_2) | |
1711 | frag_align (1, 0, 0); | |
b99bd4ef | 1712 | |
c19d1205 | 1713 | record_alignment (now_seg, 1); |
b99bd4ef | 1714 | |
c19d1205 | 1715 | demand_empty_rest_of_line (); |
b99bd4ef NC |
1716 | } |
1717 | ||
c19d1205 | 1718 | /* Directives: Literal pools. */ |
a737bd4d | 1719 | |
c19d1205 ZW |
1720 | static literal_pool * |
1721 | find_literal_pool (void) | |
a737bd4d | 1722 | { |
c19d1205 | 1723 | literal_pool * pool; |
a737bd4d | 1724 | |
c19d1205 | 1725 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 1726 | { |
c19d1205 ZW |
1727 | if (pool->section == now_seg |
1728 | && pool->sub_section == now_subseg) | |
1729 | break; | |
a737bd4d NC |
1730 | } |
1731 | ||
c19d1205 | 1732 | return pool; |
a737bd4d NC |
1733 | } |
1734 | ||
c19d1205 ZW |
1735 | static literal_pool * |
1736 | find_or_make_literal_pool (void) | |
a737bd4d | 1737 | { |
c19d1205 ZW |
1738 | /* Next literal pool ID number. */ |
1739 | static unsigned int latest_pool_num = 1; | |
1740 | literal_pool * pool; | |
a737bd4d | 1741 | |
c19d1205 | 1742 | pool = find_literal_pool (); |
a737bd4d | 1743 | |
c19d1205 | 1744 | if (pool == NULL) |
a737bd4d | 1745 | { |
c19d1205 ZW |
1746 | /* Create a new pool. */ |
1747 | pool = xmalloc (sizeof (* pool)); | |
1748 | if (! pool) | |
1749 | return NULL; | |
a737bd4d | 1750 | |
c19d1205 ZW |
1751 | pool->next_free_entry = 0; |
1752 | pool->section = now_seg; | |
1753 | pool->sub_section = now_subseg; | |
1754 | pool->next = list_of_pools; | |
1755 | pool->symbol = NULL; | |
1756 | ||
1757 | /* Add it to the list. */ | |
1758 | list_of_pools = pool; | |
a737bd4d | 1759 | } |
a737bd4d | 1760 | |
c19d1205 ZW |
1761 | /* New pools, and emptied pools, will have a NULL symbol. */ |
1762 | if (pool->symbol == NULL) | |
a737bd4d | 1763 | { |
c19d1205 ZW |
1764 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
1765 | (valueT) 0, &zero_address_frag); | |
1766 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
1767 | } |
1768 | ||
c19d1205 ZW |
1769 | /* Done. */ |
1770 | return pool; | |
a737bd4d NC |
1771 | } |
1772 | ||
c19d1205 ZW |
1773 | /* Add the literal in the global 'inst' |
1774 | structure to the relevent literal pool. */ | |
b99bd4ef NC |
1775 | |
1776 | static int | |
c19d1205 | 1777 | add_to_lit_pool (void) |
b99bd4ef | 1778 | { |
c19d1205 ZW |
1779 | literal_pool * pool; |
1780 | unsigned int entry; | |
b99bd4ef | 1781 | |
c19d1205 ZW |
1782 | pool = find_or_make_literal_pool (); |
1783 | ||
1784 | /* Check if this literal value is already in the pool. */ | |
1785 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 1786 | { |
c19d1205 ZW |
1787 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) |
1788 | && (inst.reloc.exp.X_op == O_constant) | |
1789 | && (pool->literals[entry].X_add_number | |
1790 | == inst.reloc.exp.X_add_number) | |
1791 | && (pool->literals[entry].X_unsigned | |
1792 | == inst.reloc.exp.X_unsigned)) | |
1793 | break; | |
1794 | ||
1795 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
1796 | && (inst.reloc.exp.X_op == O_symbol) | |
1797 | && (pool->literals[entry].X_add_number | |
1798 | == inst.reloc.exp.X_add_number) | |
1799 | && (pool->literals[entry].X_add_symbol | |
1800 | == inst.reloc.exp.X_add_symbol) | |
1801 | && (pool->literals[entry].X_op_symbol | |
1802 | == inst.reloc.exp.X_op_symbol)) | |
1803 | break; | |
b99bd4ef NC |
1804 | } |
1805 | ||
c19d1205 ZW |
1806 | /* Do we need to create a new entry? */ |
1807 | if (entry == pool->next_free_entry) | |
1808 | { | |
1809 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
1810 | { | |
1811 | inst.error = _("literal pool overflow"); | |
1812 | return FAIL; | |
1813 | } | |
1814 | ||
1815 | pool->literals[entry] = inst.reloc.exp; | |
1816 | pool->next_free_entry += 1; | |
1817 | } | |
b99bd4ef | 1818 | |
c19d1205 ZW |
1819 | inst.reloc.exp.X_op = O_symbol; |
1820 | inst.reloc.exp.X_add_number = ((int) entry) * 4; | |
1821 | inst.reloc.exp.X_add_symbol = pool->symbol; | |
b99bd4ef | 1822 | |
c19d1205 | 1823 | return SUCCESS; |
b99bd4ef NC |
1824 | } |
1825 | ||
c19d1205 ZW |
1826 | /* Can't use symbol_new here, so have to create a symbol and then at |
1827 | a later date assign it a value. Thats what these functions do. */ | |
e16bb312 | 1828 | |
c19d1205 ZW |
1829 | static void |
1830 | symbol_locate (symbolS * symbolP, | |
1831 | const char * name, /* It is copied, the caller can modify. */ | |
1832 | segT segment, /* Segment identifier (SEG_<something>). */ | |
1833 | valueT valu, /* Symbol value. */ | |
1834 | fragS * frag) /* Associated fragment. */ | |
1835 | { | |
1836 | unsigned int name_length; | |
1837 | char * preserved_copy_of_name; | |
e16bb312 | 1838 | |
c19d1205 ZW |
1839 | name_length = strlen (name) + 1; /* +1 for \0. */ |
1840 | obstack_grow (¬es, name, name_length); | |
1841 | preserved_copy_of_name = obstack_finish (¬es); | |
e16bb312 | 1842 | |
c19d1205 ZW |
1843 | #ifdef tc_canonicalize_symbol_name |
1844 | preserved_copy_of_name = | |
1845 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
1846 | #endif | |
b99bd4ef | 1847 | |
c19d1205 | 1848 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 1849 | |
c19d1205 ZW |
1850 | S_SET_SEGMENT (symbolP, segment); |
1851 | S_SET_VALUE (symbolP, valu); | |
1852 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 1853 | |
c19d1205 | 1854 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 1855 | |
c19d1205 ZW |
1856 | /* Link to end of symbol chain. */ |
1857 | { | |
1858 | extern int symbol_table_frozen; | |
b99bd4ef | 1859 | |
c19d1205 ZW |
1860 | if (symbol_table_frozen) |
1861 | abort (); | |
1862 | } | |
b99bd4ef | 1863 | |
c19d1205 | 1864 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 1865 | |
c19d1205 | 1866 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 1867 | |
c19d1205 ZW |
1868 | #ifdef tc_symbol_new_hook |
1869 | tc_symbol_new_hook (symbolP); | |
1870 | #endif | |
1871 | ||
1872 | #ifdef DEBUG_SYMS | |
1873 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
1874 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
1875 | } |
1876 | ||
b99bd4ef | 1877 | |
c19d1205 ZW |
1878 | static void |
1879 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 1880 | { |
c19d1205 ZW |
1881 | unsigned int entry; |
1882 | literal_pool * pool; | |
1883 | char sym_name[20]; | |
b99bd4ef | 1884 | |
c19d1205 ZW |
1885 | pool = find_literal_pool (); |
1886 | if (pool == NULL | |
1887 | || pool->symbol == NULL | |
1888 | || pool->next_free_entry == 0) | |
1889 | return; | |
b99bd4ef | 1890 | |
c19d1205 | 1891 | mapping_state (MAP_DATA); |
b99bd4ef | 1892 | |
c19d1205 ZW |
1893 | /* Align pool as you have word accesses. |
1894 | Only make a frag if we have to. */ | |
1895 | if (!need_pass_2) | |
1896 | frag_align (2, 0, 0); | |
b99bd4ef | 1897 | |
c19d1205 | 1898 | record_alignment (now_seg, 2); |
b99bd4ef | 1899 | |
c19d1205 | 1900 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 1901 | |
c19d1205 ZW |
1902 | symbol_locate (pool->symbol, sym_name, now_seg, |
1903 | (valueT) frag_now_fix (), frag_now); | |
1904 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 1905 | |
c19d1205 | 1906 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 1907 | |
c19d1205 ZW |
1908 | #if defined OBJ_COFF || defined OBJ_ELF |
1909 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
1910 | #endif | |
6c43fab6 | 1911 | |
c19d1205 ZW |
1912 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
1913 | /* First output the expression in the instruction to the pool. */ | |
1914 | emit_expr (&(pool->literals[entry]), 4); /* .word */ | |
b99bd4ef | 1915 | |
c19d1205 ZW |
1916 | /* Mark the pool as empty. */ |
1917 | pool->next_free_entry = 0; | |
1918 | pool->symbol = NULL; | |
b99bd4ef NC |
1919 | } |
1920 | ||
c19d1205 ZW |
1921 | #ifdef OBJ_ELF |
1922 | /* Forward declarations for functions below, in the MD interface | |
1923 | section. */ | |
1924 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
1925 | static valueT create_unwind_entry (int); | |
1926 | static void start_unwind_section (const segT, int); | |
1927 | static void add_unwind_opcode (valueT, int); | |
1928 | static void flush_pending_unwind (void); | |
b99bd4ef | 1929 | |
c19d1205 | 1930 | /* Directives: Data. */ |
b99bd4ef | 1931 | |
c19d1205 ZW |
1932 | static void |
1933 | s_arm_elf_cons (int nbytes) | |
1934 | { | |
1935 | expressionS exp; | |
b99bd4ef | 1936 | |
c19d1205 ZW |
1937 | #ifdef md_flush_pending_output |
1938 | md_flush_pending_output (); | |
1939 | #endif | |
b99bd4ef | 1940 | |
c19d1205 | 1941 | if (is_it_end_of_statement ()) |
b99bd4ef | 1942 | { |
c19d1205 ZW |
1943 | demand_empty_rest_of_line (); |
1944 | return; | |
b99bd4ef NC |
1945 | } |
1946 | ||
c19d1205 ZW |
1947 | #ifdef md_cons_align |
1948 | md_cons_align (nbytes); | |
1949 | #endif | |
b99bd4ef | 1950 | |
c19d1205 ZW |
1951 | mapping_state (MAP_DATA); |
1952 | do | |
b99bd4ef | 1953 | { |
c19d1205 ZW |
1954 | int reloc; |
1955 | char *base = input_line_pointer; | |
b99bd4ef | 1956 | |
c19d1205 | 1957 | expression (& exp); |
b99bd4ef | 1958 | |
c19d1205 ZW |
1959 | if (exp.X_op != O_symbol) |
1960 | emit_expr (&exp, (unsigned int) nbytes); | |
1961 | else | |
1962 | { | |
1963 | char *before_reloc = input_line_pointer; | |
1964 | reloc = parse_reloc (&input_line_pointer); | |
1965 | if (reloc == -1) | |
1966 | { | |
1967 | as_bad (_("unrecognized relocation suffix")); | |
1968 | ignore_rest_of_line (); | |
1969 | return; | |
1970 | } | |
1971 | else if (reloc == BFD_RELOC_UNUSED) | |
1972 | emit_expr (&exp, (unsigned int) nbytes); | |
1973 | else | |
1974 | { | |
1975 | reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc); | |
1976 | int size = bfd_get_reloc_size (howto); | |
b99bd4ef | 1977 | |
2fc8bdac ZW |
1978 | if (reloc == BFD_RELOC_ARM_PLT32) |
1979 | { | |
1980 | as_bad (_("(plt) is only valid on branch targets")); | |
1981 | reloc = BFD_RELOC_UNUSED; | |
1982 | size = 0; | |
1983 | } | |
1984 | ||
c19d1205 | 1985 | if (size > nbytes) |
2fc8bdac | 1986 | as_bad (_("%s relocations do not fit in %d bytes"), |
c19d1205 ZW |
1987 | howto->name, nbytes); |
1988 | else | |
1989 | { | |
1990 | /* We've parsed an expression stopping at O_symbol. | |
1991 | But there may be more expression left now that we | |
1992 | have parsed the relocation marker. Parse it again. | |
1993 | XXX Surely there is a cleaner way to do this. */ | |
1994 | char *p = input_line_pointer; | |
1995 | int offset; | |
1996 | char *save_buf = alloca (input_line_pointer - base); | |
1997 | memcpy (save_buf, base, input_line_pointer - base); | |
1998 | memmove (base + (input_line_pointer - before_reloc), | |
1999 | base, before_reloc - base); | |
2000 | ||
2001 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
2002 | expression (&exp); | |
2003 | memcpy (base, save_buf, p - base); | |
2004 | ||
2005 | offset = nbytes - size; | |
2006 | p = frag_more ((int) nbytes); | |
2007 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, | |
2008 | size, &exp, 0, reloc); | |
2009 | } | |
2010 | } | |
2011 | } | |
b99bd4ef | 2012 | } |
c19d1205 | 2013 | while (*input_line_pointer++ == ','); |
b99bd4ef | 2014 | |
c19d1205 ZW |
2015 | /* Put terminator back into stream. */ |
2016 | input_line_pointer --; | |
2017 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
2018 | } |
2019 | ||
b99bd4ef | 2020 | |
c19d1205 | 2021 | /* Parse a .rel31 directive. */ |
b99bd4ef | 2022 | |
c19d1205 ZW |
2023 | static void |
2024 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
2025 | { | |
2026 | expressionS exp; | |
2027 | char *p; | |
2028 | valueT highbit; | |
b99bd4ef | 2029 | |
c19d1205 ZW |
2030 | highbit = 0; |
2031 | if (*input_line_pointer == '1') | |
2032 | highbit = 0x80000000; | |
2033 | else if (*input_line_pointer != '0') | |
2034 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 2035 | |
c19d1205 ZW |
2036 | input_line_pointer++; |
2037 | if (*input_line_pointer != ',') | |
2038 | as_bad (_("missing comma")); | |
2039 | input_line_pointer++; | |
b99bd4ef | 2040 | |
c19d1205 ZW |
2041 | #ifdef md_flush_pending_output |
2042 | md_flush_pending_output (); | |
2043 | #endif | |
b99bd4ef | 2044 | |
c19d1205 ZW |
2045 | #ifdef md_cons_align |
2046 | md_cons_align (4); | |
2047 | #endif | |
b99bd4ef | 2048 | |
c19d1205 | 2049 | mapping_state (MAP_DATA); |
b99bd4ef | 2050 | |
c19d1205 | 2051 | expression (&exp); |
b99bd4ef | 2052 | |
c19d1205 ZW |
2053 | p = frag_more (4); |
2054 | md_number_to_chars (p, highbit, 4); | |
2055 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
2056 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 2057 | |
c19d1205 | 2058 | demand_empty_rest_of_line (); |
b99bd4ef NC |
2059 | } |
2060 | ||
c19d1205 | 2061 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 2062 | |
c19d1205 | 2063 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 2064 | |
c19d1205 ZW |
2065 | static void |
2066 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
2067 | { | |
2068 | demand_empty_rest_of_line (); | |
2069 | /* Mark the start of the function. */ | |
2070 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 2071 | |
c19d1205 ZW |
2072 | /* Reset the rest of the unwind info. */ |
2073 | unwind.opcode_count = 0; | |
2074 | unwind.table_entry = NULL; | |
2075 | unwind.personality_routine = NULL; | |
2076 | unwind.personality_index = -1; | |
2077 | unwind.frame_size = 0; | |
2078 | unwind.fp_offset = 0; | |
2079 | unwind.fp_reg = 13; | |
2080 | unwind.fp_used = 0; | |
2081 | unwind.sp_restored = 0; | |
2082 | } | |
b99bd4ef | 2083 | |
b99bd4ef | 2084 | |
c19d1205 ZW |
2085 | /* Parse a handlerdata directive. Creates the exception handling table entry |
2086 | for the function. */ | |
b99bd4ef | 2087 | |
c19d1205 ZW |
2088 | static void |
2089 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
2090 | { | |
2091 | demand_empty_rest_of_line (); | |
2092 | if (unwind.table_entry) | |
2093 | as_bad (_("dupicate .handlerdata directive")); | |
f02232aa | 2094 | |
c19d1205 ZW |
2095 | create_unwind_entry (1); |
2096 | } | |
a737bd4d | 2097 | |
c19d1205 | 2098 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 2099 | |
c19d1205 ZW |
2100 | static void |
2101 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
2102 | { | |
2103 | long where; | |
2104 | char *ptr; | |
2105 | valueT val; | |
f02232aa | 2106 | |
c19d1205 | 2107 | demand_empty_rest_of_line (); |
f02232aa | 2108 | |
c19d1205 ZW |
2109 | /* Add eh table entry. */ |
2110 | if (unwind.table_entry == NULL) | |
2111 | val = create_unwind_entry (0); | |
2112 | else | |
2113 | val = 0; | |
f02232aa | 2114 | |
c19d1205 ZW |
2115 | /* Add index table entry. This is two words. */ |
2116 | start_unwind_section (unwind.saved_seg, 1); | |
2117 | frag_align (2, 0, 0); | |
2118 | record_alignment (now_seg, 2); | |
b99bd4ef | 2119 | |
c19d1205 ZW |
2120 | ptr = frag_more (8); |
2121 | where = frag_now_fix () - 8; | |
f02232aa | 2122 | |
c19d1205 ZW |
2123 | /* Self relative offset of the function start. */ |
2124 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
2125 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 2126 | |
c19d1205 ZW |
2127 | /* Indicate dependency on EHABI-defined personality routines to the |
2128 | linker, if it hasn't been done already. */ | |
2129 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 | |
2130 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
2131 | { | |
2132 | static const char *const name[] = { | |
2133 | "__aeabi_unwind_cpp_pr0", | |
2134 | "__aeabi_unwind_cpp_pr1", | |
2135 | "__aeabi_unwind_cpp_pr2" | |
2136 | }; | |
2137 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); | |
2138 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
2139 | marked_pr_dependency |= 1 << unwind.personality_index; | |
2140 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency | |
2141 | = marked_pr_dependency; | |
2142 | } | |
f02232aa | 2143 | |
c19d1205 ZW |
2144 | if (val) |
2145 | /* Inline exception table entry. */ | |
2146 | md_number_to_chars (ptr + 4, val, 4); | |
2147 | else | |
2148 | /* Self relative offset of the table entry. */ | |
2149 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
2150 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 2151 | |
c19d1205 ZW |
2152 | /* Restore the original section. */ |
2153 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
2154 | } | |
f02232aa | 2155 | |
f02232aa | 2156 | |
c19d1205 | 2157 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 2158 | |
c19d1205 ZW |
2159 | static void |
2160 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
2161 | { | |
2162 | demand_empty_rest_of_line (); | |
2163 | if (unwind.personality_routine || unwind.personality_index != -1) | |
2164 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 2165 | |
c19d1205 ZW |
2166 | unwind.personality_index = -2; |
2167 | } | |
b99bd4ef | 2168 | |
b99bd4ef | 2169 | |
c19d1205 | 2170 | /* Parse a personalityindex directive. */ |
b99bd4ef | 2171 | |
c19d1205 ZW |
2172 | static void |
2173 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
2174 | { | |
2175 | expressionS exp; | |
b99bd4ef | 2176 | |
c19d1205 ZW |
2177 | if (unwind.personality_routine || unwind.personality_index != -1) |
2178 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 2179 | |
c19d1205 | 2180 | expression (&exp); |
b99bd4ef | 2181 | |
c19d1205 ZW |
2182 | if (exp.X_op != O_constant |
2183 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 2184 | { |
c19d1205 ZW |
2185 | as_bad (_("bad personality routine number")); |
2186 | ignore_rest_of_line (); | |
2187 | return; | |
b99bd4ef NC |
2188 | } |
2189 | ||
c19d1205 | 2190 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 2191 | |
c19d1205 ZW |
2192 | demand_empty_rest_of_line (); |
2193 | } | |
e16bb312 | 2194 | |
e16bb312 | 2195 | |
c19d1205 | 2196 | /* Parse a personality directive. */ |
e16bb312 | 2197 | |
c19d1205 ZW |
2198 | static void |
2199 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
2200 | { | |
2201 | char *name, *p, c; | |
a737bd4d | 2202 | |
c19d1205 ZW |
2203 | if (unwind.personality_routine || unwind.personality_index != -1) |
2204 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 2205 | |
c19d1205 ZW |
2206 | name = input_line_pointer; |
2207 | c = get_symbol_end (); | |
2208 | p = input_line_pointer; | |
2209 | unwind.personality_routine = symbol_find_or_make (name); | |
2210 | *p = c; | |
2211 | demand_empty_rest_of_line (); | |
2212 | } | |
e16bb312 | 2213 | |
e16bb312 | 2214 | |
c19d1205 | 2215 | /* Parse a directive saving core registers. */ |
e16bb312 | 2216 | |
c19d1205 ZW |
2217 | static void |
2218 | s_arm_unwind_save_core (void) | |
e16bb312 | 2219 | { |
c19d1205 ZW |
2220 | valueT op; |
2221 | long range; | |
2222 | int n; | |
e16bb312 | 2223 | |
c19d1205 ZW |
2224 | range = parse_reg_list (&input_line_pointer); |
2225 | if (range == FAIL) | |
e16bb312 | 2226 | { |
c19d1205 ZW |
2227 | as_bad (_("expected register list")); |
2228 | ignore_rest_of_line (); | |
2229 | return; | |
2230 | } | |
e16bb312 | 2231 | |
c19d1205 | 2232 | demand_empty_rest_of_line (); |
e16bb312 | 2233 | |
c19d1205 ZW |
2234 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
2235 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
2236 | ip because it is clobbered by calls. */ | |
2237 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
2238 | && (range & 0x3000) == 0x1000) | |
2239 | { | |
2240 | unwind.opcode_count--; | |
2241 | unwind.sp_restored = 0; | |
2242 | range = (range | 0x2000) & ~0x1000; | |
2243 | unwind.pending_offset = 0; | |
2244 | } | |
e16bb312 | 2245 | |
c19d1205 ZW |
2246 | /* See if we can use the short opcodes. These pop a block of upto 8 |
2247 | registers starting with r4, plus maybe r14. */ | |
2248 | for (n = 0; n < 8; n++) | |
2249 | { | |
2250 | /* Break at the first non-saved register. */ | |
2251 | if ((range & (1 << (n + 4))) == 0) | |
2252 | break; | |
e16bb312 | 2253 | } |
c19d1205 ZW |
2254 | /* See if there are any other bits set. */ |
2255 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
e16bb312 | 2256 | { |
c19d1205 ZW |
2257 | /* Use the long form. */ |
2258 | op = 0x8000 | ((range >> 4) & 0xfff); | |
2259 | add_unwind_opcode (op, 2); | |
e16bb312 | 2260 | } |
c19d1205 | 2261 | else |
0dd132b6 | 2262 | { |
c19d1205 ZW |
2263 | /* Use the short form. */ |
2264 | if (range & 0x4000) | |
2265 | op = 0xa8; /* Pop r14. */ | |
0dd132b6 | 2266 | else |
c19d1205 ZW |
2267 | op = 0xa0; /* Do not pop r14. */ |
2268 | op |= (n - 1); | |
2269 | add_unwind_opcode (op, 1); | |
2270 | } | |
0dd132b6 | 2271 | |
c19d1205 ZW |
2272 | /* Pop r0-r3. */ |
2273 | if (range & 0xf) | |
2274 | { | |
2275 | op = 0xb100 | (range & 0xf); | |
2276 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
2277 | } |
2278 | ||
c19d1205 ZW |
2279 | /* Record the number of bytes pushed. */ |
2280 | for (n = 0; n < 16; n++) | |
2281 | { | |
2282 | if (range & (1 << n)) | |
2283 | unwind.frame_size += 4; | |
2284 | } | |
0dd132b6 NC |
2285 | } |
2286 | ||
c19d1205 ZW |
2287 | |
2288 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
2289 | |
2290 | static void | |
c19d1205 | 2291 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 2292 | { |
c19d1205 ZW |
2293 | expressionS exp; |
2294 | int num_regs; | |
2295 | valueT op; | |
b99bd4ef | 2296 | |
c19d1205 ZW |
2297 | /* Get Number of registers to transfer. */ |
2298 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
2299 | expression (&exp); | |
2300 | else | |
2301 | exp.X_op = O_illegal; | |
b99bd4ef | 2302 | |
c19d1205 | 2303 | if (exp.X_op != O_constant) |
b99bd4ef | 2304 | { |
c19d1205 ZW |
2305 | as_bad (_("expected , <constant>")); |
2306 | ignore_rest_of_line (); | |
b99bd4ef NC |
2307 | return; |
2308 | } | |
2309 | ||
c19d1205 ZW |
2310 | num_regs = exp.X_add_number; |
2311 | ||
2312 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 2313 | { |
c19d1205 ZW |
2314 | as_bad (_("number of registers must be in the range [1:4]")); |
2315 | ignore_rest_of_line (); | |
b99bd4ef NC |
2316 | return; |
2317 | } | |
2318 | ||
c19d1205 | 2319 | demand_empty_rest_of_line (); |
b99bd4ef | 2320 | |
c19d1205 ZW |
2321 | if (reg == 4) |
2322 | { | |
2323 | /* Short form. */ | |
2324 | op = 0xb4 | (num_regs - 1); | |
2325 | add_unwind_opcode (op, 1); | |
2326 | } | |
b99bd4ef NC |
2327 | else |
2328 | { | |
c19d1205 ZW |
2329 | /* Long form. */ |
2330 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
2331 | add_unwind_opcode (op, 2); | |
b99bd4ef | 2332 | } |
c19d1205 | 2333 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
2334 | } |
2335 | ||
c19d1205 ZW |
2336 | |
2337 | /* Parse a directive saving VFP registers. */ | |
b99bd4ef NC |
2338 | |
2339 | static void | |
c19d1205 | 2340 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 2341 | { |
c19d1205 | 2342 | int count; |
ca3f61f7 | 2343 | unsigned int reg; |
c19d1205 | 2344 | valueT op; |
b99bd4ef | 2345 | |
c19d1205 ZW |
2346 | count = parse_vfp_reg_list (&input_line_pointer, ®, 1); |
2347 | if (count == FAIL) | |
b99bd4ef | 2348 | { |
c19d1205 ZW |
2349 | as_bad (_("expected register list")); |
2350 | ignore_rest_of_line (); | |
b99bd4ef NC |
2351 | return; |
2352 | } | |
2353 | ||
c19d1205 | 2354 | demand_empty_rest_of_line (); |
b99bd4ef | 2355 | |
c19d1205 | 2356 | if (reg == 8) |
b99bd4ef | 2357 | { |
c19d1205 ZW |
2358 | /* Short form. */ |
2359 | op = 0xb8 | (count - 1); | |
2360 | add_unwind_opcode (op, 1); | |
b99bd4ef | 2361 | } |
c19d1205 | 2362 | else |
b99bd4ef | 2363 | { |
c19d1205 ZW |
2364 | /* Long form. */ |
2365 | op = 0xb300 | (reg << 4) | (count - 1); | |
2366 | add_unwind_opcode (op, 2); | |
b99bd4ef | 2367 | } |
c19d1205 ZW |
2368 | unwind.frame_size += count * 8 + 4; |
2369 | } | |
b99bd4ef | 2370 | |
b99bd4ef | 2371 | |
c19d1205 ZW |
2372 | /* Parse a directive saving iWMMXt data registers. */ |
2373 | ||
2374 | static void | |
2375 | s_arm_unwind_save_mmxwr (void) | |
2376 | { | |
2377 | int reg; | |
2378 | int hi_reg; | |
2379 | int i; | |
2380 | unsigned mask = 0; | |
2381 | valueT op; | |
b99bd4ef | 2382 | |
c19d1205 ZW |
2383 | if (*input_line_pointer == '{') |
2384 | input_line_pointer++; | |
b99bd4ef | 2385 | |
c19d1205 | 2386 | do |
b99bd4ef | 2387 | { |
c19d1205 | 2388 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 2389 | |
c19d1205 | 2390 | if (reg == FAIL) |
b99bd4ef | 2391 | { |
c19d1205 ZW |
2392 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); |
2393 | goto error; | |
b99bd4ef NC |
2394 | } |
2395 | ||
c19d1205 ZW |
2396 | if (mask >> reg) |
2397 | as_tsktsk (_("register list not in ascending order")); | |
2398 | mask |= 1 << reg; | |
b99bd4ef | 2399 | |
c19d1205 ZW |
2400 | if (*input_line_pointer == '-') |
2401 | { | |
2402 | input_line_pointer++; | |
2403 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); | |
2404 | if (hi_reg == FAIL) | |
2405 | { | |
2406 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); | |
2407 | goto error; | |
2408 | } | |
2409 | else if (reg >= hi_reg) | |
2410 | { | |
2411 | as_bad (_("bad register range")); | |
2412 | goto error; | |
2413 | } | |
2414 | for (; reg < hi_reg; reg++) | |
2415 | mask |= 1 << reg; | |
2416 | } | |
2417 | } | |
2418 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 2419 | |
c19d1205 ZW |
2420 | if (*input_line_pointer == '}') |
2421 | input_line_pointer++; | |
b99bd4ef | 2422 | |
c19d1205 | 2423 | demand_empty_rest_of_line (); |
b99bd4ef | 2424 | |
c19d1205 ZW |
2425 | /* Generate any deferred opcodes becuuse we're going to be looking at |
2426 | the list. */ | |
2427 | flush_pending_unwind (); | |
b99bd4ef | 2428 | |
c19d1205 | 2429 | for (i = 0; i < 16; i++) |
b99bd4ef | 2430 | { |
c19d1205 ZW |
2431 | if (mask & (1 << i)) |
2432 | unwind.frame_size += 8; | |
b99bd4ef NC |
2433 | } |
2434 | ||
c19d1205 ZW |
2435 | /* Attempt to combine with a previous opcode. We do this because gcc |
2436 | likes to output separate unwind directives for a single block of | |
2437 | registers. */ | |
2438 | if (unwind.opcode_count > 0) | |
b99bd4ef | 2439 | { |
c19d1205 ZW |
2440 | i = unwind.opcodes[unwind.opcode_count - 1]; |
2441 | if ((i & 0xf8) == 0xc0) | |
2442 | { | |
2443 | i &= 7; | |
2444 | /* Only merge if the blocks are contiguous. */ | |
2445 | if (i < 6) | |
2446 | { | |
2447 | if ((mask & 0xfe00) == (1 << 9)) | |
2448 | { | |
2449 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
2450 | unwind.opcode_count--; | |
2451 | } | |
2452 | } | |
2453 | else if (i == 6 && unwind.opcode_count >= 2) | |
2454 | { | |
2455 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
2456 | reg = i >> 4; | |
2457 | i &= 0xf; | |
b99bd4ef | 2458 | |
c19d1205 ZW |
2459 | op = 0xffff << (reg - 1); |
2460 | if (reg > 0 | |
2461 | || ((mask & op) == (1u << (reg - 1)))) | |
2462 | { | |
2463 | op = (1 << (reg + i + 1)) - 1; | |
2464 | op &= ~((1 << reg) - 1); | |
2465 | mask |= op; | |
2466 | unwind.opcode_count -= 2; | |
2467 | } | |
2468 | } | |
2469 | } | |
b99bd4ef NC |
2470 | } |
2471 | ||
c19d1205 ZW |
2472 | hi_reg = 15; |
2473 | /* We want to generate opcodes in the order the registers have been | |
2474 | saved, ie. descending order. */ | |
2475 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 2476 | { |
c19d1205 ZW |
2477 | /* Save registers in blocks. */ |
2478 | if (reg < 0 | |
2479 | || !(mask & (1 << reg))) | |
2480 | { | |
2481 | /* We found an unsaved reg. Generate opcodes to save the | |
2482 | preceeding block. */ | |
2483 | if (reg != hi_reg) | |
2484 | { | |
2485 | if (reg == 9) | |
2486 | { | |
2487 | /* Short form. */ | |
2488 | op = 0xc0 | (hi_reg - 10); | |
2489 | add_unwind_opcode (op, 1); | |
2490 | } | |
2491 | else | |
2492 | { | |
2493 | /* Long form. */ | |
2494 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
2495 | add_unwind_opcode (op, 2); | |
2496 | } | |
2497 | } | |
2498 | hi_reg = reg - 1; | |
2499 | } | |
b99bd4ef NC |
2500 | } |
2501 | ||
c19d1205 ZW |
2502 | return; |
2503 | error: | |
2504 | ignore_rest_of_line (); | |
b99bd4ef NC |
2505 | } |
2506 | ||
2507 | static void | |
c19d1205 | 2508 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 2509 | { |
c19d1205 ZW |
2510 | int reg; |
2511 | int hi_reg; | |
2512 | unsigned mask = 0; | |
2513 | valueT op; | |
b99bd4ef | 2514 | |
c19d1205 ZW |
2515 | if (*input_line_pointer == '{') |
2516 | input_line_pointer++; | |
b99bd4ef | 2517 | |
c19d1205 | 2518 | do |
b99bd4ef | 2519 | { |
c19d1205 | 2520 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 2521 | |
c19d1205 ZW |
2522 | if (reg == FAIL) |
2523 | { | |
2524 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); | |
2525 | goto error; | |
2526 | } | |
b99bd4ef | 2527 | |
c19d1205 ZW |
2528 | reg -= 8; |
2529 | if (mask >> reg) | |
2530 | as_tsktsk (_("register list not in ascending order")); | |
2531 | mask |= 1 << reg; | |
b99bd4ef | 2532 | |
c19d1205 ZW |
2533 | if (*input_line_pointer == '-') |
2534 | { | |
2535 | input_line_pointer++; | |
2536 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); | |
2537 | if (hi_reg == FAIL) | |
2538 | { | |
2539 | as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); | |
2540 | goto error; | |
2541 | } | |
2542 | else if (reg >= hi_reg) | |
2543 | { | |
2544 | as_bad (_("bad register range")); | |
2545 | goto error; | |
2546 | } | |
2547 | for (; reg < hi_reg; reg++) | |
2548 | mask |= 1 << reg; | |
2549 | } | |
b99bd4ef | 2550 | } |
c19d1205 | 2551 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 2552 | |
c19d1205 ZW |
2553 | if (*input_line_pointer == '}') |
2554 | input_line_pointer++; | |
b99bd4ef | 2555 | |
c19d1205 ZW |
2556 | demand_empty_rest_of_line (); |
2557 | ||
2558 | /* Generate any deferred opcodes becuuse we're going to be looking at | |
2559 | the list. */ | |
2560 | flush_pending_unwind (); | |
b99bd4ef | 2561 | |
c19d1205 | 2562 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 2563 | { |
c19d1205 ZW |
2564 | if (mask & (1 << reg)) |
2565 | unwind.frame_size += 4; | |
b99bd4ef | 2566 | } |
c19d1205 ZW |
2567 | op = 0xc700 | mask; |
2568 | add_unwind_opcode (op, 2); | |
2569 | return; | |
2570 | error: | |
2571 | ignore_rest_of_line (); | |
b99bd4ef NC |
2572 | } |
2573 | ||
c19d1205 ZW |
2574 | |
2575 | /* Parse an unwind_save directive. */ | |
2576 | ||
b99bd4ef | 2577 | static void |
c19d1205 | 2578 | s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED) |
b99bd4ef | 2579 | { |
c19d1205 ZW |
2580 | char *peek; |
2581 | struct reg_entry *reg; | |
2582 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 2583 | |
c19d1205 ZW |
2584 | /* Figure out what sort of save we have. */ |
2585 | peek = input_line_pointer; | |
b99bd4ef | 2586 | |
c19d1205 | 2587 | if (*peek == '{') |
b99bd4ef | 2588 | { |
c19d1205 ZW |
2589 | had_brace = TRUE; |
2590 | peek++; | |
b99bd4ef NC |
2591 | } |
2592 | ||
c19d1205 | 2593 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 2594 | |
c19d1205 | 2595 | if (!reg) |
b99bd4ef | 2596 | { |
c19d1205 ZW |
2597 | as_bad (_("register expected")); |
2598 | ignore_rest_of_line (); | |
b99bd4ef NC |
2599 | return; |
2600 | } | |
2601 | ||
c19d1205 | 2602 | switch (reg->type) |
b99bd4ef | 2603 | { |
c19d1205 ZW |
2604 | case REG_TYPE_FN: |
2605 | if (had_brace) | |
2606 | { | |
2607 | as_bad (_("FPA .unwind_save does not take a register list")); | |
2608 | ignore_rest_of_line (); | |
2609 | return; | |
2610 | } | |
2611 | s_arm_unwind_save_fpa (reg->number); | |
b99bd4ef | 2612 | return; |
c19d1205 ZW |
2613 | |
2614 | case REG_TYPE_RN: s_arm_unwind_save_core (); return; | |
2615 | case REG_TYPE_VFD: s_arm_unwind_save_vfp (); return; | |
2616 | case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; | |
2617 | case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; | |
2618 | ||
2619 | default: | |
2620 | as_bad (_(".unwind_save does not support this kind of register")); | |
2621 | ignore_rest_of_line (); | |
b99bd4ef | 2622 | } |
c19d1205 | 2623 | } |
b99bd4ef | 2624 | |
b99bd4ef | 2625 | |
c19d1205 ZW |
2626 | /* Parse an unwind_movsp directive. */ |
2627 | ||
2628 | static void | |
2629 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
2630 | { | |
2631 | int reg; | |
2632 | valueT op; | |
2633 | ||
2634 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); | |
2635 | if (reg == FAIL) | |
b99bd4ef | 2636 | { |
c19d1205 ZW |
2637 | as_bad (_(reg_expected_msgs[REG_TYPE_RN])); |
2638 | ignore_rest_of_line (); | |
b99bd4ef NC |
2639 | return; |
2640 | } | |
c19d1205 | 2641 | demand_empty_rest_of_line (); |
b99bd4ef | 2642 | |
c19d1205 | 2643 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 2644 | { |
c19d1205 | 2645 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
2646 | return; |
2647 | } | |
2648 | ||
c19d1205 ZW |
2649 | if (unwind.fp_reg != REG_SP) |
2650 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 2651 | |
c19d1205 ZW |
2652 | /* Generate opcode to restore the value. */ |
2653 | op = 0x90 | reg; | |
2654 | add_unwind_opcode (op, 1); | |
2655 | ||
2656 | /* Record the information for later. */ | |
2657 | unwind.fp_reg = reg; | |
2658 | unwind.fp_offset = unwind.frame_size; | |
2659 | unwind.sp_restored = 1; | |
b05fe5cf ZW |
2660 | } |
2661 | ||
c19d1205 ZW |
2662 | /* Parse an unwind_pad directive. */ |
2663 | ||
b05fe5cf | 2664 | static void |
c19d1205 | 2665 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 2666 | { |
c19d1205 | 2667 | int offset; |
b05fe5cf | 2668 | |
c19d1205 ZW |
2669 | if (immediate_for_directive (&offset) == FAIL) |
2670 | return; | |
b99bd4ef | 2671 | |
c19d1205 ZW |
2672 | if (offset & 3) |
2673 | { | |
2674 | as_bad (_("stack increment must be multiple of 4")); | |
2675 | ignore_rest_of_line (); | |
2676 | return; | |
2677 | } | |
b99bd4ef | 2678 | |
c19d1205 ZW |
2679 | /* Don't generate any opcodes, just record the details for later. */ |
2680 | unwind.frame_size += offset; | |
2681 | unwind.pending_offset += offset; | |
2682 | ||
2683 | demand_empty_rest_of_line (); | |
2684 | } | |
2685 | ||
2686 | /* Parse an unwind_setfp directive. */ | |
2687 | ||
2688 | static void | |
2689 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 2690 | { |
c19d1205 ZW |
2691 | int sp_reg; |
2692 | int fp_reg; | |
2693 | int offset; | |
2694 | ||
2695 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); | |
2696 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
2697 | sp_reg = FAIL; | |
2698 | else | |
2699 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); | |
b99bd4ef | 2700 | |
c19d1205 ZW |
2701 | if (fp_reg == FAIL || sp_reg == FAIL) |
2702 | { | |
2703 | as_bad (_("expected <reg>, <reg>")); | |
2704 | ignore_rest_of_line (); | |
2705 | return; | |
2706 | } | |
b99bd4ef | 2707 | |
c19d1205 ZW |
2708 | /* Optional constant. */ |
2709 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
2710 | { | |
2711 | if (immediate_for_directive (&offset) == FAIL) | |
2712 | return; | |
2713 | } | |
2714 | else | |
2715 | offset = 0; | |
a737bd4d | 2716 | |
c19d1205 | 2717 | demand_empty_rest_of_line (); |
a737bd4d | 2718 | |
c19d1205 | 2719 | if (sp_reg != 13 && sp_reg != unwind.fp_reg) |
a737bd4d | 2720 | { |
c19d1205 ZW |
2721 | as_bad (_("register must be either sp or set by a previous" |
2722 | "unwind_movsp directive")); | |
2723 | return; | |
a737bd4d NC |
2724 | } |
2725 | ||
c19d1205 ZW |
2726 | /* Don't generate any opcodes, just record the information for later. */ |
2727 | unwind.fp_reg = fp_reg; | |
2728 | unwind.fp_used = 1; | |
2729 | if (sp_reg == 13) | |
2730 | unwind.fp_offset = unwind.frame_size - offset; | |
2731 | else | |
2732 | unwind.fp_offset -= offset; | |
a737bd4d NC |
2733 | } |
2734 | ||
c19d1205 ZW |
2735 | /* Parse an unwind_raw directive. */ |
2736 | ||
2737 | static void | |
2738 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 2739 | { |
c19d1205 ZW |
2740 | expressionS exp; |
2741 | /* This is an arbitary limit. */ | |
2742 | unsigned char op[16]; | |
2743 | int count; | |
a737bd4d | 2744 | |
c19d1205 ZW |
2745 | expression (&exp); |
2746 | if (exp.X_op == O_constant | |
2747 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 2748 | { |
c19d1205 ZW |
2749 | unwind.frame_size += exp.X_add_number; |
2750 | expression (&exp); | |
2751 | } | |
2752 | else | |
2753 | exp.X_op = O_illegal; | |
a737bd4d | 2754 | |
c19d1205 ZW |
2755 | if (exp.X_op != O_constant) |
2756 | { | |
2757 | as_bad (_("expected <offset>, <opcode>")); | |
2758 | ignore_rest_of_line (); | |
2759 | return; | |
2760 | } | |
a737bd4d | 2761 | |
c19d1205 | 2762 | count = 0; |
a737bd4d | 2763 | |
c19d1205 ZW |
2764 | /* Parse the opcode. */ |
2765 | for (;;) | |
2766 | { | |
2767 | if (count >= 16) | |
2768 | { | |
2769 | as_bad (_("unwind opcode too long")); | |
2770 | ignore_rest_of_line (); | |
a737bd4d | 2771 | } |
c19d1205 | 2772 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 2773 | { |
c19d1205 ZW |
2774 | as_bad (_("invalid unwind opcode")); |
2775 | ignore_rest_of_line (); | |
2776 | return; | |
a737bd4d | 2777 | } |
c19d1205 | 2778 | op[count++] = exp.X_add_number; |
a737bd4d | 2779 | |
c19d1205 ZW |
2780 | /* Parse the next byte. */ |
2781 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
2782 | break; | |
a737bd4d | 2783 | |
c19d1205 ZW |
2784 | expression (&exp); |
2785 | } | |
b99bd4ef | 2786 | |
c19d1205 ZW |
2787 | /* Add the opcode bytes in reverse order. */ |
2788 | while (count--) | |
2789 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 2790 | |
c19d1205 | 2791 | demand_empty_rest_of_line (); |
b99bd4ef | 2792 | } |
c19d1205 | 2793 | #endif /* OBJ_ELF */ |
b99bd4ef | 2794 | |
c19d1205 ZW |
2795 | /* This table describes all the machine specific pseudo-ops the assembler |
2796 | has to support. The fields are: | |
2797 | pseudo-op name without dot | |
2798 | function to call to execute this pseudo-op | |
2799 | Integer arg to pass to the function. */ | |
b99bd4ef | 2800 | |
c19d1205 | 2801 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 2802 | { |
c19d1205 ZW |
2803 | /* Never called because '.req' does not start a line. */ |
2804 | { "req", s_req, 0 }, | |
2805 | { "unreq", s_unreq, 0 }, | |
2806 | { "bss", s_bss, 0 }, | |
2807 | { "align", s_align, 0 }, | |
2808 | { "arm", s_arm, 0 }, | |
2809 | { "thumb", s_thumb, 0 }, | |
2810 | { "code", s_code, 0 }, | |
2811 | { "force_thumb", s_force_thumb, 0 }, | |
2812 | { "thumb_func", s_thumb_func, 0 }, | |
2813 | { "thumb_set", s_thumb_set, 0 }, | |
2814 | { "even", s_even, 0 }, | |
2815 | { "ltorg", s_ltorg, 0 }, | |
2816 | { "pool", s_ltorg, 0 }, | |
2817 | { "syntax", s_syntax, 0 }, | |
2818 | #ifdef OBJ_ELF | |
2819 | { "word", s_arm_elf_cons, 4 }, | |
2820 | { "long", s_arm_elf_cons, 4 }, | |
2821 | { "rel31", s_arm_rel31, 0 }, | |
2822 | { "fnstart", s_arm_unwind_fnstart, 0 }, | |
2823 | { "fnend", s_arm_unwind_fnend, 0 }, | |
2824 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
2825 | { "personality", s_arm_unwind_personality, 0 }, | |
2826 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
2827 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
2828 | { "save", s_arm_unwind_save, 0 }, | |
2829 | { "movsp", s_arm_unwind_movsp, 0 }, | |
2830 | { "pad", s_arm_unwind_pad, 0 }, | |
2831 | { "setfp", s_arm_unwind_setfp, 0 }, | |
2832 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
2833 | #else | |
2834 | { "word", cons, 4}, | |
2835 | #endif | |
2836 | { "extend", float_cons, 'x' }, | |
2837 | { "ldouble", float_cons, 'x' }, | |
2838 | { "packed", float_cons, 'p' }, | |
2839 | { 0, 0, 0 } | |
2840 | }; | |
2841 | \f | |
2842 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 2843 | |
c19d1205 ZW |
2844 | /* Generic immediate-value read function for use in insn parsing. |
2845 | STR points to the beginning of the immediate (the leading #); | |
2846 | VAL receives the value; if the value is outside [MIN, MAX] | |
2847 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
2848 | optional. */ | |
b99bd4ef | 2849 | |
c19d1205 ZW |
2850 | static int |
2851 | parse_immediate (char **str, int *val, int min, int max, | |
2852 | bfd_boolean prefix_opt) | |
2853 | { | |
2854 | expressionS exp; | |
2855 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); | |
2856 | if (exp.X_op != O_constant) | |
b99bd4ef | 2857 | { |
c19d1205 ZW |
2858 | inst.error = _("constant expression required"); |
2859 | return FAIL; | |
2860 | } | |
b99bd4ef | 2861 | |
c19d1205 ZW |
2862 | if (exp.X_add_number < min || exp.X_add_number > max) |
2863 | { | |
2864 | inst.error = _("immediate value out of range"); | |
2865 | return FAIL; | |
2866 | } | |
b99bd4ef | 2867 | |
c19d1205 ZW |
2868 | *val = exp.X_add_number; |
2869 | return SUCCESS; | |
2870 | } | |
b99bd4ef | 2871 | |
c19d1205 ZW |
2872 | /* Returns the pseudo-register number of an FPA immediate constant, |
2873 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 2874 | |
c19d1205 ZW |
2875 | static int |
2876 | parse_fpa_immediate (char ** str) | |
2877 | { | |
2878 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
2879 | char * save_in; | |
2880 | expressionS exp; | |
2881 | int i; | |
2882 | int j; | |
b99bd4ef | 2883 | |
c19d1205 ZW |
2884 | /* First try and match exact strings, this is to guarantee |
2885 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 2886 | |
c19d1205 ZW |
2887 | for (i = 0; fp_const[i]; i++) |
2888 | { | |
2889 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 2890 | { |
c19d1205 | 2891 | char *start = *str; |
b99bd4ef | 2892 | |
c19d1205 ZW |
2893 | *str += strlen (fp_const[i]); |
2894 | if (is_end_of_line[(unsigned char) **str]) | |
2895 | return i + 8; | |
2896 | *str = start; | |
2897 | } | |
2898 | } | |
b99bd4ef | 2899 | |
c19d1205 ZW |
2900 | /* Just because we didn't get a match doesn't mean that the constant |
2901 | isn't valid, just that it is in a format that we don't | |
2902 | automatically recognize. Try parsing it with the standard | |
2903 | expression routines. */ | |
b99bd4ef | 2904 | |
c19d1205 | 2905 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 2906 | |
c19d1205 ZW |
2907 | /* Look for a raw floating point number. */ |
2908 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
2909 | && is_end_of_line[(unsigned char) *save_in]) | |
2910 | { | |
2911 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
2912 | { | |
2913 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 2914 | { |
c19d1205 ZW |
2915 | if (words[j] != fp_values[i][j]) |
2916 | break; | |
b99bd4ef NC |
2917 | } |
2918 | ||
c19d1205 | 2919 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 2920 | { |
c19d1205 ZW |
2921 | *str = save_in; |
2922 | return i + 8; | |
b99bd4ef NC |
2923 | } |
2924 | } | |
2925 | } | |
b99bd4ef | 2926 | |
c19d1205 ZW |
2927 | /* Try and parse a more complex expression, this will probably fail |
2928 | unless the code uses a floating point prefix (eg "0f"). */ | |
2929 | save_in = input_line_pointer; | |
2930 | input_line_pointer = *str; | |
2931 | if (expression (&exp) == absolute_section | |
2932 | && exp.X_op == O_big | |
2933 | && exp.X_add_number < 0) | |
2934 | { | |
2935 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
2936 | Ditto for 15. */ | |
2937 | if (gen_to_words (words, 5, (long) 15) == 0) | |
2938 | { | |
2939 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
2940 | { | |
2941 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
2942 | { | |
2943 | if (words[j] != fp_values[i][j]) | |
2944 | break; | |
2945 | } | |
b99bd4ef | 2946 | |
c19d1205 ZW |
2947 | if (j == MAX_LITTLENUMS) |
2948 | { | |
2949 | *str = input_line_pointer; | |
2950 | input_line_pointer = save_in; | |
2951 | return i + 8; | |
2952 | } | |
2953 | } | |
2954 | } | |
b99bd4ef NC |
2955 | } |
2956 | ||
c19d1205 ZW |
2957 | *str = input_line_pointer; |
2958 | input_line_pointer = save_in; | |
2959 | inst.error = _("invalid FPA immediate expression"); | |
2960 | return FAIL; | |
b99bd4ef NC |
2961 | } |
2962 | ||
c19d1205 ZW |
2963 | /* Shift operands. */ |
2964 | enum shift_kind | |
b99bd4ef | 2965 | { |
c19d1205 ZW |
2966 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
2967 | }; | |
b99bd4ef | 2968 | |
c19d1205 ZW |
2969 | struct asm_shift_name |
2970 | { | |
2971 | const char *name; | |
2972 | enum shift_kind kind; | |
2973 | }; | |
b99bd4ef | 2974 | |
c19d1205 ZW |
2975 | /* Third argument to parse_shift. */ |
2976 | enum parse_shift_mode | |
2977 | { | |
2978 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
2979 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
2980 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
2981 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
2982 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
2983 | }; | |
b99bd4ef | 2984 | |
c19d1205 ZW |
2985 | /* Parse a <shift> specifier on an ARM data processing instruction. |
2986 | This has three forms: | |
b99bd4ef | 2987 | |
c19d1205 ZW |
2988 | (LSL|LSR|ASL|ASR|ROR) Rs |
2989 | (LSL|LSR|ASL|ASR|ROR) #imm | |
2990 | RRX | |
b99bd4ef | 2991 | |
c19d1205 ZW |
2992 | Note that ASL is assimilated to LSL in the instruction encoding, and |
2993 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 2994 | |
c19d1205 ZW |
2995 | static int |
2996 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 2997 | { |
c19d1205 ZW |
2998 | const struct asm_shift_name *shift_name; |
2999 | enum shift_kind shift; | |
3000 | char *s = *str; | |
3001 | char *p = s; | |
3002 | int reg; | |
b99bd4ef | 3003 | |
c19d1205 ZW |
3004 | for (p = *str; ISALPHA (*p); p++) |
3005 | ; | |
b99bd4ef | 3006 | |
c19d1205 | 3007 | if (p == *str) |
b99bd4ef | 3008 | { |
c19d1205 ZW |
3009 | inst.error = _("shift expression expected"); |
3010 | return FAIL; | |
b99bd4ef NC |
3011 | } |
3012 | ||
c19d1205 ZW |
3013 | shift_name = hash_find_n (arm_shift_hsh, *str, p - *str); |
3014 | ||
3015 | if (shift_name == NULL) | |
b99bd4ef | 3016 | { |
c19d1205 ZW |
3017 | inst.error = _("shift expression expected"); |
3018 | return FAIL; | |
b99bd4ef NC |
3019 | } |
3020 | ||
c19d1205 | 3021 | shift = shift_name->kind; |
b99bd4ef | 3022 | |
c19d1205 ZW |
3023 | switch (mode) |
3024 | { | |
3025 | case NO_SHIFT_RESTRICT: | |
3026 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 3027 | |
c19d1205 ZW |
3028 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
3029 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
3030 | { | |
3031 | inst.error = _("'LSL' or 'ASR' required"); | |
3032 | return FAIL; | |
3033 | } | |
3034 | break; | |
b99bd4ef | 3035 | |
c19d1205 ZW |
3036 | case SHIFT_LSL_IMMEDIATE: |
3037 | if (shift != SHIFT_LSL) | |
3038 | { | |
3039 | inst.error = _("'LSL' required"); | |
3040 | return FAIL; | |
3041 | } | |
3042 | break; | |
b99bd4ef | 3043 | |
c19d1205 ZW |
3044 | case SHIFT_ASR_IMMEDIATE: |
3045 | if (shift != SHIFT_ASR) | |
3046 | { | |
3047 | inst.error = _("'ASR' required"); | |
3048 | return FAIL; | |
3049 | } | |
3050 | break; | |
b99bd4ef | 3051 | |
c19d1205 ZW |
3052 | default: abort (); |
3053 | } | |
b99bd4ef | 3054 | |
c19d1205 ZW |
3055 | if (shift != SHIFT_RRX) |
3056 | { | |
3057 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
3058 | skip_whitespace (p); | |
b99bd4ef | 3059 | |
c19d1205 ZW |
3060 | if (mode == NO_SHIFT_RESTRICT |
3061 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) | |
3062 | { | |
3063 | inst.operands[i].imm = reg; | |
3064 | inst.operands[i].immisreg = 1; | |
3065 | } | |
3066 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
3067 | return FAIL; | |
3068 | } | |
3069 | inst.operands[i].shift_kind = shift; | |
3070 | inst.operands[i].shifted = 1; | |
3071 | *str = p; | |
3072 | return SUCCESS; | |
b99bd4ef NC |
3073 | } |
3074 | ||
c19d1205 | 3075 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 3076 | |
c19d1205 ZW |
3077 | #<immediate> |
3078 | #<immediate>, <rotate> | |
3079 | <Rm> | |
3080 | <Rm>, <shift> | |
b99bd4ef | 3081 | |
c19d1205 ZW |
3082 | where <shift> is defined by parse_shift above, and <rotate> is a |
3083 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 3084 | is deferred to md_apply_fix. */ |
b99bd4ef | 3085 | |
c19d1205 ZW |
3086 | static int |
3087 | parse_shifter_operand (char **str, int i) | |
3088 | { | |
3089 | int value; | |
3090 | expressionS expr; | |
b99bd4ef | 3091 | |
c19d1205 ZW |
3092 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
3093 | { | |
3094 | inst.operands[i].reg = value; | |
3095 | inst.operands[i].isreg = 1; | |
b99bd4ef | 3096 | |
c19d1205 ZW |
3097 | /* parse_shift will override this if appropriate */ |
3098 | inst.reloc.exp.X_op = O_constant; | |
3099 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 3100 | |
c19d1205 ZW |
3101 | if (skip_past_comma (str) == FAIL) |
3102 | return SUCCESS; | |
b99bd4ef | 3103 | |
c19d1205 ZW |
3104 | /* Shift operation on register. */ |
3105 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
3106 | } |
3107 | ||
c19d1205 ZW |
3108 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
3109 | return FAIL; | |
b99bd4ef | 3110 | |
c19d1205 | 3111 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 3112 | { |
c19d1205 ZW |
3113 | /* #x, y -- ie explicit rotation by Y. */ |
3114 | if (my_get_expression (&expr, str, GE_NO_PREFIX)) | |
3115 | return FAIL; | |
b99bd4ef | 3116 | |
c19d1205 ZW |
3117 | if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
3118 | { | |
3119 | inst.error = _("constant expression expected"); | |
3120 | return FAIL; | |
3121 | } | |
b99bd4ef | 3122 | |
c19d1205 ZW |
3123 | value = expr.X_add_number; |
3124 | if (value < 0 || value > 30 || value % 2 != 0) | |
3125 | { | |
3126 | inst.error = _("invalid rotation"); | |
3127 | return FAIL; | |
3128 | } | |
3129 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
3130 | { | |
3131 | inst.error = _("invalid constant"); | |
3132 | return FAIL; | |
3133 | } | |
09d92015 | 3134 | |
55cf6793 | 3135 | /* Convert to decoded value. md_apply_fix will put it back. */ |
c19d1205 ZW |
3136 | inst.reloc.exp.X_add_number |
3137 | = (((inst.reloc.exp.X_add_number << (32 - value)) | |
3138 | | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); | |
09d92015 MM |
3139 | } |
3140 | ||
c19d1205 ZW |
3141 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
3142 | inst.reloc.pc_rel = 0; | |
3143 | return SUCCESS; | |
09d92015 MM |
3144 | } |
3145 | ||
c19d1205 ZW |
3146 | /* Parse all forms of an ARM address expression. Information is written |
3147 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 3148 | |
c19d1205 | 3149 | Preindexed addressing (.preind=1): |
09d92015 | 3150 | |
c19d1205 ZW |
3151 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
3152 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
3153 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
3154 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 3155 | |
c19d1205 | 3156 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 3157 | |
c19d1205 | 3158 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 3159 | |
c19d1205 ZW |
3160 | [Rn], #offset .reg=Rn .reloc.exp=offset |
3161 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
3162 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
3163 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 3164 | |
c19d1205 | 3165 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 3166 | |
c19d1205 | 3167 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 3168 | |
c19d1205 | 3169 | Other: |
09d92015 | 3170 | |
c19d1205 ZW |
3171 | [Rn]{!} shorthand for [Rn,#0]{!} |
3172 | =immediate .isreg=0 .reloc.exp=immediate | |
3173 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 3174 | |
c19d1205 ZW |
3175 | It is the caller's responsibility to check for addressing modes not |
3176 | supported by the instruction, and to set inst.reloc.type. */ | |
3177 | ||
3178 | static int | |
3179 | parse_address (char **str, int i) | |
09d92015 | 3180 | { |
c19d1205 ZW |
3181 | char *p = *str; |
3182 | int reg; | |
09d92015 | 3183 | |
c19d1205 | 3184 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 3185 | { |
c19d1205 ZW |
3186 | if (skip_past_char (&p, '=') == FAIL) |
3187 | { | |
3188 | /* bare address - translate to PC-relative offset */ | |
3189 | inst.reloc.pc_rel = 1; | |
3190 | inst.operands[i].reg = REG_PC; | |
3191 | inst.operands[i].isreg = 1; | |
3192 | inst.operands[i].preind = 1; | |
3193 | } | |
3194 | /* else a load-constant pseudo op, no special treatment needed here */ | |
09d92015 | 3195 | |
c19d1205 ZW |
3196 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
3197 | return FAIL; | |
09d92015 | 3198 | |
c19d1205 ZW |
3199 | *str = p; |
3200 | return SUCCESS; | |
09d92015 MM |
3201 | } |
3202 | ||
c19d1205 | 3203 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 3204 | { |
c19d1205 ZW |
3205 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
3206 | return FAIL; | |
09d92015 | 3207 | } |
c19d1205 ZW |
3208 | inst.operands[i].reg = reg; |
3209 | inst.operands[i].isreg = 1; | |
09d92015 | 3210 | |
c19d1205 | 3211 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 3212 | { |
c19d1205 | 3213 | inst.operands[i].preind = 1; |
09d92015 | 3214 | |
c19d1205 ZW |
3215 | if (*p == '+') p++; |
3216 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
3217 | ||
3218 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) | |
09d92015 | 3219 | { |
c19d1205 ZW |
3220 | inst.operands[i].imm = reg; |
3221 | inst.operands[i].immisreg = 1; | |
3222 | ||
3223 | if (skip_past_comma (&p) == SUCCESS) | |
3224 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
3225 | return FAIL; | |
3226 | } | |
3227 | else | |
3228 | { | |
3229 | if (inst.operands[i].negative) | |
3230 | { | |
3231 | inst.operands[i].negative = 0; | |
3232 | p--; | |
3233 | } | |
3234 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
3235 | return FAIL; | |
09d92015 MM |
3236 | } |
3237 | } | |
3238 | ||
c19d1205 | 3239 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 3240 | { |
c19d1205 ZW |
3241 | inst.error = _("']' expected"); |
3242 | return FAIL; | |
09d92015 MM |
3243 | } |
3244 | ||
c19d1205 ZW |
3245 | if (skip_past_char (&p, '!') == SUCCESS) |
3246 | inst.operands[i].writeback = 1; | |
09d92015 | 3247 | |
c19d1205 | 3248 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 3249 | { |
c19d1205 ZW |
3250 | if (skip_past_char (&p, '{') == SUCCESS) |
3251 | { | |
3252 | /* [Rn], {expr} - unindexed, with option */ | |
3253 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 3254 | 0, 255, TRUE) == FAIL) |
c19d1205 | 3255 | return FAIL; |
09d92015 | 3256 | |
c19d1205 ZW |
3257 | if (skip_past_char (&p, '}') == FAIL) |
3258 | { | |
3259 | inst.error = _("'}' expected at end of 'option' field"); | |
3260 | return FAIL; | |
3261 | } | |
3262 | if (inst.operands[i].preind) | |
3263 | { | |
3264 | inst.error = _("cannot combine index with option"); | |
3265 | return FAIL; | |
3266 | } | |
3267 | *str = p; | |
3268 | return SUCCESS; | |
09d92015 | 3269 | } |
c19d1205 ZW |
3270 | else |
3271 | { | |
3272 | inst.operands[i].postind = 1; | |
3273 | inst.operands[i].writeback = 1; | |
09d92015 | 3274 | |
c19d1205 ZW |
3275 | if (inst.operands[i].preind) |
3276 | { | |
3277 | inst.error = _("cannot combine pre- and post-indexing"); | |
3278 | return FAIL; | |
3279 | } | |
09d92015 | 3280 | |
c19d1205 ZW |
3281 | if (*p == '+') p++; |
3282 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 3283 | |
c19d1205 ZW |
3284 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
3285 | { | |
3286 | inst.operands[i].imm = reg; | |
3287 | inst.operands[i].immisreg = 1; | |
a737bd4d | 3288 | |
c19d1205 ZW |
3289 | if (skip_past_comma (&p) == SUCCESS) |
3290 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
3291 | return FAIL; | |
3292 | } | |
3293 | else | |
3294 | { | |
3295 | if (inst.operands[i].negative) | |
3296 | { | |
3297 | inst.operands[i].negative = 0; | |
3298 | p--; | |
3299 | } | |
3300 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
3301 | return FAIL; | |
3302 | } | |
3303 | } | |
a737bd4d NC |
3304 | } |
3305 | ||
c19d1205 ZW |
3306 | /* If at this point neither .preind nor .postind is set, we have a |
3307 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
3308 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
3309 | { | |
3310 | inst.operands[i].preind = 1; | |
3311 | inst.reloc.exp.X_op = O_constant; | |
3312 | inst.reloc.exp.X_add_number = 0; | |
3313 | } | |
3314 | *str = p; | |
3315 | return SUCCESS; | |
a737bd4d NC |
3316 | } |
3317 | ||
c19d1205 | 3318 | /* Miscellaneous. */ |
a737bd4d | 3319 | |
c19d1205 ZW |
3320 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
3321 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
3322 | static int | |
3323 | parse_psr (char **str) | |
09d92015 | 3324 | { |
c19d1205 ZW |
3325 | char *p; |
3326 | unsigned long psr_field; | |
09d92015 | 3327 | |
c19d1205 ZW |
3328 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
3329 | feature for ease of use and backwards compatibility. */ | |
3330 | p = *str; | |
3331 | if (*p == 's' || *p == 'S') | |
3332 | psr_field = SPSR_BIT; | |
3333 | else if (*p == 'c' || *p == 'C') | |
3334 | psr_field = 0; | |
3335 | else | |
3336 | goto error; | |
09d92015 | 3337 | |
c19d1205 ZW |
3338 | p++; |
3339 | if (strncasecmp (p, "PSR", 3) != 0) | |
3340 | goto error; | |
3341 | p += 3; | |
09d92015 | 3342 | |
c19d1205 ZW |
3343 | if (*p == '_') |
3344 | { | |
3345 | /* A suffix follows. */ | |
3346 | const struct asm_psr *psr; | |
3347 | char *start; | |
a737bd4d | 3348 | |
c19d1205 ZW |
3349 | p++; |
3350 | start = p; | |
a737bd4d | 3351 | |
c19d1205 ZW |
3352 | do |
3353 | p++; | |
3354 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 3355 | |
c19d1205 ZW |
3356 | psr = hash_find_n (arm_psr_hsh, start, p - start); |
3357 | if (!psr) | |
3358 | goto error; | |
a737bd4d | 3359 | |
c19d1205 | 3360 | psr_field |= psr->field; |
a737bd4d | 3361 | } |
c19d1205 | 3362 | else |
a737bd4d | 3363 | { |
c19d1205 ZW |
3364 | if (ISALNUM (*p)) |
3365 | goto error; /* Garbage after "[CS]PSR". */ | |
3366 | ||
3367 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 3368 | } |
c19d1205 ZW |
3369 | *str = p; |
3370 | return psr_field; | |
a737bd4d | 3371 | |
c19d1205 ZW |
3372 | error: |
3373 | inst.error = _("flag for {c}psr instruction expected"); | |
3374 | return FAIL; | |
a737bd4d NC |
3375 | } |
3376 | ||
c19d1205 ZW |
3377 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
3378 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 3379 | |
c19d1205 ZW |
3380 | static int |
3381 | parse_cps_flags (char **str) | |
a737bd4d | 3382 | { |
c19d1205 ZW |
3383 | int val = 0; |
3384 | int saw_a_flag = 0; | |
3385 | char *s = *str; | |
a737bd4d | 3386 | |
c19d1205 ZW |
3387 | for (;;) |
3388 | switch (*s++) | |
3389 | { | |
3390 | case '\0': case ',': | |
3391 | goto done; | |
a737bd4d | 3392 | |
c19d1205 ZW |
3393 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
3394 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
3395 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 3396 | |
c19d1205 ZW |
3397 | default: |
3398 | inst.error = _("unrecognized CPS flag"); | |
3399 | return FAIL; | |
3400 | } | |
a737bd4d | 3401 | |
c19d1205 ZW |
3402 | done: |
3403 | if (saw_a_flag == 0) | |
a737bd4d | 3404 | { |
c19d1205 ZW |
3405 | inst.error = _("missing CPS flags"); |
3406 | return FAIL; | |
a737bd4d | 3407 | } |
a737bd4d | 3408 | |
c19d1205 ZW |
3409 | *str = s - 1; |
3410 | return val; | |
a737bd4d NC |
3411 | } |
3412 | ||
c19d1205 ZW |
3413 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
3414 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
3415 | |
3416 | static int | |
c19d1205 | 3417 | parse_endian_specifier (char **str) |
a737bd4d | 3418 | { |
c19d1205 ZW |
3419 | int little_endian; |
3420 | char *s = *str; | |
a737bd4d | 3421 | |
c19d1205 ZW |
3422 | if (strncasecmp (s, "BE", 2)) |
3423 | little_endian = 0; | |
3424 | else if (strncasecmp (s, "LE", 2)) | |
3425 | little_endian = 1; | |
3426 | else | |
a737bd4d | 3427 | { |
c19d1205 | 3428 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
3429 | return FAIL; |
3430 | } | |
3431 | ||
c19d1205 | 3432 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 3433 | { |
c19d1205 | 3434 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
3435 | return FAIL; |
3436 | } | |
3437 | ||
c19d1205 ZW |
3438 | *str = s + 2; |
3439 | return little_endian; | |
3440 | } | |
a737bd4d | 3441 | |
c19d1205 ZW |
3442 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
3443 | value suitable for poking into the rotate field of an sxt or sxta | |
3444 | instruction, or FAIL on error. */ | |
3445 | ||
3446 | static int | |
3447 | parse_ror (char **str) | |
3448 | { | |
3449 | int rot; | |
3450 | char *s = *str; | |
3451 | ||
3452 | if (strncasecmp (s, "ROR", 3) == 0) | |
3453 | s += 3; | |
3454 | else | |
a737bd4d | 3455 | { |
c19d1205 | 3456 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
3457 | return FAIL; |
3458 | } | |
c19d1205 ZW |
3459 | |
3460 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
3461 | return FAIL; | |
3462 | ||
3463 | switch (rot) | |
a737bd4d | 3464 | { |
c19d1205 ZW |
3465 | case 0: *str = s; return 0x0; |
3466 | case 8: *str = s; return 0x1; | |
3467 | case 16: *str = s; return 0x2; | |
3468 | case 24: *str = s; return 0x3; | |
3469 | ||
3470 | default: | |
3471 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
3472 | return FAIL; |
3473 | } | |
c19d1205 | 3474 | } |
a737bd4d | 3475 | |
c19d1205 ZW |
3476 | /* Parse a conditional code (from conds[] below). The value returned is in the |
3477 | range 0 .. 14, or FAIL. */ | |
3478 | static int | |
3479 | parse_cond (char **str) | |
3480 | { | |
3481 | char *p, *q; | |
3482 | const struct asm_cond *c; | |
a737bd4d | 3483 | |
c19d1205 ZW |
3484 | p = q = *str; |
3485 | while (ISALPHA (*q)) | |
3486 | q++; | |
a737bd4d | 3487 | |
c19d1205 ZW |
3488 | c = hash_find_n (arm_cond_hsh, p, q - p); |
3489 | if (!c) | |
a737bd4d | 3490 | { |
c19d1205 | 3491 | inst.error = _("condition required"); |
a737bd4d NC |
3492 | return FAIL; |
3493 | } | |
3494 | ||
c19d1205 ZW |
3495 | *str = q; |
3496 | return c->value; | |
3497 | } | |
3498 | ||
92e90b6e PB |
3499 | /* Parse the operands of a table branch instruction. Similar to a memory |
3500 | operand. */ | |
3501 | static int | |
3502 | parse_tb (char **str) | |
3503 | { | |
3504 | char * p = *str; | |
3505 | int reg; | |
3506 | ||
3507 | if (skip_past_char (&p, '[') == FAIL) | |
3508 | return FAIL; | |
3509 | ||
3510 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) | |
3511 | { | |
3512 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
3513 | return FAIL; | |
3514 | } | |
3515 | inst.operands[0].reg = reg; | |
3516 | ||
3517 | if (skip_past_comma (&p) == FAIL) | |
3518 | return FAIL; | |
3519 | ||
3520 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) | |
3521 | { | |
3522 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
3523 | return FAIL; | |
3524 | } | |
3525 | inst.operands[0].imm = reg; | |
3526 | ||
3527 | if (skip_past_comma (&p) == SUCCESS) | |
3528 | { | |
3529 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
3530 | return FAIL; | |
3531 | if (inst.reloc.exp.X_add_number != 1) | |
3532 | { | |
3533 | inst.error = _("invalid shift"); | |
3534 | return FAIL; | |
3535 | } | |
3536 | inst.operands[0].shifted = 1; | |
3537 | } | |
3538 | ||
3539 | if (skip_past_char (&p, ']') == FAIL) | |
3540 | { | |
3541 | inst.error = _("']' expected"); | |
3542 | return FAIL; | |
3543 | } | |
3544 | *str = p; | |
3545 | return SUCCESS; | |
3546 | } | |
3547 | ||
c19d1205 ZW |
3548 | /* Matcher codes for parse_operands. */ |
3549 | enum operand_parse_code | |
3550 | { | |
3551 | OP_stop, /* end of line */ | |
3552 | ||
3553 | OP_RR, /* ARM register */ | |
3554 | OP_RRnpc, /* ARM register, not r15 */ | |
3555 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ | |
3556 | OP_RRw, /* ARM register, not r15, optional trailing ! */ | |
3557 | OP_RCP, /* Coprocessor number */ | |
3558 | OP_RCN, /* Coprocessor register */ | |
3559 | OP_RF, /* FPA register */ | |
3560 | OP_RVS, /* VFP single precision register */ | |
3561 | OP_RVD, /* VFP double precision register */ | |
3562 | OP_RVC, /* VFP control register */ | |
3563 | OP_RMF, /* Maverick F register */ | |
3564 | OP_RMD, /* Maverick D register */ | |
3565 | OP_RMFX, /* Maverick FX register */ | |
3566 | OP_RMDX, /* Maverick DX register */ | |
3567 | OP_RMAX, /* Maverick AX register */ | |
3568 | OP_RMDS, /* Maverick DSPSC register */ | |
3569 | OP_RIWR, /* iWMMXt wR register */ | |
3570 | OP_RIWC, /* iWMMXt wC register */ | |
3571 | OP_RIWG, /* iWMMXt wCG register */ | |
3572 | OP_RXA, /* XScale accumulator register */ | |
3573 | ||
3574 | OP_REGLST, /* ARM register list */ | |
3575 | OP_VRSLST, /* VFP single-precision register list */ | |
3576 | OP_VRDLST, /* VFP double-precision register list */ | |
3577 | ||
3578 | OP_I7, /* immediate value 0 .. 7 */ | |
3579 | OP_I15, /* 0 .. 15 */ | |
3580 | OP_I16, /* 1 .. 16 */ | |
3581 | OP_I31, /* 0 .. 31 */ | |
3582 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
3583 | OP_I32, /* 1 .. 32 */ | |
3584 | OP_I63s, /* -64 .. 63 */ | |
3585 | OP_I255, /* 0 .. 255 */ | |
3586 | OP_Iffff, /* 0 .. 65535 */ | |
3587 | ||
3588 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
3589 | OP_I7b, /* 0 .. 7 */ | |
3590 | OP_I15b, /* 0 .. 15 */ | |
3591 | OP_I31b, /* 0 .. 31 */ | |
3592 | ||
3593 | OP_SH, /* shifter operand */ | |
3594 | OP_ADDR, /* Memory address expression (any mode) */ | |
3595 | OP_EXP, /* arbitrary expression */ | |
3596 | OP_EXPi, /* same, with optional immediate prefix */ | |
3597 | OP_EXPr, /* same, with optional relocation suffix */ | |
3598 | ||
3599 | OP_CPSF, /* CPS flags */ | |
3600 | OP_ENDI, /* Endianness specifier */ | |
3601 | OP_PSR, /* CPSR/SPSR mask for msr */ | |
3602 | OP_COND, /* conditional code */ | |
92e90b6e | 3603 | OP_TB, /* Table branch. */ |
c19d1205 ZW |
3604 | |
3605 | OP_RRnpc_I0, /* ARM register or literal 0 */ | |
3606 | OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ | |
3607 | OP_RR_EXi, /* ARM register or expression with imm prefix */ | |
3608 | OP_RF_IF, /* FPA register or immediate */ | |
3609 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
3610 | ||
3611 | /* Optional operands. */ | |
3612 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
3613 | OP_oI31b, /* 0 .. 31 */ | |
3614 | OP_oIffffb, /* 0 .. 65535 */ | |
3615 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
3616 | ||
3617 | OP_oRR, /* ARM register */ | |
3618 | OP_oRRnpc, /* ARM register, not the PC */ | |
3619 | OP_oSHll, /* LSL immediate */ | |
3620 | OP_oSHar, /* ASR immediate */ | |
3621 | OP_oSHllar, /* LSL or ASR immediate */ | |
3622 | OP_oROR, /* ROR 0/8/16/24 */ | |
3623 | ||
3624 | OP_FIRST_OPTIONAL = OP_oI7b | |
3625 | }; | |
a737bd4d | 3626 | |
c19d1205 ZW |
3627 | /* Generic instruction operand parser. This does no encoding and no |
3628 | semantic validation; it merely squirrels values away in the inst | |
3629 | structure. Returns SUCCESS or FAIL depending on whether the | |
3630 | specified grammar matched. */ | |
3631 | static int | |
ca3f61f7 | 3632 | parse_operands (char *str, const unsigned char *pattern) |
c19d1205 ZW |
3633 | { |
3634 | unsigned const char *upat = pattern; | |
3635 | char *backtrack_pos = 0; | |
3636 | const char *backtrack_error = 0; | |
3637 | int i, val, backtrack_index = 0; | |
3638 | ||
3639 | #define po_char_or_fail(chr) do { \ | |
3640 | if (skip_past_char (&str, chr) == FAIL) \ | |
3641 | goto bad_args; \ | |
3642 | } while (0) | |
3643 | ||
3644 | #define po_reg_or_fail(regtype) do { \ | |
3645 | val = arm_reg_parse (&str, regtype); \ | |
3646 | if (val == FAIL) \ | |
3647 | { \ | |
3648 | inst.error = _(reg_expected_msgs[regtype]); \ | |
3649 | goto failure; \ | |
3650 | } \ | |
3651 | inst.operands[i].reg = val; \ | |
3652 | inst.operands[i].isreg = 1; \ | |
3653 | } while (0) | |
3654 | ||
3655 | #define po_reg_or_goto(regtype, label) do { \ | |
3656 | val = arm_reg_parse (&str, regtype); \ | |
3657 | if (val == FAIL) \ | |
3658 | goto label; \ | |
3659 | \ | |
3660 | inst.operands[i].reg = val; \ | |
3661 | inst.operands[i].isreg = 1; \ | |
3662 | } while (0) | |
3663 | ||
3664 | #define po_imm_or_fail(min, max, popt) do { \ | |
3665 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
3666 | goto failure; \ | |
3667 | inst.operands[i].imm = val; \ | |
3668 | } while (0) | |
3669 | ||
3670 | #define po_misc_or_fail(expr) do { \ | |
3671 | if (expr) \ | |
3672 | goto failure; \ | |
3673 | } while (0) | |
3674 | ||
3675 | skip_whitespace (str); | |
3676 | ||
3677 | for (i = 0; upat[i] != OP_stop; i++) | |
3678 | { | |
3679 | if (upat[i] >= OP_FIRST_OPTIONAL) | |
3680 | { | |
3681 | /* Remember where we are in case we need to backtrack. */ | |
3682 | assert (!backtrack_pos); | |
3683 | backtrack_pos = str; | |
3684 | backtrack_error = inst.error; | |
3685 | backtrack_index = i; | |
3686 | } | |
3687 | ||
3688 | if (i > 0) | |
3689 | po_char_or_fail (','); | |
3690 | ||
3691 | switch (upat[i]) | |
3692 | { | |
3693 | /* Registers */ | |
3694 | case OP_oRRnpc: | |
3695 | case OP_RRnpc: | |
3696 | case OP_oRR: | |
3697 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
3698 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
3699 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
3700 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
3701 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
3702 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
3703 | case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break; | |
3704 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; | |
3705 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
3706 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
3707 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
3708 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
3709 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
3710 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
3711 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
3712 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
3713 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
3714 | ||
3715 | case OP_RRnpcb: | |
3716 | po_char_or_fail ('['); | |
3717 | po_reg_or_fail (REG_TYPE_RN); | |
3718 | po_char_or_fail (']'); | |
3719 | break; | |
a737bd4d | 3720 | |
c19d1205 ZW |
3721 | case OP_RRw: |
3722 | po_reg_or_fail (REG_TYPE_RN); | |
3723 | if (skip_past_char (&str, '!') == SUCCESS) | |
3724 | inst.operands[i].writeback = 1; | |
3725 | break; | |
3726 | ||
3727 | /* Immediates */ | |
3728 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
3729 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
3730 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
3731 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; | |
3732 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
3733 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; | |
3734 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; | |
3735 | case OP_Iffff: po_imm_or_fail ( 0, 0xffff, FALSE); break; | |
3736 | ||
3737 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
3738 | case OP_oI7b: | |
3739 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
3740 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
3741 | case OP_oI31b: | |
3742 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
3743 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; | |
3744 | ||
3745 | /* Immediate variants */ | |
3746 | case OP_oI255c: | |
3747 | po_char_or_fail ('{'); | |
3748 | po_imm_or_fail (0, 255, TRUE); | |
3749 | po_char_or_fail ('}'); | |
3750 | break; | |
3751 | ||
3752 | case OP_I31w: | |
3753 | /* The expression parser chokes on a trailing !, so we have | |
3754 | to find it first and zap it. */ | |
3755 | { | |
3756 | char *s = str; | |
3757 | while (*s && *s != ',') | |
3758 | s++; | |
3759 | if (s[-1] == '!') | |
3760 | { | |
3761 | s[-1] = '\0'; | |
3762 | inst.operands[i].writeback = 1; | |
3763 | } | |
3764 | po_imm_or_fail (0, 31, TRUE); | |
3765 | if (str == s - 1) | |
3766 | str = s; | |
3767 | } | |
3768 | break; | |
3769 | ||
3770 | /* Expressions */ | |
3771 | case OP_EXPi: EXPi: | |
3772 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
3773 | GE_OPT_PREFIX)); | |
3774 | break; | |
3775 | ||
3776 | case OP_EXP: | |
3777 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
3778 | GE_NO_PREFIX)); | |
3779 | break; | |
3780 | ||
3781 | case OP_EXPr: EXPr: | |
3782 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
3783 | GE_NO_PREFIX)); | |
3784 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 3785 | { |
c19d1205 ZW |
3786 | val = parse_reloc (&str); |
3787 | if (val == -1) | |
3788 | { | |
3789 | inst.error = _("unrecognized relocation suffix"); | |
3790 | goto failure; | |
3791 | } | |
3792 | else if (val != BFD_RELOC_UNUSED) | |
3793 | { | |
3794 | inst.operands[i].imm = val; | |
3795 | inst.operands[i].hasreloc = 1; | |
3796 | } | |
a737bd4d | 3797 | } |
c19d1205 | 3798 | break; |
a737bd4d | 3799 | |
c19d1205 ZW |
3800 | /* Register or expression */ |
3801 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; | |
3802 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 3803 | |
c19d1205 ZW |
3804 | /* Register or immediate */ |
3805 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; | |
3806 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 3807 | |
c19d1205 ZW |
3808 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
3809 | IF: | |
3810 | if (!is_immediate_prefix (*str)) | |
3811 | goto bad_args; | |
3812 | str++; | |
3813 | val = parse_fpa_immediate (&str); | |
3814 | if (val == FAIL) | |
3815 | goto failure; | |
3816 | /* FPA immediates are encoded as registers 8-15. | |
3817 | parse_fpa_immediate has already applied the offset. */ | |
3818 | inst.operands[i].reg = val; | |
3819 | inst.operands[i].isreg = 1; | |
3820 | break; | |
09d92015 | 3821 | |
c19d1205 ZW |
3822 | /* Two kinds of register */ |
3823 | case OP_RIWR_RIWC: | |
3824 | { | |
3825 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
3826 | if (rege->type != REG_TYPE_MMXWR | |
3827 | && rege->type != REG_TYPE_MMXWC | |
3828 | && rege->type != REG_TYPE_MMXWCG) | |
3829 | { | |
3830 | inst.error = _("iWMMXt data or control register expected"); | |
3831 | goto failure; | |
3832 | } | |
3833 | inst.operands[i].reg = rege->number; | |
3834 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
3835 | } | |
3836 | break; | |
09d92015 | 3837 | |
c19d1205 ZW |
3838 | /* Misc */ |
3839 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
3840 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
3841 | case OP_oROR: val = parse_ror (&str); break; | |
3842 | case OP_PSR: val = parse_psr (&str); break; | |
3843 | case OP_COND: val = parse_cond (&str); break; | |
3844 | ||
92e90b6e PB |
3845 | case OP_TB: |
3846 | po_misc_or_fail (parse_tb (&str)); | |
3847 | break; | |
3848 | ||
c19d1205 ZW |
3849 | /* Register lists */ |
3850 | case OP_REGLST: | |
3851 | val = parse_reg_list (&str); | |
3852 | if (*str == '^') | |
3853 | { | |
3854 | inst.operands[1].writeback = 1; | |
3855 | str++; | |
3856 | } | |
3857 | break; | |
09d92015 | 3858 | |
c19d1205 ZW |
3859 | case OP_VRSLST: |
3860 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 0); | |
3861 | break; | |
09d92015 | 3862 | |
c19d1205 ZW |
3863 | case OP_VRDLST: |
3864 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 1); | |
3865 | break; | |
a737bd4d | 3866 | |
c19d1205 ZW |
3867 | /* Addressing modes */ |
3868 | case OP_ADDR: | |
3869 | po_misc_or_fail (parse_address (&str, i)); | |
3870 | break; | |
09d92015 | 3871 | |
c19d1205 ZW |
3872 | case OP_SH: |
3873 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
3874 | break; | |
09d92015 | 3875 | |
c19d1205 ZW |
3876 | case OP_oSHll: |
3877 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
3878 | break; | |
09d92015 | 3879 | |
c19d1205 ZW |
3880 | case OP_oSHar: |
3881 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
3882 | break; | |
09d92015 | 3883 | |
c19d1205 ZW |
3884 | case OP_oSHllar: |
3885 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
3886 | break; | |
09d92015 | 3887 | |
c19d1205 ZW |
3888 | default: |
3889 | as_fatal ("unhandled operand code %d", upat[i]); | |
3890 | } | |
09d92015 | 3891 | |
c19d1205 ZW |
3892 | /* Various value-based sanity checks and shared operations. We |
3893 | do not signal immediate failures for the register constraints; | |
3894 | this allows a syntax error to take precedence. */ | |
3895 | switch (upat[i]) | |
3896 | { | |
3897 | case OP_oRRnpc: | |
3898 | case OP_RRnpc: | |
3899 | case OP_RRnpcb: | |
3900 | case OP_RRw: | |
3901 | case OP_RRnpc_I0: | |
3902 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
3903 | inst.error = BAD_PC; | |
3904 | break; | |
09d92015 | 3905 | |
c19d1205 ZW |
3906 | case OP_CPSF: |
3907 | case OP_ENDI: | |
3908 | case OP_oROR: | |
3909 | case OP_PSR: | |
3910 | case OP_COND: | |
3911 | case OP_REGLST: | |
3912 | case OP_VRSLST: | |
3913 | case OP_VRDLST: | |
3914 | if (val == FAIL) | |
3915 | goto failure; | |
3916 | inst.operands[i].imm = val; | |
3917 | break; | |
a737bd4d | 3918 | |
c19d1205 ZW |
3919 | default: |
3920 | break; | |
3921 | } | |
09d92015 | 3922 | |
c19d1205 ZW |
3923 | /* If we get here, this operand was successfully parsed. */ |
3924 | inst.operands[i].present = 1; | |
3925 | continue; | |
09d92015 | 3926 | |
c19d1205 | 3927 | bad_args: |
09d92015 | 3928 | inst.error = BAD_ARGS; |
c19d1205 ZW |
3929 | |
3930 | failure: | |
3931 | if (!backtrack_pos) | |
3932 | return FAIL; | |
3933 | ||
3934 | /* Do not backtrack over a trailing optional argument that | |
3935 | absorbed some text. We will only fail again, with the | |
3936 | 'garbage following instruction' error message, which is | |
3937 | probably less helpful than the current one. */ | |
3938 | if (backtrack_index == i && backtrack_pos != str | |
3939 | && upat[i+1] == OP_stop) | |
3940 | return FAIL; | |
3941 | ||
3942 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
3943 | str = backtrack_pos; | |
3944 | inst.error = backtrack_error; | |
3945 | inst.operands[backtrack_index].present = 0; | |
3946 | i = backtrack_index; | |
3947 | backtrack_pos = 0; | |
09d92015 | 3948 | } |
09d92015 | 3949 | |
c19d1205 ZW |
3950 | /* Check that we have parsed all the arguments. */ |
3951 | if (*str != '\0' && !inst.error) | |
3952 | inst.error = _("garbage following instruction"); | |
09d92015 | 3953 | |
c19d1205 | 3954 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
3955 | } |
3956 | ||
c19d1205 ZW |
3957 | #undef po_char_or_fail |
3958 | #undef po_reg_or_fail | |
3959 | #undef po_reg_or_goto | |
3960 | #undef po_imm_or_fail | |
3961 | \f | |
3962 | /* Shorthand macro for instruction encoding functions issuing errors. */ | |
3963 | #define constraint(expr, err) do { \ | |
3964 | if (expr) \ | |
3965 | { \ | |
3966 | inst.error = err; \ | |
3967 | return; \ | |
3968 | } \ | |
3969 | } while (0) | |
3970 | ||
3971 | /* Functions for operand encoding. ARM, then Thumb. */ | |
3972 | ||
3973 | #define rotate_left(v, n) (v << n | v >> (32 - n)) | |
3974 | ||
3975 | /* If VAL can be encoded in the immediate field of an ARM instruction, | |
3976 | return the encoded form. Otherwise, return FAIL. */ | |
3977 | ||
3978 | static unsigned int | |
3979 | encode_arm_immediate (unsigned int val) | |
09d92015 | 3980 | { |
c19d1205 ZW |
3981 | unsigned int a, i; |
3982 | ||
3983 | for (i = 0; i < 32; i += 2) | |
3984 | if ((a = rotate_left (val, i)) <= 0xff) | |
3985 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
3986 | ||
3987 | return FAIL; | |
09d92015 MM |
3988 | } |
3989 | ||
c19d1205 ZW |
3990 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
3991 | return the encoded form. Otherwise, return FAIL. */ | |
3992 | static unsigned int | |
3993 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 3994 | { |
c19d1205 | 3995 | unsigned int a, i; |
09d92015 | 3996 | |
9c3c69f2 | 3997 | if (val <= 0xff) |
c19d1205 | 3998 | return val; |
a737bd4d | 3999 | |
9c3c69f2 | 4000 | for (i = 1; i <= 24; i++) |
09d92015 | 4001 | { |
9c3c69f2 PB |
4002 | a = val >> i; |
4003 | if ((val & ~(0xff << i)) == 0) | |
4004 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 4005 | } |
a737bd4d | 4006 | |
c19d1205 ZW |
4007 | a = val & 0xff; |
4008 | if (val == ((a << 16) | a)) | |
4009 | return 0x100 | a; | |
4010 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
4011 | return 0x300 | a; | |
09d92015 | 4012 | |
c19d1205 ZW |
4013 | a = val & 0xff00; |
4014 | if (val == ((a << 16) | a)) | |
4015 | return 0x200 | (a >> 8); | |
a737bd4d | 4016 | |
c19d1205 | 4017 | return FAIL; |
09d92015 | 4018 | } |
c19d1205 | 4019 | /* Encode a VFP SP register number into inst.instruction. */ |
09d92015 MM |
4020 | |
4021 | static void | |
c19d1205 | 4022 | encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos) |
09d92015 | 4023 | { |
c19d1205 | 4024 | switch (pos) |
09d92015 | 4025 | { |
c19d1205 ZW |
4026 | case VFP_REG_Sd: |
4027 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
4028 | break; | |
4029 | ||
4030 | case VFP_REG_Sn: | |
4031 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
4032 | break; | |
4033 | ||
4034 | case VFP_REG_Sm: | |
4035 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
4036 | break; | |
4037 | ||
4038 | default: | |
4039 | abort (); | |
09d92015 | 4040 | } |
09d92015 MM |
4041 | } |
4042 | ||
c19d1205 | 4043 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 4044 | if any, is handled by md_apply_fix. */ |
09d92015 | 4045 | static void |
c19d1205 | 4046 | encode_arm_shift (int i) |
09d92015 | 4047 | { |
c19d1205 ZW |
4048 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
4049 | inst.instruction |= SHIFT_ROR << 5; | |
4050 | else | |
09d92015 | 4051 | { |
c19d1205 ZW |
4052 | inst.instruction |= inst.operands[i].shift_kind << 5; |
4053 | if (inst.operands[i].immisreg) | |
4054 | { | |
4055 | inst.instruction |= SHIFT_BY_REG; | |
4056 | inst.instruction |= inst.operands[i].imm << 8; | |
4057 | } | |
4058 | else | |
4059 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 4060 | } |
c19d1205 | 4061 | } |
09d92015 | 4062 | |
c19d1205 ZW |
4063 | static void |
4064 | encode_arm_shifter_operand (int i) | |
4065 | { | |
4066 | if (inst.operands[i].isreg) | |
09d92015 | 4067 | { |
c19d1205 ZW |
4068 | inst.instruction |= inst.operands[i].reg; |
4069 | encode_arm_shift (i); | |
09d92015 | 4070 | } |
c19d1205 ZW |
4071 | else |
4072 | inst.instruction |= INST_IMMEDIATE; | |
09d92015 MM |
4073 | } |
4074 | ||
c19d1205 | 4075 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 4076 | static void |
c19d1205 | 4077 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 4078 | { |
c19d1205 ZW |
4079 | assert (inst.operands[i].isreg); |
4080 | inst.instruction |= inst.operands[i].reg << 16; | |
a737bd4d | 4081 | |
c19d1205 | 4082 | if (inst.operands[i].preind) |
09d92015 | 4083 | { |
c19d1205 ZW |
4084 | if (is_t) |
4085 | { | |
4086 | inst.error = _("instruction does not accept preindexed addressing"); | |
4087 | return; | |
4088 | } | |
4089 | inst.instruction |= PRE_INDEX; | |
4090 | if (inst.operands[i].writeback) | |
4091 | inst.instruction |= WRITE_BACK; | |
09d92015 | 4092 | |
c19d1205 ZW |
4093 | } |
4094 | else if (inst.operands[i].postind) | |
4095 | { | |
4096 | assert (inst.operands[i].writeback); | |
4097 | if (is_t) | |
4098 | inst.instruction |= WRITE_BACK; | |
4099 | } | |
4100 | else /* unindexed - only for coprocessor */ | |
09d92015 | 4101 | { |
c19d1205 | 4102 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
4103 | return; |
4104 | } | |
4105 | ||
c19d1205 ZW |
4106 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
4107 | && (((inst.instruction & 0x000f0000) >> 16) | |
4108 | == ((inst.instruction & 0x0000f000) >> 12))) | |
4109 | as_warn ((inst.instruction & LOAD_BIT) | |
4110 | ? _("destination register same as write-back base") | |
4111 | : _("source register same as write-back base")); | |
09d92015 MM |
4112 | } |
4113 | ||
c19d1205 ZW |
4114 | /* inst.operands[i] was set up by parse_address. Encode it into an |
4115 | ARM-format mode 2 load or store instruction. If is_t is true, | |
4116 | reject forms that cannot be used with a T instruction (i.e. not | |
4117 | post-indexed). */ | |
a737bd4d | 4118 | static void |
c19d1205 | 4119 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 4120 | { |
c19d1205 | 4121 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 4122 | |
c19d1205 | 4123 | if (inst.operands[i].immisreg) |
09d92015 | 4124 | { |
c19d1205 ZW |
4125 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
4126 | inst.instruction |= inst.operands[i].imm; | |
4127 | if (!inst.operands[i].negative) | |
4128 | inst.instruction |= INDEX_UP; | |
4129 | if (inst.operands[i].shifted) | |
4130 | { | |
4131 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
4132 | inst.instruction |= SHIFT_ROR << 5; | |
4133 | else | |
4134 | { | |
4135 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
4136 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
4137 | } | |
4138 | } | |
09d92015 | 4139 | } |
c19d1205 | 4140 | else /* immediate offset in inst.reloc */ |
09d92015 | 4141 | { |
c19d1205 ZW |
4142 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
4143 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
09d92015 | 4144 | } |
09d92015 MM |
4145 | } |
4146 | ||
c19d1205 ZW |
4147 | /* inst.operands[i] was set up by parse_address. Encode it into an |
4148 | ARM-format mode 3 load or store instruction. Reject forms that | |
4149 | cannot be used with such instructions. If is_t is true, reject | |
4150 | forms that cannot be used with a T instruction (i.e. not | |
4151 | post-indexed). */ | |
4152 | static void | |
4153 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 4154 | { |
c19d1205 | 4155 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 4156 | { |
c19d1205 ZW |
4157 | inst.error = _("instruction does not accept scaled register index"); |
4158 | return; | |
09d92015 | 4159 | } |
a737bd4d | 4160 | |
c19d1205 | 4161 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 4162 | |
c19d1205 ZW |
4163 | if (inst.operands[i].immisreg) |
4164 | { | |
4165 | inst.instruction |= inst.operands[i].imm; | |
4166 | if (!inst.operands[i].negative) | |
4167 | inst.instruction |= INDEX_UP; | |
4168 | } | |
4169 | else /* immediate offset in inst.reloc */ | |
4170 | { | |
4171 | inst.instruction |= HWOFFSET_IMM; | |
4172 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
4173 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
c19d1205 | 4174 | } |
a737bd4d NC |
4175 | } |
4176 | ||
c19d1205 ZW |
4177 | /* inst.operands[i] was set up by parse_address. Encode it into an |
4178 | ARM-format instruction. Reject all forms which cannot be encoded | |
4179 | into a coprocessor load/store instruction. If wb_ok is false, | |
4180 | reject use of writeback; if unind_ok is false, reject use of | |
4181 | unindexed addressing. If reloc_override is not 0, use it instead | |
4182 | of BFD_ARM_CP_OFF_IMM. */ | |
09d92015 | 4183 | |
c19d1205 ZW |
4184 | static int |
4185 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
09d92015 | 4186 | { |
c19d1205 | 4187 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 4188 | |
c19d1205 | 4189 | assert (!(inst.operands[i].preind && inst.operands[i].postind)); |
09d92015 | 4190 | |
c19d1205 | 4191 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ |
09d92015 | 4192 | { |
c19d1205 ZW |
4193 | assert (!inst.operands[i].writeback); |
4194 | if (!unind_ok) | |
4195 | { | |
4196 | inst.error = _("instruction does not support unindexed addressing"); | |
4197 | return FAIL; | |
4198 | } | |
4199 | inst.instruction |= inst.operands[i].imm; | |
4200 | inst.instruction |= INDEX_UP; | |
4201 | return SUCCESS; | |
09d92015 | 4202 | } |
a737bd4d | 4203 | |
c19d1205 ZW |
4204 | if (inst.operands[i].preind) |
4205 | inst.instruction |= PRE_INDEX; | |
a737bd4d | 4206 | |
c19d1205 | 4207 | if (inst.operands[i].writeback) |
09d92015 | 4208 | { |
c19d1205 ZW |
4209 | if (inst.operands[i].reg == REG_PC) |
4210 | { | |
4211 | inst.error = _("pc may not be used with write-back"); | |
4212 | return FAIL; | |
4213 | } | |
4214 | if (!wb_ok) | |
4215 | { | |
4216 | inst.error = _("instruction does not support writeback"); | |
4217 | return FAIL; | |
4218 | } | |
4219 | inst.instruction |= WRITE_BACK; | |
09d92015 | 4220 | } |
a737bd4d | 4221 | |
c19d1205 ZW |
4222 | if (reloc_override) |
4223 | inst.reloc.type = reloc_override; | |
8f06b2d8 PB |
4224 | else if (thumb_mode) |
4225 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
09d92015 | 4226 | else |
c19d1205 | 4227 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; |
c19d1205 ZW |
4228 | return SUCCESS; |
4229 | } | |
a737bd4d | 4230 | |
c19d1205 ZW |
4231 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
4232 | Determine whether it can be performed with a move instruction; if | |
4233 | it can, convert inst.instruction to that move instruction and | |
4234 | return 1; if it can't, convert inst.instruction to a literal-pool | |
4235 | load and return 0. If this is not a valid thing to do in the | |
4236 | current context, set inst.error and return 1. | |
a737bd4d | 4237 | |
c19d1205 ZW |
4238 | inst.operands[i] describes the destination register. */ |
4239 | ||
4240 | static int | |
4241 | move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) | |
4242 | { | |
4243 | if ((inst.instruction & (thumb_p ? THUMB_LOAD_BIT : LOAD_BIT)) == 0) | |
09d92015 | 4244 | { |
c19d1205 ZW |
4245 | inst.error = _("invalid pseudo operation"); |
4246 | return 1; | |
09d92015 | 4247 | } |
c19d1205 | 4248 | if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) |
09d92015 MM |
4249 | { |
4250 | inst.error = _("constant expression expected"); | |
c19d1205 | 4251 | return 1; |
09d92015 | 4252 | } |
c19d1205 | 4253 | if (inst.reloc.exp.X_op == O_constant) |
09d92015 | 4254 | { |
c19d1205 ZW |
4255 | if (thumb_p) |
4256 | { | |
4257 | if ((inst.reloc.exp.X_add_number & ~0xFF) == 0) | |
4258 | { | |
4259 | /* This can be done with a mov(1) instruction. */ | |
4260 | inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); | |
4261 | inst.instruction |= inst.reloc.exp.X_add_number; | |
4262 | return 1; | |
4263 | } | |
4264 | } | |
4265 | else | |
4266 | { | |
4267 | int value = encode_arm_immediate (inst.reloc.exp.X_add_number); | |
4268 | if (value != FAIL) | |
4269 | { | |
4270 | /* This can be done with a mov instruction. */ | |
4271 | inst.instruction &= LITERAL_MASK; | |
4272 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
4273 | inst.instruction |= value & 0xfff; | |
4274 | return 1; | |
4275 | } | |
09d92015 | 4276 | |
c19d1205 ZW |
4277 | value = encode_arm_immediate (~inst.reloc.exp.X_add_number); |
4278 | if (value != FAIL) | |
4279 | { | |
4280 | /* This can be done with a mvn instruction. */ | |
4281 | inst.instruction &= LITERAL_MASK; | |
4282 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
4283 | inst.instruction |= value & 0xfff; | |
4284 | return 1; | |
4285 | } | |
4286 | } | |
09d92015 MM |
4287 | } |
4288 | ||
c19d1205 ZW |
4289 | if (add_to_lit_pool () == FAIL) |
4290 | { | |
4291 | inst.error = _("literal pool insertion failed"); | |
4292 | return 1; | |
4293 | } | |
4294 | inst.operands[1].reg = REG_PC; | |
4295 | inst.operands[1].isreg = 1; | |
4296 | inst.operands[1].preind = 1; | |
4297 | inst.reloc.pc_rel = 1; | |
4298 | inst.reloc.type = (thumb_p | |
4299 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
4300 | : (mode_3 | |
4301 | ? BFD_RELOC_ARM_HWLITERAL | |
4302 | : BFD_RELOC_ARM_LITERAL)); | |
4303 | return 0; | |
09d92015 MM |
4304 | } |
4305 | ||
c19d1205 ZW |
4306 | /* Functions for instruction encoding, sorted by subarchitecture. |
4307 | First some generics; their names are taken from the conventional | |
4308 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 4309 | |
a737bd4d | 4310 | static void |
c19d1205 | 4311 | do_noargs (void) |
09d92015 | 4312 | { |
c19d1205 | 4313 | } |
a737bd4d | 4314 | |
c19d1205 ZW |
4315 | static void |
4316 | do_rd (void) | |
4317 | { | |
4318 | inst.instruction |= inst.operands[0].reg << 12; | |
4319 | } | |
a737bd4d | 4320 | |
c19d1205 ZW |
4321 | static void |
4322 | do_rd_rm (void) | |
4323 | { | |
4324 | inst.instruction |= inst.operands[0].reg << 12; | |
4325 | inst.instruction |= inst.operands[1].reg; | |
4326 | } | |
09d92015 | 4327 | |
c19d1205 ZW |
4328 | static void |
4329 | do_rd_rn (void) | |
4330 | { | |
4331 | inst.instruction |= inst.operands[0].reg << 12; | |
4332 | inst.instruction |= inst.operands[1].reg << 16; | |
4333 | } | |
a737bd4d | 4334 | |
c19d1205 ZW |
4335 | static void |
4336 | do_rn_rd (void) | |
4337 | { | |
4338 | inst.instruction |= inst.operands[0].reg << 16; | |
4339 | inst.instruction |= inst.operands[1].reg << 12; | |
4340 | } | |
09d92015 | 4341 | |
c19d1205 ZW |
4342 | static void |
4343 | do_rd_rm_rn (void) | |
4344 | { | |
9a64e435 PB |
4345 | unsigned Rn = inst.operands[2].reg; |
4346 | /* Enforce resutrictions on SWP instruction. */ | |
4347 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) | |
4348 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
4349 | _("Rn must not overlap other operands")); | |
c19d1205 ZW |
4350 | inst.instruction |= inst.operands[0].reg << 12; |
4351 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 4352 | inst.instruction |= Rn << 16; |
c19d1205 | 4353 | } |
09d92015 | 4354 | |
c19d1205 ZW |
4355 | static void |
4356 | do_rd_rn_rm (void) | |
4357 | { | |
4358 | inst.instruction |= inst.operands[0].reg << 12; | |
4359 | inst.instruction |= inst.operands[1].reg << 16; | |
4360 | inst.instruction |= inst.operands[2].reg; | |
4361 | } | |
a737bd4d | 4362 | |
c19d1205 ZW |
4363 | static void |
4364 | do_rm_rd_rn (void) | |
4365 | { | |
4366 | inst.instruction |= inst.operands[0].reg; | |
4367 | inst.instruction |= inst.operands[1].reg << 12; | |
4368 | inst.instruction |= inst.operands[2].reg << 16; | |
4369 | } | |
09d92015 | 4370 | |
c19d1205 ZW |
4371 | static void |
4372 | do_imm0 (void) | |
4373 | { | |
4374 | inst.instruction |= inst.operands[0].imm; | |
4375 | } | |
09d92015 | 4376 | |
c19d1205 ZW |
4377 | static void |
4378 | do_rd_cpaddr (void) | |
4379 | { | |
4380 | inst.instruction |= inst.operands[0].reg << 12; | |
4381 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 4382 | } |
a737bd4d | 4383 | |
c19d1205 ZW |
4384 | /* ARM instructions, in alphabetical order by function name (except |
4385 | that wrapper functions appear immediately after the function they | |
4386 | wrap). */ | |
09d92015 | 4387 | |
c19d1205 ZW |
4388 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
4389 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
4390 | |
4391 | static void | |
c19d1205 | 4392 | do_adr (void) |
09d92015 | 4393 | { |
c19d1205 | 4394 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 4395 | |
c19d1205 ZW |
4396 | /* Frag hacking will turn this into a sub instruction if the offset turns |
4397 | out to be negative. */ | |
4398 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 4399 | inst.reloc.pc_rel = 1; |
2fc8bdac | 4400 | inst.reloc.exp.X_add_number -= 8; |
c19d1205 | 4401 | } |
b99bd4ef | 4402 | |
c19d1205 ZW |
4403 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
4404 | into a relative address of the form: | |
4405 | add rd, pc, #low(label-.-8)" | |
4406 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 4407 | |
c19d1205 ZW |
4408 | static void |
4409 | do_adrl (void) | |
4410 | { | |
4411 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 4412 | |
c19d1205 ZW |
4413 | /* Frag hacking will turn this into a sub instruction if the offset turns |
4414 | out to be negative. */ | |
4415 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
4416 | inst.reloc.pc_rel = 1; |
4417 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 4418 | inst.reloc.exp.X_add_number -= 8; |
b99bd4ef NC |
4419 | } |
4420 | ||
b99bd4ef | 4421 | static void |
c19d1205 | 4422 | do_arit (void) |
b99bd4ef | 4423 | { |
c19d1205 ZW |
4424 | if (!inst.operands[1].present) |
4425 | inst.operands[1].reg = inst.operands[0].reg; | |
4426 | inst.instruction |= inst.operands[0].reg << 12; | |
4427 | inst.instruction |= inst.operands[1].reg << 16; | |
4428 | encode_arm_shifter_operand (2); | |
4429 | } | |
b99bd4ef | 4430 | |
c19d1205 ZW |
4431 | static void |
4432 | do_bfc (void) | |
4433 | { | |
4434 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
4435 | constraint (msb > 32, _("bit-field extends past end of register")); | |
4436 | /* The instruction encoding stores the LSB and MSB, | |
4437 | not the LSB and width. */ | |
4438 | inst.instruction |= inst.operands[0].reg << 12; | |
4439 | inst.instruction |= inst.operands[1].imm << 7; | |
4440 | inst.instruction |= (msb - 1) << 16; | |
4441 | } | |
b99bd4ef | 4442 | |
c19d1205 ZW |
4443 | static void |
4444 | do_bfi (void) | |
4445 | { | |
4446 | unsigned int msb; | |
b99bd4ef | 4447 | |
c19d1205 ZW |
4448 | /* #0 in second position is alternative syntax for bfc, which is |
4449 | the same instruction but with REG_PC in the Rm field. */ | |
4450 | if (!inst.operands[1].isreg) | |
4451 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 4452 | |
c19d1205 ZW |
4453 | msb = inst.operands[2].imm + inst.operands[3].imm; |
4454 | constraint (msb > 32, _("bit-field extends past end of register")); | |
4455 | /* The instruction encoding stores the LSB and MSB, | |
4456 | not the LSB and width. */ | |
4457 | inst.instruction |= inst.operands[0].reg << 12; | |
4458 | inst.instruction |= inst.operands[1].reg; | |
4459 | inst.instruction |= inst.operands[2].imm << 7; | |
4460 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
4461 | } |
4462 | ||
b99bd4ef | 4463 | static void |
c19d1205 | 4464 | do_bfx (void) |
b99bd4ef | 4465 | { |
c19d1205 ZW |
4466 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
4467 | _("bit-field extends past end of register")); | |
4468 | inst.instruction |= inst.operands[0].reg << 12; | |
4469 | inst.instruction |= inst.operands[1].reg; | |
4470 | inst.instruction |= inst.operands[2].imm << 7; | |
4471 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
4472 | } | |
09d92015 | 4473 | |
c19d1205 ZW |
4474 | /* ARM V5 breakpoint instruction (argument parse) |
4475 | BKPT <16 bit unsigned immediate> | |
4476 | Instruction is not conditional. | |
4477 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
4478 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 4479 | |
c19d1205 ZW |
4480 | static void |
4481 | do_bkpt (void) | |
4482 | { | |
4483 | /* Top 12 of 16 bits to bits 19:8. */ | |
4484 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 4485 | |
c19d1205 ZW |
4486 | /* Bottom 4 of 16 bits to bits 3:0. */ |
4487 | inst.instruction |= inst.operands[0].imm & 0xf; | |
4488 | } | |
09d92015 | 4489 | |
c19d1205 ZW |
4490 | static void |
4491 | encode_branch (int default_reloc) | |
4492 | { | |
4493 | if (inst.operands[0].hasreloc) | |
4494 | { | |
4495 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32, | |
4496 | _("the only suffix valid here is '(plt)'")); | |
4497 | inst.reloc.type = BFD_RELOC_ARM_PLT32; | |
c19d1205 | 4498 | } |
b99bd4ef | 4499 | else |
c19d1205 ZW |
4500 | { |
4501 | inst.reloc.type = default_reloc; | |
c19d1205 | 4502 | } |
2fc8bdac | 4503 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
4504 | } |
4505 | ||
b99bd4ef | 4506 | static void |
c19d1205 | 4507 | do_branch (void) |
b99bd4ef | 4508 | { |
c19d1205 ZW |
4509 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); |
4510 | } | |
b99bd4ef | 4511 | |
c19d1205 ZW |
4512 | /* ARM V5 branch-link-exchange instruction (argument parse) |
4513 | BLX <target_addr> ie BLX(1) | |
4514 | BLX{<condition>} <Rm> ie BLX(2) | |
4515 | Unfortunately, there are two different opcodes for this mnemonic. | |
4516 | So, the insns[].value is not used, and the code here zaps values | |
4517 | into inst.instruction. | |
4518 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 4519 | |
c19d1205 ZW |
4520 | static void |
4521 | do_blx (void) | |
4522 | { | |
4523 | if (inst.operands[0].isreg) | |
b99bd4ef | 4524 | { |
c19d1205 ZW |
4525 | /* Arg is a register; the opcode provided by insns[] is correct. |
4526 | It is not illegal to do "blx pc", just useless. */ | |
4527 | if (inst.operands[0].reg == REG_PC) | |
4528 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 4529 | |
c19d1205 ZW |
4530 | inst.instruction |= inst.operands[0].reg; |
4531 | } | |
4532 | else | |
b99bd4ef | 4533 | { |
c19d1205 ZW |
4534 | /* Arg is an address; this instruction cannot be executed |
4535 | conditionally, and the opcode must be adjusted. */ | |
4536 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
2fc8bdac | 4537 | inst.instruction = 0xfa000000; |
c19d1205 | 4538 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
b99bd4ef | 4539 | } |
c19d1205 ZW |
4540 | } |
4541 | ||
4542 | static void | |
4543 | do_bx (void) | |
4544 | { | |
4545 | if (inst.operands[0].reg == REG_PC) | |
4546 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 4547 | |
c19d1205 | 4548 | inst.instruction |= inst.operands[0].reg; |
09d92015 MM |
4549 | } |
4550 | ||
c19d1205 ZW |
4551 | |
4552 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
4553 | |
4554 | static void | |
c19d1205 | 4555 | do_bxj (void) |
a737bd4d | 4556 | { |
c19d1205 ZW |
4557 | if (inst.operands[0].reg == REG_PC) |
4558 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
4559 | ||
4560 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
4561 | } |
4562 | ||
c19d1205 ZW |
4563 | /* Co-processor data operation: |
4564 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
4565 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
4566 | static void | |
4567 | do_cdp (void) | |
4568 | { | |
4569 | inst.instruction |= inst.operands[0].reg << 8; | |
4570 | inst.instruction |= inst.operands[1].imm << 20; | |
4571 | inst.instruction |= inst.operands[2].reg << 12; | |
4572 | inst.instruction |= inst.operands[3].reg << 16; | |
4573 | inst.instruction |= inst.operands[4].reg; | |
4574 | inst.instruction |= inst.operands[5].imm << 5; | |
4575 | } | |
a737bd4d NC |
4576 | |
4577 | static void | |
c19d1205 | 4578 | do_cmp (void) |
a737bd4d | 4579 | { |
c19d1205 ZW |
4580 | inst.instruction |= inst.operands[0].reg << 16; |
4581 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
4582 | } |
4583 | ||
c19d1205 ZW |
4584 | /* Transfer between coprocessor and ARM registers. |
4585 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
4586 | MRC2 | |
4587 | MCR{cond} | |
4588 | MCR2 | |
4589 | ||
4590 | No special properties. */ | |
09d92015 MM |
4591 | |
4592 | static void | |
c19d1205 | 4593 | do_co_reg (void) |
09d92015 | 4594 | { |
c19d1205 ZW |
4595 | inst.instruction |= inst.operands[0].reg << 8; |
4596 | inst.instruction |= inst.operands[1].imm << 21; | |
4597 | inst.instruction |= inst.operands[2].reg << 12; | |
4598 | inst.instruction |= inst.operands[3].reg << 16; | |
4599 | inst.instruction |= inst.operands[4].reg; | |
4600 | inst.instruction |= inst.operands[5].imm << 5; | |
4601 | } | |
09d92015 | 4602 | |
c19d1205 ZW |
4603 | /* Transfer between coprocessor register and pair of ARM registers. |
4604 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
4605 | MCRR2 | |
4606 | MRRC{cond} | |
4607 | MRRC2 | |
b99bd4ef | 4608 | |
c19d1205 | 4609 | Two XScale instructions are special cases of these: |
09d92015 | 4610 | |
c19d1205 ZW |
4611 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
4612 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 4613 | |
c19d1205 | 4614 | Result unpredicatable if Rd or Rn is R15. */ |
a737bd4d | 4615 | |
c19d1205 ZW |
4616 | static void |
4617 | do_co_reg2c (void) | |
4618 | { | |
4619 | inst.instruction |= inst.operands[0].reg << 8; | |
4620 | inst.instruction |= inst.operands[1].imm << 4; | |
4621 | inst.instruction |= inst.operands[2].reg << 12; | |
4622 | inst.instruction |= inst.operands[3].reg << 16; | |
4623 | inst.instruction |= inst.operands[4].reg; | |
b99bd4ef NC |
4624 | } |
4625 | ||
c19d1205 ZW |
4626 | static void |
4627 | do_cpsi (void) | |
4628 | { | |
4629 | inst.instruction |= inst.operands[0].imm << 6; | |
4630 | inst.instruction |= inst.operands[1].imm; | |
4631 | } | |
b99bd4ef NC |
4632 | |
4633 | static void | |
c19d1205 | 4634 | do_it (void) |
b99bd4ef | 4635 | { |
c19d1205 ZW |
4636 | /* There is no IT instruction in ARM mode. We |
4637 | process it but do not generate code for it. */ | |
4638 | inst.size = 0; | |
09d92015 | 4639 | } |
b99bd4ef | 4640 | |
09d92015 | 4641 | static void |
c19d1205 | 4642 | do_ldmstm (void) |
ea6ef066 | 4643 | { |
c19d1205 ZW |
4644 | int base_reg = inst.operands[0].reg; |
4645 | int range = inst.operands[1].imm; | |
ea6ef066 | 4646 | |
c19d1205 ZW |
4647 | inst.instruction |= base_reg << 16; |
4648 | inst.instruction |= range; | |
ea6ef066 | 4649 | |
c19d1205 ZW |
4650 | if (inst.operands[1].writeback) |
4651 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 4652 | |
c19d1205 | 4653 | if (inst.operands[0].writeback) |
ea6ef066 | 4654 | { |
c19d1205 ZW |
4655 | inst.instruction |= WRITE_BACK; |
4656 | /* Check for unpredictable uses of writeback. */ | |
4657 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 4658 | { |
c19d1205 ZW |
4659 | /* Not allowed in LDM type 2. */ |
4660 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
4661 | && ((range & (1 << REG_PC)) == 0)) | |
4662 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
4663 | /* Only allowed if base reg not in list for other types. */ | |
4664 | else if (range & (1 << base_reg)) | |
4665 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
4666 | } | |
4667 | else /* STM. */ | |
4668 | { | |
4669 | /* Not allowed for type 2. */ | |
4670 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
4671 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
4672 | /* Only allowed if base reg not in list, or first in list. */ | |
4673 | else if ((range & (1 << base_reg)) | |
4674 | && (range & ((1 << base_reg) - 1))) | |
4675 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 4676 | } |
ea6ef066 | 4677 | } |
a737bd4d NC |
4678 | } |
4679 | ||
c19d1205 ZW |
4680 | /* ARMv5TE load-consecutive (argument parse) |
4681 | Mode is like LDRH. | |
4682 | ||
4683 | LDRccD R, mode | |
4684 | STRccD R, mode. */ | |
4685 | ||
a737bd4d | 4686 | static void |
c19d1205 | 4687 | do_ldrd (void) |
a737bd4d | 4688 | { |
c19d1205 ZW |
4689 | constraint (inst.operands[0].reg % 2 != 0, |
4690 | _("first destination register must be even")); | |
4691 | constraint (inst.operands[1].present | |
4692 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
4693 | _("can only load two consecutive registers")); | |
4694 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
4695 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 4696 | |
c19d1205 ZW |
4697 | if (!inst.operands[1].present) |
4698 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
4699 | ||
4700 | if (inst.instruction & LOAD_BIT) | |
a737bd4d | 4701 | { |
c19d1205 ZW |
4702 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
4703 | register and the first register written; we have to diagnose | |
4704 | overlap between the base and the second register written here. */ | |
ea6ef066 | 4705 | |
c19d1205 ZW |
4706 | if (inst.operands[2].reg == inst.operands[1].reg |
4707 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
4708 | as_warn (_("base register written back, and overlaps " | |
4709 | "second destination register")); | |
b05fe5cf | 4710 | |
c19d1205 ZW |
4711 | /* For an index-register load, the index register must not overlap the |
4712 | destination (even if not write-back). */ | |
4713 | else if (inst.operands[2].immisreg | |
ca3f61f7 NC |
4714 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg |
4715 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
c19d1205 | 4716 | as_warn (_("index register overlaps destination register")); |
b05fe5cf | 4717 | } |
c19d1205 ZW |
4718 | |
4719 | inst.instruction |= inst.operands[0].reg << 12; | |
4720 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
4721 | } |
4722 | ||
4723 | static void | |
c19d1205 | 4724 | do_ldrex (void) |
b05fe5cf | 4725 | { |
c19d1205 ZW |
4726 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
4727 | || inst.operands[1].postind || inst.operands[1].writeback | |
4728 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
4729 | || inst.operands[1].negative, | |
4730 | _("instruction does not accept this addressing mode")); | |
b05fe5cf | 4731 | |
c19d1205 | 4732 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); |
b05fe5cf | 4733 | |
c19d1205 ZW |
4734 | constraint (inst.reloc.exp.X_op != O_constant |
4735 | || inst.reloc.exp.X_add_number != 0, | |
4736 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 4737 | |
c19d1205 ZW |
4738 | inst.instruction |= inst.operands[0].reg << 12; |
4739 | inst.instruction |= inst.operands[1].reg << 16; | |
4740 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
4741 | } |
4742 | ||
4743 | static void | |
c19d1205 | 4744 | do_ldrexd (void) |
b05fe5cf | 4745 | { |
c19d1205 ZW |
4746 | constraint (inst.operands[0].reg % 2 != 0, |
4747 | _("even register required")); | |
4748 | constraint (inst.operands[1].present | |
4749 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
4750 | _("can only load two consecutive registers")); | |
4751 | /* If op 1 were present and equal to PC, this function wouldn't | |
4752 | have been called in the first place. */ | |
4753 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 4754 | |
c19d1205 ZW |
4755 | inst.instruction |= inst.operands[0].reg << 12; |
4756 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
4757 | } |
4758 | ||
4759 | static void | |
c19d1205 | 4760 | do_ldst (void) |
b05fe5cf | 4761 | { |
c19d1205 ZW |
4762 | inst.instruction |= inst.operands[0].reg << 12; |
4763 | if (!inst.operands[1].isreg) | |
4764 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) | |
b05fe5cf | 4765 | return; |
c19d1205 | 4766 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
4767 | } |
4768 | ||
4769 | static void | |
c19d1205 | 4770 | do_ldstt (void) |
b05fe5cf | 4771 | { |
c19d1205 ZW |
4772 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
4773 | reject [Rn,...]. */ | |
4774 | if (inst.operands[1].preind) | |
b05fe5cf | 4775 | { |
c19d1205 ZW |
4776 | constraint (inst.reloc.exp.X_op != O_constant || |
4777 | inst.reloc.exp.X_add_number != 0, | |
4778 | _("this instruction requires a post-indexed address")); | |
b05fe5cf | 4779 | |
c19d1205 ZW |
4780 | inst.operands[1].preind = 0; |
4781 | inst.operands[1].postind = 1; | |
4782 | inst.operands[1].writeback = 1; | |
b05fe5cf | 4783 | } |
c19d1205 ZW |
4784 | inst.instruction |= inst.operands[0].reg << 12; |
4785 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
4786 | } | |
b05fe5cf | 4787 | |
c19d1205 | 4788 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 4789 | |
c19d1205 ZW |
4790 | static void |
4791 | do_ldstv4 (void) | |
4792 | { | |
4793 | inst.instruction |= inst.operands[0].reg << 12; | |
4794 | if (!inst.operands[1].isreg) | |
4795 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) | |
b05fe5cf | 4796 | return; |
c19d1205 | 4797 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
4798 | } |
4799 | ||
4800 | static void | |
c19d1205 | 4801 | do_ldsttv4 (void) |
b05fe5cf | 4802 | { |
c19d1205 ZW |
4803 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
4804 | reject [Rn,...]. */ | |
4805 | if (inst.operands[1].preind) | |
b05fe5cf | 4806 | { |
c19d1205 ZW |
4807 | constraint (inst.reloc.exp.X_op != O_constant || |
4808 | inst.reloc.exp.X_add_number != 0, | |
4809 | _("this instruction requires a post-indexed address")); | |
b05fe5cf | 4810 | |
c19d1205 ZW |
4811 | inst.operands[1].preind = 0; |
4812 | inst.operands[1].postind = 1; | |
4813 | inst.operands[1].writeback = 1; | |
b05fe5cf | 4814 | } |
c19d1205 ZW |
4815 | inst.instruction |= inst.operands[0].reg << 12; |
4816 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
4817 | } | |
b05fe5cf | 4818 | |
c19d1205 ZW |
4819 | /* Co-processor register load/store. |
4820 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
4821 | static void | |
4822 | do_lstc (void) | |
4823 | { | |
4824 | inst.instruction |= inst.operands[0].reg << 8; | |
4825 | inst.instruction |= inst.operands[1].reg << 12; | |
4826 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
4827 | } |
4828 | ||
b05fe5cf | 4829 | static void |
c19d1205 | 4830 | do_mlas (void) |
b05fe5cf | 4831 | { |
c19d1205 ZW |
4832 | /* This restriction does not apply to mls (nor to mla in v6, but |
4833 | that's hard to detect at present). */ | |
4834 | if (inst.operands[0].reg == inst.operands[1].reg | |
4835 | && !(inst.instruction & 0x00400000)) | |
4836 | as_tsktsk (_("rd and rm should be different in mla")); | |
b05fe5cf | 4837 | |
c19d1205 ZW |
4838 | inst.instruction |= inst.operands[0].reg << 16; |
4839 | inst.instruction |= inst.operands[1].reg; | |
4840 | inst.instruction |= inst.operands[2].reg << 8; | |
4841 | inst.instruction |= inst.operands[3].reg << 12; | |
b05fe5cf | 4842 | |
c19d1205 | 4843 | } |
b05fe5cf | 4844 | |
c19d1205 ZW |
4845 | static void |
4846 | do_mov (void) | |
4847 | { | |
4848 | inst.instruction |= inst.operands[0].reg << 12; | |
4849 | encode_arm_shifter_operand (1); | |
4850 | } | |
b05fe5cf | 4851 | |
c19d1205 ZW |
4852 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
4853 | static void | |
4854 | do_mov16 (void) | |
4855 | { | |
4856 | inst.instruction |= inst.operands[0].reg << 12; | |
b05fe5cf | 4857 | /* The value is in two pieces: 0:11, 16:19. */ |
c19d1205 ZW |
4858 | inst.instruction |= (inst.operands[1].imm & 0x00000fff); |
4859 | inst.instruction |= (inst.operands[1].imm & 0x0000f000) << 4; | |
b05fe5cf | 4860 | } |
b99bd4ef NC |
4861 | |
4862 | static void | |
c19d1205 | 4863 | do_mrs (void) |
b99bd4ef | 4864 | { |
c19d1205 ZW |
4865 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ |
4866 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
4867 | != (PSR_c|PSR_f), | |
4868 | _("'CPSR' or 'SPSR' expected")); | |
4869 | inst.instruction |= inst.operands[0].reg << 12; | |
4870 | inst.instruction |= (inst.operands[1].imm & SPSR_BIT); | |
4871 | } | |
b99bd4ef | 4872 | |
c19d1205 ZW |
4873 | /* Two possible forms: |
4874 | "{C|S}PSR_<field>, Rm", | |
4875 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 4876 | |
c19d1205 ZW |
4877 | static void |
4878 | do_msr (void) | |
4879 | { | |
4880 | inst.instruction |= inst.operands[0].imm; | |
4881 | if (inst.operands[1].isreg) | |
4882 | inst.instruction |= inst.operands[1].reg; | |
4883 | else | |
b99bd4ef | 4884 | { |
c19d1205 ZW |
4885 | inst.instruction |= INST_IMMEDIATE; |
4886 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
4887 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 4888 | } |
b99bd4ef NC |
4889 | } |
4890 | ||
c19d1205 ZW |
4891 | static void |
4892 | do_mul (void) | |
a737bd4d | 4893 | { |
c19d1205 ZW |
4894 | if (!inst.operands[2].present) |
4895 | inst.operands[2].reg = inst.operands[0].reg; | |
4896 | inst.instruction |= inst.operands[0].reg << 16; | |
4897 | inst.instruction |= inst.operands[1].reg; | |
4898 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 4899 | |
c19d1205 ZW |
4900 | if (inst.operands[0].reg == inst.operands[1].reg) |
4901 | as_tsktsk (_("rd and rm should be different in mul")); | |
a737bd4d NC |
4902 | } |
4903 | ||
c19d1205 ZW |
4904 | /* Long Multiply Parser |
4905 | UMULL RdLo, RdHi, Rm, Rs | |
4906 | SMULL RdLo, RdHi, Rm, Rs | |
4907 | UMLAL RdLo, RdHi, Rm, Rs | |
4908 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
4909 | |
4910 | static void | |
c19d1205 | 4911 | do_mull (void) |
b99bd4ef | 4912 | { |
c19d1205 ZW |
4913 | inst.instruction |= inst.operands[0].reg << 12; |
4914 | inst.instruction |= inst.operands[1].reg << 16; | |
4915 | inst.instruction |= inst.operands[2].reg; | |
4916 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 4917 | |
c19d1205 ZW |
4918 | /* rdhi, rdlo and rm must all be different. */ |
4919 | if (inst.operands[0].reg == inst.operands[1].reg | |
4920 | || inst.operands[0].reg == inst.operands[2].reg | |
4921 | || inst.operands[1].reg == inst.operands[2].reg) | |
4922 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); | |
4923 | } | |
b99bd4ef | 4924 | |
c19d1205 ZW |
4925 | static void |
4926 | do_nop (void) | |
4927 | { | |
4928 | if (inst.operands[0].present) | |
4929 | { | |
4930 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
4931 | inst.instruction &= 0xf0000000; | |
4932 | inst.instruction |= 0x0320f000 + inst.operands[0].imm; | |
4933 | } | |
b99bd4ef NC |
4934 | } |
4935 | ||
c19d1205 ZW |
4936 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
4937 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
4938 | Condition defaults to COND_ALWAYS. | |
4939 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
4940 | |
4941 | static void | |
c19d1205 | 4942 | do_pkhbt (void) |
b99bd4ef | 4943 | { |
c19d1205 ZW |
4944 | inst.instruction |= inst.operands[0].reg << 12; |
4945 | inst.instruction |= inst.operands[1].reg << 16; | |
4946 | inst.instruction |= inst.operands[2].reg; | |
4947 | if (inst.operands[3].present) | |
4948 | encode_arm_shift (3); | |
4949 | } | |
b99bd4ef | 4950 | |
c19d1205 | 4951 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 4952 | |
c19d1205 ZW |
4953 | static void |
4954 | do_pkhtb (void) | |
4955 | { | |
4956 | if (!inst.operands[3].present) | |
b99bd4ef | 4957 | { |
c19d1205 ZW |
4958 | /* If the shift specifier is omitted, turn the instruction |
4959 | into pkhbt rd, rm, rn. */ | |
4960 | inst.instruction &= 0xfff00010; | |
4961 | inst.instruction |= inst.operands[0].reg << 12; | |
4962 | inst.instruction |= inst.operands[1].reg; | |
4963 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
4964 | } |
4965 | else | |
4966 | { | |
c19d1205 ZW |
4967 | inst.instruction |= inst.operands[0].reg << 12; |
4968 | inst.instruction |= inst.operands[1].reg << 16; | |
4969 | inst.instruction |= inst.operands[2].reg; | |
4970 | encode_arm_shift (3); | |
b99bd4ef NC |
4971 | } |
4972 | } | |
4973 | ||
c19d1205 ZW |
4974 | /* ARMv5TE: Preload-Cache |
4975 | ||
4976 | PLD <addr_mode> | |
4977 | ||
4978 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
4979 | |
4980 | static void | |
c19d1205 | 4981 | do_pld (void) |
b99bd4ef | 4982 | { |
c19d1205 ZW |
4983 | constraint (!inst.operands[0].isreg, |
4984 | _("'[' expected after PLD mnemonic")); | |
4985 | constraint (inst.operands[0].postind, | |
4986 | _("post-indexed expression used in preload instruction")); | |
4987 | constraint (inst.operands[0].writeback, | |
4988 | _("writeback used in preload instruction")); | |
4989 | constraint (!inst.operands[0].preind, | |
4990 | _("unindexed addressing used in preload instruction")); | |
4991 | inst.instruction |= inst.operands[0].reg; | |
4992 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
4993 | } | |
b99bd4ef | 4994 | |
c19d1205 ZW |
4995 | static void |
4996 | do_push_pop (void) | |
4997 | { | |
4998 | inst.operands[1] = inst.operands[0]; | |
4999 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
5000 | inst.operands[0].isreg = 1; | |
5001 | inst.operands[0].writeback = 1; | |
5002 | inst.operands[0].reg = REG_SP; | |
5003 | do_ldmstm (); | |
5004 | } | |
b99bd4ef | 5005 | |
c19d1205 ZW |
5006 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
5007 | word at the specified address and the following word | |
5008 | respectively. | |
5009 | Unconditionally executed. | |
5010 | Error if Rn is R15. */ | |
b99bd4ef | 5011 | |
c19d1205 ZW |
5012 | static void |
5013 | do_rfe (void) | |
5014 | { | |
5015 | inst.instruction |= inst.operands[0].reg << 16; | |
5016 | if (inst.operands[0].writeback) | |
5017 | inst.instruction |= WRITE_BACK; | |
5018 | } | |
b99bd4ef | 5019 | |
c19d1205 | 5020 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 5021 | |
c19d1205 ZW |
5022 | static void |
5023 | do_ssat (void) | |
5024 | { | |
5025 | inst.instruction |= inst.operands[0].reg << 12; | |
5026 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
5027 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 5028 | |
c19d1205 ZW |
5029 | if (inst.operands[3].present) |
5030 | encode_arm_shift (3); | |
b99bd4ef NC |
5031 | } |
5032 | ||
c19d1205 | 5033 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
5034 | |
5035 | static void | |
c19d1205 | 5036 | do_usat (void) |
b99bd4ef | 5037 | { |
c19d1205 ZW |
5038 | inst.instruction |= inst.operands[0].reg << 12; |
5039 | inst.instruction |= inst.operands[1].imm << 16; | |
5040 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 5041 | |
c19d1205 ZW |
5042 | if (inst.operands[3].present) |
5043 | encode_arm_shift (3); | |
b99bd4ef NC |
5044 | } |
5045 | ||
c19d1205 | 5046 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
5047 | |
5048 | static void | |
c19d1205 | 5049 | do_ssat16 (void) |
09d92015 | 5050 | { |
c19d1205 ZW |
5051 | inst.instruction |= inst.operands[0].reg << 12; |
5052 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
5053 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
5054 | } |
5055 | ||
c19d1205 ZW |
5056 | static void |
5057 | do_usat16 (void) | |
a737bd4d | 5058 | { |
c19d1205 ZW |
5059 | inst.instruction |= inst.operands[0].reg << 12; |
5060 | inst.instruction |= inst.operands[1].imm << 16; | |
5061 | inst.instruction |= inst.operands[2].reg; | |
5062 | } | |
a737bd4d | 5063 | |
c19d1205 ZW |
5064 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
5065 | preserving the other bits. | |
a737bd4d | 5066 | |
c19d1205 ZW |
5067 | setend <endian_specifier>, where <endian_specifier> is either |
5068 | BE or LE. */ | |
a737bd4d | 5069 | |
c19d1205 ZW |
5070 | static void |
5071 | do_setend (void) | |
5072 | { | |
5073 | if (inst.operands[0].imm) | |
5074 | inst.instruction |= 0x200; | |
a737bd4d NC |
5075 | } |
5076 | ||
5077 | static void | |
c19d1205 | 5078 | do_shift (void) |
a737bd4d | 5079 | { |
c19d1205 ZW |
5080 | unsigned int Rm = (inst.operands[1].present |
5081 | ? inst.operands[1].reg | |
5082 | : inst.operands[0].reg); | |
a737bd4d | 5083 | |
c19d1205 ZW |
5084 | inst.instruction |= inst.operands[0].reg << 12; |
5085 | inst.instruction |= Rm; | |
5086 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 5087 | { |
c19d1205 ZW |
5088 | constraint (inst.operands[0].reg != Rm, |
5089 | _("source1 and dest must be same register")); | |
5090 | inst.instruction |= inst.operands[2].reg << 8; | |
5091 | inst.instruction |= SHIFT_BY_REG; | |
a737bd4d NC |
5092 | } |
5093 | else | |
c19d1205 | 5094 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
5095 | } |
5096 | ||
09d92015 | 5097 | static void |
3eb17e6b | 5098 | do_smc (void) |
09d92015 | 5099 | { |
3eb17e6b | 5100 | inst.reloc.type = BFD_RELOC_ARM_SMC; |
c19d1205 | 5101 | inst.reloc.pc_rel = 0; |
09d92015 MM |
5102 | } |
5103 | ||
09d92015 | 5104 | static void |
c19d1205 | 5105 | do_swi (void) |
09d92015 | 5106 | { |
c19d1205 ZW |
5107 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
5108 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
5109 | } |
5110 | ||
c19d1205 ZW |
5111 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
5112 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
5113 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
5114 | Error if any register is R15. */ | |
e16bb312 | 5115 | |
c19d1205 ZW |
5116 | static void |
5117 | do_smla (void) | |
e16bb312 | 5118 | { |
c19d1205 ZW |
5119 | inst.instruction |= inst.operands[0].reg << 16; |
5120 | inst.instruction |= inst.operands[1].reg; | |
5121 | inst.instruction |= inst.operands[2].reg << 8; | |
5122 | inst.instruction |= inst.operands[3].reg << 12; | |
5123 | } | |
a737bd4d | 5124 | |
c19d1205 ZW |
5125 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
5126 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
5127 | Error if any register is R15. | |
5128 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 5129 | |
c19d1205 ZW |
5130 | static void |
5131 | do_smlal (void) | |
5132 | { | |
5133 | inst.instruction |= inst.operands[0].reg << 12; | |
5134 | inst.instruction |= inst.operands[1].reg << 16; | |
5135 | inst.instruction |= inst.operands[2].reg; | |
5136 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 5137 | |
c19d1205 ZW |
5138 | if (inst.operands[0].reg == inst.operands[1].reg) |
5139 | as_tsktsk (_("rdhi and rdlo must be different")); | |
5140 | } | |
a737bd4d | 5141 | |
c19d1205 ZW |
5142 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
5143 | SMULxy{cond} Rd,Rm,Rs | |
5144 | Error if any register is R15. */ | |
a737bd4d | 5145 | |
c19d1205 ZW |
5146 | static void |
5147 | do_smul (void) | |
5148 | { | |
5149 | inst.instruction |= inst.operands[0].reg << 16; | |
5150 | inst.instruction |= inst.operands[1].reg; | |
5151 | inst.instruction |= inst.operands[2].reg << 8; | |
5152 | } | |
a737bd4d | 5153 | |
c19d1205 | 5154 | /* ARM V6 srs (argument parse). */ |
a737bd4d | 5155 | |
c19d1205 ZW |
5156 | static void |
5157 | do_srs (void) | |
5158 | { | |
5159 | inst.instruction |= inst.operands[0].imm; | |
5160 | if (inst.operands[0].writeback) | |
5161 | inst.instruction |= WRITE_BACK; | |
5162 | } | |
a737bd4d | 5163 | |
c19d1205 | 5164 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 5165 | |
c19d1205 ZW |
5166 | static void |
5167 | do_strex (void) | |
5168 | { | |
5169 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
5170 | || inst.operands[2].postind || inst.operands[2].writeback | |
5171 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
5172 | || inst.operands[2].negative, | |
5173 | _("instruction does not accept this addressing mode")); | |
e16bb312 | 5174 | |
c19d1205 | 5175 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
a737bd4d | 5176 | |
c19d1205 ZW |
5177 | constraint (inst.operands[0].reg == inst.operands[1].reg |
5178 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 5179 | |
c19d1205 ZW |
5180 | constraint (inst.reloc.exp.X_op != O_constant |
5181 | || inst.reloc.exp.X_add_number != 0, | |
5182 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 5183 | |
c19d1205 ZW |
5184 | inst.instruction |= inst.operands[0].reg << 12; |
5185 | inst.instruction |= inst.operands[1].reg; | |
5186 | inst.instruction |= inst.operands[2].reg << 16; | |
5187 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
5188 | } |
5189 | ||
5190 | static void | |
c19d1205 | 5191 | do_strexd (void) |
e16bb312 | 5192 | { |
c19d1205 ZW |
5193 | constraint (inst.operands[1].reg % 2 != 0, |
5194 | _("even register required")); | |
5195 | constraint (inst.operands[2].present | |
5196 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
5197 | _("can only store two consecutive registers")); | |
5198 | /* If op 2 were present and equal to PC, this function wouldn't | |
5199 | have been called in the first place. */ | |
5200 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 5201 | |
c19d1205 ZW |
5202 | constraint (inst.operands[0].reg == inst.operands[1].reg |
5203 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
5204 | || inst.operands[0].reg == inst.operands[3].reg, | |
5205 | BAD_OVERLAP); | |
e16bb312 | 5206 | |
c19d1205 ZW |
5207 | inst.instruction |= inst.operands[0].reg << 12; |
5208 | inst.instruction |= inst.operands[1].reg; | |
5209 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
5210 | } |
5211 | ||
c19d1205 ZW |
5212 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
5213 | extends it to 32-bits, and adds the result to a value in another | |
5214 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
5215 | before extracting the 16-bit value. | |
5216 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
5217 | Condition defaults to COND_ALWAYS. | |
5218 | Error if any register uses R15. */ | |
5219 | ||
e16bb312 | 5220 | static void |
c19d1205 | 5221 | do_sxtah (void) |
e16bb312 | 5222 | { |
c19d1205 ZW |
5223 | inst.instruction |= inst.operands[0].reg << 12; |
5224 | inst.instruction |= inst.operands[1].reg << 16; | |
5225 | inst.instruction |= inst.operands[2].reg; | |
5226 | inst.instruction |= inst.operands[3].imm << 10; | |
5227 | } | |
e16bb312 | 5228 | |
c19d1205 | 5229 | /* ARM V6 SXTH. |
e16bb312 | 5230 | |
c19d1205 ZW |
5231 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
5232 | Condition defaults to COND_ALWAYS. | |
5233 | Error if any register uses R15. */ | |
e16bb312 NC |
5234 | |
5235 | static void | |
c19d1205 | 5236 | do_sxth (void) |
e16bb312 | 5237 | { |
c19d1205 ZW |
5238 | inst.instruction |= inst.operands[0].reg << 12; |
5239 | inst.instruction |= inst.operands[1].reg; | |
5240 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 5241 | } |
c19d1205 ZW |
5242 | \f |
5243 | /* VFP instructions. In a logical order: SP variant first, monad | |
5244 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
5245 | |
5246 | static void | |
c19d1205 | 5247 | do_vfp_sp_monadic (void) |
e16bb312 | 5248 | { |
c19d1205 ZW |
5249 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
5250 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
5251 | } |
5252 | ||
5253 | static void | |
c19d1205 | 5254 | do_vfp_sp_dyadic (void) |
e16bb312 | 5255 | { |
c19d1205 ZW |
5256 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
5257 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
5258 | encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
5259 | } |
5260 | ||
5261 | static void | |
c19d1205 | 5262 | do_vfp_sp_compare_z (void) |
e16bb312 | 5263 | { |
c19d1205 | 5264 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
5265 | } |
5266 | ||
5267 | static void | |
c19d1205 | 5268 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 5269 | { |
c19d1205 ZW |
5270 | inst.instruction |= inst.operands[0].reg << 12; |
5271 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
5272 | } |
5273 | ||
5274 | static void | |
c19d1205 | 5275 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 5276 | { |
c19d1205 ZW |
5277 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
5278 | inst.instruction |= inst.operands[1].reg; | |
e16bb312 NC |
5279 | } |
5280 | ||
5281 | static void | |
c19d1205 | 5282 | do_vfp_reg_from_sp (void) |
e16bb312 | 5283 | { |
c19d1205 ZW |
5284 | inst.instruction |= inst.operands[0].reg << 12; |
5285 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
e16bb312 NC |
5286 | } |
5287 | ||
5288 | static void | |
c19d1205 | 5289 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 5290 | { |
c19d1205 ZW |
5291 | constraint (inst.operands[2].imm != 2, |
5292 | _("only two consecutive VFP SP registers allowed here")); | |
5293 | inst.instruction |= inst.operands[0].reg << 12; | |
5294 | inst.instruction |= inst.operands[1].reg << 16; | |
5295 | encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
5296 | } |
5297 | ||
5298 | static void | |
c19d1205 | 5299 | do_vfp_sp_from_reg (void) |
e16bb312 | 5300 | { |
c19d1205 ZW |
5301 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sn); |
5302 | inst.instruction |= inst.operands[1].reg << 12; | |
e16bb312 NC |
5303 | } |
5304 | ||
5305 | static void | |
c19d1205 | 5306 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 5307 | { |
c19d1205 ZW |
5308 | constraint (inst.operands[0].imm != 2, |
5309 | _("only two consecutive VFP SP registers allowed here")); | |
5310 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sm); | |
5311 | inst.instruction |= inst.operands[1].reg << 12; | |
5312 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
5313 | } |
5314 | ||
5315 | static void | |
c19d1205 | 5316 | do_vfp_sp_ldst (void) |
e16bb312 | 5317 | { |
c19d1205 ZW |
5318 | encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd); |
5319 | encode_arm_cp_address (1, FALSE, TRUE, 0); | |
e16bb312 NC |
5320 | } |
5321 | ||
5322 | static void | |
c19d1205 | 5323 | do_vfp_dp_ldst (void) |
e16bb312 | 5324 | { |
c19d1205 ZW |
5325 | inst.instruction |= inst.operands[0].reg << 12; |
5326 | encode_arm_cp_address (1, FALSE, TRUE, 0); | |
e16bb312 NC |
5327 | } |
5328 | ||
c19d1205 | 5329 | |
e16bb312 | 5330 | static void |
c19d1205 | 5331 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 5332 | { |
c19d1205 ZW |
5333 | if (inst.operands[0].writeback) |
5334 | inst.instruction |= WRITE_BACK; | |
5335 | else | |
5336 | constraint (ldstm_type != VFP_LDSTMIA, | |
5337 | _("this addressing mode requires base-register writeback")); | |
5338 | inst.instruction |= inst.operands[0].reg << 16; | |
5339 | encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sd); | |
5340 | inst.instruction |= inst.operands[1].imm; | |
e16bb312 NC |
5341 | } |
5342 | ||
5343 | static void | |
c19d1205 | 5344 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 5345 | { |
c19d1205 | 5346 | int count; |
e16bb312 | 5347 | |
c19d1205 ZW |
5348 | if (inst.operands[0].writeback) |
5349 | inst.instruction |= WRITE_BACK; | |
5350 | else | |
5351 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
5352 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 5353 | |
c19d1205 ZW |
5354 | inst.instruction |= inst.operands[0].reg << 16; |
5355 | inst.instruction |= inst.operands[1].reg << 12; | |
e16bb312 | 5356 | |
c19d1205 ZW |
5357 | count = inst.operands[1].imm << 1; |
5358 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
5359 | count += 1; | |
e16bb312 | 5360 | |
c19d1205 | 5361 | inst.instruction |= count; |
e16bb312 NC |
5362 | } |
5363 | ||
5364 | static void | |
c19d1205 | 5365 | do_vfp_sp_ldstmia (void) |
e16bb312 | 5366 | { |
c19d1205 | 5367 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
5368 | } |
5369 | ||
5370 | static void | |
c19d1205 | 5371 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 5372 | { |
c19d1205 | 5373 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
5374 | } |
5375 | ||
5376 | static void | |
c19d1205 | 5377 | do_vfp_dp_ldstmia (void) |
e16bb312 | 5378 | { |
c19d1205 | 5379 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
5380 | } |
5381 | ||
5382 | static void | |
c19d1205 | 5383 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 5384 | { |
c19d1205 | 5385 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
5386 | } |
5387 | ||
5388 | static void | |
c19d1205 | 5389 | do_vfp_xp_ldstmia (void) |
e16bb312 | 5390 | { |
c19d1205 ZW |
5391 | vfp_dp_ldstm (VFP_LDSTMIAX); |
5392 | } | |
e16bb312 | 5393 | |
c19d1205 ZW |
5394 | static void |
5395 | do_vfp_xp_ldstmdb (void) | |
5396 | { | |
5397 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 5398 | } |
c19d1205 ZW |
5399 | \f |
5400 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 5401 | |
c19d1205 ZW |
5402 | static void |
5403 | do_fpa_cmp (void) | |
5404 | { | |
5405 | inst.instruction |= inst.operands[0].reg << 16; | |
5406 | inst.instruction |= inst.operands[1].reg; | |
5407 | } | |
b99bd4ef NC |
5408 | |
5409 | static void | |
c19d1205 | 5410 | do_fpa_ldmstm (void) |
b99bd4ef | 5411 | { |
c19d1205 ZW |
5412 | inst.instruction |= inst.operands[0].reg << 12; |
5413 | switch (inst.operands[1].imm) | |
5414 | { | |
5415 | case 1: inst.instruction |= CP_T_X; break; | |
5416 | case 2: inst.instruction |= CP_T_Y; break; | |
5417 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
5418 | case 4: break; | |
5419 | default: abort (); | |
5420 | } | |
b99bd4ef | 5421 | |
c19d1205 ZW |
5422 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
5423 | { | |
5424 | /* The instruction specified "ea" or "fd", so we can only accept | |
5425 | [Rn]{!}. The instruction does not really support stacking or | |
5426 | unstacking, so we have to emulate these by setting appropriate | |
5427 | bits and offsets. */ | |
5428 | constraint (inst.reloc.exp.X_op != O_constant | |
5429 | || inst.reloc.exp.X_add_number != 0, | |
5430 | _("this instruction does not support indexing")); | |
b99bd4ef | 5431 | |
c19d1205 ZW |
5432 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
5433 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 5434 | |
c19d1205 ZW |
5435 | if (!(inst.instruction & INDEX_UP)) |
5436 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 5437 | |
c19d1205 ZW |
5438 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
5439 | { | |
5440 | inst.operands[2].preind = 0; | |
5441 | inst.operands[2].postind = 1; | |
5442 | } | |
5443 | } | |
b99bd4ef | 5444 | |
c19d1205 | 5445 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 5446 | } |
c19d1205 ZW |
5447 | \f |
5448 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 5449 | |
c19d1205 ZW |
5450 | static void |
5451 | do_iwmmxt_tandorc (void) | |
5452 | { | |
5453 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
5454 | } | |
b99bd4ef | 5455 | |
c19d1205 ZW |
5456 | static void |
5457 | do_iwmmxt_textrc (void) | |
5458 | { | |
5459 | inst.instruction |= inst.operands[0].reg << 12; | |
5460 | inst.instruction |= inst.operands[1].imm; | |
5461 | } | |
b99bd4ef NC |
5462 | |
5463 | static void | |
c19d1205 | 5464 | do_iwmmxt_textrm (void) |
b99bd4ef | 5465 | { |
c19d1205 ZW |
5466 | inst.instruction |= inst.operands[0].reg << 12; |
5467 | inst.instruction |= inst.operands[1].reg << 16; | |
5468 | inst.instruction |= inst.operands[2].imm; | |
5469 | } | |
b99bd4ef | 5470 | |
c19d1205 ZW |
5471 | static void |
5472 | do_iwmmxt_tinsr (void) | |
5473 | { | |
5474 | inst.instruction |= inst.operands[0].reg << 16; | |
5475 | inst.instruction |= inst.operands[1].reg << 12; | |
5476 | inst.instruction |= inst.operands[2].imm; | |
5477 | } | |
b99bd4ef | 5478 | |
c19d1205 ZW |
5479 | static void |
5480 | do_iwmmxt_tmia (void) | |
5481 | { | |
5482 | inst.instruction |= inst.operands[0].reg << 5; | |
5483 | inst.instruction |= inst.operands[1].reg; | |
5484 | inst.instruction |= inst.operands[2].reg << 12; | |
5485 | } | |
b99bd4ef | 5486 | |
c19d1205 ZW |
5487 | static void |
5488 | do_iwmmxt_waligni (void) | |
5489 | { | |
5490 | inst.instruction |= inst.operands[0].reg << 12; | |
5491 | inst.instruction |= inst.operands[1].reg << 16; | |
5492 | inst.instruction |= inst.operands[2].reg; | |
5493 | inst.instruction |= inst.operands[3].imm << 20; | |
5494 | } | |
b99bd4ef | 5495 | |
c19d1205 ZW |
5496 | static void |
5497 | do_iwmmxt_wmov (void) | |
5498 | { | |
5499 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
5500 | inst.instruction |= inst.operands[0].reg << 12; | |
5501 | inst.instruction |= inst.operands[1].reg << 16; | |
5502 | inst.instruction |= inst.operands[1].reg; | |
5503 | } | |
b99bd4ef | 5504 | |
c19d1205 ZW |
5505 | static void |
5506 | do_iwmmxt_wldstbh (void) | |
5507 | { | |
8f06b2d8 | 5508 | int reloc; |
c19d1205 ZW |
5509 | inst.instruction |= inst.operands[0].reg << 12; |
5510 | inst.reloc.exp.X_add_number *= 4; | |
8f06b2d8 PB |
5511 | if (thumb_mode) |
5512 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
5513 | else | |
5514 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
5515 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
5516 | } |
5517 | ||
c19d1205 ZW |
5518 | static void |
5519 | do_iwmmxt_wldstw (void) | |
5520 | { | |
5521 | /* RIWR_RIWC clears .isreg for a control register. */ | |
5522 | if (!inst.operands[0].isreg) | |
5523 | { | |
5524 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
5525 | inst.instruction |= 0xf0000000; | |
5526 | } | |
b99bd4ef | 5527 | |
c19d1205 ZW |
5528 | inst.instruction |= inst.operands[0].reg << 12; |
5529 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
5530 | } | |
b99bd4ef NC |
5531 | |
5532 | static void | |
c19d1205 | 5533 | do_iwmmxt_wldstd (void) |
b99bd4ef | 5534 | { |
c19d1205 | 5535 | inst.instruction |= inst.operands[0].reg << 12; |
f2184508 | 5536 | encode_arm_cp_address (1, TRUE, FALSE, 0); |
c19d1205 | 5537 | } |
b99bd4ef | 5538 | |
c19d1205 ZW |
5539 | static void |
5540 | do_iwmmxt_wshufh (void) | |
5541 | { | |
5542 | inst.instruction |= inst.operands[0].reg << 12; | |
5543 | inst.instruction |= inst.operands[1].reg << 16; | |
5544 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
5545 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
5546 | } | |
b99bd4ef | 5547 | |
c19d1205 ZW |
5548 | static void |
5549 | do_iwmmxt_wzero (void) | |
5550 | { | |
5551 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
5552 | inst.instruction |= inst.operands[0].reg; | |
5553 | inst.instruction |= inst.operands[0].reg << 12; | |
5554 | inst.instruction |= inst.operands[0].reg << 16; | |
5555 | } | |
5556 | \f | |
5557 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
5558 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 5559 | |
c19d1205 | 5560 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 5561 | |
c19d1205 ZW |
5562 | static void |
5563 | do_mav_triple (void) | |
5564 | { | |
5565 | inst.instruction |= inst.operands[0].reg << 16; | |
5566 | inst.instruction |= inst.operands[1].reg; | |
5567 | inst.instruction |= inst.operands[2].reg << 12; | |
5568 | } | |
b99bd4ef | 5569 | |
c19d1205 ZW |
5570 | /* Insns like "foo W,X,Y,Z". |
5571 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 5572 | |
c19d1205 ZW |
5573 | static void |
5574 | do_mav_quad (void) | |
5575 | { | |
5576 | inst.instruction |= inst.operands[0].reg << 5; | |
5577 | inst.instruction |= inst.operands[1].reg << 12; | |
5578 | inst.instruction |= inst.operands[2].reg << 16; | |
5579 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
5580 | } |
5581 | ||
c19d1205 ZW |
5582 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
5583 | static void | |
5584 | do_mav_dspsc (void) | |
a737bd4d | 5585 | { |
c19d1205 ZW |
5586 | inst.instruction |= inst.operands[1].reg << 12; |
5587 | } | |
a737bd4d | 5588 | |
c19d1205 ZW |
5589 | /* Maverick shift immediate instructions. |
5590 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
5591 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 5592 | |
c19d1205 ZW |
5593 | static void |
5594 | do_mav_shift (void) | |
5595 | { | |
5596 | int imm = inst.operands[2].imm; | |
a737bd4d | 5597 | |
c19d1205 ZW |
5598 | inst.instruction |= inst.operands[0].reg << 12; |
5599 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 5600 | |
c19d1205 ZW |
5601 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
5602 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
5603 | Bit 4 should be 0. */ | |
5604 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 5605 | |
c19d1205 ZW |
5606 | inst.instruction |= imm; |
5607 | } | |
5608 | \f | |
5609 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 5610 | |
c19d1205 ZW |
5611 | /* Xscale multiply-accumulate (argument parse) |
5612 | MIAcc acc0,Rm,Rs | |
5613 | MIAPHcc acc0,Rm,Rs | |
5614 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 5615 | |
c19d1205 ZW |
5616 | static void |
5617 | do_xsc_mia (void) | |
5618 | { | |
5619 | inst.instruction |= inst.operands[1].reg; | |
5620 | inst.instruction |= inst.operands[2].reg << 12; | |
5621 | } | |
a737bd4d | 5622 | |
c19d1205 | 5623 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 5624 | |
c19d1205 | 5625 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 5626 | |
c19d1205 ZW |
5627 | static void |
5628 | do_xsc_mar (void) | |
5629 | { | |
5630 | inst.instruction |= inst.operands[1].reg << 12; | |
5631 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
5632 | } |
5633 | ||
c19d1205 | 5634 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 5635 | |
c19d1205 | 5636 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
5637 | |
5638 | static void | |
c19d1205 | 5639 | do_xsc_mra (void) |
b99bd4ef | 5640 | { |
c19d1205 ZW |
5641 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
5642 | inst.instruction |= inst.operands[0].reg << 12; | |
5643 | inst.instruction |= inst.operands[1].reg << 16; | |
5644 | } | |
5645 | \f | |
5646 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 5647 | |
c19d1205 ZW |
5648 | /* inst.operands[i] is a shifted-register operand; encode |
5649 | it into inst.instruction in the format used by Thumb32. */ | |
5650 | ||
5651 | static void | |
5652 | encode_thumb32_shifted_operand (int i) | |
5653 | { | |
5654 | unsigned int value = inst.reloc.exp.X_add_number; | |
5655 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 5656 | |
9c3c69f2 PB |
5657 | constraint (inst.operands[i].immisreg, |
5658 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
5659 | inst.instruction |= inst.operands[i].reg; |
5660 | if (shift == SHIFT_RRX) | |
5661 | inst.instruction |= SHIFT_ROR << 4; | |
5662 | else | |
b99bd4ef | 5663 | { |
c19d1205 ZW |
5664 | constraint (inst.reloc.exp.X_op != O_constant, |
5665 | _("expression too complex")); | |
5666 | ||
5667 | constraint (value > 32 | |
5668 | || (value == 32 && (shift == SHIFT_LSL | |
5669 | || shift == SHIFT_ROR)), | |
5670 | _("shift expression is too large")); | |
5671 | ||
5672 | if (value == 0) | |
5673 | shift = SHIFT_LSL; | |
5674 | else if (value == 32) | |
5675 | value = 0; | |
5676 | ||
5677 | inst.instruction |= shift << 4; | |
5678 | inst.instruction |= (value & 0x1c) << 10; | |
5679 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 5680 | } |
c19d1205 | 5681 | } |
b99bd4ef | 5682 | |
b99bd4ef | 5683 | |
c19d1205 ZW |
5684 | /* inst.operands[i] was set up by parse_address. Encode it into a |
5685 | Thumb32 format load or store instruction. Reject forms that cannot | |
5686 | be used with such instructions. If is_t is true, reject forms that | |
5687 | cannot be used with a T instruction; if is_d is true, reject forms | |
5688 | that cannot be used with a D instruction. */ | |
b99bd4ef | 5689 | |
c19d1205 ZW |
5690 | static void |
5691 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
5692 | { | |
5693 | bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); | |
5694 | ||
5695 | constraint (!inst.operands[i].isreg, | |
5696 | _("Thumb does not support the ldr =N pseudo-operation")); | |
b99bd4ef | 5697 | |
c19d1205 ZW |
5698 | inst.instruction |= inst.operands[i].reg << 16; |
5699 | if (inst.operands[i].immisreg) | |
b99bd4ef | 5700 | { |
c19d1205 ZW |
5701 | constraint (is_pc, _("cannot use register index with PC-relative addressing")); |
5702 | constraint (is_t || is_d, _("cannot use register index with this instruction")); | |
5703 | constraint (inst.operands[i].negative, | |
5704 | _("Thumb does not support negative register indexing")); | |
5705 | constraint (inst.operands[i].postind, | |
5706 | _("Thumb does not support register post-indexing")); | |
5707 | constraint (inst.operands[i].writeback, | |
5708 | _("Thumb does not support register indexing with writeback")); | |
5709 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
5710 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 5711 | |
c19d1205 ZW |
5712 | inst.instruction |= inst.operands[1].imm; |
5713 | if (inst.operands[i].shifted) | |
b99bd4ef | 5714 | { |
c19d1205 ZW |
5715 | constraint (inst.reloc.exp.X_op != O_constant, |
5716 | _("expression too complex")); | |
9c3c69f2 PB |
5717 | constraint (inst.reloc.exp.X_add_number < 0 |
5718 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 5719 | _("shift out of range")); |
9c3c69f2 | 5720 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
5721 | } |
5722 | inst.reloc.type = BFD_RELOC_UNUSED; | |
5723 | } | |
5724 | else if (inst.operands[i].preind) | |
5725 | { | |
5726 | constraint (is_pc && inst.operands[i].writeback, | |
5727 | _("cannot use writeback with PC-relative addressing")); | |
5728 | constraint (is_t && inst.operands[1].writeback, | |
5729 | _("cannot use writeback with this instruction")); | |
5730 | ||
5731 | if (is_d) | |
5732 | { | |
5733 | inst.instruction |= 0x01000000; | |
5734 | if (inst.operands[i].writeback) | |
5735 | inst.instruction |= 0x00200000; | |
b99bd4ef | 5736 | } |
c19d1205 | 5737 | else |
b99bd4ef | 5738 | { |
c19d1205 ZW |
5739 | inst.instruction |= 0x00000c00; |
5740 | if (inst.operands[i].writeback) | |
5741 | inst.instruction |= 0x00000100; | |
b99bd4ef | 5742 | } |
c19d1205 | 5743 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 5744 | } |
c19d1205 | 5745 | else if (inst.operands[i].postind) |
b99bd4ef | 5746 | { |
c19d1205 ZW |
5747 | assert (inst.operands[i].writeback); |
5748 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); | |
5749 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
5750 | ||
5751 | if (is_d) | |
5752 | inst.instruction |= 0x00200000; | |
5753 | else | |
5754 | inst.instruction |= 0x00000900; | |
5755 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
5756 | } | |
5757 | else /* unindexed - only for coprocessor */ | |
5758 | inst.error = _("instruction does not accept unindexed addressing"); | |
5759 | } | |
5760 | ||
5761 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
5762 | encodings (the latter only in post-V6T2 cores). The index is the | |
5763 | value used in the insns table below. When there is more than one | |
5764 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
5765 | holds variant (1). |
5766 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 ZW |
5767 | #define T16_32_TAB \ |
5768 | X(adc, 4140, eb400000), \ | |
5769 | X(adcs, 4140, eb500000), \ | |
5770 | X(add, 1c00, eb000000), \ | |
5771 | X(adds, 1c00, eb100000), \ | |
0110f2b8 PB |
5772 | X(addi, 0000, f1000000), \ |
5773 | X(addis, 0000, f1100000), \ | |
5774 | X(add_pc,000f, f20f0000), \ | |
5775 | X(add_sp,000d, f10d0000), \ | |
e9f89963 | 5776 | X(adr, 000f, f20f0000), \ |
c19d1205 ZW |
5777 | X(and, 4000, ea000000), \ |
5778 | X(ands, 4000, ea100000), \ | |
5779 | X(asr, 1000, fa40f000), \ | |
5780 | X(asrs, 1000, fa50f000), \ | |
0110f2b8 PB |
5781 | X(b, e000, f000b000), \ |
5782 | X(bcond, d000, f0008000), \ | |
c19d1205 ZW |
5783 | X(bic, 4380, ea200000), \ |
5784 | X(bics, 4380, ea300000), \ | |
5785 | X(cmn, 42c0, eb100f00), \ | |
5786 | X(cmp, 2800, ebb00f00), \ | |
5787 | X(cpsie, b660, f3af8400), \ | |
5788 | X(cpsid, b670, f3af8600), \ | |
5789 | X(cpy, 4600, ea4f0000), \ | |
0110f2b8 | 5790 | X(dec_sp,80dd, f1bd0d00), \ |
c19d1205 ZW |
5791 | X(eor, 4040, ea800000), \ |
5792 | X(eors, 4040, ea900000), \ | |
0110f2b8 | 5793 | X(inc_sp,00dd, f10d0d00), \ |
c19d1205 ZW |
5794 | X(ldmia, c800, e8900000), \ |
5795 | X(ldr, 6800, f8500000), \ | |
5796 | X(ldrb, 7800, f8100000), \ | |
5797 | X(ldrh, 8800, f8300000), \ | |
5798 | X(ldrsb, 5600, f9100000), \ | |
5799 | X(ldrsh, 5e00, f9300000), \ | |
0110f2b8 PB |
5800 | X(ldr_pc,4800, f85f0000), \ |
5801 | X(ldr_pc2,4800, f85f0000), \ | |
5802 | X(ldr_sp,9800, f85d0000), \ | |
c19d1205 ZW |
5803 | X(lsl, 0000, fa00f000), \ |
5804 | X(lsls, 0000, fa10f000), \ | |
5805 | X(lsr, 0800, fa20f000), \ | |
5806 | X(lsrs, 0800, fa30f000), \ | |
5807 | X(mov, 2000, ea4f0000), \ | |
5808 | X(movs, 2000, ea5f0000), \ | |
5809 | X(mul, 4340, fb00f000), \ | |
5810 | X(muls, 4340, ffffffff), /* no 32b muls */ \ | |
5811 | X(mvn, 43c0, ea6f0000), \ | |
5812 | X(mvns, 43c0, ea7f0000), \ | |
5813 | X(neg, 4240, f1c00000), /* rsb #0 */ \ | |
5814 | X(negs, 4240, f1d00000), /* rsbs #0 */ \ | |
5815 | X(orr, 4300, ea400000), \ | |
5816 | X(orrs, 4300, ea500000), \ | |
e9f89963 PB |
5817 | X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \ |
5818 | X(push, b400, e92d0000), /* stmdb sp!,... */ \ | |
c19d1205 ZW |
5819 | X(rev, ba00, fa90f080), \ |
5820 | X(rev16, ba40, fa90f090), \ | |
5821 | X(revsh, bac0, fa90f0b0), \ | |
5822 | X(ror, 41c0, fa60f000), \ | |
5823 | X(rors, 41c0, fa70f000), \ | |
5824 | X(sbc, 4180, eb600000), \ | |
5825 | X(sbcs, 4180, eb700000), \ | |
5826 | X(stmia, c000, e8800000), \ | |
5827 | X(str, 6000, f8400000), \ | |
5828 | X(strb, 7000, f8000000), \ | |
5829 | X(strh, 8000, f8200000), \ | |
0110f2b8 | 5830 | X(str_sp,9000, f84d0000), \ |
c19d1205 ZW |
5831 | X(sub, 1e00, eba00000), \ |
5832 | X(subs, 1e00, ebb00000), \ | |
0110f2b8 PB |
5833 | X(subi, 8000, f1a00000), \ |
5834 | X(subis, 8000, f1b00000), \ | |
c19d1205 ZW |
5835 | X(sxtb, b240, fa4ff080), \ |
5836 | X(sxth, b200, fa0ff080), \ | |
5837 | X(tst, 4200, ea100f00), \ | |
5838 | X(uxtb, b2c0, fa5ff080), \ | |
5839 | X(uxth, b280, fa1ff080), \ | |
5840 | X(nop, bf00, f3af8000), \ | |
5841 | X(yield, bf10, f3af8001), \ | |
5842 | X(wfe, bf20, f3af8002), \ | |
5843 | X(wfi, bf30, f3af8003), \ | |
5844 | X(sev, bf40, f3af9004), /* typo, 8004? */ | |
5845 | ||
5846 | /* To catch errors in encoding functions, the codes are all offset by | |
5847 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
5848 | as 16-bit instructions. */ | |
5849 | #define X(a,b,c) T_MNEM_##a | |
5850 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; | |
5851 | #undef X | |
5852 | ||
5853 | #define X(a,b,c) 0x##b | |
5854 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
5855 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
5856 | #undef X | |
5857 | ||
5858 | #define X(a,b,c) 0x##c | |
5859 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
5860 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) | |
5861 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
5862 | #undef X | |
5863 | #undef T16_32_TAB | |
5864 | ||
5865 | /* Thumb instruction encoders, in alphabetical order. */ | |
5866 | ||
92e90b6e PB |
5867 | /* ADDW or SUBW. */ |
5868 | static void | |
5869 | do_t_add_sub_w (void) | |
5870 | { | |
5871 | int Rd, Rn; | |
5872 | ||
5873 | Rd = inst.operands[0].reg; | |
5874 | Rn = inst.operands[1].reg; | |
5875 | ||
5876 | constraint (Rd == 15, _("PC not allowed as destination")); | |
5877 | inst.instruction |= (Rn << 16) | (Rd << 8); | |
5878 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
5879 | } | |
5880 | ||
c19d1205 ZW |
5881 | /* Parse an add or subtract instruction. We get here with inst.instruction |
5882 | equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ | |
5883 | ||
5884 | static void | |
5885 | do_t_add_sub (void) | |
5886 | { | |
5887 | int Rd, Rs, Rn; | |
5888 | ||
5889 | Rd = inst.operands[0].reg; | |
5890 | Rs = (inst.operands[1].present | |
5891 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
5892 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
5893 | ||
5894 | if (unified_syntax) | |
5895 | { | |
0110f2b8 PB |
5896 | bfd_boolean flags; |
5897 | bfd_boolean narrow; | |
5898 | int opcode; | |
5899 | ||
5900 | flags = (inst.instruction == T_MNEM_adds | |
5901 | || inst.instruction == T_MNEM_subs); | |
5902 | if (flags) | |
5903 | narrow = (current_it_mask == 0); | |
5904 | else | |
5905 | narrow = (current_it_mask != 0); | |
c19d1205 | 5906 | if (!inst.operands[2].isreg) |
b99bd4ef | 5907 | { |
0110f2b8 PB |
5908 | opcode = 0; |
5909 | if (inst.size_req != 4) | |
5910 | { | |
5911 | int add; | |
5912 | ||
5913 | add = (inst.instruction == T_MNEM_add | |
5914 | || inst.instruction == T_MNEM_adds); | |
5915 | /* Attempt to use a narrow opcode, with relaxation if | |
5916 | appropriate. */ | |
5917 | if (Rd == REG_SP && Rs == REG_SP && !flags) | |
5918 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
5919 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
5920 | opcode = T_MNEM_add_sp; | |
5921 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
5922 | opcode = T_MNEM_add_pc; | |
5923 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
5924 | { | |
5925 | if (flags) | |
5926 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
5927 | else | |
5928 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
5929 | } | |
5930 | if (opcode) | |
5931 | { | |
5932 | inst.instruction = THUMB_OP16(opcode); | |
5933 | inst.instruction |= (Rd << 4) | Rs; | |
5934 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
5935 | if (inst.size_req != 2) | |
5936 | inst.relax = opcode; | |
5937 | } | |
5938 | else | |
5939 | constraint (inst.size_req == 2, BAD_HIREG); | |
5940 | } | |
5941 | if (inst.size_req == 4 | |
5942 | || (inst.size_req != 2 && !opcode)) | |
5943 | { | |
5944 | /* ??? Convert large immediates to addw/subw. */ | |
5945 | inst.instruction = THUMB_OP32 (inst.instruction); | |
5946 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
5947 | inst.instruction |= inst.operands[0].reg << 8; | |
5948 | inst.instruction |= inst.operands[1].reg << 16; | |
5949 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
5950 | } | |
b99bd4ef | 5951 | } |
c19d1205 ZW |
5952 | else |
5953 | { | |
5954 | Rn = inst.operands[2].reg; | |
5955 | /* See if we can do this with a 16-bit instruction. */ | |
5956 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
5957 | { | |
e27ec89e PB |
5958 | if (Rd > 7 || Rs > 7 || Rn > 7) |
5959 | narrow = FALSE; | |
5960 | ||
5961 | if (narrow) | |
c19d1205 | 5962 | { |
e27ec89e PB |
5963 | inst.instruction = ((inst.instruction == T_MNEM_adds |
5964 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
5965 | ? T_OPCODE_ADD_R3 |
5966 | : T_OPCODE_SUB_R3); | |
5967 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
5968 | return; | |
5969 | } | |
b99bd4ef | 5970 | |
c19d1205 ZW |
5971 | if (inst.instruction == T_MNEM_add) |
5972 | { | |
5973 | if (Rd == Rs) | |
5974 | { | |
5975 | inst.instruction = T_OPCODE_ADD_HI; | |
5976 | inst.instruction |= (Rd & 8) << 4; | |
5977 | inst.instruction |= (Rd & 7); | |
5978 | inst.instruction |= Rn << 3; | |
5979 | return; | |
5980 | } | |
5981 | /* ... because addition is commutative! */ | |
5982 | else if (Rd == Rn) | |
5983 | { | |
5984 | inst.instruction = T_OPCODE_ADD_HI; | |
5985 | inst.instruction |= (Rd & 8) << 4; | |
5986 | inst.instruction |= (Rd & 7); | |
5987 | inst.instruction |= Rs << 3; | |
5988 | return; | |
5989 | } | |
5990 | } | |
5991 | } | |
5992 | /* If we get here, it can't be done in 16 bits. */ | |
5993 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
5994 | _("shift must be constant")); | |
5995 | inst.instruction = THUMB_OP32 (inst.instruction); | |
5996 | inst.instruction |= Rd << 8; | |
5997 | inst.instruction |= Rs << 16; | |
5998 | encode_thumb32_shifted_operand (2); | |
5999 | } | |
6000 | } | |
6001 | else | |
6002 | { | |
6003 | constraint (inst.instruction == T_MNEM_adds | |
6004 | || inst.instruction == T_MNEM_subs, | |
6005 | BAD_THUMB32); | |
b99bd4ef | 6006 | |
c19d1205 | 6007 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 6008 | { |
c19d1205 ZW |
6009 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
6010 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
6011 | BAD_HIREG); | |
6012 | ||
6013 | inst.instruction = (inst.instruction == T_MNEM_add | |
6014 | ? 0x0000 : 0x8000); | |
6015 | inst.instruction |= (Rd << 4) | Rs; | |
6016 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
6017 | return; |
6018 | } | |
6019 | ||
c19d1205 ZW |
6020 | Rn = inst.operands[2].reg; |
6021 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 6022 | |
c19d1205 ZW |
6023 | /* We now have Rd, Rs, and Rn set to registers. */ |
6024 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 6025 | { |
c19d1205 ZW |
6026 | /* Can't do this for SUB. */ |
6027 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
6028 | inst.instruction = T_OPCODE_ADD_HI; | |
6029 | inst.instruction |= (Rd & 8) << 4; | |
6030 | inst.instruction |= (Rd & 7); | |
6031 | if (Rs == Rd) | |
6032 | inst.instruction |= Rn << 3; | |
6033 | else if (Rn == Rd) | |
6034 | inst.instruction |= Rs << 3; | |
6035 | else | |
6036 | constraint (1, _("dest must overlap one source register")); | |
6037 | } | |
6038 | else | |
6039 | { | |
6040 | inst.instruction = (inst.instruction == T_MNEM_add | |
6041 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
6042 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 6043 | } |
b99bd4ef | 6044 | } |
b99bd4ef NC |
6045 | } |
6046 | ||
c19d1205 ZW |
6047 | static void |
6048 | do_t_adr (void) | |
6049 | { | |
0110f2b8 PB |
6050 | if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7) |
6051 | { | |
6052 | /* Defer to section relaxation. */ | |
6053 | inst.relax = inst.instruction; | |
6054 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6055 | inst.instruction |= inst.operands[0].reg << 4; | |
6056 | } | |
6057 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 6058 | { |
0110f2b8 | 6059 | /* Generate a 32-bit opcode. */ |
e9f89963 PB |
6060 | inst.instruction = THUMB_OP32 (inst.instruction); |
6061 | inst.instruction |= inst.operands[0].reg << 8; | |
6062 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; | |
6063 | inst.reloc.pc_rel = 1; | |
6064 | } | |
6065 | else | |
6066 | { | |
0110f2b8 | 6067 | /* Generate a 16-bit opcode. */ |
e9f89963 PB |
6068 | inst.instruction = THUMB_OP16 (inst.instruction); |
6069 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
6070 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
6071 | inst.reloc.pc_rel = 1; | |
b99bd4ef | 6072 | |
e9f89963 PB |
6073 | inst.instruction |= inst.operands[0].reg << 4; |
6074 | } | |
c19d1205 | 6075 | } |
b99bd4ef | 6076 | |
c19d1205 ZW |
6077 | /* Arithmetic instructions for which there is just one 16-bit |
6078 | instruction encoding, and it allows only two low registers. | |
6079 | For maximal compatibility with ARM syntax, we allow three register | |
6080 | operands even when Thumb-32 instructions are not available, as long | |
6081 | as the first two are identical. For instance, both "sbc r0,r1" and | |
6082 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 6083 | static void |
c19d1205 | 6084 | do_t_arit3 (void) |
b99bd4ef | 6085 | { |
c19d1205 | 6086 | int Rd, Rs, Rn; |
b99bd4ef | 6087 | |
c19d1205 ZW |
6088 | Rd = inst.operands[0].reg; |
6089 | Rs = (inst.operands[1].present | |
6090 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
6091 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
6092 | Rn = inst.operands[2].reg; | |
b99bd4ef | 6093 | |
c19d1205 | 6094 | if (unified_syntax) |
b99bd4ef | 6095 | { |
c19d1205 ZW |
6096 | if (!inst.operands[2].isreg) |
6097 | { | |
6098 | /* For an immediate, we always generate a 32-bit opcode; | |
6099 | section relaxation will shrink it later if possible. */ | |
6100 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6101 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
6102 | inst.instruction |= Rd << 8; | |
6103 | inst.instruction |= Rs << 16; | |
6104 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
6105 | } | |
6106 | else | |
6107 | { | |
e27ec89e PB |
6108 | bfd_boolean narrow; |
6109 | ||
c19d1205 | 6110 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e PB |
6111 | if (THUMB_SETS_FLAGS (inst.instruction)) |
6112 | narrow = current_it_mask == 0; | |
6113 | else | |
6114 | narrow = current_it_mask != 0; | |
6115 | ||
6116 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
6117 | narrow = FALSE; | |
6118 | if (inst.operands[2].shifted) | |
6119 | narrow = FALSE; | |
6120 | if (inst.size_req == 4) | |
6121 | narrow = FALSE; | |
6122 | ||
6123 | if (narrow | |
c19d1205 ZW |
6124 | && Rd == Rs) |
6125 | { | |
6126 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6127 | inst.instruction |= Rd; | |
6128 | inst.instruction |= Rn << 3; | |
6129 | return; | |
6130 | } | |
b99bd4ef | 6131 | |
c19d1205 ZW |
6132 | /* If we get here, it can't be done in 16 bits. */ |
6133 | constraint (inst.operands[2].shifted | |
6134 | && inst.operands[2].immisreg, | |
6135 | _("shift must be constant")); | |
6136 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6137 | inst.instruction |= Rd << 8; | |
6138 | inst.instruction |= Rs << 16; | |
6139 | encode_thumb32_shifted_operand (2); | |
6140 | } | |
a737bd4d | 6141 | } |
c19d1205 | 6142 | else |
b99bd4ef | 6143 | { |
c19d1205 ZW |
6144 | /* On its face this is a lie - the instruction does set the |
6145 | flags. However, the only supported mnemonic in this mode | |
6146 | says it doesn't. */ | |
6147 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 6148 | |
c19d1205 ZW |
6149 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
6150 | _("unshifted register required")); | |
6151 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
6152 | constraint (Rd != Rs, | |
6153 | _("dest and source1 must be the same register")); | |
a737bd4d | 6154 | |
c19d1205 ZW |
6155 | inst.instruction = THUMB_OP16 (inst.instruction); |
6156 | inst.instruction |= Rd; | |
6157 | inst.instruction |= Rn << 3; | |
b99bd4ef | 6158 | } |
a737bd4d | 6159 | } |
b99bd4ef | 6160 | |
c19d1205 ZW |
6161 | /* Similarly, but for instructions where the arithmetic operation is |
6162 | commutative, so we can allow either of them to be different from | |
6163 | the destination operand in a 16-bit instruction. For instance, all | |
6164 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
6165 | accepted. */ | |
6166 | static void | |
6167 | do_t_arit3c (void) | |
a737bd4d | 6168 | { |
c19d1205 | 6169 | int Rd, Rs, Rn; |
b99bd4ef | 6170 | |
c19d1205 ZW |
6171 | Rd = inst.operands[0].reg; |
6172 | Rs = (inst.operands[1].present | |
6173 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
6174 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
6175 | Rn = inst.operands[2].reg; | |
a737bd4d | 6176 | |
c19d1205 | 6177 | if (unified_syntax) |
a737bd4d | 6178 | { |
c19d1205 | 6179 | if (!inst.operands[2].isreg) |
b99bd4ef | 6180 | { |
c19d1205 ZW |
6181 | /* For an immediate, we always generate a 32-bit opcode; |
6182 | section relaxation will shrink it later if possible. */ | |
6183 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6184 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
6185 | inst.instruction |= Rd << 8; | |
6186 | inst.instruction |= Rs << 16; | |
6187 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 6188 | } |
c19d1205 | 6189 | else |
a737bd4d | 6190 | { |
e27ec89e PB |
6191 | bfd_boolean narrow; |
6192 | ||
c19d1205 | 6193 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e PB |
6194 | if (THUMB_SETS_FLAGS (inst.instruction)) |
6195 | narrow = current_it_mask == 0; | |
6196 | else | |
6197 | narrow = current_it_mask != 0; | |
6198 | ||
6199 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
6200 | narrow = FALSE; | |
6201 | if (inst.operands[2].shifted) | |
6202 | narrow = FALSE; | |
6203 | if (inst.size_req == 4) | |
6204 | narrow = FALSE; | |
6205 | ||
6206 | if (narrow) | |
a737bd4d | 6207 | { |
c19d1205 | 6208 | if (Rd == Rs) |
a737bd4d | 6209 | { |
c19d1205 ZW |
6210 | inst.instruction = THUMB_OP16 (inst.instruction); |
6211 | inst.instruction |= Rd; | |
6212 | inst.instruction |= Rn << 3; | |
6213 | return; | |
a737bd4d | 6214 | } |
c19d1205 | 6215 | if (Rd == Rn) |
a737bd4d | 6216 | { |
c19d1205 ZW |
6217 | inst.instruction = THUMB_OP16 (inst.instruction); |
6218 | inst.instruction |= Rd; | |
6219 | inst.instruction |= Rs << 3; | |
6220 | return; | |
a737bd4d NC |
6221 | } |
6222 | } | |
c19d1205 ZW |
6223 | |
6224 | /* If we get here, it can't be done in 16 bits. */ | |
6225 | constraint (inst.operands[2].shifted | |
6226 | && inst.operands[2].immisreg, | |
6227 | _("shift must be constant")); | |
6228 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6229 | inst.instruction |= Rd << 8; | |
6230 | inst.instruction |= Rs << 16; | |
6231 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 6232 | } |
b99bd4ef | 6233 | } |
c19d1205 ZW |
6234 | else |
6235 | { | |
6236 | /* On its face this is a lie - the instruction does set the | |
6237 | flags. However, the only supported mnemonic in this mode | |
6238 | says it doesn't. */ | |
6239 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 6240 | |
c19d1205 ZW |
6241 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
6242 | _("unshifted register required")); | |
6243 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
6244 | ||
6245 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6246 | inst.instruction |= Rd; | |
6247 | ||
6248 | if (Rd == Rs) | |
6249 | inst.instruction |= Rn << 3; | |
6250 | else if (Rd == Rn) | |
6251 | inst.instruction |= Rs << 3; | |
6252 | else | |
6253 | constraint (1, _("dest must overlap one source register")); | |
6254 | } | |
a737bd4d NC |
6255 | } |
6256 | ||
c19d1205 ZW |
6257 | static void |
6258 | do_t_bfc (void) | |
a737bd4d | 6259 | { |
c19d1205 ZW |
6260 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
6261 | constraint (msb > 32, _("bit-field extends past end of register")); | |
6262 | /* The instruction encoding stores the LSB and MSB, | |
6263 | not the LSB and width. */ | |
6264 | inst.instruction |= inst.operands[0].reg << 8; | |
6265 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; | |
6266 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
6267 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
6268 | } |
6269 | ||
c19d1205 ZW |
6270 | static void |
6271 | do_t_bfi (void) | |
b99bd4ef | 6272 | { |
c19d1205 | 6273 | unsigned int msb; |
b99bd4ef | 6274 | |
c19d1205 ZW |
6275 | /* #0 in second position is alternative syntax for bfc, which is |
6276 | the same instruction but with REG_PC in the Rm field. */ | |
6277 | if (!inst.operands[1].isreg) | |
6278 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 6279 | |
c19d1205 ZW |
6280 | msb = inst.operands[2].imm + inst.operands[3].imm; |
6281 | constraint (msb > 32, _("bit-field extends past end of register")); | |
6282 | /* The instruction encoding stores the LSB and MSB, | |
6283 | not the LSB and width. */ | |
6284 | inst.instruction |= inst.operands[0].reg << 8; | |
6285 | inst.instruction |= inst.operands[1].reg << 16; | |
6286 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; | |
6287 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
6288 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
6289 | } |
6290 | ||
c19d1205 ZW |
6291 | static void |
6292 | do_t_bfx (void) | |
b99bd4ef | 6293 | { |
c19d1205 ZW |
6294 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
6295 | _("bit-field extends past end of register")); | |
6296 | inst.instruction |= inst.operands[0].reg << 8; | |
6297 | inst.instruction |= inst.operands[1].reg << 16; | |
6298 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; | |
6299 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
6300 | inst.instruction |= inst.operands[3].imm - 1; | |
6301 | } | |
b99bd4ef | 6302 | |
c19d1205 ZW |
6303 | /* ARM V5 Thumb BLX (argument parse) |
6304 | BLX <target_addr> which is BLX(1) | |
6305 | BLX <Rm> which is BLX(2) | |
6306 | Unfortunately, there are two different opcodes for this mnemonic. | |
6307 | So, the insns[].value is not used, and the code here zaps values | |
6308 | into inst.instruction. | |
b99bd4ef | 6309 | |
c19d1205 ZW |
6310 | ??? How to take advantage of the additional two bits of displacement |
6311 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 6312 | |
c19d1205 ZW |
6313 | static void |
6314 | do_t_blx (void) | |
6315 | { | |
6316 | if (inst.operands[0].isreg) | |
6317 | /* We have a register, so this is BLX(2). */ | |
6318 | inst.instruction |= inst.operands[0].reg << 3; | |
b99bd4ef NC |
6319 | else |
6320 | { | |
c19d1205 | 6321 | /* No register. This must be BLX(1). */ |
2fc8bdac | 6322 | inst.instruction = 0xf000e800; |
c19d1205 ZW |
6323 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; |
6324 | inst.reloc.pc_rel = 1; | |
b99bd4ef NC |
6325 | } |
6326 | } | |
6327 | ||
c19d1205 ZW |
6328 | static void |
6329 | do_t_branch (void) | |
b99bd4ef | 6330 | { |
0110f2b8 PB |
6331 | int opcode; |
6332 | if (inst.cond != COND_ALWAYS) | |
6333 | opcode = T_MNEM_bcond; | |
6334 | else | |
6335 | opcode = inst.instruction; | |
6336 | ||
6337 | if (unified_syntax && inst.size_req == 4) | |
c19d1205 | 6338 | { |
0110f2b8 | 6339 | inst.instruction = THUMB_OP32(opcode); |
c19d1205 | 6340 | if (inst.cond == COND_ALWAYS) |
0110f2b8 | 6341 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
6342 | else |
6343 | { | |
6344 | assert (inst.cond != 0xF); | |
0110f2b8 | 6345 | inst.instruction |= inst.cond << 22; |
c19d1205 ZW |
6346 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20; |
6347 | } | |
6348 | } | |
b99bd4ef NC |
6349 | else |
6350 | { | |
0110f2b8 | 6351 | inst.instruction = THUMB_OP16(opcode); |
c19d1205 ZW |
6352 | if (inst.cond == COND_ALWAYS) |
6353 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
6354 | else | |
b99bd4ef | 6355 | { |
0110f2b8 | 6356 | inst.instruction |= inst.cond << 8; |
c19d1205 | 6357 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 6358 | } |
0110f2b8 PB |
6359 | /* Allow section relaxation. */ |
6360 | if (unified_syntax && inst.size_req != 2) | |
6361 | inst.relax = opcode; | |
b99bd4ef | 6362 | } |
c19d1205 ZW |
6363 | |
6364 | inst.reloc.pc_rel = 1; | |
b99bd4ef NC |
6365 | } |
6366 | ||
6367 | static void | |
c19d1205 | 6368 | do_t_bkpt (void) |
b99bd4ef | 6369 | { |
c19d1205 | 6370 | if (inst.operands[0].present) |
b99bd4ef | 6371 | { |
c19d1205 ZW |
6372 | constraint (inst.operands[0].imm > 255, |
6373 | _("immediate value out of range")); | |
6374 | inst.instruction |= inst.operands[0].imm; | |
b99bd4ef | 6375 | } |
b99bd4ef NC |
6376 | } |
6377 | ||
6378 | static void | |
c19d1205 | 6379 | do_t_branch23 (void) |
b99bd4ef | 6380 | { |
c19d1205 | 6381 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; |
90e4755a RE |
6382 | inst.reloc.pc_rel = 1; |
6383 | ||
c19d1205 ZW |
6384 | /* If the destination of the branch is a defined symbol which does not have |
6385 | the THUMB_FUNC attribute, then we must be calling a function which has | |
6386 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
6387 | function and change the branch to refer to that function instead. */ | |
6388 | if ( inst.reloc.exp.X_op == O_symbol | |
6389 | && inst.reloc.exp.X_add_symbol != NULL | |
6390 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
6391 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
6392 | inst.reloc.exp.X_add_symbol = | |
6393 | find_real_start (inst.reloc.exp.X_add_symbol); | |
90e4755a RE |
6394 | } |
6395 | ||
6396 | static void | |
c19d1205 | 6397 | do_t_bx (void) |
90e4755a | 6398 | { |
c19d1205 ZW |
6399 | inst.instruction |= inst.operands[0].reg << 3; |
6400 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
6401 | should cause the alignment to be checked once it is known. This is | |
6402 | because BX PC only works if the instruction is word aligned. */ | |
6403 | } | |
90e4755a | 6404 | |
c19d1205 ZW |
6405 | static void |
6406 | do_t_bxj (void) | |
6407 | { | |
6408 | if (inst.operands[0].reg == REG_PC) | |
6409 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
90e4755a | 6410 | |
c19d1205 | 6411 | inst.instruction |= inst.operands[0].reg << 16; |
90e4755a RE |
6412 | } |
6413 | ||
6414 | static void | |
c19d1205 | 6415 | do_t_clz (void) |
90e4755a | 6416 | { |
c19d1205 ZW |
6417 | inst.instruction |= inst.operands[0].reg << 8; |
6418 | inst.instruction |= inst.operands[1].reg << 16; | |
6419 | inst.instruction |= inst.operands[1].reg; | |
6420 | } | |
90e4755a | 6421 | |
c19d1205 ZW |
6422 | static void |
6423 | do_t_cpsi (void) | |
6424 | { | |
6425 | if (unified_syntax | |
6426 | && (inst.operands[1].present || inst.size_req == 4)) | |
90e4755a | 6427 | { |
c19d1205 ZW |
6428 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
6429 | inst.instruction = 0xf3af8000; | |
6430 | inst.instruction |= imod << 9; | |
6431 | inst.instruction |= inst.operands[0].imm << 5; | |
6432 | if (inst.operands[1].present) | |
6433 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 6434 | } |
c19d1205 | 6435 | else |
90e4755a | 6436 | { |
c19d1205 ZW |
6437 | constraint (inst.operands[1].present, |
6438 | _("Thumb does not support the 2-argument " | |
6439 | "form of this instruction")); | |
6440 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 6441 | } |
90e4755a RE |
6442 | } |
6443 | ||
c19d1205 ZW |
6444 | /* THUMB CPY instruction (argument parse). */ |
6445 | ||
90e4755a | 6446 | static void |
c19d1205 | 6447 | do_t_cpy (void) |
90e4755a | 6448 | { |
c19d1205 | 6449 | if (inst.size_req == 4) |
90e4755a | 6450 | { |
c19d1205 ZW |
6451 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
6452 | inst.instruction |= inst.operands[0].reg << 8; | |
6453 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 6454 | } |
c19d1205 | 6455 | else |
90e4755a | 6456 | { |
c19d1205 ZW |
6457 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
6458 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
6459 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 6460 | } |
90e4755a RE |
6461 | } |
6462 | ||
90e4755a | 6463 | static void |
c19d1205 | 6464 | do_t_czb (void) |
90e4755a | 6465 | { |
c19d1205 ZW |
6466 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
6467 | inst.instruction |= inst.operands[0].reg; | |
6468 | inst.reloc.pc_rel = 1; | |
6469 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
6470 | } | |
90e4755a | 6471 | |
c19d1205 ZW |
6472 | static void |
6473 | do_t_hint (void) | |
6474 | { | |
6475 | if (unified_syntax && inst.size_req == 4) | |
6476 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6477 | else | |
6478 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6479 | } | |
90e4755a | 6480 | |
c19d1205 ZW |
6481 | static void |
6482 | do_t_it (void) | |
6483 | { | |
6484 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e PB |
6485 | |
6486 | current_it_mask = (inst.instruction & 0xf) | 0x10; | |
6487 | current_cc = cond; | |
6488 | ||
6489 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 6490 | if ((cond & 0x1) == 0x0) |
90e4755a | 6491 | { |
c19d1205 | 6492 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 6493 | |
c19d1205 ZW |
6494 | if ((mask & 0x7) == 0) |
6495 | /* no conversion needed */; | |
6496 | else if ((mask & 0x3) == 0) | |
e27ec89e PB |
6497 | mask ^= 0x8; |
6498 | else if ((mask & 0x1) == 0) | |
6499 | mask ^= 0xC; | |
c19d1205 | 6500 | else |
e27ec89e | 6501 | mask ^= 0xE; |
90e4755a | 6502 | |
e27ec89e PB |
6503 | inst.instruction &= 0xfff0; |
6504 | inst.instruction |= mask; | |
c19d1205 | 6505 | } |
90e4755a | 6506 | |
c19d1205 ZW |
6507 | inst.instruction |= cond << 4; |
6508 | } | |
90e4755a | 6509 | |
c19d1205 ZW |
6510 | static void |
6511 | do_t_ldmstm (void) | |
6512 | { | |
6513 | /* This really doesn't seem worth it. */ | |
6514 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
6515 | _("expression too complex")); | |
6516 | constraint (inst.operands[1].writeback, | |
6517 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 6518 | |
c19d1205 ZW |
6519 | if (unified_syntax) |
6520 | { | |
6521 | /* See if we can use a 16-bit instruction. */ | |
6522 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
6523 | && inst.size_req != 4 | |
6524 | && inst.operands[0].reg <= 7 | |
6525 | && !(inst.operands[1].imm & ~0xff) | |
6526 | && (inst.instruction == T_MNEM_stmia | |
6527 | ? inst.operands[0].writeback | |
6528 | : (inst.operands[0].writeback | |
6529 | == !(inst.operands[1].imm & (1 << inst.operands[0].reg))))) | |
90e4755a | 6530 | { |
c19d1205 ZW |
6531 | if (inst.instruction == T_MNEM_stmia |
6532 | && (inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
6533 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
6534 | as_warn (_("value stored for r%d is UNPREDICTABLE"), | |
6535 | inst.operands[0].reg); | |
90e4755a | 6536 | |
c19d1205 ZW |
6537 | inst.instruction = THUMB_OP16 (inst.instruction); |
6538 | inst.instruction |= inst.operands[0].reg << 8; | |
6539 | inst.instruction |= inst.operands[1].imm; | |
6540 | } | |
6541 | else | |
6542 | { | |
6543 | if (inst.operands[1].imm & (1 << 13)) | |
6544 | as_warn (_("SP should not be in register list")); | |
6545 | if (inst.instruction == T_MNEM_stmia) | |
90e4755a | 6546 | { |
c19d1205 ZW |
6547 | if (inst.operands[1].imm & (1 << 15)) |
6548 | as_warn (_("PC should not be in register list")); | |
6549 | if (inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
6550 | as_warn (_("value stored for r%d is UNPREDICTABLE"), | |
6551 | inst.operands[0].reg); | |
90e4755a RE |
6552 | } |
6553 | else | |
6554 | { | |
c19d1205 ZW |
6555 | if (inst.operands[1].imm & (1 << 14) |
6556 | && inst.operands[1].imm & (1 << 15)) | |
6557 | as_warn (_("LR and PC should not both be in register list")); | |
6558 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
6559 | && inst.operands[0].writeback) | |
6560 | as_warn (_("base register should not be in register list " | |
6561 | "when written back")); | |
90e4755a | 6562 | } |
c19d1205 ZW |
6563 | if (inst.instruction < 0xffff) |
6564 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6565 | inst.instruction |= inst.operands[0].reg << 16; | |
6566 | inst.instruction |= inst.operands[1].imm; | |
6567 | if (inst.operands[0].writeback) | |
6568 | inst.instruction |= WRITE_BACK; | |
90e4755a RE |
6569 | } |
6570 | } | |
c19d1205 | 6571 | else |
90e4755a | 6572 | { |
c19d1205 ZW |
6573 | constraint (inst.operands[0].reg > 7 |
6574 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
6575 | if (inst.instruction == T_MNEM_stmia) | |
f03698e6 | 6576 | { |
c19d1205 ZW |
6577 | if (!inst.operands[0].writeback) |
6578 | as_warn (_("this instruction will write back the base register")); | |
6579 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
6580 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
6581 | as_warn (_("value stored for r%d is UNPREDICTABLE"), | |
6582 | inst.operands[0].reg); | |
f03698e6 | 6583 | } |
c19d1205 | 6584 | else |
90e4755a | 6585 | { |
c19d1205 ZW |
6586 | if (!inst.operands[0].writeback |
6587 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
6588 | as_warn (_("this instruction will write back the base register")); | |
6589 | else if (inst.operands[0].writeback | |
6590 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
6591 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
6592 | } |
6593 | ||
c19d1205 ZW |
6594 | inst.instruction = THUMB_OP16 (inst.instruction); |
6595 | inst.instruction |= inst.operands[0].reg << 8; | |
6596 | inst.instruction |= inst.operands[1].imm; | |
6597 | } | |
6598 | } | |
e28cd48c | 6599 | |
c19d1205 ZW |
6600 | static void |
6601 | do_t_ldrex (void) | |
6602 | { | |
6603 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
6604 | || inst.operands[1].postind || inst.operands[1].writeback | |
6605 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
6606 | || inst.operands[1].negative, | |
6607 | _("instruction does not accept this addressing mode")); | |
e28cd48c | 6608 | |
c19d1205 ZW |
6609 | inst.instruction |= inst.operands[0].reg << 12; |
6610 | inst.instruction |= inst.operands[1].reg << 16; | |
6611 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
6612 | } | |
e28cd48c | 6613 | |
c19d1205 ZW |
6614 | static void |
6615 | do_t_ldrexd (void) | |
6616 | { | |
6617 | if (!inst.operands[1].present) | |
1cac9012 | 6618 | { |
c19d1205 ZW |
6619 | constraint (inst.operands[0].reg == REG_LR, |
6620 | _("r14 not allowed as first register " | |
6621 | "when second register is omitted")); | |
6622 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 6623 | } |
c19d1205 ZW |
6624 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
6625 | BAD_OVERLAP); | |
b99bd4ef | 6626 | |
c19d1205 ZW |
6627 | inst.instruction |= inst.operands[0].reg << 12; |
6628 | inst.instruction |= inst.operands[1].reg << 8; | |
6629 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
6630 | } |
6631 | ||
6632 | static void | |
c19d1205 | 6633 | do_t_ldst (void) |
b99bd4ef | 6634 | { |
0110f2b8 PB |
6635 | unsigned long opcode; |
6636 | int Rn; | |
6637 | ||
6638 | opcode = inst.instruction; | |
c19d1205 | 6639 | if (unified_syntax) |
b99bd4ef | 6640 | { |
0110f2b8 PB |
6641 | if (inst.operands[1].isreg |
6642 | && !inst.operands[1].writeback | |
c19d1205 ZW |
6643 | && !inst.operands[1].shifted && !inst.operands[1].postind |
6644 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
6645 | && opcode <= 0xffff |
6646 | && inst.size_req != 4) | |
c19d1205 | 6647 | { |
0110f2b8 PB |
6648 | /* Insn may have a 16-bit form. */ |
6649 | Rn = inst.operands[1].reg; | |
6650 | if (inst.operands[1].immisreg) | |
6651 | { | |
6652 | inst.instruction = THUMB_OP16 (opcode); | |
6653 | /* [Rn, Ri] */ | |
6654 | if (Rn <= 7 && inst.operands[1].imm <= 7) | |
6655 | goto op16; | |
6656 | } | |
6657 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
6658 | && opcode != T_MNEM_ldrsb) | |
6659 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
6660 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
6661 | { | |
6662 | /* [Rn, #const] */ | |
6663 | if (Rn > 7) | |
6664 | { | |
6665 | if (Rn == REG_PC) | |
6666 | { | |
6667 | if (inst.reloc.pc_rel) | |
6668 | opcode = T_MNEM_ldr_pc2; | |
6669 | else | |
6670 | opcode = T_MNEM_ldr_pc; | |
6671 | } | |
6672 | else | |
6673 | { | |
6674 | if (opcode == T_MNEM_ldr) | |
6675 | opcode = T_MNEM_ldr_sp; | |
6676 | else | |
6677 | opcode = T_MNEM_str_sp; | |
6678 | } | |
6679 | inst.instruction = inst.operands[0].reg << 8; | |
6680 | } | |
6681 | else | |
6682 | { | |
6683 | inst.instruction = inst.operands[0].reg; | |
6684 | inst.instruction |= inst.operands[1].reg << 3; | |
6685 | } | |
6686 | inst.instruction |= THUMB_OP16 (opcode); | |
6687 | if (inst.size_req == 2) | |
6688 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
6689 | else | |
6690 | inst.relax = opcode; | |
6691 | return; | |
6692 | } | |
c19d1205 | 6693 | } |
0110f2b8 PB |
6694 | /* Definitely a 32-bit variant. */ |
6695 | inst.instruction = THUMB_OP32 (opcode); | |
c19d1205 ZW |
6696 | inst.instruction |= inst.operands[0].reg << 12; |
6697 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
b99bd4ef NC |
6698 | return; |
6699 | } | |
6700 | ||
c19d1205 ZW |
6701 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
6702 | ||
6703 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 6704 | { |
c19d1205 ZW |
6705 | /* Only [Rn,Rm] is acceptable. */ |
6706 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
6707 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
6708 | || inst.operands[1].postind || inst.operands[1].shifted | |
6709 | || inst.operands[1].negative, | |
6710 | _("Thumb does not support this addressing mode")); | |
6711 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6712 | goto op16; | |
b99bd4ef | 6713 | } |
c19d1205 ZW |
6714 | |
6715 | inst.instruction = THUMB_OP16 (inst.instruction); | |
6716 | if (!inst.operands[1].isreg) | |
6717 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
6718 | return; | |
b99bd4ef | 6719 | |
c19d1205 ZW |
6720 | constraint (!inst.operands[1].preind |
6721 | || inst.operands[1].shifted | |
6722 | || inst.operands[1].writeback, | |
6723 | _("Thumb does not support this addressing mode")); | |
6724 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 6725 | { |
c19d1205 ZW |
6726 | constraint (inst.instruction & 0x0600, |
6727 | _("byte or halfword not valid for base register")); | |
6728 | constraint (inst.operands[1].reg == REG_PC | |
6729 | && !(inst.instruction & THUMB_LOAD_BIT), | |
6730 | _("r15 based store not allowed")); | |
6731 | constraint (inst.operands[1].immisreg, | |
6732 | _("invalid base register for register offset")); | |
b99bd4ef | 6733 | |
c19d1205 ZW |
6734 | if (inst.operands[1].reg == REG_PC) |
6735 | inst.instruction = T_OPCODE_LDR_PC; | |
6736 | else if (inst.instruction & THUMB_LOAD_BIT) | |
6737 | inst.instruction = T_OPCODE_LDR_SP; | |
6738 | else | |
6739 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 6740 | |
c19d1205 ZW |
6741 | inst.instruction |= inst.operands[0].reg << 8; |
6742 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
6743 | return; | |
6744 | } | |
90e4755a | 6745 | |
c19d1205 ZW |
6746 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
6747 | if (!inst.operands[1].immisreg) | |
6748 | { | |
6749 | /* Immediate offset. */ | |
6750 | inst.instruction |= inst.operands[0].reg; | |
6751 | inst.instruction |= inst.operands[1].reg << 3; | |
6752 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
6753 | return; | |
6754 | } | |
90e4755a | 6755 | |
c19d1205 ZW |
6756 | /* Register offset. */ |
6757 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
6758 | constraint (inst.operands[1].negative, | |
6759 | _("Thumb does not support this addressing mode")); | |
90e4755a | 6760 | |
c19d1205 ZW |
6761 | op16: |
6762 | switch (inst.instruction) | |
6763 | { | |
6764 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
6765 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
6766 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
6767 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
6768 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
6769 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
6770 | case 0x5600 /* ldrsb */: | |
6771 | case 0x5e00 /* ldrsh */: break; | |
6772 | default: abort (); | |
6773 | } | |
90e4755a | 6774 | |
c19d1205 ZW |
6775 | inst.instruction |= inst.operands[0].reg; |
6776 | inst.instruction |= inst.operands[1].reg << 3; | |
6777 | inst.instruction |= inst.operands[1].imm << 6; | |
6778 | } | |
90e4755a | 6779 | |
c19d1205 ZW |
6780 | static void |
6781 | do_t_ldstd (void) | |
6782 | { | |
6783 | if (!inst.operands[1].present) | |
b99bd4ef | 6784 | { |
c19d1205 ZW |
6785 | inst.operands[1].reg = inst.operands[0].reg + 1; |
6786 | constraint (inst.operands[0].reg == REG_LR, | |
6787 | _("r14 not allowed here")); | |
b99bd4ef | 6788 | } |
c19d1205 ZW |
6789 | inst.instruction |= inst.operands[0].reg << 12; |
6790 | inst.instruction |= inst.operands[1].reg << 8; | |
6791 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
6792 | ||
b99bd4ef NC |
6793 | } |
6794 | ||
c19d1205 ZW |
6795 | static void |
6796 | do_t_ldstt (void) | |
6797 | { | |
6798 | inst.instruction |= inst.operands[0].reg << 12; | |
6799 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
6800 | } | |
a737bd4d | 6801 | |
b99bd4ef | 6802 | static void |
c19d1205 | 6803 | do_t_mla (void) |
b99bd4ef | 6804 | { |
c19d1205 ZW |
6805 | inst.instruction |= inst.operands[0].reg << 8; |
6806 | inst.instruction |= inst.operands[1].reg << 16; | |
6807 | inst.instruction |= inst.operands[2].reg; | |
6808 | inst.instruction |= inst.operands[3].reg << 12; | |
6809 | } | |
b99bd4ef | 6810 | |
c19d1205 ZW |
6811 | static void |
6812 | do_t_mlal (void) | |
6813 | { | |
6814 | inst.instruction |= inst.operands[0].reg << 12; | |
6815 | inst.instruction |= inst.operands[1].reg << 8; | |
6816 | inst.instruction |= inst.operands[2].reg << 16; | |
6817 | inst.instruction |= inst.operands[3].reg; | |
6818 | } | |
b99bd4ef | 6819 | |
c19d1205 ZW |
6820 | static void |
6821 | do_t_mov_cmp (void) | |
6822 | { | |
6823 | if (unified_syntax) | |
b99bd4ef | 6824 | { |
c19d1205 ZW |
6825 | int r0off = (inst.instruction == T_MNEM_mov |
6826 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 6827 | unsigned long opcode; |
3d388997 PB |
6828 | bfd_boolean narrow; |
6829 | bfd_boolean low_regs; | |
6830 | ||
6831 | low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7); | |
0110f2b8 | 6832 | opcode = inst.instruction; |
3d388997 | 6833 | if (current_it_mask) |
0110f2b8 | 6834 | narrow = opcode != T_MNEM_movs; |
3d388997 | 6835 | else |
0110f2b8 | 6836 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
6837 | if (inst.size_req == 4 |
6838 | || inst.operands[1].shifted) | |
6839 | narrow = FALSE; | |
6840 | ||
c19d1205 ZW |
6841 | if (!inst.operands[1].isreg) |
6842 | { | |
0110f2b8 PB |
6843 | /* Immediate operand. */ |
6844 | if (current_it_mask == 0 && opcode == T_MNEM_mov) | |
6845 | narrow = 0; | |
6846 | if (low_regs && narrow) | |
6847 | { | |
6848 | inst.instruction = THUMB_OP16 (opcode); | |
6849 | inst.instruction |= inst.operands[0].reg << 8; | |
6850 | if (inst.size_req == 2) | |
6851 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
6852 | else | |
6853 | inst.relax = opcode; | |
6854 | } | |
6855 | else | |
6856 | { | |
6857 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6858 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
6859 | inst.instruction |= inst.operands[0].reg << r0off; | |
6860 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
6861 | } | |
c19d1205 | 6862 | } |
3d388997 | 6863 | else if (!narrow) |
c19d1205 ZW |
6864 | { |
6865 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6866 | inst.instruction |= inst.operands[0].reg << r0off; | |
6867 | encode_thumb32_shifted_operand (1); | |
6868 | } | |
6869 | else | |
6870 | switch (inst.instruction) | |
6871 | { | |
6872 | case T_MNEM_mov: | |
6873 | inst.instruction = T_OPCODE_MOV_HR; | |
6874 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; | |
6875 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
6876 | inst.instruction |= inst.operands[1].reg << 3; | |
6877 | break; | |
b99bd4ef | 6878 | |
c19d1205 ZW |
6879 | case T_MNEM_movs: |
6880 | /* We know we have low registers at this point. | |
6881 | Generate ADD Rd, Rs, #0. */ | |
6882 | inst.instruction = T_OPCODE_ADD_I3; | |
6883 | inst.instruction |= inst.operands[0].reg; | |
6884 | inst.instruction |= inst.operands[1].reg << 3; | |
6885 | break; | |
6886 | ||
6887 | case T_MNEM_cmp: | |
3d388997 | 6888 | if (low_regs) |
c19d1205 ZW |
6889 | { |
6890 | inst.instruction = T_OPCODE_CMP_LR; | |
6891 | inst.instruction |= inst.operands[0].reg; | |
6892 | inst.instruction |= inst.operands[1].reg << 3; | |
6893 | } | |
6894 | else | |
6895 | { | |
6896 | inst.instruction = T_OPCODE_CMP_HR; | |
6897 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; | |
6898 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
6899 | inst.instruction |= inst.operands[1].reg << 3; | |
6900 | } | |
6901 | break; | |
6902 | } | |
b99bd4ef NC |
6903 | return; |
6904 | } | |
6905 | ||
c19d1205 ZW |
6906 | inst.instruction = THUMB_OP16 (inst.instruction); |
6907 | if (inst.operands[1].isreg) | |
b99bd4ef | 6908 | { |
c19d1205 | 6909 | if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8) |
b99bd4ef | 6910 | { |
c19d1205 ZW |
6911 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
6912 | since a MOV instruction produces unpredictable results. */ | |
6913 | if (inst.instruction == T_OPCODE_MOV_I8) | |
6914 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 6915 | else |
c19d1205 | 6916 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 6917 | |
c19d1205 ZW |
6918 | inst.instruction |= inst.operands[0].reg; |
6919 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
6920 | } |
6921 | else | |
6922 | { | |
c19d1205 ZW |
6923 | if (inst.instruction == T_OPCODE_MOV_I8) |
6924 | inst.instruction = T_OPCODE_MOV_HR; | |
6925 | else | |
6926 | inst.instruction = T_OPCODE_CMP_HR; | |
6927 | do_t_cpy (); | |
b99bd4ef NC |
6928 | } |
6929 | } | |
c19d1205 | 6930 | else |
b99bd4ef | 6931 | { |
c19d1205 ZW |
6932 | constraint (inst.operands[0].reg > 7, |
6933 | _("only lo regs allowed with immediate")); | |
6934 | inst.instruction |= inst.operands[0].reg << 8; | |
6935 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
6936 | } | |
6937 | } | |
b99bd4ef | 6938 | |
c19d1205 ZW |
6939 | static void |
6940 | do_t_mov16 (void) | |
6941 | { | |
6942 | inst.instruction |= inst.operands[0].reg << 8; | |
6943 | inst.instruction |= (inst.operands[1].imm & 0xf000) << 4; | |
6944 | inst.instruction |= (inst.operands[1].imm & 0x0800) << 15; | |
6945 | inst.instruction |= (inst.operands[1].imm & 0x0700) << 4; | |
6946 | inst.instruction |= (inst.operands[1].imm & 0x00ff); | |
6947 | } | |
b99bd4ef | 6948 | |
c19d1205 ZW |
6949 | static void |
6950 | do_t_mvn_tst (void) | |
6951 | { | |
6952 | if (unified_syntax) | |
6953 | { | |
6954 | int r0off = (inst.instruction == T_MNEM_mvn | |
6955 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
6956 | bfd_boolean narrow; |
6957 | ||
6958 | if (inst.size_req == 4 | |
6959 | || inst.instruction > 0xffff | |
6960 | || inst.operands[1].shifted | |
6961 | || inst.operands[0].reg > 7 || inst.operands[1].reg > 7) | |
6962 | narrow = FALSE; | |
6963 | else if (inst.instruction == T_MNEM_cmn) | |
6964 | narrow = TRUE; | |
6965 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
6966 | narrow = (current_it_mask == 0); | |
6967 | else | |
6968 | narrow = (current_it_mask != 0); | |
6969 | ||
c19d1205 | 6970 | if (!inst.operands[1].isreg) |
b99bd4ef | 6971 | { |
c19d1205 ZW |
6972 | /* For an immediate, we always generate a 32-bit opcode; |
6973 | section relaxation will shrink it later if possible. */ | |
6974 | if (inst.instruction < 0xffff) | |
6975 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6976 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
6977 | inst.instruction |= inst.operands[0].reg << r0off; | |
6978 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 6979 | } |
c19d1205 | 6980 | else |
b99bd4ef | 6981 | { |
c19d1205 | 6982 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 6983 | if (narrow) |
b99bd4ef | 6984 | { |
c19d1205 ZW |
6985 | inst.instruction = THUMB_OP16 (inst.instruction); |
6986 | inst.instruction |= inst.operands[0].reg; | |
6987 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef | 6988 | } |
c19d1205 | 6989 | else |
b99bd4ef | 6990 | { |
c19d1205 ZW |
6991 | constraint (inst.operands[1].shifted |
6992 | && inst.operands[1].immisreg, | |
6993 | _("shift must be constant")); | |
6994 | if (inst.instruction < 0xffff) | |
6995 | inst.instruction = THUMB_OP32 (inst.instruction); | |
6996 | inst.instruction |= inst.operands[0].reg << r0off; | |
6997 | encode_thumb32_shifted_operand (1); | |
b99bd4ef | 6998 | } |
b99bd4ef NC |
6999 | } |
7000 | } | |
7001 | else | |
7002 | { | |
c19d1205 ZW |
7003 | constraint (inst.instruction > 0xffff |
7004 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
7005 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
7006 | _("unshifted register required")); | |
7007 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, | |
7008 | BAD_HIREG); | |
b99bd4ef | 7009 | |
c19d1205 ZW |
7010 | inst.instruction = THUMB_OP16 (inst.instruction); |
7011 | inst.instruction |= inst.operands[0].reg; | |
7012 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef | 7013 | } |
b99bd4ef NC |
7014 | } |
7015 | ||
b05fe5cf | 7016 | static void |
c19d1205 | 7017 | do_t_mrs (void) |
b05fe5cf | 7018 | { |
c19d1205 ZW |
7019 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ |
7020 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
7021 | != (PSR_c|PSR_f), | |
7022 | _("'CPSR' or 'SPSR' expected")); | |
7023 | inst.instruction |= inst.operands[0].reg << 8; | |
7024 | inst.instruction |= (inst.operands[1].imm & SPSR_BIT) >> 2; | |
7025 | } | |
b05fe5cf | 7026 | |
c19d1205 ZW |
7027 | static void |
7028 | do_t_msr (void) | |
7029 | { | |
7030 | constraint (!inst.operands[1].isreg, | |
7031 | _("Thumb encoding does not support an immediate here")); | |
7032 | inst.instruction |= (inst.operands[0].imm & SPSR_BIT) >> 2; | |
7033 | inst.instruction |= (inst.operands[0].imm & ~SPSR_BIT) >> 8; | |
7034 | inst.instruction |= inst.operands[1].reg << 16; | |
7035 | } | |
b05fe5cf | 7036 | |
c19d1205 ZW |
7037 | static void |
7038 | do_t_mul (void) | |
7039 | { | |
7040 | if (!inst.operands[2].present) | |
7041 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 7042 | |
c19d1205 ZW |
7043 | /* There is no 32-bit MULS and no 16-bit MUL. */ |
7044 | if (unified_syntax && inst.instruction == T_MNEM_mul) | |
b05fe5cf | 7045 | { |
c19d1205 ZW |
7046 | inst.instruction = THUMB_OP32 (inst.instruction); |
7047 | inst.instruction |= inst.operands[0].reg << 8; | |
7048 | inst.instruction |= inst.operands[1].reg << 16; | |
7049 | inst.instruction |= inst.operands[2].reg << 0; | |
b05fe5cf | 7050 | } |
c19d1205 | 7051 | else |
b05fe5cf | 7052 | { |
c19d1205 ZW |
7053 | constraint (!unified_syntax |
7054 | && inst.instruction == T_MNEM_muls, BAD_THUMB32); | |
7055 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, | |
7056 | BAD_HIREG); | |
b05fe5cf | 7057 | |
c19d1205 ZW |
7058 | inst.instruction = THUMB_OP16 (inst.instruction); |
7059 | inst.instruction |= inst.operands[0].reg; | |
b05fe5cf | 7060 | |
c19d1205 ZW |
7061 | if (inst.operands[0].reg == inst.operands[1].reg) |
7062 | inst.instruction |= inst.operands[2].reg << 3; | |
7063 | else if (inst.operands[0].reg == inst.operands[2].reg) | |
7064 | inst.instruction |= inst.operands[1].reg << 3; | |
7065 | else | |
7066 | constraint (1, _("dest must overlap one source register")); | |
7067 | } | |
7068 | } | |
b05fe5cf | 7069 | |
c19d1205 ZW |
7070 | static void |
7071 | do_t_mull (void) | |
7072 | { | |
7073 | inst.instruction |= inst.operands[0].reg << 12; | |
7074 | inst.instruction |= inst.operands[1].reg << 8; | |
7075 | inst.instruction |= inst.operands[2].reg << 16; | |
7076 | inst.instruction |= inst.operands[3].reg; | |
b05fe5cf | 7077 | |
c19d1205 ZW |
7078 | if (inst.operands[0].reg == inst.operands[1].reg) |
7079 | as_tsktsk (_("rdhi and rdlo must be different")); | |
7080 | } | |
b05fe5cf | 7081 | |
c19d1205 ZW |
7082 | static void |
7083 | do_t_nop (void) | |
7084 | { | |
7085 | if (unified_syntax) | |
7086 | { | |
7087 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 7088 | { |
c19d1205 ZW |
7089 | inst.instruction = THUMB_OP32 (inst.instruction); |
7090 | inst.instruction |= inst.operands[0].imm; | |
7091 | } | |
7092 | else | |
7093 | { | |
7094 | inst.instruction = THUMB_OP16 (inst.instruction); | |
7095 | inst.instruction |= inst.operands[0].imm << 4; | |
7096 | } | |
7097 | } | |
7098 | else | |
7099 | { | |
7100 | constraint (inst.operands[0].present, | |
7101 | _("Thumb does not support NOP with hints")); | |
7102 | inst.instruction = 0x46c0; | |
7103 | } | |
7104 | } | |
b05fe5cf | 7105 | |
c19d1205 ZW |
7106 | static void |
7107 | do_t_neg (void) | |
7108 | { | |
7109 | if (unified_syntax) | |
7110 | { | |
3d388997 PB |
7111 | bfd_boolean narrow; |
7112 | ||
7113 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
7114 | narrow = (current_it_mask == 0); | |
7115 | else | |
7116 | narrow = (current_it_mask != 0); | |
7117 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) | |
7118 | narrow = FALSE; | |
7119 | if (inst.size_req == 4) | |
7120 | narrow = FALSE; | |
7121 | ||
7122 | if (!narrow) | |
c19d1205 ZW |
7123 | { |
7124 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7125 | inst.instruction |= inst.operands[0].reg << 8; | |
7126 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
7127 | } |
7128 | else | |
7129 | { | |
c19d1205 ZW |
7130 | inst.instruction = THUMB_OP16 (inst.instruction); |
7131 | inst.instruction |= inst.operands[0].reg; | |
7132 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
7133 | } |
7134 | } | |
7135 | else | |
7136 | { | |
c19d1205 ZW |
7137 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
7138 | BAD_HIREG); | |
7139 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
7140 | ||
7141 | inst.instruction = THUMB_OP16 (inst.instruction); | |
7142 | inst.instruction |= inst.operands[0].reg; | |
7143 | inst.instruction |= inst.operands[1].reg << 3; | |
7144 | } | |
7145 | } | |
7146 | ||
7147 | static void | |
7148 | do_t_pkhbt (void) | |
7149 | { | |
7150 | inst.instruction |= inst.operands[0].reg << 8; | |
7151 | inst.instruction |= inst.operands[1].reg << 16; | |
7152 | inst.instruction |= inst.operands[2].reg; | |
7153 | if (inst.operands[3].present) | |
7154 | { | |
7155 | unsigned int val = inst.reloc.exp.X_add_number; | |
7156 | constraint (inst.reloc.exp.X_op != O_constant, | |
7157 | _("expression too complex")); | |
7158 | inst.instruction |= (val & 0x1c) << 10; | |
7159 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 7160 | } |
c19d1205 | 7161 | } |
b05fe5cf | 7162 | |
c19d1205 ZW |
7163 | static void |
7164 | do_t_pkhtb (void) | |
7165 | { | |
7166 | if (!inst.operands[3].present) | |
7167 | inst.instruction &= ~0x00000020; | |
7168 | do_t_pkhbt (); | |
b05fe5cf ZW |
7169 | } |
7170 | ||
c19d1205 ZW |
7171 | static void |
7172 | do_t_pld (void) | |
7173 | { | |
7174 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
7175 | } | |
b05fe5cf | 7176 | |
c19d1205 ZW |
7177 | static void |
7178 | do_t_push_pop (void) | |
b99bd4ef | 7179 | { |
e9f89963 PB |
7180 | unsigned mask; |
7181 | ||
c19d1205 ZW |
7182 | constraint (inst.operands[0].writeback, |
7183 | _("push/pop do not support {reglist}^")); | |
7184 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
7185 | _("expression too complex")); | |
b99bd4ef | 7186 | |
e9f89963 PB |
7187 | mask = inst.operands[0].imm; |
7188 | if ((mask & ~0xff) == 0) | |
c19d1205 ZW |
7189 | inst.instruction = THUMB_OP16 (inst.instruction); |
7190 | else if ((inst.instruction == T_MNEM_push | |
e9f89963 | 7191 | && (mask & ~0xff) == 1 << REG_LR) |
c19d1205 | 7192 | || (inst.instruction == T_MNEM_pop |
e9f89963 | 7193 | && (mask & ~0xff) == 1 << REG_PC)) |
b99bd4ef | 7194 | { |
c19d1205 ZW |
7195 | inst.instruction = THUMB_OP16 (inst.instruction); |
7196 | inst.instruction |= THUMB_PP_PC_LR; | |
e9f89963 | 7197 | mask &= 0xff; |
c19d1205 ZW |
7198 | } |
7199 | else if (unified_syntax) | |
7200 | { | |
e9f89963 PB |
7201 | if (mask & (1 << 13)) |
7202 | inst.error = _("SP not allowed in register list"); | |
c19d1205 | 7203 | if (inst.instruction == T_MNEM_push) |
b99bd4ef | 7204 | { |
e9f89963 PB |
7205 | if (mask & (1 << 15)) |
7206 | inst.error = _("PC not allowed in register list"); | |
c19d1205 ZW |
7207 | } |
7208 | else | |
7209 | { | |
e9f89963 PB |
7210 | if (mask & (1 << 14) |
7211 | && mask & (1 << 15)) | |
7212 | inst.error = _("LR and PC should not both be in register list"); | |
c19d1205 | 7213 | } |
e9f89963 PB |
7214 | if ((mask & (mask - 1)) == 0) |
7215 | { | |
7216 | /* Single register push/pop implemented as str/ldr. */ | |
7217 | if (inst.instruction == T_MNEM_push) | |
7218 | inst.instruction = 0xf84d0d04; /* str reg, [sp, #-4]! */ | |
7219 | else | |
7220 | inst.instruction = 0xf85d0b04; /* ldr reg, [sp], #4 */ | |
7221 | mask = ffs(mask) - 1; | |
7222 | mask <<= 12; | |
7223 | } | |
7224 | else | |
7225 | inst.instruction = THUMB_OP32 (inst.instruction); | |
c19d1205 ZW |
7226 | } |
7227 | else | |
7228 | { | |
7229 | inst.error = _("invalid register list to push/pop instruction"); | |
7230 | return; | |
7231 | } | |
b99bd4ef | 7232 | |
e9f89963 | 7233 | inst.instruction |= mask; |
c19d1205 | 7234 | } |
b99bd4ef | 7235 | |
c19d1205 ZW |
7236 | static void |
7237 | do_t_rbit (void) | |
7238 | { | |
7239 | inst.instruction |= inst.operands[0].reg << 8; | |
7240 | inst.instruction |= inst.operands[1].reg << 16; | |
7241 | } | |
b99bd4ef | 7242 | |
c19d1205 ZW |
7243 | static void |
7244 | do_t_rev (void) | |
7245 | { | |
7246 | if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 | |
7247 | && inst.size_req != 4) | |
7248 | { | |
7249 | inst.instruction = THUMB_OP16 (inst.instruction); | |
7250 | inst.instruction |= inst.operands[0].reg; | |
7251 | inst.instruction |= inst.operands[1].reg << 3; | |
7252 | } | |
7253 | else if (unified_syntax) | |
7254 | { | |
7255 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7256 | inst.instruction |= inst.operands[0].reg << 8; | |
7257 | inst.instruction |= inst.operands[1].reg << 16; | |
7258 | inst.instruction |= inst.operands[1].reg; | |
7259 | } | |
7260 | else | |
7261 | inst.error = BAD_HIREG; | |
7262 | } | |
b99bd4ef | 7263 | |
c19d1205 ZW |
7264 | static void |
7265 | do_t_rsb (void) | |
7266 | { | |
7267 | int Rd, Rs; | |
b99bd4ef | 7268 | |
c19d1205 ZW |
7269 | Rd = inst.operands[0].reg; |
7270 | Rs = (inst.operands[1].present | |
7271 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
7272 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 7273 | |
c19d1205 ZW |
7274 | inst.instruction |= Rd << 8; |
7275 | inst.instruction |= Rs << 16; | |
7276 | if (!inst.operands[2].isreg) | |
7277 | { | |
7278 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
7279 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
7280 | } | |
7281 | else | |
7282 | encode_thumb32_shifted_operand (2); | |
7283 | } | |
b99bd4ef | 7284 | |
c19d1205 ZW |
7285 | static void |
7286 | do_t_setend (void) | |
7287 | { | |
7288 | if (inst.operands[0].imm) | |
7289 | inst.instruction |= 0x8; | |
7290 | } | |
b99bd4ef | 7291 | |
c19d1205 ZW |
7292 | static void |
7293 | do_t_shift (void) | |
7294 | { | |
7295 | if (!inst.operands[1].present) | |
7296 | inst.operands[1].reg = inst.operands[0].reg; | |
7297 | ||
7298 | if (unified_syntax) | |
7299 | { | |
3d388997 PB |
7300 | bfd_boolean narrow; |
7301 | int shift_kind; | |
7302 | ||
7303 | switch (inst.instruction) | |
7304 | { | |
7305 | case T_MNEM_asr: | |
7306 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
7307 | case T_MNEM_lsl: | |
7308 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
7309 | case T_MNEM_lsr: | |
7310 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
7311 | case T_MNEM_ror: | |
7312 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
7313 | default: abort (); | |
7314 | } | |
7315 | ||
7316 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
7317 | narrow = (current_it_mask == 0); | |
7318 | else | |
7319 | narrow = (current_it_mask != 0); | |
7320 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) | |
7321 | narrow = FALSE; | |
7322 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
7323 | narrow = FALSE; | |
7324 | if (inst.operands[2].isreg | |
7325 | && (inst.operands[1].reg != inst.operands[0].reg | |
7326 | || inst.operands[2].reg > 7)) | |
7327 | narrow = FALSE; | |
7328 | if (inst.size_req == 4) | |
7329 | narrow = FALSE; | |
7330 | ||
7331 | if (!narrow) | |
c19d1205 ZW |
7332 | { |
7333 | if (inst.operands[2].isreg) | |
b99bd4ef | 7334 | { |
c19d1205 ZW |
7335 | inst.instruction = THUMB_OP32 (inst.instruction); |
7336 | inst.instruction |= inst.operands[0].reg << 8; | |
7337 | inst.instruction |= inst.operands[1].reg << 16; | |
7338 | inst.instruction |= inst.operands[2].reg; | |
7339 | } | |
7340 | else | |
7341 | { | |
7342 | inst.operands[1].shifted = 1; | |
3d388997 | 7343 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
7344 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
7345 | ? T_MNEM_movs : T_MNEM_mov); | |
7346 | inst.instruction |= inst.operands[0].reg << 8; | |
7347 | encode_thumb32_shifted_operand (1); | |
7348 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
7349 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
7350 | } |
7351 | } | |
7352 | else | |
7353 | { | |
c19d1205 | 7354 | if (inst.operands[2].isreg) |
b99bd4ef | 7355 | { |
3d388997 | 7356 | switch (shift_kind) |
b99bd4ef | 7357 | { |
3d388997 PB |
7358 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
7359 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
7360 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
7361 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 7362 | default: abort (); |
b99bd4ef | 7363 | } |
c19d1205 ZW |
7364 | |
7365 | inst.instruction |= inst.operands[0].reg; | |
7366 | inst.instruction |= inst.operands[2].reg << 3; | |
b99bd4ef NC |
7367 | } |
7368 | else | |
7369 | { | |
3d388997 | 7370 | switch (shift_kind) |
b99bd4ef | 7371 | { |
3d388997 PB |
7372 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
7373 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
7374 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 7375 | default: abort (); |
b99bd4ef | 7376 | } |
c19d1205 ZW |
7377 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
7378 | inst.instruction |= inst.operands[0].reg; | |
7379 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
7380 | } |
7381 | } | |
c19d1205 ZW |
7382 | } |
7383 | else | |
7384 | { | |
7385 | constraint (inst.operands[0].reg > 7 | |
7386 | || inst.operands[1].reg > 7, BAD_HIREG); | |
7387 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 7388 | |
c19d1205 ZW |
7389 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
7390 | { | |
7391 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
7392 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
7393 | _("source1 and dest must be same register")); | |
b99bd4ef | 7394 | |
c19d1205 ZW |
7395 | switch (inst.instruction) |
7396 | { | |
7397 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
7398 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
7399 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
7400 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
7401 | default: abort (); | |
7402 | } | |
7403 | ||
7404 | inst.instruction |= inst.operands[0].reg; | |
7405 | inst.instruction |= inst.operands[2].reg << 3; | |
7406 | } | |
7407 | else | |
b99bd4ef | 7408 | { |
c19d1205 ZW |
7409 | switch (inst.instruction) |
7410 | { | |
7411 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
7412 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
7413 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
7414 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
7415 | default: abort (); | |
7416 | } | |
7417 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
7418 | inst.instruction |= inst.operands[0].reg; | |
7419 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
7420 | } |
7421 | } | |
b99bd4ef NC |
7422 | } |
7423 | ||
7424 | static void | |
c19d1205 | 7425 | do_t_simd (void) |
b99bd4ef | 7426 | { |
c19d1205 ZW |
7427 | inst.instruction |= inst.operands[0].reg << 8; |
7428 | inst.instruction |= inst.operands[1].reg << 16; | |
7429 | inst.instruction |= inst.operands[2].reg; | |
7430 | } | |
b99bd4ef | 7431 | |
c19d1205 | 7432 | static void |
3eb17e6b | 7433 | do_t_smc (void) |
c19d1205 ZW |
7434 | { |
7435 | unsigned int value = inst.reloc.exp.X_add_number; | |
7436 | constraint (inst.reloc.exp.X_op != O_constant, | |
7437 | _("expression too complex")); | |
7438 | inst.reloc.type = BFD_RELOC_UNUSED; | |
7439 | inst.instruction |= (value & 0xf000) >> 12; | |
7440 | inst.instruction |= (value & 0x0ff0); | |
7441 | inst.instruction |= (value & 0x000f) << 16; | |
7442 | } | |
b99bd4ef | 7443 | |
c19d1205 ZW |
7444 | static void |
7445 | do_t_ssat (void) | |
7446 | { | |
7447 | inst.instruction |= inst.operands[0].reg << 8; | |
7448 | inst.instruction |= inst.operands[1].imm - 1; | |
7449 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef | 7450 | |
c19d1205 | 7451 | if (inst.operands[3].present) |
b99bd4ef | 7452 | { |
c19d1205 ZW |
7453 | constraint (inst.reloc.exp.X_op != O_constant, |
7454 | _("expression too complex")); | |
b99bd4ef | 7455 | |
c19d1205 | 7456 | if (inst.reloc.exp.X_add_number != 0) |
6189168b | 7457 | { |
c19d1205 ZW |
7458 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
7459 | inst.instruction |= 0x00200000; /* sh bit */ | |
7460 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; | |
7461 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; | |
6189168b | 7462 | } |
c19d1205 | 7463 | inst.reloc.type = BFD_RELOC_UNUSED; |
6189168b | 7464 | } |
b99bd4ef NC |
7465 | } |
7466 | ||
0dd132b6 | 7467 | static void |
c19d1205 | 7468 | do_t_ssat16 (void) |
0dd132b6 | 7469 | { |
c19d1205 ZW |
7470 | inst.instruction |= inst.operands[0].reg << 8; |
7471 | inst.instruction |= inst.operands[1].imm - 1; | |
7472 | inst.instruction |= inst.operands[2].reg << 16; | |
7473 | } | |
0dd132b6 | 7474 | |
c19d1205 ZW |
7475 | static void |
7476 | do_t_strex (void) | |
7477 | { | |
7478 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
7479 | || inst.operands[2].postind || inst.operands[2].writeback | |
7480 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
7481 | || inst.operands[2].negative, | |
7482 | _("instruction does not accept this addressing mode")); | |
0dd132b6 | 7483 | |
c19d1205 ZW |
7484 | inst.instruction |= inst.operands[0].reg << 8; |
7485 | inst.instruction |= inst.operands[1].reg << 12; | |
7486 | inst.instruction |= inst.operands[2].reg << 16; | |
7487 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
7488 | } |
7489 | ||
b99bd4ef | 7490 | static void |
c19d1205 | 7491 | do_t_strexd (void) |
b99bd4ef | 7492 | { |
c19d1205 ZW |
7493 | if (!inst.operands[2].present) |
7494 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 7495 | |
c19d1205 ZW |
7496 | constraint (inst.operands[0].reg == inst.operands[1].reg |
7497 | || inst.operands[0].reg == inst.operands[2].reg | |
7498 | || inst.operands[0].reg == inst.operands[3].reg | |
7499 | || inst.operands[1].reg == inst.operands[2].reg, | |
7500 | BAD_OVERLAP); | |
b99bd4ef | 7501 | |
c19d1205 ZW |
7502 | inst.instruction |= inst.operands[0].reg; |
7503 | inst.instruction |= inst.operands[1].reg << 12; | |
7504 | inst.instruction |= inst.operands[2].reg << 8; | |
7505 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
7506 | } |
7507 | ||
7508 | static void | |
c19d1205 | 7509 | do_t_sxtah (void) |
b99bd4ef | 7510 | { |
c19d1205 ZW |
7511 | inst.instruction |= inst.operands[0].reg << 8; |
7512 | inst.instruction |= inst.operands[1].reg << 16; | |
7513 | inst.instruction |= inst.operands[2].reg; | |
7514 | inst.instruction |= inst.operands[3].imm << 4; | |
7515 | } | |
b99bd4ef | 7516 | |
c19d1205 ZW |
7517 | static void |
7518 | do_t_sxth (void) | |
7519 | { | |
7520 | if (inst.instruction <= 0xffff && inst.size_req != 4 | |
7521 | && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 | |
7522 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) | |
b99bd4ef | 7523 | { |
c19d1205 ZW |
7524 | inst.instruction = THUMB_OP16 (inst.instruction); |
7525 | inst.instruction |= inst.operands[0].reg; | |
7526 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef | 7527 | } |
c19d1205 | 7528 | else if (unified_syntax) |
b99bd4ef | 7529 | { |
c19d1205 ZW |
7530 | if (inst.instruction <= 0xffff) |
7531 | inst.instruction = THUMB_OP32 (inst.instruction); | |
7532 | inst.instruction |= inst.operands[0].reg << 8; | |
7533 | inst.instruction |= inst.operands[1].reg; | |
7534 | inst.instruction |= inst.operands[2].imm << 4; | |
b99bd4ef | 7535 | } |
c19d1205 | 7536 | else |
b99bd4ef | 7537 | { |
c19d1205 ZW |
7538 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
7539 | _("Thumb encoding does not support rotation")); | |
7540 | constraint (1, BAD_HIREG); | |
b99bd4ef | 7541 | } |
c19d1205 | 7542 | } |
b99bd4ef | 7543 | |
c19d1205 ZW |
7544 | static void |
7545 | do_t_swi (void) | |
7546 | { | |
7547 | inst.reloc.type = BFD_RELOC_ARM_SWI; | |
7548 | } | |
b99bd4ef | 7549 | |
92e90b6e PB |
7550 | static void |
7551 | do_t_tb (void) | |
7552 | { | |
7553 | int half; | |
7554 | ||
7555 | half = (inst.instruction & 0x10) != 0; | |
7556 | constraint (inst.operands[0].imm == 15, | |
7557 | _("PC is not a valid index register")); | |
7558 | constraint (!half && inst.operands[0].shifted, | |
7559 | _("instruction does not allow shifted index")); | |
7560 | constraint (half && !inst.operands[0].shifted, | |
7561 | _("instruction requires shifted index")); | |
7562 | inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm; | |
7563 | } | |
7564 | ||
c19d1205 ZW |
7565 | static void |
7566 | do_t_usat (void) | |
7567 | { | |
7568 | inst.instruction |= inst.operands[0].reg << 8; | |
7569 | inst.instruction |= inst.operands[1].imm; | |
7570 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef | 7571 | |
c19d1205 | 7572 | if (inst.operands[3].present) |
b99bd4ef | 7573 | { |
c19d1205 ZW |
7574 | constraint (inst.reloc.exp.X_op != O_constant, |
7575 | _("expression too complex")); | |
7576 | if (inst.reloc.exp.X_add_number != 0) | |
7577 | { | |
7578 | if (inst.operands[3].shift_kind == SHIFT_ASR) | |
7579 | inst.instruction |= 0x00200000; /* sh bit */ | |
b99bd4ef | 7580 | |
c19d1205 ZW |
7581 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; |
7582 | inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; | |
7583 | } | |
7584 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 7585 | } |
b99bd4ef NC |
7586 | } |
7587 | ||
7588 | static void | |
c19d1205 | 7589 | do_t_usat16 (void) |
b99bd4ef | 7590 | { |
c19d1205 ZW |
7591 | inst.instruction |= inst.operands[0].reg << 8; |
7592 | inst.instruction |= inst.operands[1].imm; | |
7593 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef | 7594 | } |
c19d1205 ZW |
7595 | \f |
7596 | /* Overall per-instruction processing. */ | |
7597 | ||
7598 | /* We need to be able to fix up arbitrary expressions in some statements. | |
7599 | This is so that we can handle symbols that are an arbitrary distance from | |
7600 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
7601 | which returns part of an address in a form which will be valid for | |
7602 | a data instruction. We do this by pushing the expression into a symbol | |
7603 | in the expr_section, and creating a fix for that. */ | |
b99bd4ef NC |
7604 | |
7605 | static void | |
c19d1205 ZW |
7606 | fix_new_arm (fragS * frag, |
7607 | int where, | |
7608 | short int size, | |
7609 | expressionS * exp, | |
7610 | int pc_rel, | |
7611 | int reloc) | |
b99bd4ef | 7612 | { |
c19d1205 | 7613 | fixS * new_fix; |
b99bd4ef | 7614 | |
c19d1205 | 7615 | switch (exp->X_op) |
b99bd4ef | 7616 | { |
c19d1205 ZW |
7617 | case O_constant: |
7618 | case O_symbol: | |
7619 | case O_add: | |
7620 | case O_subtract: | |
7621 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc); | |
7622 | break; | |
b99bd4ef | 7623 | |
c19d1205 ZW |
7624 | default: |
7625 | new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, | |
7626 | pc_rel, reloc); | |
7627 | break; | |
b99bd4ef NC |
7628 | } |
7629 | ||
c19d1205 ZW |
7630 | /* Mark whether the fix is to a THUMB instruction, or an ARM |
7631 | instruction. */ | |
adbaf948 | 7632 | new_fix->tc_fix_data = thumb_mode; |
b99bd4ef NC |
7633 | } |
7634 | ||
0110f2b8 PB |
7635 | /* Create a frg for an instruction requiring relaxation. */ |
7636 | static void | |
7637 | output_relax_insn (void) | |
7638 | { | |
7639 | char * to; | |
7640 | symbolS *sym; | |
7641 | int offset; | |
7642 | ||
7643 | switch (inst.reloc.exp.X_op) | |
7644 | { | |
7645 | case O_symbol: | |
7646 | sym = inst.reloc.exp.X_add_symbol; | |
7647 | offset = inst.reloc.exp.X_add_number; | |
7648 | break; | |
7649 | case O_constant: | |
7650 | sym = NULL; | |
7651 | offset = inst.reloc.exp.X_add_number; | |
7652 | break; | |
7653 | default: | |
7654 | sym = make_expr_symbol (&inst.reloc.exp); | |
7655 | offset = 0; | |
7656 | break; | |
7657 | } | |
7658 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
7659 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
7660 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
7661 | ||
7662 | #ifdef OBJ_ELF | |
7663 | dwarf2_emit_insn (INSN_SIZE); | |
7664 | #endif | |
7665 | } | |
7666 | ||
7667 | /* Write a 32-bit thumb instruction to buf. */ | |
7668 | static void | |
7669 | put_thumb32_insn (char * buf, unsigned long insn) | |
7670 | { | |
7671 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
7672 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
7673 | } | |
7674 | ||
b99bd4ef | 7675 | static void |
c19d1205 | 7676 | output_inst (const char * str) |
b99bd4ef | 7677 | { |
c19d1205 | 7678 | char * to = NULL; |
b99bd4ef | 7679 | |
c19d1205 | 7680 | if (inst.error) |
b99bd4ef | 7681 | { |
c19d1205 | 7682 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
7683 | return; |
7684 | } | |
0110f2b8 PB |
7685 | if (inst.relax) { |
7686 | output_relax_insn(); | |
7687 | return; | |
7688 | } | |
c19d1205 ZW |
7689 | if (inst.size == 0) |
7690 | return; | |
b99bd4ef | 7691 | |
c19d1205 ZW |
7692 | to = frag_more (inst.size); |
7693 | ||
7694 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 7695 | { |
c19d1205 | 7696 | assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 7697 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 7698 | } |
c19d1205 | 7699 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 7700 | { |
c19d1205 ZW |
7701 | assert (inst.size == (2 * INSN_SIZE)); |
7702 | md_number_to_chars (to, inst.instruction, INSN_SIZE); | |
7703 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 7704 | } |
c19d1205 ZW |
7705 | else |
7706 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 7707 | |
c19d1205 ZW |
7708 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
7709 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
7710 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
7711 | inst.reloc.type); | |
b99bd4ef | 7712 | |
c19d1205 ZW |
7713 | #ifdef OBJ_ELF |
7714 | dwarf2_emit_insn (inst.size); | |
7715 | #endif | |
7716 | } | |
b99bd4ef | 7717 | |
c19d1205 ZW |
7718 | /* Tag values used in struct asm_opcode's tag field. */ |
7719 | enum opcode_tag | |
7720 | { | |
7721 | OT_unconditional, /* Instruction cannot be conditionalized. | |
7722 | The ARM condition field is still 0xE. */ | |
7723 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
7724 | and carries 0xF in its ARM condition field. */ | |
7725 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
7726 | OT_cinfix3, /* Instruction takes a conditional infix, | |
7727 | beginning at character index 3. (In | |
7728 | unified mode, it becomes a suffix.) */ | |
7729 | OT_csuf_or_in3, /* Instruction takes either a conditional | |
7730 | suffix or an infix at character index 3. | |
7731 | (In unified mode, a suffix only. */ | |
7732 | OT_odd_infix_unc, /* This is the unconditional variant of an | |
7733 | instruction that takes a conditional infix | |
7734 | at an unusual position. In unified mode, | |
7735 | this variant will accept a suffix. */ | |
7736 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
7737 | are the conditional variants of instructions that | |
7738 | take conditional infixes in unusual positions. | |
7739 | The infix appears at character index | |
7740 | (tag - OT_odd_infix_0). These are not accepted | |
7741 | in unified mode. */ | |
7742 | }; | |
b99bd4ef | 7743 | |
c19d1205 ZW |
7744 | /* Subroutine of md_assemble, responsible for looking up the primary |
7745 | opcode from the mnemonic the user wrote. STR points to the | |
7746 | beginning of the mnemonic. | |
7747 | ||
7748 | This is not simply a hash table lookup, because of conditional | |
7749 | variants. Most instructions have conditional variants, which are | |
7750 | expressed with a _conditional affix_ to the mnemonic. If we were | |
7751 | to encode each conditional variant as a literal string in the opcode | |
7752 | table, it would have approximately 20,000 entries. | |
7753 | ||
7754 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
7755 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
7756 | instructions take the affix as an infix, notably the s-variants of | |
7757 | the arithmetic instructions. Of those instructions, all but six | |
7758 | have the infix appear after the third character of the mnemonic. | |
7759 | ||
7760 | Accordingly, the algorithm for looking up primary opcodes given | |
7761 | an identifier is: | |
7762 | ||
7763 | 1. Look up the identifier in the opcode table. | |
7764 | If we find a match, go to step U. | |
7765 | ||
7766 | 2. Look up the last two characters of the identifier in the | |
7767 | conditions table. If we find a match, look up the first N-2 | |
7768 | characters of the identifier in the opcode table. If we | |
7769 | find a match, go to step CE. | |
7770 | ||
7771 | 3. Look up the fourth and fifth characters of the identifier in | |
7772 | the conditions table. If we find a match, extract those | |
7773 | characters from the identifier, and look up the remaining | |
7774 | characters in the opcode table. If we find a match, go | |
7775 | to step CM. | |
7776 | ||
7777 | 4. Fail. | |
7778 | ||
7779 | U. Examine the tag field of the opcode structure, in case this is | |
7780 | one of the six instructions with its conditional infix in an | |
7781 | unusual place. If it is, the tag tells us where to find the | |
7782 | infix; look it up in the conditions table and set inst.cond | |
7783 | accordingly. Otherwise, this is an unconditional instruction. | |
7784 | Again set inst.cond accordingly. Return the opcode structure. | |
7785 | ||
7786 | CE. Examine the tag field to make sure this is an instruction that | |
7787 | should receive a conditional suffix. If it is not, fail. | |
7788 | Otherwise, set inst.cond from the suffix we already looked up, | |
7789 | and return the opcode structure. | |
7790 | ||
7791 | CM. Examine the tag field to make sure this is an instruction that | |
7792 | should receive a conditional infix after the third character. | |
7793 | If it is not, fail. Otherwise, undo the edits to the current | |
7794 | line of input and proceed as for case CE. */ | |
7795 | ||
7796 | static const struct asm_opcode * | |
7797 | opcode_lookup (char **str) | |
7798 | { | |
7799 | char *end, *base; | |
7800 | char *affix; | |
7801 | const struct asm_opcode *opcode; | |
7802 | const struct asm_cond *cond; | |
7803 | ||
7804 | /* Scan up to the end of the mnemonic, which must end in white space, | |
7805 | '.' (in unified mode only), or end of string. */ | |
7806 | for (base = end = *str; *end != '\0'; end++) | |
7807 | if (*end == ' ' || (unified_syntax && *end == '.')) | |
7808 | break; | |
b99bd4ef | 7809 | |
c19d1205 ZW |
7810 | if (end == base) |
7811 | return 0; | |
b99bd4ef | 7812 | |
c19d1205 ZW |
7813 | /* Handle a possible width suffix. */ |
7814 | if (end[0] == '.') | |
b99bd4ef | 7815 | { |
c19d1205 ZW |
7816 | if (end[1] == 'w' && (end[2] == ' ' || end[2] == '\0')) |
7817 | inst.size_req = 4; | |
7818 | else if (end[1] == 'n' && (end[2] == ' ' || end[2] == '\0')) | |
7819 | inst.size_req = 2; | |
7820 | else | |
7821 | return 0; | |
b99bd4ef | 7822 | |
c19d1205 | 7823 | *str = end + 2; |
b99bd4ef | 7824 | } |
c19d1205 ZW |
7825 | else |
7826 | *str = end; | |
b99bd4ef | 7827 | |
c19d1205 ZW |
7828 | /* Look for unaffixed or special-case affixed mnemonic. */ |
7829 | opcode = hash_find_n (arm_ops_hsh, base, end - base); | |
7830 | if (opcode) | |
b99bd4ef | 7831 | { |
c19d1205 ZW |
7832 | /* step U */ |
7833 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 7834 | { |
c19d1205 ZW |
7835 | inst.cond = COND_ALWAYS; |
7836 | return opcode; | |
b99bd4ef | 7837 | } |
b99bd4ef | 7838 | |
c19d1205 ZW |
7839 | if (unified_syntax) |
7840 | as_warn (_("conditional infixes are deprecated in unified syntax")); | |
7841 | affix = base + (opcode->tag - OT_odd_infix_0); | |
7842 | cond = hash_find_n (arm_cond_hsh, affix, 2); | |
7843 | assert (cond); | |
b99bd4ef | 7844 | |
c19d1205 ZW |
7845 | inst.cond = cond->value; |
7846 | return opcode; | |
7847 | } | |
b99bd4ef | 7848 | |
c19d1205 ZW |
7849 | /* Cannot have a conditional suffix on a mnemonic of less than two |
7850 | characters. */ | |
7851 | if (end - base < 3) | |
7852 | return 0; | |
b99bd4ef | 7853 | |
c19d1205 ZW |
7854 | /* Look for suffixed mnemonic. */ |
7855 | affix = end - 2; | |
7856 | cond = hash_find_n (arm_cond_hsh, affix, 2); | |
7857 | opcode = hash_find_n (arm_ops_hsh, base, affix - base); | |
7858 | if (opcode && cond) | |
7859 | { | |
7860 | /* step CE */ | |
7861 | switch (opcode->tag) | |
7862 | { | |
7863 | case OT_cinfix3: | |
7864 | case OT_odd_infix_unc: | |
c4188bc9 PB |
7865 | /* Some mnemonics are ambiguous between infix and suffix |
7866 | conditions. Disambiguate based on assembly syntax. */ | |
c19d1205 | 7867 | if (!unified_syntax) |
c4188bc9 | 7868 | break; |
c19d1205 ZW |
7869 | /* else fall through */ |
7870 | ||
7871 | case OT_csuffix: | |
7872 | case OT_csuf_or_in3: | |
7873 | inst.cond = cond->value; | |
7874 | return opcode; | |
7875 | ||
7876 | case OT_unconditional: | |
7877 | case OT_unconditionalF: | |
7878 | /* delayed diagnostic */ | |
7879 | inst.error = BAD_COND; | |
7880 | inst.cond = COND_ALWAYS; | |
7881 | return opcode; | |
b99bd4ef | 7882 | |
c19d1205 ZW |
7883 | default: |
7884 | return 0; | |
7885 | } | |
7886 | } | |
b99bd4ef | 7887 | |
c19d1205 ZW |
7888 | /* Cannot have a usual-position infix on a mnemonic of less than |
7889 | six characters (five would be a suffix). */ | |
7890 | if (end - base < 6) | |
7891 | return 0; | |
b99bd4ef | 7892 | |
c19d1205 ZW |
7893 | /* Look for infixed mnemonic in the usual position. */ |
7894 | affix = base + 3; | |
7895 | cond = hash_find_n (arm_cond_hsh, affix, 2); | |
7896 | if (cond) | |
b99bd4ef | 7897 | { |
c19d1205 ZW |
7898 | char save[2]; |
7899 | memcpy (save, affix, 2); | |
7900 | memmove (affix, affix + 2, (end - affix) - 2); | |
7901 | opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2); | |
7902 | memmove (affix + 2, affix, (end - affix) - 2); | |
7903 | memcpy (affix, save, 2); | |
b99bd4ef | 7904 | } |
c19d1205 | 7905 | if (opcode && (opcode->tag == OT_cinfix3 || opcode->tag == OT_csuf_or_in3)) |
b99bd4ef | 7906 | { |
c19d1205 ZW |
7907 | /* step CM */ |
7908 | if (unified_syntax) | |
7909 | as_warn (_("conditional infixes are deprecated in unified syntax")); | |
7910 | ||
7911 | inst.cond = cond->value; | |
7912 | return opcode; | |
b99bd4ef NC |
7913 | } |
7914 | ||
c19d1205 | 7915 | return 0; |
b99bd4ef NC |
7916 | } |
7917 | ||
c19d1205 ZW |
7918 | void |
7919 | md_assemble (char *str) | |
b99bd4ef | 7920 | { |
c19d1205 ZW |
7921 | char *p = str; |
7922 | const struct asm_opcode * opcode; | |
b99bd4ef | 7923 | |
c19d1205 ZW |
7924 | /* Align the previous label if needed. */ |
7925 | if (last_label_seen != NULL) | |
b99bd4ef | 7926 | { |
c19d1205 ZW |
7927 | symbol_set_frag (last_label_seen, frag_now); |
7928 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
7929 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
7930 | } |
7931 | ||
c19d1205 ZW |
7932 | memset (&inst, '\0', sizeof (inst)); |
7933 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 7934 | |
c19d1205 ZW |
7935 | opcode = opcode_lookup (&p); |
7936 | if (!opcode) | |
b99bd4ef | 7937 | { |
c19d1205 ZW |
7938 | /* It wasn't an instruction, but it might be a register alias of |
7939 | the form alias .req reg. */ | |
7940 | if (!create_register_alias (str, p)) | |
7941 | as_bad (_("bad instruction `%s'"), str); | |
b99bd4ef | 7942 | |
b99bd4ef NC |
7943 | return; |
7944 | } | |
7945 | ||
c19d1205 | 7946 | if (thumb_mode) |
b99bd4ef | 7947 | { |
8f06b2d8 PB |
7948 | unsigned long variant; |
7949 | ||
7950 | variant = cpu_variant; | |
7951 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
7952 | if ((variant & ARM_EXT_V6T2) == 0) | |
7953 | variant &= ARM_ANY; | |
c19d1205 | 7954 | /* Check that this instruction is supported for this CPU. */ |
8f06b2d8 | 7955 | if (thumb_mode == 1 && (opcode->tvariant & variant) == 0) |
b99bd4ef | 7956 | { |
c19d1205 | 7957 | as_bad (_("selected processor does not support `%s'"), str); |
b99bd4ef NC |
7958 | return; |
7959 | } | |
c19d1205 ZW |
7960 | if (inst.cond != COND_ALWAYS && !unified_syntax |
7961 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 7962 | { |
c19d1205 | 7963 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
7964 | return; |
7965 | } | |
7966 | ||
e27ec89e PB |
7967 | /* Check conditional suffixes. */ |
7968 | if (current_it_mask) | |
7969 | { | |
7970 | int cond; | |
7971 | cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1; | |
7972 | if (cond != inst.cond) | |
7973 | { | |
7974 | as_bad (_("incorrect condition in IT block")); | |
7975 | return; | |
7976 | } | |
7977 | current_it_mask <<= 1; | |
7978 | current_it_mask &= 0x1f; | |
7979 | } | |
7980 | else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch) | |
7981 | { | |
7982 | as_bad (_("thumb conditional instrunction not in IT block")); | |
7983 | return; | |
7984 | } | |
7985 | ||
c19d1205 ZW |
7986 | mapping_state (MAP_THUMB); |
7987 | inst.instruction = opcode->tvalue; | |
7988 | ||
7989 | if (!parse_operands (p, opcode->operands)) | |
7990 | opcode->tencode (); | |
7991 | ||
e27ec89e PB |
7992 | /* Clear current_it_mask at the end of an IT block. */ |
7993 | if (current_it_mask == 0x10) | |
7994 | current_it_mask = 0; | |
7995 | ||
0110f2b8 | 7996 | if (!(inst.error || inst.relax)) |
b99bd4ef | 7997 | { |
c19d1205 ZW |
7998 | assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
7999 | inst.size = (inst.instruction > 0xffff ? 4 : 2); | |
8000 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 8001 | { |
c19d1205 | 8002 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
8003 | return; |
8004 | } | |
8005 | } | |
c19d1205 ZW |
8006 | } |
8007 | else | |
8008 | { | |
8009 | /* Check that this instruction is supported for this CPU. */ | |
8010 | if ((opcode->avariant & cpu_variant) == 0) | |
b99bd4ef | 8011 | { |
c19d1205 ZW |
8012 | as_bad (_("selected processor does not support `%s'"), str); |
8013 | return; | |
b99bd4ef | 8014 | } |
c19d1205 | 8015 | if (inst.size_req) |
b99bd4ef | 8016 | { |
c19d1205 ZW |
8017 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
8018 | return; | |
b99bd4ef NC |
8019 | } |
8020 | ||
c19d1205 ZW |
8021 | mapping_state (MAP_ARM); |
8022 | inst.instruction = opcode->avalue; | |
8023 | if (opcode->tag == OT_unconditionalF) | |
8024 | inst.instruction |= 0xF << 28; | |
8025 | else | |
8026 | inst.instruction |= inst.cond << 28; | |
8027 | inst.size = INSN_SIZE; | |
8028 | if (!parse_operands (p, opcode->operands)) | |
8029 | opcode->aencode (); | |
b99bd4ef | 8030 | } |
c19d1205 ZW |
8031 | output_inst (str); |
8032 | } | |
b99bd4ef | 8033 | |
c19d1205 ZW |
8034 | /* Various frobbings of labels and their addresses. */ |
8035 | ||
8036 | void | |
8037 | arm_start_line_hook (void) | |
8038 | { | |
8039 | last_label_seen = NULL; | |
b99bd4ef NC |
8040 | } |
8041 | ||
c19d1205 ZW |
8042 | void |
8043 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 8044 | { |
c19d1205 | 8045 | last_label_seen = sym; |
b99bd4ef | 8046 | |
c19d1205 | 8047 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 8048 | |
c19d1205 ZW |
8049 | #if defined OBJ_COFF || defined OBJ_ELF |
8050 | ARM_SET_INTERWORK (sym, support_interwork); | |
8051 | #endif | |
b99bd4ef | 8052 | |
c19d1205 ZW |
8053 | /* Note - do not allow local symbols (.Lxxx) to be labeled |
8054 | as Thumb functions. This is because these labels, whilst | |
8055 | they exist inside Thumb code, are not the entry points for | |
8056 | possible ARM->Thumb calls. Also, these labels can be used | |
8057 | as part of a computed goto or switch statement. eg gcc | |
8058 | can generate code that looks like this: | |
b99bd4ef | 8059 | |
c19d1205 ZW |
8060 | ldr r2, [pc, .Laaa] |
8061 | lsl r3, r3, #2 | |
8062 | ldr r2, [r3, r2] | |
8063 | mov pc, r2 | |
b99bd4ef | 8064 | |
c19d1205 ZW |
8065 | .Lbbb: .word .Lxxx |
8066 | .Lccc: .word .Lyyy | |
8067 | ..etc... | |
8068 | .Laaa: .word Lbbb | |
b99bd4ef | 8069 | |
c19d1205 ZW |
8070 | The first instruction loads the address of the jump table. |
8071 | The second instruction converts a table index into a byte offset. | |
8072 | The third instruction gets the jump address out of the table. | |
8073 | The fourth instruction performs the jump. | |
b99bd4ef | 8074 | |
c19d1205 ZW |
8075 | If the address stored at .Laaa is that of a symbol which has the |
8076 | Thumb_Func bit set, then the linker will arrange for this address | |
8077 | to have the bottom bit set, which in turn would mean that the | |
8078 | address computation performed by the third instruction would end | |
8079 | up with the bottom bit set. Since the ARM is capable of unaligned | |
8080 | word loads, the instruction would then load the incorrect address | |
8081 | out of the jump table, and chaos would ensue. */ | |
8082 | if (label_is_thumb_function_name | |
8083 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
8084 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 8085 | { |
c19d1205 ZW |
8086 | /* When the address of a Thumb function is taken the bottom |
8087 | bit of that address should be set. This will allow | |
8088 | interworking between Arm and Thumb functions to work | |
8089 | correctly. */ | |
b99bd4ef | 8090 | |
c19d1205 | 8091 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 8092 | |
c19d1205 | 8093 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 8094 | } |
07a53e5c RH |
8095 | |
8096 | #ifdef OBJ_ELF | |
8097 | dwarf2_emit_label (sym); | |
8098 | #endif | |
b99bd4ef NC |
8099 | } |
8100 | ||
c19d1205 ZW |
8101 | int |
8102 | arm_data_in_code (void) | |
b99bd4ef | 8103 | { |
c19d1205 | 8104 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 8105 | { |
c19d1205 ZW |
8106 | *input_line_pointer = '/'; |
8107 | input_line_pointer += 5; | |
8108 | *input_line_pointer = 0; | |
8109 | return 1; | |
b99bd4ef NC |
8110 | } |
8111 | ||
c19d1205 | 8112 | return 0; |
b99bd4ef NC |
8113 | } |
8114 | ||
c19d1205 ZW |
8115 | char * |
8116 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 8117 | { |
c19d1205 | 8118 | int len; |
b99bd4ef | 8119 | |
c19d1205 ZW |
8120 | if (thumb_mode && (len = strlen (name)) > 5 |
8121 | && streq (name + len - 5, "/data")) | |
8122 | *(name + len - 5) = 0; | |
b99bd4ef | 8123 | |
c19d1205 | 8124 | return name; |
b99bd4ef | 8125 | } |
c19d1205 ZW |
8126 | \f |
8127 | /* Table of all register names defined by default. The user can | |
8128 | define additional names with .req. Note that all register names | |
8129 | should appear in both upper and lowercase variants. Some registers | |
8130 | also have mixed-case names. */ | |
b99bd4ef | 8131 | |
c19d1205 ZW |
8132 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE } |
8133 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) | |
8134 | #define REGSET(p,t) \ | |
8135 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
8136 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
8137 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
8138 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
7ed4c4c5 | 8139 | |
c19d1205 | 8140 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 8141 | { |
c19d1205 ZW |
8142 | /* ARM integer registers. */ |
8143 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 8144 | |
c19d1205 ZW |
8145 | /* ATPCS synonyms. */ |
8146 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
8147 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
8148 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 8149 | |
c19d1205 ZW |
8150 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
8151 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
8152 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 8153 | |
c19d1205 ZW |
8154 | /* Well-known aliases. */ |
8155 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
8156 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
8157 | ||
8158 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
8159 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
8160 | ||
8161 | /* Coprocessor numbers. */ | |
8162 | REGSET(p, CP), REGSET(P, CP), | |
8163 | ||
8164 | /* Coprocessor register numbers. The "cr" variants are for backward | |
8165 | compatibility. */ | |
8166 | REGSET(c, CN), REGSET(C, CN), | |
8167 | REGSET(cr, CN), REGSET(CR, CN), | |
8168 | ||
8169 | /* FPA registers. */ | |
8170 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
8171 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
8172 | ||
8173 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
8174 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
8175 | ||
8176 | /* VFP SP registers. */ | |
8177 | REGSET(s,VFS), | |
8178 | REGNUM(s,16,VFS), REGNUM(s,17,VFS), REGNUM(s,18,VFS), REGNUM(s,19,VFS), | |
8179 | REGNUM(s,20,VFS), REGNUM(s,21,VFS), REGNUM(s,22,VFS), REGNUM(s,23,VFS), | |
8180 | REGNUM(s,24,VFS), REGNUM(s,25,VFS), REGNUM(s,26,VFS), REGNUM(s,27,VFS), | |
8181 | REGNUM(s,28,VFS), REGNUM(s,29,VFS), REGNUM(s,30,VFS), REGNUM(s,31,VFS), | |
8182 | ||
8183 | REGSET(S,VFS), | |
8184 | REGNUM(S,16,VFS), REGNUM(S,17,VFS), REGNUM(S,18,VFS), REGNUM(S,19,VFS), | |
8185 | REGNUM(S,20,VFS), REGNUM(S,21,VFS), REGNUM(S,22,VFS), REGNUM(S,23,VFS), | |
8186 | REGNUM(S,24,VFS), REGNUM(S,25,VFS), REGNUM(S,26,VFS), REGNUM(S,27,VFS), | |
8187 | REGNUM(S,28,VFS), REGNUM(S,29,VFS), REGNUM(S,30,VFS), REGNUM(S,31,VFS), | |
8188 | ||
8189 | /* VFP DP Registers. */ | |
8190 | REGSET(d,VFD), REGSET(D,VFS), | |
8191 | ||
8192 | /* VFP control registers. */ | |
8193 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
8194 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
8195 | ||
8196 | /* Maverick DSP coprocessor registers. */ | |
8197 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
8198 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
8199 | ||
8200 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
8201 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
8202 | REGDEF(dspsc,0,DSPSC), | |
8203 | ||
8204 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
8205 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
8206 | REGDEF(DSPSC,0,DSPSC), | |
8207 | ||
8208 | /* iWMMXt data registers - p0, c0-15. */ | |
8209 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
8210 | ||
8211 | /* iWMMXt control registers - p1, c0-3. */ | |
8212 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
8213 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
8214 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
8215 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
8216 | ||
8217 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
8218 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
8219 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
8220 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
8221 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
8222 | ||
8223 | /* XScale accumulator registers. */ | |
8224 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
8225 | }; | |
8226 | #undef REGDEF | |
8227 | #undef REGNUM | |
8228 | #undef REGSET | |
7ed4c4c5 | 8229 | |
c19d1205 ZW |
8230 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
8231 | within psr_required_here. */ | |
8232 | static const struct asm_psr psrs[] = | |
8233 | { | |
8234 | /* Backward compatibility notation. Note that "all" is no longer | |
8235 | truly all possible PSR bits. */ | |
8236 | {"all", PSR_c | PSR_f}, | |
8237 | {"flg", PSR_f}, | |
8238 | {"ctl", PSR_c}, | |
8239 | ||
8240 | /* Individual flags. */ | |
8241 | {"f", PSR_f}, | |
8242 | {"c", PSR_c}, | |
8243 | {"x", PSR_x}, | |
8244 | {"s", PSR_s}, | |
8245 | /* Combinations of flags. */ | |
8246 | {"fs", PSR_f | PSR_s}, | |
8247 | {"fx", PSR_f | PSR_x}, | |
8248 | {"fc", PSR_f | PSR_c}, | |
8249 | {"sf", PSR_s | PSR_f}, | |
8250 | {"sx", PSR_s | PSR_x}, | |
8251 | {"sc", PSR_s | PSR_c}, | |
8252 | {"xf", PSR_x | PSR_f}, | |
8253 | {"xs", PSR_x | PSR_s}, | |
8254 | {"xc", PSR_x | PSR_c}, | |
8255 | {"cf", PSR_c | PSR_f}, | |
8256 | {"cs", PSR_c | PSR_s}, | |
8257 | {"cx", PSR_c | PSR_x}, | |
8258 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
8259 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
8260 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
8261 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
8262 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
8263 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
8264 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
8265 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
8266 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
8267 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
8268 | {"scf", PSR_s | PSR_c | PSR_f}, | |
8269 | {"scx", PSR_s | PSR_c | PSR_x}, | |
8270 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
8271 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
8272 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
8273 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
8274 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
8275 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
8276 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
8277 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
8278 | {"csf", PSR_c | PSR_s | PSR_f}, | |
8279 | {"csx", PSR_c | PSR_s | PSR_x}, | |
8280 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
8281 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
8282 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
8283 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
8284 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
8285 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
8286 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
8287 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
8288 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
8289 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
8290 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
8291 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
8292 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
8293 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
8294 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
8295 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
8296 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
8297 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
8298 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
8299 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
8300 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
8301 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
8302 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
8303 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
8304 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
8305 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
8306 | }; | |
8307 | ||
8308 | /* Table of all shift-in-operand names. */ | |
8309 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 8310 | { |
c19d1205 ZW |
8311 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
8312 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
8313 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
8314 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
8315 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
8316 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
8317 | }; | |
b99bd4ef | 8318 | |
c19d1205 ZW |
8319 | /* Table of all explicit relocation names. */ |
8320 | #ifdef OBJ_ELF | |
8321 | static struct reloc_entry reloc_names[] = | |
8322 | { | |
8323 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
8324 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
8325 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
8326 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
8327 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
8328 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
8329 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
8330 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
8331 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
8332 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
8333 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32} | |
8334 | }; | |
8335 | #endif | |
b99bd4ef | 8336 | |
c19d1205 ZW |
8337 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
8338 | static const struct asm_cond conds[] = | |
8339 | { | |
8340 | {"eq", 0x0}, | |
8341 | {"ne", 0x1}, | |
8342 | {"cs", 0x2}, {"hs", 0x2}, | |
8343 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
8344 | {"mi", 0x4}, | |
8345 | {"pl", 0x5}, | |
8346 | {"vs", 0x6}, | |
8347 | {"vc", 0x7}, | |
8348 | {"hi", 0x8}, | |
8349 | {"ls", 0x9}, | |
8350 | {"ge", 0xa}, | |
8351 | {"lt", 0xb}, | |
8352 | {"gt", 0xc}, | |
8353 | {"le", 0xd}, | |
8354 | {"al", 0xe} | |
8355 | }; | |
bfae80f2 | 8356 | |
c19d1205 ZW |
8357 | /* Table of ARM-format instructions. */ |
8358 | ||
8359 | /* Macros for gluing together operand strings. N.B. In all cases | |
8360 | other than OPS0, the trailing OP_stop comes from default | |
8361 | zero-initialization of the unspecified elements of the array. */ | |
8362 | #define OPS0() { OP_stop, } | |
8363 | #define OPS1(a) { OP_##a, } | |
8364 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
8365 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
8366 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
8367 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
8368 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
8369 | ||
8370 | /* These macros abstract out the exact format of the mnemonic table and | |
8371 | save some repeated characters. */ | |
8372 | ||
8373 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
8374 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
8375 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ | |
1887dd22 | 8376 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8377 | |
8378 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
8379 | a T_MNEM_xyz enumerator. */ | |
8380 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
8381 | TxCE(mnem, aop, 0x##top, nops, ops, ae, te) | |
8382 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ | |
8383 | TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te) | |
8384 | ||
8385 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
8386 | infix after the third character. */ | |
8387 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
8388 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ | |
1887dd22 | 8389 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8390 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
8391 | TxC3(mnem, aop, 0x##top, nops, ops, ae, te) | |
8392 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ | |
8393 | TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te) | |
8394 | ||
8395 | /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to | |
8396 | appear in the condition table. */ | |
8397 | #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ | |
8398 | { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ | |
1887dd22 | 8399 | 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8400 | |
8401 | #define TxCM(m1, m2, op, top, nops, ops, ae, te) \ | |
8402 | TxCM_(m1, , m2, op, top, nops, ops, ae, te), \ | |
8403 | TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \ | |
8404 | TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \ | |
8405 | TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \ | |
8406 | TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \ | |
8407 | TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \ | |
8408 | TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \ | |
8409 | TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \ | |
8410 | TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \ | |
8411 | TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \ | |
8412 | TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \ | |
8413 | TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \ | |
8414 | TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \ | |
8415 | TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \ | |
8416 | TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \ | |
8417 | TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \ | |
8418 | TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \ | |
8419 | TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \ | |
8420 | TxCM_(m1, al, m2, op, top, nops, ops, ae, te) | |
8421 | ||
8422 | #define TCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
8423 | TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te) | |
8424 | #define tCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
8425 | TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te) | |
8426 | ||
8427 | /* Mnemonic that cannot be conditionalized. The ARM condition-code | |
8428 | field is still 0xE. */ | |
8429 | #define TUE(mnem, op, top, nops, ops, ae, te) \ | |
8430 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ | |
1887dd22 | 8431 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8432 | |
8433 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM | |
8434 | condition code field. */ | |
8435 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
8436 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ | |
1887dd22 | 8437 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
8438 | |
8439 | /* ARM-only variants of all the above. */ | |
6a86118a NC |
8440 | #define CE(mnem, op, nops, ops, ae) \ |
8441 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
8442 | ||
8443 | #define C3(mnem, op, nops, ops, ae) \ | |
8444 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
8445 | ||
8f06b2d8 PB |
8446 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
8447 | #define cCE(mnem, op, nops, ops, ae) \ | |
8448 | { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } | |
8449 | ||
8450 | #define cC3(mnem, op, nops, ops, ae) \ | |
8451 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } | |
8452 | ||
6a86118a NC |
8453 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
8454 | { #m1 #m2 #m3, OPS##nops ops, \ | |
8455 | sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ | |
8456 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
8457 | ||
8458 | #define CM(m1, m2, op, nops, ops, ae) \ | |
8459 | xCM_(m1, , m2, op, nops, ops, ae), \ | |
8460 | xCM_(m1, eq, m2, op, nops, ops, ae), \ | |
8461 | xCM_(m1, ne, m2, op, nops, ops, ae), \ | |
8462 | xCM_(m1, cs, m2, op, nops, ops, ae), \ | |
8463 | xCM_(m1, hs, m2, op, nops, ops, ae), \ | |
8464 | xCM_(m1, cc, m2, op, nops, ops, ae), \ | |
8465 | xCM_(m1, ul, m2, op, nops, ops, ae), \ | |
8466 | xCM_(m1, lo, m2, op, nops, ops, ae), \ | |
8467 | xCM_(m1, mi, m2, op, nops, ops, ae), \ | |
8468 | xCM_(m1, pl, m2, op, nops, ops, ae), \ | |
8469 | xCM_(m1, vs, m2, op, nops, ops, ae), \ | |
8470 | xCM_(m1, vc, m2, op, nops, ops, ae), \ | |
8471 | xCM_(m1, hi, m2, op, nops, ops, ae), \ | |
8472 | xCM_(m1, ls, m2, op, nops, ops, ae), \ | |
8473 | xCM_(m1, ge, m2, op, nops, ops, ae), \ | |
8474 | xCM_(m1, lt, m2, op, nops, ops, ae), \ | |
8475 | xCM_(m1, gt, m2, op, nops, ops, ae), \ | |
8476 | xCM_(m1, le, m2, op, nops, ops, ae), \ | |
8477 | xCM_(m1, al, m2, op, nops, ops, ae) | |
8478 | ||
8479 | #define UE(mnem, op, nops, ops, ae) \ | |
8480 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
8481 | ||
8482 | #define UF(mnem, op, nops, ops, ae) \ | |
8483 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
8484 | ||
c19d1205 ZW |
8485 | #define do_0 0 |
8486 | ||
8487 | /* Thumb-only, unconditional. */ | |
8488 | #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te) | |
8489 | ||
8490 | /* ARM-only, takes either a suffix or a position-3 infix | |
8491 | (for an FPA corner case). */ | |
8492 | #define C3E(mnem, op, nops, ops, ae) \ | |
8493 | { #mnem, OPS##nops ops, OT_csuf_or_in3, 0x##op, 0, ARM_VARIANT, 0, do_##ae, 0 } | |
bfae80f2 | 8494 | |
c19d1205 | 8495 | static const struct asm_opcode insns[] = |
bfae80f2 | 8496 | { |
c19d1205 ZW |
8497 | #define ARM_VARIANT ARM_EXT_V1 /* Core ARM Instructions. */ |
8498 | #define THUMB_VARIANT ARM_EXT_V4T | |
8499 | tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c), | |
8500 | tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
8501 | tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
8502 | tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
8503 | tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
8504 | tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
8505 | tCE(add, 0800000, add, 3, (RR, oRR, SH), arit, t_add_sub), | |
8506 | tC3(adds, 0900000, adds, 3, (RR, oRR, SH), arit, t_add_sub), | |
8507 | tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
8508 | tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
8509 | tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
8510 | tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
8511 | tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
8512 | tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
8513 | tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3), | |
8514 | tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3), | |
8515 | ||
8516 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
8517 | for setting PSR flag bits. They are obsolete in V6 and do not | |
8518 | have Thumb equivalents. */ | |
8519 | tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), | |
8520 | tC3(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), | |
8521 | C3(tstp, 110f000, 2, (RR, SH), cmp), | |
8522 | tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
8523 | tC3(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
8524 | C3(cmpp, 150f000, 2, (RR, SH), cmp), | |
8525 | tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
8526 | tC3(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
8527 | C3(cmnp, 170f000, 2, (RR, SH), cmp), | |
8528 | ||
8529 | tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp), | |
8530 | tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp), | |
8531 | tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst), | |
8532 | tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst), | |
8533 | ||
8534 | tCE(ldr, 4100000, ldr, 2, (RR, ADDR), ldst, t_ldst), | |
8535 | tC3(ldrb, 4500000, ldrb, 2, (RR, ADDR), ldst, t_ldst), | |
8536 | tCE(str, 4000000, str, 2, (RR, ADDR), ldst, t_ldst), | |
8537 | tC3(strb, 4400000, strb, 2, (RR, ADDR), ldst, t_ldst), | |
8538 | ||
8539 | tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
8540 | tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
8541 | tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
8542 | tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
8543 | ||
8544 | TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi), | |
0110f2b8 | 8545 | tCE(b, a000000, b, 1, (EXPr), branch, t_branch), |
2fc8bdac | 8546 | TCE(bl, b000000, f000f800, 1, (EXPr), branch, t_branch23), |
bfae80f2 | 8547 | |
c19d1205 | 8548 | /* Pseudo ops. */ |
e9f89963 | 8549 | tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac ZW |
8550 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
8551 | tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop), | |
c19d1205 ZW |
8552 | |
8553 | /* Thumb-compatibility pseudo ops. */ | |
8554 | tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift), | |
8555 | tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift), | |
8556 | tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift), | |
8557 | tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
8558 | tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift), | |
2fc8bdac | 8559 | tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift), |
c19d1205 ZW |
8560 | tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift), |
8561 | tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift), | |
8562 | tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg), | |
8563 | tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg), | |
8564 | tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop), | |
8565 | tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop), | |
8566 | ||
8567 | #undef THUMB_VARIANT | |
8568 | #define THUMB_VARIANT ARM_EXT_V6 | |
2fc8bdac | 8569 | TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
8570 | |
8571 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
8572 | #undef THUMB_VARIANT | |
8573 | #define THUMB_VARIANT ARM_EXT_V6T2 | |
8574 | TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), | |
8575 | TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
8576 | TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
8577 | TC3(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
8578 | C3(teqp, 130f000, 2, (RR, SH), cmp), | |
8579 | ||
8580 | TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt), | |
8581 | TC3(ldrbt, 4700000, f8300e00, 2, (RR, ADDR), ldstt, t_ldstt), | |
8582 | TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt), | |
8583 | TC3(strbt, 4600000, f8200e00, 2, (RR, ADDR), ldstt, t_ldstt), | |
8584 | ||
9c3c69f2 PB |
8585 | TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
8586 | TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 8587 | |
9c3c69f2 PB |
8588 | TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
8589 | TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
8590 | |
8591 | /* V1 instructions with no Thumb analogue at all. */ | |
8592 | CE(rsc, 0e00000, 3, (RR, oRR, SH), arit), | |
8593 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), | |
8594 | ||
8595 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
8596 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
8597 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
8598 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
8599 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
8600 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
8601 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
8602 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
8603 | ||
8604 | #undef ARM_VARIANT | |
8605 | #define ARM_VARIANT ARM_EXT_V2 /* ARM 2 - multiplies. */ | |
8606 | #undef THUMB_VARIANT | |
8607 | #define THUMB_VARIANT ARM_EXT_V4T | |
8608 | tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
8609 | tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
8610 | ||
8611 | #undef THUMB_VARIANT | |
8612 | #define THUMB_VARIANT ARM_EXT_V6T2 | |
8613 | TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), | |
8614 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), | |
8615 | ||
8616 | /* Generic coprocessor instructions. */ | |
8617 | TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
8618 | TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8619 | TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8620 | TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8621 | TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8622 | TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
8623 | TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
8624 | ||
8625 | #undef ARM_VARIANT | |
8626 | #define ARM_VARIANT ARM_EXT_V2S /* ARM 3 - swp instructions. */ | |
8627 | CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), | |
8628 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), | |
8629 | ||
8630 | #undef ARM_VARIANT | |
8631 | #define ARM_VARIANT ARM_EXT_V3 /* ARM 6 Status register instructions. */ | |
8632 | TCE(mrs, 10f0000, f3ef8000, 2, (RR, PSR), mrs, t_mrs), | |
8633 | TCE(msr, 120f000, f3808000, 2, (PSR, RR_EXi), msr, t_msr), | |
8634 | ||
8635 | #undef ARM_VARIANT | |
8636 | #define ARM_VARIANT ARM_EXT_V3M /* ARM 7M long multiplies. */ | |
8637 | TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
8638 | CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
8639 | TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
8640 | CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
8641 | TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
8642 | CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
8643 | TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
8644 | CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
8645 | ||
8646 | #undef ARM_VARIANT | |
8647 | #define ARM_VARIANT ARM_EXT_V4 /* ARM Architecture 4. */ | |
8648 | #undef THUMB_VARIANT | |
8649 | #define THUMB_VARIANT ARM_EXT_V4T | |
8650 | tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDR), ldstv4, t_ldst), | |
8651 | tC3(strh, 00000b0, strh, 2, (RR, ADDR), ldstv4, t_ldst), | |
8652 | tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst), | |
8653 | tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst), | |
8654 | tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst), | |
8655 | tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst), | |
8656 | ||
8657 | #undef ARM_VARIANT | |
8658 | #define ARM_VARIANT ARM_EXT_V4T|ARM_EXT_V5 | |
8659 | /* ARM Architecture 4T. */ | |
8660 | /* Note: bx (and blx) are required on V5, even if the processor does | |
8661 | not support Thumb. */ | |
8662 | TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx), | |
8663 | ||
8664 | #undef ARM_VARIANT | |
8665 | #define ARM_VARIANT ARM_EXT_V5 /* ARM Architecture 5T. */ | |
8666 | #undef THUMB_VARIANT | |
8667 | #define THUMB_VARIANT ARM_EXT_V5T | |
8668 | /* Note: blx has 2 variants; the .value coded here is for | |
8669 | BLX(2). Only this variant has conditional execution. */ | |
8670 | TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx), | |
8671 | TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
8672 | ||
8673 | #undef THUMB_VARIANT | |
8674 | #define THUMB_VARIANT ARM_EXT_V6T2 | |
8675 | TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), | |
8676 | TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8677 | TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8678 | TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8679 | TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDR), lstc, lstc), | |
8680 | TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
8681 | TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
8682 | TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
8683 | ||
8684 | #undef ARM_VARIANT | |
8685 | #define ARM_VARIANT ARM_EXT_V5ExP /* ARM Architecture 5TExP. */ | |
8686 | TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
8687 | TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
8688 | TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
8689 | TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
8690 | ||
8691 | TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
8692 | TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
8693 | ||
8694 | TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
8695 | TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
8696 | TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
8697 | TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
8698 | ||
8699 | TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8700 | TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8701 | TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8702 | TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8703 | ||
8704 | TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8705 | TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8706 | ||
8707 | TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
8708 | TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
8709 | TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
8710 | TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), | |
8711 | ||
8712 | #undef ARM_VARIANT | |
8713 | #define ARM_VARIANT ARM_EXT_V5E /* ARM Architecture 5TE. */ | |
8714 | TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld), | |
8715 | TC3(ldrd, 00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd), | |
8716 | TC3(strd, 00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd), | |
8717 | ||
8718 | TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
8719 | TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
8720 | ||
8721 | #undef ARM_VARIANT | |
8722 | #define ARM_VARIANT ARM_EXT_V5J /* ARM Architecture 5TEJ. */ | |
8723 | TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), | |
8724 | ||
8725 | #undef ARM_VARIANT | |
8726 | #define ARM_VARIANT ARM_EXT_V6 /* ARM V6. */ | |
8727 | #undef THUMB_VARIANT | |
8728 | #define THUMB_VARIANT ARM_EXT_V6 | |
8729 | TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
8730 | TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
8731 | tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
8732 | tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
8733 | tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
8734 | tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
8735 | tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
8736 | tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
8737 | tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
8738 | TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend), | |
8739 | ||
8740 | #undef THUMB_VARIANT | |
8741 | #define THUMB_VARIANT ARM_EXT_V6T2 | |
8742 | TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, imm0), | |
8743 | TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex), | |
8744 | TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
8745 | TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
8746 | TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), | |
8747 | TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
8748 | TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8749 | TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8750 | TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8751 | TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8752 | TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8753 | TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8754 | TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8755 | TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8756 | TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8757 | TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8758 | TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8759 | TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8760 | TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8761 | TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8762 | TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8763 | TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8764 | TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8765 | TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8766 | TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8767 | TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8768 | TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8769 | TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8770 | TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8771 | TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8772 | TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8773 | TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8774 | TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8775 | TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8776 | TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8777 | TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8778 | TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8779 | TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8780 | TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8781 | TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8782 | TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8783 | TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8784 | TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
8785 | UF(rfeib, 9900a00, 1, (RRw), rfe), | |
8786 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
8787 | TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
8788 | TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
8789 | UF(rfefa, 9900a00, 1, (RRw), rfe), | |
8790 | UF(rfeea, 8100a00, 1, (RRw), rfe), | |
8791 | TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
8792 | TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
8793 | TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
8794 | TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
8795 | TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
8796 | TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
8797 | TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
8798 | TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
8799 | TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
8800 | TCE(sel, 68000b0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
8801 | TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
8802 | TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
8803 | TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
8804 | TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
8805 | TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
8806 | TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
8807 | TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
8808 | TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
8809 | TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
8810 | TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
8811 | TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
8812 | TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
8813 | TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8814 | TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8815 | TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8816 | TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8817 | TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8818 | TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8819 | TUF(srsia, 8cd0500, e980c000, 1, (I31w), srs, srs), | |
8820 | UF(srsib, 9cd0500, 1, (I31w), srs), | |
8821 | UF(srsda, 84d0500, 1, (I31w), srs), | |
8822 | TUF(srsdb, 94d0500, e800c000, 1, (I31w), srs, srs), | |
8823 | TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), | |
8824 | TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), | |
8825 | TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex), | |
8826 | TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
8827 | TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
8828 | TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
8829 | TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
8830 | TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), | |
8831 | ||
8832 | #undef ARM_VARIANT | |
8833 | #define ARM_VARIANT ARM_EXT_V6K | |
8834 | #undef THUMB_VARIANT | |
8835 | #define THUMB_VARIANT ARM_EXT_V6K | |
8836 | tCE(yield, 320f001, yield, 0, (), noargs, t_hint), | |
8837 | tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint), | |
8838 | tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint), | |
8839 | tCE(sev, 320f004, sev, 0, (), noargs, t_hint), | |
8840 | ||
8841 | #undef THUMB_VARIANT | |
8842 | #define THUMB_VARIANT ARM_EXT_V6T2 | |
8843 | TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
8844 | TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), | |
8845 | TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd), | |
8846 | TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), | |
8847 | TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), | |
8848 | TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd), | |
8849 | TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs), | |
8850 | ||
8851 | #undef ARM_VARIANT | |
8852 | #define ARM_VARIANT ARM_EXT_V6Z | |
3eb17e6b | 8853 | TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 ZW |
8854 | |
8855 | #undef ARM_VARIANT | |
8856 | #define ARM_VARIANT ARM_EXT_V6T2 | |
8857 | TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), | |
8858 | TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
8859 | TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
8860 | TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
8861 | ||
8862 | TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), | |
8863 | TCE(movw, 3000000, f2400000, 2, (RRnpc, Iffff), mov16, t_mov16), | |
8864 | TCE(movt, 3400000, f2c00000, 2, (RRnpc, Iffff), mov16, t_mov16), | |
8865 | TCE(rbit, 3ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), | |
8866 | ||
8867 | TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
8868 | TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
8869 | TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
8870 | TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt), | |
8871 | ||
8872 | UT(cbnz, b900, 2, (RR, EXP), t_czb), | |
8873 | UT(cbz, b100, 2, (RR, EXP), t_czb), | |
8874 | /* ARM does not really have an IT instruction. */ | |
8875 | TUE(it, 0, bf08, 1, (COND), it, t_it), | |
8876 | TUE(itt, 0, bf0c, 1, (COND), it, t_it), | |
8877 | TUE(ite, 0, bf04, 1, (COND), it, t_it), | |
8878 | TUE(ittt, 0, bf0e, 1, (COND), it, t_it), | |
8879 | TUE(itet, 0, bf06, 1, (COND), it, t_it), | |
8880 | TUE(itte, 0, bf0a, 1, (COND), it, t_it), | |
8881 | TUE(itee, 0, bf02, 1, (COND), it, t_it), | |
8882 | TUE(itttt, 0, bf0f, 1, (COND), it, t_it), | |
8883 | TUE(itett, 0, bf07, 1, (COND), it, t_it), | |
8884 | TUE(ittet, 0, bf0b, 1, (COND), it, t_it), | |
8885 | TUE(iteet, 0, bf03, 1, (COND), it, t_it), | |
8886 | TUE(ittte, 0, bf0d, 1, (COND), it, t_it), | |
8887 | TUE(itete, 0, bf05, 1, (COND), it, t_it), | |
8888 | TUE(ittee, 0, bf09, 1, (COND), it, t_it), | |
8889 | TUE(iteee, 0, bf01, 1, (COND), it, t_it), | |
8890 | ||
92e90b6e PB |
8891 | /* Thumb2 only instructions. */ |
8892 | #undef ARM_VARIANT | |
8893 | #define ARM_VARIANT 0 | |
8894 | ||
8895 | TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
8896 | TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
8897 | TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb), | |
8898 | TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb), | |
8899 | ||
c19d1205 ZW |
8900 | #undef ARM_VARIANT |
8901 | #define ARM_VARIANT FPU_FPA_EXT_V1 /* Core FPA instruction set (V1). */ | |
8f06b2d8 PB |
8902 | cCE(wfs, e200110, 1, (RR), rd), |
8903 | cCE(rfs, e300110, 1, (RR), rd), | |
8904 | cCE(wfc, e400110, 1, (RR), rd), | |
8905 | cCE(rfc, e500110, 1, (RR), rd), | |
8906 | ||
8907 | cC3(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr), | |
8908 | cC3(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr), | |
8909 | cC3(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr), | |
8910 | cC3(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr), | |
8911 | ||
8912 | cC3(stfs, c000100, 2, (RF, ADDR), rd_cpaddr), | |
8913 | cC3(stfd, c008100, 2, (RF, ADDR), rd_cpaddr), | |
8914 | cC3(stfe, c400100, 2, (RF, ADDR), rd_cpaddr), | |
8915 | cC3(stfp, c408100, 2, (RF, ADDR), rd_cpaddr), | |
8916 | ||
8917 | cC3(mvfs, e008100, 2, (RF, RF_IF), rd_rm), | |
8918 | cC3(mvfsp, e008120, 2, (RF, RF_IF), rd_rm), | |
8919 | cC3(mvfsm, e008140, 2, (RF, RF_IF), rd_rm), | |
8920 | cC3(mvfsz, e008160, 2, (RF, RF_IF), rd_rm), | |
8921 | cC3(mvfd, e008180, 2, (RF, RF_IF), rd_rm), | |
8922 | cC3(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm), | |
8923 | cC3(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm), | |
8924 | cC3(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm), | |
8925 | cC3(mvfe, e088100, 2, (RF, RF_IF), rd_rm), | |
8926 | cC3(mvfep, e088120, 2, (RF, RF_IF), rd_rm), | |
8927 | cC3(mvfem, e088140, 2, (RF, RF_IF), rd_rm), | |
8928 | cC3(mvfez, e088160, 2, (RF, RF_IF), rd_rm), | |
8929 | ||
8930 | cC3(mnfs, e108100, 2, (RF, RF_IF), rd_rm), | |
8931 | cC3(mnfsp, e108120, 2, (RF, RF_IF), rd_rm), | |
8932 | cC3(mnfsm, e108140, 2, (RF, RF_IF), rd_rm), | |
8933 | cC3(mnfsz, e108160, 2, (RF, RF_IF), rd_rm), | |
8934 | cC3(mnfd, e108180, 2, (RF, RF_IF), rd_rm), | |
8935 | cC3(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm), | |
8936 | cC3(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm), | |
8937 | cC3(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm), | |
8938 | cC3(mnfe, e188100, 2, (RF, RF_IF), rd_rm), | |
8939 | cC3(mnfep, e188120, 2, (RF, RF_IF), rd_rm), | |
8940 | cC3(mnfem, e188140, 2, (RF, RF_IF), rd_rm), | |
8941 | cC3(mnfez, e188160, 2, (RF, RF_IF), rd_rm), | |
8942 | ||
8943 | cC3(abss, e208100, 2, (RF, RF_IF), rd_rm), | |
8944 | cC3(abssp, e208120, 2, (RF, RF_IF), rd_rm), | |
8945 | cC3(abssm, e208140, 2, (RF, RF_IF), rd_rm), | |
8946 | cC3(abssz, e208160, 2, (RF, RF_IF), rd_rm), | |
8947 | cC3(absd, e208180, 2, (RF, RF_IF), rd_rm), | |
8948 | cC3(absdp, e2081a0, 2, (RF, RF_IF), rd_rm), | |
8949 | cC3(absdm, e2081c0, 2, (RF, RF_IF), rd_rm), | |
8950 | cC3(absdz, e2081e0, 2, (RF, RF_IF), rd_rm), | |
8951 | cC3(abse, e288100, 2, (RF, RF_IF), rd_rm), | |
8952 | cC3(absep, e288120, 2, (RF, RF_IF), rd_rm), | |
8953 | cC3(absem, e288140, 2, (RF, RF_IF), rd_rm), | |
8954 | cC3(absez, e288160, 2, (RF, RF_IF), rd_rm), | |
8955 | ||
8956 | cC3(rnds, e308100, 2, (RF, RF_IF), rd_rm), | |
8957 | cC3(rndsp, e308120, 2, (RF, RF_IF), rd_rm), | |
8958 | cC3(rndsm, e308140, 2, (RF, RF_IF), rd_rm), | |
8959 | cC3(rndsz, e308160, 2, (RF, RF_IF), rd_rm), | |
8960 | cC3(rndd, e308180, 2, (RF, RF_IF), rd_rm), | |
8961 | cC3(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm), | |
8962 | cC3(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm), | |
8963 | cC3(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm), | |
8964 | cC3(rnde, e388100, 2, (RF, RF_IF), rd_rm), | |
8965 | cC3(rndep, e388120, 2, (RF, RF_IF), rd_rm), | |
8966 | cC3(rndem, e388140, 2, (RF, RF_IF), rd_rm), | |
8967 | cC3(rndez, e388160, 2, (RF, RF_IF), rd_rm), | |
8968 | ||
8969 | cC3(sqts, e408100, 2, (RF, RF_IF), rd_rm), | |
8970 | cC3(sqtsp, e408120, 2, (RF, RF_IF), rd_rm), | |
8971 | cC3(sqtsm, e408140, 2, (RF, RF_IF), rd_rm), | |
8972 | cC3(sqtsz, e408160, 2, (RF, RF_IF), rd_rm), | |
8973 | cC3(sqtd, e408180, 2, (RF, RF_IF), rd_rm), | |
8974 | cC3(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm), | |
8975 | cC3(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm), | |
8976 | cC3(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm), | |
8977 | cC3(sqte, e488100, 2, (RF, RF_IF), rd_rm), | |
8978 | cC3(sqtep, e488120, 2, (RF, RF_IF), rd_rm), | |
8979 | cC3(sqtem, e488140, 2, (RF, RF_IF), rd_rm), | |
8980 | cC3(sqtez, e488160, 2, (RF, RF_IF), rd_rm), | |
8981 | ||
8982 | cC3(logs, e508100, 2, (RF, RF_IF), rd_rm), | |
8983 | cC3(logsp, e508120, 2, (RF, RF_IF), rd_rm), | |
8984 | cC3(logsm, e508140, 2, (RF, RF_IF), rd_rm), | |
8985 | cC3(logsz, e508160, 2, (RF, RF_IF), rd_rm), | |
8986 | cC3(logd, e508180, 2, (RF, RF_IF), rd_rm), | |
8987 | cC3(logdp, e5081a0, 2, (RF, RF_IF), rd_rm), | |
8988 | cC3(logdm, e5081c0, 2, (RF, RF_IF), rd_rm), | |
8989 | cC3(logdz, e5081e0, 2, (RF, RF_IF), rd_rm), | |
8990 | cC3(loge, e588100, 2, (RF, RF_IF), rd_rm), | |
8991 | cC3(logep, e588120, 2, (RF, RF_IF), rd_rm), | |
8992 | cC3(logem, e588140, 2, (RF, RF_IF), rd_rm), | |
8993 | cC3(logez, e588160, 2, (RF, RF_IF), rd_rm), | |
8994 | ||
8995 | cC3(lgns, e608100, 2, (RF, RF_IF), rd_rm), | |
8996 | cC3(lgnsp, e608120, 2, (RF, RF_IF), rd_rm), | |
8997 | cC3(lgnsm, e608140, 2, (RF, RF_IF), rd_rm), | |
8998 | cC3(lgnsz, e608160, 2, (RF, RF_IF), rd_rm), | |
8999 | cC3(lgnd, e608180, 2, (RF, RF_IF), rd_rm), | |
9000 | cC3(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm), | |
9001 | cC3(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm), | |
9002 | cC3(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm), | |
9003 | cC3(lgne, e688100, 2, (RF, RF_IF), rd_rm), | |
9004 | cC3(lgnep, e688120, 2, (RF, RF_IF), rd_rm), | |
9005 | cC3(lgnem, e688140, 2, (RF, RF_IF), rd_rm), | |
9006 | cC3(lgnez, e688160, 2, (RF, RF_IF), rd_rm), | |
9007 | ||
9008 | cC3(exps, e708100, 2, (RF, RF_IF), rd_rm), | |
9009 | cC3(expsp, e708120, 2, (RF, RF_IF), rd_rm), | |
9010 | cC3(expsm, e708140, 2, (RF, RF_IF), rd_rm), | |
9011 | cC3(expsz, e708160, 2, (RF, RF_IF), rd_rm), | |
9012 | cC3(expd, e708180, 2, (RF, RF_IF), rd_rm), | |
9013 | cC3(expdp, e7081a0, 2, (RF, RF_IF), rd_rm), | |
9014 | cC3(expdm, e7081c0, 2, (RF, RF_IF), rd_rm), | |
9015 | cC3(expdz, e7081e0, 2, (RF, RF_IF), rd_rm), | |
9016 | cC3(expe, e788100, 2, (RF, RF_IF), rd_rm), | |
9017 | cC3(expep, e788120, 2, (RF, RF_IF), rd_rm), | |
9018 | cC3(expem, e788140, 2, (RF, RF_IF), rd_rm), | |
9019 | cC3(expdz, e788160, 2, (RF, RF_IF), rd_rm), | |
9020 | ||
9021 | cC3(sins, e808100, 2, (RF, RF_IF), rd_rm), | |
9022 | cC3(sinsp, e808120, 2, (RF, RF_IF), rd_rm), | |
9023 | cC3(sinsm, e808140, 2, (RF, RF_IF), rd_rm), | |
9024 | cC3(sinsz, e808160, 2, (RF, RF_IF), rd_rm), | |
9025 | cC3(sind, e808180, 2, (RF, RF_IF), rd_rm), | |
9026 | cC3(sindp, e8081a0, 2, (RF, RF_IF), rd_rm), | |
9027 | cC3(sindm, e8081c0, 2, (RF, RF_IF), rd_rm), | |
9028 | cC3(sindz, e8081e0, 2, (RF, RF_IF), rd_rm), | |
9029 | cC3(sine, e888100, 2, (RF, RF_IF), rd_rm), | |
9030 | cC3(sinep, e888120, 2, (RF, RF_IF), rd_rm), | |
9031 | cC3(sinem, e888140, 2, (RF, RF_IF), rd_rm), | |
9032 | cC3(sinez, e888160, 2, (RF, RF_IF), rd_rm), | |
9033 | ||
9034 | cC3(coss, e908100, 2, (RF, RF_IF), rd_rm), | |
9035 | cC3(cossp, e908120, 2, (RF, RF_IF), rd_rm), | |
9036 | cC3(cossm, e908140, 2, (RF, RF_IF), rd_rm), | |
9037 | cC3(cossz, e908160, 2, (RF, RF_IF), rd_rm), | |
9038 | cC3(cosd, e908180, 2, (RF, RF_IF), rd_rm), | |
9039 | cC3(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm), | |
9040 | cC3(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm), | |
9041 | cC3(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm), | |
9042 | cC3(cose, e988100, 2, (RF, RF_IF), rd_rm), | |
9043 | cC3(cosep, e988120, 2, (RF, RF_IF), rd_rm), | |
9044 | cC3(cosem, e988140, 2, (RF, RF_IF), rd_rm), | |
9045 | cC3(cosez, e988160, 2, (RF, RF_IF), rd_rm), | |
9046 | ||
9047 | cC3(tans, ea08100, 2, (RF, RF_IF), rd_rm), | |
9048 | cC3(tansp, ea08120, 2, (RF, RF_IF), rd_rm), | |
9049 | cC3(tansm, ea08140, 2, (RF, RF_IF), rd_rm), | |
9050 | cC3(tansz, ea08160, 2, (RF, RF_IF), rd_rm), | |
9051 | cC3(tand, ea08180, 2, (RF, RF_IF), rd_rm), | |
9052 | cC3(tandp, ea081a0, 2, (RF, RF_IF), rd_rm), | |
9053 | cC3(tandm, ea081c0, 2, (RF, RF_IF), rd_rm), | |
9054 | cC3(tandz, ea081e0, 2, (RF, RF_IF), rd_rm), | |
9055 | cC3(tane, ea88100, 2, (RF, RF_IF), rd_rm), | |
9056 | cC3(tanep, ea88120, 2, (RF, RF_IF), rd_rm), | |
9057 | cC3(tanem, ea88140, 2, (RF, RF_IF), rd_rm), | |
9058 | cC3(tanez, ea88160, 2, (RF, RF_IF), rd_rm), | |
9059 | ||
9060 | cC3(asns, eb08100, 2, (RF, RF_IF), rd_rm), | |
9061 | cC3(asnsp, eb08120, 2, (RF, RF_IF), rd_rm), | |
9062 | cC3(asnsm, eb08140, 2, (RF, RF_IF), rd_rm), | |
9063 | cC3(asnsz, eb08160, 2, (RF, RF_IF), rd_rm), | |
9064 | cC3(asnd, eb08180, 2, (RF, RF_IF), rd_rm), | |
9065 | cC3(asndp, eb081a0, 2, (RF, RF_IF), rd_rm), | |
9066 | cC3(asndm, eb081c0, 2, (RF, RF_IF), rd_rm), | |
9067 | cC3(asndz, eb081e0, 2, (RF, RF_IF), rd_rm), | |
9068 | cC3(asne, eb88100, 2, (RF, RF_IF), rd_rm), | |
9069 | cC3(asnep, eb88120, 2, (RF, RF_IF), rd_rm), | |
9070 | cC3(asnem, eb88140, 2, (RF, RF_IF), rd_rm), | |
9071 | cC3(asnez, eb88160, 2, (RF, RF_IF), rd_rm), | |
9072 | ||
9073 | cC3(acss, ec08100, 2, (RF, RF_IF), rd_rm), | |
9074 | cC3(acssp, ec08120, 2, (RF, RF_IF), rd_rm), | |
9075 | cC3(acssm, ec08140, 2, (RF, RF_IF), rd_rm), | |
9076 | cC3(acssz, ec08160, 2, (RF, RF_IF), rd_rm), | |
9077 | cC3(acsd, ec08180, 2, (RF, RF_IF), rd_rm), | |
9078 | cC3(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm), | |
9079 | cC3(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm), | |
9080 | cC3(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm), | |
9081 | cC3(acse, ec88100, 2, (RF, RF_IF), rd_rm), | |
9082 | cC3(acsep, ec88120, 2, (RF, RF_IF), rd_rm), | |
9083 | cC3(acsem, ec88140, 2, (RF, RF_IF), rd_rm), | |
9084 | cC3(acsez, ec88160, 2, (RF, RF_IF), rd_rm), | |
9085 | ||
9086 | cC3(atns, ed08100, 2, (RF, RF_IF), rd_rm), | |
9087 | cC3(atnsp, ed08120, 2, (RF, RF_IF), rd_rm), | |
9088 | cC3(atnsm, ed08140, 2, (RF, RF_IF), rd_rm), | |
9089 | cC3(atnsz, ed08160, 2, (RF, RF_IF), rd_rm), | |
9090 | cC3(atnd, ed08180, 2, (RF, RF_IF), rd_rm), | |
9091 | cC3(atndp, ed081a0, 2, (RF, RF_IF), rd_rm), | |
9092 | cC3(atndm, ed081c0, 2, (RF, RF_IF), rd_rm), | |
9093 | cC3(atndz, ed081e0, 2, (RF, RF_IF), rd_rm), | |
9094 | cC3(atne, ed88100, 2, (RF, RF_IF), rd_rm), | |
9095 | cC3(atnep, ed88120, 2, (RF, RF_IF), rd_rm), | |
9096 | cC3(atnem, ed88140, 2, (RF, RF_IF), rd_rm), | |
9097 | cC3(atnez, ed88160, 2, (RF, RF_IF), rd_rm), | |
9098 | ||
9099 | cC3(urds, ee08100, 2, (RF, RF_IF), rd_rm), | |
9100 | cC3(urdsp, ee08120, 2, (RF, RF_IF), rd_rm), | |
9101 | cC3(urdsm, ee08140, 2, (RF, RF_IF), rd_rm), | |
9102 | cC3(urdsz, ee08160, 2, (RF, RF_IF), rd_rm), | |
9103 | cC3(urdd, ee08180, 2, (RF, RF_IF), rd_rm), | |
9104 | cC3(urddp, ee081a0, 2, (RF, RF_IF), rd_rm), | |
9105 | cC3(urddm, ee081c0, 2, (RF, RF_IF), rd_rm), | |
9106 | cC3(urddz, ee081e0, 2, (RF, RF_IF), rd_rm), | |
9107 | cC3(urde, ee88100, 2, (RF, RF_IF), rd_rm), | |
9108 | cC3(urdep, ee88120, 2, (RF, RF_IF), rd_rm), | |
9109 | cC3(urdem, ee88140, 2, (RF, RF_IF), rd_rm), | |
9110 | cC3(urdez, ee88160, 2, (RF, RF_IF), rd_rm), | |
9111 | ||
9112 | cC3(nrms, ef08100, 2, (RF, RF_IF), rd_rm), | |
9113 | cC3(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm), | |
9114 | cC3(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm), | |
9115 | cC3(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm), | |
9116 | cC3(nrmd, ef08180, 2, (RF, RF_IF), rd_rm), | |
9117 | cC3(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm), | |
9118 | cC3(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm), | |
9119 | cC3(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm), | |
9120 | cC3(nrme, ef88100, 2, (RF, RF_IF), rd_rm), | |
9121 | cC3(nrmep, ef88120, 2, (RF, RF_IF), rd_rm), | |
9122 | cC3(nrmem, ef88140, 2, (RF, RF_IF), rd_rm), | |
9123 | cC3(nrmez, ef88160, 2, (RF, RF_IF), rd_rm), | |
9124 | ||
9125 | cC3(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9126 | cC3(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9127 | cC3(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9128 | cC3(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9129 | cC3(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9130 | cC3(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9131 | cC3(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9132 | cC3(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9133 | cC3(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9134 | cC3(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9135 | cC3(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9136 | cC3(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9137 | ||
9138 | cC3(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9139 | cC3(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9140 | cC3(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9141 | cC3(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9142 | cC3(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9143 | cC3(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9144 | cC3(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9145 | cC3(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9146 | cC3(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9147 | cC3(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9148 | cC3(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9149 | cC3(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9150 | ||
9151 | cC3(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9152 | cC3(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9153 | cC3(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9154 | cC3(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9155 | cC3(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9156 | cC3(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9157 | cC3(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9158 | cC3(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9159 | cC3(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9160 | cC3(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9161 | cC3(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9162 | cC3(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9163 | ||
9164 | cC3(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9165 | cC3(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9166 | cC3(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9167 | cC3(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9168 | cC3(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9169 | cC3(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9170 | cC3(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9171 | cC3(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9172 | cC3(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9173 | cC3(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9174 | cC3(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9175 | cC3(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9176 | ||
9177 | cC3(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9178 | cC3(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9179 | cC3(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9180 | cC3(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9181 | cC3(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9182 | cC3(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9183 | cC3(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9184 | cC3(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9185 | cC3(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9186 | cC3(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9187 | cC3(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9188 | cC3(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9189 | ||
9190 | cC3(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9191 | cC3(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9192 | cC3(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9193 | cC3(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9194 | cC3(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9195 | cC3(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9196 | cC3(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9197 | cC3(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9198 | cC3(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9199 | cC3(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9200 | cC3(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9201 | cC3(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9202 | ||
9203 | cC3(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9204 | cC3(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9205 | cC3(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9206 | cC3(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9207 | cC3(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9208 | cC3(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9209 | cC3(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9210 | cC3(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9211 | cC3(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9212 | cC3(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9213 | cC3(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9214 | cC3(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9215 | ||
9216 | cC3(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9217 | cC3(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9218 | cC3(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9219 | cC3(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9220 | cC3(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9221 | cC3(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9222 | cC3(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9223 | cC3(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9224 | cC3(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9225 | cC3(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9226 | cC3(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9227 | cC3(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9228 | ||
9229 | cC3(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9230 | cC3(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9231 | cC3(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9232 | cC3(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9233 | cC3(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9234 | cC3(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9235 | cC3(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9236 | cC3(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9237 | cC3(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9238 | cC3(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9239 | cC3(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9240 | cC3(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9241 | ||
9242 | cC3(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9243 | cC3(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9244 | cC3(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9245 | cC3(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9246 | cC3(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9247 | cC3(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9248 | cC3(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9249 | cC3(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9250 | cC3(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9251 | cC3(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9252 | cC3(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9253 | cC3(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9254 | ||
9255 | cC3(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9256 | cC3(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9257 | cC3(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9258 | cC3(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9259 | cC3(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9260 | cC3(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9261 | cC3(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9262 | cC3(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9263 | cC3(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9264 | cC3(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9265 | cC3(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9266 | cC3(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9267 | ||
9268 | cC3(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9269 | cC3(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9270 | cC3(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9271 | cC3(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9272 | cC3(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9273 | cC3(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9274 | cC3(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9275 | cC3(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9276 | cC3(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9277 | cC3(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9278 | cC3(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9279 | cC3(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9280 | ||
9281 | cC3(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9282 | cC3(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9283 | cC3(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9284 | cC3(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9285 | cC3(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9286 | cC3(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9287 | cC3(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9288 | cC3(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9289 | cC3(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9290 | cC3(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9291 | cC3(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9292 | cC3(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
9293 | ||
9294 | cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp), | |
c19d1205 | 9295 | C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp), |
8f06b2d8 | 9296 | cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp), |
c19d1205 ZW |
9297 | C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp), |
9298 | ||
8f06b2d8 PB |
9299 | cC3(flts, e000110, 2, (RF, RR), rn_rd), |
9300 | cC3(fltsp, e000130, 2, (RF, RR), rn_rd), | |
9301 | cC3(fltsm, e000150, 2, (RF, RR), rn_rd), | |
9302 | cC3(fltsz, e000170, 2, (RF, RR), rn_rd), | |
9303 | cC3(fltd, e000190, 2, (RF, RR), rn_rd), | |
9304 | cC3(fltdp, e0001b0, 2, (RF, RR), rn_rd), | |
9305 | cC3(fltdm, e0001d0, 2, (RF, RR), rn_rd), | |
9306 | cC3(fltdz, e0001f0, 2, (RF, RR), rn_rd), | |
9307 | cC3(flte, e080110, 2, (RF, RR), rn_rd), | |
9308 | cC3(fltep, e080130, 2, (RF, RR), rn_rd), | |
9309 | cC3(fltem, e080150, 2, (RF, RR), rn_rd), | |
9310 | cC3(fltez, e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 9311 | |
c19d1205 ZW |
9312 | /* The implementation of the FIX instruction is broken on some |
9313 | assemblers, in that it accepts a precision specifier as well as a | |
9314 | rounding specifier, despite the fact that this is meaningless. | |
9315 | To be more compatible, we accept it as well, though of course it | |
9316 | does not set any bits. */ | |
8f06b2d8 PB |
9317 | cCE(fix, e100110, 2, (RR, RF), rd_rm), |
9318 | cC3(fixp, e100130, 2, (RR, RF), rd_rm), | |
9319 | cC3(fixm, e100150, 2, (RR, RF), rd_rm), | |
9320 | cC3(fixz, e100170, 2, (RR, RF), rd_rm), | |
9321 | cC3(fixsp, e100130, 2, (RR, RF), rd_rm), | |
9322 | cC3(fixsm, e100150, 2, (RR, RF), rd_rm), | |
9323 | cC3(fixsz, e100170, 2, (RR, RF), rd_rm), | |
9324 | cC3(fixdp, e100130, 2, (RR, RF), rd_rm), | |
9325 | cC3(fixdm, e100150, 2, (RR, RF), rd_rm), | |
9326 | cC3(fixdz, e100170, 2, (RR, RF), rd_rm), | |
9327 | cC3(fixep, e100130, 2, (RR, RF), rd_rm), | |
9328 | cC3(fixem, e100150, 2, (RR, RF), rd_rm), | |
9329 | cC3(fixez, e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 9330 | |
c19d1205 ZW |
9331 | /* Instructions that were new with the real FPA, call them V2. */ |
9332 | #undef ARM_VARIANT | |
9333 | #define ARM_VARIANT FPU_FPA_EXT_V2 | |
8f06b2d8 PB |
9334 | cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
9335 | cC3(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
9336 | cC3(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
9337 | cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
9338 | cC3(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
9339 | cC3(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 ZW |
9340 | |
9341 | #undef ARM_VARIANT | |
9342 | #define ARM_VARIANT FPU_VFP_EXT_V1xD /* VFP V1xD (single precision). */ | |
9343 | /* Moves and type conversions. */ | |
8f06b2d8 PB |
9344 | cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
9345 | cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
9346 | cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
9347 | cCE(fmstat, ef1fa10, 0, (), noargs), | |
9348 | cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
9349 | cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
9350 | cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
9351 | cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
9352 | cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
9353 | cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
9354 | cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn), | |
9355 | cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
9356 | |
9357 | /* Memory operations. */ | |
8f06b2d8 PB |
9358 | cCE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst), |
9359 | cCE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst), | |
9360 | cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
9361 | cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
9362 | cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
9363 | cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
9364 | cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
9365 | cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
9366 | cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
9367 | cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
9368 | cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
9369 | cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), | |
9370 | cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
9371 | cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), | |
9372 | cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
9373 | cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), | |
9374 | cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
9375 | cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 9376 | |
c19d1205 | 9377 | /* Monadic operations. */ |
8f06b2d8 PB |
9378 | cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
9379 | cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
9380 | cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
9381 | |
9382 | /* Dyadic operations. */ | |
8f06b2d8 PB |
9383 | cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
9384 | cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9385 | cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9386 | cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9387 | cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9388 | cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9389 | cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9390 | cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
9391 | cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 9392 | |
c19d1205 | 9393 | /* Comparisons. */ |
8f06b2d8 PB |
9394 | cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
9395 | cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z), | |
9396 | cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
9397 | cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 9398 | |
c19d1205 ZW |
9399 | #undef ARM_VARIANT |
9400 | #define ARM_VARIANT FPU_VFP_EXT_V1 /* VFP V1 (Double precision). */ | |
9401 | /* Moves and type conversions. */ | |
8f06b2d8 PB |
9402 | cCE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm), |
9403 | cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
9404 | cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
9405 | cCE(fmdhr, e200b10, 2, (RVD, RR), rn_rd), | |
9406 | cCE(fmdlr, e000b10, 2, (RVD, RR), rn_rd), | |
9407 | cCE(fmrdh, e300b10, 2, (RR, RVD), rd_rn), | |
9408 | cCE(fmrdl, e100b10, 2, (RR, RVD), rd_rn), | |
9409 | cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
9410 | cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
9411 | cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
9412 | cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
9413 | cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
9414 | cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 ZW |
9415 | |
9416 | /* Memory operations. */ | |
8f06b2d8 PB |
9417 | cCE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst), |
9418 | cCE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst), | |
9419 | cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
9420 | cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
9421 | cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
9422 | cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
9423 | cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
9424 | cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), | |
9425 | cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
9426 | cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), | |
b99bd4ef | 9427 | |
c19d1205 | 9428 | /* Monadic operations. */ |
8f06b2d8 PB |
9429 | cCE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm), |
9430 | cCE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm), | |
9431 | cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm), | |
c19d1205 ZW |
9432 | |
9433 | /* Dyadic operations. */ | |
8f06b2d8 PB |
9434 | cCE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm), |
9435 | cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9436 | cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9437 | cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9438 | cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9439 | cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9440 | cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9441 | cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm), | |
9442 | cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm), | |
b99bd4ef | 9443 | |
c19d1205 | 9444 | /* Comparisons. */ |
8f06b2d8 PB |
9445 | cCE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm), |
9446 | cCE(fcmpzd, eb50b40, 1, (RVD), rd), | |
9447 | cCE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm), | |
9448 | cCE(fcmpezd, eb50bc0, 1, (RVD), rd), | |
c19d1205 ZW |
9449 | |
9450 | #undef ARM_VARIANT | |
9451 | #define ARM_VARIANT FPU_VFP_EXT_V2 | |
8f06b2d8 PB |
9452 | cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
9453 | cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
9454 | cCE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn), | |
9455 | cCE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm), | |
c19d1205 ZW |
9456 | |
9457 | #undef ARM_VARIANT | |
9458 | #define ARM_VARIANT ARM_CEXT_XSCALE /* Intel XScale extensions. */ | |
8f06b2d8 PB |
9459 | cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
9460 | cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9461 | cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9462 | cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9463 | cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9464 | cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
9465 | cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
9466 | cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 ZW |
9467 | |
9468 | #undef ARM_VARIANT | |
9469 | #define ARM_VARIANT ARM_CEXT_IWMMXT /* Intel Wireless MMX technology. */ | |
8f06b2d8 PB |
9470 | cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc), |
9471 | cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc), | |
9472 | cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc), | |
9473 | cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd), | |
9474 | cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd), | |
9475 | cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd), | |
9476 | cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc), | |
9477 | cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc), | |
9478 | cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc), | |
9479 | cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9480 | cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9481 | cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9482 | cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9483 | cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9484 | cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
9485 | cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
9486 | cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
9487 | cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
9488 | cCE(tmcr, e000110, 2, (RIWC, RR), rn_rd), | |
9489 | cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
9490 | cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9491 | cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9492 | cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9493 | cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9494 | cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9495 | cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
9496 | cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn), | |
9497 | cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn), | |
9498 | cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn), | |
9499 | cCE(tmrc, e100110, 2, (RR, RIWC), rd_rn), | |
9500 | cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
9501 | cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc), | |
9502 | cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc), | |
9503 | cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc), | |
9504 | cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn), | |
9505 | cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn), | |
9506 | cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn), | |
9507 | cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9508 | cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9509 | cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9510 | cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9511 | cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9512 | cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9513 | cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9514 | cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9515 | cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9516 | cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
9517 | cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9518 | cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9519 | cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9520 | cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9521 | cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9522 | cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9523 | cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9524 | cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9525 | cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9526 | cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9527 | cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9528 | cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9529 | cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9530 | cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9531 | cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9532 | cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9533 | cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9534 | cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9535 | cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9536 | cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
9537 | cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
9538 | cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
9539 | cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
9540 | cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9541 | cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9542 | cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9543 | cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9544 | cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9545 | cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9546 | cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9547 | cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9548 | cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9549 | cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9550 | cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9551 | cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9552 | cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9553 | cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9554 | cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9555 | cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9556 | cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9557 | cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9558 | cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
9559 | cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9560 | cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9561 | cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9562 | cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9563 | cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9564 | cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9565 | cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9566 | cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9567 | cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9568 | cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9569 | cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9570 | cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9571 | cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9572 | cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9573 | cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9574 | cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9575 | cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9576 | cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9577 | cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9578 | cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9579 | cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9580 | cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
9581 | cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9582 | cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9583 | cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9584 | cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9585 | cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9586 | cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9587 | cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9588 | cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9589 | cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9590 | cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9591 | cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9592 | cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9593 | cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9594 | cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9595 | cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9596 | cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9597 | cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9598 | cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
9599 | cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
9600 | cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
9601 | cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
9602 | cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
9603 | cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9604 | cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9605 | cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9606 | cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9607 | cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9608 | cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9609 | cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9610 | cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9611 | cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9612 | cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn), | |
9613 | cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn), | |
9614 | cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn), | |
9615 | cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn), | |
9616 | cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn), | |
9617 | cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn), | |
9618 | cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9619 | cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9620 | cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9621 | cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn), | |
9622 | cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn), | |
9623 | cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn), | |
9624 | cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn), | |
9625 | cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn), | |
9626 | cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn), | |
9627 | cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9628 | cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9629 | cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9630 | cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
9631 | cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 ZW |
9632 | |
9633 | #undef ARM_VARIANT | |
9634 | #define ARM_VARIANT ARM_CEXT_MAVERICK /* Cirrus Maverick instructions. */ | |
8f06b2d8 PB |
9635 | cCE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr), |
9636 | cCE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr), | |
9637 | cCE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr), | |
9638 | cCE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr), | |
9639 | cCE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr), | |
9640 | cCE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr), | |
9641 | cCE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr), | |
9642 | cCE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr), | |
9643 | cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd), | |
9644 | cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn), | |
9645 | cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd), | |
9646 | cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn), | |
9647 | cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd), | |
9648 | cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn), | |
9649 | cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd), | |
9650 | cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn), | |
9651 | cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd), | |
9652 | cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn), | |
9653 | cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn), | |
9654 | cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn), | |
9655 | cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn), | |
9656 | cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn), | |
9657 | cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn), | |
9658 | cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn), | |
9659 | cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn), | |
9660 | cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn), | |
9661 | cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn), | |
9662 | cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn), | |
9663 | cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc), | |
9664 | cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd), | |
9665 | cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn), | |
9666 | cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn), | |
9667 | cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn), | |
9668 | cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn), | |
9669 | cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn), | |
9670 | cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn), | |
9671 | cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn), | |
9672 | cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn), | |
9673 | cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn), | |
9674 | cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn), | |
9675 | cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn), | |
9676 | cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn), | |
9677 | cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple), | |
9678 | cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
9679 | cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift), | |
9680 | cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
9681 | cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
9682 | cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
9683 | cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
9684 | cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
9685 | cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn), | |
9686 | cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn), | |
9687 | cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn), | |
9688 | cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn), | |
9689 | cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
9690 | cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
9691 | cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
9692 | cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
9693 | cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
9694 | cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
9695 | cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn), | |
9696 | cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn), | |
9697 | cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn), | |
9698 | cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn), | |
9699 | cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
9700 | cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
9701 | cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
9702 | cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
9703 | cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
9704 | cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
9705 | cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
9706 | cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
9707 | cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
9708 | cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
9709 | cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
9710 | cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
c19d1205 ZW |
9711 | }; |
9712 | #undef ARM_VARIANT | |
9713 | #undef THUMB_VARIANT | |
9714 | #undef TCE | |
9715 | #undef TCM | |
9716 | #undef TUE | |
9717 | #undef TUF | |
9718 | #undef TCC | |
8f06b2d8 PB |
9719 | #undef cCE |
9720 | #undef cC3 | |
c19d1205 ZW |
9721 | #undef CE |
9722 | #undef CM | |
9723 | #undef UE | |
9724 | #undef UF | |
9725 | #undef UT | |
9726 | #undef OPS0 | |
9727 | #undef OPS1 | |
9728 | #undef OPS2 | |
9729 | #undef OPS3 | |
9730 | #undef OPS4 | |
9731 | #undef OPS5 | |
9732 | #undef OPS6 | |
9733 | #undef do_0 | |
9734 | \f | |
9735 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 9736 | |
c19d1205 ZW |
9737 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
9738 | for use in the a.out file, and stores them in the array pointed to by buf. | |
9739 | This knows about the endian-ness of the target machine and does | |
9740 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
9741 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
9742 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 9743 | |
c19d1205 ZW |
9744 | void |
9745 | md_number_to_chars (char * buf, valueT val, int n) | |
9746 | { | |
9747 | if (target_big_endian) | |
9748 | number_to_chars_bigendian (buf, val, n); | |
9749 | else | |
9750 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
9751 | } |
9752 | ||
c19d1205 ZW |
9753 | static valueT |
9754 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 9755 | { |
c19d1205 ZW |
9756 | valueT result = 0; |
9757 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 9758 | |
c19d1205 | 9759 | if (target_big_endian) |
b99bd4ef | 9760 | { |
c19d1205 ZW |
9761 | while (n--) |
9762 | { | |
9763 | result <<= 8; | |
9764 | result |= (*where++ & 255); | |
9765 | } | |
b99bd4ef | 9766 | } |
c19d1205 | 9767 | else |
b99bd4ef | 9768 | { |
c19d1205 ZW |
9769 | while (n--) |
9770 | { | |
9771 | result <<= 8; | |
9772 | result |= (where[n] & 255); | |
9773 | } | |
bfae80f2 | 9774 | } |
b99bd4ef | 9775 | |
c19d1205 | 9776 | return result; |
bfae80f2 | 9777 | } |
b99bd4ef | 9778 | |
c19d1205 | 9779 | /* MD interface: Sections. */ |
b99bd4ef | 9780 | |
0110f2b8 PB |
9781 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
9782 | 2 bytes. */ | |
9783 | ||
c19d1205 | 9784 | int |
0110f2b8 | 9785 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
9786 | segT segtype ATTRIBUTE_UNUSED) |
9787 | { | |
0110f2b8 PB |
9788 | fragp->fr_var = 2; |
9789 | return 2; | |
9790 | } | |
9791 | ||
9792 | /* Convert a machine dependent frag. */ | |
9793 | ||
9794 | void | |
9795 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
9796 | { | |
9797 | unsigned long insn; | |
9798 | unsigned long old_op; | |
9799 | char *buf; | |
9800 | expressionS exp; | |
9801 | fixS *fixp; | |
9802 | int reloc_type; | |
9803 | int pc_rel; | |
9804 | int opcode; | |
9805 | ||
9806 | buf = fragp->fr_literal + fragp->fr_fix; | |
9807 | ||
9808 | old_op = bfd_get_16(abfd, buf); | |
9809 | if (fragp->fr_symbol) { | |
9810 | exp.X_op = O_symbol; | |
9811 | exp.X_add_symbol = fragp->fr_symbol; | |
9812 | } else { | |
9813 | exp.X_op = O_constant; | |
9814 | } | |
9815 | exp.X_add_number = fragp->fr_offset; | |
9816 | opcode = fragp->fr_subtype; | |
9817 | switch (opcode) | |
9818 | { | |
9819 | case T_MNEM_ldr_pc: | |
9820 | case T_MNEM_ldr_pc2: | |
9821 | case T_MNEM_ldr_sp: | |
9822 | case T_MNEM_str_sp: | |
9823 | case T_MNEM_ldr: | |
9824 | case T_MNEM_ldrb: | |
9825 | case T_MNEM_ldrh: | |
9826 | case T_MNEM_str: | |
9827 | case T_MNEM_strb: | |
9828 | case T_MNEM_strh: | |
9829 | if (fragp->fr_var == 4) | |
9830 | { | |
9831 | insn = THUMB_OP32(opcode); | |
9832 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) | |
9833 | { | |
9834 | insn |= (old_op & 0x700) << 4; | |
9835 | } | |
9836 | else | |
9837 | { | |
9838 | insn |= (old_op & 7) << 12; | |
9839 | insn |= (old_op & 0x38) << 13; | |
9840 | } | |
9841 | insn |= 0x00000c00; | |
9842 | put_thumb32_insn (buf, insn); | |
9843 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
9844 | } | |
9845 | else | |
9846 | { | |
9847 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
9848 | } | |
9849 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
9850 | break; | |
9851 | case T_MNEM_adr: | |
9852 | if (fragp->fr_var == 4) | |
9853 | { | |
9854 | insn = THUMB_OP32 (opcode); | |
9855 | insn |= (old_op & 0xf0) << 4; | |
9856 | put_thumb32_insn (buf, insn); | |
9857 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
9858 | } | |
9859 | else | |
9860 | { | |
9861 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
9862 | exp.X_add_number -= 4; | |
9863 | } | |
9864 | pc_rel = 1; | |
9865 | break; | |
9866 | case T_MNEM_mov: | |
9867 | case T_MNEM_movs: | |
9868 | case T_MNEM_cmp: | |
9869 | case T_MNEM_cmn: | |
9870 | if (fragp->fr_var == 4) | |
9871 | { | |
9872 | int r0off = (opcode == T_MNEM_mov | |
9873 | || opcode == T_MNEM_movs) ? 0 : 8; | |
9874 | insn = THUMB_OP32 (opcode); | |
9875 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
9876 | insn |= (old_op & 0x700) << r0off; | |
9877 | put_thumb32_insn (buf, insn); | |
9878 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9879 | } | |
9880 | else | |
9881 | { | |
9882 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
9883 | } | |
9884 | pc_rel = 0; | |
9885 | break; | |
9886 | case T_MNEM_b: | |
9887 | if (fragp->fr_var == 4) | |
9888 | { | |
9889 | insn = THUMB_OP32(opcode); | |
9890 | put_thumb32_insn (buf, insn); | |
9891 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
9892 | } | |
9893 | else | |
9894 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
9895 | pc_rel = 1; | |
9896 | break; | |
9897 | case T_MNEM_bcond: | |
9898 | if (fragp->fr_var == 4) | |
9899 | { | |
9900 | insn = THUMB_OP32(opcode); | |
9901 | insn |= (old_op & 0xf00) << 14; | |
9902 | put_thumb32_insn (buf, insn); | |
9903 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
9904 | } | |
9905 | else | |
9906 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
9907 | pc_rel = 1; | |
9908 | break; | |
9909 | case T_MNEM_add_sp: | |
9910 | case T_MNEM_add_pc: | |
9911 | case T_MNEM_inc_sp: | |
9912 | case T_MNEM_dec_sp: | |
9913 | if (fragp->fr_var == 4) | |
9914 | { | |
9915 | /* ??? Choose between add and addw. */ | |
9916 | insn = THUMB_OP32 (opcode); | |
9917 | insn |= (old_op & 0xf0) << 4; | |
9918 | put_thumb32_insn (buf, insn); | |
9919 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9920 | } | |
9921 | else | |
9922 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
9923 | pc_rel = 0; | |
9924 | break; | |
9925 | ||
9926 | case T_MNEM_addi: | |
9927 | case T_MNEM_addis: | |
9928 | case T_MNEM_subi: | |
9929 | case T_MNEM_subis: | |
9930 | if (fragp->fr_var == 4) | |
9931 | { | |
9932 | insn = THUMB_OP32 (opcode); | |
9933 | insn |= (old_op & 0xf0) << 4; | |
9934 | insn |= (old_op & 0xf) << 16; | |
9935 | put_thumb32_insn (buf, insn); | |
9936 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9937 | } | |
9938 | else | |
9939 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
9940 | pc_rel = 0; | |
9941 | break; | |
9942 | default: | |
9943 | abort(); | |
9944 | } | |
9945 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
9946 | reloc_type); | |
9947 | fixp->fx_file = fragp->fr_file; | |
9948 | fixp->fx_line = fragp->fr_line; | |
9949 | fragp->fr_fix += fragp->fr_var; | |
9950 | } | |
9951 | ||
9952 | /* Return the size of a relaxable immediate operand instruction. | |
9953 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
9954 | static int | |
9955 | relax_immediate (fragS *fragp, int size, int shift) | |
9956 | { | |
9957 | offsetT offset; | |
9958 | offsetT mask; | |
9959 | offsetT low; | |
9960 | ||
9961 | /* ??? Should be able to do better than this. */ | |
9962 | if (fragp->fr_symbol) | |
9963 | return 4; | |
9964 | ||
9965 | low = (1 << shift) - 1; | |
9966 | mask = (1 << (shift + size)) - (1 << shift); | |
9967 | offset = fragp->fr_offset; | |
9968 | /* Force misaligned offsets to 32-bit variant. */ | |
9969 | if (offset & low) | |
9970 | return -4; | |
9971 | if (offset & ~mask) | |
9972 | return 4; | |
9973 | return 2; | |
9974 | } | |
9975 | ||
9976 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative | |
9977 | load. */ | |
9978 | static int | |
9979 | relax_adr (fragS *fragp, asection *sec) | |
9980 | { | |
9981 | addressT addr; | |
9982 | offsetT val; | |
9983 | ||
9984 | /* Assume worst case for symbols not known to be in the same section. */ | |
9985 | if (!S_IS_DEFINED(fragp->fr_symbol) | |
9986 | || sec != S_GET_SEGMENT (fragp->fr_symbol)) | |
9987 | return 4; | |
9988 | ||
9989 | val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset; | |
9990 | addr = fragp->fr_address + fragp->fr_fix; | |
9991 | addr = (addr + 4) & ~3; | |
9992 | /* Fix the insn as the 4-byte version if the target address is not | |
9993 | sufficiently aligned. This is prevents an infinite loop when two | |
9994 | instructions have contradictory range/alignment requirements. */ | |
9995 | if (val & 3) | |
9996 | return -4; | |
9997 | val -= addr; | |
9998 | if (val < 0 || val > 1020) | |
9999 | return 4; | |
10000 | return 2; | |
10001 | } | |
10002 | ||
10003 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
10004 | static int | |
10005 | relax_addsub (fragS *fragp, asection *sec) | |
10006 | { | |
10007 | char *buf; | |
10008 | int op; | |
10009 | ||
10010 | buf = fragp->fr_literal + fragp->fr_fix; | |
10011 | op = bfd_get_16(sec->owner, buf); | |
10012 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
10013 | return relax_immediate (fragp, 8, 0); | |
10014 | else | |
10015 | return relax_immediate (fragp, 3, 0); | |
10016 | } | |
10017 | ||
10018 | ||
10019 | /* Return the size of a relaxable branch instruction. BITS is the | |
10020 | size of the offset field in the narrow instruction. */ | |
10021 | ||
10022 | static int | |
10023 | relax_branch (fragS *fragp, asection *sec, int bits) | |
10024 | { | |
10025 | addressT addr; | |
10026 | offsetT val; | |
10027 | offsetT limit; | |
10028 | ||
10029 | /* Assume worst case for symbols not known to be in the same section. */ | |
10030 | if (!S_IS_DEFINED(fragp->fr_symbol) | |
10031 | || sec != S_GET_SEGMENT (fragp->fr_symbol)) | |
10032 | return 4; | |
10033 | ||
10034 | val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset; | |
10035 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
10036 | val -= addr; | |
10037 | ||
10038 | /* Offset is a signed value *2 */ | |
10039 | limit = 1 << bits; | |
10040 | if (val >= limit || val < -limit) | |
10041 | return 4; | |
10042 | return 2; | |
10043 | } | |
10044 | ||
10045 | ||
10046 | /* Relax a machine dependent frag. This returns the amount by which | |
10047 | the current size of the frag should change. */ | |
10048 | ||
10049 | int | |
10050 | arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED) | |
10051 | { | |
10052 | int oldsize; | |
10053 | int newsize; | |
10054 | ||
10055 | oldsize = fragp->fr_var; | |
10056 | switch (fragp->fr_subtype) | |
10057 | { | |
10058 | case T_MNEM_ldr_pc2: | |
10059 | newsize = relax_adr(fragp, sec); | |
10060 | break; | |
10061 | case T_MNEM_ldr_pc: | |
10062 | case T_MNEM_ldr_sp: | |
10063 | case T_MNEM_str_sp: | |
10064 | newsize = relax_immediate(fragp, 8, 2); | |
10065 | break; | |
10066 | case T_MNEM_ldr: | |
10067 | case T_MNEM_str: | |
10068 | newsize = relax_immediate(fragp, 5, 2); | |
10069 | break; | |
10070 | case T_MNEM_ldrh: | |
10071 | case T_MNEM_strh: | |
10072 | newsize = relax_immediate(fragp, 5, 1); | |
10073 | break; | |
10074 | case T_MNEM_ldrb: | |
10075 | case T_MNEM_strb: | |
10076 | newsize = relax_immediate(fragp, 5, 0); | |
10077 | break; | |
10078 | case T_MNEM_adr: | |
10079 | newsize = relax_adr(fragp, sec); | |
10080 | break; | |
10081 | case T_MNEM_mov: | |
10082 | case T_MNEM_movs: | |
10083 | case T_MNEM_cmp: | |
10084 | case T_MNEM_cmn: | |
10085 | newsize = relax_immediate(fragp, 8, 0); | |
10086 | break; | |
10087 | case T_MNEM_b: | |
10088 | newsize = relax_branch(fragp, sec, 11); | |
10089 | break; | |
10090 | case T_MNEM_bcond: | |
10091 | newsize = relax_branch(fragp, sec, 8); | |
10092 | break; | |
10093 | case T_MNEM_add_sp: | |
10094 | case T_MNEM_add_pc: | |
10095 | newsize = relax_immediate (fragp, 8, 2); | |
10096 | break; | |
10097 | case T_MNEM_inc_sp: | |
10098 | case T_MNEM_dec_sp: | |
10099 | newsize = relax_immediate (fragp, 7, 2); | |
10100 | break; | |
10101 | case T_MNEM_addi: | |
10102 | case T_MNEM_addis: | |
10103 | case T_MNEM_subi: | |
10104 | case T_MNEM_subis: | |
10105 | newsize = relax_addsub (fragp, sec); | |
10106 | break; | |
10107 | default: | |
10108 | abort(); | |
10109 | } | |
10110 | if (newsize < 0) | |
10111 | { | |
10112 | fragp->fr_var = -newsize; | |
10113 | md_convert_frag (sec->owner, sec, fragp); | |
10114 | frag_wane(fragp); | |
10115 | return -(newsize + oldsize); | |
10116 | } | |
10117 | fragp->fr_var = newsize; | |
10118 | return newsize - oldsize; | |
c19d1205 | 10119 | } |
b99bd4ef | 10120 | |
c19d1205 | 10121 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 10122 | |
c19d1205 ZW |
10123 | valueT |
10124 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
10125 | valueT size) | |
10126 | { | |
10127 | #ifdef OBJ_ELF | |
10128 | return size; | |
10129 | #else | |
10130 | /* Round all sects to multiple of 4. */ | |
10131 | return (size + 3) & ~3; | |
10132 | #endif | |
bfae80f2 | 10133 | } |
b99bd4ef | 10134 | |
c19d1205 ZW |
10135 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
10136 | of an rs_align_code fragment. */ | |
10137 | ||
10138 | void | |
10139 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 10140 | { |
c19d1205 ZW |
10141 | static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 }; |
10142 | static char const thumb_noop[2] = { 0xc0, 0x46 }; | |
10143 | static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 }; | |
10144 | static char const thumb_bigend_noop[2] = { 0x46, 0xc0 }; | |
10145 | ||
10146 | int bytes, fix, noop_size; | |
10147 | char * p; | |
10148 | const char * noop; | |
bfae80f2 | 10149 | |
c19d1205 | 10150 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
10151 | return; |
10152 | ||
c19d1205 ZW |
10153 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
10154 | p = fragP->fr_literal + fragP->fr_fix; | |
10155 | fix = 0; | |
bfae80f2 | 10156 | |
c19d1205 ZW |
10157 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
10158 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 10159 | |
c19d1205 | 10160 | if (fragP->tc_frag_data) |
a737bd4d | 10161 | { |
c19d1205 ZW |
10162 | if (target_big_endian) |
10163 | noop = thumb_bigend_noop; | |
10164 | else | |
10165 | noop = thumb_noop; | |
10166 | noop_size = sizeof (thumb_noop); | |
7ed4c4c5 NC |
10167 | } |
10168 | else | |
10169 | { | |
c19d1205 ZW |
10170 | if (target_big_endian) |
10171 | noop = arm_bigend_noop; | |
10172 | else | |
10173 | noop = arm_noop; | |
10174 | noop_size = sizeof (arm_noop); | |
7ed4c4c5 | 10175 | } |
a737bd4d | 10176 | |
c19d1205 | 10177 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 10178 | { |
c19d1205 ZW |
10179 | fix = bytes & (noop_size - 1); |
10180 | memset (p, 0, fix); | |
10181 | p += fix; | |
10182 | bytes -= fix; | |
a737bd4d | 10183 | } |
a737bd4d | 10184 | |
c19d1205 | 10185 | while (bytes >= noop_size) |
a737bd4d | 10186 | { |
c19d1205 ZW |
10187 | memcpy (p, noop, noop_size); |
10188 | p += noop_size; | |
10189 | bytes -= noop_size; | |
10190 | fix += noop_size; | |
a737bd4d NC |
10191 | } |
10192 | ||
c19d1205 ZW |
10193 | fragP->fr_fix += fix; |
10194 | fragP->fr_var = noop_size; | |
a737bd4d NC |
10195 | } |
10196 | ||
c19d1205 ZW |
10197 | /* Called from md_do_align. Used to create an alignment |
10198 | frag in a code section. */ | |
10199 | ||
10200 | void | |
10201 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 10202 | { |
c19d1205 | 10203 | char * p; |
7ed4c4c5 | 10204 | |
c19d1205 ZW |
10205 | /* We assume that there will never be a requirement |
10206 | to support alignments greater than 32 bytes. */ | |
10207 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) | |
10208 | as_fatal (_("alignments greater than 32 bytes not supported in .text sections.")); | |
bfae80f2 | 10209 | |
c19d1205 ZW |
10210 | p = frag_var (rs_align_code, |
10211 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
10212 | 1, | |
10213 | (relax_substateT) max, | |
10214 | (symbolS *) NULL, | |
10215 | (offsetT) n, | |
10216 | (char *) NULL); | |
10217 | *p = 0; | |
10218 | } | |
bfae80f2 | 10219 | |
c19d1205 | 10220 | /* Perform target specific initialisation of a frag. */ |
bfae80f2 | 10221 | |
c19d1205 ZW |
10222 | void |
10223 | arm_init_frag (fragS * fragP) | |
10224 | { | |
10225 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
10226 | fragP->tc_frag_data = thumb_mode; | |
bfae80f2 RE |
10227 | } |
10228 | ||
c19d1205 ZW |
10229 | #ifdef OBJ_ELF |
10230 | /* When we change sections we need to issue a new mapping symbol. */ | |
10231 | ||
10232 | void | |
10233 | arm_elf_change_section (void) | |
bfae80f2 | 10234 | { |
c19d1205 ZW |
10235 | flagword flags; |
10236 | segment_info_type *seginfo; | |
bfae80f2 | 10237 | |
c19d1205 ZW |
10238 | /* Link an unlinked unwind index table section to the .text section. */ |
10239 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
10240 | && elf_linked_to_section (now_seg) == NULL) | |
10241 | elf_linked_to_section (now_seg) = text_section; | |
10242 | ||
10243 | if (!SEG_NORMAL (now_seg)) | |
bfae80f2 RE |
10244 | return; |
10245 | ||
c19d1205 ZW |
10246 | flags = bfd_get_section_flags (stdoutput, now_seg); |
10247 | ||
10248 | /* We can ignore sections that only contain debug info. */ | |
10249 | if ((flags & SEC_ALLOC) == 0) | |
10250 | return; | |
bfae80f2 | 10251 | |
c19d1205 ZW |
10252 | seginfo = seg_info (now_seg); |
10253 | mapstate = seginfo->tc_segment_info_data.mapstate; | |
10254 | marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency; | |
bfae80f2 RE |
10255 | } |
10256 | ||
c19d1205 ZW |
10257 | int |
10258 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 10259 | { |
c19d1205 ZW |
10260 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
10261 | return SHT_ARM_EXIDX; | |
e45d0630 | 10262 | |
c19d1205 ZW |
10263 | return -1; |
10264 | } | |
10265 | \f | |
10266 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 10267 | |
c19d1205 | 10268 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 10269 | |
c19d1205 | 10270 | /* Cenerate and deferred unwind frame offset. */ |
e45d0630 | 10271 | |
bfae80f2 | 10272 | static void |
c19d1205 | 10273 | flush_pending_unwind (void) |
bfae80f2 | 10274 | { |
c19d1205 | 10275 | offsetT offset; |
bfae80f2 | 10276 | |
c19d1205 ZW |
10277 | offset = unwind.pending_offset; |
10278 | unwind.pending_offset = 0; | |
10279 | if (offset != 0) | |
10280 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
10281 | } |
10282 | ||
c19d1205 ZW |
10283 | /* Add an opcode to this list for this function. Two-byte opcodes should |
10284 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
10285 | order. */ | |
10286 | ||
bfae80f2 | 10287 | static void |
c19d1205 | 10288 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 10289 | { |
c19d1205 ZW |
10290 | /* Add any deferred stack adjustment. */ |
10291 | if (unwind.pending_offset) | |
10292 | flush_pending_unwind (); | |
bfae80f2 | 10293 | |
c19d1205 | 10294 | unwind.sp_restored = 0; |
bfae80f2 | 10295 | |
c19d1205 | 10296 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 10297 | { |
c19d1205 ZW |
10298 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
10299 | if (unwind.opcodes) | |
10300 | unwind.opcodes = xrealloc (unwind.opcodes, | |
10301 | unwind.opcode_alloc); | |
10302 | else | |
10303 | unwind.opcodes = xmalloc (unwind.opcode_alloc); | |
bfae80f2 | 10304 | } |
c19d1205 | 10305 | while (length > 0) |
bfae80f2 | 10306 | { |
c19d1205 ZW |
10307 | length--; |
10308 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
10309 | op >>= 8; | |
10310 | unwind.opcode_count++; | |
bfae80f2 | 10311 | } |
bfae80f2 RE |
10312 | } |
10313 | ||
c19d1205 ZW |
10314 | /* Add unwind opcodes to adjust the stack pointer. */ |
10315 | ||
bfae80f2 | 10316 | static void |
c19d1205 | 10317 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 10318 | { |
c19d1205 | 10319 | valueT op; |
bfae80f2 | 10320 | |
c19d1205 | 10321 | if (offset > 0x200) |
bfae80f2 | 10322 | { |
c19d1205 ZW |
10323 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
10324 | char bytes[5]; | |
10325 | int n; | |
10326 | valueT o; | |
bfae80f2 | 10327 | |
c19d1205 ZW |
10328 | /* Long form: 0xb2, uleb128. */ |
10329 | /* This might not fit in a word so add the individual bytes, | |
10330 | remembering the list is built in reverse order. */ | |
10331 | o = (valueT) ((offset - 0x204) >> 2); | |
10332 | if (o == 0) | |
10333 | add_unwind_opcode (0, 1); | |
bfae80f2 | 10334 | |
c19d1205 ZW |
10335 | /* Calculate the uleb128 encoding of the offset. */ |
10336 | n = 0; | |
10337 | while (o) | |
10338 | { | |
10339 | bytes[n] = o & 0x7f; | |
10340 | o >>= 7; | |
10341 | if (o) | |
10342 | bytes[n] |= 0x80; | |
10343 | n++; | |
10344 | } | |
10345 | /* Add the insn. */ | |
10346 | for (; n; n--) | |
10347 | add_unwind_opcode (bytes[n - 1], 1); | |
10348 | add_unwind_opcode (0xb2, 1); | |
10349 | } | |
10350 | else if (offset > 0x100) | |
bfae80f2 | 10351 | { |
c19d1205 ZW |
10352 | /* Two short opcodes. */ |
10353 | add_unwind_opcode (0x3f, 1); | |
10354 | op = (offset - 0x104) >> 2; | |
10355 | add_unwind_opcode (op, 1); | |
bfae80f2 | 10356 | } |
c19d1205 ZW |
10357 | else if (offset > 0) |
10358 | { | |
10359 | /* Short opcode. */ | |
10360 | op = (offset - 4) >> 2; | |
10361 | add_unwind_opcode (op, 1); | |
10362 | } | |
10363 | else if (offset < 0) | |
bfae80f2 | 10364 | { |
c19d1205 ZW |
10365 | offset = -offset; |
10366 | while (offset > 0x100) | |
bfae80f2 | 10367 | { |
c19d1205 ZW |
10368 | add_unwind_opcode (0x7f, 1); |
10369 | offset -= 0x100; | |
bfae80f2 | 10370 | } |
c19d1205 ZW |
10371 | op = ((offset - 4) >> 2) | 0x40; |
10372 | add_unwind_opcode (op, 1); | |
bfae80f2 | 10373 | } |
bfae80f2 RE |
10374 | } |
10375 | ||
c19d1205 ZW |
10376 | /* Finish the list of unwind opcodes for this function. */ |
10377 | static void | |
10378 | finish_unwind_opcodes (void) | |
bfae80f2 | 10379 | { |
c19d1205 | 10380 | valueT op; |
bfae80f2 | 10381 | |
c19d1205 | 10382 | if (unwind.fp_used) |
bfae80f2 | 10383 | { |
c19d1205 ZW |
10384 | /* Adjust sp as neccessary. */ |
10385 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; | |
10386 | flush_pending_unwind (); | |
bfae80f2 | 10387 | |
c19d1205 ZW |
10388 | /* After restoring sp from the frame pointer. */ |
10389 | op = 0x90 | unwind.fp_reg; | |
10390 | add_unwind_opcode (op, 1); | |
10391 | } | |
10392 | else | |
10393 | flush_pending_unwind (); | |
bfae80f2 RE |
10394 | } |
10395 | ||
bfae80f2 | 10396 | |
c19d1205 ZW |
10397 | /* Start an exception table entry. If idx is nonzero this is an index table |
10398 | entry. */ | |
bfae80f2 RE |
10399 | |
10400 | static void | |
c19d1205 | 10401 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 10402 | { |
c19d1205 ZW |
10403 | const char * text_name; |
10404 | const char * prefix; | |
10405 | const char * prefix_once; | |
10406 | const char * group_name; | |
10407 | size_t prefix_len; | |
10408 | size_t text_len; | |
10409 | char * sec_name; | |
10410 | size_t sec_name_len; | |
10411 | int type; | |
10412 | int flags; | |
10413 | int linkonce; | |
bfae80f2 | 10414 | |
c19d1205 | 10415 | if (idx) |
bfae80f2 | 10416 | { |
c19d1205 ZW |
10417 | prefix = ELF_STRING_ARM_unwind; |
10418 | prefix_once = ELF_STRING_ARM_unwind_once; | |
10419 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 10420 | } |
c19d1205 | 10421 | else |
bfae80f2 | 10422 | { |
c19d1205 ZW |
10423 | prefix = ELF_STRING_ARM_unwind_info; |
10424 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
10425 | type = SHT_PROGBITS; | |
bfae80f2 RE |
10426 | } |
10427 | ||
c19d1205 ZW |
10428 | text_name = segment_name (text_seg); |
10429 | if (streq (text_name, ".text")) | |
10430 | text_name = ""; | |
10431 | ||
10432 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
10433 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 10434 | { |
c19d1205 ZW |
10435 | prefix = prefix_once; |
10436 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
10437 | } |
10438 | ||
c19d1205 ZW |
10439 | prefix_len = strlen (prefix); |
10440 | text_len = strlen (text_name); | |
10441 | sec_name_len = prefix_len + text_len; | |
10442 | sec_name = xmalloc (sec_name_len + 1); | |
10443 | memcpy (sec_name, prefix, prefix_len); | |
10444 | memcpy (sec_name + prefix_len, text_name, text_len); | |
10445 | sec_name[prefix_len + text_len] = '\0'; | |
bfae80f2 | 10446 | |
c19d1205 ZW |
10447 | flags = SHF_ALLOC; |
10448 | linkonce = 0; | |
10449 | group_name = 0; | |
bfae80f2 | 10450 | |
c19d1205 ZW |
10451 | /* Handle COMDAT group. */ |
10452 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 10453 | { |
c19d1205 ZW |
10454 | group_name = elf_group_name (text_seg); |
10455 | if (group_name == NULL) | |
10456 | { | |
10457 | as_bad ("Group section `%s' has no group signature", | |
10458 | segment_name (text_seg)); | |
10459 | ignore_rest_of_line (); | |
10460 | return; | |
10461 | } | |
10462 | flags |= SHF_GROUP; | |
10463 | linkonce = 1; | |
bfae80f2 RE |
10464 | } |
10465 | ||
c19d1205 | 10466 | obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); |
bfae80f2 | 10467 | |
c19d1205 ZW |
10468 | /* Set the setion link for index tables. */ |
10469 | if (idx) | |
10470 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
10471 | } |
10472 | ||
bfae80f2 | 10473 | |
c19d1205 ZW |
10474 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
10475 | personality routine data. Returns zero, or the index table value for | |
10476 | and inline entry. */ | |
10477 | ||
10478 | static valueT | |
10479 | create_unwind_entry (int have_data) | |
bfae80f2 | 10480 | { |
c19d1205 ZW |
10481 | int size; |
10482 | addressT where; | |
10483 | char *ptr; | |
10484 | /* The current word of data. */ | |
10485 | valueT data; | |
10486 | /* The number of bytes left in this word. */ | |
10487 | int n; | |
bfae80f2 | 10488 | |
c19d1205 | 10489 | finish_unwind_opcodes (); |
bfae80f2 | 10490 | |
c19d1205 ZW |
10491 | /* Remember the current text section. */ |
10492 | unwind.saved_seg = now_seg; | |
10493 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 10494 | |
c19d1205 | 10495 | start_unwind_section (now_seg, 0); |
bfae80f2 | 10496 | |
c19d1205 | 10497 | if (unwind.personality_routine == NULL) |
bfae80f2 | 10498 | { |
c19d1205 ZW |
10499 | if (unwind.personality_index == -2) |
10500 | { | |
10501 | if (have_data) | |
10502 | as_bad (_("handerdata in cantunwind frame")); | |
10503 | return 1; /* EXIDX_CANTUNWIND. */ | |
10504 | } | |
bfae80f2 | 10505 | |
c19d1205 ZW |
10506 | /* Use a default personality routine if none is specified. */ |
10507 | if (unwind.personality_index == -1) | |
10508 | { | |
10509 | if (unwind.opcode_count > 3) | |
10510 | unwind.personality_index = 1; | |
10511 | else | |
10512 | unwind.personality_index = 0; | |
10513 | } | |
bfae80f2 | 10514 | |
c19d1205 ZW |
10515 | /* Space for the personality routine entry. */ |
10516 | if (unwind.personality_index == 0) | |
10517 | { | |
10518 | if (unwind.opcode_count > 3) | |
10519 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 10520 | |
c19d1205 ZW |
10521 | if (!have_data) |
10522 | { | |
10523 | /* All the data is inline in the index table. */ | |
10524 | data = 0x80; | |
10525 | n = 3; | |
10526 | while (unwind.opcode_count > 0) | |
10527 | { | |
10528 | unwind.opcode_count--; | |
10529 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
10530 | n--; | |
10531 | } | |
bfae80f2 | 10532 | |
c19d1205 ZW |
10533 | /* Pad with "finish" opcodes. */ |
10534 | while (n--) | |
10535 | data = (data << 8) | 0xb0; | |
bfae80f2 | 10536 | |
c19d1205 ZW |
10537 | return data; |
10538 | } | |
10539 | size = 0; | |
10540 | } | |
10541 | else | |
10542 | /* We get two opcodes "free" in the first word. */ | |
10543 | size = unwind.opcode_count - 2; | |
10544 | } | |
10545 | else | |
10546 | /* An extra byte is required for the opcode count. */ | |
10547 | size = unwind.opcode_count + 1; | |
bfae80f2 | 10548 | |
c19d1205 ZW |
10549 | size = (size + 3) >> 2; |
10550 | if (size > 0xff) | |
10551 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 10552 | |
c19d1205 ZW |
10553 | frag_align (2, 0, 0); |
10554 | record_alignment (now_seg, 2); | |
10555 | unwind.table_entry = expr_build_dot (); | |
10556 | ||
10557 | /* Allocate the table entry. */ | |
10558 | ptr = frag_more ((size << 2) + 4); | |
10559 | where = frag_now_fix () - ((size << 2) + 4); | |
bfae80f2 | 10560 | |
c19d1205 | 10561 | switch (unwind.personality_index) |
bfae80f2 | 10562 | { |
c19d1205 ZW |
10563 | case -1: |
10564 | /* ??? Should this be a PLT generating relocation? */ | |
10565 | /* Custom personality routine. */ | |
10566 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
10567 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 10568 | |
c19d1205 ZW |
10569 | where += 4; |
10570 | ptr += 4; | |
bfae80f2 | 10571 | |
c19d1205 ZW |
10572 | /* Set the first byte to the number of additional words. */ |
10573 | data = size - 1; | |
10574 | n = 3; | |
10575 | break; | |
bfae80f2 | 10576 | |
c19d1205 ZW |
10577 | /* ABI defined personality routines. */ |
10578 | case 0: | |
10579 | /* Three opcodes bytes are packed into the first word. */ | |
10580 | data = 0x80; | |
10581 | n = 3; | |
10582 | break; | |
bfae80f2 | 10583 | |
c19d1205 ZW |
10584 | case 1: |
10585 | case 2: | |
10586 | /* The size and first two opcode bytes go in the first word. */ | |
10587 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
10588 | n = 2; | |
10589 | break; | |
bfae80f2 | 10590 | |
c19d1205 ZW |
10591 | default: |
10592 | /* Should never happen. */ | |
10593 | abort (); | |
10594 | } | |
bfae80f2 | 10595 | |
c19d1205 ZW |
10596 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
10597 | time. */ | |
10598 | while (unwind.opcode_count > 0) | |
10599 | { | |
10600 | if (n == 0) | |
10601 | { | |
10602 | md_number_to_chars (ptr, data, 4); | |
10603 | ptr += 4; | |
10604 | n = 4; | |
10605 | data = 0; | |
10606 | } | |
10607 | unwind.opcode_count--; | |
10608 | n--; | |
10609 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
10610 | } | |
10611 | ||
10612 | /* Finish off the last word. */ | |
10613 | if (n < 4) | |
10614 | { | |
10615 | /* Pad with "finish" opcodes. */ | |
10616 | while (n--) | |
10617 | data = (data << 8) | 0xb0; | |
10618 | ||
10619 | md_number_to_chars (ptr, data, 4); | |
10620 | } | |
10621 | ||
10622 | if (!have_data) | |
10623 | { | |
10624 | /* Add an empty descriptor if there is no user-specified data. */ | |
10625 | ptr = frag_more (4); | |
10626 | md_number_to_chars (ptr, 0, 4); | |
10627 | } | |
10628 | ||
10629 | return 0; | |
bfae80f2 RE |
10630 | } |
10631 | ||
c19d1205 ZW |
10632 | /* Convert REGNAME to a DWARF-2 register number. */ |
10633 | ||
10634 | int | |
10635 | tc_arm_regname_to_dw2regnum (const char *regname) | |
bfae80f2 | 10636 | { |
c19d1205 ZW |
10637 | int reg = arm_reg_parse ((char **) ®name, REG_TYPE_RN); |
10638 | ||
10639 | if (reg == FAIL) | |
10640 | return -1; | |
10641 | ||
10642 | return reg; | |
bfae80f2 RE |
10643 | } |
10644 | ||
c19d1205 ZW |
10645 | /* Initialize the DWARF-2 unwind information for this procedure. */ |
10646 | ||
10647 | void | |
10648 | tc_arm_frame_initial_instructions (void) | |
bfae80f2 | 10649 | { |
c19d1205 | 10650 | cfi_add_CFA_def_cfa (REG_SP, 0); |
bfae80f2 | 10651 | } |
c19d1205 | 10652 | #endif /* OBJ_ELF */ |
bfae80f2 | 10653 | |
bfae80f2 | 10654 | |
c19d1205 | 10655 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 10656 | |
2fc8bdac ZW |
10657 | /* Return the address within the segment that a PC-relative fixup is |
10658 | relative to. For ARM, PC-relative fixups applied to instructions | |
10659 | are generally relative to the location of the fixup plus 8 bytes. | |
10660 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
10661 | require special handling. */ | |
bfae80f2 | 10662 | |
c19d1205 | 10663 | long |
2fc8bdac | 10664 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 10665 | { |
2fc8bdac ZW |
10666 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
10667 | ||
10668 | /* If this is pc-relative and we are going to emit a relocation | |
10669 | then we just want to put out any pipeline compensation that the linker | |
10670 | will need. Otherwise we want to use the calculated base. */ | |
10671 | if (fixP->fx_pcrel | |
10672 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
10673 | || arm_force_relocation (fixP))) | |
10674 | base = 0; | |
bfae80f2 | 10675 | |
c19d1205 | 10676 | switch (fixP->fx_r_type) |
bfae80f2 | 10677 | { |
2fc8bdac ZW |
10678 | /* PC relative addressing on the Thumb is slightly odd as the |
10679 | bottom two bits of the PC are forced to zero for the | |
10680 | calculation. This happens *after* application of the | |
10681 | pipeline offset. However, Thumb adrl already adjusts for | |
10682 | this, so we need not do it again. */ | |
c19d1205 | 10683 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 10684 | return base & ~3; |
c19d1205 ZW |
10685 | |
10686 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
10687 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 10688 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 10689 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 10690 | return (base + 4) & ~3; |
c19d1205 | 10691 | |
2fc8bdac ZW |
10692 | /* Thumb branches are simply offset by +4. */ |
10693 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
10694 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
10695 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
10696 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
10697 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
10698 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
10699 | case BFD_RELOC_THUMB_PCREL_BLX: | |
10700 | return base + 4; | |
bfae80f2 | 10701 | |
2fc8bdac ZW |
10702 | /* ARM mode branches are offset by +8. However, the Windows CE |
10703 | loader expects the relocation not to take this into account. */ | |
10704 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
10705 | case BFD_RELOC_ARM_PCREL_BLX: | |
10706 | case BFD_RELOC_ARM_PLT32: | |
c19d1205 | 10707 | #ifdef TE_WINCE |
2fc8bdac | 10708 | return base; |
c19d1205 | 10709 | #else |
2fc8bdac | 10710 | return base + 8; |
c19d1205 | 10711 | #endif |
2fc8bdac ZW |
10712 | |
10713 | /* ARM mode loads relative to PC are also offset by +8. Unlike | |
10714 | branches, the Windows CE loader *does* expect the relocation | |
10715 | to take this into account. */ | |
10716 | case BFD_RELOC_ARM_OFFSET_IMM: | |
10717 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
10718 | case BFD_RELOC_ARM_HWLITERAL: | |
10719 | case BFD_RELOC_ARM_LITERAL: | |
10720 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
10721 | return base + 8; | |
10722 | ||
10723 | ||
10724 | /* Other PC-relative relocations are un-offset. */ | |
10725 | default: | |
10726 | return base; | |
10727 | } | |
bfae80f2 RE |
10728 | } |
10729 | ||
c19d1205 ZW |
10730 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. |
10731 | Otherwise we have no need to default values of symbols. */ | |
10732 | ||
10733 | symbolS * | |
10734 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
bfae80f2 | 10735 | { |
c19d1205 ZW |
10736 | #ifdef OBJ_ELF |
10737 | if (name[0] == '_' && name[1] == 'G' | |
10738 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
10739 | { | |
10740 | if (!GOT_symbol) | |
10741 | { | |
10742 | if (symbol_find (name)) | |
10743 | as_bad ("GOT already in the symbol table"); | |
bfae80f2 | 10744 | |
c19d1205 ZW |
10745 | GOT_symbol = symbol_new (name, undefined_section, |
10746 | (valueT) 0, & zero_address_frag); | |
10747 | } | |
bfae80f2 | 10748 | |
c19d1205 | 10749 | return GOT_symbol; |
bfae80f2 | 10750 | } |
c19d1205 | 10751 | #endif |
bfae80f2 | 10752 | |
c19d1205 | 10753 | return 0; |
bfae80f2 RE |
10754 | } |
10755 | ||
55cf6793 | 10756 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
10757 | computed as two separate immediate values, added together. We |
10758 | already know that this value cannot be computed by just one ARM | |
10759 | instruction. */ | |
10760 | ||
10761 | static unsigned int | |
10762 | validate_immediate_twopart (unsigned int val, | |
10763 | unsigned int * highpart) | |
bfae80f2 | 10764 | { |
c19d1205 ZW |
10765 | unsigned int a; |
10766 | unsigned int i; | |
bfae80f2 | 10767 | |
c19d1205 ZW |
10768 | for (i = 0; i < 32; i += 2) |
10769 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
10770 | { | |
10771 | if (a & 0xff00) | |
10772 | { | |
10773 | if (a & ~ 0xffff) | |
10774 | continue; | |
10775 | * highpart = (a >> 8) | ((i + 24) << 7); | |
10776 | } | |
10777 | else if (a & 0xff0000) | |
10778 | { | |
10779 | if (a & 0xff000000) | |
10780 | continue; | |
10781 | * highpart = (a >> 16) | ((i + 16) << 7); | |
10782 | } | |
10783 | else | |
10784 | { | |
10785 | assert (a & 0xff000000); | |
10786 | * highpart = (a >> 24) | ((i + 8) << 7); | |
10787 | } | |
bfae80f2 | 10788 | |
c19d1205 ZW |
10789 | return (a & 0xff) | (i << 7); |
10790 | } | |
bfae80f2 | 10791 | |
c19d1205 | 10792 | return FAIL; |
bfae80f2 RE |
10793 | } |
10794 | ||
c19d1205 ZW |
10795 | static int |
10796 | validate_offset_imm (unsigned int val, int hwse) | |
10797 | { | |
10798 | if ((hwse && val > 255) || val > 4095) | |
10799 | return FAIL; | |
10800 | return val; | |
10801 | } | |
bfae80f2 | 10802 | |
55cf6793 | 10803 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
10804 | negative immediate constant by altering the instruction. A bit of |
10805 | a hack really. | |
10806 | MOV <-> MVN | |
10807 | AND <-> BIC | |
10808 | ADC <-> SBC | |
10809 | by inverting the second operand, and | |
10810 | ADD <-> SUB | |
10811 | CMP <-> CMN | |
10812 | by negating the second operand. */ | |
bfae80f2 | 10813 | |
c19d1205 ZW |
10814 | static int |
10815 | negate_data_op (unsigned long * instruction, | |
10816 | unsigned long value) | |
bfae80f2 | 10817 | { |
c19d1205 ZW |
10818 | int op, new_inst; |
10819 | unsigned long negated, inverted; | |
bfae80f2 | 10820 | |
c19d1205 ZW |
10821 | negated = encode_arm_immediate (-value); |
10822 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 10823 | |
c19d1205 ZW |
10824 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
10825 | switch (op) | |
bfae80f2 | 10826 | { |
c19d1205 ZW |
10827 | /* First negates. */ |
10828 | case OPCODE_SUB: /* ADD <-> SUB */ | |
10829 | new_inst = OPCODE_ADD; | |
10830 | value = negated; | |
10831 | break; | |
bfae80f2 | 10832 | |
c19d1205 ZW |
10833 | case OPCODE_ADD: |
10834 | new_inst = OPCODE_SUB; | |
10835 | value = negated; | |
10836 | break; | |
bfae80f2 | 10837 | |
c19d1205 ZW |
10838 | case OPCODE_CMP: /* CMP <-> CMN */ |
10839 | new_inst = OPCODE_CMN; | |
10840 | value = negated; | |
10841 | break; | |
bfae80f2 | 10842 | |
c19d1205 ZW |
10843 | case OPCODE_CMN: |
10844 | new_inst = OPCODE_CMP; | |
10845 | value = negated; | |
10846 | break; | |
bfae80f2 | 10847 | |
c19d1205 ZW |
10848 | /* Now Inverted ops. */ |
10849 | case OPCODE_MOV: /* MOV <-> MVN */ | |
10850 | new_inst = OPCODE_MVN; | |
10851 | value = inverted; | |
10852 | break; | |
bfae80f2 | 10853 | |
c19d1205 ZW |
10854 | case OPCODE_MVN: |
10855 | new_inst = OPCODE_MOV; | |
10856 | value = inverted; | |
10857 | break; | |
bfae80f2 | 10858 | |
c19d1205 ZW |
10859 | case OPCODE_AND: /* AND <-> BIC */ |
10860 | new_inst = OPCODE_BIC; | |
10861 | value = inverted; | |
10862 | break; | |
bfae80f2 | 10863 | |
c19d1205 ZW |
10864 | case OPCODE_BIC: |
10865 | new_inst = OPCODE_AND; | |
10866 | value = inverted; | |
10867 | break; | |
bfae80f2 | 10868 | |
c19d1205 ZW |
10869 | case OPCODE_ADC: /* ADC <-> SBC */ |
10870 | new_inst = OPCODE_SBC; | |
10871 | value = inverted; | |
10872 | break; | |
bfae80f2 | 10873 | |
c19d1205 ZW |
10874 | case OPCODE_SBC: |
10875 | new_inst = OPCODE_ADC; | |
10876 | value = inverted; | |
10877 | break; | |
bfae80f2 | 10878 | |
c19d1205 ZW |
10879 | /* We cannot do anything. */ |
10880 | default: | |
10881 | return FAIL; | |
b99bd4ef NC |
10882 | } |
10883 | ||
c19d1205 ZW |
10884 | if (value == (unsigned) FAIL) |
10885 | return FAIL; | |
10886 | ||
10887 | *instruction &= OPCODE_MASK; | |
10888 | *instruction |= new_inst << DATA_OP_SHIFT; | |
10889 | return value; | |
b99bd4ef NC |
10890 | } |
10891 | ||
8f06b2d8 PB |
10892 | /* Read a 32-bit thumb instruction from buf. */ |
10893 | static unsigned long | |
10894 | get_thumb32_insn (char * buf) | |
10895 | { | |
10896 | unsigned long insn; | |
10897 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
10898 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
10899 | ||
10900 | return insn; | |
10901 | } | |
10902 | ||
c19d1205 | 10903 | void |
55cf6793 | 10904 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
10905 | valueT * valP, |
10906 | segT seg) | |
10907 | { | |
10908 | offsetT value = * valP; | |
10909 | offsetT newval; | |
10910 | unsigned int newimm; | |
10911 | unsigned long temp; | |
10912 | int sign; | |
10913 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 10914 | |
c19d1205 | 10915 | assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 10916 | |
c19d1205 ZW |
10917 | /* Note whether this will delete the relocation. */ |
10918 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
10919 | fixP->fx_done = 1; | |
b99bd4ef | 10920 | |
adbaf948 ZW |
10921 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
10922 | consistency with the behavior on 32-bit hosts. Remember value | |
10923 | for emit_reloc. */ | |
10924 | value &= 0xffffffff; | |
10925 | value ^= 0x80000000; | |
10926 | value -= 0x80000000; | |
10927 | ||
10928 | *valP = value; | |
c19d1205 | 10929 | fixP->fx_addnumber = value; |
b99bd4ef | 10930 | |
adbaf948 ZW |
10931 | /* Same treatment for fixP->fx_offset. */ |
10932 | fixP->fx_offset &= 0xffffffff; | |
10933 | fixP->fx_offset ^= 0x80000000; | |
10934 | fixP->fx_offset -= 0x80000000; | |
10935 | ||
c19d1205 | 10936 | switch (fixP->fx_r_type) |
b99bd4ef | 10937 | { |
c19d1205 ZW |
10938 | case BFD_RELOC_NONE: |
10939 | /* This will need to go in the object file. */ | |
10940 | fixP->fx_done = 0; | |
10941 | break; | |
b99bd4ef | 10942 | |
c19d1205 ZW |
10943 | case BFD_RELOC_ARM_IMMEDIATE: |
10944 | /* We claim that this fixup has been processed here, | |
10945 | even if in fact we generate an error because we do | |
10946 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
10947 | fixP->fx_done = 1; | |
b99bd4ef | 10948 | |
c19d1205 ZW |
10949 | if (fixP->fx_addsy |
10950 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
b99bd4ef | 10951 | { |
c19d1205 ZW |
10952 | as_bad_where (fixP->fx_file, fixP->fx_line, |
10953 | _("undefined symbol %s used as an immediate value"), | |
10954 | S_GET_NAME (fixP->fx_addsy)); | |
10955 | break; | |
b99bd4ef NC |
10956 | } |
10957 | ||
c19d1205 ZW |
10958 | newimm = encode_arm_immediate (value); |
10959 | temp = md_chars_to_number (buf, INSN_SIZE); | |
10960 | ||
10961 | /* If the instruction will fail, see if we can fix things up by | |
10962 | changing the opcode. */ | |
10963 | if (newimm == (unsigned int) FAIL | |
10964 | && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) | |
b99bd4ef | 10965 | { |
c19d1205 ZW |
10966 | as_bad_where (fixP->fx_file, fixP->fx_line, |
10967 | _("invalid constant (%lx) after fixup"), | |
10968 | (unsigned long) value); | |
10969 | break; | |
b99bd4ef | 10970 | } |
b99bd4ef | 10971 | |
c19d1205 ZW |
10972 | newimm |= (temp & 0xfffff000); |
10973 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
10974 | break; | |
b99bd4ef | 10975 | |
c19d1205 ZW |
10976 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
10977 | { | |
10978 | unsigned int highpart = 0; | |
10979 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 10980 | |
c19d1205 ZW |
10981 | newimm = encode_arm_immediate (value); |
10982 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 10983 | |
c19d1205 ZW |
10984 | /* If the instruction will fail, see if we can fix things up by |
10985 | changing the opcode. */ | |
10986 | if (newimm == (unsigned int) FAIL | |
10987 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
10988 | { | |
10989 | /* No ? OK - try using two ADD instructions to generate | |
10990 | the value. */ | |
10991 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 10992 | |
c19d1205 ZW |
10993 | /* Yes - then make sure that the second instruction is |
10994 | also an add. */ | |
10995 | if (newimm != (unsigned int) FAIL) | |
10996 | newinsn = temp; | |
10997 | /* Still No ? Try using a negated value. */ | |
10998 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
10999 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
11000 | /* Otherwise - give up. */ | |
11001 | else | |
11002 | { | |
11003 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11004 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
11005 | (long) value); | |
11006 | break; | |
11007 | } | |
b99bd4ef | 11008 | |
c19d1205 ZW |
11009 | /* Replace the first operand in the 2nd instruction (which |
11010 | is the PC) with the destination register. We have | |
11011 | already added in the PC in the first instruction and we | |
11012 | do not want to do it again. */ | |
11013 | newinsn &= ~ 0xf0000; | |
11014 | newinsn |= ((newinsn & 0x0f000) << 4); | |
11015 | } | |
b99bd4ef | 11016 | |
c19d1205 ZW |
11017 | newimm |= (temp & 0xfffff000); |
11018 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 11019 | |
c19d1205 ZW |
11020 | highpart |= (newinsn & 0xfffff000); |
11021 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
11022 | } | |
11023 | break; | |
b99bd4ef | 11024 | |
c19d1205 ZW |
11025 | case BFD_RELOC_ARM_OFFSET_IMM: |
11026 | case BFD_RELOC_ARM_LITERAL: | |
11027 | sign = value >= 0; | |
b99bd4ef | 11028 | |
c19d1205 ZW |
11029 | if (value < 0) |
11030 | value = - value; | |
b99bd4ef | 11031 | |
c19d1205 | 11032 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 11033 | { |
c19d1205 ZW |
11034 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
11035 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11036 | _("invalid literal constant: pool needs to be closer")); | |
11037 | else | |
11038 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11039 | _("bad immediate value for offset (%ld)"), | |
11040 | (long) value); | |
11041 | break; | |
f03698e6 RE |
11042 | } |
11043 | ||
c19d1205 ZW |
11044 | newval = md_chars_to_number (buf, INSN_SIZE); |
11045 | newval &= 0xff7ff000; | |
11046 | newval |= value | (sign ? INDEX_UP : 0); | |
11047 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11048 | break; | |
b99bd4ef | 11049 | |
c19d1205 ZW |
11050 | case BFD_RELOC_ARM_OFFSET_IMM8: |
11051 | case BFD_RELOC_ARM_HWLITERAL: | |
11052 | sign = value >= 0; | |
b99bd4ef | 11053 | |
c19d1205 ZW |
11054 | if (value < 0) |
11055 | value = - value; | |
b99bd4ef | 11056 | |
c19d1205 | 11057 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 11058 | { |
c19d1205 ZW |
11059 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
11060 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11061 | _("invalid literal constant: pool needs to be closer")); | |
11062 | else | |
11063 | as_bad (_("bad immediate value for half-word offset (%ld)"), | |
11064 | (long) value); | |
11065 | break; | |
b99bd4ef NC |
11066 | } |
11067 | ||
c19d1205 ZW |
11068 | newval = md_chars_to_number (buf, INSN_SIZE); |
11069 | newval &= 0xff7ff0f0; | |
11070 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
11071 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11072 | break; | |
b99bd4ef | 11073 | |
c19d1205 ZW |
11074 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
11075 | if (value < 0 || value > 1020 || value % 4 != 0) | |
11076 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11077 | _("bad immediate value for offset (%ld)"), (long) value); | |
11078 | value /= 4; | |
b99bd4ef | 11079 | |
c19d1205 | 11080 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
11081 | newval |= value; |
11082 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
11083 | break; | |
b99bd4ef | 11084 | |
c19d1205 ZW |
11085 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
11086 | /* This is a complicated relocation used for all varieties of Thumb32 | |
11087 | load/store instruction with immediate offset: | |
11088 | ||
11089 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
11090 | *4, optional writeback(W) | |
11091 | (doubleword load/store) | |
11092 | ||
11093 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
11094 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
11095 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
11096 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
11097 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
11098 | ||
11099 | Uppercase letters indicate bits that are already encoded at | |
11100 | this point. Lowercase letters are our problem. For the | |
11101 | second block of instructions, the secondary opcode nybble | |
11102 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
11103 | a PC-relative operation. */ | |
11104 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11105 | newval <<= 16; | |
11106 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 11107 | |
c19d1205 | 11108 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 11109 | { |
c19d1205 ZW |
11110 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
11111 | if (value >= 0) | |
11112 | newval |= (1 << 23); | |
11113 | else | |
11114 | value = -value; | |
11115 | if (value % 4 != 0) | |
11116 | { | |
11117 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11118 | _("offset not a multiple of 4")); | |
11119 | break; | |
11120 | } | |
11121 | value /= 4; | |
11122 | if (value >= 0xff) | |
11123 | { | |
11124 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11125 | _("offset out of range")); | |
11126 | break; | |
11127 | } | |
11128 | newval &= ~0xff; | |
b99bd4ef | 11129 | } |
c19d1205 | 11130 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 11131 | { |
c19d1205 ZW |
11132 | /* PC-relative, 12-bit offset. */ |
11133 | if (value >= 0) | |
11134 | newval |= (1 << 23); | |
11135 | else | |
11136 | value = -value; | |
11137 | if (value >= 0xfff) | |
11138 | { | |
11139 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11140 | _("offset out of range")); | |
11141 | break; | |
11142 | } | |
11143 | newval &= ~0xfff; | |
b99bd4ef | 11144 | } |
c19d1205 | 11145 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 11146 | { |
c19d1205 ZW |
11147 | /* Writeback: 8-bit, +/- offset. */ |
11148 | if (value >= 0) | |
11149 | newval |= (1 << 9); | |
11150 | else | |
11151 | value = -value; | |
11152 | if (value >= 0xff) | |
11153 | { | |
11154 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11155 | _("offset out of range")); | |
11156 | break; | |
11157 | } | |
11158 | newval &= ~0xff; | |
b99bd4ef | 11159 | } |
c19d1205 | 11160 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 11161 | { |
c19d1205 ZW |
11162 | /* T-instruction: positive 8-bit offset. */ |
11163 | if (value < 0 || value >= 0xff) | |
b99bd4ef | 11164 | { |
c19d1205 ZW |
11165 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11166 | _("offset out of range")); | |
11167 | break; | |
b99bd4ef | 11168 | } |
c19d1205 ZW |
11169 | newval &= ~0xff; |
11170 | newval |= value; | |
b99bd4ef NC |
11171 | } |
11172 | else | |
b99bd4ef | 11173 | { |
c19d1205 ZW |
11174 | /* Positive 12-bit or negative 8-bit offset. */ |
11175 | int limit; | |
11176 | if (value >= 0) | |
b99bd4ef | 11177 | { |
c19d1205 ZW |
11178 | newval |= (1 << 23); |
11179 | limit = 0xfff; | |
11180 | } | |
11181 | else | |
11182 | { | |
11183 | value = -value; | |
11184 | limit = 0xff; | |
11185 | } | |
11186 | if (value > limit) | |
11187 | { | |
11188 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11189 | _("offset out of range")); | |
11190 | break; | |
b99bd4ef | 11191 | } |
c19d1205 | 11192 | newval &= ~limit; |
b99bd4ef | 11193 | } |
b99bd4ef | 11194 | |
c19d1205 ZW |
11195 | newval |= value; |
11196 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
11197 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
11198 | break; | |
404ff6b5 | 11199 | |
c19d1205 ZW |
11200 | case BFD_RELOC_ARM_SHIFT_IMM: |
11201 | newval = md_chars_to_number (buf, INSN_SIZE); | |
11202 | if (((unsigned long) value) > 32 | |
11203 | || (value == 32 | |
11204 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
11205 | { | |
11206 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11207 | _("shift expression is too large")); | |
11208 | break; | |
11209 | } | |
404ff6b5 | 11210 | |
c19d1205 ZW |
11211 | if (value == 0) |
11212 | /* Shifts of zero must be done as lsl. */ | |
11213 | newval &= ~0x60; | |
11214 | else if (value == 32) | |
11215 | value = 0; | |
11216 | newval &= 0xfffff07f; | |
11217 | newval |= (value & 0x1f) << 7; | |
11218 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11219 | break; | |
404ff6b5 | 11220 | |
c19d1205 | 11221 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
92e90b6e | 11222 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 11223 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
11224 | /* We claim that this fixup has been processed here, |
11225 | even if in fact we generate an error because we do | |
11226 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
11227 | fixP->fx_done = 1; | |
404ff6b5 | 11228 | |
c19d1205 ZW |
11229 | if (fixP->fx_addsy |
11230 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
11231 | { | |
11232 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11233 | _("undefined symbol %s used as an immediate value"), | |
11234 | S_GET_NAME (fixP->fx_addsy)); | |
11235 | break; | |
11236 | } | |
404ff6b5 | 11237 | |
c19d1205 ZW |
11238 | newval = md_chars_to_number (buf, THUMB_SIZE); |
11239 | newval <<= 16; | |
11240 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 11241 | |
e9f89963 PB |
11242 | /* FUTURE: Implement analogue of negate_data_op for T32. */ |
11243 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE) | |
11244 | newimm = encode_thumb32_immediate (value); | |
11245 | else | |
92e90b6e | 11246 | { |
e9f89963 PB |
11247 | /* 12 bit immediate for addw/subw. */ |
11248 | if (value < 0) | |
11249 | { | |
11250 | value = -value; | |
11251 | newval ^= 0x00a00000; | |
11252 | } | |
92e90b6e PB |
11253 | if (value > 0xfff) |
11254 | newimm = (unsigned int) FAIL; | |
11255 | else | |
11256 | newimm = value; | |
11257 | } | |
cc8a6dd0 | 11258 | |
c19d1205 | 11259 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 11260 | { |
c19d1205 ZW |
11261 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11262 | _("invalid constant (%lx) after fixup"), | |
11263 | (unsigned long) value); | |
11264 | break; | |
3631a3c8 NC |
11265 | } |
11266 | ||
c19d1205 ZW |
11267 | newval |= (newimm & 0x800) << 15; |
11268 | newval |= (newimm & 0x700) << 4; | |
11269 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 11270 | |
c19d1205 ZW |
11271 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
11272 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
11273 | break; | |
a737bd4d | 11274 | |
3eb17e6b | 11275 | case BFD_RELOC_ARM_SMC: |
c19d1205 ZW |
11276 | if (((unsigned long) value) > 0xffff) |
11277 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3eb17e6b | 11278 | _("invalid smc expression")); |
2fc8bdac | 11279 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
11280 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
11281 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11282 | break; | |
a737bd4d | 11283 | |
c19d1205 | 11284 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 11285 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
11286 | { |
11287 | if (((unsigned long) value) > 0xff) | |
11288 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11289 | _("invalid swi expression")); | |
2fc8bdac | 11290 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
11291 | newval |= value; |
11292 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11293 | } | |
11294 | else | |
11295 | { | |
11296 | if (((unsigned long) value) > 0x00ffffff) | |
11297 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11298 | _("invalid swi expression")); | |
2fc8bdac | 11299 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
11300 | newval |= value; |
11301 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11302 | } | |
11303 | break; | |
a737bd4d | 11304 | |
c19d1205 ZW |
11305 | case BFD_RELOC_ARM_MULTI: |
11306 | if (((unsigned long) value) > 0xffff) | |
11307 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11308 | _("invalid expression in load/store multiple")); | |
11309 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
11310 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11311 | break; | |
a737bd4d | 11312 | |
c19d1205 | 11313 | case BFD_RELOC_ARM_PCREL_BRANCH: |
c19d1205 | 11314 | #ifdef OBJ_ELF |
2fc8bdac | 11315 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 11316 | #endif |
a737bd4d | 11317 | |
c19d1205 | 11318 | /* We are going to store value (shifted right by two) in the |
2fc8bdac ZW |
11319 | instruction, in a 24 bit, signed field. Bits 0 and 1 must be |
11320 | clear, and bits 26 through 32 either all clear or all set. */ | |
11321 | if (value & 0x00000003) | |
c19d1205 | 11322 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
11323 | _("misaligned branch destination")); |
11324 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
11325 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
11326 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11327 | _("branch out of range")); | |
a737bd4d | 11328 | |
2fc8bdac | 11329 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 11330 | { |
2fc8bdac ZW |
11331 | newval = md_chars_to_number (buf, INSN_SIZE); |
11332 | newval |= (value >> 2) & 0x00ffffff; | |
11333 | md_number_to_chars (buf, newval, INSN_SIZE); | |
c19d1205 | 11334 | } |
c19d1205 | 11335 | break; |
a737bd4d | 11336 | |
c19d1205 | 11337 | case BFD_RELOC_ARM_PCREL_BLX: |
2fc8bdac ZW |
11338 | /* BLX allows bit 1 to be set in the branch destination, since |
11339 | it targets a Thumb instruction which is only required to be | |
11340 | aligned modulo 2. Other constraints are as for B/BL. */ | |
11341 | if (value & 0x00000001) | |
11342 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11343 | _("misaligned BLX destination")); | |
11344 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
11345 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
11346 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11347 | _("branch out of range")); | |
a737bd4d | 11348 | |
2fc8bdac ZW |
11349 | if (fixP->fx_done || !seg->use_rela_p) |
11350 | { | |
11351 | offsetT hbit; | |
11352 | hbit = (value >> 1) & 1; | |
11353 | value = (value >> 2) & 0x00ffffff; | |
a737bd4d | 11354 | |
2fc8bdac ZW |
11355 | newval = md_chars_to_number (buf, INSN_SIZE); |
11356 | newval |= value | hbit << 24; | |
11357 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11358 | } | |
c19d1205 | 11359 | break; |
a737bd4d | 11360 | |
c19d1205 | 11361 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */ |
2fc8bdac ZW |
11362 | /* CZB can only branch forward. */ |
11363 | if (value & ~0x7e) | |
11364 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11365 | _("branch out of range")); | |
a737bd4d | 11366 | |
2fc8bdac ZW |
11367 | if (fixP->fx_done || !seg->use_rela_p) |
11368 | { | |
11369 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
c19d1205 | 11370 | newval |= ((value & 0x2e) << 2) | ((value & 0x40) << 3); |
2fc8bdac ZW |
11371 | md_number_to_chars (buf, newval, THUMB_SIZE); |
11372 | } | |
c19d1205 | 11373 | break; |
a737bd4d | 11374 | |
c19d1205 | 11375 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac ZW |
11376 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
11377 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11378 | _("branch out of range")); | |
a737bd4d | 11379 | |
2fc8bdac ZW |
11380 | if (fixP->fx_done || !seg->use_rela_p) |
11381 | { | |
11382 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11383 | newval |= (value & 0x1ff) >> 1; | |
11384 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11385 | } | |
c19d1205 | 11386 | break; |
a737bd4d | 11387 | |
c19d1205 | 11388 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac ZW |
11389 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
11390 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11391 | _("branch out of range")); | |
a737bd4d | 11392 | |
2fc8bdac ZW |
11393 | if (fixP->fx_done || !seg->use_rela_p) |
11394 | { | |
11395 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11396 | newval |= (value & 0xfff) >> 1; | |
11397 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11398 | } | |
c19d1205 | 11399 | break; |
a737bd4d | 11400 | |
c19d1205 | 11401 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
2fc8bdac ZW |
11402 | if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) |
11403 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11404 | _("conditional branch out of range")); | |
404ff6b5 | 11405 | |
2fc8bdac ZW |
11406 | if (fixP->fx_done || !seg->use_rela_p) |
11407 | { | |
11408 | offsetT newval2; | |
11409 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 11410 | |
2fc8bdac ZW |
11411 | S = (value & 0x00100000) >> 20; |
11412 | J2 = (value & 0x00080000) >> 19; | |
11413 | J1 = (value & 0x00040000) >> 18; | |
11414 | hi = (value & 0x0003f000) >> 12; | |
11415 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 11416 | |
2fc8bdac ZW |
11417 | newval = md_chars_to_number (buf, THUMB_SIZE); |
11418 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
11419 | newval |= (S << 10) | hi; | |
11420 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
11421 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11422 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
11423 | } | |
c19d1205 | 11424 | break; |
6c43fab6 | 11425 | |
c19d1205 ZW |
11426 | case BFD_RELOC_THUMB_PCREL_BLX: |
11427 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
2fc8bdac ZW |
11428 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
11429 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11430 | _("branch out of range")); | |
404ff6b5 | 11431 | |
2fc8bdac ZW |
11432 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
11433 | /* For a BLX instruction, make sure that the relocation is rounded up | |
11434 | to a word boundary. This follows the semantics of the instruction | |
11435 | which specifies that bit 1 of the target address will come from bit | |
11436 | 1 of the base address. */ | |
11437 | value = (value + 1) & ~ 1; | |
404ff6b5 | 11438 | |
2fc8bdac | 11439 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 11440 | { |
2fc8bdac ZW |
11441 | offsetT newval2; |
11442 | ||
11443 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11444 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
11445 | newval |= (value & 0x7fffff) >> 12; | |
11446 | newval2 |= (value & 0xfff) >> 1; | |
11447 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11448 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
c19d1205 | 11449 | } |
c19d1205 | 11450 | break; |
404ff6b5 | 11451 | |
c19d1205 | 11452 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac ZW |
11453 | if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) |
11454 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11455 | _("branch out of range")); | |
6c43fab6 | 11456 | |
2fc8bdac ZW |
11457 | if (fixP->fx_done || !seg->use_rela_p) |
11458 | { | |
11459 | offsetT newval2; | |
11460 | addressT S, I1, I2, lo, hi; | |
6c43fab6 | 11461 | |
2fc8bdac ZW |
11462 | S = (value & 0x01000000) >> 24; |
11463 | I1 = (value & 0x00800000) >> 23; | |
11464 | I2 = (value & 0x00400000) >> 22; | |
11465 | hi = (value & 0x003ff000) >> 12; | |
11466 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 11467 | |
2fc8bdac ZW |
11468 | I1 = !(I1 ^ S); |
11469 | I2 = !(I2 ^ S); | |
a737bd4d | 11470 | |
2fc8bdac ZW |
11471 | newval = md_chars_to_number (buf, THUMB_SIZE); |
11472 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
11473 | newval |= (S << 10) | hi; | |
11474 | newval2 |= (I1 << 13) | (I2 << 11) | lo; | |
11475 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11476 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
11477 | } | |
11478 | break; | |
a737bd4d | 11479 | |
2fc8bdac ZW |
11480 | case BFD_RELOC_8: |
11481 | if (fixP->fx_done || !seg->use_rela_p) | |
11482 | md_number_to_chars (buf, value, 1); | |
c19d1205 | 11483 | break; |
a737bd4d | 11484 | |
c19d1205 | 11485 | case BFD_RELOC_16: |
2fc8bdac | 11486 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 11487 | md_number_to_chars (buf, value, 2); |
c19d1205 | 11488 | break; |
a737bd4d | 11489 | |
c19d1205 ZW |
11490 | #ifdef OBJ_ELF |
11491 | case BFD_RELOC_ARM_TLS_GD32: | |
11492 | case BFD_RELOC_ARM_TLS_LE32: | |
11493 | case BFD_RELOC_ARM_TLS_IE32: | |
11494 | case BFD_RELOC_ARM_TLS_LDM32: | |
11495 | case BFD_RELOC_ARM_TLS_LDO32: | |
11496 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11497 | /* fall through */ | |
6c43fab6 | 11498 | |
c19d1205 ZW |
11499 | case BFD_RELOC_ARM_GOT32: |
11500 | case BFD_RELOC_ARM_GOTOFF: | |
11501 | case BFD_RELOC_ARM_TARGET2: | |
2fc8bdac ZW |
11502 | if (fixP->fx_done || !seg->use_rela_p) |
11503 | md_number_to_chars (buf, 0, 4); | |
c19d1205 ZW |
11504 | break; |
11505 | #endif | |
6c43fab6 | 11506 | |
c19d1205 ZW |
11507 | case BFD_RELOC_RVA: |
11508 | case BFD_RELOC_32: | |
11509 | case BFD_RELOC_ARM_TARGET1: | |
11510 | case BFD_RELOC_ARM_ROSEGREL32: | |
11511 | case BFD_RELOC_ARM_SBREL32: | |
11512 | case BFD_RELOC_32_PCREL: | |
2fc8bdac | 11513 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 11514 | md_number_to_chars (buf, value, 4); |
c19d1205 | 11515 | break; |
6c43fab6 | 11516 | |
c19d1205 ZW |
11517 | #ifdef OBJ_ELF |
11518 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 11519 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
11520 | { |
11521 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
11522 | if ((value ^ (value >> 1)) & 0x40000000) | |
11523 | { | |
11524 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11525 | _("rel31 relocation overflow")); | |
11526 | } | |
11527 | newval |= value & 0x7fffffff; | |
11528 | md_number_to_chars (buf, newval, 4); | |
11529 | } | |
11530 | break; | |
c19d1205 | 11531 | #endif |
a737bd4d | 11532 | |
c19d1205 | 11533 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 11534 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
c19d1205 ZW |
11535 | if (value < -1023 || value > 1023 || (value & 3)) |
11536 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11537 | _("co-processor offset out of range")); | |
11538 | cp_off_common: | |
11539 | sign = value >= 0; | |
11540 | if (value < 0) | |
11541 | value = -value; | |
8f06b2d8 PB |
11542 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
11543 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
11544 | newval = md_chars_to_number (buf, INSN_SIZE); | |
11545 | else | |
11546 | newval = get_thumb32_insn (buf); | |
11547 | newval &= 0xff7fff00; | |
c19d1205 ZW |
11548 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); |
11549 | if (value == 0) | |
11550 | newval &= ~WRITE_BACK; | |
8f06b2d8 PB |
11551 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
11552 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
11553 | md_number_to_chars (buf, newval, INSN_SIZE); | |
11554 | else | |
11555 | put_thumb32_insn (buf, newval); | |
c19d1205 | 11556 | break; |
a737bd4d | 11557 | |
c19d1205 | 11558 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 11559 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
11560 | if (value < -255 || value > 255) |
11561 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11562 | _("co-processor offset out of range")); | |
11563 | goto cp_off_common; | |
6c43fab6 | 11564 | |
c19d1205 ZW |
11565 | case BFD_RELOC_ARM_THUMB_OFFSET: |
11566 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11567 | /* Exactly what ranges, and where the offset is inserted depends | |
11568 | on the type of instruction, we can establish this from the | |
11569 | top 4 bits. */ | |
11570 | switch (newval >> 12) | |
11571 | { | |
11572 | case 4: /* PC load. */ | |
11573 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
11574 | forced to zero for these loads; md_pcrel_from has already | |
11575 | compensated for this. */ | |
11576 | if (value & 3) | |
11577 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11578 | _("invalid offset, target not word aligned (0x%08lX)"), | |
11579 | (((unsigned int) fixP->fx_frag->fr_address | |
11580 | + (unsigned int) fixP->fx_where) & ~3) + value); | |
a737bd4d | 11581 | |
c19d1205 ZW |
11582 | if (value & ~0x3fc) |
11583 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11584 | _("invalid offset, value too big (0x%08lX)"), | |
11585 | (long) value); | |
a737bd4d | 11586 | |
c19d1205 ZW |
11587 | newval |= value >> 2; |
11588 | break; | |
a737bd4d | 11589 | |
c19d1205 ZW |
11590 | case 9: /* SP load/store. */ |
11591 | if (value & ~0x3fc) | |
11592 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11593 | _("invalid offset, value too big (0x%08lX)"), | |
11594 | (long) value); | |
11595 | newval |= value >> 2; | |
11596 | break; | |
6c43fab6 | 11597 | |
c19d1205 ZW |
11598 | case 6: /* Word load/store. */ |
11599 | if (value & ~0x7c) | |
11600 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11601 | _("invalid offset, value too big (0x%08lX)"), | |
11602 | (long) value); | |
11603 | newval |= value << 4; /* 6 - 2. */ | |
11604 | break; | |
a737bd4d | 11605 | |
c19d1205 ZW |
11606 | case 7: /* Byte load/store. */ |
11607 | if (value & ~0x1f) | |
11608 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11609 | _("invalid offset, value too big (0x%08lX)"), | |
11610 | (long) value); | |
11611 | newval |= value << 6; | |
11612 | break; | |
a737bd4d | 11613 | |
c19d1205 ZW |
11614 | case 8: /* Halfword load/store. */ |
11615 | if (value & ~0x3e) | |
11616 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11617 | _("invalid offset, value too big (0x%08lX)"), | |
11618 | (long) value); | |
11619 | newval |= value << 5; /* 6 - 1. */ | |
11620 | break; | |
a737bd4d | 11621 | |
c19d1205 ZW |
11622 | default: |
11623 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11624 | "Unable to process relocation for thumb opcode: %lx", | |
11625 | (unsigned long) newval); | |
11626 | break; | |
11627 | } | |
11628 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11629 | break; | |
a737bd4d | 11630 | |
c19d1205 ZW |
11631 | case BFD_RELOC_ARM_THUMB_ADD: |
11632 | /* This is a complicated relocation, since we use it for all of | |
11633 | the following immediate relocations: | |
a737bd4d | 11634 | |
c19d1205 ZW |
11635 | 3bit ADD/SUB |
11636 | 8bit ADD/SUB | |
11637 | 9bit ADD/SUB SP word-aligned | |
11638 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 11639 | |
c19d1205 ZW |
11640 | The type of instruction being processed is encoded in the |
11641 | instruction field: | |
a737bd4d | 11642 | |
c19d1205 ZW |
11643 | 0x8000 SUB |
11644 | 0x00F0 Rd | |
11645 | 0x000F Rs | |
11646 | */ | |
11647 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11648 | { | |
11649 | int rd = (newval >> 4) & 0xf; | |
11650 | int rs = newval & 0xf; | |
11651 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 11652 | |
c19d1205 ZW |
11653 | /* Check for HI regs, only very restricted cases allowed: |
11654 | Adjusting SP, and using PC or SP to get an address. */ | |
11655 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
11656 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
11657 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11658 | _("invalid Hi register with immediate")); | |
a737bd4d | 11659 | |
c19d1205 ZW |
11660 | /* If value is negative, choose the opposite instruction. */ |
11661 | if (value < 0) | |
11662 | { | |
11663 | value = -value; | |
11664 | subtract = !subtract; | |
11665 | if (value < 0) | |
11666 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11667 | _("immediate value out of range")); | |
11668 | } | |
a737bd4d | 11669 | |
c19d1205 ZW |
11670 | if (rd == REG_SP) |
11671 | { | |
11672 | if (value & ~0x1fc) | |
11673 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11674 | _("invalid immediate for stack address calculation")); | |
11675 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
11676 | newval |= value >> 2; | |
11677 | } | |
11678 | else if (rs == REG_PC || rs == REG_SP) | |
11679 | { | |
11680 | if (subtract || value & ~0x3fc) | |
11681 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11682 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
11683 | (unsigned long) value); | |
11684 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); | |
11685 | newval |= rd << 8; | |
11686 | newval |= value >> 2; | |
11687 | } | |
11688 | else if (rs == rd) | |
11689 | { | |
11690 | if (value & ~0xff) | |
11691 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11692 | _("immediate value out of range")); | |
11693 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
11694 | newval |= (rd << 8) | value; | |
11695 | } | |
11696 | else | |
11697 | { | |
11698 | if (value & ~0x7) | |
11699 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11700 | _("immediate value out of range")); | |
11701 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
11702 | newval |= rd | (rs << 3) | (value << 6); | |
11703 | } | |
11704 | } | |
11705 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11706 | break; | |
a737bd4d | 11707 | |
c19d1205 ZW |
11708 | case BFD_RELOC_ARM_THUMB_IMM: |
11709 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
11710 | if (value < 0 || value > 255) | |
11711 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11712 | _("invalid immediate: %ld is too large"), | |
11713 | (long) value); | |
11714 | newval |= value; | |
11715 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11716 | break; | |
a737bd4d | 11717 | |
c19d1205 ZW |
11718 | case BFD_RELOC_ARM_THUMB_SHIFT: |
11719 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
11720 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
11721 | temp = newval & 0xf800; | |
11722 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
11723 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11724 | _("invalid shift value: %ld"), (long) value); | |
11725 | /* Shifts of zero must be encoded as LSL. */ | |
11726 | if (value == 0) | |
11727 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
11728 | /* Shifts of 32 are encoded as zero. */ | |
11729 | else if (value == 32) | |
11730 | value = 0; | |
11731 | newval |= value << 6; | |
11732 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
11733 | break; | |
a737bd4d | 11734 | |
c19d1205 ZW |
11735 | case BFD_RELOC_VTABLE_INHERIT: |
11736 | case BFD_RELOC_VTABLE_ENTRY: | |
11737 | fixP->fx_done = 0; | |
11738 | return; | |
6c43fab6 | 11739 | |
c19d1205 ZW |
11740 | case BFD_RELOC_UNUSED: |
11741 | default: | |
11742 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11743 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
11744 | } | |
6c43fab6 RE |
11745 | } |
11746 | ||
c19d1205 ZW |
11747 | /* Translate internal representation of relocation info to BFD target |
11748 | format. */ | |
a737bd4d | 11749 | |
c19d1205 ZW |
11750 | arelent * |
11751 | tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, | |
11752 | fixS * fixp) | |
a737bd4d | 11753 | { |
c19d1205 ZW |
11754 | arelent * reloc; |
11755 | bfd_reloc_code_real_type code; | |
a737bd4d | 11756 | |
c19d1205 | 11757 | reloc = xmalloc (sizeof (arelent)); |
a737bd4d | 11758 | |
c19d1205 ZW |
11759 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); |
11760 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
11761 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 11762 | |
2fc8bdac ZW |
11763 | if (fixp->fx_pcrel) |
11764 | fixp->fx_offset = reloc->address; | |
c19d1205 | 11765 | reloc->addend = fixp->fx_offset; |
a737bd4d | 11766 | |
c19d1205 | 11767 | switch (fixp->fx_r_type) |
a737bd4d | 11768 | { |
c19d1205 ZW |
11769 | case BFD_RELOC_8: |
11770 | if (fixp->fx_pcrel) | |
11771 | { | |
11772 | code = BFD_RELOC_8_PCREL; | |
11773 | break; | |
11774 | } | |
a737bd4d | 11775 | |
c19d1205 ZW |
11776 | case BFD_RELOC_16: |
11777 | if (fixp->fx_pcrel) | |
11778 | { | |
11779 | code = BFD_RELOC_16_PCREL; | |
11780 | break; | |
11781 | } | |
6c43fab6 | 11782 | |
c19d1205 ZW |
11783 | case BFD_RELOC_32: |
11784 | if (fixp->fx_pcrel) | |
11785 | { | |
11786 | code = BFD_RELOC_32_PCREL; | |
11787 | break; | |
11788 | } | |
a737bd4d | 11789 | |
c19d1205 ZW |
11790 | case BFD_RELOC_NONE: |
11791 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
11792 | case BFD_RELOC_ARM_PCREL_BLX: | |
11793 | case BFD_RELOC_RVA: | |
11794 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
11795 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
11796 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
11797 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
11798 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
11799 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
11800 | case BFD_RELOC_THUMB_PCREL_BLX: | |
11801 | case BFD_RELOC_VTABLE_ENTRY: | |
11802 | case BFD_RELOC_VTABLE_INHERIT: | |
11803 | code = fixp->fx_r_type; | |
11804 | break; | |
a737bd4d | 11805 | |
c19d1205 ZW |
11806 | case BFD_RELOC_ARM_LITERAL: |
11807 | case BFD_RELOC_ARM_HWLITERAL: | |
11808 | /* If this is called then the a literal has | |
11809 | been referenced across a section boundary. */ | |
11810 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11811 | _("literal referenced across section boundary")); | |
11812 | return NULL; | |
a737bd4d | 11813 | |
c19d1205 ZW |
11814 | #ifdef OBJ_ELF |
11815 | case BFD_RELOC_ARM_GOT32: | |
11816 | case BFD_RELOC_ARM_GOTOFF: | |
11817 | case BFD_RELOC_ARM_PLT32: | |
11818 | case BFD_RELOC_ARM_TARGET1: | |
11819 | case BFD_RELOC_ARM_ROSEGREL32: | |
11820 | case BFD_RELOC_ARM_SBREL32: | |
11821 | case BFD_RELOC_ARM_PREL31: | |
11822 | case BFD_RELOC_ARM_TARGET2: | |
11823 | case BFD_RELOC_ARM_TLS_LE32: | |
11824 | case BFD_RELOC_ARM_TLS_LDO32: | |
11825 | code = fixp->fx_r_type; | |
11826 | break; | |
a737bd4d | 11827 | |
c19d1205 ZW |
11828 | case BFD_RELOC_ARM_TLS_GD32: |
11829 | case BFD_RELOC_ARM_TLS_IE32: | |
11830 | case BFD_RELOC_ARM_TLS_LDM32: | |
11831 | /* BFD will include the symbol's address in the addend. | |
11832 | But we don't want that, so subtract it out again here. */ | |
11833 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
11834 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
11835 | code = fixp->fx_r_type; | |
11836 | break; | |
11837 | #endif | |
a737bd4d | 11838 | |
c19d1205 ZW |
11839 | case BFD_RELOC_ARM_IMMEDIATE: |
11840 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11841 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
11842 | return NULL; | |
a737bd4d | 11843 | |
c19d1205 ZW |
11844 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
11845 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11846 | _("ADRL used for a symbol not defined in the same file")); | |
11847 | return NULL; | |
a737bd4d | 11848 | |
c19d1205 ZW |
11849 | case BFD_RELOC_ARM_OFFSET_IMM: |
11850 | if (fixp->fx_addsy != NULL | |
11851 | && !S_IS_DEFINED (fixp->fx_addsy) | |
11852 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 11853 | { |
c19d1205 ZW |
11854 | as_bad_where (fixp->fx_file, fixp->fx_line, |
11855 | _("undefined local label `%s'"), | |
11856 | S_GET_NAME (fixp->fx_addsy)); | |
11857 | return NULL; | |
a737bd4d NC |
11858 | } |
11859 | ||
c19d1205 ZW |
11860 | as_bad_where (fixp->fx_file, fixp->fx_line, |
11861 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
11862 | return NULL; | |
a737bd4d | 11863 | |
c19d1205 ZW |
11864 | default: |
11865 | { | |
11866 | char * type; | |
6c43fab6 | 11867 | |
c19d1205 ZW |
11868 | switch (fixp->fx_r_type) |
11869 | { | |
11870 | case BFD_RELOC_NONE: type = "NONE"; break; | |
11871 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
11872 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 11873 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
11874 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
11875 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
11876 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
8f06b2d8 | 11877 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
11878 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
11879 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
11880 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
11881 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
11882 | default: type = _("<unknown>"); break; | |
11883 | } | |
11884 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11885 | _("cannot represent %s relocation in this object file format"), | |
11886 | type); | |
11887 | return NULL; | |
11888 | } | |
a737bd4d | 11889 | } |
6c43fab6 | 11890 | |
c19d1205 ZW |
11891 | #ifdef OBJ_ELF |
11892 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
11893 | && GOT_symbol | |
11894 | && fixp->fx_addsy == GOT_symbol) | |
11895 | { | |
11896 | code = BFD_RELOC_ARM_GOTPC; | |
11897 | reloc->addend = fixp->fx_offset = reloc->address; | |
11898 | } | |
11899 | #endif | |
6c43fab6 | 11900 | |
c19d1205 | 11901 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 11902 | |
c19d1205 ZW |
11903 | if (reloc->howto == NULL) |
11904 | { | |
11905 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11906 | _("cannot represent %s relocation in this object file format"), | |
11907 | bfd_get_reloc_code_name (code)); | |
11908 | return NULL; | |
11909 | } | |
6c43fab6 | 11910 | |
c19d1205 ZW |
11911 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
11912 | vtable entry to be used in the relocation's section offset. */ | |
11913 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11914 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 11915 | |
c19d1205 | 11916 | return reloc; |
6c43fab6 RE |
11917 | } |
11918 | ||
c19d1205 | 11919 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 11920 | |
c19d1205 ZW |
11921 | void |
11922 | cons_fix_new_arm (fragS * frag, | |
11923 | int where, | |
11924 | int size, | |
11925 | expressionS * exp) | |
6c43fab6 | 11926 | { |
c19d1205 ZW |
11927 | bfd_reloc_code_real_type type; |
11928 | int pcrel = 0; | |
6c43fab6 | 11929 | |
c19d1205 ZW |
11930 | /* Pick a reloc. |
11931 | FIXME: @@ Should look at CPU word size. */ | |
11932 | switch (size) | |
11933 | { | |
11934 | case 1: | |
11935 | type = BFD_RELOC_8; | |
11936 | break; | |
11937 | case 2: | |
11938 | type = BFD_RELOC_16; | |
11939 | break; | |
11940 | case 4: | |
11941 | default: | |
11942 | type = BFD_RELOC_32; | |
11943 | break; | |
11944 | case 8: | |
11945 | type = BFD_RELOC_64; | |
11946 | break; | |
11947 | } | |
6c43fab6 | 11948 | |
c19d1205 ZW |
11949 | fix_new_exp (frag, where, (int) size, exp, pcrel, type); |
11950 | } | |
6c43fab6 | 11951 | |
c19d1205 ZW |
11952 | #if defined OBJ_COFF || defined OBJ_ELF |
11953 | void | |
11954 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 11955 | { |
c19d1205 ZW |
11956 | /* If the destination of the branch is a defined symbol which does not have |
11957 | the THUMB_FUNC attribute, then we must be calling a function which has | |
11958 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
11959 | function and change the branch to refer to that function instead. */ | |
11960 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
11961 | && fixP->fx_addsy != NULL | |
11962 | && S_IS_DEFINED (fixP->fx_addsy) | |
11963 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 11964 | { |
c19d1205 | 11965 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 11966 | } |
c19d1205 ZW |
11967 | } |
11968 | #endif | |
6c43fab6 | 11969 | |
c19d1205 ZW |
11970 | int |
11971 | arm_force_relocation (struct fix * fixp) | |
11972 | { | |
11973 | #if defined (OBJ_COFF) && defined (TE_PE) | |
11974 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
11975 | return 1; | |
11976 | #endif | |
6c43fab6 | 11977 | |
c19d1205 ZW |
11978 | /* Resolve these relocations even if the symbol is extern or weak. */ |
11979 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE | |
11980 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
0110f2b8 PB |
11981 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
11982 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE | |
11983 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
11984 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12) | |
c19d1205 | 11985 | return 0; |
a737bd4d | 11986 | |
c19d1205 | 11987 | return generic_force_reloc (fixp); |
404ff6b5 AH |
11988 | } |
11989 | ||
c19d1205 ZW |
11990 | #ifdef OBJ_COFF |
11991 | /* This is a little hack to help the gas/arm/adrl.s test. It prevents | |
11992 | local labels from being added to the output symbol table when they | |
11993 | are used with the ADRL pseudo op. The ADRL relocation should always | |
11994 | be resolved before the binbary is emitted, so it is safe to say that | |
11995 | it is adjustable. */ | |
404ff6b5 | 11996 | |
c19d1205 ZW |
11997 | bfd_boolean |
11998 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 11999 | { |
c19d1205 ZW |
12000 | if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE) |
12001 | return 1; | |
12002 | return 0; | |
404ff6b5 | 12003 | } |
c19d1205 | 12004 | #endif |
404ff6b5 | 12005 | |
c19d1205 ZW |
12006 | #ifdef OBJ_ELF |
12007 | /* Relocations against Thumb function names must be left unadjusted, | |
12008 | so that the linker can use this information to correctly set the | |
12009 | bottom bit of their addresses. The MIPS version of this function | |
12010 | also prevents relocations that are mips-16 specific, but I do not | |
12011 | know why it does this. | |
404ff6b5 | 12012 | |
c19d1205 ZW |
12013 | FIXME: |
12014 | There is one other problem that ought to be addressed here, but | |
12015 | which currently is not: Taking the address of a label (rather | |
12016 | than a function) and then later jumping to that address. Such | |
12017 | addresses also ought to have their bottom bit set (assuming that | |
12018 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 12019 | |
c19d1205 ZW |
12020 | bfd_boolean |
12021 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 12022 | { |
c19d1205 ZW |
12023 | if (fixP->fx_addsy == NULL) |
12024 | return 1; | |
404ff6b5 | 12025 | |
c19d1205 ZW |
12026 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
12027 | && fixP->fx_subsy == NULL) | |
12028 | return 0; | |
a737bd4d | 12029 | |
c19d1205 ZW |
12030 | /* We need the symbol name for the VTABLE entries. */ |
12031 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
12032 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12033 | return 0; | |
404ff6b5 | 12034 | |
c19d1205 ZW |
12035 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
12036 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
12037 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
12038 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
12039 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
12040 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 | |
12041 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
12042 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 | |
12043 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 | |
12044 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) | |
12045 | return 0; | |
a737bd4d | 12046 | |
c19d1205 | 12047 | return 1; |
a737bd4d | 12048 | } |
404ff6b5 | 12049 | |
c19d1205 ZW |
12050 | const char * |
12051 | elf32_arm_target_format (void) | |
404ff6b5 | 12052 | { |
c19d1205 ZW |
12053 | #ifdef TE_SYMBIAN |
12054 | return (target_big_endian | |
12055 | ? "elf32-bigarm-symbian" | |
12056 | : "elf32-littlearm-symbian"); | |
12057 | #elif defined (TE_VXWORKS) | |
12058 | return (target_big_endian | |
12059 | ? "elf32-bigarm-vxworks" | |
12060 | : "elf32-littlearm-vxworks"); | |
12061 | #else | |
12062 | if (target_big_endian) | |
12063 | return "elf32-bigarm"; | |
12064 | else | |
12065 | return "elf32-littlearm"; | |
12066 | #endif | |
404ff6b5 AH |
12067 | } |
12068 | ||
c19d1205 ZW |
12069 | void |
12070 | armelf_frob_symbol (symbolS * symp, | |
12071 | int * puntp) | |
404ff6b5 | 12072 | { |
c19d1205 ZW |
12073 | elf_frob_symbol (symp, puntp); |
12074 | } | |
12075 | #endif | |
404ff6b5 | 12076 | |
c19d1205 | 12077 | /* MD interface: Finalization. */ |
a737bd4d | 12078 | |
c19d1205 ZW |
12079 | /* A good place to do this, although this was probably not intended |
12080 | for this kind of use. We need to dump the literal pool before | |
12081 | references are made to a null symbol pointer. */ | |
a737bd4d | 12082 | |
c19d1205 ZW |
12083 | void |
12084 | arm_cleanup (void) | |
12085 | { | |
12086 | literal_pool * pool; | |
a737bd4d | 12087 | |
c19d1205 ZW |
12088 | for (pool = list_of_pools; pool; pool = pool->next) |
12089 | { | |
12090 | /* Put it at the end of the relevent section. */ | |
12091 | subseg_set (pool->section, pool->sub_section); | |
12092 | #ifdef OBJ_ELF | |
12093 | arm_elf_change_section (); | |
12094 | #endif | |
12095 | s_ltorg (0); | |
12096 | } | |
404ff6b5 AH |
12097 | } |
12098 | ||
c19d1205 ZW |
12099 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
12100 | ARM ones. */ | |
404ff6b5 | 12101 | |
c19d1205 ZW |
12102 | void |
12103 | arm_adjust_symtab (void) | |
404ff6b5 | 12104 | { |
c19d1205 ZW |
12105 | #ifdef OBJ_COFF |
12106 | symbolS * sym; | |
404ff6b5 | 12107 | |
c19d1205 ZW |
12108 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
12109 | { | |
12110 | if (ARM_IS_THUMB (sym)) | |
12111 | { | |
12112 | if (THUMB_IS_FUNC (sym)) | |
12113 | { | |
12114 | /* Mark the symbol as a Thumb function. */ | |
12115 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
12116 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
12117 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 12118 | |
c19d1205 ZW |
12119 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
12120 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
12121 | else | |
12122 | as_bad (_("%s: unexpected function type: %d"), | |
12123 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
12124 | } | |
12125 | else switch (S_GET_STORAGE_CLASS (sym)) | |
12126 | { | |
12127 | case C_EXT: | |
12128 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
12129 | break; | |
12130 | case C_STAT: | |
12131 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
12132 | break; | |
12133 | case C_LABEL: | |
12134 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
12135 | break; | |
12136 | default: | |
12137 | /* Do nothing. */ | |
12138 | break; | |
12139 | } | |
12140 | } | |
a737bd4d | 12141 | |
c19d1205 ZW |
12142 | if (ARM_IS_INTERWORK (sym)) |
12143 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 12144 | } |
c19d1205 ZW |
12145 | #endif |
12146 | #ifdef OBJ_ELF | |
12147 | symbolS * sym; | |
12148 | char bind; | |
404ff6b5 | 12149 | |
c19d1205 | 12150 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 12151 | { |
c19d1205 ZW |
12152 | if (ARM_IS_THUMB (sym)) |
12153 | { | |
12154 | elf_symbol_type * elf_sym; | |
404ff6b5 | 12155 | |
c19d1205 ZW |
12156 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
12157 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 12158 | |
c19d1205 ZW |
12159 | if (! bfd_is_arm_mapping_symbol_name (elf_sym->symbol.name)) |
12160 | { | |
12161 | /* If it's a .thumb_func, declare it as so, | |
12162 | otherwise tag label as .code 16. */ | |
12163 | if (THUMB_IS_FUNC (sym)) | |
12164 | elf_sym->internal_elf_sym.st_info = | |
12165 | ELF_ST_INFO (bind, STT_ARM_TFUNC); | |
12166 | else | |
12167 | elf_sym->internal_elf_sym.st_info = | |
12168 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
12169 | } | |
12170 | } | |
12171 | } | |
12172 | #endif | |
404ff6b5 AH |
12173 | } |
12174 | ||
c19d1205 | 12175 | /* MD interface: Initialization. */ |
404ff6b5 | 12176 | |
a737bd4d | 12177 | static void |
c19d1205 | 12178 | set_constant_flonums (void) |
a737bd4d | 12179 | { |
c19d1205 | 12180 | int i; |
404ff6b5 | 12181 | |
c19d1205 ZW |
12182 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
12183 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
12184 | abort (); | |
a737bd4d | 12185 | } |
404ff6b5 | 12186 | |
c19d1205 ZW |
12187 | void |
12188 | md_begin (void) | |
a737bd4d | 12189 | { |
c19d1205 ZW |
12190 | unsigned mach; |
12191 | unsigned int i; | |
404ff6b5 | 12192 | |
c19d1205 ZW |
12193 | if ( (arm_ops_hsh = hash_new ()) == NULL |
12194 | || (arm_cond_hsh = hash_new ()) == NULL | |
12195 | || (arm_shift_hsh = hash_new ()) == NULL | |
12196 | || (arm_psr_hsh = hash_new ()) == NULL | |
12197 | || (arm_reg_hsh = hash_new ()) == NULL | |
12198 | || (arm_reloc_hsh = hash_new ()) == NULL) | |
12199 | as_fatal (_("virtual memory exhausted")); | |
12200 | ||
12201 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
12202 | hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i)); | |
12203 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) | |
12204 | hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i)); | |
12205 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) | |
12206 | hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i)); | |
12207 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) | |
12208 | hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i)); | |
12209 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) | |
12210 | hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i)); | |
12211 | #ifdef OBJ_ELF | |
12212 | for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) | |
12213 | hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i)); | |
12214 | #endif | |
12215 | ||
12216 | set_constant_flonums (); | |
404ff6b5 | 12217 | |
c19d1205 ZW |
12218 | /* Set the cpu variant based on the command-line options. We prefer |
12219 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
12220 | -mfpu= over any other way of setting the floating point unit. | |
12221 | Use of legacy options with new options are faulted. */ | |
12222 | if (legacy_cpu != -1) | |
404ff6b5 | 12223 | { |
c19d1205 ZW |
12224 | if (mcpu_cpu_opt != -1 || march_cpu_opt != -1) |
12225 | as_bad (_("use of old and new-style options to set CPU type")); | |
12226 | ||
12227 | mcpu_cpu_opt = legacy_cpu; | |
404ff6b5 | 12228 | } |
c19d1205 ZW |
12229 | else if (mcpu_cpu_opt == -1) |
12230 | mcpu_cpu_opt = march_cpu_opt; | |
404ff6b5 | 12231 | |
c19d1205 ZW |
12232 | if (legacy_fpu != -1) |
12233 | { | |
12234 | if (mfpu_opt != -1) | |
12235 | as_bad (_("use of old and new-style options to set FPU type")); | |
03b1477f RE |
12236 | |
12237 | mfpu_opt = legacy_fpu; | |
12238 | } | |
12239 | else if (mfpu_opt == -1) | |
12240 | { | |
c19d1205 | 12241 | #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS)) |
39c2da32 RE |
12242 | /* Some environments specify a default FPU. If they don't, infer it |
12243 | from the processor. */ | |
03b1477f RE |
12244 | if (mcpu_fpu_opt != -1) |
12245 | mfpu_opt = mcpu_fpu_opt; | |
12246 | else | |
12247 | mfpu_opt = march_fpu_opt; | |
39c2da32 RE |
12248 | #else |
12249 | mfpu_opt = FPU_DEFAULT; | |
12250 | #endif | |
03b1477f RE |
12251 | } |
12252 | ||
12253 | if (mfpu_opt == -1) | |
12254 | { | |
12255 | if (mcpu_cpu_opt == -1) | |
12256 | mfpu_opt = FPU_DEFAULT; | |
12257 | else if (mcpu_cpu_opt & ARM_EXT_V5) | |
12258 | mfpu_opt = FPU_ARCH_VFP_V2; | |
12259 | else | |
12260 | mfpu_opt = FPU_ARCH_FPA; | |
12261 | } | |
12262 | ||
12263 | if (mcpu_cpu_opt == -1) | |
12264 | mcpu_cpu_opt = CPU_DEFAULT; | |
12265 | ||
12266 | cpu_variant = mcpu_cpu_opt | mfpu_opt; | |
12267 | ||
f17c130b | 12268 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 12269 | { |
7cc69913 NC |
12270 | unsigned int flags = 0; |
12271 | ||
12272 | #if defined OBJ_ELF | |
12273 | flags = meabi_flags; | |
d507cf36 PB |
12274 | |
12275 | switch (meabi_flags) | |
33a392fb | 12276 | { |
d507cf36 | 12277 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 12278 | #endif |
d507cf36 PB |
12279 | /* Set the flags in the private structure. */ |
12280 | if (uses_apcs_26) flags |= F_APCS26; | |
12281 | if (support_interwork) flags |= F_INTERWORK; | |
12282 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 12283 | if (pic_code) flags |= F_PIC; |
d507cf36 PB |
12284 | if ((cpu_variant & FPU_ANY) == FPU_NONE |
12285 | || (cpu_variant & FPU_ANY) == FPU_ARCH_VFP) /* VFP layout only. */ | |
7cc69913 NC |
12286 | flags |= F_SOFT_FLOAT; |
12287 | ||
d507cf36 PB |
12288 | switch (mfloat_abi_opt) |
12289 | { | |
12290 | case ARM_FLOAT_ABI_SOFT: | |
12291 | case ARM_FLOAT_ABI_SOFTFP: | |
12292 | flags |= F_SOFT_FLOAT; | |
12293 | break; | |
33a392fb | 12294 | |
d507cf36 PB |
12295 | case ARM_FLOAT_ABI_HARD: |
12296 | if (flags & F_SOFT_FLOAT) | |
12297 | as_bad (_("hard-float conflicts with specified fpu")); | |
12298 | break; | |
12299 | } | |
03b1477f | 12300 | |
c19d1205 | 12301 | /* Using VFP conventions (even if soft-float). */ |
7cc69913 NC |
12302 | if (cpu_variant & FPU_VFP_EXT_NONE) |
12303 | flags |= F_VFP_FLOAT; | |
f17c130b | 12304 | |
fde78edd | 12305 | #if defined OBJ_ELF |
d507cf36 PB |
12306 | if (cpu_variant & FPU_ARCH_MAVERICK) |
12307 | flags |= EF_ARM_MAVERICK_FLOAT; | |
d507cf36 PB |
12308 | break; |
12309 | ||
8cb51566 | 12310 | case EF_ARM_EABI_VER4: |
c19d1205 | 12311 | /* No additional flags to set. */ |
d507cf36 PB |
12312 | break; |
12313 | ||
12314 | default: | |
12315 | abort (); | |
12316 | } | |
7cc69913 | 12317 | #endif |
b99bd4ef NC |
12318 | bfd_set_private_flags (stdoutput, flags); |
12319 | ||
12320 | /* We have run out flags in the COFF header to encode the | |
12321 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 12322 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
12323 | if (atpcs) |
12324 | { | |
12325 | asection * sec; | |
12326 | ||
12327 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
12328 | ||
12329 | if (sec != NULL) | |
12330 | { | |
12331 | bfd_set_section_flags | |
12332 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
12333 | bfd_set_section_size (stdoutput, sec, 0); | |
12334 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
12335 | } | |
12336 | } | |
7cc69913 | 12337 | } |
f17c130b | 12338 | #endif |
b99bd4ef NC |
12339 | |
12340 | /* Record the CPU type as well. */ | |
12341 | switch (cpu_variant & ARM_CPU_MASK) | |
12342 | { | |
12343 | case ARM_2: | |
12344 | mach = bfd_mach_arm_2; | |
12345 | break; | |
12346 | ||
c19d1205 | 12347 | case ARM_3: /* Also ARM_250. */ |
b99bd4ef NC |
12348 | mach = bfd_mach_arm_2a; |
12349 | break; | |
12350 | ||
c19d1205 | 12351 | case ARM_6: /* Also ARM_7. */ |
b89dddec RE |
12352 | mach = bfd_mach_arm_3; |
12353 | break; | |
12354 | ||
b99bd4ef | 12355 | default: |
5a6c6817 | 12356 | mach = bfd_mach_arm_unknown; |
b99bd4ef | 12357 | break; |
b99bd4ef NC |
12358 | } |
12359 | ||
12360 | /* Catch special cases. */ | |
e16bb312 NC |
12361 | if (cpu_variant & ARM_CEXT_IWMMXT) |
12362 | mach = bfd_mach_arm_iWMMXt; | |
12363 | else if (cpu_variant & ARM_CEXT_XSCALE) | |
b99bd4ef | 12364 | mach = bfd_mach_arm_XScale; |
fde78edd NC |
12365 | else if (cpu_variant & ARM_CEXT_MAVERICK) |
12366 | mach = bfd_mach_arm_ep9312; | |
b99bd4ef NC |
12367 | else if (cpu_variant & ARM_EXT_V5E) |
12368 | mach = bfd_mach_arm_5TE; | |
12369 | else if (cpu_variant & ARM_EXT_V5) | |
12370 | { | |
b89dddec | 12371 | if (cpu_variant & ARM_EXT_V4T) |
b99bd4ef NC |
12372 | mach = bfd_mach_arm_5T; |
12373 | else | |
12374 | mach = bfd_mach_arm_5; | |
12375 | } | |
b89dddec | 12376 | else if (cpu_variant & ARM_EXT_V4) |
b99bd4ef | 12377 | { |
b89dddec | 12378 | if (cpu_variant & ARM_EXT_V4T) |
b99bd4ef NC |
12379 | mach = bfd_mach_arm_4T; |
12380 | else | |
12381 | mach = bfd_mach_arm_4; | |
12382 | } | |
b89dddec | 12383 | else if (cpu_variant & ARM_EXT_V3M) |
b99bd4ef NC |
12384 | mach = bfd_mach_arm_3M; |
12385 | ||
12386 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
12387 | } | |
12388 | ||
c19d1205 | 12389 | /* Command line processing. */ |
b99bd4ef | 12390 | |
c19d1205 ZW |
12391 | /* md_parse_option |
12392 | Invocation line includes a switch not recognized by the base assembler. | |
12393 | See if it's a processor-specific option. | |
b99bd4ef | 12394 | |
c19d1205 ZW |
12395 | This routine is somewhat complicated by the need for backwards |
12396 | compatibility (since older releases of gcc can't be changed). | |
12397 | The new options try to make the interface as compatible as | |
12398 | possible with GCC. | |
b99bd4ef | 12399 | |
c19d1205 | 12400 | New options (supported) are: |
b99bd4ef | 12401 | |
c19d1205 ZW |
12402 | -mcpu=<cpu name> Assemble for selected processor |
12403 | -march=<architecture name> Assemble for selected architecture | |
12404 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
12405 | -EB/-mbig-endian Big-endian | |
12406 | -EL/-mlittle-endian Little-endian | |
12407 | -k Generate PIC code | |
12408 | -mthumb Start in Thumb mode | |
12409 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 12410 | |
c19d1205 | 12411 | For now we will also provide support for: |
b99bd4ef | 12412 | |
c19d1205 ZW |
12413 | -mapcs-32 32-bit Program counter |
12414 | -mapcs-26 26-bit Program counter | |
12415 | -macps-float Floats passed in FP registers | |
12416 | -mapcs-reentrant Reentrant code | |
12417 | -matpcs | |
12418 | (sometime these will probably be replaced with -mapcs=<list of options> | |
12419 | and -matpcs=<list of options>) | |
b99bd4ef | 12420 | |
c19d1205 ZW |
12421 | The remaining options are only supported for back-wards compatibility. |
12422 | Cpu variants, the arm part is optional: | |
12423 | -m[arm]1 Currently not supported. | |
12424 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
12425 | -m[arm]3 Arm 3 processor | |
12426 | -m[arm]6[xx], Arm 6 processors | |
12427 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
12428 | -m[arm]8[10] Arm 8 processors | |
12429 | -m[arm]9[20][tdmi] Arm 9 processors | |
12430 | -mstrongarm[110[0]] StrongARM processors | |
12431 | -mxscale XScale processors | |
12432 | -m[arm]v[2345[t[e]]] Arm architectures | |
12433 | -mall All (except the ARM1) | |
12434 | FP variants: | |
12435 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
12436 | -mfpe-old (No float load/store multiples) | |
12437 | -mvfpxd VFP Single precision | |
12438 | -mvfp All VFP | |
12439 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 12440 | |
c19d1205 ZW |
12441 | The following CPU names are recognized: |
12442 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
12443 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
12444 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
12445 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
12446 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
12447 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
12448 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 12449 | |
c19d1205 | 12450 | */ |
b99bd4ef | 12451 | |
c19d1205 | 12452 | const char * md_shortopts = "m:k"; |
b99bd4ef | 12453 | |
c19d1205 ZW |
12454 | #ifdef ARM_BI_ENDIAN |
12455 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
12456 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 12457 | #else |
c19d1205 ZW |
12458 | #if TARGET_BYTES_BIG_ENDIAN |
12459 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 12460 | #else |
c19d1205 ZW |
12461 | #define OPTION_EL (OPTION_MD_BASE + 1) |
12462 | #endif | |
b99bd4ef | 12463 | #endif |
b99bd4ef | 12464 | |
c19d1205 | 12465 | struct option md_longopts[] = |
b99bd4ef | 12466 | { |
c19d1205 ZW |
12467 | #ifdef OPTION_EB |
12468 | {"EB", no_argument, NULL, OPTION_EB}, | |
12469 | #endif | |
12470 | #ifdef OPTION_EL | |
12471 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 12472 | #endif |
c19d1205 ZW |
12473 | {NULL, no_argument, NULL, 0} |
12474 | }; | |
b99bd4ef | 12475 | |
c19d1205 | 12476 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 12477 | |
c19d1205 | 12478 | struct arm_option_table |
b99bd4ef | 12479 | { |
c19d1205 ZW |
12480 | char *option; /* Option name to match. */ |
12481 | char *help; /* Help information. */ | |
12482 | int *var; /* Variable to change. */ | |
12483 | int value; /* What to change it to. */ | |
12484 | char *deprecated; /* If non-null, print this message. */ | |
12485 | }; | |
b99bd4ef | 12486 | |
c19d1205 ZW |
12487 | struct arm_option_table arm_opts[] = |
12488 | { | |
12489 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
12490 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
12491 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
12492 | &support_interwork, 1, NULL}, | |
12493 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
12494 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
12495 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
12496 | 1, NULL}, | |
12497 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
12498 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
12499 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
12500 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
12501 | NULL}, | |
b99bd4ef | 12502 | |
c19d1205 ZW |
12503 | /* These are recognized by the assembler, but have no affect on code. */ |
12504 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
12505 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
b99bd4ef | 12506 | |
c19d1205 ZW |
12507 | /* DON'T add any new processors to this list -- we want the whole list |
12508 | to go away... Add them to the processors table instead. */ | |
12509 | {"marm1", NULL, &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
12510 | {"m1", NULL, &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
12511 | {"marm2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
12512 | {"m2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
12513 | {"marm250", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
12514 | {"m250", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
12515 | {"marm3", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
12516 | {"m3", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
12517 | {"marm6", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
12518 | {"m6", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
12519 | {"marm600", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
12520 | {"m600", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
12521 | {"marm610", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
12522 | {"m610", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
12523 | {"marm620", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
12524 | {"m620", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
12525 | {"marm7", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
12526 | {"m7", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
12527 | {"marm70", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
12528 | {"m70", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
12529 | {"marm700", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
12530 | {"m700", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
12531 | {"marm700i", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
12532 | {"m700i", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
12533 | {"marm710", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
12534 | {"m710", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
12535 | {"marm710c", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
12536 | {"m710c", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
12537 | {"marm720", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
12538 | {"m720", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
12539 | {"marm7d", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
12540 | {"m7d", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
12541 | {"marm7di", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
12542 | {"m7di", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
12543 | {"marm7m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
12544 | {"m7m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
12545 | {"marm7dm", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
12546 | {"m7dm", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
12547 | {"marm7dmi", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
12548 | {"m7dmi", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
12549 | {"marm7100", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
12550 | {"m7100", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
12551 | {"marm7500", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
12552 | {"m7500", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
12553 | {"marm7500fe", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
12554 | {"m7500fe", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
12555 | {"marm7t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
12556 | {"m7t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
12557 | {"marm7tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
12558 | {"m7tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
12559 | {"marm710t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
12560 | {"m710t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
12561 | {"marm720t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
12562 | {"m720t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
12563 | {"marm740t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
12564 | {"m740t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
12565 | {"marm8", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
12566 | {"m8", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
12567 | {"marm810", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
12568 | {"m810", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
12569 | {"marm9", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
12570 | {"m9", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
12571 | {"marm9tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
12572 | {"m9tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
12573 | {"marm920", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
12574 | {"m920", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
12575 | {"marm940", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
12576 | {"m940", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
12577 | {"mstrongarm", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
12578 | {"mstrongarm110", NULL, &legacy_cpu, ARM_ARCH_V4, | |
12579 | N_("use -mcpu=strongarm110")}, | |
12580 | {"mstrongarm1100", NULL, &legacy_cpu, ARM_ARCH_V4, | |
12581 | N_("use -mcpu=strongarm1100")}, | |
12582 | {"mstrongarm1110", NULL, &legacy_cpu, ARM_ARCH_V4, | |
12583 | N_("use -mcpu=strongarm1110")}, | |
12584 | {"mxscale", NULL, &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, | |
12585 | {"miwmmxt", NULL, &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
12586 | {"mall", NULL, &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 12587 | |
c19d1205 ZW |
12588 | /* Architecture variants -- don't add any more to this list either. */ |
12589 | {"mv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
12590 | {"marmv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
12591 | {"mv2a", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
12592 | {"marmv2a", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
12593 | {"mv3", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
12594 | {"marmv3", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
12595 | {"mv3m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
12596 | {"marmv3m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
12597 | {"mv4", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
12598 | {"marmv4", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
12599 | {"mv4t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
12600 | {"marmv4t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
12601 | {"mv5", NULL, &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
12602 | {"marmv5", NULL, &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
12603 | {"mv5t", NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
12604 | {"marmv5t", NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
12605 | {"mv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
12606 | {"marmv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 12607 | |
c19d1205 ZW |
12608 | /* Floating point variants -- don't add any more to this list either. */ |
12609 | {"mfpe-old", NULL, &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, | |
12610 | {"mfpa10", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
12611 | {"mfpa11", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
12612 | {"mno-fpu", NULL, &legacy_fpu, 0, | |
12613 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, | |
7ed4c4c5 | 12614 | |
c19d1205 ZW |
12615 | {NULL, NULL, NULL, 0, NULL} |
12616 | }; | |
7ed4c4c5 | 12617 | |
c19d1205 | 12618 | struct arm_cpu_option_table |
7ed4c4c5 | 12619 | { |
c19d1205 ZW |
12620 | char *name; |
12621 | int value; | |
12622 | /* For some CPUs we assume an FPU unless the user explicitly sets | |
12623 | -mfpu=... */ | |
12624 | int default_fpu; | |
12625 | }; | |
7ed4c4c5 | 12626 | |
c19d1205 ZW |
12627 | /* This list should, at a minimum, contain all the cpu names |
12628 | recognized by GCC. */ | |
12629 | static struct arm_cpu_option_table arm_cpus[] = | |
12630 | { | |
12631 | {"all", ARM_ANY, FPU_ARCH_FPA}, | |
12632 | {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA}, | |
12633 | {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA}, | |
12634 | {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
12635 | {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
12636 | {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12637 | {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12638 | {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12639 | {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12640 | {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12641 | {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12642 | {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA}, | |
12643 | {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12644 | {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA}, | |
12645 | {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12646 | {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA}, | |
12647 | {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12648 | {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12649 | {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12650 | {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12651 | {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12652 | {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12653 | {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12654 | {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12655 | {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12656 | {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12657 | {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12658 | {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12659 | {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12660 | {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12661 | {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12662 | {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
12663 | {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
12664 | {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
12665 | {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
12666 | {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
12667 | {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
12668 | {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
12669 | {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12670 | {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12671 | {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12672 | {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12673 | {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12674 | {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12675 | /* For V5 or later processors we default to using VFP; but the user | |
12676 | should really set the FPU type explicitly. */ | |
12677 | {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2}, | |
12678 | {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2}, | |
12679 | {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2}, | |
12680 | {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2}, | |
12681 | {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2}, | |
12682 | {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2}, | |
12683 | {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2}, | |
db8ac8f9 | 12684 | {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2}, |
c19d1205 ZW |
12685 | {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2}, |
12686 | {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2}, | |
db8ac8f9 PB |
12687 | {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2}, |
12688 | {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2}, | |
c19d1205 | 12689 | {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1}, |
db8ac8f9 | 12690 | {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1}, |
c19d1205 ZW |
12691 | {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2}, |
12692 | {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2}, | |
12693 | {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1}, | |
12694 | {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2}, | |
db8ac8f9 | 12695 | {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2}, |
c19d1205 ZW |
12696 | {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2}, |
12697 | {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2}, | |
12698 | {"arm1136js", ARM_ARCH_V6, FPU_NONE}, | |
12699 | {"arm1136j-s", ARM_ARCH_V6, FPU_NONE}, | |
12700 | {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2}, | |
12701 | {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2}, | |
12702 | {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2}, | |
12703 | {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE}, | |
db8ac8f9 PB |
12704 | {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE}, |
12705 | {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2}, | |
c19d1205 ZW |
12706 | {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE}, |
12707 | {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2}, | |
12708 | /* ??? XSCALE is really an architecture. */ | |
12709 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2}, | |
12710 | /* ??? iwmmxt is not a processor. */ | |
12711 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2}, | |
12712 | {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2}, | |
12713 | /* Maverick */ | |
12714 | {"ep9312", ARM_ARCH_V4T | ARM_CEXT_MAVERICK, FPU_ARCH_MAVERICK}, | |
12715 | {NULL, 0, 0} | |
12716 | }; | |
7ed4c4c5 | 12717 | |
c19d1205 | 12718 | struct arm_arch_option_table |
7ed4c4c5 | 12719 | { |
c19d1205 ZW |
12720 | char *name; |
12721 | int value; | |
12722 | int default_fpu; | |
12723 | }; | |
7ed4c4c5 | 12724 | |
c19d1205 ZW |
12725 | /* This list should, at a minimum, contain all the architecture names |
12726 | recognized by GCC. */ | |
12727 | static struct arm_arch_option_table arm_archs[] = | |
12728 | { | |
12729 | {"all", ARM_ANY, FPU_ARCH_FPA}, | |
12730 | {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, | |
12731 | {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, | |
12732 | {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
12733 | {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
12734 | {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
12735 | {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, | |
12736 | {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
12737 | {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, | |
12738 | {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
12739 | {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, | |
12740 | {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, | |
12741 | {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, | |
12742 | {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, | |
12743 | {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, | |
12744 | {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, | |
12745 | {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, | |
12746 | {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
12747 | {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
12748 | {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, | |
12749 | {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, | |
12750 | {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, | |
12751 | {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, | |
12752 | {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, | |
12753 | {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, | |
12754 | {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, | |
12755 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, | |
12756 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, | |
12757 | {NULL, 0, 0} | |
12758 | }; | |
7ed4c4c5 | 12759 | |
c19d1205 ZW |
12760 | /* ISA extensions in the co-processor space. */ |
12761 | struct arm_option_value_table | |
12762 | { | |
12763 | char *name; | |
12764 | int value; | |
12765 | }; | |
7ed4c4c5 | 12766 | |
c19d1205 ZW |
12767 | static struct arm_option_value_table arm_extensions[] = |
12768 | { | |
12769 | {"maverick", ARM_CEXT_MAVERICK}, | |
12770 | {"xscale", ARM_CEXT_XSCALE}, | |
12771 | {"iwmmxt", ARM_CEXT_IWMMXT}, | |
12772 | {NULL, 0} | |
12773 | }; | |
7ed4c4c5 | 12774 | |
c19d1205 ZW |
12775 | /* This list should, at a minimum, contain all the fpu names |
12776 | recognized by GCC. */ | |
12777 | static struct arm_option_value_table arm_fpus[] = | |
12778 | { | |
12779 | {"softfpa", FPU_NONE}, | |
12780 | {"fpe", FPU_ARCH_FPE}, | |
12781 | {"fpe2", FPU_ARCH_FPE}, | |
12782 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
12783 | {"fpa", FPU_ARCH_FPA}, | |
12784 | {"fpa10", FPU_ARCH_FPA}, | |
12785 | {"fpa11", FPU_ARCH_FPA}, | |
12786 | {"arm7500fe", FPU_ARCH_FPA}, | |
12787 | {"softvfp", FPU_ARCH_VFP}, | |
12788 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
12789 | {"vfp", FPU_ARCH_VFP_V2}, | |
12790 | {"vfp9", FPU_ARCH_VFP_V2}, | |
12791 | {"vfp10", FPU_ARCH_VFP_V2}, | |
12792 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
12793 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
12794 | {"arm1020t", FPU_ARCH_VFP_V1}, | |
12795 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
12796 | {"arm1136jfs", FPU_ARCH_VFP_V2}, | |
12797 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, | |
12798 | {"maverick", FPU_ARCH_MAVERICK}, | |
12799 | {NULL, 0} | |
12800 | }; | |
7ed4c4c5 | 12801 | |
c19d1205 ZW |
12802 | static struct arm_option_value_table arm_float_abis[] = |
12803 | { | |
12804 | {"hard", ARM_FLOAT_ABI_HARD}, | |
12805 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
12806 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
12807 | {NULL, 0} | |
12808 | }; | |
7ed4c4c5 | 12809 | |
c19d1205 ZW |
12810 | #ifdef OBJ_ELF |
12811 | /* We only know how to output GNU and ver 4 (AAELF) formats. */ | |
12812 | static struct arm_option_value_table arm_eabis[] = | |
12813 | { | |
12814 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
12815 | {"4", EF_ARM_EABI_VER4}, | |
12816 | {NULL, 0} | |
12817 | }; | |
12818 | #endif | |
7ed4c4c5 | 12819 | |
c19d1205 ZW |
12820 | struct arm_long_option_table |
12821 | { | |
12822 | char * option; /* Substring to match. */ | |
12823 | char * help; /* Help information. */ | |
12824 | int (* func) (char * subopt); /* Function to decode sub-option. */ | |
12825 | char * deprecated; /* If non-null, print this message. */ | |
12826 | }; | |
7ed4c4c5 NC |
12827 | |
12828 | static int | |
c19d1205 | 12829 | arm_parse_extension (char * str, int * opt_p) |
7ed4c4c5 | 12830 | { |
c19d1205 | 12831 | while (str != NULL && *str != 0) |
7ed4c4c5 | 12832 | { |
c19d1205 ZW |
12833 | struct arm_option_value_table * opt; |
12834 | char * ext; | |
12835 | int optlen; | |
7ed4c4c5 | 12836 | |
c19d1205 ZW |
12837 | if (*str != '+') |
12838 | { | |
12839 | as_bad (_("invalid architectural extension")); | |
12840 | return 0; | |
12841 | } | |
7ed4c4c5 | 12842 | |
c19d1205 ZW |
12843 | str++; |
12844 | ext = strchr (str, '+'); | |
7ed4c4c5 | 12845 | |
c19d1205 ZW |
12846 | if (ext != NULL) |
12847 | optlen = ext - str; | |
12848 | else | |
12849 | optlen = strlen (str); | |
7ed4c4c5 | 12850 | |
c19d1205 ZW |
12851 | if (optlen == 0) |
12852 | { | |
12853 | as_bad (_("missing architectural extension")); | |
12854 | return 0; | |
12855 | } | |
7ed4c4c5 | 12856 | |
c19d1205 ZW |
12857 | for (opt = arm_extensions; opt->name != NULL; opt++) |
12858 | if (strncmp (opt->name, str, optlen) == 0) | |
12859 | { | |
12860 | *opt_p |= opt->value; | |
12861 | break; | |
12862 | } | |
7ed4c4c5 | 12863 | |
c19d1205 ZW |
12864 | if (opt->name == NULL) |
12865 | { | |
12866 | as_bad (_("unknown architectural extnsion `%s'"), str); | |
12867 | return 0; | |
12868 | } | |
7ed4c4c5 | 12869 | |
c19d1205 ZW |
12870 | str = ext; |
12871 | }; | |
7ed4c4c5 | 12872 | |
c19d1205 ZW |
12873 | return 1; |
12874 | } | |
7ed4c4c5 | 12875 | |
c19d1205 ZW |
12876 | static int |
12877 | arm_parse_cpu (char * str) | |
7ed4c4c5 | 12878 | { |
c19d1205 ZW |
12879 | struct arm_cpu_option_table * opt; |
12880 | char * ext = strchr (str, '+'); | |
12881 | int optlen; | |
7ed4c4c5 | 12882 | |
c19d1205 ZW |
12883 | if (ext != NULL) |
12884 | optlen = ext - str; | |
7ed4c4c5 | 12885 | else |
c19d1205 | 12886 | optlen = strlen (str); |
7ed4c4c5 | 12887 | |
c19d1205 | 12888 | if (optlen == 0) |
7ed4c4c5 | 12889 | { |
c19d1205 ZW |
12890 | as_bad (_("missing cpu name `%s'"), str); |
12891 | return 0; | |
7ed4c4c5 NC |
12892 | } |
12893 | ||
c19d1205 ZW |
12894 | for (opt = arm_cpus; opt->name != NULL; opt++) |
12895 | if (strncmp (opt->name, str, optlen) == 0) | |
12896 | { | |
12897 | mcpu_cpu_opt = opt->value; | |
12898 | mcpu_fpu_opt = opt->default_fpu; | |
7ed4c4c5 | 12899 | |
c19d1205 ZW |
12900 | if (ext != NULL) |
12901 | return arm_parse_extension (ext, &mcpu_cpu_opt); | |
7ed4c4c5 | 12902 | |
c19d1205 ZW |
12903 | return 1; |
12904 | } | |
7ed4c4c5 | 12905 | |
c19d1205 ZW |
12906 | as_bad (_("unknown cpu `%s'"), str); |
12907 | return 0; | |
7ed4c4c5 NC |
12908 | } |
12909 | ||
c19d1205 ZW |
12910 | static int |
12911 | arm_parse_arch (char * str) | |
7ed4c4c5 | 12912 | { |
c19d1205 ZW |
12913 | struct arm_arch_option_table *opt; |
12914 | char *ext = strchr (str, '+'); | |
12915 | int optlen; | |
7ed4c4c5 | 12916 | |
c19d1205 ZW |
12917 | if (ext != NULL) |
12918 | optlen = ext - str; | |
7ed4c4c5 | 12919 | else |
c19d1205 | 12920 | optlen = strlen (str); |
7ed4c4c5 | 12921 | |
c19d1205 | 12922 | if (optlen == 0) |
7ed4c4c5 | 12923 | { |
c19d1205 ZW |
12924 | as_bad (_("missing architecture name `%s'"), str); |
12925 | return 0; | |
7ed4c4c5 NC |
12926 | } |
12927 | ||
7ed4c4c5 | 12928 | |
c19d1205 ZW |
12929 | for (opt = arm_archs; opt->name != NULL; opt++) |
12930 | if (streq (opt->name, str)) | |
12931 | { | |
12932 | march_cpu_opt = opt->value; | |
12933 | march_fpu_opt = opt->default_fpu; | |
7ed4c4c5 | 12934 | |
c19d1205 ZW |
12935 | if (ext != NULL) |
12936 | return arm_parse_extension (ext, &march_cpu_opt); | |
7ed4c4c5 | 12937 | |
c19d1205 ZW |
12938 | return 1; |
12939 | } | |
12940 | ||
12941 | as_bad (_("unknown architecture `%s'\n"), str); | |
12942 | return 0; | |
7ed4c4c5 | 12943 | } |
eb043451 | 12944 | |
c19d1205 ZW |
12945 | static int |
12946 | arm_parse_fpu (char * str) | |
12947 | { | |
12948 | struct arm_option_value_table * opt; | |
b99bd4ef | 12949 | |
c19d1205 ZW |
12950 | for (opt = arm_fpus; opt->name != NULL; opt++) |
12951 | if (streq (opt->name, str)) | |
12952 | { | |
12953 | mfpu_opt = opt->value; | |
12954 | return 1; | |
12955 | } | |
b99bd4ef | 12956 | |
c19d1205 ZW |
12957 | as_bad (_("unknown floating point format `%s'\n"), str); |
12958 | return 0; | |
12959 | } | |
12960 | ||
12961 | static int | |
12962 | arm_parse_float_abi (char * str) | |
b99bd4ef | 12963 | { |
c19d1205 | 12964 | struct arm_option_value_table * opt; |
b99bd4ef | 12965 | |
c19d1205 ZW |
12966 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
12967 | if (streq (opt->name, str)) | |
12968 | { | |
12969 | mfloat_abi_opt = opt->value; | |
12970 | return 1; | |
12971 | } | |
cc8a6dd0 | 12972 | |
c19d1205 ZW |
12973 | as_bad (_("unknown floating point abi `%s'\n"), str); |
12974 | return 0; | |
12975 | } | |
b99bd4ef | 12976 | |
c19d1205 ZW |
12977 | #ifdef OBJ_ELF |
12978 | static int | |
12979 | arm_parse_eabi (char * str) | |
12980 | { | |
12981 | struct arm_option_value_table *opt; | |
cc8a6dd0 | 12982 | |
c19d1205 ZW |
12983 | for (opt = arm_eabis; opt->name != NULL; opt++) |
12984 | if (streq (opt->name, str)) | |
12985 | { | |
12986 | meabi_flags = opt->value; | |
12987 | return 1; | |
12988 | } | |
12989 | as_bad (_("unknown EABI `%s'\n"), str); | |
12990 | return 0; | |
12991 | } | |
12992 | #endif | |
cc8a6dd0 | 12993 | |
c19d1205 ZW |
12994 | struct arm_long_option_table arm_long_opts[] = |
12995 | { | |
12996 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
12997 | arm_parse_cpu, NULL}, | |
12998 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
12999 | arm_parse_arch, NULL}, | |
13000 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
13001 | arm_parse_fpu, NULL}, | |
13002 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
13003 | arm_parse_float_abi, NULL}, | |
13004 | #ifdef OBJ_ELF | |
13005 | {"meabi=", N_("<ver>\t assemble for eabi version <ver>"), | |
13006 | arm_parse_eabi, NULL}, | |
13007 | #endif | |
13008 | {NULL, NULL, 0, NULL} | |
13009 | }; | |
cc8a6dd0 | 13010 | |
c19d1205 ZW |
13011 | int |
13012 | md_parse_option (int c, char * arg) | |
13013 | { | |
13014 | struct arm_option_table *opt; | |
13015 | struct arm_long_option_table *lopt; | |
b99bd4ef | 13016 | |
c19d1205 | 13017 | switch (c) |
b99bd4ef | 13018 | { |
c19d1205 ZW |
13019 | #ifdef OPTION_EB |
13020 | case OPTION_EB: | |
13021 | target_big_endian = 1; | |
13022 | break; | |
13023 | #endif | |
cc8a6dd0 | 13024 | |
c19d1205 ZW |
13025 | #ifdef OPTION_EL |
13026 | case OPTION_EL: | |
13027 | target_big_endian = 0; | |
13028 | break; | |
13029 | #endif | |
b99bd4ef | 13030 | |
c19d1205 ZW |
13031 | case 'a': |
13032 | /* Listing option. Just ignore these, we don't support additional | |
13033 | ones. */ | |
13034 | return 0; | |
b99bd4ef | 13035 | |
c19d1205 ZW |
13036 | default: |
13037 | for (opt = arm_opts; opt->option != NULL; opt++) | |
13038 | { | |
13039 | if (c == opt->option[0] | |
13040 | && ((arg == NULL && opt->option[1] == 0) | |
13041 | || streq (arg, opt->option + 1))) | |
13042 | { | |
13043 | #if WARN_DEPRECATED | |
13044 | /* If the option is deprecated, tell the user. */ | |
13045 | if (opt->deprecated != NULL) | |
13046 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, | |
13047 | arg ? arg : "", _(opt->deprecated)); | |
13048 | #endif | |
b99bd4ef | 13049 | |
c19d1205 ZW |
13050 | if (opt->var != NULL) |
13051 | *opt->var = opt->value; | |
cc8a6dd0 | 13052 | |
c19d1205 ZW |
13053 | return 1; |
13054 | } | |
13055 | } | |
b99bd4ef | 13056 | |
c19d1205 ZW |
13057 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
13058 | { | |
13059 | /* These options are expected to have an argument. */ | |
13060 | if (c == lopt->option[0] | |
13061 | && arg != NULL | |
13062 | && strncmp (arg, lopt->option + 1, | |
13063 | strlen (lopt->option + 1)) == 0) | |
13064 | { | |
13065 | #if WARN_DEPRECATED | |
13066 | /* If the option is deprecated, tell the user. */ | |
13067 | if (lopt->deprecated != NULL) | |
13068 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, | |
13069 | _(lopt->deprecated)); | |
13070 | #endif | |
b99bd4ef | 13071 | |
c19d1205 ZW |
13072 | /* Call the sup-option parser. */ |
13073 | return lopt->func (arg + strlen (lopt->option) - 1); | |
13074 | } | |
13075 | } | |
a737bd4d | 13076 | |
c19d1205 ZW |
13077 | return 0; |
13078 | } | |
a394c00f | 13079 | |
c19d1205 ZW |
13080 | return 1; |
13081 | } | |
a394c00f | 13082 | |
c19d1205 ZW |
13083 | void |
13084 | md_show_usage (FILE * fp) | |
a394c00f | 13085 | { |
c19d1205 ZW |
13086 | struct arm_option_table *opt; |
13087 | struct arm_long_option_table *lopt; | |
a394c00f | 13088 | |
c19d1205 | 13089 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 13090 | |
c19d1205 ZW |
13091 | for (opt = arm_opts; opt->option != NULL; opt++) |
13092 | if (opt->help != NULL) | |
13093 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 13094 | |
c19d1205 ZW |
13095 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
13096 | if (lopt->help != NULL) | |
13097 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 13098 | |
c19d1205 ZW |
13099 | #ifdef OPTION_EB |
13100 | fprintf (fp, _("\ | |
13101 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
13102 | #endif |
13103 | ||
c19d1205 ZW |
13104 | #ifdef OPTION_EL |
13105 | fprintf (fp, _("\ | |
13106 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 13107 | #endif |
c19d1205 | 13108 | } |