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252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
aef6203b 3 2000, 2001, 2002, 2003, 2004, 2005
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 107static void output_imm PARAMS ((fragS *insn_start_frag,
108 offsetT insn_start_off));
109static void output_disp PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
29b0f896
AM		 111#ifndef I386COFF
112static void s_bss PARAMS ((int));
252b5132
RH		 113#endif
114
a847613f 115static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 116
252b5132 117/* 'md_assemble ()' gathers together information and puts it into a
47926f60 118 i386_insn. */
252b5132 119
520dc8e8
AM		 120union i386_op
121 {
122 expressionS *disps;
123 expressionS *imms;
124 const reg_entry *regs;
125 };
126
252b5132
RH		 127struct _i386_insn
128 {
47926f60 129 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 130 template tm;
131
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
134 char suffix;
135
47926f60 136 /* OPERANDS gives the number of given operands. */
252b5132
RH		 137 unsigned int operands;
138
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
47926f60 141 operands. */
252b5132
RH		 142 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
143
144 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 145 use OP[i] for the corresponding operand. */
252b5132
RH		 146 unsigned int types[MAX_OPERANDS];
147
520dc8e8
AM		 148 /* Displacement expression, immediate expression, or register for each
149 operand. */
150 union i386_op op[MAX_OPERANDS];
252b5132 151
3e73aa7c
JH		 152 /* Flags for operands. */
153 unsigned int flags[MAX_OPERANDS];
154#define Operand_PCrel 1
155
252b5132 156 /* Relocation type for operand */
f86103b7 157 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 158
252b5132
RH		 159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry *base_reg;
162 const reg_entry *index_reg;
163 unsigned int log2_scale_factor;
164
165 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 166 explicit segment overrides are given. */
ce8a8b2f 167 const seg_entry *seg[2];
252b5132
RH		 168
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes;
172 unsigned char prefix[MAX_PREFIXES];
173
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
176
177 modrm_byte rm;
3e73aa7c 178 rex_byte rex;
252b5132
RH		 179 sib_byte sib;
180 };
181
182typedef struct _i386_insn i386_insn;
183
184/* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
32137342 186const char extra_symbol_chars[] = "*%-(["
252b5132 187#ifdef LEX_AT
32137342
NC		 188 "@"
189#endif
190#ifdef LEX_QM
191 "?"
252b5132 192#endif
32137342 193 ;
252b5132 194
29b0f896
AM		 195#if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
32137342 198 && !defined (TE_NETWARE) \
29b0f896
AM		 199 && !defined (TE_FreeBSD) \
200 && !defined (TE_NetBSD)))
252b5132 201/* This array holds the chars that always start a comment. If the
ce8a8b2f 202 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 203const char comment_chars[] = "#/";
204#define PREFIX_SEPARATOR '\\'
252b5132
RH		 205
206/* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 210 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
252b5132 213 '/' isn't otherwise defined. */
0d9f6d04 214const char line_comment_chars[] = "#";
29b0f896 215
252b5132 216#else
29b0f896
AM		 217/* Putting '/' here makes it impossible to use the divide operator.
218 However, we need it for compatibility with SVR4 systems. */
219const char comment_chars[] = "#";
220#define PREFIX_SEPARATOR '/'
221
0d9f6d04 222const char line_comment_chars[] = "/#";
252b5132
RH		 223#endif
224
63a0b638 225const char line_separator_chars[] = ";";
252b5132 226
ce8a8b2f
AM		 227/* Chars that can be used to separate mant from exp in floating point
228 nums. */
252b5132
RH		 229const char EXP_CHARS[] = "eE";
230
ce8a8b2f
AM		 231/* Chars that mean this number is a floating point constant
232 As in 0f12.456
233 or 0d1.2345e12. */
252b5132
RH		 234const char FLT_CHARS[] = "fFdDxX";
235
ce8a8b2f 236/* Tables for lexical analysis. */
252b5132
RH		 237static char mnemonic_chars[256];
238static char register_chars[256];
239static char operand_chars[256];
240static char identifier_chars[256];
241static char digit_chars[256];
242
ce8a8b2f 243/* Lexical macros. */
252b5132
RH		 244#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
245#define is_operand_char(x) (operand_chars[(unsigned char) x])
246#define is_register_char(x) (register_chars[(unsigned char) x])
247#define is_space_char(x) ((x) == ' ')
248#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
249#define is_digit_char(x) (digit_chars[(unsigned char) x])
250
0234cb7c 251/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 252static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
253
254/* md_assemble() always leaves the strings it's passed unaltered. To
255 effect this we maintain a stack of saved characters that we've smashed
256 with '\0's (indicating end of strings for various sub-fields of the
47926f60 257 assembler instruction). */
252b5132 258static char save_stack[32];
ce8a8b2f 259static char *save_stack_p;
252b5132
RH		 260#define END_STRING_AND_SAVE(s) \
261 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
262#define RESTORE_END_STRING(s) \
263 do { *(s) = *--save_stack_p; } while (0)
264
47926f60 265/* The instruction we're assembling. */
252b5132
RH		 266static i386_insn i;
267
268/* Possible templates for current insn. */
269static const templates *current_templates;
270
47926f60 271/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 272static expressionS disp_expressions[2], im_expressions[2];
273
47926f60
KH		 274/* Current operand we are working on. */
275static int this_operand;
252b5132 276
3e73aa7c
JH		 277/* We support four different modes. FLAG_CODE variable is used to distinguish
278 these. */
279
280enum flag_code {
281 CODE_32BIT,
282 CODE_16BIT,
283 CODE_64BIT };
f3c180ae 284#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 285
286static enum flag_code flag_code;
287static int use_rela_relocations = 0;
288
289/* The names used to print error messages. */
b77a7acd 290static const char *flag_code_names[] =
3e73aa7c
JH		 291 {
292 "32",
293 "16",
294 "64"
295 };
252b5132 296
47926f60
KH		 297/* 1 for intel syntax,
298 0 if att syntax. */
299static int intel_syntax = 0;
252b5132 300
47926f60
KH		 301/* 1 if register prefix % not required. */
302static int allow_naked_reg = 0;
252b5132 303
47926f60
KH		 304/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
305 leave, push, and pop instructions so that gcc has the same stack
306 frame as in 32 bit mode. */
307static char stackop_size = '\0';
eecb386c 308
12b55ccc
L		 309/* Non-zero to optimize code alignment. */
310int optimize_align_code = 1;
311
47926f60
KH		 312/* Non-zero to quieten some warnings. */
313static int quiet_warnings = 0;
a38cf1db 314
47926f60
KH		 315/* CPU name. */
316static const char *cpu_arch_name = NULL;
5c6af06e 317static const char *cpu_sub_arch_name = NULL;
a38cf1db 318
47926f60 319/* CPU feature flags. */
29b0f896 320static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 321
fddf5b5b
AM		 322/* If set, conditional jumps are not automatically promoted to handle
323 larger than a byte offset. */
324static unsigned int no_cond_jump_promotion = 0;
325
29b0f896 326/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 327static symbolS *GOT_symbol;
29b0f896 328
a4447b93
RH		 329/* The dwarf2 return column, adjusted for 32 or 64 bit. */
330unsigned int x86_dwarf2_return_column;
331
332/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
333int x86_cie_data_alignment;
334
252b5132 335/* Interface to relax_segment.
fddf5b5b
AM		 336 There are 3 major relax states for 386 jump insns because the
337 different types of jumps add different sizes to frags when we're
338 figuring out what sort of jump to choose to reach a given label. */
252b5132 339
47926f60 340/* Types. */
93c2a809
AM		 341#define UNCOND_JUMP 0
342#define COND_JUMP 1
343#define COND_JUMP86 2
fddf5b5b 344
47926f60 345/* Sizes. */
252b5132
RH		 346#define CODE16 1
347#define SMALL 0
29b0f896 348#define SMALL16 (SMALL | CODE16)
252b5132 349#define BIG 2
29b0f896 350#define BIG16 (BIG | CODE16)
252b5132
RH		 351
352#ifndef INLINE
353#ifdef __GNUC__
354#define INLINE __inline__
355#else
356#define INLINE
357#endif
358#endif
359
fddf5b5b
AM		 360#define ENCODE_RELAX_STATE(type, size) \
361 ((relax_substateT) (((type) << 2) | (size)))
362#define TYPE_FROM_RELAX_STATE(s) \
363 ((s) >> 2)
364#define DISP_SIZE_FROM_RELAX_STATE(s) \
365 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 366
367/* This table is used by relax_frag to promote short jumps to long
368 ones where necessary. SMALL (short) jumps may be promoted to BIG
369 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
370 don't allow a short jump in a 32 bit code segment to be promoted to
371 a 16 bit offset jump because it's slower (requires data size
372 prefix), and doesn't work, unless the destination is in the bottom
373 64k of the code segment (The top 16 bits of eip are zeroed). */
374
375const relax_typeS md_relax_table[] =
376{
24eab124
AM		 377 /* The fields are:
378 1) most positive reach of this state,
379 2) most negative reach of this state,
93c2a809 380 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 381 4) which index into the table to try if we can't fit into this one. */
252b5132 382
fddf5b5b 383 /* UNCOND_JUMP states. */
93c2a809
AM		 384 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
386 /* dword jmp adds 4 bytes to frag:
387 0 extra opcode bytes, 4 displacement bytes. */
252b5132 388 {0, 0, 4, 0},
93c2a809
AM		 389 /* word jmp adds 2 byte2 to frag:
390 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 391 {0, 0, 2, 0},
392
93c2a809
AM		 393 /* COND_JUMP states. */
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
396 /* dword conditionals adds 5 bytes to frag:
397 1 extra opcode byte, 4 displacement bytes. */
398 {0, 0, 5, 0},
fddf5b5b 399 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 400 1 extra opcode byte, 2 displacement bytes. */
401 {0, 0, 3, 0},
402
403 /* COND_JUMP86 states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
406 /* dword conditionals adds 5 bytes to frag:
407 1 extra opcode byte, 4 displacement bytes. */
408 {0, 0, 5, 0},
409 /* word conditionals add 4 bytes to frag:
410 1 displacement byte and a 3 byte long branch insn. */
411 {0, 0, 4, 0}
252b5132
RH		 412};
413
e413e4e9
AM		 414static const arch_entry cpu_arch[] = {
415 {"i8086", Cpu086 },
416 {"i186", Cpu086|Cpu186 },
417 {"i286", Cpu086|Cpu186|Cpu286 },
418 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
419 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
5c6af06e
JB		 420 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
421 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
422 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
423 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
424 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
425 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
426 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
427 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
428 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
429 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
430 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
431 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
432 {".mmx", CpuMMX },
433 {".sse", CpuMMX|CpuMMX2|CpuSSE },
434 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
435 {".3dnow", CpuMMX|Cpu3dnow },
436 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
437 {".padlock", CpuPadLock },
e413e4e9
AM		 438 {NULL, 0 }
439};
440
29b0f896
AM		 441const pseudo_typeS md_pseudo_table[] =
442{
443#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
444 {"align", s_align_bytes, 0},
445#else
446 {"align", s_align_ptwo, 0},
447#endif
448 {"arch", set_cpu_arch, 0},
449#ifndef I386COFF
450 {"bss", s_bss, 0},
451#endif
452 {"ffloat", float_cons, 'f'},
453 {"dfloat", float_cons, 'd'},
454 {"tfloat", float_cons, 'x'},
455 {"value", cons, 2},
456 {"noopt", s_ignore, 0},
457 {"optim", s_ignore, 0},
458 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
459 {"code16", set_code_flag, CODE_16BIT},
460 {"code32", set_code_flag, CODE_32BIT},
461 {"code64", set_code_flag, CODE_64BIT},
462 {"intel_syntax", set_intel_syntax, 1},
463 {"att_syntax", set_intel_syntax, 0},
c6682705 464 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
29b0f896 465 {"loc", dwarf2_directive_loc, 0},
6482c264
NC		 466#ifdef TE_PE
467 {"secrel32", pe_directive_secrel, 0},
468#endif
29b0f896
AM		 469 {0, 0, 0}
470};
471
472/* For interface with expression (). */
473extern char *input_line_pointer;
474
475/* Hash table for instruction mnemonic lookup. */
476static struct hash_control *op_hash;
477
478/* Hash table for register lookup. */
479static struct hash_control *reg_hash;
480\f
252b5132
RH		 481void
482i386_align_code (fragP, count)
483 fragS *fragP;
484 int count;
485{
ce8a8b2f
AM		 486 /* Various efficient no-op patterns for aligning code labels.
487 Note: Don't try to assemble the instructions in the comments.
488 0L and 0w are not legal. */
252b5132
RH		 489 static const char f32_1[] =
490 {0x90}; /* nop */
491 static const char f32_2[] =
492 {0x89,0xf6}; /* movl %esi,%esi */
493 static const char f32_3[] =
494 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
495 static const char f32_4[] =
496 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
497 static const char f32_5[] =
498 {0x90, /* nop */
499 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
500 static const char f32_6[] =
501 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
502 static const char f32_7[] =
503 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
504 static const char f32_8[] =
505 {0x90, /* nop */
506 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
507 static const char f32_9[] =
508 {0x89,0xf6, /* movl %esi,%esi */
509 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
510 static const char f32_10[] =
511 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
512 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
513 static const char f32_11[] =
514 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
515 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
516 static const char f32_12[] =
517 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
518 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
519 static const char f32_13[] =
520 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
521 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
522 static const char f32_14[] =
523 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
524 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
525 static const char f32_15[] =
526 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
527 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 528 static const char f16_3[] =
529 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 530 static const char f16_4[] =
531 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
532 static const char f16_5[] =
533 {0x90, /* nop */
534 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
535 static const char f16_6[] =
536 {0x89,0xf6, /* mov %si,%si */
537 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
538 static const char f16_7[] =
539 {0x8d,0x74,0x00, /* lea 0(%si),%si */
540 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
541 static const char f16_8[] =
542 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
543 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
544 static const char *const f32_patt[] = {
545 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
546 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
547 };
548 static const char *const f16_patt[] = {
c3332e24 549 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 550 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
551 };
552
33fef721
JH		 553 if (count <= 0 || count > 15)
554 return;
3e73aa7c 555
33fef721
JH		 556 /* The recommended way to pad 64bit code is to use NOPs preceded by
557 maximally four 0x66 prefixes. Balance the size of nops. */
558 if (flag_code == CODE_64BIT)
252b5132 559 {
33fef721
JH		 560 int i;
561 int nnops = (count + 3) / 4;
562 int len = count / nnops;
563 int remains = count - nnops * len;
564 int pos = 0;
565
566 for (i = 0; i < remains; i++)
252b5132 567 {
33fef721
JH		 568 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
569 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
570 pos += len + 1;
571 }
572 for (; i < nnops; i++)
573 {
574 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
575 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
576 pos += len;
252b5132 577 }
252b5132 578 }
33fef721
JH		 579 else
580 if (flag_code == CODE_16BIT)
581 {
582 memcpy (fragP->fr_literal + fragP->fr_fix,
583 f16_patt[count - 1], count);
584 if (count > 8)
585 /* Adjust jump offset. */
586 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
587 }
588 else
589 memcpy (fragP->fr_literal + fragP->fr_fix,
590 f32_patt[count - 1], count);
591 fragP->fr_var = count;
252b5132
RH		 592}
593
252b5132
RH		 594static INLINE unsigned int
595mode_from_disp_size (t)
596 unsigned int t;
597{
3e73aa7c 598 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 599}
600
601static INLINE int
602fits_in_signed_byte (num)
847f7ad4 603 offsetT num;
252b5132
RH		 604{
605 return (num >= -128) && (num <= 127);
47926f60 606}
252b5132
RH		 607
608static INLINE int
609fits_in_unsigned_byte (num)
847f7ad4 610 offsetT num;
252b5132
RH		 611{
612 return (num & 0xff) == num;
47926f60 613}
252b5132
RH		 614
615static INLINE int
616fits_in_unsigned_word (num)
847f7ad4 617 offsetT num;
252b5132
RH		 618{
619 return (num & 0xffff) == num;
47926f60 620}
252b5132
RH		 621
622static INLINE int
623fits_in_signed_word (num)
847f7ad4 624 offsetT num;
252b5132
RH		 625{
626 return (-32768 <= num) && (num <= 32767);
47926f60 627}
3e73aa7c
JH		 628static INLINE int
629fits_in_signed_long (num)
630 offsetT num ATTRIBUTE_UNUSED;
631{
632#ifndef BFD64
633 return 1;
634#else
635 return (!(((offsetT) -1 << 31) & num)
636 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
637#endif
638} /* fits_in_signed_long() */
639static INLINE int
640fits_in_unsigned_long (num)
641 offsetT num ATTRIBUTE_UNUSED;
642{
643#ifndef BFD64
644 return 1;
645#else
646 return (num & (((offsetT) 2 << 31) - 1)) == num;
647#endif
648} /* fits_in_unsigned_long() */
252b5132
RH		 649
650static int
651smallest_imm_type (num)
847f7ad4 652 offsetT num;
252b5132 653{
a847613f 654 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 655 {
656 /* This code is disabled on the 486 because all the Imm1 forms
657 in the opcode table are slower on the i486. They're the
658 versions with the implicitly specified single-position
659 displacement, which has another syntax if you really want to
660 use that form. */
661 if (num == 1)
3e73aa7c 662 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 663 }
252b5132 664 return (fits_in_signed_byte (num)
3e73aa7c 665 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 666 : fits_in_unsigned_byte (num)
3e73aa7c 667 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 668 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 669 ? (Imm16 | Imm32 | Imm32S | Imm64)
670 : fits_in_signed_long (num)
671 ? (Imm32 | Imm32S | Imm64)
672 : fits_in_unsigned_long (num)
673 ? (Imm32 | Imm64)
674 : Imm64);
47926f60 675}
252b5132 676
847f7ad4
AM		 677static offsetT
678offset_in_range (val, size)
679 offsetT val;
680 int size;
681{
508866be 682 addressT mask;
ba2adb93 683
847f7ad4
AM		 684 switch (size)
685 {
508866be
L		 686 case 1: mask = ((addressT) 1 << 8) - 1; break;
687 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 688 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 689#ifdef BFD64
690 case 8: mask = ((addressT) 2 << 63) - 1; break;
691#endif
47926f60 692 default: abort ();
847f7ad4
AM		 693 }
694
ba2adb93 695 /* If BFD64, sign extend val. */
3e73aa7c
JH		 696 if (!use_rela_relocations)
697 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
698 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 699
47926f60 700 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 701 {
702 char buf1[40], buf2[40];
703
704 sprint_value (buf1, val);
705 sprint_value (buf2, val & mask);
706 as_warn (_("%s shortened to %s"), buf1, buf2);
707 }
708 return val & mask;
709}
710
252b5132
RH		 711/* Returns 0 if attempting to add a prefix where one from the same
712 class already exists, 1 if non rep/repne added, 2 if rep/repne
713 added. */
714static int
715add_prefix (prefix)
716 unsigned int prefix;
717{
718 int ret = 1;
719 int q;
720
29b0f896
AM		 721 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
722 && flag_code == CODE_64BIT)
3e73aa7c
JH		 723 q = REX_PREFIX;
724 else
725 switch (prefix)
726 {
727 default:
728 abort ();
729
730 case CS_PREFIX_OPCODE:
731 case DS_PREFIX_OPCODE:
732 case ES_PREFIX_OPCODE:
733 case FS_PREFIX_OPCODE:
734 case GS_PREFIX_OPCODE:
735 case SS_PREFIX_OPCODE:
736 q = SEG_PREFIX;
737 break;
252b5132 738
3e73aa7c
JH		 739 case REPNE_PREFIX_OPCODE:
740 case REPE_PREFIX_OPCODE:
741 ret = 2;
742 /* fall thru */
743 case LOCK_PREFIX_OPCODE:
744 q = LOCKREP_PREFIX;
745 break;
252b5132 746
3e73aa7c
JH		 747 case FWAIT_OPCODE:
748 q = WAIT_PREFIX;
749 break;
252b5132 750
3e73aa7c
JH		 751 case ADDR_PREFIX_OPCODE:
752 q = ADDR_PREFIX;
753 break;
252b5132 754
3e73aa7c
JH		 755 case DATA_PREFIX_OPCODE:
756 q = DATA_PREFIX;
757 break;
758 }
252b5132 759
29b0f896 760 if (i.prefix[q] != 0)
252b5132
RH		 761 {
762 as_bad (_("same type of prefix used twice"));
763 return 0;
764 }
765
766 i.prefixes += 1;
767 i.prefix[q] = prefix;
768 return ret;
769}
770
771static void
3e73aa7c 772set_code_flag (value)
e5cb08ac 773 int value;
eecb386c 774{
3e73aa7c
JH		 775 flag_code = value;
776 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
777 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
778 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
779 {
780 as_bad (_("64bit mode not supported on this CPU."));
781 }
782 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
783 {
784 as_bad (_("32bit mode not supported on this CPU."));
785 }
eecb386c
AM		 786 stackop_size = '\0';
787}
788
789static void
3e73aa7c
JH		 790set_16bit_gcc_code_flag (new_code_flag)
791 int new_code_flag;
252b5132 792{
3e73aa7c
JH		 793 flag_code = new_code_flag;
794 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
795 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 796 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 797}
798
799static void
800set_intel_syntax (syntax_flag)
eecb386c 801 int syntax_flag;
252b5132
RH		 802{
803 /* Find out if register prefixing is specified. */
804 int ask_naked_reg = 0;
805
806 SKIP_WHITESPACE ();
29b0f896 807 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 808 {
809 char *string = input_line_pointer;
810 int e = get_symbol_end ();
811
47926f60 812 if (strcmp (string, "prefix") == 0)
252b5132 813 ask_naked_reg = 1;
47926f60 814 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 815 ask_naked_reg = -1;
816 else
d0b47220 817 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 818 *input_line_pointer = e;
819 }
820 demand_empty_rest_of_line ();
c3332e24 821
252b5132
RH		 822 intel_syntax = syntax_flag;
823
824 if (ask_naked_reg == 0)
f86103b7
AM		 825 allow_naked_reg = (intel_syntax
826 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 827 else
828 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 829
830 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
831 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 832}
833
e413e4e9
AM		 834static void
835set_cpu_arch (dummy)
47926f60 836 int dummy ATTRIBUTE_UNUSED;
e413e4e9 837{
47926f60 838 SKIP_WHITESPACE ();
e413e4e9 839
29b0f896 840 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 841 {
842 char *string = input_line_pointer;
843 int e = get_symbol_end ();
844 int i;
845
846 for (i = 0; cpu_arch[i].name; i++)
847 {
848 if (strcmp (string, cpu_arch[i].name) == 0)
849 {
5c6af06e
JB		 850 if (*string != '.')
851 {
852 cpu_arch_name = cpu_arch[i].name;
853 cpu_sub_arch_name = NULL;
854 cpu_arch_flags = (cpu_arch[i].flags
855 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
856 break;
857 }
858 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
859 {
860 cpu_sub_arch_name = cpu_arch[i].name;
861 cpu_arch_flags |= cpu_arch[i].flags;
862 }
863 *input_line_pointer = e;
864 demand_empty_rest_of_line ();
865 return;
e413e4e9
AM		 866 }
867 }
868 if (!cpu_arch[i].name)
869 as_bad (_("no such architecture: `%s'"), string);
870
871 *input_line_pointer = e;
872 }
873 else
874 as_bad (_("missing cpu architecture"));
875
fddf5b5b
AM		 876 no_cond_jump_promotion = 0;
877 if (*input_line_pointer == ','
29b0f896 878 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 879 {
880 char *string = ++input_line_pointer;
881 int e = get_symbol_end ();
882
883 if (strcmp (string, "nojumps") == 0)
884 no_cond_jump_promotion = 1;
885 else if (strcmp (string, "jumps") == 0)
886 ;
887 else
888 as_bad (_("no such architecture modifier: `%s'"), string);
889
890 *input_line_pointer = e;
891 }
892
e413e4e9
AM		 893 demand_empty_rest_of_line ();
894}
895
b9d79e03
JH		 896unsigned long
897i386_mach ()
898{
899 if (!strcmp (default_arch, "x86_64"))
900 return bfd_mach_x86_64;
901 else if (!strcmp (default_arch, "i386"))
902 return bfd_mach_i386_i386;
903 else
904 as_fatal (_("Unknown architecture"));
905}
b9d79e03 906\f
252b5132
RH		 907void
908md_begin ()
909{
910 const char *hash_err;
911
47926f60 912 /* Initialize op_hash hash table. */
252b5132
RH		 913 op_hash = hash_new ();
914
915 {
29b0f896
AM		 916 const template *optab;
917 templates *core_optab;
252b5132 918
47926f60
KH		 919 /* Setup for loop. */
920 optab = i386_optab;
252b5132
RH		 921 core_optab = (templates *) xmalloc (sizeof (templates));
922 core_optab->start = optab;
923
924 while (1)
925 {
926 ++optab;
927 if (optab->name == NULL
928 || strcmp (optab->name, (optab - 1)->name) != 0)
929 {
930 /* different name --> ship out current template list;
47926f60 931 add to hash table; & begin anew. */
252b5132
RH		 932 core_optab->end = optab;
933 hash_err = hash_insert (op_hash,
934 (optab - 1)->name,
935 (PTR) core_optab);
936 if (hash_err)
937 {
252b5132
RH		 938 as_fatal (_("Internal Error: Can't hash %s: %s"),
939 (optab - 1)->name,
940 hash_err);
941 }
942 if (optab->name == NULL)
943 break;
944 core_optab = (templates *) xmalloc (sizeof (templates));
945 core_optab->start = optab;
946 }
947 }
948 }
949
47926f60 950 /* Initialize reg_hash hash table. */
252b5132
RH		 951 reg_hash = hash_new ();
952 {
29b0f896 953 const reg_entry *regtab;
252b5132
RH		 954
955 for (regtab = i386_regtab;
956 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
957 regtab++)
958 {
959 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
960 if (hash_err)
3e73aa7c
JH		 961 as_fatal (_("Internal Error: Can't hash %s: %s"),
962 regtab->reg_name,
963 hash_err);
252b5132
RH		 964 }
965 }
966
47926f60 967 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 968 {
29b0f896
AM		 969 int c;
970 char *p;
252b5132
RH		 971
972 for (c = 0; c < 256; c++)
973 {
3882b010 974 if (ISDIGIT (c))
252b5132
RH		 975 {
976 digit_chars[c] = c;
977 mnemonic_chars[c] = c;
978 register_chars[c] = c;
979 operand_chars[c] = c;
980 }
3882b010 981 else if (ISLOWER (c))
252b5132
RH		 982 {
983 mnemonic_chars[c] = c;
984 register_chars[c] = c;
985 operand_chars[c] = c;
986 }
3882b010 987 else if (ISUPPER (c))
252b5132 988 {
3882b010 989 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 990 register_chars[c] = mnemonic_chars[c];
991 operand_chars[c] = c;
992 }
993
3882b010 994 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 995 identifier_chars[c] = c;
996 else if (c >= 128)
997 {
998 identifier_chars[c] = c;
999 operand_chars[c] = c;
1000 }
1001 }
1002
1003#ifdef LEX_AT
1004 identifier_chars['@'] = '@';
32137342
NC		 1005#endif
1006#ifdef LEX_QM
1007 identifier_chars['?'] = '?';
1008 operand_chars['?'] = '?';
252b5132 1009#endif
252b5132 1010 digit_chars['-'] = '-';
791fe849 1011 mnemonic_chars['-'] = '-';
252b5132
RH		 1012 identifier_chars['_'] = '_';
1013 identifier_chars['.'] = '.';
1014
1015 for (p = operand_special_chars; *p != '\0'; p++)
1016 operand_chars[(unsigned char) *p] = *p;
1017 }
1018
1019#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1020 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1021 {
1022 record_alignment (text_section, 2);
1023 record_alignment (data_section, 2);
1024 record_alignment (bss_section, 2);
1025 }
1026#endif
a4447b93
RH		 1027
1028 if (flag_code == CODE_64BIT)
1029 {
1030 x86_dwarf2_return_column = 16;
1031 x86_cie_data_alignment = -8;
1032 }
1033 else
1034 {
1035 x86_dwarf2_return_column = 8;
1036 x86_cie_data_alignment = -4;
1037 }
252b5132
RH		 1038}
1039
1040void
1041i386_print_statistics (file)
1042 FILE *file;
1043{
1044 hash_print_statistics (file, "i386 opcode", op_hash);
1045 hash_print_statistics (file, "i386 register", reg_hash);
1046}
1047\f
252b5132
RH		 1048#ifdef DEBUG386
1049
ce8a8b2f 1050/* Debugging routines for md_assemble. */
252b5132
RH		 1051static void pi PARAMS ((char *, i386_insn *));
1052static void pte PARAMS ((template *));
1053static void pt PARAMS ((unsigned int));
1054static void pe PARAMS ((expressionS *));
1055static void ps PARAMS ((symbolS *));
1056
1057static void
1058pi (line, x)
1059 char *line;
1060 i386_insn *x;
1061{
09f131f2 1062 unsigned int i;
252b5132
RH		 1063
1064 fprintf (stdout, "%s: template ", line);
1065 pte (&x->tm);
09f131f2
JH		 1066 fprintf (stdout, " address: base %s index %s scale %x\n",
1067 x->base_reg ? x->base_reg->reg_name : "none",
1068 x->index_reg ? x->index_reg->reg_name : "none",
1069 x->log2_scale_factor);
1070 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1071 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1072 fprintf (stdout, " sib: base %x index %x scale %x\n",
1073 x->sib.base, x->sib.index, x->sib.scale);
1074 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1075 (x->rex & REX_MODE64) != 0,
1076 (x->rex & REX_EXTX) != 0,
1077 (x->rex & REX_EXTY) != 0,
1078 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1079 for (i = 0; i < x->operands; i++)
1080 {
1081 fprintf (stdout, " #%d: ", i + 1);
1082 pt (x->types[i]);
1083 fprintf (stdout, "\n");
1084 if (x->types[i]
3f4438ab 1085 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1086 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1087 if (x->types[i] & Imm)
520dc8e8 1088 pe (x->op[i].imms);
252b5132 1089 if (x->types[i] & Disp)
520dc8e8 1090 pe (x->op[i].disps);
252b5132
RH		 1091 }
1092}
1093
1094static void
1095pte (t)
1096 template *t;
1097{
09f131f2 1098 unsigned int i;
252b5132 1099 fprintf (stdout, " %d operands ", t->operands);
47926f60 1100 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1101 if (t->extension_opcode != None)
1102 fprintf (stdout, "ext %x ", t->extension_opcode);
1103 if (t->opcode_modifier & D)
1104 fprintf (stdout, "D");
1105 if (t->opcode_modifier & W)
1106 fprintf (stdout, "W");
1107 fprintf (stdout, "\n");
1108 for (i = 0; i < t->operands; i++)
1109 {
1110 fprintf (stdout, " #%d type ", i + 1);
1111 pt (t->operand_types[i]);
1112 fprintf (stdout, "\n");
1113 }
1114}
1115
1116static void
1117pe (e)
1118 expressionS *e;
1119{
24eab124 1120 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1121 fprintf (stdout, " add_number %ld (%lx)\n",
1122 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1123 if (e->X_add_symbol)
1124 {
1125 fprintf (stdout, " add_symbol ");
1126 ps (e->X_add_symbol);
1127 fprintf (stdout, "\n");
1128 }
1129 if (e->X_op_symbol)
1130 {
1131 fprintf (stdout, " op_symbol ");
1132 ps (e->X_op_symbol);
1133 fprintf (stdout, "\n");
1134 }
1135}
1136
1137static void
1138ps (s)
1139 symbolS *s;
1140{
1141 fprintf (stdout, "%s type %s%s",
1142 S_GET_NAME (s),
1143 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1144 segment_name (S_GET_SEGMENT (s)));
1145}
1146
1147struct type_name
1148 {
1149 unsigned int mask;
1150 char *tname;
1151 }
1152
29b0f896 1153static const type_names[] =
252b5132
RH		 1154{
1155 { Reg8, "r8" },
1156 { Reg16, "r16" },
1157 { Reg32, "r32" },
09f131f2 1158 { Reg64, "r64" },
252b5132
RH		 1159 { Imm8, "i8" },
1160 { Imm8S, "i8s" },
1161 { Imm16, "i16" },
1162 { Imm32, "i32" },
09f131f2
JH		 1163 { Imm32S, "i32s" },
1164 { Imm64, "i64" },
252b5132
RH		 1165 { Imm1, "i1" },
1166 { BaseIndex, "BaseIndex" },
1167 { Disp8, "d8" },
1168 { Disp16, "d16" },
1169 { Disp32, "d32" },
09f131f2
JH		 1170 { Disp32S, "d32s" },
1171 { Disp64, "d64" },
252b5132
RH		 1172 { InOutPortReg, "InOutPortReg" },
1173 { ShiftCount, "ShiftCount" },
1174 { Control, "control reg" },
1175 { Test, "test reg" },
1176 { Debug, "debug reg" },
1177 { FloatReg, "FReg" },
1178 { FloatAcc, "FAcc" },
1179 { SReg2, "SReg2" },
1180 { SReg3, "SReg3" },
1181 { Acc, "Acc" },
1182 { JumpAbsolute, "Jump Absolute" },
1183 { RegMMX, "rMMX" },
3f4438ab 1184 { RegXMM, "rXMM" },
252b5132
RH		 1185 { EsSeg, "es" },
1186 { 0, "" }
1187};
1188
1189static void
1190pt (t)
1191 unsigned int t;
1192{
29b0f896 1193 const struct type_name *ty;
252b5132 1194
09f131f2
JH		 1195 for (ty = type_names; ty->mask; ty++)
1196 if (t & ty->mask)
1197 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1198 fflush (stdout);
1199}
1200
1201#endif /* DEBUG386 */
1202\f
29b0f896
AM		 1203static bfd_reloc_code_real_type reloc
1204 PARAMS ((int, int, int, bfd_reloc_code_real_type));
252b5132
RH		 1205
1206static bfd_reloc_code_real_type
3e73aa7c 1207reloc (size, pcrel, sign, other)
252b5132
RH		 1208 int size;
1209 int pcrel;
3e73aa7c 1210 int sign;
252b5132
RH		 1211 bfd_reloc_code_real_type other;
1212{
47926f60
KH		 1213 if (other != NO_RELOC)
1214 return other;
252b5132
RH		 1215
1216 if (pcrel)
1217 {
3e73aa7c 1218 if (!sign)
e5cb08ac 1219 as_bad (_("There are no unsigned pc-relative relocations"));
252b5132
RH		 1220 switch (size)
1221 {
1222 case 1: return BFD_RELOC_8_PCREL;
1223 case 2: return BFD_RELOC_16_PCREL;
1224 case 4: return BFD_RELOC_32_PCREL;
1225 }
d0b47220 1226 as_bad (_("can not do %d byte pc-relative relocation"), size);
252b5132
RH		 1227 }
1228 else
1229 {
3e73aa7c 1230 if (sign)
e5cb08ac 1231 switch (size)
3e73aa7c
JH		 1232 {
1233 case 4: return BFD_RELOC_X86_64_32S;
1234 }
1235 else
1236 switch (size)
1237 {
1238 case 1: return BFD_RELOC_8;
1239 case 2: return BFD_RELOC_16;
1240 case 4: return BFD_RELOC_32;
1241 case 8: return BFD_RELOC_64;
1242 }
1243 as_bad (_("can not do %s %d byte relocation"),
1244 sign ? "signed" : "unsigned", size);
252b5132
RH		 1245 }
1246
bfb32b52 1247 abort ();
252b5132
RH		 1248 return BFD_RELOC_NONE;
1249}
1250
47926f60
KH		 1251/* Here we decide which fixups can be adjusted to make them relative to
1252 the beginning of the section instead of the symbol. Basically we need
1253 to make sure that the dynamic relocations are done correctly, so in
1254 some cases we force the original symbol to be used. */
1255
252b5132 1256int
c0c949c7 1257tc_i386_fix_adjustable (fixP)
31312f95 1258 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1259{
6d249963 1260#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 1261 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
1262 return 1;
1263
a161fe53
AM		 1264 /* Don't adjust pc-relative references to merge sections in 64-bit
1265 mode. */
1266 if (use_rela_relocations
1267 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1268 && fixP->fx_pcrel)
252b5132 1269 return 0;
31312f95 1270
8d01d9a9
AJ		 1271 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1272 and changed later by validate_fix. */
1273 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1274 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1275 return 0;
1276
ce8a8b2f 1277 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1278 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1279 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1280 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1281 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1282 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1283 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1284 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1285 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1286 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1287 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1288 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1289 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1290 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1291 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1292 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1293 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1294 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1295 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1296 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
252b5132
RH		 1297 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1298 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1299 return 0;
31312f95 1300#endif
252b5132
RH		 1301 return 1;
1302}
252b5132 1303
29b0f896 1304static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1305
1306static int
252b5132 1307intel_float_operand (mnemonic)
29b0f896 1308 const char *mnemonic;
252b5132 1309{
9306ca4a
JB		 1310 /* Note that the value returned is meaningful only for opcodes with (memory)
1311 operands, hence the code here is free to improperly handle opcodes that
1312 have no operands (for better performance and smaller code). */
1313
1314 if (mnemonic[0] != 'f')
1315 return 0; /* non-math */
1316
1317 switch (mnemonic[1])
1318 {
1319 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1320 the fs segment override prefix not currently handled because no
1321 call path can make opcodes without operands get here */
1322 case 'i':
1323 return 2 /* integer op */;
1324 case 'l':
1325 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1326 return 3; /* fldcw/fldenv */
1327 break;
1328 case 'n':
1329 if (mnemonic[2] != 'o' /* fnop */)
1330 return 3; /* non-waiting control op */
1331 break;
1332 case 'r':
1333 if (mnemonic[2] == 's')
1334 return 3; /* frstor/frstpm */
1335 break;
1336 case 's':
1337 if (mnemonic[2] == 'a')
1338 return 3; /* fsave */
1339 if (mnemonic[2] == 't')
1340 {
1341 switch (mnemonic[3])
1342 {
1343 case 'c': /* fstcw */
1344 case 'd': /* fstdw */
1345 case 'e': /* fstenv */
1346 case 's': /* fsts[gw] */
1347 return 3;
1348 }
1349 }
1350 break;
1351 case 'x':
1352 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1353 return 0; /* fxsave/fxrstor are not really math ops */
1354 break;
1355 }
252b5132 1356
9306ca4a 1357 return 1;
252b5132
RH		 1358}
1359
1360/* This is the guts of the machine-dependent assembler. LINE points to a
1361 machine dependent instruction. This function is supposed to emit
1362 the frags/bytes it assembles to. */
1363
1364void
1365md_assemble (line)
1366 char *line;
1367{
252b5132 1368 int j;
252b5132
RH		 1369 char mnemonic[MAX_MNEM_SIZE];
1370
47926f60 1371 /* Initialize globals. */
252b5132
RH		 1372 memset (&i, '\0', sizeof (i));
1373 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1374 i.reloc[j] = NO_RELOC;
252b5132
RH		 1375 memset (disp_expressions, '\0', sizeof (disp_expressions));
1376 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1377 save_stack_p = save_stack;
252b5132
RH		 1378
1379 /* First parse an instruction mnemonic & call i386_operand for the operands.
1380 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1381 start of a (possibly prefixed) mnemonic. */
252b5132 1382
29b0f896
AM		 1383 line = parse_insn (line, mnemonic);
1384 if (line == NULL)
1385 return;
252b5132 1386
29b0f896
AM		 1387 line = parse_operands (line, mnemonic);
1388 if (line == NULL)
1389 return;
252b5132 1390
29b0f896
AM		 1391 /* Now we've parsed the mnemonic into a set of templates, and have the
1392 operands at hand. */
1393
1394 /* All intel opcodes have reversed operands except for "bound" and
1395 "enter". We also don't reverse intersegment "jmp" and "call"
1396 instructions with 2 immediate operands so that the immediate segment
1397 precedes the offset, as it does when in AT&T mode. "enter" and the
1398 intersegment "jmp" and "call" instructions are the only ones that
1399 have two immediate operands. */
1400 if (intel_syntax && i.operands > 1
1401 && (strcmp (mnemonic, "bound") != 0)
1402 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1403 swap_operands ();
1404
1405 if (i.imm_operands)
1406 optimize_imm ();
1407
1408 if (i.disp_operands)
1409 optimize_disp ();
1410
1411 /* Next, we find a template that matches the given insn,
1412 making sure the overlap of the given operands types is consistent
1413 with the template operand types. */
252b5132 1414
29b0f896
AM		 1415 if (!match_template ())
1416 return;
252b5132 1417
cd61ebfe
AM		 1418 if (intel_syntax)
1419 {
1420 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1421 if (SYSV386_COMPAT
1422 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1423 i.tm.base_opcode ^= FloatR;
1424
1425 /* Zap movzx and movsx suffix. The suffix may have been set from
1426 "word ptr" or "byte ptr" on the source operand, but we'll use
1427 the suffix later to choose the destination register. */
1428 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1429 {
1430 if (i.reg_operands < 2
1431 && !i.suffix
1432 && (~i.tm.opcode_modifier
1433 & (No_bSuf
1434 | No_wSuf
1435 | No_lSuf
1436 | No_sSuf
1437 | No_xSuf
1438 | No_qSuf)))
1439 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1440
1441 i.suffix = 0;
1442 }
cd61ebfe 1443 }
24eab124 1444
29b0f896
AM		 1445 if (i.tm.opcode_modifier & FWait)
1446 if (!add_prefix (FWAIT_OPCODE))
1447 return;
252b5132 1448
29b0f896
AM		 1449 /* Check string instruction segment overrides. */
1450 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1451 {
1452 if (!check_string ())
5dd0794d 1453 return;
29b0f896 1454 }
5dd0794d 1455
29b0f896
AM		 1456 if (!process_suffix ())
1457 return;
e413e4e9 1458
29b0f896
AM		 1459 /* Make still unresolved immediate matches conform to size of immediate
1460 given in i.suffix. */
1461 if (!finalize_imm ())
1462 return;
252b5132 1463
29b0f896
AM		 1464 if (i.types[0] & Imm1)
1465 i.imm_operands = 0; /* kludge for shift insns. */
1466 if (i.types[0] & ImplicitRegister)
1467 i.reg_operands--;
1468 if (i.types[1] & ImplicitRegister)
1469 i.reg_operands--;
1470 if (i.types[2] & ImplicitRegister)
1471 i.reg_operands--;
252b5132 1472
29b0f896
AM		 1473 if (i.tm.opcode_modifier & ImmExt)
1474 {
02fc3089
L		 1475 expressionS *exp;
1476
ca164297
L		 1477 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1478 {
67c1ffbe 1479 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1480 operands with an opcode suffix which is coded in the same
1481 place as an 8-bit immediate field would be. Here we check
1482 those operands and remove them afterwards. */
1483 unsigned int x;
1484
a4622f40 1485 for (x = 0; x < i.operands; x++)
ca164297
L		 1486 if (i.op[x].regs->reg_num != x)
1487 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1488 i.op[x].regs->reg_name, x + 1, i.tm.name);
1489 i.operands = 0;
1490 }
1491
29b0f896
AM		 1492 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1493 opcode suffix which is coded in the same place as an 8-bit
1494 immediate field would be. Here we fake an 8-bit immediate
1495 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1496
29b0f896 1497 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1498
29b0f896
AM		 1499 exp = &im_expressions[i.imm_operands++];
1500 i.op[i.operands].imms = exp;
1501 i.types[i.operands++] = Imm8;
1502 exp->X_op = O_constant;
1503 exp->X_add_number = i.tm.extension_opcode;
1504 i.tm.extension_opcode = None;
1505 }
252b5132 1506
29b0f896
AM		 1507 /* For insns with operands there are more diddles to do to the opcode. */
1508 if (i.operands)
1509 {
1510 if (!process_operands ())
1511 return;
1512 }
1513 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1514 {
1515 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1516 as_warn (_("translating to `%sp'"), i.tm.name);
1517 }
252b5132 1518
29b0f896
AM		 1519 /* Handle conversion of 'int $3' --> special int3 insn. */
1520 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1521 {
1522 i.tm.base_opcode = INT3_OPCODE;
1523 i.imm_operands = 0;
1524 }
252b5132 1525
29b0f896
AM		 1526 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1527 && i.op[0].disps->X_op == O_constant)
1528 {
1529 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1530 the absolute address given by the constant. Since ix86 jumps and
1531 calls are pc relative, we need to generate a reloc. */
1532 i.op[0].disps->X_add_symbol = &abs_symbol;
1533 i.op[0].disps->X_op = O_symbol;
1534 }
252b5132 1535
29b0f896
AM		 1536 if ((i.tm.opcode_modifier & Rex64) != 0)
1537 i.rex |= REX_MODE64;
252b5132 1538
29b0f896
AM		 1539 /* For 8 bit registers we need an empty rex prefix. Also if the
1540 instruction already has a prefix, we need to convert old
1541 registers to new ones. */
773f551c 1542
29b0f896
AM		 1543 if (((i.types[0] & Reg8) != 0
1544 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1545 || ((i.types[1] & Reg8) != 0
1546 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1547 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1548 && i.rex != 0))
1549 {
1550 int x;
726c5dcd 1551
29b0f896
AM		 1552 i.rex |= REX_OPCODE;
1553 for (x = 0; x < 2; x++)
1554 {
1555 /* Look for 8 bit operand that uses old registers. */
1556 if ((i.types[x] & Reg8) != 0
1557 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1558 {
29b0f896
AM		 1559 /* In case it is "hi" register, give up. */
1560 if (i.op[x].regs->reg_num > 3)
0477af35 1561 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1562 i.op[x].regs->reg_name);
773f551c 1563
29b0f896
AM		 1564 /* Otherwise it is equivalent to the extended register.
1565 Since the encoding doesn't change this is merely
1566 cosmetic cleanup for debug output. */
1567
1568 i.op[x].regs = i.op[x].regs + 8;
773f551c 1569 }
29b0f896
AM		 1570 }
1571 }
773f551c 1572
29b0f896
AM		 1573 if (i.rex != 0)
1574 add_prefix (REX_OPCODE | i.rex);
1575
1576 /* We are ready to output the insn. */
1577 output_insn ();
1578}
1579
1580static char *
1581parse_insn (line, mnemonic)
1582 char *line;
1583 char *mnemonic;
1584{
1585 char *l = line;
1586 char *token_start = l;
1587 char *mnem_p;
5c6af06e
JB		 1588 int supported;
1589 const template *t;
29b0f896
AM		 1590
1591 /* Non-zero if we found a prefix only acceptable with string insns. */
1592 const char *expecting_string_instruction = NULL;
45288df1 1593
29b0f896
AM		 1594 while (1)
1595 {
1596 mnem_p = mnemonic;
1597 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1598 {
1599 mnem_p++;
1600 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1601 {
29b0f896
AM		 1602 as_bad (_("no such instruction: `%s'"), token_start);
1603 return NULL;
1604 }
1605 l++;
1606 }
1607 if (!is_space_char (*l)
1608 && *l != END_OF_INSN
1609 && *l != PREFIX_SEPARATOR
1610 && *l != ',')
1611 {
1612 as_bad (_("invalid character %s in mnemonic"),
1613 output_invalid (*l));
1614 return NULL;
1615 }
1616 if (token_start == l)
1617 {
1618 if (*l == PREFIX_SEPARATOR)
1619 as_bad (_("expecting prefix; got nothing"));
1620 else
1621 as_bad (_("expecting mnemonic; got nothing"));
1622 return NULL;
1623 }
45288df1 1624
29b0f896
AM		 1625 /* Look up instruction (or prefix) via hash table. */
1626 current_templates = hash_find (op_hash, mnemonic);
47926f60 1627
29b0f896
AM		 1628 if (*l != END_OF_INSN
1629 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1630 && current_templates
1631 && (current_templates->start->opcode_modifier & IsPrefix))
1632 {
1633 /* If we are in 16-bit mode, do not allow addr16 or data16.
1634 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1635 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1636 && flag_code != CODE_64BIT
1637 && (((current_templates->start->opcode_modifier & Size32) != 0)
1638 ^ (flag_code == CODE_16BIT)))
1639 {
1640 as_bad (_("redundant %s prefix"),
1641 current_templates->start->name);
1642 return NULL;
45288df1 1643 }
29b0f896
AM		 1644 /* Add prefix, checking for repeated prefixes. */
1645 switch (add_prefix (current_templates->start->base_opcode))
1646 {
1647 case 0:
1648 return NULL;
1649 case 2:
1650 expecting_string_instruction = current_templates->start->name;
1651 break;
1652 }
1653 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1654 token_start = ++l;
1655 }
1656 else
1657 break;
1658 }
45288df1 1659
29b0f896
AM		 1660 if (!current_templates)
1661 {
1662 /* See if we can get a match by trimming off a suffix. */
1663 switch (mnem_p[-1])
1664 {
1665 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 1666 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1667 i.suffix = SHORT_MNEM_SUFFIX;
1668 else
29b0f896
AM		 1669 case BYTE_MNEM_SUFFIX:
1670 case QWORD_MNEM_SUFFIX:
1671 i.suffix = mnem_p[-1];
1672 mnem_p[-1] = '\0';
1673 current_templates = hash_find (op_hash, mnemonic);
1674 break;
1675 case SHORT_MNEM_SUFFIX:
1676 case LONG_MNEM_SUFFIX:
1677 if (!intel_syntax)
1678 {
1679 i.suffix = mnem_p[-1];
1680 mnem_p[-1] = '\0';
1681 current_templates = hash_find (op_hash, mnemonic);
1682 }
1683 break;
252b5132 1684
29b0f896
AM		 1685 /* Intel Syntax. */
1686 case 'd':
1687 if (intel_syntax)
1688 {
9306ca4a 1689 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 1690 i.suffix = SHORT_MNEM_SUFFIX;
1691 else
1692 i.suffix = LONG_MNEM_SUFFIX;
1693 mnem_p[-1] = '\0';
1694 current_templates = hash_find (op_hash, mnemonic);
1695 }
1696 break;
1697 }
1698 if (!current_templates)
1699 {
1700 as_bad (_("no such instruction: `%s'"), token_start);
1701 return NULL;
1702 }
1703 }
252b5132 1704
29b0f896
AM		 1705 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1706 {
1707 /* Check for a branch hint. We allow ",pt" and ",pn" for
1708 predict taken and predict not taken respectively.
1709 I'm not sure that branch hints actually do anything on loop
1710 and jcxz insns (JumpByte) for current Pentium4 chips. They
1711 may work in the future and it doesn't hurt to accept them
1712 now. */
1713 if (l[0] == ',' && l[1] == 'p')
1714 {
1715 if (l[2] == 't')
1716 {
1717 if (!add_prefix (DS_PREFIX_OPCODE))
1718 return NULL;
1719 l += 3;
1720 }
1721 else if (l[2] == 'n')
1722 {
1723 if (!add_prefix (CS_PREFIX_OPCODE))
1724 return NULL;
1725 l += 3;
1726 }
1727 }
1728 }
1729 /* Any other comma loses. */
1730 if (*l == ',')
1731 {
1732 as_bad (_("invalid character %s in mnemonic"),
1733 output_invalid (*l));
1734 return NULL;
1735 }
252b5132 1736
29b0f896 1737 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 1738 supported = 0;
1739 for (t = current_templates->start; t < current_templates->end; ++t)
1740 {
1741 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1742 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1743 supported |= 1;
1744 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1745 supported |= 2;
1746 }
1747 if (!(supported & 2))
1748 {
1749 as_bad (flag_code == CODE_64BIT
1750 ? _("`%s' is not supported in 64-bit mode")
1751 : _("`%s' is only supported in 64-bit mode"),
1752 current_templates->start->name);
1753 return NULL;
1754 }
1755 if (!(supported & 1))
29b0f896 1756 {
5c6af06e
JB		 1757 as_warn (_("`%s' is not supported on `%s%s'"),
1758 current_templates->start->name,
1759 cpu_arch_name,
1760 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 1761 }
1762 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1763 {
1764 as_warn (_("use .code16 to ensure correct addressing mode"));
1765 }
252b5132 1766
29b0f896
AM		 1767 /* Check for rep/repne without a string instruction. */
1768 if (expecting_string_instruction
1769 && !(current_templates->start->opcode_modifier & IsString))
1770 {
1771 as_bad (_("expecting string instruction after `%s'"),
1772 expecting_string_instruction);
1773 return NULL;
1774 }
252b5132 1775
29b0f896
AM		 1776 return l;
1777}
252b5132 1778
29b0f896
AM		 1779static char *
1780parse_operands (l, mnemonic)
1781 char *l;
1782 const char *mnemonic;
1783{
1784 char *token_start;
3138f287 1785
29b0f896
AM		 1786 /* 1 if operand is pending after ','. */
1787 unsigned int expecting_operand = 0;
252b5132 1788
29b0f896
AM		 1789 /* Non-zero if operand parens not balanced. */
1790 unsigned int paren_not_balanced;
1791
1792 while (*l != END_OF_INSN)
1793 {
1794 /* Skip optional white space before operand. */
1795 if (is_space_char (*l))
1796 ++l;
1797 if (!is_operand_char (*l) && *l != END_OF_INSN)
1798 {
1799 as_bad (_("invalid character %s before operand %d"),
1800 output_invalid (*l),
1801 i.operands + 1);
1802 return NULL;
1803 }
1804 token_start = l; /* after white space */
1805 paren_not_balanced = 0;
1806 while (paren_not_balanced || *l != ',')
1807 {
1808 if (*l == END_OF_INSN)
1809 {
1810 if (paren_not_balanced)
1811 {
1812 if (!intel_syntax)
1813 as_bad (_("unbalanced parenthesis in operand %d."),
1814 i.operands + 1);
1815 else
1816 as_bad (_("unbalanced brackets in operand %d."),
1817 i.operands + 1);
1818 return NULL;
1819 }
1820 else
1821 break; /* we are done */
1822 }
1823 else if (!is_operand_char (*l) && !is_space_char (*l))
1824 {
1825 as_bad (_("invalid character %s in operand %d"),
1826 output_invalid (*l),
1827 i.operands + 1);
1828 return NULL;
1829 }
1830 if (!intel_syntax)
1831 {
1832 if (*l == '(')
1833 ++paren_not_balanced;
1834 if (*l == ')')
1835 --paren_not_balanced;
1836 }
1837 else
1838 {
1839 if (*l == '[')
1840 ++paren_not_balanced;
1841 if (*l == ']')
1842 --paren_not_balanced;
1843 }
1844 l++;
1845 }
1846 if (l != token_start)
1847 { /* Yes, we've read in another operand. */
1848 unsigned int operand_ok;
1849 this_operand = i.operands++;
1850 if (i.operands > MAX_OPERANDS)
1851 {
1852 as_bad (_("spurious operands; (%d operands/instruction max)"),
1853 MAX_OPERANDS);
1854 return NULL;
1855 }
1856 /* Now parse operand adding info to 'i' as we go along. */
1857 END_STRING_AND_SAVE (l);
1858
1859 if (intel_syntax)
1860 operand_ok =
1861 i386_intel_operand (token_start,
1862 intel_float_operand (mnemonic));
1863 else
1864 operand_ok = i386_operand (token_start);
1865
1866 RESTORE_END_STRING (l);
1867 if (!operand_ok)
1868 return NULL;
1869 }
1870 else
1871 {
1872 if (expecting_operand)
1873 {
1874 expecting_operand_after_comma:
1875 as_bad (_("expecting operand after ','; got nothing"));
1876 return NULL;
1877 }
1878 if (*l == ',')
1879 {
1880 as_bad (_("expecting operand before ','; got nothing"));
1881 return NULL;
1882 }
1883 }
7f3f1ea2 1884
29b0f896
AM		 1885 /* Now *l must be either ',' or END_OF_INSN. */
1886 if (*l == ',')
1887 {
1888 if (*++l == END_OF_INSN)
1889 {
1890 /* Just skip it, if it's \n complain. */
1891 goto expecting_operand_after_comma;
1892 }
1893 expecting_operand = 1;
1894 }
1895 }
1896 return l;
1897}
7f3f1ea2 1898
29b0f896
AM		 1899static void
1900swap_operands ()
1901{
1902 union i386_op temp_op;
1903 unsigned int temp_type;
f86103b7 1904 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 1905 int xchg1 = 0;
1906 int xchg2 = 0;
252b5132 1907
29b0f896
AM		 1908 if (i.operands == 2)
1909 {
1910 xchg1 = 0;
1911 xchg2 = 1;
1912 }
1913 else if (i.operands == 3)
1914 {
1915 xchg1 = 0;
1916 xchg2 = 2;
1917 }
1918 temp_type = i.types[xchg2];
1919 i.types[xchg2] = i.types[xchg1];
1920 i.types[xchg1] = temp_type;
1921 temp_op = i.op[xchg2];
1922 i.op[xchg2] = i.op[xchg1];
1923 i.op[xchg1] = temp_op;
1924 temp_reloc = i.reloc[xchg2];
1925 i.reloc[xchg2] = i.reloc[xchg1];
1926 i.reloc[xchg1] = temp_reloc;
1927
1928 if (i.mem_operands == 2)
1929 {
1930 const seg_entry *temp_seg;
1931 temp_seg = i.seg[0];
1932 i.seg[0] = i.seg[1];
1933 i.seg[1] = temp_seg;
1934 }
1935}
252b5132 1936
29b0f896
AM		 1937/* Try to ensure constant immediates are represented in the smallest
1938 opcode possible. */
1939static void
1940optimize_imm ()
1941{
1942 char guess_suffix = 0;
1943 int op;
252b5132 1944
29b0f896
AM		 1945 if (i.suffix)
1946 guess_suffix = i.suffix;
1947 else if (i.reg_operands)
1948 {
1949 /* Figure out a suffix from the last register operand specified.
1950 We can't do this properly yet, ie. excluding InOutPortReg,
1951 but the following works for instructions with immediates.
1952 In any case, we can't set i.suffix yet. */
1953 for (op = i.operands; --op >= 0;)
1954 if (i.types[op] & Reg)
252b5132 1955 {
29b0f896
AM		 1956 if (i.types[op] & Reg8)
1957 guess_suffix = BYTE_MNEM_SUFFIX;
1958 else if (i.types[op] & Reg16)
1959 guess_suffix = WORD_MNEM_SUFFIX;
1960 else if (i.types[op] & Reg32)
1961 guess_suffix = LONG_MNEM_SUFFIX;
1962 else if (i.types[op] & Reg64)
1963 guess_suffix = QWORD_MNEM_SUFFIX;
1964 break;
252b5132 1965 }
29b0f896
AM		 1966 }
1967 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1968 guess_suffix = WORD_MNEM_SUFFIX;
1969
1970 for (op = i.operands; --op >= 0;)
1971 if (i.types[op] & Imm)
1972 {
1973 switch (i.op[op].imms->X_op)
252b5132 1974 {
29b0f896
AM		 1975 case O_constant:
1976 /* If a suffix is given, this operand may be shortened. */
1977 switch (guess_suffix)
252b5132 1978 {
29b0f896
AM		 1979 case LONG_MNEM_SUFFIX:
1980 i.types[op] |= Imm32 | Imm64;
1981 break;
1982 case WORD_MNEM_SUFFIX:
1983 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1984 break;
1985 case BYTE_MNEM_SUFFIX:
1986 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1987 break;
252b5132 1988 }
252b5132 1989
29b0f896
AM		 1990 /* If this operand is at most 16 bits, convert it
1991 to a signed 16 bit number before trying to see
1992 whether it will fit in an even smaller size.
1993 This allows a 16-bit operand such as $0xffe0 to
1994 be recognised as within Imm8S range. */
1995 if ((i.types[op] & Imm16)
1996 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 1997 {
29b0f896
AM		 1998 i.op[op].imms->X_add_number =
1999 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2000 }
2001 if ((i.types[op] & Imm32)
2002 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2003 == 0))
2004 {
2005 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2006 ^ ((offsetT) 1 << 31))
2007 - ((offsetT) 1 << 31));
2008 }
2009 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2010
29b0f896
AM		 2011 /* We must avoid matching of Imm32 templates when 64bit
2012 only immediate is available. */
2013 if (guess_suffix == QWORD_MNEM_SUFFIX)
2014 i.types[op] &= ~Imm32;
2015 break;
252b5132 2016
29b0f896
AM		 2017 case O_absent:
2018 case O_register:
2019 abort ();
2020
2021 /* Symbols and expressions. */
2022 default:
2023 /* Convert symbolic operand to proper sizes for matching. */
2024 switch (guess_suffix)
2025 {
2026 case QWORD_MNEM_SUFFIX:
2027 i.types[op] = Imm64 | Imm32S;
2028 break;
2029 case LONG_MNEM_SUFFIX:
20f0a1fc 2030 i.types[op] = Imm32;
29b0f896
AM		 2031 break;
2032 case WORD_MNEM_SUFFIX:
20f0a1fc 2033 i.types[op] = Imm16;
29b0f896
AM		 2034 break;
2035 case BYTE_MNEM_SUFFIX:
20f0a1fc 2036 i.types[op] = Imm8 | Imm8S;
29b0f896 2037 break;
252b5132 2038 }
29b0f896 2039 break;
252b5132 2040 }
29b0f896
AM		 2041 }
2042}
47926f60 2043
29b0f896
AM		 2044/* Try to use the smallest displacement type too. */
2045static void
2046optimize_disp ()
2047{
2048 int op;
3e73aa7c 2049
29b0f896
AM		 2050 for (op = i.operands; --op >= 0;)
2051 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
252b5132 2052 {
29b0f896
AM		 2053 offsetT disp = i.op[op].disps->X_add_number;
2054
2055 if (i.types[op] & Disp16)
252b5132 2056 {
29b0f896
AM		 2057 /* We know this operand is at most 16 bits, so
2058 convert to a signed 16 bit number before trying
2059 to see whether it will fit in an even smaller
2060 size. */
2061
2062 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
252b5132 2063 }
29b0f896 2064 else if (i.types[op] & Disp32)
252b5132 2065 {
29b0f896
AM		 2066 /* We know this operand is at most 32 bits, so convert to a
2067 signed 32 bit number before trying to see whether it will
2068 fit in an even smaller size. */
2069 disp &= (((offsetT) 2 << 31) - 1);
2070 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 2071 }
29b0f896 2072 if (flag_code == CODE_64BIT)
252b5132 2073 {
29b0f896
AM		 2074 if (fits_in_signed_long (disp))
2075 i.types[op] |= Disp32S;
2076 if (fits_in_unsigned_long (disp))
2077 i.types[op] |= Disp32;
252b5132 2078 }
29b0f896
AM		 2079 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2080 && fits_in_signed_byte (disp))
2081 i.types[op] |= Disp8;
252b5132 2082 }
29b0f896
AM		 2083}
2084
2085static int
2086match_template ()
2087{
2088 /* Points to template once we've found it. */
2089 const template *t;
2090 unsigned int overlap0, overlap1, overlap2;
2091 unsigned int found_reverse_match;
2092 int suffix_check;
2093
2094#define MATCH(overlap, given, template) \
2095 ((overlap & ~JumpAbsolute) \
2096 && (((given) & (BaseIndex | JumpAbsolute)) \
2097 == ((overlap) & (BaseIndex | JumpAbsolute))))
2098
2099 /* If given types r0 and r1 are registers they must be of the same type
2100 unless the expected operand type register overlap is null.
2101 Note that Acc in a template matches every size of reg. */
2102#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2103 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2104 || ((g0) & Reg) == ((g1) & Reg) \
2105 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2106
2107 overlap0 = 0;
2108 overlap1 = 0;
2109 overlap2 = 0;
2110 found_reverse_match = 0;
2111 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2112 ? No_bSuf
2113 : (i.suffix == WORD_MNEM_SUFFIX
2114 ? No_wSuf
2115 : (i.suffix == SHORT_MNEM_SUFFIX
2116 ? No_sSuf
2117 : (i.suffix == LONG_MNEM_SUFFIX
2118 ? No_lSuf
2119 : (i.suffix == QWORD_MNEM_SUFFIX
2120 ? No_qSuf
2121 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2122 ? No_xSuf : 0))))));
2123
20f0a1fc
NC		 2124 t = current_templates->start;
2125 if (i.suffix == QWORD_MNEM_SUFFIX
2126 && flag_code != CODE_64BIT
9306ca4a
JB		 2127 && (intel_syntax
2128 ? !(t->opcode_modifier & IgnoreSize)
2129 && !intel_float_operand (t->name)
2130 : intel_float_operand (t->name) != 2)
20f0a1fc
NC		 2131 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2132 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2133 && (t->base_opcode != 0x0fc7
2134 || t->extension_opcode != 1 /* cmpxchg8b */))
2135 t = current_templates->end;
2136 for (; t < current_templates->end; t++)
29b0f896
AM		 2137 {
2138 /* Must have right number of operands. */
2139 if (i.operands != t->operands)
2140 continue;
2141
2142 /* Check the suffix, except for some instructions in intel mode. */
2143 if ((t->opcode_modifier & suffix_check)
2144 && !(intel_syntax
9306ca4a 2145 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2146 continue;
2147
2148 /* Do not verify operands when there are none. */
2149 else if (!t->operands)
2150 {
2151 if (t->cpu_flags & ~cpu_arch_flags)
2152 continue;
2153 /* We've found a match; break out of loop. */
2154 break;
2155 }
252b5132 2156
29b0f896
AM		 2157 overlap0 = i.types[0] & t->operand_types[0];
2158 switch (t->operands)
2159 {
2160 case 1:
2161 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2162 continue;
2163 break;
2164 case 2:
2165 case 3:
2166 overlap1 = i.types[1] & t->operand_types[1];
2167 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2168 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2169 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2170 t->operand_types[0],
2171 overlap1, i.types[1],
2172 t->operand_types[1]))
2173 {
2174 /* Check if other direction is valid ... */
2175 if ((t->opcode_modifier & (D | FloatD)) == 0)
2176 continue;
2177
2178 /* Try reversing direction of operands. */
2179 overlap0 = i.types[0] & t->operand_types[1];
2180 overlap1 = i.types[1] & t->operand_types[0];
2181 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2182 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2183 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2184 t->operand_types[1],
2185 overlap1, i.types[1],
2186 t->operand_types[0]))
2187 {
2188 /* Does not match either direction. */
2189 continue;
2190 }
2191 /* found_reverse_match holds which of D or FloatDR
2192 we've found. */
2193 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2194 }
2195 /* Found a forward 2 operand match here. */
2196 else if (t->operands == 3)
2197 {
2198 /* Here we make use of the fact that there are no
2199 reverse match 3 operand instructions, and all 3
2200 operand instructions only need to be checked for
2201 register consistency between operands 2 and 3. */
2202 overlap2 = i.types[2] & t->operand_types[2];
2203 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2204 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2205 t->operand_types[1],
2206 overlap2, i.types[2],
2207 t->operand_types[2]))
2208
2209 continue;
2210 }
2211 /* Found either forward/reverse 2 or 3 operand match here:
2212 slip through to break. */
2213 }
2214 if (t->cpu_flags & ~cpu_arch_flags)
2215 {
2216 found_reverse_match = 0;
2217 continue;
2218 }
2219 /* We've found a match; break out of loop. */
2220 break;
2221 }
2222
2223 if (t == current_templates->end)
2224 {
2225 /* We found no match. */
2226 as_bad (_("suffix or operands invalid for `%s'"),
2227 current_templates->start->name);
2228 return 0;
2229 }
252b5132 2230
29b0f896
AM		 2231 if (!quiet_warnings)
2232 {
2233 if (!intel_syntax
2234 && ((i.types[0] & JumpAbsolute)
2235 != (t->operand_types[0] & JumpAbsolute)))
2236 {
2237 as_warn (_("indirect %s without `*'"), t->name);
2238 }
2239
2240 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2241 == (IsPrefix | IgnoreSize))
2242 {
2243 /* Warn them that a data or address size prefix doesn't
2244 affect assembly of the next line of code. */
2245 as_warn (_("stand-alone `%s' prefix"), t->name);
2246 }
2247 }
2248
2249 /* Copy the template we found. */
2250 i.tm = *t;
2251 if (found_reverse_match)
2252 {
2253 /* If we found a reverse match we must alter the opcode
2254 direction bit. found_reverse_match holds bits to change
2255 (different for int & float insns). */
2256
2257 i.tm.base_opcode ^= found_reverse_match;
2258
2259 i.tm.operand_types[0] = t->operand_types[1];
2260 i.tm.operand_types[1] = t->operand_types[0];
2261 }
2262
2263 return 1;
2264}
2265
2266static int
2267check_string ()
2268{
2269 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2270 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2271 {
2272 if (i.seg[0] != NULL && i.seg[0] != &es)
2273 {
2274 as_bad (_("`%s' operand %d must use `%%es' segment"),
2275 i.tm.name,
2276 mem_op + 1);
2277 return 0;
2278 }
2279 /* There's only ever one segment override allowed per instruction.
2280 This instruction possibly has a legal segment override on the
2281 second operand, so copy the segment to where non-string
2282 instructions store it, allowing common code. */
2283 i.seg[0] = i.seg[1];
2284 }
2285 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2286 {
2287 if (i.seg[1] != NULL && i.seg[1] != &es)
2288 {
2289 as_bad (_("`%s' operand %d must use `%%es' segment"),
2290 i.tm.name,
2291 mem_op + 2);
2292 return 0;
2293 }
2294 }
2295 return 1;
2296}
2297
2298static int
543613e9 2299process_suffix (void)
29b0f896
AM		 2300{
2301 /* If matched instruction specifies an explicit instruction mnemonic
2302 suffix, use it. */
2303 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2304 {
2305 if (i.tm.opcode_modifier & Size16)
2306 i.suffix = WORD_MNEM_SUFFIX;
2307 else if (i.tm.opcode_modifier & Size64)
2308 i.suffix = QWORD_MNEM_SUFFIX;
2309 else
2310 i.suffix = LONG_MNEM_SUFFIX;
2311 }
2312 else if (i.reg_operands)
2313 {
2314 /* If there's no instruction mnemonic suffix we try to invent one
2315 based on register operands. */
2316 if (!i.suffix)
2317 {
2318 /* We take i.suffix from the last register operand specified,
2319 Destination register type is more significant than source
2320 register type. */
2321 int op;
543613e9 2322
29b0f896
AM		 2323 for (op = i.operands; --op >= 0;)
2324 if ((i.types[op] & Reg)
2325 && !(i.tm.operand_types[op] & InOutPortReg))
2326 {
2327 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2328 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2329 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2330 LONG_MNEM_SUFFIX);
2331 break;
2332 }
2333 }
2334 else if (i.suffix == BYTE_MNEM_SUFFIX)
2335 {
2336 if (!check_byte_reg ())
2337 return 0;
2338 }
2339 else if (i.suffix == LONG_MNEM_SUFFIX)
2340 {
2341 if (!check_long_reg ())
2342 return 0;
2343 }
2344 else if (i.suffix == QWORD_MNEM_SUFFIX)
2345 {
2346 if (!check_qword_reg ())
2347 return 0;
2348 }
2349 else if (i.suffix == WORD_MNEM_SUFFIX)
2350 {
2351 if (!check_word_reg ())
2352 return 0;
2353 }
2354 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2355 /* Do nothing if the instruction is going to ignore the prefix. */
2356 ;
2357 else
2358 abort ();
2359 }
9306ca4a
JB		 2360 else if ((i.tm.opcode_modifier & DefaultSize)
2361 && !i.suffix
2362 /* exclude fldenv/frstor/fsave/fstenv */
2363 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2364 {
2365 i.suffix = stackop_size;
2366 }
9306ca4a
JB		 2367 else if (intel_syntax
2368 && !i.suffix
2369 && ((i.tm.operand_types[0] & JumpAbsolute)
2370 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2371 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2372 && i.tm.extension_opcode <= 3)))
2373 {
2374 switch (flag_code)
2375 {
2376 case CODE_64BIT:
2377 if (!(i.tm.opcode_modifier & No_qSuf))
2378 {
2379 i.suffix = QWORD_MNEM_SUFFIX;
2380 break;
2381 }
2382 case CODE_32BIT:
2383 if (!(i.tm.opcode_modifier & No_lSuf))
2384 i.suffix = LONG_MNEM_SUFFIX;
2385 break;
2386 case CODE_16BIT:
2387 if (!(i.tm.opcode_modifier & No_wSuf))
2388 i.suffix = WORD_MNEM_SUFFIX;
2389 break;
2390 }
2391 }
252b5132 2392
9306ca4a 2393 if (!i.suffix)
29b0f896 2394 {
9306ca4a
JB		 2395 if (!intel_syntax)
2396 {
2397 if (i.tm.opcode_modifier & W)
2398 {
2399 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2400 return 0;
2401 }
2402 }
2403 else
2404 {
2405 unsigned int suffixes = ~i.tm.opcode_modifier
2406 & (No_bSuf
2407 | No_wSuf
2408 | No_lSuf
2409 | No_sSuf
2410 | No_xSuf
2411 | No_qSuf);
2412
2413 if ((i.tm.opcode_modifier & W)
2414 || ((suffixes & (suffixes - 1))
2415 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2416 {
2417 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2418 return 0;
2419 }
2420 }
29b0f896 2421 }
252b5132 2422
9306ca4a
JB		 2423 /* Change the opcode based on the operand size given by i.suffix;
2424 We don't need to change things for byte insns. */
2425
29b0f896
AM		 2426 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2427 {
2428 /* It's not a byte, select word/dword operation. */
2429 if (i.tm.opcode_modifier & W)
2430 {
2431 if (i.tm.opcode_modifier & ShortForm)
2432 i.tm.base_opcode |= 8;
2433 else
2434 i.tm.base_opcode |= 1;
2435 }
0f3f3d8b 2436
29b0f896
AM		 2437 /* Now select between word & dword operations via the operand
2438 size prefix, except for instructions that will ignore this
2439 prefix anyway. */
2440 if (i.suffix != QWORD_MNEM_SUFFIX
9306ca4a
JB		 2441 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2442 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
9146926a
AM		 2443 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2444 || (flag_code == CODE_64BIT
2445 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2446 {
2447 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2448
29b0f896
AM		 2449 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2450 prefix = ADDR_PREFIX_OPCODE;
252b5132 2451
29b0f896
AM		 2452 if (!add_prefix (prefix))
2453 return 0;
24eab124 2454 }
252b5132 2455
29b0f896
AM		 2456 /* Set mode64 for an operand. */
2457 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2458 && flag_code == CODE_64BIT
29b0f896 2459 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2460 i.rex |= REX_MODE64;
3e73aa7c 2461
29b0f896
AM		 2462 /* Size floating point instruction. */
2463 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2464 if (i.tm.opcode_modifier & FloatMF)
2465 i.tm.base_opcode ^= 4;
29b0f896 2466 }
7ecd2f8b 2467
29b0f896
AM		 2468 return 1;
2469}
3e73aa7c 2470
29b0f896 2471static int
543613e9 2472check_byte_reg (void)
29b0f896
AM		 2473{
2474 int op;
543613e9 2475
29b0f896
AM		 2476 for (op = i.operands; --op >= 0;)
2477 {
2478 /* If this is an eight bit register, it's OK. If it's the 16 or
2479 32 bit version of an eight bit register, we will just use the
2480 low portion, and that's OK too. */
2481 if (i.types[op] & Reg8)
2482 continue;
2483
2484 /* movzx and movsx should not generate this warning. */
2485 if (intel_syntax
2486 && (i.tm.base_opcode == 0xfb7
2487 || i.tm.base_opcode == 0xfb6
2488 || i.tm.base_opcode == 0x63
2489 || i.tm.base_opcode == 0xfbe
2490 || i.tm.base_opcode == 0xfbf))
2491 continue;
2492
65ec77d2 2493 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 2494 {
2495 /* Prohibit these changes in the 64bit mode, since the
2496 lowering is more complicated. */
2497 if (flag_code == CODE_64BIT
2498 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2499 {
0f3f3d8b 2500 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2501 i.op[op].regs->reg_name,
2502 i.suffix);
2503 return 0;
2504 }
2505#if REGISTER_WARNINGS
2506 if (!quiet_warnings
2507 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2508 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2509 (i.op[op].regs + (i.types[op] & Reg16
2510 ? REGNAM_AL - REGNAM_AX
2511 : REGNAM_AL - REGNAM_EAX))->reg_name,
2512 i.op[op].regs->reg_name,
2513 i.suffix);
2514#endif
2515 continue;
2516 }
2517 /* Any other register is bad. */
2518 if (i.types[op] & (Reg | RegMMX | RegXMM
2519 | SReg2 | SReg3
2520 | Control | Debug | Test
2521 | FloatReg | FloatAcc))
2522 {
2523 as_bad (_("`%%%s' not allowed with `%s%c'"),
2524 i.op[op].regs->reg_name,
2525 i.tm.name,
2526 i.suffix);
2527 return 0;
2528 }
2529 }
2530 return 1;
2531}
2532
2533static int
2534check_long_reg ()
2535{
2536 int op;
2537
2538 for (op = i.operands; --op >= 0;)
2539 /* Reject eight bit registers, except where the template requires
2540 them. (eg. movzb) */
2541 if ((i.types[op] & Reg8) != 0
2542 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2543 {
2544 as_bad (_("`%%%s' not allowed with `%s%c'"),
2545 i.op[op].regs->reg_name,
2546 i.tm.name,
2547 i.suffix);
2548 return 0;
2549 }
2550 /* Warn if the e prefix on a general reg is missing. */
2551 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2552 && (i.types[op] & Reg16) != 0
2553 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2554 {
2555 /* Prohibit these changes in the 64bit mode, since the
2556 lowering is more complicated. */
2557 if (flag_code == CODE_64BIT)
252b5132 2558 {
0f3f3d8b 2559 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2560 i.op[op].regs->reg_name,
2561 i.suffix);
2562 return 0;
252b5132 2563 }
29b0f896
AM		 2564#if REGISTER_WARNINGS
2565 else
2566 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2567 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2568 i.op[op].regs->reg_name,
2569 i.suffix);
2570#endif
252b5132 2571 }
29b0f896
AM		 2572 /* Warn if the r prefix on a general reg is missing. */
2573 else if ((i.types[op] & Reg64) != 0
2574 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2575 {
0f3f3d8b 2576 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2577 i.op[op].regs->reg_name,
2578 i.suffix);
2579 return 0;
2580 }
2581 return 1;
2582}
252b5132 2583
29b0f896
AM		 2584static int
2585check_qword_reg ()
2586{
2587 int op;
252b5132 2588
29b0f896
AM		 2589 for (op = i.operands; --op >= 0; )
2590 /* Reject eight bit registers, except where the template requires
2591 them. (eg. movzb) */
2592 if ((i.types[op] & Reg8) != 0
2593 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2594 {
2595 as_bad (_("`%%%s' not allowed with `%s%c'"),
2596 i.op[op].regs->reg_name,
2597 i.tm.name,
2598 i.suffix);
2599 return 0;
2600 }
2601 /* Warn if the e prefix on a general reg is missing. */
2602 else if (((i.types[op] & Reg16) != 0
2603 || (i.types[op] & Reg32) != 0)
2604 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2605 {
2606 /* Prohibit these changes in the 64bit mode, since the
2607 lowering is more complicated. */
0f3f3d8b 2608 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2609 i.op[op].regs->reg_name,
2610 i.suffix);
2611 return 0;
252b5132 2612 }
29b0f896
AM		 2613 return 1;
2614}
252b5132 2615
29b0f896
AM		 2616static int
2617check_word_reg ()
2618{
2619 int op;
2620 for (op = i.operands; --op >= 0;)
2621 /* Reject eight bit registers, except where the template requires
2622 them. (eg. movzb) */
2623 if ((i.types[op] & Reg8) != 0
2624 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2625 {
2626 as_bad (_("`%%%s' not allowed with `%s%c'"),
2627 i.op[op].regs->reg_name,
2628 i.tm.name,
2629 i.suffix);
2630 return 0;
2631 }
2632 /* Warn if the e prefix on a general reg is present. */
2633 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2634 && (i.types[op] & Reg32) != 0
2635 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2636 {
29b0f896
AM		 2637 /* Prohibit these changes in the 64bit mode, since the
2638 lowering is more complicated. */
2639 if (flag_code == CODE_64BIT)
252b5132 2640 {
0f3f3d8b 2641 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2642 i.op[op].regs->reg_name,
2643 i.suffix);
2644 return 0;
252b5132 2645 }
29b0f896
AM		 2646 else
2647#if REGISTER_WARNINGS
2648 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2649 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2650 i.op[op].regs->reg_name,
2651 i.suffix);
2652#endif
2653 }
2654 return 1;
2655}
252b5132 2656
29b0f896
AM		 2657static int
2658finalize_imm ()
2659{
2660 unsigned int overlap0, overlap1, overlap2;
2661
2662 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 2663 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 2664 && overlap0 != Imm8 && overlap0 != Imm8S
2665 && overlap0 != Imm16 && overlap0 != Imm32S
2666 && overlap0 != Imm32 && overlap0 != Imm64)
2667 {
2668 if (i.suffix)
2669 {
2670 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2671 ? Imm8 | Imm8S
2672 : (i.suffix == WORD_MNEM_SUFFIX
2673 ? Imm16
2674 : (i.suffix == QWORD_MNEM_SUFFIX
2675 ? Imm64 | Imm32S
2676 : Imm32)));
2677 }
2678 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2679 || overlap0 == (Imm16 | Imm32)
2680 || overlap0 == (Imm16 | Imm32S))
2681 {
2682 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2683 ? Imm16 : Imm32S);
2684 }
2685 if (overlap0 != Imm8 && overlap0 != Imm8S
2686 && overlap0 != Imm16 && overlap0 != Imm32S
2687 && overlap0 != Imm32 && overlap0 != Imm64)
2688 {
2689 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2690 return 0;
2691 }
2692 }
2693 i.types[0] = overlap0;
2694
2695 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 2696 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 2697 && overlap1 != Imm8 && overlap1 != Imm8S
2698 && overlap1 != Imm16 && overlap1 != Imm32S
2699 && overlap1 != Imm32 && overlap1 != Imm64)
2700 {
2701 if (i.suffix)
2702 {
2703 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2704 ? Imm8 | Imm8S
2705 : (i.suffix == WORD_MNEM_SUFFIX
2706 ? Imm16
2707 : (i.suffix == QWORD_MNEM_SUFFIX
2708 ? Imm64 | Imm32S
2709 : Imm32)));
2710 }
2711 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2712 || overlap1 == (Imm16 | Imm32)
2713 || overlap1 == (Imm16 | Imm32S))
2714 {
2715 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2716 ? Imm16 : Imm32S);
2717 }
2718 if (overlap1 != Imm8 && overlap1 != Imm8S
2719 && overlap1 != Imm16 && overlap1 != Imm32S
2720 && overlap1 != Imm32 && overlap1 != Imm64)
2721 {
2722 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2723 return 0;
2724 }
2725 }
2726 i.types[1] = overlap1;
2727
2728 overlap2 = i.types[2] & i.tm.operand_types[2];
2729 assert ((overlap2 & Imm) == 0);
2730 i.types[2] = overlap2;
2731
2732 return 1;
2733}
2734
2735static int
2736process_operands ()
2737{
2738 /* Default segment register this instruction will use for memory
2739 accesses. 0 means unknown. This is only for optimizing out
2740 unnecessary segment overrides. */
2741 const seg_entry *default_seg = 0;
2742
2743 /* The imul $imm, %reg instruction is converted into
2744 imul $imm, %reg, %reg, and the clr %reg instruction
2745 is converted into xor %reg, %reg. */
2746 if (i.tm.opcode_modifier & regKludge)
2747 {
2748 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2749 /* Pretend we saw the extra register operand. */
2750 assert (i.op[first_reg_op + 1].regs == 0);
2751 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2752 i.types[first_reg_op + 1] = i.types[first_reg_op];
2753 i.reg_operands = 2;
2754 }
2755
2756 if (i.tm.opcode_modifier & ShortForm)
2757 {
2758 /* The register or float register operand is in operand 0 or 1. */
2759 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2760 /* Register goes in low 3 bits of opcode. */
2761 i.tm.base_opcode |= i.op[op].regs->reg_num;
2762 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2763 i.rex |= REX_EXTZ;
2764 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2765 {
2766 /* Warn about some common errors, but press on regardless.
2767 The first case can be generated by gcc (<= 2.8.1). */
2768 if (i.operands == 2)
2769 {
2770 /* Reversed arguments on faddp, fsubp, etc. */
2771 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2772 i.op[1].regs->reg_name,
2773 i.op[0].regs->reg_name);
2774 }
2775 else
2776 {
2777 /* Extraneous `l' suffix on fp insn. */
2778 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2779 i.op[0].regs->reg_name);
2780 }
2781 }
2782 }
2783 else if (i.tm.opcode_modifier & Modrm)
2784 {
2785 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2786 must be put into the modrm byte). Now, we make the modrm and
2787 index base bytes based on all the info we've collected. */
29b0f896
AM		 2788
2789 default_seg = build_modrm_byte ();
2790 }
2791 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2792 {
2793 if (i.tm.base_opcode == POP_SEG_SHORT
2794 && i.op[0].regs->reg_num == 1)
2795 {
2796 as_bad (_("you can't `pop %%cs'"));
2797 return 0;
2798 }
2799 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2800 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2801 i.rex |= REX_EXTZ;
2802 }
2803 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2804 {
2805 default_seg = &ds;
2806 }
2807 else if ((i.tm.opcode_modifier & IsString) != 0)
2808 {
2809 /* For the string instructions that allow a segment override
2810 on one of their operands, the default segment is ds. */
2811 default_seg = &ds;
2812 }
2813
52271982
AM		 2814 if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings)
2815 as_warn (_("segment override on `lea' is ineffectual"));
2816
2817 /* If a segment was explicitly specified, and the specified segment
2818 is not the default, use an opcode prefix to select it. If we
2819 never figured out what the default segment is, then default_seg
2820 will be zero at this point, and the specified segment prefix will
2821 always be used. */
29b0f896
AM		 2822 if ((i.seg[0]) && (i.seg[0] != default_seg))
2823 {
2824 if (!add_prefix (i.seg[0]->seg_prefix))
2825 return 0;
2826 }
2827 return 1;
2828}
2829
2830static const seg_entry *
2831build_modrm_byte ()
2832{
2833 const seg_entry *default_seg = 0;
2834
2835 /* i.reg_operands MUST be the number of real register operands;
2836 implicit registers do not count. */
2837 if (i.reg_operands == 2)
2838 {
2839 unsigned int source, dest;
2840 source = ((i.types[0]
2841 & (Reg | RegMMX | RegXMM
2842 | SReg2 | SReg3
2843 | Control | Debug | Test))
2844 ? 0 : 1);
2845 dest = source + 1;
2846
2847 i.rm.mode = 3;
2848 /* One of the register operands will be encoded in the i.tm.reg
2849 field, the other in the combined i.tm.mode and i.tm.regmem
2850 fields. If no form of this instruction supports a memory
2851 destination operand, then we assume the source operand may
2852 sometimes be a memory operand and so we need to store the
2853 destination in the i.rm.reg field. */
2854 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2855 {
2856 i.rm.reg = i.op[dest].regs->reg_num;
2857 i.rm.regmem = i.op[source].regs->reg_num;
2858 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2859 i.rex |= REX_EXTX;
2860 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2861 i.rex |= REX_EXTZ;
2862 }
2863 else
2864 {
2865 i.rm.reg = i.op[source].regs->reg_num;
2866 i.rm.regmem = i.op[dest].regs->reg_num;
2867 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2868 i.rex |= REX_EXTZ;
2869 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2870 i.rex |= REX_EXTX;
2871 }
c4a530c5
JB		 2872 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
2873 {
2874 if (!((i.types[0] | i.types[1]) & Control))
2875 abort ();
2876 i.rex &= ~(REX_EXTX | REX_EXTZ);
2877 add_prefix (LOCK_PREFIX_OPCODE);
2878 }
29b0f896
AM		 2879 }
2880 else
2881 { /* If it's not 2 reg operands... */
2882 if (i.mem_operands)
2883 {
2884 unsigned int fake_zero_displacement = 0;
2885 unsigned int op = ((i.types[0] & AnyMem)
2886 ? 0
2887 : (i.types[1] & AnyMem) ? 1 : 2);
2888
2889 default_seg = &ds;
2890
2891 if (i.base_reg == 0)
2892 {
2893 i.rm.mode = 0;
2894 if (!i.disp_operands)
2895 fake_zero_displacement = 1;
2896 if (i.index_reg == 0)
2897 {
2898 /* Operand is just <disp> */
20f0a1fc 2899 if (flag_code == CODE_64BIT)
29b0f896
AM		 2900 {
2901 /* 64bit mode overwrites the 32bit absolute
2902 addressing by RIP relative addressing and
2903 absolute addressing is encoded by one of the
2904 redundant SIB forms. */
2905 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2906 i.sib.base = NO_BASE_REGISTER;
2907 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 2908 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
2909 }
2910 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
2911 {
2912 i.rm.regmem = NO_BASE_REGISTER_16;
2913 i.types[op] = Disp16;
2914 }
2915 else
2916 {
2917 i.rm.regmem = NO_BASE_REGISTER;
2918 i.types[op] = Disp32;
29b0f896
AM		 2919 }
2920 }
2921 else /* !i.base_reg && i.index_reg */
2922 {
2923 i.sib.index = i.index_reg->reg_num;
2924 i.sib.base = NO_BASE_REGISTER;
2925 i.sib.scale = i.log2_scale_factor;
2926 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2927 i.types[op] &= ~Disp;
2928 if (flag_code != CODE_64BIT)
2929 i.types[op] |= Disp32; /* Must be 32 bit */
2930 else
2931 i.types[op] |= Disp32S;
2932 if ((i.index_reg->reg_flags & RegRex) != 0)
2933 i.rex |= REX_EXTY;
2934 }
2935 }
2936 /* RIP addressing for 64bit mode. */
2937 else if (i.base_reg->reg_type == BaseIndex)
2938 {
2939 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 2940 i.types[op] &= ~ Disp;
29b0f896
AM		 2941 i.types[op] |= Disp32S;
2942 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 2943 if (! i.disp_operands)
2944 fake_zero_displacement = 1;
29b0f896
AM		 2945 }
2946 else if (i.base_reg->reg_type & Reg16)
2947 {
2948 switch (i.base_reg->reg_num)
2949 {
2950 case 3: /* (%bx) */
2951 if (i.index_reg == 0)
2952 i.rm.regmem = 7;
2953 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2954 i.rm.regmem = i.index_reg->reg_num - 6;
2955 break;
2956 case 5: /* (%bp) */
2957 default_seg = &ss;
2958 if (i.index_reg == 0)
2959 {
2960 i.rm.regmem = 6;
2961 if ((i.types[op] & Disp) == 0)
2962 {
2963 /* fake (%bp) into 0(%bp) */
2964 i.types[op] |= Disp8;
252b5132 2965 fake_zero_displacement = 1;
29b0f896
AM		 2966 }
2967 }
2968 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2969 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2970 break;
2971 default: /* (%si) -> 4 or (%di) -> 5 */
2972 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2973 }
2974 i.rm.mode = mode_from_disp_size (i.types[op]);
2975 }
2976 else /* i.base_reg and 32/64 bit mode */
2977 {
2978 if (flag_code == CODE_64BIT
2979 && (i.types[op] & Disp))
20f0a1fc
NC		 2980 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
2981
29b0f896
AM		 2982 i.rm.regmem = i.base_reg->reg_num;
2983 if ((i.base_reg->reg_flags & RegRex) != 0)
2984 i.rex |= REX_EXTZ;
2985 i.sib.base = i.base_reg->reg_num;
2986 /* x86-64 ignores REX prefix bit here to avoid decoder
2987 complications. */
2988 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2989 {
2990 default_seg = &ss;
2991 if (i.disp_operands == 0)
2992 {
2993 fake_zero_displacement = 1;
2994 i.types[op] |= Disp8;
2995 }
2996 }
2997 else if (i.base_reg->reg_num == ESP_REG_NUM)
2998 {
2999 default_seg = &ss;
3000 }
3001 i.sib.scale = i.log2_scale_factor;
3002 if (i.index_reg == 0)
3003 {
3004 /* <disp>(%esp) becomes two byte modrm with no index
3005 register. We've already stored the code for esp
3006 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3007 Any base register besides %esp will not use the
3008 extra modrm byte. */
3009 i.sib.index = NO_INDEX_REGISTER;
3010#if !SCALE1_WHEN_NO_INDEX
3011 /* Another case where we force the second modrm byte. */
3012 if (i.log2_scale_factor)
3013 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3014#endif
29b0f896
AM		 3015 }
3016 else
3017 {
3018 i.sib.index = i.index_reg->reg_num;
3019 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3020 if ((i.index_reg->reg_flags & RegRex) != 0)
3021 i.rex |= REX_EXTY;
3022 }
3023 i.rm.mode = mode_from_disp_size (i.types[op]);
3024 }
252b5132 3025
29b0f896
AM		 3026 if (fake_zero_displacement)
3027 {
3028 /* Fakes a zero displacement assuming that i.types[op]
3029 holds the correct displacement size. */
3030 expressionS *exp;
3031
3032 assert (i.op[op].disps == 0);
3033 exp = &disp_expressions[i.disp_operands++];
3034 i.op[op].disps = exp;
3035 exp->X_op = O_constant;
3036 exp->X_add_number = 0;
3037 exp->X_add_symbol = (symbolS *) 0;
3038 exp->X_op_symbol = (symbolS *) 0;
3039 }
3040 }
252b5132 3041
29b0f896
AM		 3042 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3043 (if any) based on i.tm.extension_opcode. Again, we must be
3044 careful to make sure that segment/control/debug/test/MMX
3045 registers are coded into the i.rm.reg field. */
3046 if (i.reg_operands)
3047 {
3048 unsigned int op =
3049 ((i.types[0]
3050 & (Reg | RegMMX | RegXMM
3051 | SReg2 | SReg3
3052 | Control | Debug | Test))
3053 ? 0
3054 : ((i.types[1]
3055 & (Reg | RegMMX | RegXMM
3056 | SReg2 | SReg3
3057 | Control | Debug | Test))
3058 ? 1
3059 : 2));
3060 /* If there is an extension opcode to put here, the register
3061 number must be put into the regmem field. */
3062 if (i.tm.extension_opcode != None)
3063 {
3064 i.rm.regmem = i.op[op].regs->reg_num;
3065 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3066 i.rex |= REX_EXTZ;
3067 }
3068 else
3069 {
3070 i.rm.reg = i.op[op].regs->reg_num;
3071 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3072 i.rex |= REX_EXTX;
3073 }
252b5132 3074
29b0f896
AM		 3075 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3076 must set it to 3 to indicate this is a register operand
3077 in the regmem field. */
3078 if (!i.mem_operands)
3079 i.rm.mode = 3;
3080 }
252b5132 3081
29b0f896
AM		 3082 /* Fill in i.rm.reg field with extension opcode (if any). */
3083 if (i.tm.extension_opcode != None)
3084 i.rm.reg = i.tm.extension_opcode;
3085 }
3086 return default_seg;
3087}
252b5132 3088
29b0f896
AM		 3089static void
3090output_branch ()
3091{
3092 char *p;
3093 int code16;
3094 int prefix;
3095 relax_substateT subtype;
3096 symbolS *sym;
3097 offsetT off;
3098
3099 code16 = 0;
3100 if (flag_code == CODE_16BIT)
3101 code16 = CODE16;
3102
3103 prefix = 0;
3104 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3105 {
29b0f896
AM		 3106 prefix = 1;
3107 i.prefixes -= 1;
3108 code16 ^= CODE16;
252b5132 3109 }
29b0f896
AM		 3110 /* Pentium4 branch hints. */
3111 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3112 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3113 {
29b0f896
AM		 3114 prefix++;
3115 i.prefixes--;
3116 }
3117 if (i.prefix[REX_PREFIX] != 0)
3118 {
3119 prefix++;
3120 i.prefixes--;
2f66722d
AM		 3121 }
3122
29b0f896
AM		 3123 if (i.prefixes != 0 && !intel_syntax)
3124 as_warn (_("skipping prefixes on this instruction"));
3125
3126 /* It's always a symbol; End frag & setup for relax.
3127 Make sure there is enough room in this frag for the largest
3128 instruction we may generate in md_convert_frag. This is 2
3129 bytes for the opcode and room for the prefix and largest
3130 displacement. */
3131 frag_grow (prefix + 2 + 4);
3132 /* Prefix and 1 opcode byte go in fr_fix. */
3133 p = frag_more (prefix + 1);
3134 if (i.prefix[DATA_PREFIX] != 0)
3135 *p++ = DATA_PREFIX_OPCODE;
3136 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3137 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3138 *p++ = i.prefix[SEG_PREFIX];
3139 if (i.prefix[REX_PREFIX] != 0)
3140 *p++ = i.prefix[REX_PREFIX];
3141 *p = i.tm.base_opcode;
3142
3143 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3144 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3145 else if ((cpu_arch_flags & Cpu386) != 0)
3146 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3147 else
3148 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3149 subtype |= code16;
3e73aa7c 3150
29b0f896
AM		 3151 sym = i.op[0].disps->X_add_symbol;
3152 off = i.op[0].disps->X_add_number;
3e73aa7c 3153
29b0f896
AM		 3154 if (i.op[0].disps->X_op != O_constant
3155 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3156 {
29b0f896
AM		 3157 /* Handle complex expressions. */
3158 sym = make_expr_symbol (i.op[0].disps);
3159 off = 0;
3160 }
3e73aa7c 3161
29b0f896
AM		 3162 /* 1 possible extra opcode + 4 byte displacement go in var part.
3163 Pass reloc in fr_var. */
3164 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3165}
3e73aa7c 3166
29b0f896
AM		 3167static void
3168output_jump ()
3169{
3170 char *p;
3171 int size;
3e02c1cc 3172 fixS *fixP;
29b0f896
AM		 3173
3174 if (i.tm.opcode_modifier & JumpByte)
3175 {
3176 /* This is a loop or jecxz type instruction. */
3177 size = 1;
3178 if (i.prefix[ADDR_PREFIX] != 0)
3179 {
3180 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3181 i.prefixes -= 1;
3182 }
3183 /* Pentium4 branch hints. */
3184 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3185 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3186 {
3187 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3188 i.prefixes--;
3e73aa7c
JH		 3189 }
3190 }
29b0f896
AM		 3191 else
3192 {
3193 int code16;
3e73aa7c 3194
29b0f896
AM		 3195 code16 = 0;
3196 if (flag_code == CODE_16BIT)
3197 code16 = CODE16;
3e73aa7c 3198
29b0f896
AM		 3199 if (i.prefix[DATA_PREFIX] != 0)
3200 {
3201 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3202 i.prefixes -= 1;
3203 code16 ^= CODE16;
3204 }
252b5132 3205
29b0f896
AM		 3206 size = 4;
3207 if (code16)
3208 size = 2;
3209 }
9fcc94b6 3210
29b0f896
AM		 3211 if (i.prefix[REX_PREFIX] != 0)
3212 {
3213 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3214 i.prefixes -= 1;
3215 }
252b5132 3216
29b0f896
AM		 3217 if (i.prefixes != 0 && !intel_syntax)
3218 as_warn (_("skipping prefixes on this instruction"));
e0890092 3219
29b0f896
AM		 3220 p = frag_more (1 + size);
3221 *p++ = i.tm.base_opcode;
e0890092 3222
3e02c1cc
AM		 3223 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3224 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3225
3226 /* All jumps handled here are signed, but don't use a signed limit
3227 check for 32 and 16 bit jumps as we want to allow wrap around at
3228 4G and 64k respectively. */
3229 if (size == 1)
3230 fixP->fx_signed = 1;
29b0f896 3231}
e0890092 3232
29b0f896
AM		 3233static void
3234output_interseg_jump ()
3235{
3236 char *p;
3237 int size;
3238 int prefix;
3239 int code16;
252b5132 3240
29b0f896
AM		 3241 code16 = 0;
3242 if (flag_code == CODE_16BIT)
3243 code16 = CODE16;
a217f122 3244
29b0f896
AM		 3245 prefix = 0;
3246 if (i.prefix[DATA_PREFIX] != 0)
3247 {
3248 prefix = 1;
3249 i.prefixes -= 1;
3250 code16 ^= CODE16;
3251 }
3252 if (i.prefix[REX_PREFIX] != 0)
3253 {
3254 prefix++;
3255 i.prefixes -= 1;
3256 }
252b5132 3257
29b0f896
AM		 3258 size = 4;
3259 if (code16)
3260 size = 2;
252b5132 3261
29b0f896
AM		 3262 if (i.prefixes != 0 && !intel_syntax)
3263 as_warn (_("skipping prefixes on this instruction"));
252b5132 3264
29b0f896
AM		 3265 /* 1 opcode; 2 segment; offset */
3266 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3267
29b0f896
AM		 3268 if (i.prefix[DATA_PREFIX] != 0)
3269 *p++ = DATA_PREFIX_OPCODE;
252b5132 3270
29b0f896
AM		 3271 if (i.prefix[REX_PREFIX] != 0)
3272 *p++ = i.prefix[REX_PREFIX];
252b5132 3273
29b0f896
AM		 3274 *p++ = i.tm.base_opcode;
3275 if (i.op[1].imms->X_op == O_constant)
3276 {
3277 offsetT n = i.op[1].imms->X_add_number;
252b5132 3278
29b0f896
AM		 3279 if (size == 2
3280 && !fits_in_unsigned_word (n)
3281 && !fits_in_signed_word (n))
3282 {
3283 as_bad (_("16-bit jump out of range"));
3284 return;
3285 }
3286 md_number_to_chars (p, n, size);
3287 }
3288 else
3289 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3290 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3291 if (i.op[0].imms->X_op != O_constant)
3292 as_bad (_("can't handle non absolute segment in `%s'"),
3293 i.tm.name);
3294 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3295}
a217f122 3296
29b0f896
AM		 3297static void
3298output_insn ()
3299{
2bbd9c25
JJ		 3300 fragS *insn_start_frag;
3301 offsetT insn_start_off;
3302
29b0f896
AM		 3303 /* Tie dwarf2 debug info to the address at the start of the insn.
3304 We can't do this after the insn has been output as the current
3305 frag may have been closed off. eg. by frag_var. */
3306 dwarf2_emit_insn (0);
3307
2bbd9c25
JJ		 3308 insn_start_frag = frag_now;
3309 insn_start_off = frag_now_fix ();
3310
29b0f896
AM		 3311 /* Output jumps. */
3312 if (i.tm.opcode_modifier & Jump)
3313 output_branch ();
3314 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3315 output_jump ();
3316 else if (i.tm.opcode_modifier & JumpInterSegment)
3317 output_interseg_jump ();
3318 else
3319 {
3320 /* Output normal instructions here. */
3321 char *p;
3322 unsigned char *q;
252b5132 3323
bc4bd9ab
MK		 3324 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3325 more higher byte to specify a prefix the instruction
3326 requires. */
3327 if ((i.tm.base_opcode & 0xff0000) != 0)
3328 {
3329 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3330 {
3331 unsigned int prefix;
3332 prefix = (i.tm.base_opcode >> 16) & 0xff;
3333
3334 if (prefix != REPE_PREFIX_OPCODE
3335 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3336 add_prefix (prefix);
3337 }
3338 else
3339 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
0f10071e 3340 }
252b5132 3341
29b0f896
AM		 3342 /* The prefix bytes. */
3343 for (q = i.prefix;
3344 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3345 q++)
3346 {
3347 if (*q)
3348 {
3349 p = frag_more (1);
3350 md_number_to_chars (p, (valueT) *q, 1);
3351 }
3352 }
252b5132 3353
29b0f896
AM		 3354 /* Now the opcode; be careful about word order here! */
3355 if (fits_in_unsigned_byte (i.tm.base_opcode))
3356 {
3357 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3358 }
3359 else
3360 {
bc4bd9ab 3361 p = frag_more (2);
0f10071e 3362
29b0f896
AM		 3363 /* Put out high byte first: can't use md_number_to_chars! */
3364 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3365 *p = i.tm.base_opcode & 0xff;
3366 }
3e73aa7c 3367
29b0f896
AM		 3368 /* Now the modrm byte and sib byte (if present). */
3369 if (i.tm.opcode_modifier & Modrm)
3370 {
3371 p = frag_more (1);
3372 md_number_to_chars (p,
3373 (valueT) (i.rm.regmem << 0
3374 | i.rm.reg << 3
3375 | i.rm.mode << 6),
3376 1);
3377 /* If i.rm.regmem == ESP (4)
3378 && i.rm.mode != (Register mode)
3379 && not 16 bit
3380 ==> need second modrm byte. */
3381 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3382 && i.rm.mode != 3
3383 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3384 {
3385 p = frag_more (1);
3386 md_number_to_chars (p,
3387 (valueT) (i.sib.base << 0
3388 | i.sib.index << 3
3389 | i.sib.scale << 6),
3390 1);
3391 }
3392 }
3e73aa7c 3393
29b0f896 3394 if (i.disp_operands)
2bbd9c25 3395 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3396
29b0f896 3397 if (i.imm_operands)
2bbd9c25 3398 output_imm (insn_start_frag, insn_start_off);
29b0f896 3399 }
252b5132 3400
29b0f896
AM		 3401#ifdef DEBUG386
3402 if (flag_debug)
3403 {
3404 pi (line, &i);
3405 }
3406#endif /* DEBUG386 */
3407}
252b5132 3408
29b0f896 3409static void
2bbd9c25
JJ		 3410output_disp (insn_start_frag, insn_start_off)
3411 fragS *insn_start_frag;
3412 offsetT insn_start_off;
29b0f896
AM		 3413{
3414 char *p;
3415 unsigned int n;
252b5132 3416
29b0f896
AM		 3417 for (n = 0; n < i.operands; n++)
3418 {
3419 if (i.types[n] & Disp)
3420 {
3421 if (i.op[n].disps->X_op == O_constant)
3422 {
3423 int size;
3424 offsetT val;
252b5132 3425
29b0f896
AM		 3426 size = 4;
3427 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3428 {
3429 size = 2;
3430 if (i.types[n] & Disp8)
3431 size = 1;
3432 if (i.types[n] & Disp64)
3433 size = 8;
3434 }
3435 val = offset_in_range (i.op[n].disps->X_add_number,
3436 size);
3437 p = frag_more (size);
3438 md_number_to_chars (p, val, size);
3439 }
3440 else
3441 {
f86103b7 3442 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3443 int size = 4;
3444 int sign = 0;
3445 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3446
3447 /* The PC relative address is computed relative
3448 to the instruction boundary, so in case immediate
3449 fields follows, we need to adjust the value. */
3450 if (pcrel && i.imm_operands)
3451 {
3452 int imm_size = 4;
3453 unsigned int n1;
252b5132 3454
29b0f896
AM		 3455 for (n1 = 0; n1 < i.operands; n1++)
3456 if (i.types[n1] & Imm)
252b5132 3457 {
29b0f896 3458 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3459 {
29b0f896
AM		 3460 imm_size = 2;
3461 if (i.types[n1] & (Imm8 | Imm8S))
3462 imm_size = 1;
3463 if (i.types[n1] & Imm64)
3464 imm_size = 8;
252b5132 3465 }
29b0f896 3466 break;
252b5132 3467 }
29b0f896
AM		 3468 /* We should find the immediate. */
3469 if (n1 == i.operands)
3470 abort ();
3471 i.op[n].disps->X_add_number -= imm_size;
3472 }
520dc8e8 3473
29b0f896
AM		 3474 if (i.types[n] & Disp32S)
3475 sign = 1;
3e73aa7c 3476
29b0f896
AM		 3477 if (i.types[n] & (Disp16 | Disp64))
3478 {
3479 size = 2;
3480 if (i.types[n] & Disp64)
3481 size = 8;
3482 }
520dc8e8 3483
29b0f896 3484 p = frag_more (size);
2bbd9c25 3485 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
2bbd9c25
JJ		 3486 if (reloc_type == BFD_RELOC_32
3487 && GOT_symbol
3488 && GOT_symbol == i.op[n].disps->X_add_symbol
3489 && (i.op[n].disps->X_op == O_symbol
3490 || (i.op[n].disps->X_op == O_add
3491 && ((symbol_get_value_expression
3492 (i.op[n].disps->X_op_symbol)->X_op)
3493 == O_subtract))))
3494 {
3495 offsetT add;
3496
3497 if (insn_start_frag == frag_now)
3498 add = (p - frag_now->fr_literal) - insn_start_off;
3499 else
3500 {
3501 fragS *fr;
3502
3503 add = insn_start_frag->fr_fix - insn_start_off;
3504 for (fr = insn_start_frag->fr_next;
3505 fr && fr != frag_now; fr = fr->fr_next)
3506 add += fr->fr_fix;
3507 add += p - frag_now->fr_literal;
3508 }
3509
3510 /* We don't support dynamic linking on x86-64 yet. */
3511 if (flag_code == CODE_64BIT)
3512 abort ();
3513 reloc_type = BFD_RELOC_386_GOTPC;
3514 i.op[n].disps->X_add_number += add;
3515 }
062cd5e7 3516 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3517 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3518 }
3519 }
3520 }
3521}
252b5132 3522
29b0f896 3523static void
2bbd9c25
JJ		 3524output_imm (insn_start_frag, insn_start_off)
3525 fragS *insn_start_frag;
3526 offsetT insn_start_off;
29b0f896
AM		 3527{
3528 char *p;
3529 unsigned int n;
252b5132 3530
29b0f896
AM		 3531 for (n = 0; n < i.operands; n++)
3532 {
3533 if (i.types[n] & Imm)
3534 {
3535 if (i.op[n].imms->X_op == O_constant)
3536 {
3537 int size;
3538 offsetT val;
b4cac588 3539
29b0f896
AM		 3540 size = 4;
3541 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3542 {
3543 size = 2;
3544 if (i.types[n] & (Imm8 | Imm8S))
3545 size = 1;
3546 else if (i.types[n] & Imm64)
3547 size = 8;
3548 }
3549 val = offset_in_range (i.op[n].imms->X_add_number,
3550 size);
3551 p = frag_more (size);
3552 md_number_to_chars (p, val, size);
3553 }
3554 else
3555 {
3556 /* Not absolute_section.
3557 Need a 32-bit fixup (don't support 8bit
3558 non-absolute imms). Try to support other
3559 sizes ... */
f86103b7 3560 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3561 int size = 4;
3562 int sign = 0;
3563
3564 if ((i.types[n] & (Imm32S))
a7d61044
JB		 3565 && (i.suffix == QWORD_MNEM_SUFFIX
3566 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 3567 sign = 1;
3568 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3569 {
3570 size = 2;
3571 if (i.types[n] & (Imm8 | Imm8S))
3572 size = 1;
3573 if (i.types[n] & Imm64)
3574 size = 8;
3575 }
520dc8e8 3576
29b0f896
AM		 3577 p = frag_more (size);
3578 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 3579
2bbd9c25
JJ		 3580 /* This is tough to explain. We end up with this one if we
3581 * have operands that look like
3582 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3583 * obtain the absolute address of the GOT, and it is strongly
3584 * preferable from a performance point of view to avoid using
3585 * a runtime relocation for this. The actual sequence of
3586 * instructions often look something like:
3587 *
3588 * call .L66
3589 * .L66:
3590 * popl %ebx
3591 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3592 *
3593 * The call and pop essentially return the absolute address
3594 * of the label .L66 and store it in %ebx. The linker itself
3595 * will ultimately change the first operand of the addl so
3596 * that %ebx points to the GOT, but to keep things simple, the
3597 * .o file must have this operand set so that it generates not
3598 * the absolute address of .L66, but the absolute address of
3599 * itself. This allows the linker itself simply treat a GOTPC
3600 * relocation as asking for a pcrel offset to the GOT to be
3601 * added in, and the addend of the relocation is stored in the
3602 * operand field for the instruction itself.
3603 *
3604 * Our job here is to fix the operand so that it would add
3605 * the correct offset so that %ebx would point to itself. The
3606 * thing that is tricky is that .-.L66 will point to the
3607 * beginning of the instruction, so we need to further modify
3608 * the operand so that it will point to itself. There are
3609 * other cases where you have something like:
3610 *
3611 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3612 *
3613 * and here no correction would be required. Internally in
3614 * the assembler we treat operands of this form as not being
3615 * pcrel since the '.' is explicitly mentioned, and I wonder
3616 * whether it would simplify matters to do it this way. Who
3617 * knows. In earlier versions of the PIC patches, the
3618 * pcrel_adjust field was used to store the correction, but
3619 * since the expression is not pcrel, I felt it would be
3620 * confusing to do it this way. */
3621
29b0f896
AM		 3622 if (reloc_type == BFD_RELOC_32
3623 && GOT_symbol
3624 && GOT_symbol == i.op[n].imms->X_add_symbol
3625 && (i.op[n].imms->X_op == O_symbol
3626 || (i.op[n].imms->X_op == O_add
3627 && ((symbol_get_value_expression
3628 (i.op[n].imms->X_op_symbol)->X_op)
3629 == O_subtract))))
3630 {
2bbd9c25
JJ		 3631 offsetT add;
3632
3633 if (insn_start_frag == frag_now)
3634 add = (p - frag_now->fr_literal) - insn_start_off;
3635 else
3636 {
3637 fragS *fr;
3638
3639 add = insn_start_frag->fr_fix - insn_start_off;
3640 for (fr = insn_start_frag->fr_next;
3641 fr && fr != frag_now; fr = fr->fr_next)
3642 add += fr->fr_fix;
3643 add += p - frag_now->fr_literal;
3644 }
3645
29b0f896
AM		 3646 /* We don't support dynamic linking on x86-64 yet. */
3647 if (flag_code == CODE_64BIT)
3648 abort ();
3649 reloc_type = BFD_RELOC_386_GOTPC;
2bbd9c25 3650 i.op[n].imms->X_add_number += add;
29b0f896 3651 }
29b0f896
AM		 3652 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3653 i.op[n].imms, 0, reloc_type);
3654 }
3655 }
3656 }
252b5132
RH		 3657}
3658\f
f3c180ae 3659#ifndef LEX_AT
f86103b7 3660static char *lex_got PARAMS ((enum bfd_reloc_code_real *, int *));
f3c180ae
AM		 3661
3662/* Parse operands of the form
3663 <symbol>@GOTOFF+<nnn>
3664 and similar .plt or .got references.
3665
3666 If we find one, set up the correct relocation in RELOC and copy the
3667 input string, minus the `@GOTOFF' into a malloc'd buffer for
3668 parsing by the calling routine. Return this buffer, and if ADJUST
3669 is non-null set it to the length of the string we removed from the
3670 input line. Otherwise return NULL. */
3671static char *
3672lex_got (reloc, adjust)
f86103b7 3673 enum bfd_reloc_code_real *reloc;
f3c180ae
AM		 3674 int *adjust;
3675{
3676 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3677 static const struct {
3678 const char *str;
f86103b7 3679 const enum bfd_reloc_code_real rel[NUM_FLAG_CODE];
f3c180ae 3680 } gotrel[] = {
13ae64f3
JJ		 3681 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3682 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3683 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
bffbf940 3684 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD } },
13ae64f3 3685 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
bffbf940
JJ		 3686 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD } },
3687 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF } },
3688 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 } },
13ae64f3 3689 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
bffbf940 3690 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } },
37e55690
JJ		 3691 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } },
3692 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } },
13ae64f3 3693 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
f3c180ae
AM		 3694 };
3695 char *cp;
3696 unsigned int j;
3697
3698 for (cp = input_line_pointer; *cp != '@'; cp++)
3699 if (is_end_of_line[(unsigned char) *cp])
3700 return NULL;
3701
3702 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3703 {
3704 int len;
3705
3706 len = strlen (gotrel[j].str);
28f81592 3707 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3708 {
3709 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3710 {
28f81592
AM		 3711 int first, second;
3712 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3713
3714 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3715 if (adjust)
3716 *adjust = len;
f3c180ae
AM		 3717
3718 if (GOT_symbol == NULL)
3719 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3720
3721 /* Replace the relocation token with ' ', so that
3722 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3723
3724 /* The length of the first part of our input line. */
f3c180ae 3725 first = cp - input_line_pointer;
28f81592
AM		 3726
3727 /* The second part goes from after the reloc token until
3728 (and including) an end_of_line char. Don't use strlen
3729 here as the end_of_line char may not be a NUL. */
3730 past_reloc = cp + 1 + len;
3731 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3732 ;
3733 second = cp - past_reloc;
3734
3735 /* Allocate and copy string. The trailing NUL shouldn't
3736 be necessary, but be safe. */
3737 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3738 memcpy (tmpbuf, input_line_pointer, first);
3739 tmpbuf[first] = ' ';
28f81592
AM		 3740 memcpy (tmpbuf + first + 1, past_reloc, second);
3741 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3742 return tmpbuf;
3743 }
3744
3745 as_bad (_("@%s reloc is not supported in %s bit mode"),
3746 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3747 return NULL;
3748 }
3749 }
3750
3751 /* Might be a symbol version string. Don't as_bad here. */
3752 return NULL;
3753}
3754
3755/* x86_cons_fix_new is called via the expression parsing code when a
3756 reloc is needed. We use this hook to get the correct .got reloc. */
f86103b7 3757static enum bfd_reloc_code_real got_reloc = NO_RELOC;
f3c180ae
AM		 3758
3759void
3760x86_cons_fix_new (frag, off, len, exp)
3761 fragS *frag;
3762 unsigned int off;
3763 unsigned int len;
3764 expressionS *exp;
3765{
f86103b7 3766 enum bfd_reloc_code_real r = reloc (len, 0, 0, got_reloc);
f3c180ae
AM		 3767 got_reloc = NO_RELOC;
3768 fix_new_exp (frag, off, len, exp, 0, r);
3769}
3770
3771void
3772x86_cons (exp, size)
3773 expressionS *exp;
3774 int size;
3775{
3776 if (size == 4)
3777 {
3778 /* Handle @GOTOFF and the like in an expression. */
3779 char *save;
3780 char *gotfree_input_line;
3781 int adjust;
3782
3783 save = input_line_pointer;
3784 gotfree_input_line = lex_got (&got_reloc, &adjust);
3785 if (gotfree_input_line)
3786 input_line_pointer = gotfree_input_line;
3787
3788 expression (exp);
3789
3790 if (gotfree_input_line)
3791 {
3792 /* expression () has merrily parsed up to the end of line,
3793 or a comma - in the wrong buffer. Transfer how far
3794 input_line_pointer has moved to the right buffer. */
3795 input_line_pointer = (save
3796 + (input_line_pointer - gotfree_input_line)
3797 + adjust);
3798 free (gotfree_input_line);
3799 }
3800 }
3801 else
3802 expression (exp);
3803}
3804#endif
3805
6482c264
NC		 3806#ifdef TE_PE
3807
6482c264
NC		 3808void
3809x86_pe_cons_fix_new (frag, off, len, exp)
3810 fragS *frag;
3811 unsigned int off;
3812 unsigned int len;
3813 expressionS *exp;
3814{
3815 enum bfd_reloc_code_real r = reloc (len, 0, 0, NO_RELOC);
3816
3817 if (exp->X_op == O_secrel)
3818 {
3819 exp->X_op = O_symbol;
3820 r = BFD_RELOC_32_SECREL;
3821 }
3822
3823 fix_new_exp (frag, off, len, exp, 0, r);
3824}
3825
3826static void
3827pe_directive_secrel (dummy)
3828 int dummy ATTRIBUTE_UNUSED;
3829{
3830 expressionS exp;
3831
3832 do
3833 {
3834 expression (&exp);
3835 if (exp.X_op == O_symbol)
3836 exp.X_op = O_secrel;
3837
3838 emit_expr (&exp, 4);
3839 }
3840 while (*input_line_pointer++ == ',');
3841
3842 input_line_pointer--;
3843 demand_empty_rest_of_line ();
3844}
3845
3846#endif
3847
252b5132
RH		 3848static int i386_immediate PARAMS ((char *));
3849
3850static int
3851i386_immediate (imm_start)
3852 char *imm_start;
3853{
3854 char *save_input_line_pointer;
f3c180ae
AM		 3855#ifndef LEX_AT
3856 char *gotfree_input_line;
3857#endif
252b5132 3858 segT exp_seg = 0;
47926f60 3859 expressionS *exp;
252b5132
RH		 3860
3861 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3862 {
d0b47220 3863 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3864 return 0;
3865 }
3866
3867 exp = &im_expressions[i.imm_operands++];
520dc8e8 3868 i.op[this_operand].imms = exp;
252b5132
RH		 3869
3870 if (is_space_char (*imm_start))
3871 ++imm_start;
3872
3873 save_input_line_pointer = input_line_pointer;
3874 input_line_pointer = imm_start;
3875
3876#ifndef LEX_AT
f3c180ae
AM		 3877 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3878 if (gotfree_input_line)
3879 input_line_pointer = gotfree_input_line;
252b5132
RH		 3880#endif
3881
3882 exp_seg = expression (exp);
3883
83183c0c 3884 SKIP_WHITESPACE ();
252b5132 3885 if (*input_line_pointer)
f3c180ae 3886 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3887
3888 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3889#ifndef LEX_AT
3890 if (gotfree_input_line)
3891 free (gotfree_input_line);
3892#endif
252b5132 3893
2daf4fd8 3894 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 3895 {
47926f60 3896 /* Missing or bad expr becomes absolute 0. */
d0b47220 3897 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 3898 imm_start);
252b5132
RH		 3899 exp->X_op = O_constant;
3900 exp->X_add_number = 0;
3901 exp->X_add_symbol = (symbolS *) 0;
3902 exp->X_op_symbol = (symbolS *) 0;
252b5132 3903 }
3e73aa7c 3904 else if (exp->X_op == O_constant)
252b5132 3905 {
47926f60 3906 /* Size it properly later. */
3e73aa7c
JH		 3907 i.types[this_operand] |= Imm64;
3908 /* If BFD64, sign extend val. */
3909 if (!use_rela_relocations)
3910 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3911 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 3912 }
4c63da97 3913#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 3914 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 3915 && exp_seg != absolute_section
47926f60 3916 && exp_seg != text_section
24eab124
AM		 3917 && exp_seg != data_section
3918 && exp_seg != bss_section
3919 && exp_seg != undefined_section
f86103b7 3920 && !bfd_is_com_section (exp_seg))
252b5132 3921 {
d0b47220 3922 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 3923 return 0;
3924 }
3925#endif
3926 else
3927 {
3928 /* This is an address. The size of the address will be
24eab124 3929 determined later, depending on destination register,
3e73aa7c
JH		 3930 suffix, or the default for the section. */
3931 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
252b5132
RH		 3932 }
3933
3934 return 1;
3935}
3936
551c1ca1 3937static char *i386_scale PARAMS ((char *));
252b5132 3938
551c1ca1 3939static char *
252b5132
RH		 3940i386_scale (scale)
3941 char *scale;
3942{
551c1ca1
AM		 3943 offsetT val;
3944 char *save = input_line_pointer;
252b5132 3945
551c1ca1
AM		 3946 input_line_pointer = scale;
3947 val = get_absolute_expression ();
3948
3949 switch (val)
252b5132 3950 {
551c1ca1 3951 case 1:
252b5132
RH		 3952 i.log2_scale_factor = 0;
3953 break;
551c1ca1 3954 case 2:
252b5132
RH		 3955 i.log2_scale_factor = 1;
3956 break;
551c1ca1 3957 case 4:
252b5132
RH		 3958 i.log2_scale_factor = 2;
3959 break;
551c1ca1 3960 case 8:
252b5132
RH		 3961 i.log2_scale_factor = 3;
3962 break;
3963 default:
a724f0f4
JB		 3964 {
3965 char sep = *input_line_pointer;
3966
3967 *input_line_pointer = '\0';
3968 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3969 scale);
3970 *input_line_pointer = sep;
3971 input_line_pointer = save;
3972 return NULL;
3973 }
252b5132 3974 }
29b0f896 3975 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 3976 {
3977 as_warn (_("scale factor of %d without an index register"),
24eab124 3978 1 << i.log2_scale_factor);
252b5132
RH		 3979#if SCALE1_WHEN_NO_INDEX
3980 i.log2_scale_factor = 0;
3981#endif
3982 }
551c1ca1
AM		 3983 scale = input_line_pointer;
3984 input_line_pointer = save;
3985 return scale;
252b5132
RH		 3986}
3987
3988static int i386_displacement PARAMS ((char *, char *));
3989
3990static int
3991i386_displacement (disp_start, disp_end)
3992 char *disp_start;
3993 char *disp_end;
3994{
29b0f896 3995 expressionS *exp;
252b5132
RH		 3996 segT exp_seg = 0;
3997 char *save_input_line_pointer;
f3c180ae
AM		 3998#ifndef LEX_AT
3999 char *gotfree_input_line;
4000#endif
252b5132
RH		 4001 int bigdisp = Disp32;
4002
3e73aa7c 4003 if (flag_code == CODE_64BIT)
7ecd2f8b 4004 {
29b0f896
AM		 4005 if (i.prefix[ADDR_PREFIX] == 0)
4006 bigdisp = Disp64;
7ecd2f8b
JH		 4007 }
4008 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4009 bigdisp = Disp16;
252b5132
RH		 4010 i.types[this_operand] |= bigdisp;
4011
4012 exp = &disp_expressions[i.disp_operands];
520dc8e8 4013 i.op[this_operand].disps = exp;
252b5132
RH		 4014 i.disp_operands++;
4015 save_input_line_pointer = input_line_pointer;
4016 input_line_pointer = disp_start;
4017 END_STRING_AND_SAVE (disp_end);
4018
4019#ifndef GCC_ASM_O_HACK
4020#define GCC_ASM_O_HACK 0
4021#endif
4022#if GCC_ASM_O_HACK
4023 END_STRING_AND_SAVE (disp_end + 1);
4024 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4025 && displacement_string_end[-1] == '+')
252b5132
RH		 4026 {
4027 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4028 constraint within gcc asm statements.
4029 For instance:
4030
4031 #define _set_tssldt_desc(n,addr,limit,type) \
4032 __asm__ __volatile__ ( \
4033 "movw %w2,%0\n\t" \
4034 "movw %w1,2+%0\n\t" \
4035 "rorl $16,%1\n\t" \
4036 "movb %b1,4+%0\n\t" \
4037 "movb %4,5+%0\n\t" \
4038 "movb $0,6+%0\n\t" \
4039 "movb %h1,7+%0\n\t" \
4040 "rorl $16,%1" \
4041 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4042
4043 This works great except that the output assembler ends
4044 up looking a bit weird if it turns out that there is
4045 no offset. You end up producing code that looks like:
4046
4047 #APP
4048 movw $235,(%eax)
4049 movw %dx,2+(%eax)
4050 rorl $16,%edx
4051 movb %dl,4+(%eax)
4052 movb $137,5+(%eax)
4053 movb $0,6+(%eax)
4054 movb %dh,7+(%eax)
4055 rorl $16,%edx
4056 #NO_APP
4057
47926f60 4058 So here we provide the missing zero. */
24eab124
AM		 4059
4060 *displacement_string_end = '0';
252b5132
RH		 4061 }
4062#endif
4063#ifndef LEX_AT
f3c180ae
AM		 4064 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
4065 if (gotfree_input_line)
4066 input_line_pointer = gotfree_input_line;
252b5132
RH		 4067#endif
4068
24eab124 4069 exp_seg = expression (exp);
252b5132 4070
636c26b0
AM		 4071 SKIP_WHITESPACE ();
4072 if (*input_line_pointer)
4073 as_bad (_("junk `%s' after expression"), input_line_pointer);
4074#if GCC_ASM_O_HACK
4075 RESTORE_END_STRING (disp_end + 1);
4076#endif
4077 RESTORE_END_STRING (disp_end);
4078 input_line_pointer = save_input_line_pointer;
4079#ifndef LEX_AT
4080 if (gotfree_input_line)
4081 free (gotfree_input_line);
4082#endif
4083
24eab124
AM		 4084 /* We do this to make sure that the section symbol is in
4085 the symbol table. We will ultimately change the relocation
47926f60 4086 to be relative to the beginning of the section. */
1ae12ab7
AM		 4087 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4088 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
24eab124 4089 {
636c26b0
AM		 4090 if (exp->X_op != O_symbol)
4091 {
4092 as_bad (_("bad expression used with @%s"),
4093 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4094 ? "GOTPCREL"
4095 : "GOTOFF"));
4096 return 0;
4097 }
4098
e5cb08ac 4099 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4100 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4101 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4102 exp->X_op = O_subtract;
4103 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4104 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4105 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
23df1078 4106 else
29b0f896 4107 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4108 }
252b5132 4109
2daf4fd8
AM		 4110 if (exp->X_op == O_absent || exp->X_op == O_big)
4111 {
47926f60 4112 /* Missing or bad expr becomes absolute 0. */
d0b47220 4113 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4114 disp_start);
4115 exp->X_op = O_constant;
4116 exp->X_add_number = 0;
4117 exp->X_add_symbol = (symbolS *) 0;
4118 exp->X_op_symbol = (symbolS *) 0;
4119 }
4120
4c63da97 4121#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4122 if (exp->X_op != O_constant
45288df1 4123 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4124 && exp_seg != absolute_section
45288df1
AM		 4125 && exp_seg != text_section
4126 && exp_seg != data_section
4127 && exp_seg != bss_section
31312f95 4128 && exp_seg != undefined_section
f86103b7 4129 && !bfd_is_com_section (exp_seg))
24eab124 4130 {
d0b47220 4131 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4132 return 0;
4133 }
252b5132 4134#endif
3e73aa7c
JH		 4135 else if (flag_code == CODE_64BIT)
4136 i.types[this_operand] |= Disp32S | Disp32;
252b5132
RH		 4137 return 1;
4138}
4139
e5cb08ac 4140static int i386_index_check PARAMS ((const char *));
252b5132 4141
eecb386c 4142/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4143 Return 1 on success, 0 on a failure. */
4144
252b5132 4145static int
eecb386c
AM		 4146i386_index_check (operand_string)
4147 const char *operand_string;
252b5132 4148{
3e73aa7c 4149 int ok;
24eab124 4150#if INFER_ADDR_PREFIX
eecb386c
AM		 4151 int fudged = 0;
4152
24eab124
AM		 4153 tryprefix:
4154#endif
3e73aa7c 4155 ok = 1;
20f0a1fc
NC		 4156 if (flag_code == CODE_64BIT)
4157 {
4158 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4159
4160 if ((i.base_reg
4161 && ((i.base_reg->reg_type & RegXX) == 0)
4162 && (i.base_reg->reg_type != BaseIndex
4163 || i.index_reg))
4164 || (i.index_reg
4165 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4166 != (RegXX | BaseIndex))))
4167 ok = 0;
3e73aa7c
JH		 4168 }
4169 else
4170 {
4171 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4172 {
4173 /* 16bit checks. */
4174 if ((i.base_reg
29b0f896
AM		 4175 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4176 != (Reg16 | BaseIndex)))
3e73aa7c 4177 || (i.index_reg
29b0f896
AM		 4178 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4179 != (Reg16 | BaseIndex))
4180 || !(i.base_reg
4181 && i.base_reg->reg_num < 6
4182 && i.index_reg->reg_num >= 6
4183 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4184 ok = 0;
4185 }
4186 else
e5cb08ac 4187 {
3e73aa7c
JH		 4188 /* 32bit checks. */
4189 if ((i.base_reg
4190 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4191 || (i.index_reg
29b0f896
AM		 4192 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4193 != (Reg32 | BaseIndex))))
e5cb08ac 4194 ok = 0;
3e73aa7c
JH		 4195 }
4196 }
4197 if (!ok)
24eab124
AM		 4198 {
4199#if INFER_ADDR_PREFIX
20f0a1fc 4200 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4201 {
4202 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4203 i.prefixes += 1;
b23bac36
AM		 4204 /* Change the size of any displacement too. At most one of
4205 Disp16 or Disp32 is set.
4206 FIXME. There doesn't seem to be any real need for separate
4207 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4208 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4209 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
29b0f896 4210 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4211 fudged = 1;
24eab124
AM		 4212 goto tryprefix;
4213 }
eecb386c
AM		 4214 if (fudged)
4215 as_bad (_("`%s' is not a valid base/index expression"),
4216 operand_string);
4217 else
c388dee8 4218#endif
eecb386c
AM		 4219 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4220 operand_string,
3e73aa7c 4221 flag_code_names[flag_code]);
24eab124 4222 }
20f0a1fc 4223 return ok;
24eab124 4224}
252b5132 4225
252b5132 4226/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4227 on error. */
252b5132 4228
252b5132
RH		 4229static int
4230i386_operand (operand_string)
4231 char *operand_string;
4232{
af6bdddf
AM		 4233 const reg_entry *r;
4234 char *end_op;
24eab124 4235 char *op_string = operand_string;
252b5132 4236
24eab124 4237 if (is_space_char (*op_string))
252b5132
RH		 4238 ++op_string;
4239
24eab124 4240 /* We check for an absolute prefix (differentiating,
47926f60 4241 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4242 if (*op_string == ABSOLUTE_PREFIX)
4243 {
4244 ++op_string;
4245 if (is_space_char (*op_string))
4246 ++op_string;
4247 i.types[this_operand] |= JumpAbsolute;
4248 }
252b5132 4249
47926f60 4250 /* Check if operand is a register. */
af6bdddf
AM		 4251 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4252 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 4253 {
24eab124
AM		 4254 /* Check for a segment override by searching for ':' after a
4255 segment register. */
4256 op_string = end_op;
4257 if (is_space_char (*op_string))
4258 ++op_string;
4259 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4260 {
4261 switch (r->reg_num)
4262 {
4263 case 0:
4264 i.seg[i.mem_operands] = &es;
4265 break;
4266 case 1:
4267 i.seg[i.mem_operands] = &cs;
4268 break;
4269 case 2:
4270 i.seg[i.mem_operands] = &ss;
4271 break;
4272 case 3:
4273 i.seg[i.mem_operands] = &ds;
4274 break;
4275 case 4:
4276 i.seg[i.mem_operands] = &fs;
4277 break;
4278 case 5:
4279 i.seg[i.mem_operands] = &gs;
4280 break;
4281 }
252b5132 4282
24eab124 4283 /* Skip the ':' and whitespace. */
252b5132
RH		 4284 ++op_string;
4285 if (is_space_char (*op_string))
24eab124 4286 ++op_string;
252b5132 4287
24eab124
AM		 4288 if (!is_digit_char (*op_string)
4289 && !is_identifier_char (*op_string)
4290 && *op_string != '('
4291 && *op_string != ABSOLUTE_PREFIX)
4292 {
4293 as_bad (_("bad memory operand `%s'"), op_string);
4294 return 0;
4295 }
47926f60 4296 /* Handle case of %es:*foo. */
24eab124
AM		 4297 if (*op_string == ABSOLUTE_PREFIX)
4298 {
4299 ++op_string;
4300 if (is_space_char (*op_string))
4301 ++op_string;
4302 i.types[this_operand] |= JumpAbsolute;
4303 }
4304 goto do_memory_reference;
4305 }
4306 if (*op_string)
4307 {
d0b47220 4308 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4309 return 0;
4310 }
4311 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4312 i.op[this_operand].regs = r;
24eab124
AM		 4313 i.reg_operands++;
4314 }
af6bdddf
AM		 4315 else if (*op_string == REGISTER_PREFIX)
4316 {
4317 as_bad (_("bad register name `%s'"), op_string);
4318 return 0;
4319 }
24eab124 4320 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4321 {
24eab124
AM		 4322 ++op_string;
4323 if (i.types[this_operand] & JumpAbsolute)
4324 {
d0b47220 4325 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4326 return 0;
4327 }
4328 if (!i386_immediate (op_string))
4329 return 0;
4330 }
4331 else if (is_digit_char (*op_string)
4332 || is_identifier_char (*op_string)
e5cb08ac 4333 || *op_string == '(')
24eab124 4334 {
47926f60 4335 /* This is a memory reference of some sort. */
af6bdddf 4336 char *base_string;
252b5132 4337
47926f60 4338 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4339 char *displacement_string_start;
4340 char *displacement_string_end;
252b5132 4341
24eab124 4342 do_memory_reference:
24eab124
AM		 4343 if ((i.mem_operands == 1
4344 && (current_templates->start->opcode_modifier & IsString) == 0)
4345 || i.mem_operands == 2)
4346 {
4347 as_bad (_("too many memory references for `%s'"),
4348 current_templates->start->name);
4349 return 0;
4350 }
252b5132 4351
24eab124
AM		 4352 /* Check for base index form. We detect the base index form by
4353 looking for an ')' at the end of the operand, searching
4354 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4355 after the '('. */
af6bdddf 4356 base_string = op_string + strlen (op_string);
c3332e24 4357
af6bdddf
AM		 4358 --base_string;
4359 if (is_space_char (*base_string))
4360 --base_string;
252b5132 4361
47926f60 4362 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4363 displacement_string_start = op_string;
4364 displacement_string_end = base_string + 1;
252b5132 4365
24eab124
AM		 4366 if (*base_string == ')')
4367 {
af6bdddf 4368 char *temp_string;
24eab124
AM		 4369 unsigned int parens_balanced = 1;
4370 /* We've already checked that the number of left & right ()'s are
47926f60 4371 equal, so this loop will not be infinite. */
24eab124
AM		 4372 do
4373 {
4374 base_string--;
4375 if (*base_string == ')')
4376 parens_balanced++;
4377 if (*base_string == '(')
4378 parens_balanced--;
4379 }
4380 while (parens_balanced);
c3332e24 4381
af6bdddf 4382 temp_string = base_string;
c3332e24 4383
24eab124 4384 /* Skip past '(' and whitespace. */
252b5132
RH		 4385 ++base_string;
4386 if (is_space_char (*base_string))
24eab124 4387 ++base_string;
252b5132 4388
af6bdddf
AM		 4389 if (*base_string == ','
4390 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4391 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4392 {
af6bdddf 4393 displacement_string_end = temp_string;
252b5132 4394
af6bdddf 4395 i.types[this_operand] |= BaseIndex;
252b5132 4396
af6bdddf 4397 if (i.base_reg)
24eab124 4398 {
24eab124
AM		 4399 base_string = end_op;
4400 if (is_space_char (*base_string))
4401 ++base_string;
af6bdddf
AM		 4402 }
4403
4404 /* There may be an index reg or scale factor here. */
4405 if (*base_string == ',')
4406 {
4407 ++base_string;
4408 if (is_space_char (*base_string))
4409 ++base_string;
4410
4411 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4412 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4413 {
af6bdddf 4414 base_string = end_op;
24eab124
AM		 4415 if (is_space_char (*base_string))
4416 ++base_string;
af6bdddf
AM		 4417 if (*base_string == ',')
4418 {
4419 ++base_string;
4420 if (is_space_char (*base_string))
4421 ++base_string;
4422 }
e5cb08ac 4423 else if (*base_string != ')')
af6bdddf
AM		 4424 {
4425 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4426 operand_string);
4427 return 0;
4428 }
24eab124 4429 }
af6bdddf 4430 else if (*base_string == REGISTER_PREFIX)
24eab124 4431 {
af6bdddf 4432 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4433 return 0;
4434 }
252b5132 4435
47926f60 4436 /* Check for scale factor. */
551c1ca1 4437 if (*base_string != ')')
af6bdddf 4438 {
551c1ca1
AM		 4439 char *end_scale = i386_scale (base_string);
4440
4441 if (!end_scale)
af6bdddf 4442 return 0;
24eab124 4443
551c1ca1 4444 base_string = end_scale;
af6bdddf
AM		 4445 if (is_space_char (*base_string))
4446 ++base_string;
4447 if (*base_string != ')')
4448 {
4449 as_bad (_("expecting `)' after scale factor in `%s'"),
4450 operand_string);
4451 return 0;
4452 }
4453 }
4454 else if (!i.index_reg)
24eab124 4455 {
af6bdddf
AM		 4456 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4457 *base_string);
24eab124
AM		 4458 return 0;
4459 }
4460 }
af6bdddf 4461 else if (*base_string != ')')
24eab124 4462 {
af6bdddf
AM		 4463 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4464 operand_string);
24eab124
AM		 4465 return 0;
4466 }
c3332e24 4467 }
af6bdddf 4468 else if (*base_string == REGISTER_PREFIX)
c3332e24 4469 {
af6bdddf 4470 as_bad (_("bad register name `%s'"), base_string);
24eab124 4471 return 0;
c3332e24 4472 }
24eab124
AM		 4473 }
4474
4475 /* If there's an expression beginning the operand, parse it,
4476 assuming displacement_string_start and
4477 displacement_string_end are meaningful. */
4478 if (displacement_string_start != displacement_string_end)
4479 {
4480 if (!i386_displacement (displacement_string_start,
4481 displacement_string_end))
4482 return 0;
4483 }
4484
4485 /* Special case for (%dx) while doing input/output op. */
4486 if (i.base_reg
4487 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4488 && i.index_reg == 0
4489 && i.log2_scale_factor == 0
4490 && i.seg[i.mem_operands] == 0
4491 && (i.types[this_operand] & Disp) == 0)
4492 {
4493 i.types[this_operand] = InOutPortReg;
4494 return 1;
4495 }
4496
eecb386c
AM		 4497 if (i386_index_check (operand_string) == 0)
4498 return 0;
24eab124
AM		 4499 i.mem_operands++;
4500 }
4501 else
ce8a8b2f
AM		 4502 {
4503 /* It's not a memory operand; argh! */
24eab124
AM		 4504 as_bad (_("invalid char %s beginning operand %d `%s'"),
4505 output_invalid (*op_string),
4506 this_operand + 1,
4507 op_string);
4508 return 0;
4509 }
47926f60 4510 return 1; /* Normal return. */
252b5132
RH		 4511}
4512\f
ee7fcc42
AM		 4513/* md_estimate_size_before_relax()
4514
4515 Called just before relax() for rs_machine_dependent frags. The x86
4516 assembler uses these frags to handle variable size jump
4517 instructions.
4518
4519 Any symbol that is now undefined will not become defined.
4520 Return the correct fr_subtype in the frag.
4521 Return the initial "guess for variable size of frag" to caller.
4522 The guess is actually the growth beyond the fixed part. Whatever
4523 we do to grow the fixed or variable part contributes to our
4524 returned value. */
4525
252b5132
RH		 4526int
4527md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4528 fragS *fragP;
4529 segT segment;
252b5132 4530{
252b5132 4531 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4532 check for un-relaxable symbols. On an ELF system, we can't relax
4533 an externally visible symbol, because it may be overridden by a
4534 shared library. */
4535 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4536#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 4537 || (OUTPUT_FLAVOR == bfd_target_elf_flavour
4538 && (S_IS_EXTERNAL (fragP->fr_symbol)
4539 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4540#endif
4541 )
252b5132 4542 {
b98ef147
AM		 4543 /* Symbol is undefined in this segment, or we need to keep a
4544 reloc so that weak symbols can be overridden. */
4545 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 4546 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 4547 unsigned char *opcode;
4548 int old_fr_fix;
f6af82bd 4549
ee7fcc42
AM		 4550 if (fragP->fr_var != NO_RELOC)
4551 reloc_type = fragP->fr_var;
b98ef147 4552 else if (size == 2)
f6af82bd
AM		 4553 reloc_type = BFD_RELOC_16_PCREL;
4554 else
4555 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4556
ee7fcc42
AM		 4557 old_fr_fix = fragP->fr_fix;
4558 opcode = (unsigned char *) fragP->fr_opcode;
4559
fddf5b5b 4560 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4561 {
fddf5b5b
AM		 4562 case UNCOND_JUMP:
4563 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4564 opcode[0] = 0xe9;
252b5132 4565 fragP->fr_fix += size;
062cd5e7
AS		 4566 fix_new (fragP, old_fr_fix, size,
4567 fragP->fr_symbol,
4568 fragP->fr_offset, 1,
4569 reloc_type);
252b5132
RH		 4570 break;
4571
fddf5b5b 4572 case COND_JUMP86:
412167cb
AM		 4573 if (size == 2
4574 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4575 {
4576 /* Negate the condition, and branch past an
4577 unconditional jump. */
4578 opcode[0] ^= 1;
4579 opcode[1] = 3;
4580 /* Insert an unconditional jump. */
4581 opcode[2] = 0xe9;
4582 /* We added two extra opcode bytes, and have a two byte
4583 offset. */
4584 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4585 fix_new (fragP, old_fr_fix + 2, 2,
4586 fragP->fr_symbol,
4587 fragP->fr_offset, 1,
4588 reloc_type);
fddf5b5b
AM		 4589 break;
4590 }
4591 /* Fall through. */
4592
4593 case COND_JUMP:
412167cb
AM		 4594 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4595 {
3e02c1cc
AM		 4596 fixS *fixP;
4597
412167cb 4598 fragP->fr_fix += 1;
3e02c1cc
AM		 4599 fixP = fix_new (fragP, old_fr_fix, 1,
4600 fragP->fr_symbol,
4601 fragP->fr_offset, 1,
4602 BFD_RELOC_8_PCREL);
4603 fixP->fx_signed = 1;
412167cb
AM		 4604 break;
4605 }
93c2a809 4606
24eab124 4607 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4608 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4609 opcode[1] = opcode[0] + 0x10;
f6af82bd 4610 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4611 /* We've added an opcode byte. */
4612 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4613 fix_new (fragP, old_fr_fix + 1, size,
4614 fragP->fr_symbol,
4615 fragP->fr_offset, 1,
4616 reloc_type);
252b5132 4617 break;
fddf5b5b
AM		 4618
4619 default:
4620 BAD_CASE (fragP->fr_subtype);
4621 break;
252b5132
RH		 4622 }
4623 frag_wane (fragP);
ee7fcc42 4624 return fragP->fr_fix - old_fr_fix;
252b5132 4625 }
93c2a809 4626
93c2a809
AM		 4627 /* Guess size depending on current relax state. Initially the relax
4628 state will correspond to a short jump and we return 1, because
4629 the variable part of the frag (the branch offset) is one byte
4630 long. However, we can relax a section more than once and in that
4631 case we must either set fr_subtype back to the unrelaxed state,
4632 or return the value for the appropriate branch. */
4633 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4634}
4635
47926f60
KH		 4636/* Called after relax() is finished.
4637
4638 In: Address of frag.
4639 fr_type == rs_machine_dependent.
4640 fr_subtype is what the address relaxed to.
4641
4642 Out: Any fixSs and constants are set up.
4643 Caller will turn frag into a ".space 0". */
4644
252b5132
RH		 4645void
4646md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4647 bfd *abfd ATTRIBUTE_UNUSED;
4648 segT sec ATTRIBUTE_UNUSED;
29b0f896 4649 fragS *fragP;
252b5132 4650{
29b0f896 4651 unsigned char *opcode;
252b5132 4652 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4653 offsetT target_address;
4654 offsetT opcode_address;
252b5132 4655 unsigned int extension = 0;
847f7ad4 4656 offsetT displacement_from_opcode_start;
252b5132
RH		 4657
4658 opcode = (unsigned char *) fragP->fr_opcode;
4659
47926f60 4660 /* Address we want to reach in file space. */
252b5132 4661 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4662
47926f60 4663 /* Address opcode resides at in file space. */
252b5132
RH		 4664 opcode_address = fragP->fr_address + fragP->fr_fix;
4665
47926f60 4666 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4667 displacement_from_opcode_start = target_address - opcode_address;
4668
fddf5b5b 4669 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4670 {
47926f60
KH		 4671 /* Don't have to change opcode. */
4672 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4673 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4674 }
4675 else
4676 {
4677 if (no_cond_jump_promotion
4678 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4679 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4680
fddf5b5b
AM		 4681 switch (fragP->fr_subtype)
4682 {
4683 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4684 extension = 4; /* 1 opcode + 4 displacement */
4685 opcode[0] = 0xe9;
4686 where_to_put_displacement = &opcode[1];
4687 break;
252b5132 4688
fddf5b5b
AM		 4689 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4690 extension = 2; /* 1 opcode + 2 displacement */
4691 opcode[0] = 0xe9;
4692 where_to_put_displacement = &opcode[1];
4693 break;
252b5132 4694
fddf5b5b
AM		 4695 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4696 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4697 extension = 5; /* 2 opcode + 4 displacement */
4698 opcode[1] = opcode[0] + 0x10;
4699 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4700 where_to_put_displacement = &opcode[2];
4701 break;
252b5132 4702
fddf5b5b
AM		 4703 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4704 extension = 3; /* 2 opcode + 2 displacement */
4705 opcode[1] = opcode[0] + 0x10;
4706 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4707 where_to_put_displacement = &opcode[2];
4708 break;
252b5132 4709
fddf5b5b
AM		 4710 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4711 extension = 4;
4712 opcode[0] ^= 1;
4713 opcode[1] = 3;
4714 opcode[2] = 0xe9;
4715 where_to_put_displacement = &opcode[3];
4716 break;
4717
4718 default:
4719 BAD_CASE (fragP->fr_subtype);
4720 break;
4721 }
252b5132 4722 }
fddf5b5b 4723
47926f60 4724 /* Now put displacement after opcode. */
252b5132
RH		 4725 md_number_to_chars ((char *) where_to_put_displacement,
4726 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4727 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4728 fragP->fr_fix += extension;
4729}
4730\f
47926f60
KH		 4731/* Size of byte displacement jmp. */
4732int md_short_jump_size = 2;
4733
4734/* Size of dword displacement jmp. */
4735int md_long_jump_size = 5;
252b5132 4736
47926f60
KH		 4737/* Size of relocation record. */
4738const int md_reloc_size = 8;
252b5132
RH		 4739
4740void
4741md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4742 char *ptr;
4743 addressT from_addr, to_addr;
ab9da554
ILT		 4744 fragS *frag ATTRIBUTE_UNUSED;
4745 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4746{
847f7ad4 4747 offsetT offset;
252b5132
RH		 4748
4749 offset = to_addr - (from_addr + 2);
47926f60
KH		 4750 /* Opcode for byte-disp jump. */
4751 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4752 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4753}
4754
4755void
4756md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4757 char *ptr;
4758 addressT from_addr, to_addr;
a38cf1db
AM		 4759 fragS *frag ATTRIBUTE_UNUSED;
4760 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4761{
847f7ad4 4762 offsetT offset;
252b5132 4763
a38cf1db
AM		 4764 offset = to_addr - (from_addr + 5);
4765 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4766 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4767}
4768\f
4769/* Apply a fixup (fixS) to segment data, once it has been determined
4770 by our caller that we have all the info we need to fix it up.
4771
4772 On the 386, immediates, displacements, and data pointers are all in
4773 the same (little-endian) format, so we don't need to care about which
4774 we are handling. */
4775
94f592af
NC		 4776void
4777md_apply_fix3 (fixP, valP, seg)
47926f60
KH		 4778 /* The fix we're to put in. */
4779 fixS *fixP;
47926f60 4780 /* Pointer to the value of the bits. */
c6682705 4781 valueT *valP;
47926f60
KH		 4782 /* Segment fix is from. */
4783 segT seg ATTRIBUTE_UNUSED;
252b5132 4784{
94f592af 4785 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4786 valueT value = *valP;
252b5132 4787
f86103b7 4788#if !defined (TE_Mach)
93382f6d
AM		 4789 if (fixP->fx_pcrel)
4790 {
4791 switch (fixP->fx_r_type)
4792 {
5865bb77
ILT		 4793 default:
4794 break;
4795
93382f6d 4796 case BFD_RELOC_32:
ae8887b5 4797 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 4798 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4799 break;
4800 case BFD_RELOC_16:
4801 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4802 break;
4803 case BFD_RELOC_8:
4804 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4805 break;
4806 }
4807 }
252b5132 4808
a161fe53 4809 if (fixP->fx_addsy != NULL
31312f95
AM		 4810 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
4811 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4812 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4813 && !use_rela_relocations)
252b5132 4814 {
31312f95
AM		 4815 /* This is a hack. There should be a better way to handle this.
4816 This covers for the fact that bfd_install_relocation will
4817 subtract the current location (for partial_inplace, PC relative
4818 relocations); see more below. */
252b5132
RH		 4819#ifndef OBJ_AOUT
4820 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4821#ifdef TE_PE
4822 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4823#endif
4824 )
4825 value += fixP->fx_where + fixP->fx_frag->fr_address;
4826#endif
4827#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2f66722d 4828 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132 4829 {
6539b54b 4830 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 4831
6539b54b 4832 if ((sym_seg == seg
2f66722d 4833 || (symbol_section_p (fixP->fx_addsy)
6539b54b 4834 && sym_seg != absolute_section))
ae6063d4 4835 && !generic_force_reloc (fixP))
2f66722d
AM		 4836 {
4837 /* Yes, we add the values in twice. This is because
6539b54b
AM		 4838 bfd_install_relocation subtracts them out again. I think
4839 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 4840 it. FIXME. */
4841 value += fixP->fx_where + fixP->fx_frag->fr_address;
4842 }
252b5132
RH		 4843 }
4844#endif
4845#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 4846 /* For some reason, the PE format does not store a
4847 section address offset for a PC relative symbol. */
4848 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
4849#if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4850 || S_IS_WEAK (fixP->fx_addsy)
4851#endif
4852 )
252b5132
RH		 4853 value += md_pcrel_from (fixP);
4854#endif
4855 }
4856
4857 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 4858 and we must not disappoint it. */
252b5132
RH		 4859#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4860 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4861 && fixP->fx_addsy)
47926f60
KH		 4862 switch (fixP->fx_r_type)
4863 {
4864 case BFD_RELOC_386_PLT32:
3e73aa7c 4865 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4866 /* Make the jump instruction point to the address of the operand. At
4867 runtime we merely add the offset to the actual PLT entry. */
4868 value = -4;
4869 break;
31312f95 4870
13ae64f3
JJ		 4871 case BFD_RELOC_386_TLS_GD:
4872 case BFD_RELOC_386_TLS_LDM:
13ae64f3 4873 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 4874 case BFD_RELOC_386_TLS_IE:
4875 case BFD_RELOC_386_TLS_GOTIE:
bffbf940
JJ		 4876 case BFD_RELOC_X86_64_TLSGD:
4877 case BFD_RELOC_X86_64_TLSLD:
4878 case BFD_RELOC_X86_64_GOTTPOFF:
00f7efb6
JJ		 4879 value = 0; /* Fully resolved at runtime. No addend. */
4880 /* Fallthrough */
4881 case BFD_RELOC_386_TLS_LE:
4882 case BFD_RELOC_386_TLS_LDO_32:
4883 case BFD_RELOC_386_TLS_LE_32:
4884 case BFD_RELOC_X86_64_DTPOFF32:
4885 case BFD_RELOC_X86_64_TPOFF32:
4886 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4887 break;
4888
4889 case BFD_RELOC_386_GOT32:
4890 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 4891 value = 0; /* Fully resolved at runtime. No addend. */
4892 break;
47926f60
KH		 4893
4894 case BFD_RELOC_VTABLE_INHERIT:
4895 case BFD_RELOC_VTABLE_ENTRY:
4896 fixP->fx_done = 0;
94f592af 4897 return;
47926f60
KH		 4898
4899 default:
4900 break;
4901 }
4902#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 4903 *valP = value;
f86103b7 4904#endif /* !defined (TE_Mach) */
3e73aa7c 4905
3e73aa7c 4906 /* Are we finished with this relocation now? */
c6682705 4907 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 4908 fixP->fx_done = 1;
4909 else if (use_rela_relocations)
4910 {
4911 fixP->fx_no_overflow = 1;
062cd5e7
AS		 4912 /* Remember value for tc_gen_reloc. */
4913 fixP->fx_addnumber = value;
3e73aa7c
JH		 4914 value = 0;
4915 }
f86103b7 4916
94f592af 4917 md_number_to_chars (p, value, fixP->fx_size);
252b5132 4918}
252b5132 4919\f
252b5132
RH		 4920#define MAX_LITTLENUMS 6
4921
47926f60
KH		 4922/* Turn the string pointed to by litP into a floating point constant
4923 of type TYPE, and emit the appropriate bytes. The number of
4924 LITTLENUMS emitted is stored in *SIZEP. An error message is
4925 returned, or NULL on OK. */
4926
252b5132
RH		 4927char *
4928md_atof (type, litP, sizeP)
2ab9b79e 4929 int type;
252b5132
RH		 4930 char *litP;
4931 int *sizeP;
4932{
4933 int prec;
4934 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4935 LITTLENUM_TYPE *wordP;
4936 char *t;
4937
4938 switch (type)
4939 {
4940 case 'f':
4941 case 'F':
4942 prec = 2;
4943 break;
4944
4945 case 'd':
4946 case 'D':
4947 prec = 4;
4948 break;
4949
4950 case 'x':
4951 case 'X':
4952 prec = 5;
4953 break;
4954
4955 default:
4956 *sizeP = 0;
4957 return _("Bad call to md_atof ()");
4958 }
4959 t = atof_ieee (input_line_pointer, type, words);
4960 if (t)
4961 input_line_pointer = t;
4962
4963 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4964 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4965 the bigendian 386. */
4966 for (wordP = words + prec - 1; prec--;)
4967 {
4968 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4969 litP += sizeof (LITTLENUM_TYPE);
4970 }
4971 return 0;
4972}
4973\f
87c245cc 4974static char output_invalid_buf[8];
252b5132 4975
252b5132
RH		 4976static char *
4977output_invalid (c)
4978 int c;
4979{
3882b010 4980 if (ISPRINT (c))
252b5132
RH		 4981 sprintf (output_invalid_buf, "'%c'", c);
4982 else
4983 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4984 return output_invalid_buf;
4985}
4986
af6bdddf 4987/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 4988
4989static const reg_entry *
4990parse_register (reg_string, end_op)
4991 char *reg_string;
4992 char **end_op;
4993{
af6bdddf
AM		 4994 char *s = reg_string;
4995 char *p;
252b5132
RH		 4996 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4997 const reg_entry *r;
4998
4999 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5000 if (*s == REGISTER_PREFIX)
5001 ++s;
5002
5003 if (is_space_char (*s))
5004 ++s;
5005
5006 p = reg_name_given;
af6bdddf 5007 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5008 {
5009 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5010 return (const reg_entry *) NULL;
5011 s++;
252b5132
RH		 5012 }
5013
6588847e
DN		 5014 /* For naked regs, make sure that we are not dealing with an identifier.
5015 This prevents confusing an identifier like `eax_var' with register
5016 `eax'. */
5017 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5018 return (const reg_entry *) NULL;
5019
af6bdddf 5020 *end_op = s;
252b5132
RH		 5021
5022 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5023
5f47d35b 5024 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5025 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5026 {
5f47d35b
AM		 5027 if (is_space_char (*s))
5028 ++s;
5029 if (*s == '(')
5030 {
af6bdddf 5031 ++s;
5f47d35b
AM		 5032 if (is_space_char (*s))
5033 ++s;
5034 if (*s >= '0' && *s <= '7')
5035 {
5036 r = &i386_float_regtab[*s - '0'];
af6bdddf 5037 ++s;
5f47d35b
AM		 5038 if (is_space_char (*s))
5039 ++s;
5040 if (*s == ')')
5041 {
5042 *end_op = s + 1;
5043 return r;
5044 }
5f47d35b 5045 }
47926f60 5046 /* We have "%st(" then garbage. */
5f47d35b
AM		 5047 return (const reg_entry *) NULL;
5048 }
5049 }
5050
1ae00879 5051 if (r != NULL
20f0a1fc 5052 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5053 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5054 && flag_code != CODE_64BIT)
20f0a1fc 5055 return (const reg_entry *) NULL;
1ae00879 5056
252b5132
RH		 5057 return r;
5058}
5059\f
4cc782b5 5060#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5061const char *md_shortopts = "kVQ:sqn";
252b5132 5062#else
12b55ccc 5063const char *md_shortopts = "qn";
252b5132 5064#endif
6e0b89ee 5065
252b5132 5066struct option md_longopts[] = {
3e73aa7c
JH		 5067#define OPTION_32 (OPTION_MD_BASE + 0)
5068 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 5069#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 5070#define OPTION_64 (OPTION_MD_BASE + 1)
5071 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5072#endif
252b5132
RH		 5073 {NULL, no_argument, NULL, 0}
5074};
5075size_t md_longopts_size = sizeof (md_longopts);
5076
5077int
5078md_parse_option (c, arg)
5079 int c;
ab9da554 5080 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 5081{
5082 switch (c)
5083 {
12b55ccc
L		 5084 case 'n':
5085 optimize_align_code = 0;
5086 break;
5087
a38cf1db
AM		 5088 case 'q':
5089 quiet_warnings = 1;
252b5132
RH		 5090 break;
5091
5092#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5093 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5094 should be emitted or not. FIXME: Not implemented. */
5095 case 'Q':
252b5132
RH		 5096 break;
5097
5098 /* -V: SVR4 argument to print version ID. */
5099 case 'V':
5100 print_version_id ();
5101 break;
5102
a38cf1db
AM		 5103 /* -k: Ignore for FreeBSD compatibility. */
5104 case 'k':
252b5132 5105 break;
4cc782b5
ILT		 5106
5107 case 's':
5108 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5109 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5110 break;
6e0b89ee 5111
3e73aa7c
JH		 5112 case OPTION_64:
5113 {
5114 const char **list, **l;
5115
3e73aa7c
JH		 5116 list = bfd_target_list ();
5117 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 5118 if (strcmp (*l, "elf64-x86-64") == 0)
5119 {
5120 default_arch = "x86_64";
5121 break;
5122 }
3e73aa7c 5123 if (*l == NULL)
6e0b89ee 5124 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5125 free (list);
5126 }
5127 break;
5128#endif
252b5132 5129
6e0b89ee
AM		 5130 case OPTION_32:
5131 default_arch = "i386";
5132 break;
5133
252b5132
RH		 5134 default:
5135 return 0;
5136 }
5137 return 1;
5138}
5139
5140void
5141md_show_usage (stream)
5142 FILE *stream;
5143{
4cc782b5
ILT		 5144#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5145 fprintf (stream, _("\
a38cf1db
AM		 5146 -Q ignored\n\
5147 -V print assembler version number\n\
5148 -k ignored\n\
12b55ccc 5149 -n Do not optimize code alignment\n\
a38cf1db
AM		 5150 -q quieten some warnings\n\
5151 -s ignored\n"));
5152#else
5153 fprintf (stream, _("\
12b55ccc 5154 -n Do not optimize code alignment\n\
a38cf1db 5155 -q quieten some warnings\n"));
4cc782b5 5156#endif
252b5132
RH		 5157}
5158
3e73aa7c
JH		 5159#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5160 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5161
5162/* Pick the target format to use. */
5163
47926f60 5164const char *
252b5132
RH		 5165i386_target_format ()
5166{
3e73aa7c
JH		 5167 if (!strcmp (default_arch, "x86_64"))
5168 set_code_flag (CODE_64BIT);
5169 else if (!strcmp (default_arch, "i386"))
5170 set_code_flag (CODE_32BIT);
5171 else
5172 as_fatal (_("Unknown architecture"));
252b5132
RH		 5173 switch (OUTPUT_FLAVOR)
5174 {
4c63da97
AM		 5175#ifdef OBJ_MAYBE_AOUT
5176 case bfd_target_aout_flavour:
47926f60 5177 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5178#endif
5179#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5180 case bfd_target_coff_flavour:
5181 return "coff-i386";
4c63da97 5182#endif
3e73aa7c 5183#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5184 case bfd_target_elf_flavour:
3e73aa7c 5185 {
e5cb08ac
KH		 5186 if (flag_code == CODE_64BIT)
5187 use_rela_relocations = 1;
4ada7262 5188 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5189 }
4c63da97 5190#endif
252b5132
RH		 5191 default:
5192 abort ();
5193 return NULL;
5194 }
5195}
5196
47926f60 5197#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5198
5199#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5200void i386_elf_emit_arch_note ()
5201{
5202 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
5203 && cpu_arch_name != NULL)
5204 {
5205 char *p;
5206 asection *seg = now_seg;
5207 subsegT subseg = now_subseg;
5208 Elf_Internal_Note i_note;
5209 Elf_External_Note e_note;
5210 asection *note_secp;
5211 int len;
5212
5213 /* Create the .note section. */
5214 note_secp = subseg_new (".note", 0);
5215 bfd_set_section_flags (stdoutput,
5216 note_secp,
5217 SEC_HAS_CONTENTS | SEC_READONLY);
5218
5219 /* Process the arch string. */
5220 len = strlen (cpu_arch_name);
5221
5222 i_note.namesz = len + 1;
5223 i_note.descsz = 0;
5224 i_note.type = NT_ARCH;
5225 p = frag_more (sizeof (e_note.namesz));
5226 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5227 p = frag_more (sizeof (e_note.descsz));
5228 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5229 p = frag_more (sizeof (e_note.type));
5230 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5231 p = frag_more (len + 1);
5232 strcpy (p, cpu_arch_name);
5233
5234 frag_align (2, 0, 0);
5235
5236 subseg_set (seg, subseg);
5237 }
5238}
5239#endif
252b5132 5240\f
252b5132
RH		 5241symbolS *
5242md_undefined_symbol (name)
5243 char *name;
5244{
18dc2407
ILT		 5245 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5246 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5247 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5248 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5249 {
5250 if (!GOT_symbol)
5251 {
5252 if (symbol_find (name))
5253 as_bad (_("GOT already in symbol table"));
5254 GOT_symbol = symbol_new (name, undefined_section,
5255 (valueT) 0, &zero_address_frag);
5256 };
5257 return GOT_symbol;
5258 }
252b5132
RH		 5259 return 0;
5260}
5261
5262/* Round up a section size to the appropriate boundary. */
47926f60 5263
252b5132
RH		 5264valueT
5265md_section_align (segment, size)
ab9da554 5266 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5267 valueT size;
5268{
4c63da97
AM		 5269#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5270 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5271 {
5272 /* For a.out, force the section size to be aligned. If we don't do
5273 this, BFD will align it for us, but it will not write out the
5274 final bytes of the section. This may be a bug in BFD, but it is
5275 easier to fix it here since that is how the other a.out targets
5276 work. */
5277 int align;
5278
5279 align = bfd_get_section_alignment (stdoutput, segment);
5280 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5281 }
252b5132
RH		 5282#endif
5283
5284 return size;
5285}
5286
5287/* On the i386, PC-relative offsets are relative to the start of the
5288 next instruction. That is, the address of the offset, plus its
5289 size, since the offset is always the last part of the insn. */
5290
5291long
5292md_pcrel_from (fixP)
5293 fixS *fixP;
5294{
5295 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5296}
5297
5298#ifndef I386COFF
5299
5300static void
5301s_bss (ignore)
ab9da554 5302 int ignore ATTRIBUTE_UNUSED;
252b5132 5303{
29b0f896 5304 int temp;
252b5132 5305
8a75718c
JB		 5306#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5307 if (IS_ELF)
5308 obj_elf_section_change_hook ();
5309#endif
252b5132
RH		 5310 temp = get_absolute_expression ();
5311 subseg_set (bss_section, (subsegT) temp);
5312 demand_empty_rest_of_line ();
5313}
5314
5315#endif
5316
252b5132
RH		 5317void
5318i386_validate_fix (fixp)
5319 fixS *fixp;
5320{
5321 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5322 {
3e73aa7c 5323 /* GOTOFF relocation are nonsense in 64bit mode. */
23df1078
JH		 5324 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5325 {
5326 if (flag_code != CODE_64BIT)
5327 abort ();
5328 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5329 }
5330 else
5331 {
5332 if (flag_code == CODE_64BIT)
5333 abort ();
5334 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5335 }
252b5132
RH		 5336 fixp->fx_subsy = 0;
5337 }
5338}
5339
252b5132
RH		 5340arelent *
5341tc_gen_reloc (section, fixp)
ab9da554 5342 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5343 fixS *fixp;
5344{
5345 arelent *rel;
5346 bfd_reloc_code_real_type code;
5347
5348 switch (fixp->fx_r_type)
5349 {
3e73aa7c
JH		 5350 case BFD_RELOC_X86_64_PLT32:
5351 case BFD_RELOC_X86_64_GOT32:
5352 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5353 case BFD_RELOC_386_PLT32:
5354 case BFD_RELOC_386_GOT32:
5355 case BFD_RELOC_386_GOTOFF:
5356 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5357 case BFD_RELOC_386_TLS_GD:
5358 case BFD_RELOC_386_TLS_LDM:
5359 case BFD_RELOC_386_TLS_LDO_32:
5360 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5361 case BFD_RELOC_386_TLS_IE:
5362 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5363 case BFD_RELOC_386_TLS_LE_32:
5364 case BFD_RELOC_386_TLS_LE:
bffbf940
JJ		 5365 case BFD_RELOC_X86_64_TLSGD:
5366 case BFD_RELOC_X86_64_TLSLD:
5367 case BFD_RELOC_X86_64_DTPOFF32:
5368 case BFD_RELOC_X86_64_GOTTPOFF:
5369 case BFD_RELOC_X86_64_TPOFF32:
252b5132
RH		 5370 case BFD_RELOC_RVA:
5371 case BFD_RELOC_VTABLE_ENTRY:
5372 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 5373#ifdef TE_PE
5374 case BFD_RELOC_32_SECREL:
5375#endif
252b5132
RH		 5376 code = fixp->fx_r_type;
5377 break;
dbbaec26
L		 5378 case BFD_RELOC_X86_64_32S:
5379 if (!fixp->fx_pcrel)
5380 {
5381 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5382 code = fixp->fx_r_type;
5383 break;
5384 }
252b5132 5385 default:
93382f6d 5386 if (fixp->fx_pcrel)
252b5132 5387 {
93382f6d
AM		 5388 switch (fixp->fx_size)
5389 {
5390 default:
b091f402
AM		 5391 as_bad_where (fixp->fx_file, fixp->fx_line,
5392 _("can not do %d byte pc-relative relocation"),
5393 fixp->fx_size);
93382f6d
AM		 5394 code = BFD_RELOC_32_PCREL;
5395 break;
5396 case 1: code = BFD_RELOC_8_PCREL; break;
5397 case 2: code = BFD_RELOC_16_PCREL; break;
5398 case 4: code = BFD_RELOC_32_PCREL; break;
5399 }
5400 }
5401 else
5402 {
5403 switch (fixp->fx_size)
5404 {
5405 default:
b091f402
AM		 5406 as_bad_where (fixp->fx_file, fixp->fx_line,
5407 _("can not do %d byte relocation"),
5408 fixp->fx_size);
93382f6d
AM		 5409 code = BFD_RELOC_32;
5410 break;
5411 case 1: code = BFD_RELOC_8; break;
5412 case 2: code = BFD_RELOC_16; break;
5413 case 4: code = BFD_RELOC_32; break;
937149dd 5414#ifdef BFD64
3e73aa7c 5415 case 8: code = BFD_RELOC_64; break;
937149dd 5416#endif
93382f6d 5417 }
252b5132
RH		 5418 }
5419 break;
5420 }
252b5132
RH		 5421
5422 if (code == BFD_RELOC_32
5423 && GOT_symbol
5424 && fixp->fx_addsy == GOT_symbol)
3e73aa7c
JH		 5425 {
5426 /* We don't support GOTPC on 64bit targets. */
5427 if (flag_code == CODE_64BIT)
bfb32b52 5428 abort ();
3e73aa7c
JH		 5429 code = BFD_RELOC_386_GOTPC;
5430 }
252b5132
RH		 5431
5432 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5433 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5434 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5435
5436 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 5437
3e73aa7c
JH		 5438 if (!use_rela_relocations)
5439 {
5440 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5441 vtable entry to be used in the relocation's section offset. */
5442 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5443 rel->address = fixp->fx_offset;
252b5132 5444
c6682705 5445 rel->addend = 0;
3e73aa7c
JH		 5446 }
5447 /* Use the rela in 64bit mode. */
252b5132 5448 else
3e73aa7c 5449 {
062cd5e7
AS		 5450 if (!fixp->fx_pcrel)
5451 rel->addend = fixp->fx_offset;
5452 else
5453 switch (code)
5454 {
5455 case BFD_RELOC_X86_64_PLT32:
5456 case BFD_RELOC_X86_64_GOT32:
5457 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5458 case BFD_RELOC_X86_64_TLSGD:
5459 case BFD_RELOC_X86_64_TLSLD:
5460 case BFD_RELOC_X86_64_GOTTPOFF:
062cd5e7
AS		 5461 rel->addend = fixp->fx_offset - fixp->fx_size;
5462 break;
5463 default:
5464 rel->addend = (section->vma
5465 - fixp->fx_size
5466 + fixp->fx_addnumber
5467 + md_pcrel_from (fixp));
5468 break;
5469 }
3e73aa7c
JH		 5470 }
5471
252b5132
RH		 5472 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5473 if (rel->howto == NULL)
5474 {
5475 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5476 _("cannot represent relocation type %s"),
252b5132
RH		 5477 bfd_get_reloc_code_name (code));
5478 /* Set howto to a garbage value so that we can keep going. */
5479 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5480 assert (rel->howto != NULL);
5481 }
5482
5483 return rel;
5484}
5485
64a0c779
DN		 5486\f
5487/* Parse operands using Intel syntax. This implements a recursive descent
5488 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5489 Programmer's Guide.
5490
5491 FIXME: We do not recognize the full operand grammar defined in the MASM
5492 documentation. In particular, all the structure/union and
5493 high-level macro operands are missing.
5494
5495 Uppercase words are terminals, lower case words are non-terminals.
5496 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5497 bars '|' denote choices. Most grammar productions are implemented in
5498 functions called 'intel_<production>'.
5499
5500 Initial production is 'expr'.
5501
9306ca4a 5502 addOp + | -
64a0c779
DN		 5503
5504 alpha [a-zA-Z]
5505
9306ca4a
JB		 5506 binOp & | AND | \| | OR | ^ | XOR
5507
64a0c779
DN		 5508 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5509
5510 constant digits [[ radixOverride ]]
5511
9306ca4a 5512 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 5513
5514 digits decdigit
b77a7acd
AJ		 5515 | digits decdigit
5516 | digits hexdigit
64a0c779
DN		 5517
5518 decdigit [0-9]
5519
9306ca4a
JB		 5520 e04 e04 addOp e05
5521 | e05
5522
5523 e05 e05 binOp e06
b77a7acd 5524 | e06
64a0c779
DN		 5525
5526 e06 e06 mulOp e09
b77a7acd 5527 | e09
64a0c779
DN		 5528
5529 e09 OFFSET e10
a724f0f4
JB		 5530 | SHORT e10
5531 | + e10
5532 | - e10
9306ca4a
JB		 5533 | ~ e10
5534 | NOT e10
64a0c779
DN		 5535 | e09 PTR e10
5536 | e09 : e10
5537 | e10
5538
5539 e10 e10 [ expr ]
b77a7acd 5540 | e11
64a0c779
DN		 5541
5542 e11 ( expr )
b77a7acd 5543 | [ expr ]
64a0c779
DN		 5544 | constant
5545 | dataType
5546 | id
5547 | $
5548 | register
5549
a724f0f4 5550 => expr expr cmpOp e04
9306ca4a 5551 | e04
64a0c779
DN		 5552
5553 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5554 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5555
5556 hexdigit a | b | c | d | e | f
b77a7acd 5557 | A | B | C | D | E | F
64a0c779
DN		 5558
5559 id alpha
b77a7acd 5560 | id alpha
64a0c779
DN		 5561 | id decdigit
5562
9306ca4a 5563 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 5564
5565 quote " | '
5566
5567 register specialRegister
b77a7acd 5568 | gpRegister
64a0c779
DN		 5569 | byteRegister
5570
5571 segmentRegister CS | DS | ES | FS | GS | SS
5572
9306ca4a 5573 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 5574 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5575 | TR3 | TR4 | TR5 | TR6 | TR7
5576
64a0c779
DN		 5577 We simplify the grammar in obvious places (e.g., register parsing is
5578 done by calling parse_register) and eliminate immediate left recursion
5579 to implement a recursive-descent parser.
5580
a724f0f4
JB		 5581 expr e04 expr'
5582
5583 expr' cmpOp e04 expr'
5584 | Empty
9306ca4a
JB		 5585
5586 e04 e05 e04'
5587
5588 e04' addOp e05 e04'
5589 | Empty
64a0c779
DN		 5590
5591 e05 e06 e05'
5592
9306ca4a 5593 e05' binOp e06 e05'
b77a7acd 5594 | Empty
64a0c779
DN		 5595
5596 e06 e09 e06'
5597
5598 e06' mulOp e09 e06'
b77a7acd 5599 | Empty
64a0c779
DN		 5600
5601 e09 OFFSET e10 e09'
a724f0f4
JB		 5602 | SHORT e10'
5603 | + e10'
5604 | - e10'
5605 | ~ e10'
5606 | NOT e10'
b77a7acd 5607 | e10 e09'
64a0c779
DN		 5608
5609 e09' PTR e10 e09'
b77a7acd 5610 | : e10 e09'
64a0c779
DN		 5611 | Empty
5612
5613 e10 e11 e10'
5614
5615 e10' [ expr ] e10'
b77a7acd 5616 | Empty
64a0c779
DN		 5617
5618 e11 ( expr )
b77a7acd 5619 | [ expr ]
64a0c779
DN		 5620 | BYTE
5621 | WORD
5622 | DWORD
9306ca4a 5623 | FWORD
64a0c779 5624 | QWORD
9306ca4a
JB		 5625 | TBYTE
5626 | OWORD
5627 | XMMWORD
64a0c779
DN		 5628 | .
5629 | $
5630 | register
5631 | id
5632 | constant */
5633
5634/* Parsing structure for the intel syntax parser. Used to implement the
5635 semantic actions for the operand grammar. */
5636struct intel_parser_s
5637 {
5638 char *op_string; /* The string being parsed. */
5639 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5640 int op_modifier; /* Operand modifier. */
64a0c779 5641 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 5642 int in_offset; /* >=1 if parsing operand of offset. */
5643 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 5644 const reg_entry *reg; /* Last register reference found. */
5645 char *disp; /* Displacement string being built. */
a724f0f4 5646 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 5647 };
5648
5649static struct intel_parser_s intel_parser;
5650
5651/* Token structure for parsing intel syntax. */
5652struct intel_token
5653 {
5654 int code; /* Token code. */
5655 const reg_entry *reg; /* Register entry for register tokens. */
5656 char *str; /* String representation. */
5657 };
5658
5659static struct intel_token cur_token, prev_token;
5660
50705ef4
AM		 5661/* Token codes for the intel parser. Since T_SHORT is already used
5662 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5663#define T_NIL -1
5664#define T_CONST 1
5665#define T_REG 2
5666#define T_BYTE 3
5667#define T_WORD 4
9306ca4a
JB		 5668#define T_DWORD 5
5669#define T_FWORD 6
5670#define T_QWORD 7
5671#define T_TBYTE 8
5672#define T_XMMWORD 9
50705ef4 5673#undef T_SHORT
9306ca4a
JB		 5674#define T_SHORT 10
5675#define T_OFFSET 11
5676#define T_PTR 12
5677#define T_ID 13
5678#define T_SHL 14
5679#define T_SHR 15
64a0c779
DN		 5680
5681/* Prototypes for intel parser functions. */
5682static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5683static void intel_get_token PARAMS ((void));
5684static void intel_putback_token PARAMS ((void));
5685static int intel_expr PARAMS ((void));
9306ca4a 5686static int intel_e04 PARAMS ((void));
cce0cbdc 5687static int intel_e05 PARAMS ((void));
cce0cbdc 5688static int intel_e06 PARAMS ((void));
cce0cbdc 5689static int intel_e09 PARAMS ((void));
a724f0f4 5690static int intel_bracket_expr PARAMS ((void));
cce0cbdc 5691static int intel_e10 PARAMS ((void));
cce0cbdc 5692static int intel_e11 PARAMS ((void));
64a0c779 5693
64a0c779
DN		 5694static int
5695i386_intel_operand (operand_string, got_a_float)
5696 char *operand_string;
5697 int got_a_float;
5698{
5699 int ret;
5700 char *p;
5701
a724f0f4
JB		 5702 p = intel_parser.op_string = xstrdup (operand_string);
5703 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
5704
5705 for (;;)
64a0c779 5706 {
a724f0f4
JB		 5707 /* Initialize token holders. */
5708 cur_token.code = prev_token.code = T_NIL;
5709 cur_token.reg = prev_token.reg = NULL;
5710 cur_token.str = prev_token.str = NULL;
5711
5712 /* Initialize parser structure. */
5713 intel_parser.got_a_float = got_a_float;
5714 intel_parser.op_modifier = 0;
5715 intel_parser.is_mem = 0;
5716 intel_parser.in_offset = 0;
5717 intel_parser.in_bracket = 0;
5718 intel_parser.reg = NULL;
5719 intel_parser.disp[0] = '\0';
5720 intel_parser.next_operand = NULL;
5721
5722 /* Read the first token and start the parser. */
5723 intel_get_token ();
5724 ret = intel_expr ();
5725
5726 if (!ret)
5727 break;
5728
9306ca4a
JB		 5729 if (cur_token.code != T_NIL)
5730 {
5731 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5732 current_templates->start->name, cur_token.str);
5733 ret = 0;
5734 }
64a0c779
DN		 5735 /* If we found a memory reference, hand it over to i386_displacement
5736 to fill in the rest of the operand fields. */
9306ca4a 5737 else if (intel_parser.is_mem)
64a0c779
DN		 5738 {
5739 if ((i.mem_operands == 1
5740 && (current_templates->start->opcode_modifier & IsString) == 0)
5741 || i.mem_operands == 2)
5742 {
5743 as_bad (_("too many memory references for '%s'"),
5744 current_templates->start->name);
5745 ret = 0;
5746 }
5747 else
5748 {
5749 char *s = intel_parser.disp;
5750 i.mem_operands++;
5751
a724f0f4
JB		 5752 if (!quiet_warnings && intel_parser.is_mem < 0)
5753 /* See the comments in intel_bracket_expr. */
5754 as_warn (_("Treating `%s' as memory reference"), operand_string);
5755
64a0c779
DN		 5756 /* Add the displacement expression. */
5757 if (*s != '\0')
a4622f40
AM		 5758 ret = i386_displacement (s, s + strlen (s));
5759 if (ret)
a724f0f4
JB		 5760 {
5761 /* Swap base and index in 16-bit memory operands like
5762 [si+bx]. Since i386_index_check is also used in AT&T
5763 mode we have to do that here. */
5764 if (i.base_reg
5765 && i.index_reg
5766 && (i.base_reg->reg_type & Reg16)
5767 && (i.index_reg->reg_type & Reg16)
5768 && i.base_reg->reg_num >= 6
5769 && i.index_reg->reg_num < 6)
5770 {
5771 const reg_entry *base = i.index_reg;
5772
5773 i.index_reg = i.base_reg;
5774 i.base_reg = base;
5775 }
5776 ret = i386_index_check (operand_string);
5777 }
64a0c779
DN		 5778 }
5779 }
5780
5781 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 5782 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 5783 || intel_parser.reg == NULL)
5784 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 5785
5786 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
5787 ret = 0;
5788 if (!ret || !intel_parser.next_operand)
5789 break;
5790 intel_parser.op_string = intel_parser.next_operand;
5791 this_operand = i.operands++;
64a0c779
DN		 5792 }
5793
5794 free (p);
5795 free (intel_parser.disp);
5796
5797 return ret;
5798}
5799
a724f0f4
JB		 5800#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5801
5802/* expr e04 expr'
5803
5804 expr' cmpOp e04 expr'
5805 | Empty */
64a0c779
DN		 5806static int
5807intel_expr ()
5808{
a724f0f4
JB		 5809 /* XXX Implement the comparison operators. */
5810 return intel_e04 ();
9306ca4a
JB		 5811}
5812
a724f0f4 5813/* e04 e05 e04'
9306ca4a 5814
a724f0f4 5815 e04' addOp e05 e04'
9306ca4a
JB		 5816 | Empty */
5817static int
5818intel_e04 ()
5819{
a724f0f4 5820 int nregs = -1;
9306ca4a 5821
a724f0f4 5822 for (;;)
9306ca4a 5823 {
a724f0f4
JB		 5824 if (!intel_e05())
5825 return 0;
9306ca4a 5826
a724f0f4
JB		 5827 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5828 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 5829
a724f0f4
JB		 5830 if (cur_token.code == '+')
5831 nregs = -1;
5832 else if (cur_token.code == '-')
5833 nregs = NUM_ADDRESS_REGS;
5834 else
5835 return 1;
64a0c779 5836
a724f0f4
JB		 5837 strcat (intel_parser.disp, cur_token.str);
5838 intel_match_token (cur_token.code);
5839 }
64a0c779
DN		 5840}
5841
64a0c779
DN		 5842/* e05 e06 e05'
5843
9306ca4a 5844 e05' binOp e06 e05'
64a0c779
DN		 5845 | Empty */
5846static int
5847intel_e05 ()
5848{
a724f0f4 5849 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 5850
a724f0f4 5851 for (;;)
64a0c779 5852 {
a724f0f4
JB		 5853 if (!intel_e06())
5854 return 0;
5855
5856 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
5857 {
5858 char str[2];
5859
5860 str[0] = cur_token.code;
5861 str[1] = 0;
5862 strcat (intel_parser.disp, str);
5863 }
5864 else
5865 break;
9306ca4a 5866
64a0c779
DN		 5867 intel_match_token (cur_token.code);
5868
a724f0f4
JB		 5869 if (nregs < 0)
5870 nregs = ~nregs;
64a0c779 5871 }
a724f0f4
JB		 5872 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5873 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
5874 return 1;
4a1805b1 5875}
64a0c779
DN		 5876
5877/* e06 e09 e06'
5878
5879 e06' mulOp e09 e06'
b77a7acd 5880 | Empty */
64a0c779
DN		 5881static int
5882intel_e06 ()
5883{
a724f0f4 5884 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 5885
a724f0f4 5886 for (;;)
64a0c779 5887 {
a724f0f4
JB		 5888 if (!intel_e09())
5889 return 0;
9306ca4a 5890
a724f0f4
JB		 5891 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
5892 {
5893 char str[2];
9306ca4a 5894
a724f0f4
JB		 5895 str[0] = cur_token.code;
5896 str[1] = 0;
5897 strcat (intel_parser.disp, str);
5898 }
5899 else if (cur_token.code == T_SHL)
5900 strcat (intel_parser.disp, "<<");
5901 else if (cur_token.code == T_SHR)
5902 strcat (intel_parser.disp, ">>");
5903 else
5904 break;
9306ca4a 5905
a724f0f4 5906 intel_match_token (cur_token.code);
64a0c779 5907
a724f0f4
JB		 5908 if (nregs < 0)
5909 nregs = ~nregs;
64a0c779 5910 }
a724f0f4
JB		 5911 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5912 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
5913 return 1;
64a0c779
DN		 5914}
5915
a724f0f4
JB		 5916/* e09 OFFSET e09
5917 | SHORT e09
5918 | + e09
5919 | - e09
5920 | ~ e09
5921 | NOT e09
9306ca4a
JB		 5922 | e10 e09'
5923
64a0c779 5924 e09' PTR e10 e09'
b77a7acd 5925 | : e10 e09'
64a0c779
DN		 5926 | Empty */
5927static int
5928intel_e09 ()
5929{
a724f0f4
JB		 5930 int nregs = ~NUM_ADDRESS_REGS;
5931 int in_offset = 0;
5932
5933 for (;;)
64a0c779 5934 {
a724f0f4
JB		 5935 /* Don't consume constants here. */
5936 if (cur_token.code == '+' || cur_token.code == '-')
5937 {
5938 /* Need to look one token ahead - if the next token
5939 is a constant, the current token is its sign. */
5940 int next_code;
5941
5942 intel_match_token (cur_token.code);
5943 next_code = cur_token.code;
5944 intel_putback_token ();
5945 if (next_code == T_CONST)
5946 break;
5947 }
5948
5949 /* e09 OFFSET e09 */
5950 if (cur_token.code == T_OFFSET)
5951 {
5952 if (!in_offset++)
5953 ++intel_parser.in_offset;
5954 }
5955
5956 /* e09 SHORT e09 */
5957 else if (cur_token.code == T_SHORT)
5958 intel_parser.op_modifier |= 1 << T_SHORT;
5959
5960 /* e09 + e09 */
5961 else if (cur_token.code == '+')
5962 strcat (intel_parser.disp, "+");
5963
5964 /* e09 - e09
5965 | ~ e09
5966 | NOT e09 */
5967 else if (cur_token.code == '-' || cur_token.code == '~')
5968 {
5969 char str[2];
64a0c779 5970
a724f0f4
JB		 5971 if (nregs < 0)
5972 nregs = ~nregs;
5973 str[0] = cur_token.code;
5974 str[1] = 0;
5975 strcat (intel_parser.disp, str);
5976 }
5977
5978 /* e09 e10 e09' */
5979 else
5980 break;
5981
5982 intel_match_token (cur_token.code);
64a0c779
DN		 5983 }
5984
a724f0f4 5985 for (;;)
9306ca4a 5986 {
a724f0f4
JB		 5987 if (!intel_e10 ())
5988 return 0;
9306ca4a 5989
a724f0f4
JB		 5990 /* e09' PTR e10 e09' */
5991 if (cur_token.code == T_PTR)
5992 {
5993 char suffix;
9306ca4a 5994
a724f0f4
JB		 5995 if (prev_token.code == T_BYTE)
5996 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 5997
a724f0f4
JB		 5998 else if (prev_token.code == T_WORD)
5999 {
6000 if (current_templates->start->name[0] == 'l'
6001 && current_templates->start->name[2] == 's'
6002 && current_templates->start->name[3] == 0)
6003 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6004 else if (intel_parser.got_a_float == 2) /* "fi..." */
6005 suffix = SHORT_MNEM_SUFFIX;
6006 else
6007 suffix = WORD_MNEM_SUFFIX;
6008 }
64a0c779 6009
a724f0f4
JB		 6010 else if (prev_token.code == T_DWORD)
6011 {
6012 if (current_templates->start->name[0] == 'l'
6013 && current_templates->start->name[2] == 's'
6014 && current_templates->start->name[3] == 0)
6015 suffix = WORD_MNEM_SUFFIX;
6016 else if (flag_code == CODE_16BIT
6017 && (current_templates->start->opcode_modifier
6018 & (Jump|JumpDword|JumpInterSegment)))
6019 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6020 else if (intel_parser.got_a_float == 1) /* "f..." */
6021 suffix = SHORT_MNEM_SUFFIX;
6022 else
6023 suffix = LONG_MNEM_SUFFIX;
6024 }
9306ca4a 6025
a724f0f4
JB		 6026 else if (prev_token.code == T_FWORD)
6027 {
6028 if (current_templates->start->name[0] == 'l'
6029 && current_templates->start->name[2] == 's'
6030 && current_templates->start->name[3] == 0)
6031 suffix = LONG_MNEM_SUFFIX;
6032 else if (!intel_parser.got_a_float)
6033 {
6034 if (flag_code == CODE_16BIT)
6035 add_prefix (DATA_PREFIX_OPCODE);
6036 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6037 }
6038 else
6039 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6040 }
64a0c779 6041
a724f0f4
JB		 6042 else if (prev_token.code == T_QWORD)
6043 {
6044 if (intel_parser.got_a_float == 1) /* "f..." */
6045 suffix = LONG_MNEM_SUFFIX;
6046 else
6047 suffix = QWORD_MNEM_SUFFIX;
6048 }
64a0c779 6049
a724f0f4
JB		 6050 else if (prev_token.code == T_TBYTE)
6051 {
6052 if (intel_parser.got_a_float == 1)
6053 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6054 else
6055 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6056 }
9306ca4a 6057
a724f0f4 6058 else if (prev_token.code == T_XMMWORD)
9306ca4a 6059 {
a724f0f4
JB		 6060 /* XXX ignored for now, but accepted since gcc uses it */
6061 suffix = 0;
9306ca4a 6062 }
64a0c779 6063
f16b83df 6064 else
a724f0f4
JB		 6065 {
6066 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6067 return 0;
6068 }
6069
6070 if (current_templates->start->base_opcode == 0x8d /* lea */)
6071 ;
6072 else if (!i.suffix)
6073 i.suffix = suffix;
6074 else if (i.suffix != suffix)
6075 {
6076 as_bad (_("Conflicting operand modifiers"));
6077 return 0;
6078 }
64a0c779 6079
9306ca4a
JB		 6080 }
6081
a724f0f4
JB		 6082 /* e09' : e10 e09' */
6083 else if (cur_token.code == ':')
9306ca4a 6084 {
a724f0f4
JB		 6085 if (prev_token.code != T_REG)
6086 {
6087 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6088 segment/group identifier (which we don't have), using comma
6089 as the operand separator there is even less consistent, since
6090 there all branches only have a single operand. */
6091 if (this_operand != 0
6092 || intel_parser.in_offset
6093 || intel_parser.in_bracket
6094 || (!(current_templates->start->opcode_modifier
6095 & (Jump|JumpDword|JumpInterSegment))
6096 && !(current_templates->start->operand_types[0]
6097 & JumpAbsolute)))
6098 return intel_match_token (T_NIL);
6099 /* Remember the start of the 2nd operand and terminate 1st
6100 operand here.
6101 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6102 another expression), but it gets at least the simplest case
6103 (a plain number or symbol on the left side) right. */
6104 intel_parser.next_operand = intel_parser.op_string;
6105 *--intel_parser.op_string = '\0';
6106 return intel_match_token (':');
6107 }
9306ca4a 6108 }
64a0c779 6109
a724f0f4 6110 /* e09' Empty */
64a0c779 6111 else
a724f0f4 6112 break;
64a0c779 6113
a724f0f4
JB		 6114 intel_match_token (cur_token.code);
6115
6116 }
6117
6118 if (in_offset)
6119 {
6120 --intel_parser.in_offset;
6121 if (nregs < 0)
6122 nregs = ~nregs;
6123 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 6124 {
a724f0f4 6125 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 6126 return 0;
6127 }
a724f0f4
JB		 6128 intel_parser.op_modifier |= 1 << T_OFFSET;
6129 }
9306ca4a 6130
a724f0f4
JB		 6131 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6132 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6133 return 1;
6134}
64a0c779 6135
a724f0f4
JB		 6136static int
6137intel_bracket_expr ()
6138{
6139 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6140 const char *start = intel_parser.op_string;
6141 int len;
6142
6143 if (i.op[this_operand].regs)
6144 return intel_match_token (T_NIL);
6145
6146 intel_match_token ('[');
6147
6148 /* Mark as a memory operand only if it's not already known to be an
6149 offset expression. If it's an offset expression, we need to keep
6150 the brace in. */
6151 if (!intel_parser.in_offset)
6152 {
6153 ++intel_parser.in_bracket;
6154 /* Unfortunately gas always diverged from MASM in a respect that can't
6155 be easily fixed without risking to break code sequences likely to be
6156 encountered (the testsuite even check for this): MASM doesn't consider
6157 an expression inside brackets unconditionally as a memory reference.
6158 When that is e.g. a constant, an offset expression, or the sum of the
6159 two, this is still taken as a constant load. gas, however, always
6160 treated these as memory references. As a compromise, we'll try to make
6161 offset expressions inside brackets work the MASM way (since that's
6162 less likely to be found in real world code), but make constants alone
6163 continue to work the traditional gas way. In either case, issue a
6164 warning. */
6165 intel_parser.op_modifier &= ~was_offset;
64a0c779 6166 }
a724f0f4
JB		 6167 else
6168 strcat (intel_parser.disp, "[");
6169
6170 /* Add a '+' to the displacement string if necessary. */
6171 if (*intel_parser.disp != '\0'
6172 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6173 strcat (intel_parser.disp, "+");
64a0c779 6174
a724f0f4
JB		 6175 if (intel_expr ()
6176 && (len = intel_parser.op_string - start - 1,
6177 intel_match_token (']')))
64a0c779 6178 {
a724f0f4
JB		 6179 /* Preserve brackets when the operand is an offset expression. */
6180 if (intel_parser.in_offset)
6181 strcat (intel_parser.disp, "]");
6182 else
6183 {
6184 --intel_parser.in_bracket;
6185 if (i.base_reg || i.index_reg)
6186 intel_parser.is_mem = 1;
6187 if (!intel_parser.is_mem)
6188 {
6189 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6190 /* Defer the warning until all of the operand was parsed. */
6191 intel_parser.is_mem = -1;
6192 else if (!quiet_warnings)
6193 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6194 }
6195 }
6196 intel_parser.op_modifier |= was_offset;
64a0c779 6197
a724f0f4 6198 return 1;
64a0c779 6199 }
a724f0f4 6200 return 0;
64a0c779
DN		 6201}
6202
6203/* e10 e11 e10'
6204
6205 e10' [ expr ] e10'
b77a7acd 6206 | Empty */
64a0c779
DN		 6207static int
6208intel_e10 ()
6209{
a724f0f4
JB		 6210 if (!intel_e11 ())
6211 return 0;
64a0c779 6212
a724f0f4 6213 while (cur_token.code == '[')
64a0c779 6214 {
a724f0f4 6215 if (!intel_bracket_expr ())
21d6c4af 6216 return 0;
64a0c779
DN		 6217 }
6218
a724f0f4 6219 return 1;
64a0c779
DN		 6220}
6221
64a0c779 6222/* e11 ( expr )
b77a7acd 6223 | [ expr ]
64a0c779
DN		 6224 | BYTE
6225 | WORD
6226 | DWORD
9306ca4a 6227 | FWORD
64a0c779 6228 | QWORD
9306ca4a
JB		 6229 | TBYTE
6230 | OWORD
6231 | XMMWORD
4a1805b1 6232 | $
64a0c779
DN		 6233 | .
6234 | register
6235 | id
6236 | constant */
6237static int
6238intel_e11 ()
6239{
a724f0f4 6240 switch (cur_token.code)
64a0c779 6241 {
a724f0f4
JB		 6242 /* e11 ( expr ) */
6243 case '(':
64a0c779
DN		 6244 intel_match_token ('(');
6245 strcat (intel_parser.disp, "(");
6246
6247 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 6248 {
6249 strcat (intel_parser.disp, ")");
6250 return 1;
6251 }
a724f0f4 6252 return 0;
4a1805b1 6253
a724f0f4
JB		 6254 /* e11 [ expr ] */
6255 case '[':
6256 /* Operands for jump/call inside brackets denote absolute addresses.
6257 XXX This shouldn't be needed anymore (or if it should rather live
6258 in intel_bracket_expr). */
9306ca4a
JB		 6259 if (current_templates->start->opcode_modifier
6260 & (Jump|JumpDword|JumpByte|JumpInterSegment))
64a0c779
DN		 6261 i.types[this_operand] |= JumpAbsolute;
6262
a724f0f4 6263 return intel_bracket_expr ();
64a0c779 6264
a724f0f4
JB		 6265 /* e11 $
6266 | . */
6267 case '.':
64a0c779
DN		 6268 strcat (intel_parser.disp, cur_token.str);
6269 intel_match_token (cur_token.code);
21d6c4af
DN		 6270
6271 /* Mark as a memory operand only if it's not already known to be an
6272 offset expression. */
a724f0f4 6273 if (!intel_parser.in_offset)
21d6c4af 6274 intel_parser.is_mem = 1;
64a0c779
DN		 6275
6276 return 1;
64a0c779 6277
a724f0f4
JB		 6278 /* e11 register */
6279 case T_REG:
6280 {
6281 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 6282
a724f0f4 6283 intel_match_token (T_REG);
64a0c779 6284
a724f0f4
JB		 6285 /* Check for segment change. */
6286 if (cur_token.code == ':')
6287 {
6288 if (!(reg->reg_type & (SReg2 | SReg3)))
6289 {
6290 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6291 return 0;
6292 }
6293 else if (i.seg[i.mem_operands])
6294 as_warn (_("Extra segment override ignored"));
6295 else
6296 {
6297 if (!intel_parser.in_offset)
6298 intel_parser.is_mem = 1;
6299 switch (reg->reg_num)
6300 {
6301 case 0:
6302 i.seg[i.mem_operands] = &es;
6303 break;
6304 case 1:
6305 i.seg[i.mem_operands] = &cs;
6306 break;
6307 case 2:
6308 i.seg[i.mem_operands] = &ss;
6309 break;
6310 case 3:
6311 i.seg[i.mem_operands] = &ds;
6312 break;
6313 case 4:
6314 i.seg[i.mem_operands] = &fs;
6315 break;
6316 case 5:
6317 i.seg[i.mem_operands] = &gs;
6318 break;
6319 }
6320 }
6321 }
64a0c779 6322
a724f0f4
JB		 6323 /* Not a segment register. Check for register scaling. */
6324 else if (cur_token.code == '*')
6325 {
6326 if (!intel_parser.in_bracket)
6327 {
6328 as_bad (_("Register scaling only allowed in memory operands"));
6329 return 0;
6330 }
64a0c779 6331
a724f0f4
JB		 6332 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6333 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6334 else if (i.index_reg)
6335 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 6336
a724f0f4
JB		 6337 /* What follows must be a valid scale. */
6338 intel_match_token ('*');
6339 i.index_reg = reg;
6340 i.types[this_operand] |= BaseIndex;
64a0c779 6341
a724f0f4
JB		 6342 /* Set the scale after setting the register (otherwise,
6343 i386_scale will complain) */
6344 if (cur_token.code == '+' || cur_token.code == '-')
6345 {
6346 char *str, sign = cur_token.code;
6347 intel_match_token (cur_token.code);
6348 if (cur_token.code != T_CONST)
6349 {
6350 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6351 cur_token.str);
6352 return 0;
6353 }
6354 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6355 strcpy (str + 1, cur_token.str);
6356 *str = sign;
6357 if (!i386_scale (str))
6358 return 0;
6359 free (str);
6360 }
6361 else if (!i386_scale (cur_token.str))
64a0c779 6362 return 0;
a724f0f4
JB		 6363 intel_match_token (cur_token.code);
6364 }
64a0c779 6365
a724f0f4
JB		 6366 /* No scaling. If this is a memory operand, the register is either a
6367 base register (first occurrence) or an index register (second
6368 occurrence). */
6369 else if (intel_parser.in_bracket && !(reg->reg_type & (SReg2 | SReg3)))
6370 {
64a0c779 6371
a724f0f4
JB		 6372 if (!i.base_reg)
6373 i.base_reg = reg;
6374 else if (!i.index_reg)
6375 i.index_reg = reg;
6376 else
6377 {
6378 as_bad (_("Too many register references in memory operand"));
6379 return 0;
6380 }
64a0c779 6381
a724f0f4
JB		 6382 i.types[this_operand] |= BaseIndex;
6383 }
4a1805b1 6384
a724f0f4
JB		 6385 /* Offset modifier. Add the register to the displacement string to be
6386 parsed as an immediate expression after we're done. */
6387 else if (intel_parser.in_offset)
6388 {
6389 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6390 strcat (intel_parser.disp, reg->reg_name);
6391 }
64a0c779 6392
a724f0f4
JB		 6393 /* It's neither base nor index nor offset. */
6394 else if (!intel_parser.is_mem)
6395 {
6396 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6397 i.op[this_operand].regs = reg;
6398 i.reg_operands++;
6399 }
6400 else
6401 {
6402 as_bad (_("Invalid use of register"));
6403 return 0;
6404 }
64a0c779 6405
a724f0f4
JB		 6406 /* Since registers are not part of the displacement string (except
6407 when we're parsing offset operands), we may need to remove any
6408 preceding '+' from the displacement string. */
6409 if (*intel_parser.disp != '\0'
6410 && !intel_parser.in_offset)
6411 {
6412 char *s = intel_parser.disp;
6413 s += strlen (s) - 1;
6414 if (*s == '+')
6415 *s = '\0';
6416 }
4a1805b1 6417
a724f0f4
JB		 6418 return 1;
6419 }
6420
6421 /* e11 BYTE
6422 | WORD
6423 | DWORD
6424 | FWORD
6425 | QWORD
6426 | TBYTE
6427 | OWORD
6428 | XMMWORD */
6429 case T_BYTE:
6430 case T_WORD:
6431 case T_DWORD:
6432 case T_FWORD:
6433 case T_QWORD:
6434 case T_TBYTE:
6435 case T_XMMWORD:
6436 intel_match_token (cur_token.code);
64a0c779 6437
a724f0f4
JB		 6438 if (cur_token.code == T_PTR)
6439 return 1;
6440
6441 /* It must have been an identifier. */
6442 intel_putback_token ();
6443 cur_token.code = T_ID;
6444 /* FALLTHRU */
6445
6446 /* e11 id
6447 | constant */
6448 case T_ID:
6449 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 6450 {
6451 symbolS *symbolP;
6452
a724f0f4
JB		 6453 /* The identifier represents a memory reference only if it's not
6454 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 6455 symbolP = symbol_find(cur_token.str);
6456 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6457 intel_parser.is_mem = 1;
6458 }
a724f0f4 6459 /* FALLTHRU */
64a0c779 6460
a724f0f4
JB		 6461 case T_CONST:
6462 case '-':
6463 case '+':
6464 {
6465 char *save_str, sign = 0;
64a0c779 6466
a724f0f4
JB		 6467 /* Allow constants that start with `+' or `-'. */
6468 if (cur_token.code == '-' || cur_token.code == '+')
6469 {
6470 sign = cur_token.code;
6471 intel_match_token (cur_token.code);
6472 if (cur_token.code != T_CONST)
6473 {
6474 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6475 cur_token.str);
6476 return 0;
6477 }
6478 }
64a0c779 6479
a724f0f4
JB		 6480 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6481 strcpy (save_str + !!sign, cur_token.str);
6482 if (sign)
6483 *save_str = sign;
64a0c779 6484
a724f0f4
JB		 6485 /* Get the next token to check for register scaling. */
6486 intel_match_token (cur_token.code);
64a0c779 6487
a724f0f4
JB		 6488 /* Check if this constant is a scaling factor for an index register. */
6489 if (cur_token.code == '*')
6490 {
6491 if (intel_match_token ('*') && cur_token.code == T_REG)
6492 {
6493 const reg_entry *reg = cur_token.reg;
6494
6495 if (!intel_parser.in_bracket)
6496 {
6497 as_bad (_("Register scaling only allowed in memory operands"));
6498 return 0;
6499 }
6500
6501 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6502 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6503 else if (i.index_reg)
6504 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6505
6506 /* The constant is followed by `* reg', so it must be
6507 a valid scale. */
6508 i.index_reg = reg;
6509 i.types[this_operand] |= BaseIndex;
6510
6511 /* Set the scale after setting the register (otherwise,
6512 i386_scale will complain) */
6513 if (!i386_scale (save_str))
64a0c779 6514 return 0;
a724f0f4
JB		 6515 intel_match_token (T_REG);
6516
6517 /* Since registers are not part of the displacement
6518 string, we may need to remove any preceding '+' from
6519 the displacement string. */
6520 if (*intel_parser.disp != '\0')
6521 {
6522 char *s = intel_parser.disp;
6523 s += strlen (s) - 1;
6524 if (*s == '+')
6525 *s = '\0';
6526 }
6527
6528 free (save_str);
6529
6530 return 1;
6531 }
64a0c779 6532
a724f0f4
JB		 6533 /* The constant was not used for register scaling. Since we have
6534 already consumed the token following `*' we now need to put it
6535 back in the stream. */
64a0c779 6536 intel_putback_token ();
a724f0f4 6537 }
64a0c779 6538
a724f0f4
JB		 6539 /* Add the constant to the displacement string. */
6540 strcat (intel_parser.disp, save_str);
6541 free (save_str);
64a0c779 6542
a724f0f4
JB		 6543 return 1;
6544 }
64a0c779
DN		 6545 }
6546
64a0c779
DN		 6547 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6548 return 0;
6549}
6550
64a0c779
DN		 6551/* Match the given token against cur_token. If they match, read the next
6552 token from the operand string. */
6553static int
6554intel_match_token (code)
e5cb08ac 6555 int code;
64a0c779
DN		 6556{
6557 if (cur_token.code == code)
6558 {
6559 intel_get_token ();
6560 return 1;
6561 }
6562 else
6563 {
0477af35 6564 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 6565 return 0;
6566 }
6567}
6568
64a0c779
DN		 6569/* Read a new token from intel_parser.op_string and store it in cur_token. */
6570static void
6571intel_get_token ()
6572{
6573 char *end_op;
6574 const reg_entry *reg;
6575 struct intel_token new_token;
6576
6577 new_token.code = T_NIL;
6578 new_token.reg = NULL;
6579 new_token.str = NULL;
6580
4a1805b1 6581 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6582 cur_token to prev_token. */
6583 if (prev_token.str)
6584 free (prev_token.str);
6585
6586 prev_token = cur_token;
6587
6588 /* Skip whitespace. */
6589 while (is_space_char (*intel_parser.op_string))
6590 intel_parser.op_string++;
6591
6592 /* Return an empty token if we find nothing else on the line. */
6593 if (*intel_parser.op_string == '\0')
6594 {
6595 cur_token = new_token;
6596 return;
6597 }
6598
6599 /* The new token cannot be larger than the remainder of the operand
6600 string. */
a724f0f4 6601 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 6602 new_token.str[0] = '\0';
6603
6604 if (strchr ("0123456789", *intel_parser.op_string))
6605 {
6606 char *p = new_token.str;
6607 char *q = intel_parser.op_string;
6608 new_token.code = T_CONST;
6609
6610 /* Allow any kind of identifier char to encompass floating point and
6611 hexadecimal numbers. */
6612 while (is_identifier_char (*q))
6613 *p++ = *q++;
6614 *p = '\0';
6615
6616 /* Recognize special symbol names [0-9][bf]. */
6617 if (strlen (intel_parser.op_string) == 2
4a1805b1 6618 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6619 || intel_parser.op_string[1] == 'f'))
6620 new_token.code = T_ID;
6621 }
6622
64a0c779
DN		 6623 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6624 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6625 {
6626 new_token.code = T_REG;
6627 new_token.reg = reg;
6628
6629 if (*intel_parser.op_string == REGISTER_PREFIX)
6630 {
6631 new_token.str[0] = REGISTER_PREFIX;
6632 new_token.str[1] = '\0';
6633 }
6634
6635 strcat (new_token.str, reg->reg_name);
6636 }
6637
6638 else if (is_identifier_char (*intel_parser.op_string))
6639 {
6640 char *p = new_token.str;
6641 char *q = intel_parser.op_string;
6642
6643 /* A '.' or '$' followed by an identifier char is an identifier.
6644 Otherwise, it's operator '.' followed by an expression. */
6645 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6646 {
9306ca4a
JB		 6647 new_token.code = '.';
6648 new_token.str[0] = '.';
64a0c779
DN		 6649 new_token.str[1] = '\0';
6650 }
6651 else
6652 {
6653 while (is_identifier_char (*q) || *q == '@')
6654 *p++ = *q++;
6655 *p = '\0';
6656
9306ca4a
JB		 6657 if (strcasecmp (new_token.str, "NOT") == 0)
6658 new_token.code = '~';
6659
6660 else if (strcasecmp (new_token.str, "MOD") == 0)
6661 new_token.code = '%';
6662
6663 else if (strcasecmp (new_token.str, "AND") == 0)
6664 new_token.code = '&';
6665
6666 else if (strcasecmp (new_token.str, "OR") == 0)
6667 new_token.code = '|';
6668
6669 else if (strcasecmp (new_token.str, "XOR") == 0)
6670 new_token.code = '^';
6671
6672 else if (strcasecmp (new_token.str, "SHL") == 0)
6673 new_token.code = T_SHL;
6674
6675 else if (strcasecmp (new_token.str, "SHR") == 0)
6676 new_token.code = T_SHR;
6677
6678 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 6679 new_token.code = T_BYTE;
6680
6681 else if (strcasecmp (new_token.str, "WORD") == 0)
6682 new_token.code = T_WORD;
6683
6684 else if (strcasecmp (new_token.str, "DWORD") == 0)
6685 new_token.code = T_DWORD;
6686
9306ca4a
JB		 6687 else if (strcasecmp (new_token.str, "FWORD") == 0)
6688 new_token.code = T_FWORD;
6689
64a0c779
DN		 6690 else if (strcasecmp (new_token.str, "QWORD") == 0)
6691 new_token.code = T_QWORD;
6692
9306ca4a
JB		 6693 else if (strcasecmp (new_token.str, "TBYTE") == 0
6694 /* XXX remove (gcc still uses it) */
6695 || strcasecmp (new_token.str, "XWORD") == 0)
6696 new_token.code = T_TBYTE;
6697
6698 else if (strcasecmp (new_token.str, "XMMWORD") == 0
6699 || strcasecmp (new_token.str, "OWORD") == 0)
6700 new_token.code = T_XMMWORD;
64a0c779
DN		 6701
6702 else if (strcasecmp (new_token.str, "PTR") == 0)
6703 new_token.code = T_PTR;
6704
6705 else if (strcasecmp (new_token.str, "SHORT") == 0)
6706 new_token.code = T_SHORT;
6707
6708 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6709 {
6710 new_token.code = T_OFFSET;
6711
6712 /* ??? This is not mentioned in the MASM grammar but gcc
6713 makes use of it with -mintel-syntax. OFFSET may be
6714 followed by FLAT: */
6715 if (strncasecmp (q, " FLAT:", 6) == 0)
6716 strcat (new_token.str, " FLAT:");
6717 }
6718
6719 /* ??? This is not mentioned in the MASM grammar. */
6720 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 6721 {
6722 new_token.code = T_OFFSET;
6723 if (*q == ':')
6724 strcat (new_token.str, ":");
6725 else
6726 as_bad (_("`:' expected"));
6727 }
64a0c779
DN		 6728
6729 else
6730 new_token.code = T_ID;
6731 }
6732 }
6733
9306ca4a
JB		 6734 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
6735 {
6736 new_token.code = *intel_parser.op_string;
6737 new_token.str[0] = *intel_parser.op_string;
6738 new_token.str[1] = '\0';
6739 }
6740
6741 else if (strchr ("<>", *intel_parser.op_string)
6742 && *intel_parser.op_string == *(intel_parser.op_string + 1))
6743 {
6744 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
6745 new_token.str[0] = *intel_parser.op_string;
6746 new_token.str[1] = *intel_parser.op_string;
6747 new_token.str[2] = '\0';
6748 }
6749
64a0c779 6750 else
0477af35 6751 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 6752
6753 intel_parser.op_string += strlen (new_token.str);
6754 cur_token = new_token;
6755}
6756
64a0c779
DN		 6757/* Put cur_token back into the token stream and make cur_token point to
6758 prev_token. */
6759static void
6760intel_putback_token ()
6761{
a724f0f4
JB		 6762 if (cur_token.code != T_NIL)
6763 {
6764 intel_parser.op_string -= strlen (cur_token.str);
6765 free (cur_token.str);
6766 }
64a0c779 6767 cur_token = prev_token;
4a1805b1 6768
64a0c779
DN		 6769 /* Forget prev_token. */
6770 prev_token.code = T_NIL;
6771 prev_token.reg = NULL;
6772 prev_token.str = NULL;
6773}
54cfded0 6774
a4447b93 6775int
54cfded0
AM		 6776tc_x86_regname_to_dw2regnum (const char *regname)
6777{
6778 unsigned int regnum;
6779 unsigned int regnames_count;
6780 char *regnames_32[] =
6781 {
a4447b93
RH		 6782 "eax", "ecx", "edx", "ebx",
6783 "esp", "ebp", "esi", "edi",
54cfded0
AM		 6784 "eip"
6785 };
6786 char *regnames_64[] =
6787 {
6788 "rax", "rbx", "rcx", "rdx",
6789 "rdi", "rsi", "rbp", "rsp",
6790 "r8", "r9", "r10", "r11",
6791 "r12", "r13", "r14", "r15",
6792 "rip"
6793 };
6794 char **regnames;
6795
6796 if (flag_code == CODE_64BIT)
6797 {
6798 regnames = regnames_64;
0cea6190 6799 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 6800 }
6801 else
6802 {
6803 regnames = regnames_32;
0cea6190 6804 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 6805 }
6806
6807 for (regnum = 0; regnum < regnames_count; regnum++)
6808 if (strcmp (regname, regnames[regnum]) == 0)
6809 return regnum;
6810
54cfded0
AM		 6811 return -1;
6812}
6813
6814void
6815tc_x86_frame_initial_instructions (void)
6816{
a4447b93
RH		 6817 static unsigned int sp_regno;
6818
6819 if (!sp_regno)
6820 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
6821 ? "rsp" : "esp");
6822
6823 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
6824 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 6825}
d2b2c203
DJ		 6826
6827int
6828i386_elf_section_type (const char *str, size_t len)
6829{
6830 if (flag_code == CODE_64BIT
6831 && len == sizeof ("unwind") - 1
6832 && strncmp (str, "unwind", 6) == 0)
6833 return SHT_X86_64_UNWIND;
6834
6835 return -1;
6836}
bb41ade5
AM		 6837
6838#ifdef TE_PE
6839void
6840tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
6841{
6842 expressionS expr;
6843
6844 expr.X_op = O_secrel;
6845 expr.X_add_symbol = symbol;
6846 expr.X_add_number = 0;
6847 emit_expr (&expr, size);
6848}
6849#endif
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