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542e1629 | 1 | /* tc-i960.c - All the i80960-specific stuff |
48401fcf TT |
2 | Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 1997 |
3 | Free Software Foundation, Inc. | |
355afbcd | 4 | |
a39116f1 | 5 | This file is part of GAS. |
355afbcd | 6 | |
a39116f1 RP |
7 | GAS is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
355afbcd | 11 | |
a39116f1 RP |
12 | GAS is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
355afbcd | 16 | |
a39116f1 | 17 | You should have received a copy of the GNU General Public License |
48401fcf TT |
18 | along with GAS; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
fecd2382 | 21 | |
fecd2382 RP |
22 | /* See comment on md_parse_option for 80960-specific invocation options. */ |
23 | ||
fecd2382 | 24 | /* There are 4 different lengths of (potentially) symbol-based displacements |
0e6f2f82 KR |
25 | in the 80960 instruction set, each of which could require address fix-ups |
26 | and (in the case of external symbols) emission of relocation directives: | |
27 | ||
28 | 32-bit (MEMB) | |
29 | This is a standard length for the base assembler and requires no | |
30 | special action. | |
31 | ||
32 | 13-bit (COBR) | |
33 | This is a non-standard length, but the base assembler has a | |
34 | hook for bit field address fixups: the fixS structure can | |
35 | point to a descriptor of the field, in which case our | |
36 | md_number_to_field() routine gets called to process it. | |
37 | ||
38 | I made the hook a little cleaner by having fix_new() (in the base | |
39 | assembler) return a pointer to the fixS in question. And I made it a | |
40 | little simpler by storing the field size (in this case 13) instead of | |
41 | of a pointer to another structure: 80960 displacements are ALWAYS | |
42 | stored in the low-order bits of a 4-byte word. | |
43 | ||
44 | Since the target of a COBR cannot be external, no relocation | |
45 | directives for this size displacement have to be generated. | |
46 | But the base assembler had to be modified to issue error | |
47 | messages if the symbol did turn out to be external. | |
48 | ||
49 | 24-bit (CTRL) | |
50 | Fixups are handled as for the 13-bit case (except that 24 is stored | |
51 | in the fixS). | |
52 | ||
53 | The relocation directive generated is the same as that for the 32-bit | |
54 | displacement, except that it's PC-relative (the 32-bit displacement | |
55 | never is). The i80960 version of the linker needs a mod to | |
56 | distinguish and handle the 24-bit case. | |
57 | ||
58 | 12-bit (MEMA) | |
59 | MEMA formats are always promoted to MEMB (32-bit) if the displacement | |
60 | is based on a symbol, because it could be relocated at link time. | |
61 | The only time we use the 12-bit format is if an absolute value of | |
62 | less than 4096 is specified, in which case we need neither a fixup nor | |
63 | a relocation directive. */ | |
fecd2382 RP |
64 | |
65 | #include <stdio.h> | |
66 | #include <ctype.h> | |
67 | ||
68 | #include "as.h" | |
69 | ||
70 | #include "obstack.h" | |
71 | ||
a39116f1 | 72 | #include "opcode/i960.h" |
fecd2382 | 73 | |
0e6f2f82 KR |
74 | #if defined (OBJ_AOUT) || defined (OBJ_BOUT) |
75 | ||
76 | #define TC_S_IS_SYSPROC(s) ((1<=S_GET_OTHER(s)) && (S_GET_OTHER(s)<=32)) | |
77 | #define TC_S_IS_BALNAME(s) (S_GET_OTHER(s) == N_BALNAME) | |
78 | #define TC_S_IS_CALLNAME(s) (S_GET_OTHER(s) == N_CALLNAME) | |
79 | #define TC_S_IS_BADPROC(s) ((S_GET_OTHER(s) != 0) && !TC_S_IS_CALLNAME(s) && !TC_S_IS_BALNAME(s) && !TC_S_IS_SYSPROC(s)) | |
80 | ||
81 | #define TC_S_SET_SYSPROC(s, p) (S_SET_OTHER((s), (p)+1)) | |
82 | #define TC_S_GET_SYSPROC(s) (S_GET_OTHER(s)-1) | |
83 | ||
84 | #define TC_S_FORCE_TO_BALNAME(s) (S_SET_OTHER((s), N_BALNAME)) | |
85 | #define TC_S_FORCE_TO_CALLNAME(s) (S_SET_OTHER((s), N_CALLNAME)) | |
86 | #define TC_S_FORCE_TO_SYSPROC(s) {;} | |
87 | ||
88 | #else /* ! OBJ_A/BOUT */ | |
89 | #ifdef OBJ_COFF | |
90 | ||
91 | #define TC_S_IS_SYSPROC(s) (S_GET_STORAGE_CLASS(s) == C_SCALL) | |
92 | #define TC_S_IS_BALNAME(s) (SF_GET_BALNAME(s)) | |
93 | #define TC_S_IS_CALLNAME(s) (SF_GET_CALLNAME(s)) | |
94 | #define TC_S_IS_BADPROC(s) (TC_S_IS_SYSPROC(s) && TC_S_GET_SYSPROC(s) < 0 && 31 < TC_S_GET_SYSPROC(s)) | |
95 | ||
96 | #define TC_S_SET_SYSPROC(s, p) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p)) | |
97 | #define TC_S_GET_SYSPROC(s) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx) | |
98 | ||
99 | #define TC_S_FORCE_TO_BALNAME(s) (SF_SET_BALNAME(s)) | |
100 | #define TC_S_FORCE_TO_CALLNAME(s) (SF_SET_CALLNAME(s)) | |
101 | #define TC_S_FORCE_TO_SYSPROC(s) (S_SET_STORAGE_CLASS((s), C_SCALL)) | |
102 | ||
103 | #else /* ! OBJ_COFF */ | |
104 | you lose; | |
105 | #endif /* ! OBJ_COFF */ | |
106 | #endif /* ! OBJ_A/BOUT */ | |
f3d817d8 | 107 | |
fecd2382 | 108 | extern char *input_line_pointer; |
fecd2382 | 109 | |
f3d817d8 | 110 | #if !defined (BFD_ASSEMBLER) && !defined (BFD) |
fecd2382 | 111 | #ifdef OBJ_COFF |
c47d388b | 112 | const int md_reloc_size = sizeof (struct reloc); |
fecd2382 | 113 | #else /* OBJ_COFF */ |
c47d388b | 114 | const int md_reloc_size = sizeof (struct relocation_info); |
fecd2382 | 115 | #endif /* OBJ_COFF */ |
f3d817d8 | 116 | #endif |
fecd2382 | 117 | |
0e6f2f82 | 118 | /* Local i80960 routines. */ |
fecd2382 | 119 | |
355afbcd KR |
120 | static void brcnt_emit (); /* Emit branch-prediction instrumentation code */ |
121 | static char *brlab_next (); /* Return next branch local label */ | |
122 | void brtab_emit (); /* Emit br-predict instrumentation table */ | |
123 | static void cobr_fmt (); /* Generate COBR instruction */ | |
124 | static void ctrl_fmt (); /* Generate CTRL instruction */ | |
125 | static char *emit (); /* Emit (internally) binary */ | |
126 | static int get_args (); /* Break arguments out of comma-separated list */ | |
127 | static void get_cdisp (); /* Handle COBR or CTRL displacement */ | |
128 | static char *get_ispec (); /* Find index specification string */ | |
129 | static int get_regnum (); /* Translate text to register number */ | |
130 | static int i_scan (); /* Lexical scan of instruction source */ | |
131 | static void mem_fmt (); /* Generate MEMA or MEMB instruction */ | |
132 | static void mema_to_memb (); /* Convert MEMA instruction to MEMB format */ | |
5ac34ac3 | 133 | static void parse_expr (); /* Parse an expression */ |
355afbcd KR |
134 | static int parse_ldconst (); /* Parse and replace a 'ldconst' pseudo-op */ |
135 | static void parse_memop (); /* Parse a memory operand */ | |
136 | static void parse_po (); /* Parse machine-dependent pseudo-op */ | |
137 | static void parse_regop (); /* Parse a register operand */ | |
138 | static void reg_fmt (); /* Generate a REG format instruction */ | |
139 | void reloc_callj (); /* Relocate a 'callj' instruction */ | |
140 | static void relax_cobr (); /* "De-optimize" cobr into compare/branch */ | |
141 | static void s_leafproc (); /* Process '.leafproc' pseudo-op */ | |
142 | static void s_sysproc (); /* Process '.sysproc' pseudo-op */ | |
143 | static int shift_ok (); /* Will a 'shlo' substiture for a 'ldconst'? */ | |
144 | static void syntax (); /* Give syntax error */ | |
145 | static int targ_has_sfr (); /* Target chip supports spec-func register? */ | |
146 | static int targ_has_iclass (); /* Target chip supports instruction set? */ | |
fecd2382 RP |
147 | |
148 | /* See md_parse_option() for meanings of these options */ | |
09952cd9 | 149 | static char norelax; /* True if -norelax switch seen */ |
0e6f2f82 | 150 | static char instrument_branches; /* True if -b switch seen */ |
fecd2382 RP |
151 | |
152 | /* Characters that always start a comment. | |
0e6f2f82 | 153 | If the pre-processor is disabled, these aren't very useful. |
fecd2382 | 154 | */ |
355afbcd | 155 | const char comment_chars[] = "#"; |
fecd2382 RP |
156 | |
157 | /* Characters that only start a comment at the beginning of | |
0e6f2f82 KR |
158 | a line. If the line seems to have the form '# 123 filename' |
159 | .line and .file directives will appear in the pre-processed output. | |
160 | ||
161 | Note that input_file.c hand checks for '#' at the beginning of the | |
162 | first line of the input file. This is because the compiler outputs | |
163 | #NO_APP at the beginning of its output. | |
fecd2382 RP |
164 | */ |
165 | ||
166 | /* Also note that comments started like this one will always work. */ | |
167 | ||
c47d388b | 168 | const char line_comment_chars[1]; |
355afbcd | 169 | |
c47d388b | 170 | const char line_separator_chars[1]; |
fecd2382 RP |
171 | |
172 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
355afbcd | 173 | const char EXP_CHARS[] = "eE"; |
fecd2382 RP |
174 | |
175 | /* Chars that mean this number is a floating point constant, | |
0e6f2f82 | 176 | as in 0f12.456 or 0d1.2345e12 |
fecd2382 | 177 | */ |
355afbcd | 178 | const char FLT_CHARS[] = "fFdDtT"; |
fecd2382 RP |
179 | |
180 | ||
181 | /* Table used by base assembler to relax addresses based on varying length | |
0e6f2f82 KR |
182 | instructions. The fields are: |
183 | 1) most positive reach of this state, | |
184 | 2) most negative reach of this state, | |
185 | 3) how many bytes this mode will add to the size of the current frag | |
186 | 4) which index into the table to try if we can't fit into this one. | |
187 | ||
188 | For i80960, the only application is the (de-)optimization of cobr | |
189 | instructions into separate compare and branch instructions when a 13-bit | |
190 | displacement won't hack it. | |
fecd2382 | 191 | */ |
0e6f2f82 | 192 | const relax_typeS md_relax_table[] = |
355afbcd KR |
193 | { |
194 | {0, 0, 0, 0}, /* State 0 => no more relaxation possible */ | |
195 | {4088, -4096, 0, 2}, /* State 1: conditional branch (cobr) */ | |
196 | {0x800000 - 8, -0x800000, 4, 0}, /* State 2: compare (reg) & branch (ctrl) */ | |
197 | }; | |
fecd2382 | 198 | |
0e6f2f82 | 199 | static void s_endian PARAMS ((int)); |
fecd2382 RP |
200 | |
201 | /* These are the machine dependent pseudo-ops. | |
0e6f2f82 KR |
202 | |
203 | This table describes all the machine specific pseudo-ops the assembler | |
204 | has to support. The fields are: | |
205 | pseudo-op name without dot | |
206 | function to call to execute this pseudo-op | |
207 | integer arg to pass to the function | |
fecd2382 RP |
208 | */ |
209 | #define S_LEAFPROC 1 | |
210 | #define S_SYSPROC 2 | |
211 | ||
355afbcd KR |
212 | const pseudo_typeS md_pseudo_table[] = |
213 | { | |
214 | {"bss", s_lcomm, 1}, | |
0e6f2f82 | 215 | {"endian", s_endian, 0}, |
355afbcd KR |
216 | {"extended", float_cons, 't'}, |
217 | {"leafproc", parse_po, S_LEAFPROC}, | |
218 | {"sysproc", parse_po, S_SYSPROC}, | |
09952cd9 | 219 | |
355afbcd | 220 | {"word", cons, 4}, |
80aab579 | 221 | {"quad", cons, 16}, |
09952cd9 | 222 | |
355afbcd | 223 | {0, 0, 0} |
09952cd9 | 224 | }; |
fecd2382 RP |
225 | \f |
226 | /* Macros to extract info from an 'expressionS' structure 'e' */ | |
227 | #define adds(e) e.X_add_symbol | |
fecd2382 | 228 | #define offs(e) e.X_add_number |
355afbcd KR |
229 | |
230 | ||
231 | /* Branch-prediction bits for CTRL/COBR format opcodes */ | |
232 | #define BP_MASK 0x00000002 /* Mask for branch-prediction bit */ | |
233 | #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */ | |
234 | #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */ | |
235 | ||
236 | ||
237 | /* Some instruction opcodes that we need explicitly */ | |
fecd2382 RP |
238 | #define BE 0x12000000 |
239 | #define BG 0x11000000 | |
240 | #define BGE 0x13000000 | |
241 | #define BL 0x14000000 | |
242 | #define BLE 0x16000000 | |
243 | #define BNE 0x15000000 | |
244 | #define BNO 0x10000000 | |
245 | #define BO 0x17000000 | |
246 | #define CHKBIT 0x5a002700 | |
247 | #define CMPI 0x5a002080 | |
248 | #define CMPO 0x5a002000 | |
355afbcd | 249 | |
fecd2382 RP |
250 | #define B 0x08000000 |
251 | #define BAL 0x0b000000 | |
252 | #define CALL 0x09000000 | |
253 | #define CALLS 0x66003800 | |
254 | #define RET 0x0a000000 | |
355afbcd KR |
255 | |
256 | ||
257 | /* These masks are used to build up a set of MEMB mode bits. */ | |
fecd2382 RP |
258 | #define A_BIT 0x0400 |
259 | #define I_BIT 0x0800 | |
260 | #define MEMB_BIT 0x1000 | |
261 | #define D_BIT 0x2000 | |
355afbcd KR |
262 | |
263 | ||
c47d388b ME |
264 | /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is |
265 | used). */ | |
fecd2382 | 266 | #define MEMA_ABASE 0x2000 |
355afbcd KR |
267 | |
268 | /* Info from which a MEMA or MEMB format instruction can be generated */ | |
269 | typedef struct | |
270 | { | |
c47d388b ME |
271 | /* (First) 32 bits of instruction */ |
272 | long opcode; | |
273 | /* 0-(none), 12- or, 32-bit displacement needed */ | |
274 | int disp; | |
275 | /* The expression in the source instruction from which the | |
276 | displacement should be determined. */ | |
277 | char *e; | |
355afbcd KR |
278 | } |
279 | ||
280 | memS; | |
fecd2382 RP |
281 | |
282 | ||
283 | /* The two pieces of info we need to generate a register operand */ | |
355afbcd KR |
284 | struct regop |
285 | { | |
286 | int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg */ | |
287 | int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0) */ | |
288 | int n; /* Register number or literal value */ | |
289 | }; | |
fecd2382 RP |
290 | |
291 | ||
0e6f2f82 KR |
292 | /* Number and assembler mnemonic for all registers that can appear in |
293 | operands. */ | |
294 | static const struct | |
355afbcd KR |
295 | { |
296 | char *reg_name; | |
297 | int reg_num; | |
298 | } | |
355afbcd KR |
299 | regnames[] = |
300 | { | |
301 | { "pfp", 0 }, | |
302 | { "sp", 1 }, | |
303 | { "rip", 2 }, | |
304 | { "r3", 3 }, | |
305 | { "r4", 4 }, | |
306 | { "r5", 5 }, | |
307 | { "r6", 6 }, | |
308 | { "r7", 7 }, | |
309 | { "r8", 8 }, | |
310 | { "r9", 9 }, | |
311 | { "r10", 10 }, | |
312 | { "r11", 11 }, | |
313 | { "r12", 12 }, | |
314 | { "r13", 13 }, | |
315 | { "r14", 14 }, | |
316 | { "r15", 15 }, | |
317 | { "g0", 16 }, | |
318 | { "g1", 17 }, | |
319 | { "g2", 18 }, | |
320 | { "g3", 19 }, | |
321 | { "g4", 20 }, | |
322 | { "g5", 21 }, | |
323 | { "g6", 22 }, | |
324 | { "g7", 23 }, | |
325 | { "g8", 24 }, | |
326 | { "g9", 25 }, | |
327 | { "g10", 26 }, | |
328 | { "g11", 27 }, | |
329 | { "g12", 28 }, | |
330 | { "g13", 29 }, | |
331 | { "g14", 30 }, | |
332 | { "fp", 31 }, | |
333 | ||
334 | /* Numbers for special-function registers are for assembler internal | |
335 | use only: they are scaled back to range [0-31] for binary output. */ | |
336 | #define SF0 32 | |
337 | ||
338 | { "sf0", 32 }, | |
339 | { "sf1", 33 }, | |
340 | { "sf2", 34 }, | |
341 | { "sf3", 35 }, | |
342 | { "sf4", 36 }, | |
343 | { "sf5", 37 }, | |
344 | { "sf6", 38 }, | |
345 | { "sf7", 39 }, | |
346 | { "sf8", 40 }, | |
347 | { "sf9", 41 }, | |
348 | { "sf10", 42 }, | |
349 | { "sf11", 43 }, | |
350 | { "sf12", 44 }, | |
351 | { "sf13", 45 }, | |
352 | { "sf14", 46 }, | |
353 | { "sf15", 47 }, | |
354 | { "sf16", 48 }, | |
355 | { "sf17", 49 }, | |
356 | { "sf18", 50 }, | |
357 | { "sf19", 51 }, | |
358 | { "sf20", 52 }, | |
359 | { "sf21", 53 }, | |
360 | { "sf22", 54 }, | |
361 | { "sf23", 55 }, | |
362 | { "sf24", 56 }, | |
363 | { "sf25", 57 }, | |
364 | { "sf26", 58 }, | |
365 | { "sf27", 59 }, | |
366 | { "sf28", 60 }, | |
367 | { "sf29", 61 }, | |
368 | { "sf30", 62 }, | |
369 | { "sf31", 63 }, | |
370 | ||
0e6f2f82 KR |
371 | /* Numbers for floating point registers are for assembler internal |
372 | use only: they are scaled back to [0-3] for binary output. */ | |
355afbcd KR |
373 | #define FP0 64 |
374 | ||
375 | { "fp0", 64 }, | |
376 | { "fp1", 65 }, | |
377 | { "fp2", 66 }, | |
378 | { "fp3", 67 }, | |
379 | ||
380 | { NULL, 0 }, /* END OF LIST */ | |
fecd2382 RP |
381 | }; |
382 | ||
383 | #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0)) | |
384 | #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0)) | |
385 | #define IS_FP_REG(n) ((n) >= FP0) | |
386 | ||
0e6f2f82 KR |
387 | /* Number and assembler mnemonic for all registers that can appear as |
388 | 'abase' (indirect addressing) registers. */ | |
389 | static const struct | |
355afbcd KR |
390 | { |
391 | char *areg_name; | |
392 | int areg_num; | |
393 | } | |
355afbcd KR |
394 | aregs[] = |
395 | { | |
396 | { "(pfp)", 0 }, | |
397 | { "(sp)", 1 }, | |
398 | { "(rip)", 2 }, | |
399 | { "(r3)", 3 }, | |
400 | { "(r4)", 4 }, | |
401 | { "(r5)", 5 }, | |
402 | { "(r6)", 6 }, | |
403 | { "(r7)", 7 }, | |
404 | { "(r8)", 8 }, | |
405 | { "(r9)", 9 }, | |
406 | { "(r10)", 10 }, | |
407 | { "(r11)", 11 }, | |
408 | { "(r12)", 12 }, | |
409 | { "(r13)", 13 }, | |
410 | { "(r14)", 14 }, | |
411 | { "(r15)", 15 }, | |
412 | { "(g0)", 16 }, | |
413 | { "(g1)", 17 }, | |
414 | { "(g2)", 18 }, | |
415 | { "(g3)", 19 }, | |
416 | { "(g4)", 20 }, | |
417 | { "(g5)", 21 }, | |
418 | { "(g6)", 22 }, | |
419 | { "(g7)", 23 }, | |
420 | { "(g8)", 24 }, | |
421 | { "(g9)", 25 }, | |
422 | { "(g10)", 26 }, | |
423 | { "(g11)", 27 }, | |
424 | { "(g12)", 28 }, | |
425 | { "(g13)", 29 }, | |
426 | { "(g14)", 30 }, | |
427 | { "(fp)", 31 }, | |
428 | ||
429 | #define IPREL 32 | |
430 | /* For assembler internal use only: this number never appears in binary | |
431 | output. */ | |
432 | { "(ip)", IPREL }, | |
433 | ||
434 | { NULL, 0 }, /* END OF LIST */ | |
fecd2382 RP |
435 | }; |
436 | ||
437 | ||
438 | /* Hash tables */ | |
c47d388b ME |
439 | static struct hash_control *op_hash; /* Opcode mnemonics */ |
440 | static struct hash_control *reg_hash; /* Register name hash table */ | |
441 | static struct hash_control *areg_hash; /* Abase register hash table */ | |
fecd2382 RP |
442 | |
443 | ||
444 | /* Architecture for which we are assembling */ | |
445 | #define ARCH_ANY 0 /* Default: no architecture checking done */ | |
446 | #define ARCH_KA 1 | |
447 | #define ARCH_KB 2 | |
448 | #define ARCH_MC 3 | |
449 | #define ARCH_CA 4 | |
48401fcf TT |
450 | #define ARCH_JX 5 |
451 | #define ARCH_HX 6 | |
fecd2382 | 452 | int architecture = ARCH_ANY; /* Architecture requested on invocation line */ |
c47d388b | 453 | int iclasses_seen; /* OR of instruction classes (I_* constants) |
0e6f2f82 KR |
454 | * for which we've actually assembled |
455 | * instructions. | |
fecd2382 RP |
456 | */ |
457 | ||
458 | ||
459 | /* BRANCH-PREDICTION INSTRUMENTATION | |
0e6f2f82 KR |
460 | |
461 | The following supports generation of branch-prediction instrumentation | |
462 | (turned on by -b switch). The instrumentation collects counts | |
463 | of branches taken/not-taken for later input to a utility that will | |
464 | set the branch prediction bits of the instructions in accordance with | |
465 | the behavior observed. (Note that the KX series does not have | |
466 | brach-prediction.) | |
467 | ||
468 | The instrumentation consists of: | |
469 | ||
470 | (1) before and after each conditional branch, a call to an external | |
471 | routine that increments and steps over an inline counter. The | |
472 | counter itself, initialized to 0, immediately follows the call | |
473 | instruction. For each branch, the counter following the branch | |
474 | is the number of times the branch was not taken, and the difference | |
475 | between the counters is the number of times it was taken. An | |
476 | example of an instrumented conditional branch: | |
477 | ||
478 | call BR_CNT_FUNC | |
479 | .word 0 | |
480 | LBRANCH23: be label | |
481 | call BR_CNT_FUNC | |
482 | .word 0 | |
483 | ||
484 | (2) a table of pointers to the instrumented branches, so that an | |
485 | external postprocessing routine can locate all of the counters. | |
486 | the table begins with a 2-word header: a pointer to the next in | |
487 | a linked list of such tables (initialized to 0); and a count | |
488 | of the number of entries in the table (exclusive of the header. | |
489 | ||
490 | Note that input source code is expected to already contain calls | |
491 | an external routine that will link the branch local table into a | |
492 | list of such tables. | |
fecd2382 RP |
493 | */ |
494 | ||
0e6f2f82 KR |
495 | /* Number of branches instrumented so far. Also used to generate |
496 | unique local labels for each instrumented branch. */ | |
497 | static int br_cnt; | |
fecd2382 RP |
498 | |
499 | #define BR_LABEL_BASE "LBRANCH" | |
0e6f2f82 KR |
500 | /* Basename of local labels on instrumented branches, to avoid |
501 | conflict with compiler- generated local labels. */ | |
fecd2382 RP |
502 | |
503 | #define BR_CNT_FUNC "__inc_branch" | |
0e6f2f82 KR |
504 | /* Name of the external routine that will increment (and step over) an |
505 | inline counter. */ | |
fecd2382 RP |
506 | |
507 | #define BR_TAB_NAME "__BRANCH_TABLE__" | |
0e6f2f82 KR |
508 | /* Name of the table of pointers to branches. A local (i.e., |
509 | non-external) symbol. */ | |
fecd2382 RP |
510 | \f |
511 | /***************************************************************************** | |
0e6f2f82 KR |
512 | md_begin: One-time initialization. |
513 | ||
514 | Set up hash tables. | |
515 | ||
516 | *************************************************************************** */ | |
fecd2382 | 517 | void |
355afbcd | 518 | md_begin () |
fecd2382 | 519 | { |
355afbcd KR |
520 | int i; /* Loop counter */ |
521 | const struct i960_opcode *oP; /* Pointer into opcode table */ | |
80aab579 | 522 | const char *retval; /* Value returned by hash functions */ |
355afbcd | 523 | |
f3d817d8 DM |
524 | op_hash = hash_new (); |
525 | reg_hash = hash_new (); | |
526 | areg_hash = hash_new (); | |
355afbcd | 527 | |
c47d388b ME |
528 | /* For some reason, the base assembler uses an empty string for "no |
529 | error message", instead of a NULL pointer. */ | |
f3d817d8 | 530 | retval = 0; |
355afbcd | 531 | |
80aab579 ILT |
532 | for (oP = i960_opcodes; oP->name && !retval; oP++) |
533 | retval = hash_insert (op_hash, oP->name, (PTR) oP); | |
355afbcd | 534 | |
80aab579 ILT |
535 | for (i = 0; regnames[i].reg_name && !retval; i++) |
536 | retval = hash_insert (reg_hash, regnames[i].reg_name, | |
0e6f2f82 | 537 | (char *) ®names[i].reg_num); |
355afbcd | 538 | |
80aab579 ILT |
539 | for (i = 0; aregs[i].areg_name && !retval; i++) |
540 | retval = hash_insert (areg_hash, aregs[i].areg_name, | |
0e6f2f82 | 541 | (char *) &aregs[i].areg_num); |
355afbcd | 542 | |
80aab579 | 543 | if (retval) |
48401fcf | 544 | as_fatal (_("Hashing returned \"%s\"."), retval); |
80aab579 | 545 | } |
fecd2382 | 546 | |
fecd2382 | 547 | /***************************************************************************** |
0e6f2f82 KR |
548 | md_assemble: Assemble an instruction |
549 | ||
550 | Assumptions about the passed-in text: | |
551 | - all comments, labels removed | |
552 | - text is an instruction | |
553 | - all white space compressed to single blanks | |
554 | - all character constants have been replaced with decimal | |
555 | ||
556 | *************************************************************************** */ | |
fecd2382 | 557 | void |
355afbcd KR |
558 | md_assemble (textP) |
559 | char *textP; /* Source text of instruction */ | |
fecd2382 | 560 | { |
0e6f2f82 KR |
561 | /* Parsed instruction text, containing NO whitespace: arg[0]->opcode |
562 | mnemonic arg[1-3]->operands, with char constants replaced by | |
563 | decimal numbers. */ | |
c47d388b ME |
564 | char *args[4]; |
565 | ||
355afbcd | 566 | int n_ops; /* Number of instruction operands */ |
355afbcd | 567 | /* Pointer to instruction description */ |
c47d388b | 568 | struct i960_opcode *oP; |
0e6f2f82 KR |
569 | /* TRUE iff opcode mnemonic included branch-prediction suffix (".f" |
570 | or ".t"). */ | |
c47d388b | 571 | int branch_predict; |
0e6f2f82 KR |
572 | /* Setting of branch-prediction bit(s) to be OR'd into instruction |
573 | opcode of CTRL/COBR format instructions. */ | |
c47d388b ME |
574 | long bp_bits; |
575 | ||
355afbcd KR |
576 | int n; /* Offset of last character in opcode mnemonic */ |
577 | ||
48401fcf | 578 | static const char bp_error_msg[] = _("branch prediction invalid on this opcode"); |
355afbcd KR |
579 | |
580 | ||
581 | /* Parse instruction into opcode and operands */ | |
582 | memset (args, '\0', sizeof (args)); | |
583 | n_ops = i_scan (textP, args); | |
584 | if (n_ops == -1) | |
585 | { | |
586 | return; /* Error message already issued */ | |
587 | } | |
588 | ||
589 | /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */ | |
590 | if (!strcmp (args[0], "ldconst")) | |
591 | { | |
592 | n_ops = parse_ldconst (args); | |
593 | if (n_ops == -1) | |
594 | { | |
595 | return; | |
fecd2382 | 596 | } |
355afbcd | 597 | } |
09952cd9 KR |
598 | |
599 | ||
355afbcd KR |
600 | |
601 | /* Check for branch-prediction suffix on opcode mnemonic, strip it off */ | |
602 | n = strlen (args[0]) - 1; | |
603 | branch_predict = 0; | |
604 | bp_bits = 0; | |
605 | if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f')) | |
606 | { | |
607 | /* We could check here to see if the target architecture | |
0e6f2f82 KR |
608 | supports branch prediction, but why bother? The bit will |
609 | just be ignored by processors that don't use it. */ | |
355afbcd KR |
610 | branch_predict = 1; |
611 | bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN; | |
612 | args[0][n - 1] = '\0'; /* Strip suffix from opcode mnemonic */ | |
613 | } | |
614 | ||
615 | /* Look up opcode mnemonic in table and check number of operands. | |
0e6f2f82 KR |
616 | Check that opcode is legal for the target architecture. If all |
617 | looks good, assemble instruction. */ | |
355afbcd KR |
618 | oP = (struct i960_opcode *) hash_find (op_hash, args[0]); |
619 | if (!oP || !targ_has_iclass (oP->iclass)) | |
620 | { | |
48401fcf | 621 | as_bad (_("invalid opcode, \"%s\"."), args[0]); |
355afbcd KR |
622 | |
623 | } | |
624 | else if (n_ops != oP->num_ops) | |
625 | { | |
48401fcf | 626 | as_bad (_("improper number of operands. expecting %d, got %d"), |
c47d388b | 627 | oP->num_ops, n_ops); |
355afbcd KR |
628 | } |
629 | else | |
630 | { | |
631 | switch (oP->format) | |
632 | { | |
633 | case FBRA: | |
634 | case CTRL: | |
635 | ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops); | |
636 | if (oP->format == FBRA) | |
637 | { | |
638 | /* Now generate a 'bno' to same arg */ | |
639 | ctrl_fmt (args[1], BNO | bp_bits, 1); | |
640 | } | |
641 | break; | |
642 | case COBR: | |
643 | case COJ: | |
644 | cobr_fmt (args, oP->opcode | bp_bits, oP); | |
645 | break; | |
646 | case REG: | |
647 | if (branch_predict) | |
648 | { | |
649 | as_warn (bp_error_msg); | |
650 | } | |
651 | reg_fmt (args, oP); | |
652 | break; | |
653 | case MEM1: | |
654 | if (args[0][0] == 'c' && args[0][1] == 'a') | |
655 | { | |
656 | if (branch_predict) | |
657 | { | |
658 | as_warn (bp_error_msg); | |
659 | } | |
660 | mem_fmt (args, oP, 1); | |
661 | break; | |
662 | } | |
663 | case MEM2: | |
664 | case MEM4: | |
665 | case MEM8: | |
666 | case MEM12: | |
667 | case MEM16: | |
668 | if (branch_predict) | |
669 | { | |
670 | as_warn (bp_error_msg); | |
671 | } | |
672 | mem_fmt (args, oP, 0); | |
673 | break; | |
674 | case CALLJ: | |
675 | if (branch_predict) | |
676 | { | |
677 | as_warn (bp_error_msg); | |
678 | } | |
f3d817d8 DM |
679 | /* Output opcode & set up "fixup" (relocation); flag |
680 | relocation as 'callj' type. */ | |
355afbcd KR |
681 | know (oP->num_ops == 1); |
682 | get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1); | |
683 | break; | |
684 | default: | |
685 | BAD_CASE (oP->format); | |
686 | break; | |
fecd2382 | 687 | } |
355afbcd KR |
688 | } |
689 | } /* md_assemble() */ | |
fecd2382 RP |
690 | |
691 | /***************************************************************************** | |
0e6f2f82 KR |
692 | md_number_to_chars: convert a number to target byte order |
693 | ||
694 | *************************************************************************** */ | |
fecd2382 | 695 | void |
355afbcd | 696 | md_number_to_chars (buf, value, n) |
f3d817d8 DM |
697 | char *buf; |
698 | valueT value; | |
699 | int n; | |
fecd2382 | 700 | { |
f3d817d8 DM |
701 | number_to_chars_littleendian (buf, value, n); |
702 | } | |
fecd2382 RP |
703 | |
704 | /***************************************************************************** | |
0e6f2f82 KR |
705 | md_chars_to_number: convert from target byte order to host byte order. |
706 | ||
707 | *************************************************************************** */ | |
fecd2382 | 708 | int |
355afbcd KR |
709 | md_chars_to_number (val, n) |
710 | unsigned char *val; /* Value in target byte order */ | |
711 | int n; /* Number of bytes in the input */ | |
fecd2382 | 712 | { |
355afbcd KR |
713 | int retval; |
714 | ||
715 | for (retval = 0; n--;) | |
716 | { | |
717 | retval <<= 8; | |
718 | retval |= val[n]; | |
719 | } | |
720 | return retval; | |
fecd2382 RP |
721 | } |
722 | ||
723 | ||
724 | #define MAX_LITTLENUMS 6 | |
725 | #define LNUM_SIZE sizeof(LITTLENUM_TYPE) | |
726 | ||
727 | /***************************************************************************** | |
0e6f2f82 KR |
728 | md_atof: convert ascii to floating point |
729 | ||
730 | Turn a string at input_line_pointer into a floating point constant of type | |
731 | 'type', and store the appropriate bytes at *litP. The number of LITTLENUMS | |
732 | emitted is returned at 'sizeP'. An error message is returned, or a pointer | |
733 | to an empty message if OK. | |
734 | ||
735 | Note we call the i386 floating point routine, rather than complicating | |
736 | things with more files or symbolic links. | |
737 | ||
738 | *************************************************************************** */ | |
355afbcd KR |
739 | char * |
740 | md_atof (type, litP, sizeP) | |
741 | int type; | |
742 | char *litP; | |
743 | int *sizeP; | |
fecd2382 | 744 | { |
355afbcd KR |
745 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
746 | LITTLENUM_TYPE *wordP; | |
747 | int prec; | |
748 | char *t; | |
749 | char *atof_ieee (); | |
750 | ||
751 | switch (type) | |
752 | { | |
753 | case 'f': | |
754 | case 'F': | |
755 | prec = 2; | |
756 | break; | |
757 | ||
758 | case 'd': | |
759 | case 'D': | |
760 | prec = 4; | |
761 | break; | |
762 | ||
763 | case 't': | |
764 | case 'T': | |
765 | prec = 5; | |
766 | type = 'x'; /* That's what atof_ieee() understands */ | |
767 | break; | |
768 | ||
769 | default: | |
770 | *sizeP = 0; | |
48401fcf | 771 | return _("Bad call to md_atof()"); |
355afbcd KR |
772 | } |
773 | ||
774 | t = atof_ieee (input_line_pointer, type, words); | |
775 | if (t) | |
776 | { | |
777 | input_line_pointer = t; | |
778 | } | |
779 | ||
780 | *sizeP = prec * LNUM_SIZE; | |
781 | ||
782 | /* Output the LITTLENUMs in REVERSE order in accord with i80960 | |
f3d817d8 DM |
783 | word-order. (Dunno why atof_ieee doesn't do it in the right |
784 | order in the first place -- probably because it's a hack of | |
785 | atof_m68k.) */ | |
355afbcd KR |
786 | |
787 | for (wordP = words + prec - 1; prec--;) | |
788 | { | |
789 | md_number_to_chars (litP, (long) (*wordP--), LNUM_SIZE); | |
790 | litP += sizeof (LITTLENUM_TYPE); | |
791 | } | |
792 | ||
f3d817d8 | 793 | return 0; |
fecd2382 RP |
794 | } |
795 | ||
796 | ||
797 | /***************************************************************************** | |
0e6f2f82 KR |
798 | md_number_to_imm |
799 | ||
800 | *************************************************************************** */ | |
fecd2382 | 801 | void |
355afbcd KR |
802 | md_number_to_imm (buf, val, n) |
803 | char *buf; | |
804 | long val; | |
805 | int n; | |
fecd2382 | 806 | { |
355afbcd | 807 | md_number_to_chars (buf, val, n); |
fecd2382 RP |
808 | } |
809 | ||
810 | ||
811 | /***************************************************************************** | |
0e6f2f82 KR |
812 | md_number_to_disp |
813 | ||
814 | *************************************************************************** */ | |
fecd2382 | 815 | void |
355afbcd KR |
816 | md_number_to_disp (buf, val, n) |
817 | char *buf; | |
818 | long val; | |
819 | int n; | |
fecd2382 | 820 | { |
355afbcd | 821 | md_number_to_chars (buf, val, n); |
fecd2382 RP |
822 | } |
823 | ||
824 | /***************************************************************************** | |
0e6f2f82 KR |
825 | md_number_to_field: |
826 | ||
827 | Stick a value (an address fixup) into a bit field of | |
828 | previously-generated instruction. | |
829 | ||
830 | *************************************************************************** */ | |
fecd2382 | 831 | void |
355afbcd KR |
832 | md_number_to_field (instrP, val, bfixP) |
833 | char *instrP; /* Pointer to instruction to be fixed */ | |
834 | long val; /* Address fixup value */ | |
835 | bit_fixS *bfixP; /* Description of bit field to be fixed up */ | |
fecd2382 | 836 | { |
355afbcd KR |
837 | int numbits; /* Length of bit field to be fixed */ |
838 | long instr; /* 32-bit instruction to be fixed-up */ | |
839 | long sign; /* 0 or -1, according to sign bit of 'val' */ | |
840 | ||
0e6f2f82 | 841 | /* Convert instruction back to host byte order. */ |
355afbcd KR |
842 | instr = md_chars_to_number (instrP, 4); |
843 | ||
0e6f2f82 KR |
844 | /* Surprise! -- we stored the number of bits to be modified rather |
845 | than a pointer to a structure. */ | |
355afbcd KR |
846 | numbits = (int) bfixP; |
847 | if (numbits == 1) | |
848 | { | |
849 | /* This is a no-op, stuck here by reloc_callj() */ | |
850 | return; | |
851 | } | |
852 | ||
853 | know ((numbits == 13) || (numbits == 24)); | |
854 | ||
0e6f2f82 KR |
855 | /* Propagate sign bit of 'val' for the given number of bits. Result |
856 | should be all 0 or all 1. */ | |
355afbcd KR |
857 | sign = val >> ((int) numbits - 1); |
858 | if (((val < 0) && (sign != -1)) | |
859 | || ((val > 0) && (sign != 0))) | |
860 | { | |
48401fcf | 861 | as_bad (_("Fixup of %ld too large for field width of %d"), |
355afbcd KR |
862 | val, numbits); |
863 | } | |
864 | else | |
865 | { | |
866 | /* Put bit field into instruction and write back in target | |
0e6f2f82 KR |
867 | * byte order. |
868 | */ | |
355afbcd KR |
869 | val &= ~(-1 << (int) numbits); /* Clear unused sign bits */ |
870 | instr |= val; | |
871 | md_number_to_chars (instrP, instr, 4); | |
872 | } | |
873 | } /* md_number_to_field() */ | |
f3d817d8 | 874 | \f |
0e6f2f82 | 875 | |
fecd2382 | 876 | /***************************************************************************** |
0e6f2f82 KR |
877 | md_parse_option |
878 | Invocation line includes a switch not recognized by the base assembler. | |
879 | See if it's a processor-specific option. For the 960, these are: | |
880 | ||
881 | -norelax: | |
882 | Conditional branch instructions that require displacements | |
883 | greater than 13 bits (or that have external targets) should | |
884 | generate errors. The default is to replace each such | |
885 | instruction with the corresponding compare (or chkbit) and | |
886 | branch instructions. Note that the Intel "j" cobr directives | |
887 | are ALWAYS "de-optimized" in this way when necessary, | |
888 | regardless of the setting of this option. | |
889 | ||
890 | -b: | |
891 | Add code to collect information about branches taken, for | |
892 | later optimization of branch prediction bits by a separate | |
893 | tool. COBR and CNTL format instructions have branch | |
894 | prediction bits (in the CX architecture); if "BR" represents | |
895 | an instruction in one of these classes, the following rep- | |
896 | resents the code generated by the assembler: | |
897 | ||
898 | call <increment routine> | |
899 | .word 0 # pre-counter | |
900 | Label: BR | |
901 | call <increment routine> | |
902 | .word 0 # post-counter | |
903 | ||
904 | A table of all such "Labels" is also generated. | |
905 | ||
906 | ||
907 | -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA: | |
908 | Select the 80960 architecture. Instructions or features not | |
909 | supported by the selected architecture cause fatal errors. | |
910 | The default is to generate code for any instruction or feature | |
911 | that is supported by SOME version of the 960 (even if this | |
912 | means mixing architectures!). | |
913 | ||
914 | ****************************************************************************/ | |
f3d817d8 DM |
915 | |
916 | CONST char *md_shortopts = "A:b"; | |
0e6f2f82 KR |
917 | struct option md_longopts[] = |
918 | { | |
f3d817d8 DM |
919 | #define OPTION_LINKRELAX (OPTION_MD_BASE) |
920 | {"linkrelax", no_argument, NULL, OPTION_LINKRELAX}, | |
0e6f2f82 | 921 | {"link-relax", no_argument, NULL, OPTION_LINKRELAX}, |
f3d817d8 DM |
922 | #define OPTION_NORELAX (OPTION_MD_BASE + 1) |
923 | {"norelax", no_argument, NULL, OPTION_NORELAX}, | |
0e6f2f82 | 924 | {"no-relax", no_argument, NULL, OPTION_NORELAX}, |
f3d817d8 DM |
925 | {NULL, no_argument, NULL, 0} |
926 | }; | |
0e6f2f82 KR |
927 | size_t md_longopts_size = sizeof (md_longopts); |
928 | ||
929 | struct tabentry | |
930 | { | |
931 | char *flag; | |
932 | int arch; | |
933 | }; | |
934 | static const struct tabentry arch_tab[] = | |
935 | { | |
936 | {"KA", ARCH_KA}, | |
937 | {"KB", ARCH_KB}, | |
938 | {"SA", ARCH_KA}, /* Synonym for KA */ | |
939 | {"SB", ARCH_KB}, /* Synonym for KB */ | |
940 | {"KC", ARCH_MC}, /* Synonym for MC */ | |
941 | {"MC", ARCH_MC}, | |
942 | {"CA", ARCH_CA}, | |
48401fcf | 943 | {"JX", ARCH_JX}, |
f9e90c2e | 944 | {"HX", ARCH_HX}, |
0e6f2f82 KR |
945 | {NULL, 0} |
946 | }; | |
f3d817d8 | 947 | |
fecd2382 | 948 | int |
f3d817d8 DM |
949 | md_parse_option (c, arg) |
950 | int c; | |
951 | char *arg; | |
fecd2382 | 952 | { |
f3d817d8 | 953 | switch (c) |
355afbcd | 954 | { |
f3d817d8 | 955 | case OPTION_LINKRELAX: |
355afbcd | 956 | linkrelax = 1; |
0e6f2f82 | 957 | flag_keep_locals = 1; |
f3d817d8 DM |
958 | break; |
959 | ||
960 | case OPTION_NORELAX: | |
355afbcd | 961 | norelax = 1; |
f3d817d8 | 962 | break; |
355afbcd | 963 | |
f3d817d8 | 964 | case 'b': |
355afbcd | 965 | instrument_branches = 1; |
f3d817d8 | 966 | break; |
355afbcd | 967 | |
f3d817d8 DM |
968 | case 'A': |
969 | { | |
0e6f2f82 | 970 | const struct tabentry *tp; |
f3d817d8 DM |
971 | char *p = arg; |
972 | ||
973 | for (tp = arch_tab; tp->flag != NULL; tp++) | |
0e6f2f82 KR |
974 | if (!strcmp (p, tp->flag)) |
975 | break; | |
f3d817d8 DM |
976 | |
977 | if (tp->flag == NULL) | |
978 | { | |
48401fcf | 979 | as_bad (_("invalid architecture %s"), p); |
f3d817d8 DM |
980 | return 0; |
981 | } | |
982 | else | |
0e6f2f82 | 983 | architecture = tp->arch; |
f3d817d8 DM |
984 | } |
985 | break; | |
355afbcd | 986 | |
f3d817d8 | 987 | default: |
355afbcd KR |
988 | return 0; |
989 | } | |
f3d817d8 | 990 | |
355afbcd | 991 | return 1; |
fecd2382 RP |
992 | } |
993 | ||
f3d817d8 DM |
994 | void |
995 | md_show_usage (stream) | |
996 | FILE *stream; | |
997 | { | |
0e6f2f82 | 998 | int i; |
48401fcf | 999 | fprintf (stream, _("I960 options:\n")); |
0e6f2f82 KR |
1000 | for (i = 0; arch_tab[i].flag; i++) |
1001 | fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag); | |
48401fcf | 1002 | fprintf (stream, _("\n\ |
f3d817d8 DM |
1003 | specify variant of 960 architecture\n\ |
1004 | -b add code to collect statistics about branches taken\n\ | |
0e6f2f82 KR |
1005 | -link-relax preserve individual alignment directives so linker\n\ |
1006 | can do relaxing (b.out format only)\n\ | |
1007 | -no-relax don't alter compare-and-branch instructions for\n\ | |
48401fcf | 1008 | long displacements\n")); |
f3d817d8 DM |
1009 | } |
1010 | \f | |
1011 | ||
0e6f2f82 | 1012 | #ifndef BFD_ASSEMBLER |
fecd2382 | 1013 | /***************************************************************************** |
0e6f2f82 KR |
1014 | md_convert_frag: |
1015 | Called by base assembler after address relaxation is finished: modify | |
1016 | variable fragments according to how much relaxation was done. | |
1017 | ||
1018 | If the fragment substate is still 1, a 13-bit displacement was enough | |
1019 | to reach the symbol in question. Set up an address fixup, but otherwise | |
1020 | leave the cobr instruction alone. | |
1021 | ||
1022 | If the fragment substate is 2, a 13-bit displacement was not enough. | |
1023 | Replace the cobr with a two instructions (a compare and a branch). | |
1024 | ||
1025 | *************************************************************************** */ | |
fecd2382 | 1026 | void |
0e6f2f82 | 1027 | md_convert_frag (headers, seg, fragP) |
355afbcd | 1028 | object_headers *headers; |
0e6f2f82 | 1029 | segT seg; |
355afbcd | 1030 | fragS *fragP; |
fecd2382 | 1031 | { |
355afbcd KR |
1032 | fixS *fixP; /* Structure describing needed address fix */ |
1033 | ||
1034 | switch (fragP->fr_subtype) | |
1035 | { | |
1036 | case 1: | |
1037 | /* LEAVE SINGLE COBR INSTRUCTION */ | |
1038 | fixP = fix_new (fragP, | |
1039 | fragP->fr_opcode - fragP->fr_literal, | |
1040 | 4, | |
1041 | fragP->fr_symbol, | |
355afbcd KR |
1042 | fragP->fr_offset, |
1043 | 1, | |
1044 | NO_RELOC); | |
1045 | ||
1046 | fixP->fx_bit_fixP = (bit_fixS *) 13; /* size of bit field */ | |
1047 | break; | |
1048 | case 2: | |
1049 | /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */ | |
1050 | relax_cobr (fragP); | |
1051 | break; | |
1052 | default: | |
1053 | BAD_CASE (fragP->fr_subtype); | |
1054 | break; | |
1055 | } | |
fecd2382 RP |
1056 | } |
1057 | ||
1058 | /***************************************************************************** | |
0e6f2f82 KR |
1059 | md_estimate_size_before_relax: How much does it look like *fragP will grow? |
1060 | ||
1061 | Called by base assembler just before address relaxation. | |
1062 | Return the amount by which the fragment will grow. | |
1063 | ||
1064 | Any symbol that is now undefined will not become defined; cobr's | |
1065 | based on undefined symbols will have to be replaced with a compare | |
1066 | instruction and a branch instruction, and the code fragment will grow | |
1067 | by 4 bytes. | |
1068 | ||
1069 | *************************************************************************** */ | |
fecd2382 | 1070 | int |
355afbcd KR |
1071 | md_estimate_size_before_relax (fragP, segment_type) |
1072 | register fragS *fragP; | |
1073 | register segT segment_type; | |
fecd2382 | 1074 | { |
355afbcd | 1075 | /* If symbol is undefined in this segment, go to "relaxed" state |
0e6f2f82 | 1076 | (compare and branch instructions instead of cobr) right now. */ |
355afbcd KR |
1077 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type) |
1078 | { | |
1079 | relax_cobr (fragP); | |
1080 | return 4; | |
1081 | } | |
1082 | return 0; | |
1083 | } /* md_estimate_size_before_relax() */ | |
fecd2382 RP |
1084 | |
1085 | ||
1086 | /***************************************************************************** | |
0e6f2f82 KR |
1087 | md_ri_to_chars: |
1088 | This routine exists in order to overcome machine byte-order problems | |
1089 | when dealing with bit-field entries in the relocation_info struct. | |
1090 | ||
1091 | But relocation info will be used on the host machine only (only | |
1092 | executable code is actually downloaded to the i80960). Therefore, | |
1093 | we leave it in host byte order. | |
1094 | ||
1095 | The above comment is no longer true. This routine now really | |
1096 | does do the reordering (Ian Taylor 28 Aug 92). | |
1097 | ||
1098 | *************************************************************************** */ | |
355afbcd KR |
1099 | void |
1100 | md_ri_to_chars (where, ri) | |
1101 | char *where; | |
1102 | struct relocation_info *ri; | |
fecd2382 | 1103 | { |
355afbcd KR |
1104 | md_number_to_chars (where, ri->r_address, |
1105 | sizeof (ri->r_address)); | |
1106 | where[4] = ri->r_index & 0x0ff; | |
1107 | where[5] = (ri->r_index >> 8) & 0x0ff; | |
1108 | where[6] = (ri->r_index >> 16) & 0x0ff; | |
1109 | where[7] = ((ri->r_pcrel << 0) | |
1110 | | (ri->r_length << 1) | |
1111 | | (ri->r_extern << 3) | |
1112 | | (ri->r_bsr << 4) | |
1113 | | (ri->r_disp << 5) | |
1114 | | (ri->r_callj << 6)); | |
f3d817d8 | 1115 | } |
fecd2382 | 1116 | |
fecd2382 RP |
1117 | #ifndef WORKING_DOT_WORD |
1118 | ||
1119 | int md_short_jump_size = 0; | |
1120 | int md_long_jump_size = 0; | |
1121 | ||
355afbcd KR |
1122 | void |
1123 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
1124 | char *ptr; | |
c47d388b ME |
1125 | addressT from_addr; |
1126 | addressT to_addr; | |
355afbcd KR |
1127 | fragS *frag; |
1128 | symbolS *to_symbol; | |
fecd2382 | 1129 | { |
48401fcf | 1130 | as_fatal (_("failed sanity check.")); |
fecd2382 RP |
1131 | } |
1132 | ||
1133 | void | |
355afbcd KR |
1134 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) |
1135 | char *ptr; | |
c47d388b | 1136 | addressT from_addr, to_addr; |
355afbcd KR |
1137 | fragS *frag; |
1138 | symbolS *to_symbol; | |
fecd2382 | 1139 | { |
48401fcf | 1140 | as_fatal (_("failed sanity check.")); |
fecd2382 | 1141 | } |
355afbcd | 1142 | |
fecd2382 | 1143 | #endif |
0e6f2f82 | 1144 | #endif /* BFD_ASSEMBLER */ |
fecd2382 | 1145 | \f |
0e6f2f82 | 1146 | /* FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER */ |
fecd2382 RP |
1147 | |
1148 | /***************************************************************************** | |
0e6f2f82 KR |
1149 | brcnt_emit: Emit code to increment inline branch counter. |
1150 | ||
1151 | See the comments above the declaration of 'br_cnt' for details on | |
1152 | branch-prediction instrumentation. | |
1153 | *************************************************************************** */ | |
fecd2382 | 1154 | static void |
355afbcd | 1155 | brcnt_emit () |
fecd2382 | 1156 | { |
355afbcd KR |
1157 | ctrl_fmt (BR_CNT_FUNC, CALL, 1); /* Emit call to "increment" routine */ |
1158 | emit (0); /* Emit inline counter to be incremented */ | |
fecd2382 RP |
1159 | } |
1160 | ||
1161 | /***************************************************************************** | |
0e6f2f82 KR |
1162 | brlab_next: generate the next branch local label |
1163 | ||
1164 | See the comments above the declaration of 'br_cnt' for details on | |
1165 | branch-prediction instrumentation. | |
1166 | *************************************************************************** */ | |
fecd2382 | 1167 | static char * |
355afbcd | 1168 | brlab_next () |
fecd2382 | 1169 | { |
355afbcd KR |
1170 | static char buf[20]; |
1171 | ||
1172 | sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++); | |
1173 | return buf; | |
fecd2382 RP |
1174 | } |
1175 | ||
1176 | /***************************************************************************** | |
0e6f2f82 KR |
1177 | brtab_emit: generate the fetch-prediction branch table. |
1178 | ||
1179 | See the comments above the declaration of 'br_cnt' for details on | |
1180 | branch-prediction instrumentation. | |
1181 | ||
1182 | The code emitted here would be functionally equivalent to the following | |
1183 | example assembler source. | |
1184 | ||
1185 | .data | |
1186 | .align 2 | |
1187 | BR_TAB_NAME: | |
1188 | .word 0 # link to next table | |
1189 | .word 3 # length of table | |
1190 | .word LBRANCH0 # 1st entry in table proper | |
1191 | .word LBRANCH1 | |
1192 | .word LBRANCH2 | |
1193 | **************************************************************************** */ | |
fecd2382 | 1194 | void |
355afbcd | 1195 | brtab_emit () |
fecd2382 | 1196 | { |
355afbcd KR |
1197 | int i; |
1198 | char buf[20]; | |
1199 | char *p; /* Where the binary was output to */ | |
0e6f2f82 KR |
1200 | /* Pointer to description of deferred address fixup. */ |
1201 | fixS *fixP; | |
355afbcd KR |
1202 | |
1203 | if (!instrument_branches) | |
1204 | { | |
1205 | return; | |
1206 | } | |
1207 | ||
0e6f2f82 | 1208 | subseg_set (data_section, 0); /* .data */ |
48401fcf | 1209 | frag_align (2, 0, 0); /* .align 2 */ |
355afbcd KR |
1210 | record_alignment (now_seg, 2); |
1211 | colon (BR_TAB_NAME); /* BR_TAB_NAME: */ | |
0e6f2f82 KR |
1212 | emit (0); /* .word 0 #link to next table */ |
1213 | emit (br_cnt); /* .word n #length of table */ | |
355afbcd KR |
1214 | |
1215 | for (i = 0; i < br_cnt; i++) | |
1216 | { | |
1217 | sprintf (buf, "%s%d", BR_LABEL_BASE, i); | |
1218 | p = emit (0); | |
1219 | fixP = fix_new (frag_now, | |
1220 | p - frag_now->fr_literal, | |
1221 | 4, | |
1222 | symbol_find (buf), | |
1223 | 0, | |
1224 | 0, | |
355afbcd | 1225 | NO_RELOC); |
355afbcd | 1226 | } |
fecd2382 RP |
1227 | } |
1228 | ||
1229 | /***************************************************************************** | |
0e6f2f82 KR |
1230 | cobr_fmt: generate a COBR-format instruction |
1231 | ||
1232 | *************************************************************************** */ | |
fecd2382 | 1233 | static |
355afbcd KR |
1234 | void |
1235 | cobr_fmt (arg, opcode, oP) | |
0e6f2f82 KR |
1236 | /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */ |
1237 | char *arg[]; | |
1238 | /* Opcode, with branch-prediction bits already set if necessary. */ | |
1239 | long opcode; | |
1240 | /* Pointer to description of instruction. */ | |
355afbcd | 1241 | struct i960_opcode *oP; |
fecd2382 | 1242 | { |
355afbcd KR |
1243 | long instr; /* 32-bit instruction */ |
1244 | struct regop regop; /* Description of register operand */ | |
1245 | int n; /* Number of operands */ | |
1246 | int var_frag; /* 1 if varying length code fragment should | |
0e6f2f82 KR |
1247 | * be emitted; 0 if an address fix |
1248 | * should be emitted. | |
fecd2382 | 1249 | */ |
355afbcd KR |
1250 | |
1251 | instr = opcode; | |
1252 | n = oP->num_ops; | |
1253 | ||
1254 | if (n >= 1) | |
1255 | { | |
1256 | /* First operand (if any) of a COBR is always a register | |
0e6f2f82 | 1257 | operand. Parse it. */ |
355afbcd KR |
1258 | parse_regop (®op, arg[1], oP->operand[0]); |
1259 | instr |= (regop.n << 19) | (regop.mode << 13); | |
1260 | } | |
1261 | if (n >= 2) | |
1262 | { | |
1263 | /* Second operand (if any) of a COBR is always a register | |
0e6f2f82 KR |
1264 | operand. Parse it. */ |
1265 | parse_regop (®op, arg[2], oP->operand[1]); | |
355afbcd KR |
1266 | instr |= (regop.n << 14) | regop.special; |
1267 | } | |
1268 | ||
1269 | ||
1270 | if (n < 3) | |
1271 | { | |
1272 | emit (instr); | |
1273 | ||
1274 | } | |
1275 | else | |
1276 | { | |
1277 | if (instrument_branches) | |
1278 | { | |
1279 | brcnt_emit (); | |
1280 | colon (brlab_next ()); | |
fecd2382 | 1281 | } |
355afbcd | 1282 | |
0e6f2f82 KR |
1283 | /* A third operand to a COBR is always a displacement. Parse |
1284 | it; if it's relaxable (a cobr "j" directive, or any cobr | |
1285 | other than bbs/bbc when the "-norelax" option is not in use) | |
1286 | set up a variable code fragment; otherwise set up an address | |
1287 | fix. */ | |
355afbcd KR |
1288 | var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */ |
1289 | get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0); | |
1290 | ||
1291 | if (instrument_branches) | |
1292 | { | |
1293 | brcnt_emit (); | |
fecd2382 | 1294 | } |
355afbcd KR |
1295 | } |
1296 | } /* cobr_fmt() */ | |
fecd2382 RP |
1297 | |
1298 | ||
1299 | /***************************************************************************** | |
0e6f2f82 KR |
1300 | ctrl_fmt: generate a CTRL-format instruction |
1301 | ||
1302 | *************************************************************************** */ | |
fecd2382 | 1303 | static |
355afbcd KR |
1304 | void |
1305 | ctrl_fmt (targP, opcode, num_ops) | |
1306 | char *targP; /* Pointer to text of lone operand (if any) */ | |
1307 | long opcode; /* Template of instruction */ | |
1308 | int num_ops; /* Number of operands */ | |
fecd2382 | 1309 | { |
355afbcd | 1310 | int instrument; /* TRUE iff we should add instrumentation to track |
0e6f2f82 KR |
1311 | * how often the branch is taken |
1312 | */ | |
355afbcd KR |
1313 | |
1314 | ||
1315 | if (num_ops == 0) | |
1316 | { | |
1317 | emit (opcode); /* Output opcode */ | |
1318 | } | |
1319 | else | |
1320 | { | |
1321 | ||
1322 | instrument = instrument_branches && (opcode != CALL) | |
1323 | && (opcode != B) && (opcode != RET) && (opcode != BAL); | |
1324 | ||
1325 | if (instrument) | |
1326 | { | |
1327 | brcnt_emit (); | |
1328 | colon (brlab_next ()); | |
1329 | } | |
1330 | ||
1331 | /* The operand MUST be an ip-relative displacment. Parse it | |
0e6f2f82 KR |
1332 | * and set up address fix for the instruction we just output. |
1333 | */ | |
355afbcd KR |
1334 | get_cdisp (targP, "CTRL", opcode, 24, 0, 0); |
1335 | ||
1336 | if (instrument) | |
1337 | { | |
1338 | brcnt_emit (); | |
fecd2382 | 1339 | } |
355afbcd KR |
1340 | } |
1341 | ||
fecd2382 RP |
1342 | } |
1343 | ||
1344 | ||
1345 | /***************************************************************************** | |
0e6f2f82 KR |
1346 | emit: output instruction binary |
1347 | ||
1348 | Output instruction binary, in target byte order, 4 bytes at a time. | |
1349 | Return pointer to where it was placed. | |
1350 | ||
1351 | *************************************************************************** */ | |
fecd2382 | 1352 | static |
355afbcd KR |
1353 | char * |
1354 | emit (instr) | |
1355 | long instr; /* Word to be output, host byte order */ | |
fecd2382 | 1356 | { |
355afbcd KR |
1357 | char *toP; /* Where to output it */ |
1358 | ||
1359 | toP = frag_more (4); /* Allocate storage */ | |
1360 | md_number_to_chars (toP, instr, 4); /* Convert to target byte order */ | |
1361 | return toP; | |
fecd2382 RP |
1362 | } |
1363 | ||
1364 | ||
1365 | /***************************************************************************** | |
0e6f2f82 KR |
1366 | get_args: break individual arguments out of comma-separated list |
1367 | ||
1368 | Input assumptions: | |
1369 | - all comments and labels have been removed | |
1370 | - all strings of whitespace have been collapsed to a single blank. | |
1371 | - all character constants ('x') have been replaced with decimal | |
1372 | ||
1373 | Output: | |
1374 | args[0] is untouched. args[1] points to first operand, etc. All args: | |
1375 | - are NULL-terminated | |
1376 | - contain no whitespace | |
1377 | ||
1378 | Return value: | |
1379 | Number of operands (0,1,2, or 3) or -1 on error. | |
1380 | ||
1381 | *************************************************************************** */ | |
355afbcd KR |
1382 | static int |
1383 | get_args (p, args) | |
0e6f2f82 KR |
1384 | /* Pointer to comma-separated operands; MUCKED BY US */ |
1385 | register char *p; | |
1386 | /* Output arg: pointers to operands placed in args[1-3]. MUST | |
1387 | ACCOMMODATE 4 ENTRIES (args[0-3]). */ | |
1388 | char *args[]; | |
fecd2382 | 1389 | { |
355afbcd KR |
1390 | register int n; /* Number of operands */ |
1391 | register char *to; | |
355afbcd KR |
1392 | |
1393 | /* Skip lead white space */ | |
1394 | while (*p == ' ') | |
1395 | { | |
1396 | p++; | |
1397 | } | |
1398 | ||
1399 | if (*p == '\0') | |
1400 | { | |
1401 | return 0; | |
1402 | } | |
1403 | ||
1404 | n = 1; | |
1405 | args[1] = p; | |
1406 | ||
1407 | /* Squeze blanks out by moving non-blanks toward start of string. | |
0e6f2f82 KR |
1408 | * Isolate operands, whenever comma is found. |
1409 | */ | |
355afbcd KR |
1410 | to = p; |
1411 | while (*p != '\0') | |
1412 | { | |
1413 | ||
0e6f2f82 KR |
1414 | if (*p == ' ' |
1415 | && (! isalnum (p[1]) || ! isalnum (p[-1]))) | |
355afbcd KR |
1416 | { |
1417 | p++; | |
1418 | ||
1419 | } | |
1420 | else if (*p == ',') | |
1421 | { | |
1422 | ||
1423 | /* Start of operand */ | |
1424 | if (n == 3) | |
1425 | { | |
48401fcf | 1426 | as_bad (_("too many operands")); |
355afbcd KR |
1427 | return -1; |
1428 | } | |
1429 | *to++ = '\0'; /* Terminate argument */ | |
1430 | args[++n] = to; /* Start next argument */ | |
1431 | p++; | |
1432 | ||
fecd2382 | 1433 | } |
355afbcd KR |
1434 | else |
1435 | { | |
1436 | *to++ = *p++; | |
1437 | } | |
1438 | } | |
1439 | *to = '\0'; | |
1440 | return n; | |
fecd2382 RP |
1441 | } |
1442 | ||
1443 | ||
1444 | /***************************************************************************** | |
0e6f2f82 KR |
1445 | get_cdisp: handle displacement for a COBR or CTRL instruction. |
1446 | ||
1447 | Parse displacement for a COBR or CTRL instruction. | |
1448 | ||
1449 | If successful, output the instruction opcode and set up for it, | |
1450 | depending on the arg 'var_frag', either: | |
1451 | o an address fixup to be done when all symbol values are known, or | |
1452 | o a varying length code fragment, with address fixup info. This | |
1453 | will be done for cobr instructions that may have to be relaxed | |
1454 | in to compare/branch instructions (8 bytes) if the final | |
1455 | address displacement is greater than 13 bits. | |
1456 | ||
1457 | ****************************************************************************/ | |
fecd2382 | 1458 | static |
355afbcd KR |
1459 | void |
1460 | get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj) | |
c47d388b ME |
1461 | /* displacement as specified in source instruction */ |
1462 | char *dispP; | |
1463 | /* "COBR" or "CTRL" (for use in error message) */ | |
1464 | char *ifmtP; | |
1465 | /* Instruction needing the displacement */ | |
1466 | long instr; | |
1467 | /* # bits of displacement (13 for COBR, 24 for CTRL) */ | |
1468 | int numbits; | |
1469 | /* 1 if varying length code fragment should be emitted; | |
0e6f2f82 | 1470 | * 0 if an address fix should be emitted. |
c47d388b ME |
1471 | */ |
1472 | int var_frag; | |
1473 | /* 1 if callj relocation should be done; else 0 */ | |
1474 | int callj; | |
fecd2382 | 1475 | { |
355afbcd KR |
1476 | expressionS e; /* Parsed expression */ |
1477 | fixS *fixP; /* Structure describing needed address fix */ | |
1478 | char *outP; /* Where instruction binary is output to */ | |
1479 | ||
1480 | fixP = NULL; | |
1481 | ||
5ac34ac3 ILT |
1482 | parse_expr (dispP, &e); |
1483 | switch (e.X_op) | |
355afbcd | 1484 | { |
5ac34ac3 | 1485 | case O_illegal: |
48401fcf | 1486 | as_bad (_("expression syntax error")); |
355afbcd | 1487 | |
5ac34ac3 | 1488 | case O_symbol: |
0e6f2f82 | 1489 | if (S_GET_SEGMENT (e.X_add_symbol) == now_seg |
5ac34ac3 | 1490 | || S_GET_SEGMENT (e.X_add_symbol) == undefined_section) |
0e6f2f82 | 1491 | { |
5ac34ac3 ILT |
1492 | if (var_frag) |
1493 | { | |
0e6f2f82 | 1494 | outP = frag_more (8); /* Allocate worst-case storage */ |
5ac34ac3 ILT |
1495 | md_number_to_chars (outP, instr, 4); |
1496 | frag_variant (rs_machine_dependent, 4, 4, 1, | |
0e6f2f82 | 1497 | adds (e), offs (e), outP); |
5ac34ac3 ILT |
1498 | } |
1499 | else | |
1500 | { | |
1501 | /* Set up a new fix structure, so address can be updated | |
1502 | * when all symbol values are known. | |
1503 | */ | |
1504 | outP = emit (instr); | |
1505 | fixP = fix_new (frag_now, | |
1506 | outP - frag_now->fr_literal, | |
1507 | 4, | |
1508 | adds (e), | |
1509 | offs (e), | |
1510 | 1, | |
1511 | NO_RELOC); | |
1512 | ||
f3d817d8 | 1513 | fixP->fx_tcbit = callj; |
5ac34ac3 ILT |
1514 | |
1515 | /* We want to modify a bit field when the address is | |
1516 | * known. But we don't need all the garbage in the | |
1517 | * bit_fix structure. So we're going to lie and store | |
1518 | * the number of bits affected instead of a pointer. | |
1519 | */ | |
1520 | fixP->fx_bit_fixP = (bit_fixS *) numbits; | |
1521 | } | |
355afbcd KR |
1522 | } |
1523 | else | |
48401fcf | 1524 | as_bad (_("attempt to branch into different segment")); |
355afbcd KR |
1525 | break; |
1526 | ||
1527 | default: | |
48401fcf | 1528 | as_bad (_("target of %s instruction must be a label"), ifmtP); |
355afbcd KR |
1529 | break; |
1530 | } | |
fecd2382 RP |
1531 | } |
1532 | ||
1533 | ||
1534 | /***************************************************************************** | |
0e6f2f82 KR |
1535 | get_ispec: parse a memory operand for an index specification |
1536 | ||
1537 | Here, an "index specification" is taken to be anything surrounded | |
1538 | by square brackets and NOT followed by anything else. | |
1539 | ||
1540 | If it's found, detach it from the input string, remove the surrounding | |
1541 | square brackets, and return a pointer to it. Otherwise, return NULL. | |
1542 | ||
1543 | *************************************************************************** */ | |
fecd2382 | 1544 | static |
355afbcd KR |
1545 | char * |
1546 | get_ispec (textP) | |
0e6f2f82 KR |
1547 | /* Pointer to memory operand from source instruction, no white space. */ |
1548 | char *textP; | |
fecd2382 | 1549 | { |
0e6f2f82 KR |
1550 | /* Points to start of index specification. */ |
1551 | char *start; | |
1552 | /* Points to end of index specification. */ | |
1553 | char *end; | |
355afbcd | 1554 | |
0e6f2f82 | 1555 | /* Find opening square bracket, if any. */ |
355afbcd KR |
1556 | start = strchr (textP, '['); |
1557 | ||
1558 | if (start != NULL) | |
1559 | { | |
1560 | ||
1561 | /* Eliminate '[', detach from rest of operand */ | |
1562 | *start++ = '\0'; | |
1563 | ||
1564 | end = strchr (start, ']'); | |
1565 | ||
1566 | if (end == NULL) | |
1567 | { | |
48401fcf | 1568 | as_bad (_("unmatched '['")); |
355afbcd KR |
1569 | |
1570 | } | |
1571 | else | |
1572 | { | |
1573 | /* Eliminate ']' and make sure it was the last thing | |
0e6f2f82 KR |
1574 | * in the string. |
1575 | */ | |
355afbcd KR |
1576 | *end = '\0'; |
1577 | if (*(end + 1) != '\0') | |
1578 | { | |
48401fcf | 1579 | as_bad (_("garbage after index spec ignored")); |
355afbcd | 1580 | } |
fecd2382 | 1581 | } |
355afbcd KR |
1582 | } |
1583 | return start; | |
fecd2382 RP |
1584 | } |
1585 | ||
1586 | /***************************************************************************** | |
0e6f2f82 KR |
1587 | get_regnum: |
1588 | ||
1589 | Look up a (suspected) register name in the register table and return the | |
1590 | associated register number (or -1 if not found). | |
1591 | ||
1592 | *************************************************************************** */ | |
fecd2382 | 1593 | static |
355afbcd KR |
1594 | int |
1595 | get_regnum (regname) | |
1596 | char *regname; /* Suspected register name */ | |
fecd2382 | 1597 | { |
355afbcd KR |
1598 | int *rP; |
1599 | ||
1600 | rP = (int *) hash_find (reg_hash, regname); | |
1601 | return (rP == NULL) ? -1 : *rP; | |
fecd2382 RP |
1602 | } |
1603 | ||
1604 | ||
1605 | /***************************************************************************** | |
0e6f2f82 KR |
1606 | i_scan: perform lexical scan of ascii assembler instruction. |
1607 | ||
1608 | Input assumptions: | |
1609 | - input string is an i80960 instruction (not a pseudo-op) | |
1610 | - all comments and labels have been removed | |
1611 | - all strings of whitespace have been collapsed to a single blank. | |
1612 | ||
1613 | Output: | |
1614 | args[0] points to opcode, other entries point to operands. All strings: | |
1615 | - are NULL-terminated | |
1616 | - contain no whitespace | |
1617 | - have character constants ('x') replaced with a decimal number | |
1618 | ||
1619 | Return value: | |
1620 | Number of operands (0,1,2, or 3) or -1 on error. | |
1621 | ||
1622 | *************************************************************************** */ | |
355afbcd KR |
1623 | static int |
1624 | i_scan (iP, args) | |
0e6f2f82 KR |
1625 | /* Pointer to ascii instruction; MUCKED BY US. */ |
1626 | register char *iP; | |
1627 | /* Output arg: pointers to opcode and operands placed here. MUST | |
1628 | ACCOMMODATE 4 ENTRIES. */ | |
1629 | char *args[]; | |
fecd2382 | 1630 | { |
355afbcd KR |
1631 | |
1632 | /* Isolate opcode */ | |
1633 | if (*(iP) == ' ') | |
1634 | { | |
1635 | iP++; | |
1636 | } /* Skip lead space, if any */ | |
1637 | args[0] = iP; | |
1638 | for (; *iP != ' '; iP++) | |
1639 | { | |
1640 | if (*iP == '\0') | |
1641 | { | |
1642 | /* There are no operands */ | |
1643 | if (args[0] == iP) | |
1644 | { | |
1645 | /* We never moved: there was no opcode either! */ | |
48401fcf | 1646 | as_bad (_("missing opcode")); |
355afbcd KR |
1647 | return -1; |
1648 | } | |
1649 | return 0; | |
fecd2382 | 1650 | } |
355afbcd KR |
1651 | } |
1652 | *iP++ = '\0'; /* Terminate opcode */ | |
1653 | return (get_args (iP, args)); | |
1654 | } /* i_scan() */ | |
fecd2382 RP |
1655 | |
1656 | ||
1657 | /***************************************************************************** | |
0e6f2f82 KR |
1658 | mem_fmt: generate a MEMA- or MEMB-format instruction |
1659 | ||
1660 | *************************************************************************** */ | |
355afbcd KR |
1661 | static void |
1662 | mem_fmt (args, oP, callx) | |
1663 | char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */ | |
1664 | struct i960_opcode *oP; /* Pointer to description of instruction */ | |
1665 | int callx; /* Is this a callx opcode */ | |
fecd2382 | 1666 | { |
355afbcd KR |
1667 | int i; /* Loop counter */ |
1668 | struct regop regop; /* Description of register operand */ | |
1669 | char opdesc; /* Operand descriptor byte */ | |
1670 | memS instr; /* Description of binary to be output */ | |
1671 | char *outP; /* Where the binary was output to */ | |
1672 | expressionS expr; /* Parsed expression */ | |
0e6f2f82 KR |
1673 | /* ->description of deferred address fixup */ |
1674 | fixS *fixP; | |
355afbcd | 1675 | |
f3d817d8 DM |
1676 | #ifdef OBJ_COFF |
1677 | /* COFF support isn't in place yet for callx relaxing. */ | |
1678 | callx = 0; | |
1679 | #endif | |
1680 | ||
355afbcd KR |
1681 | memset (&instr, '\0', sizeof (memS)); |
1682 | instr.opcode = oP->opcode; | |
1683 | ||
1684 | /* Process operands. */ | |
1685 | for (i = 1; i <= oP->num_ops; i++) | |
1686 | { | |
1687 | opdesc = oP->operand[i - 1]; | |
1688 | ||
1689 | if (MEMOP (opdesc)) | |
1690 | { | |
1691 | parse_memop (&instr, args[i], oP->format); | |
fecd2382 | 1692 | } |
355afbcd KR |
1693 | else |
1694 | { | |
1695 | parse_regop (®op, args[i], opdesc); | |
1696 | instr.opcode |= regop.n << 19; | |
fecd2382 | 1697 | } |
355afbcd KR |
1698 | } |
1699 | ||
48401fcf TT |
1700 | /* Parse the displacement; this must be done before emitting the |
1701 | opcode, in case it is an expression using `.'. */ | |
1702 | parse_expr (instr.e, &expr); | |
1703 | ||
355afbcd KR |
1704 | /* Output opcode */ |
1705 | outP = emit (instr.opcode); | |
1706 | ||
1707 | if (instr.disp == 0) | |
1708 | { | |
1709 | return; | |
1710 | } | |
1711 | ||
48401fcf | 1712 | /* Process the displacement */ |
5ac34ac3 | 1713 | switch (expr.X_op) |
355afbcd | 1714 | { |
5ac34ac3 | 1715 | case O_illegal: |
48401fcf | 1716 | as_bad (_("expression syntax error")); |
355afbcd KR |
1717 | break; |
1718 | ||
5ac34ac3 | 1719 | case O_constant: |
355afbcd KR |
1720 | if (instr.disp == 32) |
1721 | { | |
1722 | (void) emit (offs (expr)); /* Output displacement */ | |
1723 | } | |
1724 | else | |
1725 | { | |
1726 | /* 12-bit displacement */ | |
1727 | if (offs (expr) & ~0xfff) | |
1728 | { | |
1729 | /* Won't fit in 12 bits: convert already-output | |
5ac34ac3 ILT |
1730 | * instruction to MEMB format, output |
1731 | * displacement. | |
1732 | */ | |
355afbcd KR |
1733 | mema_to_memb (outP); |
1734 | (void) emit (offs (expr)); | |
1735 | } | |
1736 | else | |
1737 | { | |
1738 | /* WILL fit in 12 bits: OR into opcode and | |
5ac34ac3 ILT |
1739 | * overwrite the binary we already put out |
1740 | */ | |
355afbcd KR |
1741 | instr.opcode |= offs (expr); |
1742 | md_number_to_chars (outP, instr.opcode, 4); | |
1743 | } | |
1744 | } | |
1745 | break; | |
1746 | ||
5ac34ac3 | 1747 | default: |
355afbcd KR |
1748 | if (instr.disp == 12) |
1749 | { | |
1750 | /* Displacement is dependent on a symbol, whose value | |
c47d388b ME |
1751 | * may change at link time. We HAVE to reserve 32 bits. |
1752 | * Convert already-output opcode to MEMB format. | |
1753 | */ | |
355afbcd KR |
1754 | mema_to_memb (outP); |
1755 | } | |
1756 | ||
1757 | /* Output 0 displacement and set up address fixup for when | |
c47d388b ME |
1758 | * this symbol's value becomes known. |
1759 | */ | |
355afbcd | 1760 | outP = emit ((long) 0); |
5ac34ac3 ILT |
1761 | fixP = fix_new_exp (frag_now, |
1762 | outP - frag_now->fr_literal, | |
1763 | 4, | |
1764 | &expr, | |
1765 | 0, | |
1766 | NO_RELOC); | |
f3d817d8 | 1767 | /* Steve's linker relaxing hack. Mark this 32-bit relocation as |
0e6f2f82 KR |
1768 | being in the instruction stream, specifically as part of a callx |
1769 | instruction. */ | |
f3d817d8 | 1770 | fixP->fx_bsr = callx; |
355afbcd | 1771 | break; |
355afbcd KR |
1772 | } |
1773 | } /* memfmt() */ | |
fecd2382 RP |
1774 | |
1775 | ||
1776 | /***************************************************************************** | |
0e6f2f82 KR |
1777 | mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode. |
1778 | ||
1779 | There are 2 possible MEMA formats: | |
1780 | - displacement only | |
1781 | - displacement + abase | |
1782 | ||
1783 | They are distinguished by the setting of the MEMA_ABASE bit. | |
1784 | ||
1785 | *************************************************************************** */ | |
355afbcd KR |
1786 | static void |
1787 | mema_to_memb (opcodeP) | |
1788 | char *opcodeP; /* Where to find the opcode, in target byte order */ | |
fecd2382 | 1789 | { |
355afbcd KR |
1790 | long opcode; /* Opcode in host byte order */ |
1791 | long mode; /* Mode bits for MEMB instruction */ | |
1792 | ||
1793 | opcode = md_chars_to_number (opcodeP, 4); | |
1794 | know (!(opcode & MEMB_BIT)); | |
1795 | ||
1796 | mode = MEMB_BIT | D_BIT; | |
1797 | if (opcode & MEMA_ABASE) | |
1798 | { | |
1799 | mode |= A_BIT; | |
1800 | } | |
1801 | ||
1802 | opcode &= 0xffffc000; /* Clear MEMA offset and mode bits */ | |
1803 | opcode |= mode; /* Set MEMB mode bits */ | |
1804 | ||
1805 | md_number_to_chars (opcodeP, opcode, 4); | |
1806 | } /* mema_to_memb() */ | |
fecd2382 RP |
1807 | |
1808 | ||
1809 | /***************************************************************************** | |
0e6f2f82 KR |
1810 | parse_expr: parse an expression |
1811 | ||
1812 | Use base assembler's expression parser to parse an expression. | |
1813 | It, unfortunately, runs off a global which we have to save/restore | |
1814 | in order to make it work for us. | |
1815 | ||
1816 | An empty expression string is treated as an absolute 0. | |
1817 | ||
1818 | Sets O_illegal regardless of expression evaluation if entire input | |
1819 | string is not consumed in the evaluation -- tolerate no dangling junk! | |
1820 | ||
1821 | *************************************************************************** */ | |
5ac34ac3 | 1822 | static void |
355afbcd KR |
1823 | parse_expr (textP, expP) |
1824 | char *textP; /* Text of expression to be parsed */ | |
1825 | expressionS *expP; /* Where to put the results of parsing */ | |
fecd2382 | 1826 | { |
355afbcd | 1827 | char *save_in; /* Save global here */ |
355afbcd KR |
1828 | symbolS *symP; |
1829 | ||
1830 | know (textP); | |
1831 | ||
1832 | if (*textP == '\0') | |
1833 | { | |
1834 | /* Treat empty string as absolute 0 */ | |
5ac34ac3 | 1835 | expP->X_add_symbol = expP->X_op_symbol = NULL; |
355afbcd | 1836 | expP->X_add_number = 0; |
604633ae | 1837 | expP->X_op = O_constant; |
355afbcd KR |
1838 | } |
1839 | else | |
1840 | { | |
1841 | save_in = input_line_pointer; /* Save global */ | |
1842 | input_line_pointer = textP; /* Make parser work for us */ | |
1843 | ||
604633ae | 1844 | (void) expression (expP); |
355afbcd KR |
1845 | if (input_line_pointer - textP != strlen (textP)) |
1846 | { | |
1847 | /* Did not consume all of the input */ | |
5ac34ac3 | 1848 | expP->X_op = O_illegal; |
355afbcd KR |
1849 | } |
1850 | symP = expP->X_add_symbol; | |
1851 | if (symP && (hash_find (reg_hash, S_GET_NAME (symP)))) | |
1852 | { | |
1853 | /* Register name in an expression */ | |
5ac34ac3 ILT |
1854 | /* FIXME: this isn't much of a check any more. */ |
1855 | expP->X_op = O_illegal; | |
fecd2382 | 1856 | } |
355afbcd KR |
1857 | |
1858 | input_line_pointer = save_in; /* Restore global */ | |
1859 | } | |
fecd2382 RP |
1860 | } |
1861 | ||
1862 | ||
1863 | /***************************************************************************** | |
0e6f2f82 KR |
1864 | parse_ldcont: |
1865 | Parse and replace a 'ldconst' pseudo-instruction with an appropriate | |
1866 | i80960 instruction. | |
1867 | ||
1868 | Assumes the input consists of: | |
1869 | arg[0] opcode mnemonic ('ldconst') | |
1870 | arg[1] first operand (constant) | |
1871 | arg[2] name of register to be loaded | |
1872 | ||
1873 | Replaces opcode and/or operands as appropriate. | |
1874 | ||
1875 | Returns the new number of arguments, or -1 on failure. | |
1876 | ||
1877 | *************************************************************************** */ | |
fecd2382 | 1878 | static |
355afbcd KR |
1879 | int |
1880 | parse_ldconst (arg) | |
1881 | char *arg[]; /* See above */ | |
fecd2382 | 1882 | { |
355afbcd KR |
1883 | int n; /* Constant to be loaded */ |
1884 | int shift; /* Shift count for "shlo" instruction */ | |
1885 | static char buf[5]; /* Literal for first operand */ | |
1886 | static char buf2[5]; /* Literal for second operand */ | |
1887 | expressionS e; /* Parsed expression */ | |
1888 | ||
1889 | ||
1890 | arg[3] = NULL; /* So we can tell at the end if it got used or not */ | |
1891 | ||
5ac34ac3 ILT |
1892 | parse_expr (arg[1], &e); |
1893 | switch (e.X_op) | |
355afbcd | 1894 | { |
5ac34ac3 | 1895 | default: |
355afbcd KR |
1896 | /* We're dependent on one or more symbols -- use "lda" */ |
1897 | arg[0] = "lda"; | |
1898 | break; | |
1899 | ||
5ac34ac3 | 1900 | case O_constant: |
355afbcd | 1901 | /* Try the following mappings: |
0e6f2f82 KR |
1902 | * ldconst 0,<reg> ->mov 0,<reg> |
1903 | * ldconst 31,<reg> ->mov 31,<reg> | |
1904 | * ldconst 32,<reg> ->addo 1,31,<reg> | |
1905 | * ldconst 62,<reg> ->addo 31,31,<reg> | |
1906 | * ldconst 64,<reg> ->shlo 8,3,<reg> | |
1907 | * ldconst -1,<reg> ->subo 1,0,<reg> | |
1908 | * ldconst -31,<reg>->subo 31,0,<reg> | |
5ac34ac3 ILT |
1909 | * |
1910 | * anthing else becomes: | |
0e6f2f82 | 1911 | * lda xxx,<reg> |
5ac34ac3 | 1912 | */ |
355afbcd KR |
1913 | n = offs (e); |
1914 | if ((0 <= n) && (n <= 31)) | |
1915 | { | |
1916 | arg[0] = "mov"; | |
1917 | ||
1918 | } | |
1919 | else if ((-31 <= n) && (n <= -1)) | |
1920 | { | |
1921 | arg[0] = "subo"; | |
1922 | arg[3] = arg[2]; | |
1923 | sprintf (buf, "%d", -n); | |
1924 | arg[1] = buf; | |
1925 | arg[2] = "0"; | |
1926 | ||
fecd2382 | 1927 | } |
355afbcd KR |
1928 | else if ((32 <= n) && (n <= 62)) |
1929 | { | |
1930 | arg[0] = "addo"; | |
1931 | arg[3] = arg[2]; | |
1932 | arg[1] = "31"; | |
1933 | sprintf (buf, "%d", n - 31); | |
1934 | arg[2] = buf; | |
1935 | ||
1936 | } | |
1937 | else if ((shift = shift_ok (n)) != 0) | |
1938 | { | |
1939 | arg[0] = "shlo"; | |
1940 | arg[3] = arg[2]; | |
1941 | sprintf (buf, "%d", shift); | |
1942 | arg[1] = buf; | |
1943 | sprintf (buf2, "%d", n >> shift); | |
1944 | arg[2] = buf2; | |
1945 | ||
1946 | } | |
1947 | else | |
1948 | { | |
1949 | arg[0] = "lda"; | |
1950 | } | |
1951 | break; | |
1952 | ||
5ac34ac3 | 1953 | case O_illegal: |
48401fcf | 1954 | as_bad (_("invalid constant")); |
355afbcd KR |
1955 | return -1; |
1956 | break; | |
1957 | } | |
1958 | return (arg[3] == 0) ? 2 : 3; | |
fecd2382 RP |
1959 | } |
1960 | ||
1961 | /***************************************************************************** | |
0e6f2f82 KR |
1962 | parse_memop: parse a memory operand |
1963 | ||
1964 | This routine is based on the observation that the 4 mode bits of the | |
1965 | MEMB format, taken individually, have fairly consistent meaning: | |
1966 | ||
1967 | M3 (bit 13): 1 if displacement is present (D_BIT) | |
1968 | M2 (bit 12): 1 for MEMB instructions (MEMB_BIT) | |
1969 | M1 (bit 11): 1 if index is present (I_BIT) | |
1970 | M0 (bit 10): 1 if abase is present (A_BIT) | |
1971 | ||
1972 | So we parse the memory operand and set bits in the mode as we find | |
1973 | things. Then at the end, if we go to MEMB format, we need only set | |
1974 | the MEMB bit (M2) and our mode is built for us. | |
1975 | ||
1976 | Unfortunately, I said "fairly consistent". The exceptions: | |
1977 | ||
1978 | DBIA | |
1979 | 0100 Would seem illegal, but means "abase-only". | |
1980 | ||
1981 | 0101 Would seem to mean "abase-only" -- it means IP-relative. | |
1982 | Must be converted to 0100. | |
1983 | ||
1984 | 0110 Would seem to mean "index-only", but is reserved. | |
1985 | We turn on the D bit and provide a 0 displacement. | |
1986 | ||
1987 | The other thing to observe is that we parse from the right, peeling | |
1988 | things * off as we go: first any index spec, then any abase, then | |
1989 | the displacement. | |
1990 | ||
1991 | *************************************************************************** */ | |
fecd2382 | 1992 | static |
355afbcd KR |
1993 | void |
1994 | parse_memop (memP, argP, optype) | |
1995 | memS *memP; /* Where to put the results */ | |
1996 | char *argP; /* Text of the operand to be parsed */ | |
1997 | int optype; /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */ | |
fecd2382 | 1998 | { |
355afbcd KR |
1999 | char *indexP; /* Pointer to index specification with "[]" removed */ |
2000 | char *p; /* Temp char pointer */ | |
2001 | char iprel_flag; /* True if this is an IP-relative operand */ | |
2002 | int regnum; /* Register number */ | |
0e6f2f82 KR |
2003 | /* Scale factor: 1,2,4,8, or 16. Later converted to internal format |
2004 | (0,1,2,3,4 respectively). */ | |
2005 | int scale; | |
355afbcd KR |
2006 | int mode; /* MEMB mode bits */ |
2007 | int *intP; /* Pointer to register number */ | |
2008 | ||
2009 | /* The following table contains the default scale factors for each | |
0e6f2f82 KR |
2010 | type of memory instruction. It is accessed using (optype-MEM1) |
2011 | as an index -- thus it assumes the 'optype' constants are | |
2012 | assigned consecutive values, in the order they appear in this | |
2013 | table. */ | |
2014 | static const int def_scale[] = | |
355afbcd KR |
2015 | { |
2016 | 1, /* MEM1 */ | |
2017 | 2, /* MEM2 */ | |
2018 | 4, /* MEM4 */ | |
2019 | 8, /* MEM8 */ | |
2020 | -1, /* MEM12 -- no valid default */ | |
2021 | 16 /* MEM16 */ | |
2022 | }; | |
2023 | ||
2024 | ||
2025 | iprel_flag = mode = 0; | |
2026 | ||
2027 | /* Any index present? */ | |
2028 | indexP = get_ispec (argP); | |
2029 | if (indexP) | |
2030 | { | |
2031 | p = strchr (indexP, '*'); | |
2032 | if (p == NULL) | |
2033 | { | |
0e6f2f82 KR |
2034 | /* No explicit scale -- use default for this instruction |
2035 | type and assembler mode. */ | |
2036 | if (flag_mri) | |
2037 | scale = 1; | |
2038 | else | |
2039 | /* GNU960 compatibility */ | |
2040 | scale = def_scale[optype - MEM1]; | |
355afbcd KR |
2041 | } |
2042 | else | |
2043 | { | |
2044 | *p++ = '\0'; /* Eliminate '*' */ | |
2045 | ||
2046 | /* Now indexP->a '\0'-terminated register name, | |
0e6f2f82 KR |
2047 | * and p->a scale factor. |
2048 | */ | |
355afbcd KR |
2049 | |
2050 | if (!strcmp (p, "16")) | |
2051 | { | |
2052 | scale = 16; | |
2053 | } | |
2054 | else if (strchr ("1248", *p) && (p[1] == '\0')) | |
2055 | { | |
2056 | scale = *p - '0'; | |
2057 | } | |
2058 | else | |
2059 | { | |
2060 | scale = -1; | |
2061 | } | |
2062 | } | |
2063 | ||
2064 | regnum = get_regnum (indexP); /* Get index reg. # */ | |
2065 | if (!IS_RG_REG (regnum)) | |
2066 | { | |
48401fcf | 2067 | as_bad (_("invalid index register")); |
355afbcd | 2068 | return; |
fecd2382 | 2069 | } |
355afbcd KR |
2070 | |
2071 | /* Convert scale to its binary encoding */ | |
2072 | switch (scale) | |
2073 | { | |
2074 | case 1: | |
2075 | scale = 0 << 7; | |
2076 | break; | |
2077 | case 2: | |
2078 | scale = 1 << 7; | |
2079 | break; | |
2080 | case 4: | |
2081 | scale = 2 << 7; | |
2082 | break; | |
2083 | case 8: | |
2084 | scale = 3 << 7; | |
2085 | break; | |
2086 | case 16: | |
2087 | scale = 4 << 7; | |
2088 | break; | |
2089 | default: | |
48401fcf | 2090 | as_bad (_("invalid scale factor")); |
355afbcd KR |
2091 | return; |
2092 | }; | |
2093 | ||
2094 | memP->opcode |= scale | regnum; /* Set index bits in opcode */ | |
2095 | mode |= I_BIT; /* Found a valid index spec */ | |
2096 | } | |
2097 | ||
2098 | /* Any abase (Register Indirect) specification present? */ | |
2099 | if ((p = strrchr (argP, '(')) != NULL) | |
2100 | { | |
0e6f2f82 KR |
2101 | /* "(" is there -- does it start a legal abase spec? If not, it |
2102 | could be part of a displacement expression. */ | |
355afbcd KR |
2103 | intP = (int *) hash_find (areg_hash, p); |
2104 | if (intP != NULL) | |
2105 | { | |
2106 | /* Got an abase here */ | |
2107 | regnum = *intP; | |
2108 | *p = '\0'; /* discard register spec */ | |
2109 | if (regnum == IPREL) | |
2110 | { | |
2111 | /* We have to specialcase ip-rel mode */ | |
2112 | iprel_flag = 1; | |
2113 | } | |
2114 | else | |
2115 | { | |
2116 | memP->opcode |= regnum << 14; | |
2117 | mode |= A_BIT; | |
2118 | } | |
fecd2382 | 2119 | } |
355afbcd KR |
2120 | } |
2121 | ||
2122 | /* Any expression present? */ | |
2123 | memP->e = argP; | |
2124 | if (*argP != '\0') | |
2125 | { | |
2126 | mode |= D_BIT; | |
2127 | } | |
2128 | ||
2129 | /* Special-case ip-relative addressing */ | |
2130 | if (iprel_flag) | |
2131 | { | |
2132 | if (mode & I_BIT) | |
2133 | { | |
2134 | syntax (); | |
fecd2382 | 2135 | } |
355afbcd KR |
2136 | else |
2137 | { | |
2138 | memP->opcode |= 5 << 10; /* IP-relative mode */ | |
2139 | memP->disp = 32; | |
fecd2382 | 2140 | } |
355afbcd KR |
2141 | return; |
2142 | } | |
2143 | ||
2144 | /* Handle all other modes */ | |
2145 | switch (mode) | |
2146 | { | |
2147 | case D_BIT | A_BIT: | |
2148 | /* Go with MEMA instruction format for now (grow to MEMB later | |
0e6f2f82 KR |
2149 | if 12 bits is not enough for the displacement). MEMA format |
2150 | has a single mode bit: set it to indicate that abase is | |
2151 | present. */ | |
355afbcd KR |
2152 | memP->opcode |= MEMA_ABASE; |
2153 | memP->disp = 12; | |
2154 | break; | |
2155 | ||
2156 | case D_BIT: | |
2157 | /* Go with MEMA instruction format for now (grow to MEMB later | |
0e6f2f82 | 2158 | if 12 bits is not enough for the displacement). */ |
355afbcd KR |
2159 | memP->disp = 12; |
2160 | break; | |
2161 | ||
2162 | case A_BIT: | |
2163 | /* For some reason, the bit string for this mode is not | |
0e6f2f82 KR |
2164 | consistent: it should be 0 (exclusive of the MEMB bit), so we |
2165 | set it "by hand" here. */ | |
355afbcd KR |
2166 | memP->opcode |= MEMB_BIT; |
2167 | break; | |
2168 | ||
2169 | case A_BIT | I_BIT: | |
2170 | /* set MEMB bit in mode, and OR in mode bits */ | |
2171 | memP->opcode |= mode | MEMB_BIT; | |
2172 | break; | |
2173 | ||
2174 | case I_BIT: | |
0e6f2f82 | 2175 | /* Treat missing displacement as displacement of 0. */ |
355afbcd | 2176 | mode |= D_BIT; |
0e6f2f82 | 2177 | /* Fall into next case. */ |
355afbcd KR |
2178 | case D_BIT | A_BIT | I_BIT: |
2179 | case D_BIT | I_BIT: | |
2180 | /* set MEMB bit in mode, and OR in mode bits */ | |
2181 | memP->opcode |= mode | MEMB_BIT; | |
2182 | memP->disp = 32; | |
2183 | break; | |
2184 | ||
2185 | default: | |
2186 | syntax (); | |
2187 | break; | |
2188 | } | |
fecd2382 RP |
2189 | } |
2190 | ||
2191 | /***************************************************************************** | |
0e6f2f82 KR |
2192 | parse_po: parse machine-dependent pseudo-op |
2193 | ||
2194 | This is a top-level routine for machine-dependent pseudo-ops. It slurps | |
2195 | up the rest of the input line, breaks out the individual arguments, | |
2196 | and dispatches them to the correct handler. | |
2197 | *************************************************************************** */ | |
fecd2382 | 2198 | static |
355afbcd KR |
2199 | void |
2200 | parse_po (po_num) | |
2201 | int po_num; /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC */ | |
fecd2382 | 2202 | { |
0e6f2f82 KR |
2203 | /* Pointers operands, with no embedded whitespace. |
2204 | arg[0] unused, arg[1-3]->operands */ | |
2205 | char *args[4]; | |
355afbcd KR |
2206 | int n_ops; /* Number of operands */ |
2207 | char *p; /* Pointer to beginning of unparsed argument string */ | |
2208 | char eol; /* Character that indicated end of line */ | |
2209 | ||
2210 | extern char is_end_of_line[]; | |
2211 | ||
2212 | /* Advance input pointer to end of line. */ | |
2213 | p = input_line_pointer; | |
80aab579 | 2214 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) |
355afbcd KR |
2215 | { |
2216 | input_line_pointer++; | |
2217 | } | |
2218 | eol = *input_line_pointer; /* Save end-of-line char */ | |
2219 | *input_line_pointer = '\0'; /* Terminate argument list */ | |
2220 | ||
2221 | /* Parse out operands */ | |
2222 | n_ops = get_args (p, args); | |
2223 | if (n_ops == -1) | |
2224 | { | |
2225 | return; | |
2226 | } | |
2227 | ||
2228 | /* Dispatch to correct handler */ | |
2229 | switch (po_num) | |
2230 | { | |
2231 | case S_SYSPROC: | |
2232 | s_sysproc (n_ops, args); | |
2233 | break; | |
2234 | case S_LEAFPROC: | |
2235 | s_leafproc (n_ops, args); | |
2236 | break; | |
2237 | default: | |
2238 | BAD_CASE (po_num); | |
2239 | break; | |
2240 | } | |
2241 | ||
0e6f2f82 KR |
2242 | /* Restore eol, so line numbers get updated correctly. Base |
2243 | assembler assumes we leave input pointer pointing at char | |
2244 | following the eol. */ | |
355afbcd | 2245 | *input_line_pointer++ = eol; |
fecd2382 RP |
2246 | } |
2247 | ||
2248 | /***************************************************************************** | |
0e6f2f82 KR |
2249 | parse_regop: parse a register operand. |
2250 | ||
2251 | In case of illegal operand, issue a message and return some valid | |
2252 | information so instruction processing can continue. | |
2253 | *************************************************************************** */ | |
fecd2382 | 2254 | static |
355afbcd KR |
2255 | void |
2256 | parse_regop (regopP, optext, opdesc) | |
2257 | struct regop *regopP; /* Where to put description of register operand */ | |
2258 | char *optext; /* Text of operand */ | |
2259 | char opdesc; /* Descriptor byte: what's legal for this operand */ | |
fecd2382 | 2260 | { |
355afbcd KR |
2261 | int n; /* Register number */ |
2262 | expressionS e; /* Parsed expression */ | |
2263 | ||
2264 | /* See if operand is a register */ | |
2265 | n = get_regnum (optext); | |
2266 | if (n >= 0) | |
2267 | { | |
2268 | if (IS_RG_REG (n)) | |
2269 | { | |
2270 | /* global or local register */ | |
2271 | if (!REG_ALIGN (opdesc, n)) | |
2272 | { | |
48401fcf | 2273 | as_bad (_("unaligned register")); |
355afbcd KR |
2274 | } |
2275 | regopP->n = n; | |
2276 | regopP->mode = 0; | |
2277 | regopP->special = 0; | |
2278 | return; | |
2279 | } | |
2280 | else if (IS_FP_REG (n) && FP_OK (opdesc)) | |
2281 | { | |
2282 | /* Floating point register, and it's allowed */ | |
2283 | regopP->n = n - FP0; | |
2284 | regopP->mode = 1; | |
2285 | regopP->special = 0; | |
2286 | return; | |
2287 | } | |
2288 | else if (IS_SF_REG (n) && SFR_OK (opdesc)) | |
2289 | { | |
2290 | /* Special-function register, and it's allowed */ | |
2291 | regopP->n = n - SF0; | |
2292 | regopP->mode = 0; | |
2293 | regopP->special = 1; | |
2294 | if (!targ_has_sfr (regopP->n)) | |
2295 | { | |
48401fcf | 2296 | as_bad (_("no such sfr in this architecture")); |
355afbcd KR |
2297 | } |
2298 | return; | |
2299 | } | |
2300 | } | |
2301 | else if (LIT_OK (opdesc)) | |
2302 | { | |
0e6f2f82 | 2303 | /* How about a literal? */ |
355afbcd KR |
2304 | regopP->mode = 1; |
2305 | regopP->special = 0; | |
2306 | if (FP_OK (opdesc)) | |
2307 | { /* floating point literal acceptable */ | |
2308 | /* Skip over 0f, 0d, or 0e prefix */ | |
2309 | if ((optext[0] == '0') | |
2310 | && (optext[1] >= 'd') | |
2311 | && (optext[1] <= 'f')) | |
2312 | { | |
2313 | optext += 2; | |
2314 | } | |
2315 | ||
2316 | if (!strcmp (optext, "0.0") || !strcmp (optext, "0")) | |
2317 | { | |
2318 | regopP->n = 0x10; | |
2319 | return; | |
2320 | } | |
2321 | if (!strcmp (optext, "1.0") || !strcmp (optext, "1")) | |
2322 | { | |
2323 | regopP->n = 0x16; | |
2324 | return; | |
2325 | } | |
2326 | ||
fecd2382 | 2327 | } |
355afbcd KR |
2328 | else |
2329 | { /* fixed point literal acceptable */ | |
5ac34ac3 ILT |
2330 | parse_expr (optext, &e); |
2331 | if (e.X_op != O_constant | |
355afbcd KR |
2332 | || (offs (e) < 0) || (offs (e) > 31)) |
2333 | { | |
48401fcf | 2334 | as_bad (_("illegal literal")); |
355afbcd KR |
2335 | offs (e) = 0; |
2336 | } | |
2337 | regopP->n = offs (e); | |
2338 | return; | |
2339 | } | |
2340 | } | |
2341 | ||
2342 | /* Nothing worked */ | |
2343 | syntax (); | |
2344 | regopP->mode = 0; /* Register r0 is always a good one */ | |
2345 | regopP->n = 0; | |
2346 | regopP->special = 0; | |
2347 | } /* parse_regop() */ | |
fecd2382 RP |
2348 | |
2349 | /***************************************************************************** | |
0e6f2f82 KR |
2350 | reg_fmt: generate a REG-format instruction |
2351 | ||
2352 | *************************************************************************** */ | |
355afbcd KR |
2353 | static void |
2354 | reg_fmt (args, oP) | |
2355 | char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */ | |
2356 | struct i960_opcode *oP; /* Pointer to description of instruction */ | |
fecd2382 | 2357 | { |
355afbcd KR |
2358 | long instr; /* Binary to be output */ |
2359 | struct regop regop; /* Description of register operand */ | |
2360 | int n_ops; /* Number of operands */ | |
2361 | ||
2362 | ||
2363 | instr = oP->opcode; | |
2364 | n_ops = oP->num_ops; | |
2365 | ||
2366 | if (n_ops >= 1) | |
2367 | { | |
2368 | parse_regop (®op, args[1], oP->operand[0]); | |
2369 | ||
2370 | if ((n_ops == 1) && !(instr & M3)) | |
2371 | { | |
2372 | /* 1-operand instruction in which the dst field should | |
0e6f2f82 KR |
2373 | * be used (instead of src1). |
2374 | */ | |
355afbcd KR |
2375 | regop.n <<= 19; |
2376 | if (regop.special) | |
2377 | { | |
2378 | regop.mode = regop.special; | |
2379 | } | |
2380 | regop.mode <<= 13; | |
2381 | regop.special = 0; | |
2382 | } | |
2383 | else | |
2384 | { | |
2385 | /* regop.n goes in bit 0, needs no shifting */ | |
2386 | regop.mode <<= 11; | |
2387 | regop.special <<= 5; | |
fecd2382 | 2388 | } |
355afbcd KR |
2389 | instr |= regop.n | regop.mode | regop.special; |
2390 | } | |
2391 | ||
2392 | if (n_ops >= 2) | |
2393 | { | |
2394 | parse_regop (®op, args[2], oP->operand[1]); | |
2395 | ||
2396 | if ((n_ops == 2) && !(instr & M3)) | |
2397 | { | |
2398 | /* 2-operand instruction in which the dst field should | |
0e6f2f82 KR |
2399 | * be used instead of src2). |
2400 | */ | |
355afbcd KR |
2401 | regop.n <<= 19; |
2402 | if (regop.special) | |
2403 | { | |
2404 | regop.mode = regop.special; | |
2405 | } | |
2406 | regop.mode <<= 13; | |
2407 | regop.special = 0; | |
fecd2382 | 2408 | } |
355afbcd KR |
2409 | else |
2410 | { | |
2411 | regop.n <<= 14; | |
2412 | regop.mode <<= 12; | |
2413 | regop.special <<= 6; | |
fecd2382 | 2414 | } |
355afbcd KR |
2415 | instr |= regop.n | regop.mode | regop.special; |
2416 | } | |
2417 | if (n_ops == 3) | |
2418 | { | |
2419 | parse_regop (®op, args[3], oP->operand[2]); | |
2420 | if (regop.special) | |
2421 | { | |
2422 | regop.mode = regop.special; | |
2423 | } | |
2424 | instr |= (regop.n <<= 19) | (regop.mode <<= 13); | |
2425 | } | |
2426 | emit (instr); | |
fecd2382 RP |
2427 | } |
2428 | ||
2429 | ||
2430 | /***************************************************************************** | |
0e6f2f82 KR |
2431 | relax_cobr: |
2432 | Replace cobr instruction in a code fragment with equivalent branch and | |
2433 | compare instructions, so it can reach beyond a 13-bit displacement. | |
2434 | Set up an address fix/relocation for the new branch instruction. | |
2435 | ||
2436 | *************************************************************************** */ | |
2437 | ||
2438 | /* This "conditional jump" table maps cobr instructions into | |
2439 | equivalent compare and branch opcodes. */ | |
2440 | static const | |
355afbcd | 2441 | struct |
0e6f2f82 KR |
2442 | { |
2443 | long compare; | |
2444 | long branch; | |
2445 | } | |
355afbcd KR |
2446 | |
2447 | coj[] = | |
2448 | { /* COBR OPCODE: */ | |
0e6f2f82 KR |
2449 | { CHKBIT, BNO }, /* 0x30 - bbc */ |
2450 | { CMPO, BG }, /* 0x31 - cmpobg */ | |
2451 | { CMPO, BE }, /* 0x32 - cmpobe */ | |
2452 | { CMPO, BGE }, /* 0x33 - cmpobge */ | |
2453 | { CMPO, BL }, /* 0x34 - cmpobl */ | |
2454 | { CMPO, BNE }, /* 0x35 - cmpobne */ | |
2455 | { CMPO, BLE }, /* 0x36 - cmpoble */ | |
2456 | { CHKBIT, BO }, /* 0x37 - bbs */ | |
2457 | { CMPI, BNO }, /* 0x38 - cmpibno */ | |
2458 | { CMPI, BG }, /* 0x39 - cmpibg */ | |
2459 | { CMPI, BE }, /* 0x3a - cmpibe */ | |
2460 | { CMPI, BGE }, /* 0x3b - cmpibge */ | |
2461 | { CMPI, BL }, /* 0x3c - cmpibl */ | |
2462 | { CMPI, BNE }, /* 0x3d - cmpibne */ | |
2463 | { CMPI, BLE }, /* 0x3e - cmpible */ | |
2464 | { CMPI, BO }, /* 0x3f - cmpibo */ | |
355afbcd | 2465 | }; |
fecd2382 RP |
2466 | |
2467 | static | |
355afbcd KR |
2468 | void |
2469 | relax_cobr (fragP) | |
2470 | register fragS *fragP; /* fragP->fr_opcode is assumed to point to | |
c47d388b ME |
2471 | * the cobr instruction, which comes at the |
2472 | * end of the code fragment. | |
2473 | */ | |
fecd2382 | 2474 | { |
355afbcd KR |
2475 | int opcode, src1, src2, m1, s2; |
2476 | /* Bit fields from cobr instruction */ | |
2477 | long bp_bits; /* Branch prediction bits from cobr instruction */ | |
2478 | long instr; /* A single i960 instruction */ | |
0e6f2f82 KR |
2479 | /* ->instruction to be replaced */ |
2480 | char *iP; | |
355afbcd KR |
2481 | fixS *fixP; /* Relocation that can be done at assembly time */ |
2482 | ||
2483 | /* PICK UP & PARSE COBR INSTRUCTION */ | |
2484 | iP = fragP->fr_opcode; | |
2485 | instr = md_chars_to_number (iP, 4); | |
2486 | opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index */ | |
2487 | src1 = (instr >> 19) & 0x1f; | |
2488 | m1 = (instr >> 13) & 1; | |
2489 | s2 = instr & 1; | |
2490 | src2 = (instr >> 14) & 0x1f; | |
2491 | bp_bits = instr & BP_MASK; | |
2492 | ||
2493 | /* GENERATE AND OUTPUT COMPARE INSTRUCTION */ | |
2494 | instr = coj[opcode].compare | |
2495 | | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14); | |
2496 | md_number_to_chars (iP, instr, 4); | |
2497 | ||
2498 | /* OUTPUT BRANCH INSTRUCTION */ | |
2499 | md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4); | |
2500 | ||
2501 | /* SET UP ADDRESS FIXUP/RELOCATION */ | |
2502 | fixP = fix_new (fragP, | |
2503 | iP + 4 - fragP->fr_literal, | |
2504 | 4, | |
2505 | fragP->fr_symbol, | |
355afbcd KR |
2506 | fragP->fr_offset, |
2507 | 1, | |
2508 | NO_RELOC); | |
2509 | ||
2510 | fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field */ | |
2511 | ||
2512 | fragP->fr_fix += 4; | |
2513 | frag_wane (fragP); | |
fecd2382 RP |
2514 | } |
2515 | ||
2516 | ||
2517 | /***************************************************************************** | |
0e6f2f82 KR |
2518 | reloc_callj: Relocate a 'callj' instruction |
2519 | ||
2520 | This is a "non-(GNU)-standard" machine-dependent hook. The base | |
2521 | assembler calls it when it decides it can relocate an address at | |
2522 | assembly time instead of emitting a relocation directive. | |
2523 | ||
2524 | Check to see if the relocation involves a 'callj' instruction to a: | |
2525 | sysproc: Replace the default 'call' instruction with a 'calls' | |
2526 | leafproc: Replace the default 'call' instruction with a 'bal'. | |
2527 | other proc: Do nothing. | |
2528 | ||
2529 | See b.out.h for details on the 'n_other' field in a symbol structure. | |
2530 | ||
2531 | IMPORTANT!: | |
2532 | Assumes the caller has already figured out, in the case of a leafproc, | |
2533 | to use the 'bal' entry point, and has substituted that symbol into the | |
2534 | passed fixup structure. | |
2535 | ||
2536 | *************************************************************************** */ | |
355afbcd KR |
2537 | void |
2538 | reloc_callj (fixP) | |
0e6f2f82 KR |
2539 | /* Relocation that can be done at assembly time */ |
2540 | fixS *fixP; | |
fecd2382 | 2541 | { |
0e6f2f82 KR |
2542 | /* Points to the binary for the instruction being relocated. */ |
2543 | char *where; | |
355afbcd | 2544 | |
f3d817d8 | 2545 | if (!fixP->fx_tcbit) |
355afbcd | 2546 | { |
0e6f2f82 | 2547 | /* This wasn't a callj instruction in the first place */ |
355afbcd | 2548 | return; |
0e6f2f82 | 2549 | } |
355afbcd KR |
2550 | |
2551 | where = fixP->fx_frag->fr_literal + fixP->fx_where; | |
2552 | ||
2553 | if (TC_S_IS_SYSPROC (fixP->fx_addsy)) | |
2554 | { | |
0e6f2f82 KR |
2555 | /* Symbol is a .sysproc: replace 'call' with 'calls'. System |
2556 | procedure number is (other-1). */ | |
355afbcd KR |
2557 | md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4); |
2558 | ||
0e6f2f82 KR |
2559 | /* Nothing else needs to be done for this instruction. Make |
2560 | sure 'md_number_to_field()' will perform a no-op. */ | |
355afbcd KR |
2561 | fixP->fx_bit_fixP = (bit_fixS *) 1; |
2562 | ||
2563 | } | |
2564 | else if (TC_S_IS_CALLNAME (fixP->fx_addsy)) | |
2565 | { | |
2566 | /* Should not happen: see block comment above */ | |
48401fcf | 2567 | as_fatal (_("Trying to 'bal' to %s"), S_GET_NAME (fixP->fx_addsy)); |
355afbcd KR |
2568 | } |
2569 | else if (TC_S_IS_BALNAME (fixP->fx_addsy)) | |
2570 | { | |
0e6f2f82 KR |
2571 | /* Replace 'call' with 'bal'; both instructions have the same |
2572 | format, so calling code should complete relocation as if | |
2573 | nothing happened here. */ | |
355afbcd KR |
2574 | md_number_to_chars (where, BAL, 4); |
2575 | } | |
2576 | else if (TC_S_IS_BADPROC (fixP->fx_addsy)) | |
2577 | { | |
48401fcf | 2578 | as_bad (_("Looks like a proc, but can't tell what kind.\n")); |
355afbcd KR |
2579 | } /* switch on proc type */ |
2580 | ||
2581 | /* else Symbol is neither a sysproc nor a leafproc */ | |
f3d817d8 | 2582 | } |
fecd2382 RP |
2583 | |
2584 | ||
2585 | /***************************************************************************** | |
0e6f2f82 KR |
2586 | s_leafproc: process .leafproc pseudo-op |
2587 | ||
2588 | .leafproc takes two arguments, the second one is optional: | |
2589 | arg[1]: name of 'call' entry point to leaf procedure | |
2590 | arg[2]: name of 'bal' entry point to leaf procedure | |
2591 | ||
2592 | If the two arguments are identical, or if the second one is missing, | |
2593 | the first argument is taken to be the 'bal' entry point. | |
2594 | ||
2595 | If there are 2 distinct arguments, we must make sure that the 'bal' | |
2596 | entry point immediately follows the 'call' entry point in the linked | |
2597 | list of symbols. | |
2598 | ||
2599 | *************************************************************************** */ | |
355afbcd KR |
2600 | static void |
2601 | s_leafproc (n_ops, args) | |
2602 | int n_ops; /* Number of operands */ | |
2603 | char *args[]; /* args[1]->1st operand, args[2]->2nd operand */ | |
fecd2382 | 2604 | { |
355afbcd KR |
2605 | symbolS *callP; /* Pointer to leafproc 'call' entry point symbol */ |
2606 | symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol */ | |
2607 | ||
2608 | if ((n_ops != 1) && (n_ops != 2)) | |
2609 | { | |
48401fcf | 2610 | as_bad (_("should have 1 or 2 operands")); |
355afbcd KR |
2611 | return; |
2612 | } /* Check number of arguments */ | |
2613 | ||
2614 | /* Find or create symbol for 'call' entry point. */ | |
2615 | callP = symbol_find_or_make (args[1]); | |
2616 | ||
2617 | if (TC_S_IS_CALLNAME (callP)) | |
2618 | { | |
48401fcf | 2619 | as_warn (_("Redefining leafproc %s"), S_GET_NAME (callP)); |
355afbcd KR |
2620 | } /* is leafproc */ |
2621 | ||
2622 | /* If that was the only argument, use it as the 'bal' entry point. | |
0e6f2f82 KR |
2623 | * Otherwise, mark it as the 'call' entry point and find or create |
2624 | * another symbol for the 'bal' entry point. | |
2625 | */ | |
355afbcd KR |
2626 | if ((n_ops == 1) || !strcmp (args[1], args[2])) |
2627 | { | |
2628 | TC_S_FORCE_TO_BALNAME (callP); | |
2629 | ||
2630 | } | |
2631 | else | |
2632 | { | |
2633 | TC_S_FORCE_TO_CALLNAME (callP); | |
2634 | ||
2635 | balP = symbol_find_or_make (args[2]); | |
2636 | if (TC_S_IS_CALLNAME (balP)) | |
2637 | { | |
48401fcf | 2638 | as_warn (_("Redefining leafproc %s"), S_GET_NAME (balP)); |
355afbcd KR |
2639 | } |
2640 | TC_S_FORCE_TO_BALNAME (balP); | |
2641 | ||
2642 | tc_set_bal_of_call (callP, balP); | |
2643 | } /* if only one arg, or the args are the same */ | |
f3d817d8 | 2644 | } |
fecd2382 RP |
2645 | |
2646 | ||
2647 | /* | |
0e6f2f82 KR |
2648 | s_sysproc: process .sysproc pseudo-op |
2649 | ||
2650 | .sysproc takes two arguments: | |
2651 | arg[1]: name of entry point to system procedure | |
2652 | arg[2]: 'entry_num' (index) of system procedure in the range | |
2653 | [0,31] inclusive. | |
2654 | ||
2655 | For [ab].out, we store the 'entrynum' in the 'n_other' field of | |
2656 | the symbol. Since that entry is normally 0, we bias 'entrynum' | |
2657 | by adding 1 to it. It must be unbiased before it is used. */ | |
355afbcd KR |
2658 | static void |
2659 | s_sysproc (n_ops, args) | |
2660 | int n_ops; /* Number of operands */ | |
2661 | char *args[]; /* args[1]->1st operand, args[2]->2nd operand */ | |
fecd2382 | 2662 | { |
355afbcd KR |
2663 | expressionS exp; |
2664 | symbolS *symP; | |
2665 | ||
2666 | if (n_ops != 2) | |
2667 | { | |
48401fcf | 2668 | as_bad (_("should have two operands")); |
355afbcd KR |
2669 | return; |
2670 | } /* bad arg count */ | |
2671 | ||
2672 | /* Parse "entry_num" argument and check it for validity. */ | |
5ac34ac3 ILT |
2673 | parse_expr (args[2], &exp); |
2674 | if (exp.X_op != O_constant | |
355afbcd KR |
2675 | || (offs (exp) < 0) |
2676 | || (offs (exp) > 31)) | |
2677 | { | |
48401fcf | 2678 | as_bad (_("'entry_num' must be absolute number in [0,31]")); |
355afbcd KR |
2679 | return; |
2680 | } | |
2681 | ||
2682 | /* Find/make symbol and stick entry number (biased by +1) into it */ | |
2683 | symP = symbol_find_or_make (args[1]); | |
2684 | ||
2685 | if (TC_S_IS_SYSPROC (symP)) | |
2686 | { | |
48401fcf | 2687 | as_warn (_("Redefining entrynum for sysproc %s"), S_GET_NAME (symP)); |
355afbcd KR |
2688 | } /* redefining */ |
2689 | ||
2690 | TC_S_SET_SYSPROC (symP, offs (exp)); /* encode entry number */ | |
2691 | TC_S_FORCE_TO_SYSPROC (symP); | |
f3d817d8 | 2692 | } |
fecd2382 RP |
2693 | |
2694 | ||
2695 | /***************************************************************************** | |
0e6f2f82 KR |
2696 | shift_ok: |
2697 | Determine if a "shlo" instruction can be used to implement a "ldconst". | |
2698 | This means that some number X < 32 can be shifted left to produce the | |
2699 | constant of interest. | |
2700 | ||
2701 | Return the shift count, or 0 if we can't do it. | |
2702 | Caller calculates X by shifting original constant right 'shift' places. | |
2703 | ||
2704 | *************************************************************************** */ | |
fecd2382 | 2705 | static |
355afbcd KR |
2706 | int |
2707 | shift_ok (n) | |
2708 | int n; /* The constant of interest */ | |
fecd2382 | 2709 | { |
355afbcd KR |
2710 | int shift; /* The shift count */ |
2711 | ||
2712 | if (n <= 0) | |
2713 | { | |
2714 | /* Can't do it for negative numbers */ | |
2715 | return 0; | |
2716 | } | |
2717 | ||
2718 | /* Shift 'n' right until a 1 is about to be lost */ | |
2719 | for (shift = 0; (n & 1) == 0; shift++) | |
2720 | { | |
2721 | n >>= 1; | |
2722 | } | |
2723 | ||
2724 | if (n >= 32) | |
2725 | { | |
2726 | return 0; | |
2727 | } | |
2728 | return shift; | |
fecd2382 RP |
2729 | } |
2730 | ||
2731 | ||
0e6f2f82 KR |
2732 | /* syntax: issue syntax error */ |
2733 | ||
355afbcd KR |
2734 | static void |
2735 | syntax () | |
2736 | { | |
48401fcf | 2737 | as_bad (_("syntax error")); |
355afbcd | 2738 | } /* syntax() */ |
fecd2382 RP |
2739 | |
2740 | ||
0e6f2f82 KR |
2741 | /* targ_has_sfr: |
2742 | ||
2743 | Return TRUE iff the target architecture supports the specified | |
2744 | special-function register (sfr). */ | |
2745 | ||
fecd2382 | 2746 | static |
355afbcd KR |
2747 | int |
2748 | targ_has_sfr (n) | |
2749 | int n; /* Number (0-31) of sfr */ | |
fecd2382 | 2750 | { |
355afbcd KR |
2751 | switch (architecture) |
2752 | { | |
2753 | case ARCH_KA: | |
2754 | case ARCH_KB: | |
2755 | case ARCH_MC: | |
48401fcf | 2756 | case ARCH_JX: |
355afbcd | 2757 | return 0; |
f9e90c2e ILT |
2758 | case ARCH_HX: |
2759 | return ((0 <= n) && (n <= 4)); | |
355afbcd KR |
2760 | case ARCH_CA: |
2761 | default: | |
2762 | return ((0 <= n) && (n <= 2)); | |
2763 | } | |
fecd2382 RP |
2764 | } |
2765 | ||
2766 | ||
0e6f2f82 KR |
2767 | /* targ_has_iclass: |
2768 | ||
2769 | Return TRUE iff the target architecture supports the indicated | |
2770 | class of instructions. */ | |
fecd2382 | 2771 | static |
355afbcd KR |
2772 | int |
2773 | targ_has_iclass (ic) | |
0e6f2f82 | 2774 | /* Instruction class; one of: |
f9e90c2e | 2775 | I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2 |
0e6f2f82 KR |
2776 | */ |
2777 | int ic; | |
fecd2382 | 2778 | { |
355afbcd KR |
2779 | iclasses_seen |= ic; |
2780 | switch (architecture) | |
2781 | { | |
2782 | case ARCH_KA: | |
2783 | return ic & (I_BASE | I_KX); | |
2784 | case ARCH_KB: | |
2785 | return ic & (I_BASE | I_KX | I_FP | I_DEC); | |
2786 | case ARCH_MC: | |
2787 | return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL); | |
2788 | case ARCH_CA: | |
0e6f2f82 | 2789 | return ic & (I_BASE | I_CX | I_CX2 | I_CASIM); |
48401fcf TT |
2790 | case ARCH_JX: |
2791 | return ic & (I_BASE | I_CX2 | I_JX); | |
f9e90c2e | 2792 | case ARCH_HX: |
48401fcf | 2793 | return ic & (I_BASE | I_CX2 | I_JX | I_HX); |
355afbcd KR |
2794 | default: |
2795 | if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL)) | |
0e6f2f82 | 2796 | && (iclasses_seen & (I_CX | I_CX2))) |
355afbcd | 2797 | { |
48401fcf | 2798 | as_warn (_("architecture of opcode conflicts with that of earlier instruction(s)")); |
355afbcd | 2799 | iclasses_seen &= ~ic; |
fecd2382 | 2800 | } |
355afbcd KR |
2801 | return 1; |
2802 | } | |
fecd2382 RP |
2803 | } |
2804 | ||
0e6f2f82 | 2805 | /* Handle the MRI .endian pseudo-op. */ |
fecd2382 | 2806 | |
0e6f2f82 KR |
2807 | static void |
2808 | s_endian (ignore) | |
2809 | int ignore; | |
fecd2382 | 2810 | { |
0e6f2f82 KR |
2811 | char *name; |
2812 | char c; | |
2813 | ||
2814 | name = input_line_pointer; | |
2815 | c = get_symbol_end (); | |
2816 | if (strcasecmp (name, "little") == 0) | |
2817 | ; | |
2818 | else if (strcasecmp (name, "big") == 0) | |
48401fcf | 2819 | as_bad (_("big endian mode is not supported")); |
0e6f2f82 | 2820 | else |
48401fcf | 2821 | as_warn (_("ignoring unrecognized .endian type `%s'"), name); |
0e6f2f82 KR |
2822 | |
2823 | *input_line_pointer = c; | |
2824 | ||
2825 | demand_empty_rest_of_line (); | |
fecd2382 RP |
2826 | } |
2827 | ||
2828 | /* We have no need to default values of symbols. */ | |
2829 | ||
2830 | /* ARGSUSED */ | |
355afbcd KR |
2831 | symbolS * |
2832 | md_undefined_symbol (name) | |
2833 | char *name; | |
fecd2382 | 2834 | { |
355afbcd | 2835 | return 0; |
f3d817d8 | 2836 | } |
fecd2382 RP |
2837 | |
2838 | /* Exactly what point is a PC-relative offset relative TO? | |
2839 | On the i960, they're relative to the address of the instruction, | |
2840 | which we have set up as the address of the fixup too. */ | |
2841 | long | |
355afbcd KR |
2842 | md_pcrel_from (fixP) |
2843 | fixS *fixP; | |
fecd2382 | 2844 | { |
355afbcd | 2845 | return fixP->fx_where + fixP->fx_frag->fr_address; |
fecd2382 RP |
2846 | } |
2847 | ||
2848 | void | |
355afbcd KR |
2849 | md_apply_fix (fixP, val) |
2850 | fixS *fixP; | |
2851 | long val; | |
fecd2382 | 2852 | { |
355afbcd KR |
2853 | char *place = fixP->fx_where + fixP->fx_frag->fr_literal; |
2854 | ||
2855 | if (!fixP->fx_bit_fixP) | |
48401fcf TT |
2856 | { |
2857 | /* For callx, we always want to write out zero, and emit a | |
2858 | symbolic relocation. */ | |
2859 | if (fixP->fx_bsr) | |
2860 | val = 0; | |
2861 | ||
2862 | fixP->fx_addnumber = val; | |
2863 | md_number_to_imm (place, val, fixP->fx_size, fixP); | |
2864 | } | |
355afbcd | 2865 | else |
f3d817d8 DM |
2866 | md_number_to_field (place, val, fixP->fx_bit_fixP); |
2867 | } | |
fecd2382 RP |
2868 | |
2869 | #if defined(OBJ_AOUT) | defined(OBJ_BOUT) | |
355afbcd KR |
2870 | void |
2871 | tc_bout_fix_to_chars (where, fixP, segment_address_in_file) | |
2872 | char *where; | |
2873 | fixS *fixP; | |
2874 | relax_addressT segment_address_in_file; | |
fecd2382 | 2875 | { |
f3d817d8 | 2876 | static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; |
355afbcd KR |
2877 | struct relocation_info ri; |
2878 | symbolS *symbolP; | |
2879 | ||
355afbcd KR |
2880 | memset ((char *) &ri, '\0', sizeof (ri)); |
2881 | symbolP = fixP->fx_addsy; | |
2882 | know (symbolP != 0 || fixP->fx_r_type != NO_RELOC); | |
2883 | ri.r_bsr = fixP->fx_bsr; /*SAC LD RELAX HACK */ | |
2884 | /* These two 'cuz of NS32K */ | |
f3d817d8 | 2885 | ri.r_callj = fixP->fx_tcbit; |
355afbcd | 2886 | if (fixP->fx_bit_fixP) |
f3d817d8 | 2887 | ri.r_length = 2; |
355afbcd | 2888 | else |
f3d817d8 | 2889 | ri.r_length = nbytes_r_length[fixP->fx_size]; |
355afbcd KR |
2890 | ri.r_pcrel = fixP->fx_pcrel; |
2891 | ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file; | |
2892 | ||
2893 | if (fixP->fx_r_type != NO_RELOC) | |
2894 | { | |
2895 | switch (fixP->fx_r_type) | |
2896 | { | |
2897 | case rs_align: | |
2898 | ri.r_index = -2; | |
2899 | ri.r_pcrel = 1; | |
2900 | ri.r_length = fixP->fx_size - 1; | |
2901 | break; | |
2902 | case rs_org: | |
2903 | ri.r_index = -2; | |
2904 | ri.r_pcrel = 0; | |
2905 | break; | |
2906 | case rs_fill: | |
2907 | ri.r_index = -1; | |
2908 | break; | |
2909 | default: | |
2910 | abort (); | |
fecd2382 | 2911 | } |
355afbcd KR |
2912 | ri.r_extern = 0; |
2913 | } | |
f3d817d8 | 2914 | else if (linkrelax || !S_IS_DEFINED (symbolP) || fixP->fx_bsr) |
355afbcd KR |
2915 | { |
2916 | ri.r_extern = 1; | |
2917 | ri.r_index = symbolP->sy_number; | |
2918 | } | |
2919 | else | |
2920 | { | |
2921 | ri.r_extern = 0; | |
2922 | ri.r_index = S_GET_TYPE (symbolP); | |
2923 | } | |
2924 | ||
2925 | /* Output the relocation information in machine-dependent form. */ | |
2926 | md_ri_to_chars (where, &ri); | |
f3d817d8 | 2927 | } |
fecd2382 | 2928 | |
fecd2382 RP |
2929 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
2930 | ||
f3d817d8 DM |
2931 | #if defined (OBJ_COFF) && defined (BFD) |
2932 | short | |
2933 | tc_coff_fix2rtype (fixP) | |
2934 | fixS *fixP; | |
2935 | { | |
2936 | if (fixP->fx_bsr) | |
2937 | abort (); | |
2938 | ||
2939 | if (fixP->fx_pcrel == 0 && fixP->fx_size == 4) | |
2940 | return R_RELLONG; | |
2941 | ||
2942 | if (fixP->fx_pcrel != 0 && fixP->fx_size == 4) | |
2943 | return R_IPRMED; | |
2944 | ||
2945 | abort (); | |
f9e90c2e | 2946 | return 0; |
f3d817d8 DM |
2947 | } |
2948 | ||
2949 | int | |
2950 | tc_coff_sizemachdep (frag) | |
2951 | fragS *frag; | |
2952 | { | |
2953 | if (frag->fr_next) | |
2954 | return frag->fr_next->fr_address - frag->fr_address; | |
2955 | else | |
2956 | return 0; | |
2957 | } | |
2958 | #endif | |
2959 | ||
2960 | /* Align an address by rounding it up to the specified boundary. */ | |
c47d388b | 2961 | valueT |
355afbcd KR |
2962 | md_section_align (seg, addr) |
2963 | segT seg; | |
c47d388b | 2964 | valueT addr; /* Address to be rounded up */ |
fecd2382 | 2965 | { |
355afbcd KR |
2966 | return ((addr + (1 << section_alignment[(int) seg]) - 1) & (-1 << section_alignment[(int) seg])); |
2967 | } /* md_section_align() */ | |
fecd2382 | 2968 | |
f9e90c2e ILT |
2969 | extern int coff_flags; |
2970 | ||
fecd2382 | 2971 | #ifdef OBJ_COFF |
355afbcd KR |
2972 | void |
2973 | tc_headers_hook (headers) | |
2974 | object_headers *headers; | |
fecd2382 | 2975 | { |
f9e90c2e | 2976 | switch (architecture) |
355afbcd | 2977 | { |
f9e90c2e ILT |
2978 | case ARCH_KA: |
2979 | coff_flags |= F_I960KA; | |
2980 | break; | |
2981 | ||
2982 | case ARCH_KB: | |
2983 | coff_flags |= F_I960KB; | |
2984 | break; | |
2985 | ||
2986 | case ARCH_MC: | |
2987 | coff_flags |= F_I960MC; | |
2988 | break; | |
2989 | ||
2990 | case ARCH_CA: | |
2991 | coff_flags |= F_I960CA; | |
2992 | break; | |
2993 | ||
48401fcf TT |
2994 | case ARCH_JX: |
2995 | coff_flags |= F_I960JX; | |
2996 | break; | |
2997 | ||
f9e90c2e ILT |
2998 | case ARCH_HX: |
2999 | coff_flags |= F_I960HX; | |
3000 | break; | |
3001 | ||
f9e90c2e ILT |
3002 | default: |
3003 | if (iclasses_seen == I_BASE) | |
3004 | coff_flags |= F_I960CORE; | |
3005 | else if (iclasses_seen & I_CX) | |
3006 | coff_flags |= F_I960CA; | |
48401fcf | 3007 | else if (iclasses_seen & I_HX) |
f9e90c2e | 3008 | coff_flags |= F_I960HX; |
48401fcf TT |
3009 | else if (iclasses_seen & I_JX) |
3010 | coff_flags |= F_I960JX; | |
f9e90c2e ILT |
3011 | else if (iclasses_seen & I_CX2) |
3012 | coff_flags |= F_I960CA; | |
3013 | else if (iclasses_seen & I_MIL) | |
3014 | coff_flags |= F_I960MC; | |
3015 | else if (iclasses_seen & (I_DEC | I_FP)) | |
3016 | coff_flags |= F_I960KB; | |
3017 | else | |
3018 | coff_flags |= F_I960KA; | |
3019 | break; | |
355afbcd | 3020 | } |
355afbcd | 3021 | |
0e6f2f82 | 3022 | if (flag_readonly_data_in_text) |
355afbcd KR |
3023 | { |
3024 | headers->filehdr.f_magic = I960RWMAGIC; | |
3025 | headers->aouthdr.magic = OMAGIC; | |
3026 | } | |
3027 | else | |
3028 | { | |
3029 | headers->filehdr.f_magic = I960ROMAGIC; | |
3030 | headers->aouthdr.magic = NMAGIC; | |
3031 | } /* set magic numbers */ | |
f3d817d8 | 3032 | } |
355afbcd | 3033 | |
fecd2382 RP |
3034 | #endif /* OBJ_COFF */ |
3035 | ||
0e6f2f82 KR |
3036 | /* Things going on here: |
3037 | ||
3038 | For bout, We need to assure a couple of simplifying | |
3039 | assumptions about leafprocs for the linker: the leafproc | |
3040 | entry symbols will be defined in the same assembly in | |
3041 | which they're declared with the '.leafproc' directive; | |
3042 | and if a leafproc has both 'call' and 'bal' entry points | |
3043 | they are both global or both local. | |
3044 | ||
3045 | For coff, the call symbol has a second aux entry that | |
3046 | contains the bal entry point. The bal symbol becomes a | |
3047 | label. | |
3048 | ||
3049 | For coff representation, the call symbol has a second aux entry that | |
3050 | contains the bal entry point. The bal symbol becomes a label. */ | |
fecd2382 | 3051 | |
355afbcd KR |
3052 | void |
3053 | tc_crawl_symbol_chain (headers) | |
3054 | object_headers *headers; | |
fecd2382 | 3055 | { |
355afbcd KR |
3056 | symbolS *symbolP; |
3057 | ||
3058 | for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP)) | |
3059 | { | |
fecd2382 | 3060 | #ifdef OBJ_COFF |
355afbcd KR |
3061 | if (TC_S_IS_SYSPROC (symbolP)) |
3062 | { | |
3063 | /* second aux entry already contains the sysproc number */ | |
3064 | S_SET_NUMBER_AUXILIARY (symbolP, 2); | |
3065 | S_SET_STORAGE_CLASS (symbolP, C_SCALL); | |
3066 | S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT)); | |
3067 | continue; | |
3068 | } /* rewrite sysproc */ | |
fecd2382 | 3069 | #endif /* OBJ_COFF */ |
355afbcd KR |
3070 | |
3071 | if (!TC_S_IS_BALNAME (symbolP) && !TC_S_IS_CALLNAME (symbolP)) | |
3072 | { | |
3073 | continue; | |
3074 | } /* Not a leafproc symbol */ | |
3075 | ||
3076 | if (!S_IS_DEFINED (symbolP)) | |
3077 | { | |
48401fcf | 3078 | as_bad (_("leafproc symbol '%s' undefined"), S_GET_NAME (symbolP)); |
355afbcd KR |
3079 | } /* undefined leaf */ |
3080 | ||
3081 | if (TC_S_IS_CALLNAME (symbolP)) | |
3082 | { | |
3083 | symbolS *balP = tc_get_bal_of_call (symbolP); | |
3084 | if (S_IS_EXTERNAL (symbolP) != S_IS_EXTERNAL (balP)) | |
3085 | { | |
3086 | S_SET_EXTERNAL (symbolP); | |
3087 | S_SET_EXTERNAL (balP); | |
48401fcf | 3088 | as_warn (_("Warning: making leafproc entries %s and %s both global\n"), |
355afbcd KR |
3089 | S_GET_NAME (symbolP), S_GET_NAME (balP)); |
3090 | } /* externality mismatch */ | |
3091 | } /* if callname */ | |
3092 | } /* walk the symbol chain */ | |
f3d817d8 | 3093 | } |
fecd2382 | 3094 | |
0e6f2f82 KR |
3095 | /* For aout or bout, the bal immediately follows the call. |
3096 | ||
3097 | For coff, we cheat and store a pointer to the bal symbol in the | |
3098 | second aux entry of the call. */ | |
fecd2382 | 3099 | |
355afbcd KR |
3100 | #undef OBJ_ABOUT |
3101 | #ifdef OBJ_AOUT | |
3102 | #define OBJ_ABOUT | |
3103 | #endif | |
3104 | #ifdef OBJ_BOUT | |
3105 | #define OBJ_ABOUT | |
3106 | #endif | |
3107 | ||
3108 | void | |
3109 | tc_set_bal_of_call (callP, balP) | |
3110 | symbolS *callP; | |
3111 | symbolS *balP; | |
fecd2382 | 3112 | { |
355afbcd KR |
3113 | know (TC_S_IS_CALLNAME (callP)); |
3114 | know (TC_S_IS_BALNAME (balP)); | |
3115 | ||
fecd2382 | 3116 | #ifdef OBJ_COFF |
355afbcd | 3117 | |
48401fcf | 3118 | callP->sy_tc = balP; |
355afbcd KR |
3119 | S_SET_NUMBER_AUXILIARY (callP, 2); |
3120 | ||
3121 | #else /* ! OBJ_COFF */ | |
3122 | #ifdef OBJ_ABOUT | |
3123 | ||
3124 | /* If the 'bal' entry doesn't immediately follow the 'call' | |
0e6f2f82 KR |
3125 | * symbol, unlink it from the symbol list and re-insert it. |
3126 | */ | |
355afbcd KR |
3127 | if (symbol_next (callP) != balP) |
3128 | { | |
3129 | symbol_remove (balP, &symbol_rootP, &symbol_lastP); | |
3130 | symbol_append (balP, callP, &symbol_rootP, &symbol_lastP); | |
3131 | } /* if not in order */ | |
3132 | ||
3133 | #else /* ! OBJ_ABOUT */ | |
3134 | (as yet unwritten.); | |
3135 | #endif /* ! OBJ_ABOUT */ | |
3136 | #endif /* ! OBJ_COFF */ | |
f3d817d8 | 3137 | } |
355afbcd | 3138 | |
48401fcf TT |
3139 | symbolS * |
3140 | tc_get_bal_of_call (callP) | |
355afbcd | 3141 | symbolS *callP; |
fecd2382 | 3142 | { |
355afbcd KR |
3143 | symbolS *retval; |
3144 | ||
3145 | know (TC_S_IS_CALLNAME (callP)); | |
3146 | ||
fecd2382 | 3147 | #ifdef OBJ_COFF |
48401fcf | 3148 | retval = callP->sy_tc; |
fecd2382 | 3149 | #else |
355afbcd KR |
3150 | #ifdef OBJ_ABOUT |
3151 | retval = symbol_next (callP); | |
3152 | #else | |
3153 | (as yet unwritten.); | |
3154 | #endif /* ! OBJ_ABOUT */ | |
3155 | #endif /* ! OBJ_COFF */ | |
3156 | ||
3157 | know (TC_S_IS_BALNAME (retval)); | |
48401fcf | 3158 | return retval; |
355afbcd KR |
3159 | } /* _tc_get_bal_of_call() */ |
3160 | ||
3161 | void | |
3162 | tc_coff_symbol_emit_hook (symbolP) | |
3163 | symbolS *symbolP; | |
fecd2382 | 3164 | { |
355afbcd KR |
3165 | if (TC_S_IS_CALLNAME (symbolP)) |
3166 | { | |
fecd2382 | 3167 | #ifdef OBJ_COFF |
355afbcd KR |
3168 | symbolS *balP = tc_get_bal_of_call (symbolP); |
3169 | ||
0e6f2f82 | 3170 | #if 0 |
355afbcd | 3171 | /* second aux entry contains the bal entry point */ |
0e6f2f82 KR |
3172 | S_SET_NUMBER_AUXILIARY (symbolP, 2); |
3173 | #endif | |
355afbcd | 3174 | symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP); |
48401fcf TT |
3175 | if (S_GET_STORAGE_CLASS (symbolP) == C_EXT) |
3176 | S_SET_STORAGE_CLASS (symbolP, C_LEAFEXT); | |
3177 | else | |
3178 | S_SET_STORAGE_CLASS (symbolP, C_LEAFSTAT); | |
355afbcd KR |
3179 | S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT)); |
3180 | /* fix up the bal symbol */ | |
3181 | S_SET_STORAGE_CLASS (balP, C_LABEL); | |
fecd2382 | 3182 | #endif /* OBJ_COFF */ |
355afbcd | 3183 | } /* only on calls */ |
f3d817d8 | 3184 | } |
fecd2382 | 3185 | |
09952cd9 KR |
3186 | void |
3187 | i960_handle_align (fragp) | |
3188 | fragS *fragp; | |
3189 | { | |
09952cd9 KR |
3190 | if (!linkrelax) |
3191 | return; | |
3192 | ||
f3d817d8 DM |
3193 | #ifndef OBJ_BOUT |
3194 | ||
48401fcf | 3195 | as_bad (_("option --link-relax is only supported in b.out format")); |
f3d817d8 DM |
3196 | linkrelax = 0; |
3197 | return; | |
3198 | ||
3199 | #else | |
3200 | ||
09952cd9 KR |
3201 | /* The text section "ends" with another alignment reloc, to which we |
3202 | aren't adding padding. */ | |
3203 | if (fragp->fr_next == text_last_frag | |
3204 | || fragp->fr_next == data_last_frag) | |
f3d817d8 | 3205 | return; |
09952cd9 KR |
3206 | |
3207 | /* alignment directive */ | |
f9e90c2e ILT |
3208 | fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0, |
3209 | (int) fragp->fr_type); | |
f3d817d8 DM |
3210 | #endif /* OBJ_BOUT */ |
3211 | } | |
3212 | ||
3213 | int | |
3214 | i960_validate_fix (fixP, this_segment_type, add_symbolPP) | |
3215 | fixS *fixP; | |
3216 | segT this_segment_type; | |
3217 | symbolS **add_symbolPP; | |
3218 | { | |
3219 | #define add_symbolP (*add_symbolPP) | |
3220 | if (fixP->fx_tcbit && TC_S_IS_CALLNAME (add_symbolP)) | |
3221 | { | |
3222 | /* Relocation should be done via the associated 'bal' | |
0e6f2f82 | 3223 | entry point symbol. */ |
f3d817d8 DM |
3224 | |
3225 | if (!TC_S_IS_BALNAME (tc_get_bal_of_call (add_symbolP))) | |
3226 | { | |
48401fcf | 3227 | as_bad (_("No 'bal' entry point for leafproc %s"), |
f3d817d8 DM |
3228 | S_GET_NAME (add_symbolP)); |
3229 | return 1; | |
3230 | } | |
3231 | fixP->fx_addsy = add_symbolP = tc_get_bal_of_call (add_symbolP); | |
3232 | } | |
3233 | #if 0 | |
0e6f2f82 KR |
3234 | /* Still have to work out other conditions for these tests. */ |
3235 | { | |
3236 | if (fixP->fx_tcbit) | |
3237 | { | |
48401fcf | 3238 | as_bad (_("callj to difference of two symbols")); |
0e6f2f82 KR |
3239 | return 1; |
3240 | } | |
3241 | reloc_callj (fixP); | |
3242 | if ((int) fixP->fx_bit_fixP == 13) | |
3243 | { | |
3244 | /* This is a COBR instruction. They have only a 13-bit | |
3245 | displacement and are only to be used for local branches: | |
3246 | flag as error, don't generate relocation. */ | |
48401fcf | 3247 | as_bad (_("can't use COBR format with external label")); |
0e6f2f82 KR |
3248 | fixP->fx_addsy = NULL; /* No relocations please. */ |
3249 | return 1; | |
3250 | } | |
3251 | } | |
f3d817d8 DM |
3252 | #endif |
3253 | #undef add_symbolP | |
3254 | return 0; | |
09952cd9 KR |
3255 | } |
3256 | ||
8b228fe9 | 3257 | /* end of tc-i960.c */ |