[thirdparty/binutils-gdb.git] / gas / config / tc-ip2k.c

/* tc-ip2k.c -- Assembler for the Scenix IP2xxx.
   Copyright (C) 2000-2021 Free Software Foundation, Inc.

   This file is part of GAS, the GNU Assembler.

   GAS is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   GAS is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS; see the file COPYING.  If not, write to
   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
   Boston, MA 02110-1301, USA.  */

#include "as.h"
#include "subsegs.h"
#include "symcat.h"
#include "opcodes/ip2k-desc.h"
#include "opcodes/ip2k-opc.h"
#include "cgen.h"
#include "elf/common.h"
#include "elf/ip2k.h"

/* Structure to hold all of the different components describing
   an individual instruction.  */
typedef struct
{
  const CGEN_INSN *	insn;
  const CGEN_INSN *	orig_insn;
  CGEN_FIELDS		fields;
#if CGEN_INT_INSN_P
  CGEN_INSN_INT         buffer [1];
#define INSN_VALUE(buf) (*(buf))
#else
  unsigned char         buffer [CGEN_MAX_INSN_SIZE];
#define INSN_VALUE(buf) (buf)
#endif
  char *		addr;
  fragS *		frag;
  int                   num_fixups;
  fixS *                fixups [GAS_CGEN_MAX_FIXUPS];
  int                   indices [MAX_OPERAND_INSTANCES];
}
ip2k_insn;

const char comment_chars[]        = ";";
const char line_comment_chars[]   = "#";
const char line_separator_chars[] = "";
const char EXP_CHARS[]            = "eE";
const char FLT_CHARS[]            = "dD";

/* Flag to detect when switching to code section where insn alignment is
   implied.  */
static int force_code_align = 0;

/* Mach selected from command line.  */
static int ip2k_mach = 0;
static unsigned ip2k_mach_bitmask = 0;


static void
ip2k_elf_section_rtn (int i)
{
  obj_elf_section(i);

  if (force_code_align)
    {
      do_align (1, NULL, 0, 0);
      force_code_align = 0;
    }
}

static void
ip2k_elf_section_text (int i)
{
  obj_elf_text(i);

  do_align (1, NULL, 0, 0);
  force_code_align = 0;
}

/* The target specific pseudo-ops which we support.  */
const pseudo_typeS md_pseudo_table[] =
{
    { "text",   ip2k_elf_section_text,  0 },
    { "sect",   ip2k_elf_section_rtn,   0 },
    { NULL, 	NULL,			0 }
};

\f

enum options
{
  OPTION_CPU_IP2022 = OPTION_MD_BASE,
  OPTION_CPU_IP2022EXT
};

struct option md_longopts[] =
{
  { "mip2022",     no_argument, NULL, OPTION_CPU_IP2022 },
  { "mip2022ext",  no_argument, NULL, OPTION_CPU_IP2022EXT },
  { NULL,           no_argument, NULL, 0 },
};
size_t md_longopts_size = sizeof (md_longopts);

const char * md_shortopts = "";

int
md_parse_option (int c ATTRIBUTE_UNUSED, const char * arg ATTRIBUTE_UNUSED)
{
  switch (c)
    {
    case OPTION_CPU_IP2022:
      ip2k_mach = bfd_mach_ip2022;
      ip2k_mach_bitmask = 1 << MACH_IP2022;
      break;

    case OPTION_CPU_IP2022EXT:
      ip2k_mach = bfd_mach_ip2022ext;
      ip2k_mach_bitmask = 1 << MACH_IP2022EXT;
      break;

    default:
      return 0;
    }

  return 1;
}

void
md_show_usage (FILE * stream)
{
  fprintf (stream, _("IP2K specific command line options:\n"));
  fprintf (stream, _("  -mip2022               restrict to IP2022 insns \n"));
  fprintf (stream, _("  -mip2022ext            permit extended IP2022 insn\n"));
}

\f
void
md_begin (void)
{
  /* Initialize the `cgen' interface.  */

  /* Set the machine number and endian.  */
  gas_cgen_cpu_desc = ip2k_cgen_cpu_open (CGEN_CPU_OPEN_MACHS,
					  ip2k_mach_bitmask,
					  CGEN_CPU_OPEN_ENDIAN,
					  CGEN_ENDIAN_BIG,
					  CGEN_CPU_OPEN_END);
  ip2k_cgen_init_asm (gas_cgen_cpu_desc);

  /* This is a callback from cgen to gas to parse operands.  */
  cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);

  /* Set the machine type.  */
  bfd_default_set_arch_mach (stdoutput, bfd_arch_ip2k, ip2k_mach);

  literal_prefix_dollar_hex = TRUE;
}


void
md_assemble (char * str)
{
  ip2k_insn insn;
  char * errmsg;

  /* Initialize GAS's cgen interface for a new instruction.  */
  gas_cgen_init_parse ();

  insn.insn = ip2k_cgen_assemble_insn
      (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);

  if (!insn.insn)
    {
      as_bad ("%s", errmsg);
      return;
    }

  /* Check for special relocation required by SKIP instructions.  */
  if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SKIPA))
    /* Unconditional skip has a 1-bit relocation of the current pc, so
       that we emit either sb pcl.0 or snb pcl.0 depending on whether
       the PCL (pc + 2) >> 1 is odd or even.  */
    {
      enum cgen_parse_operand_result result_type;
      bfd_vma value;
      const char *curpc_plus_2 = ".+2";
      const char *err;

      err = cgen_parse_address (gas_cgen_cpu_desc, & curpc_plus_2,
				IP2K_OPERAND_ADDR16CJP,
				BFD_RELOC_IP2K_PC_SKIP,
				& result_type, & value);
      if (err)
	{
	  as_bad ("%s", err);
	  return;
	}
    }

  /* Doesn't really matter what we pass for RELAX_P here.  */
  gas_cgen_finish_insn (insn.insn, insn.buffer,
			CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
}

valueT
md_section_align (segT segment, valueT size)
{
  int align = bfd_section_alignment (segment);

  return ((size + (1 << align) - 1) & -(1 << align));
}


symbolS *
md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
{
    return 0;
}
\f
int
md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
			       segT    segment ATTRIBUTE_UNUSED)
{
  as_fatal (_("relaxation not supported\n"));
  return 1;
}


/* *fragP has been relaxed to its final size, and now needs to have
   the bytes inside it modified to conform to the new size.

   Called after relaxation is finished.
   fragP->fr_type == rs_machine_dependent.
   fragP->fr_subtype is the subtype of what the address relaxed to.  */

void
md_convert_frag (bfd   * abfd  ATTRIBUTE_UNUSED,
		 segT    sec   ATTRIBUTE_UNUSED,
		 fragS * fragP ATTRIBUTE_UNUSED)
{
}

\f
/* Functions concerning relocs.  */

long
md_pcrel_from (fixS *fixP ATTRIBUTE_UNUSED)
{
  abort ();
}


/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
   Returns BFD_RELOC_NONE if no reloc type can be found.
   *FIXP may be modified if desired.  */

bfd_reloc_code_real_type
md_cgen_lookup_reloc (const CGEN_INSN *    insn     ATTRIBUTE_UNUSED,
		      const CGEN_OPERAND * operand,
		      fixS *               fixP     ATTRIBUTE_UNUSED)
{
  bfd_reloc_code_real_type result;

  result = BFD_RELOC_NONE;

  switch (operand->type)
    {
    case IP2K_OPERAND_FR:
    case IP2K_OPERAND_ADDR16L:
    case IP2K_OPERAND_ADDR16H:
    case IP2K_OPERAND_LIT8:
      /* These may have been processed at parse time.  */
      if (fixP->fx_cgen.opinfo != 0)
	result = fixP->fx_cgen.opinfo;
      fixP->fx_no_overflow = 1;
      break;

    case IP2K_OPERAND_ADDR16CJP:
      result = fixP->fx_cgen.opinfo;
      if (result == 0 || result == BFD_RELOC_NONE)
	result = BFD_RELOC_IP2K_ADDR16CJP;
      fixP->fx_no_overflow = 1;
      break;

    case IP2K_OPERAND_ADDR16P:
      result = BFD_RELOC_IP2K_PAGE3;
      fixP->fx_no_overflow = 1;
      break;

    default:
      result = BFD_RELOC_NONE;
      break;
    }

  return result;
}


/* Write a value out to the object file, using the appropriate endianness.  */

void
md_number_to_chars (char * buf, valueT val, int n)
{
  number_to_chars_bigendian (buf, val, n);
}

const char *
md_atof (int type, char * litP, int *  sizeP)
{
  return ieee_md_atof (type, litP, sizeP, TRUE);
}


/* See whether we need to force a relocation into the output file.
   Force most of them, since the linker's bfd relocation engine
   understands range limits better than gas' cgen fixup engine.
   Consider the case of a fixup intermediate value being larger than
   the instruction it will be eventually encoded within.  */

int
ip2k_force_relocation (fixS * fix)
{
  switch (fix->fx_r_type)
    {
    case BFD_RELOC_IP2K_FR9:
    case BFD_RELOC_IP2K_FR_OFFSET:
    case BFD_RELOC_IP2K_BANK:
    case BFD_RELOC_IP2K_ADDR16CJP:
    case BFD_RELOC_IP2K_PAGE3:
    case BFD_RELOC_IP2K_LO8DATA:
    case BFD_RELOC_IP2K_HI8DATA:
    case BFD_RELOC_IP2K_EX8DATA:
    case BFD_RELOC_IP2K_LO8INSN:
    case BFD_RELOC_IP2K_HI8INSN:
    case BFD_RELOC_IP2K_PC_SKIP:
    case BFD_RELOC_IP2K_TEXT:
      return 1;

    case BFD_RELOC_16:
      if (fix->fx_subsy && S_IS_DEFINED (fix->fx_subsy)
	  && fix->fx_addsy && S_IS_DEFINED (fix->fx_addsy)
	  && (S_GET_SEGMENT (fix->fx_addsy)->flags & SEC_CODE))
	{
	  fix->fx_r_type = BFD_RELOC_IP2K_TEXT;
	  return 0;
	}
      break;

    default:
      break;
    }

  return generic_force_reloc (fix);
}

void
ip2k_apply_fix (fixS *fixP, valueT *valueP, segT seg)
{
  if (fixP->fx_r_type == BFD_RELOC_IP2K_TEXT
      && ! fixP->fx_addsy
      && ! fixP->fx_subsy)
    {
      *valueP = ((int)(* valueP)) / 2;
      fixP->fx_r_type = BFD_RELOC_16;
    }
  else if (fixP->fx_r_type == BFD_RELOC_UNUSED + IP2K_OPERAND_FR)
    {
      /* Must be careful when we are fixing up an FR.  We could be
	 fixing up an offset to (SP) or (DP) in which case we don't
	 want to step on the top 2 bits of the FR operand.  The
	 gas_cgen_md_apply_fix doesn't know any better and overwrites
	 the entire operand.  We counter this by adding the bits
	 to the new value.  */
      char *where = fixP->fx_frag->fr_literal + fixP->fx_where;

      /* Canonical name, since used a lot.  */
      CGEN_CPU_DESC cd = gas_cgen_cpu_desc;
      CGEN_INSN_INT insn_value
	= cgen_get_insn_value (cd, (unsigned char *) where,
			       CGEN_INSN_BITSIZE (fixP->fx_cgen.insn),
			       gas_cgen_cpu_desc->insn_endian);
      /* Preserve (DP) or (SP) specification.  */
      *valueP += (insn_value & 0x180);
    }

  gas_cgen_md_apply_fix (fixP, valueP, seg);
}

int
ip2k_elf_section_flags (flagword flags,
			bfd_vma attr ATTRIBUTE_UNUSED,
			int type ATTRIBUTE_UNUSED)
{
  /* This is used to detect when the section changes to an executable section.
     This function is called by the elf section processing.  When we note an
     executable section specifier we set an internal flag to denote when
     word alignment should be forced.  */
  if (flags & SEC_CODE)
    force_code_align = 1;

  return flags;
}
Commit	Line	Data
a40cbfa3	1	/* tc-ip2k.c -- Assembler for the Scenix IP2xxx.
250d07de	2	Copyright (C) 2000-2021 Free Software Foundation, Inc.
a40cbfa3 NC	3
	4	This file is part of GAS, the GNU Assembler.
	5
	6	GAS is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
ec2655a6	8	the Free Software Foundation; either version 3, or (at your option)
a40cbfa3 NC	9	any later version.
	10
	11	GAS is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with GAS; see the file COPYING. If not, write to
4b4da160 NC	18	the Free Software Foundation, 51 Franklin Street - Fifth Floor,
4b4da160 NC	19	Boston, MA 02110-1301, USA. */
a40cbfa3	20
a40cbfa3	21	#include "as.h"
3739860c	22	#include "subsegs.h"
a40cbfa3 NC	23	#include "symcat.h"
	24	#include "opcodes/ip2k-desc.h"
	25	#include "opcodes/ip2k-opc.h"
	26	#include "cgen.h"
	27	#include "elf/common.h"
	28	#include "elf/ip2k.h"
a40cbfa3 NC	29
	30	/* Structure to hold all of the different components describing
	31	an individual instruction. */
	32	typedef struct
	33	{
	34	const CGEN_INSN * insn;
	35	const CGEN_INSN * orig_insn;
	36	CGEN_FIELDS fields;
	37	#if CGEN_INT_INSN_P
	38	CGEN_INSN_INT buffer [1];
	39	#define INSN_VALUE(buf) (*(buf))
	40	#else
	41	unsigned char buffer [CGEN_MAX_INSN_SIZE];
	42	#define INSN_VALUE(buf) (buf)
	43	#endif
	44	char * addr;
	45	fragS * frag;
	46	int num_fixups;
	47	fixS * fixups [GAS_CGEN_MAX_FIXUPS];
	48	int indices [MAX_OPERAND_INSTANCES];
	49	}
	50	ip2k_insn;
	51
	52	const char comment_chars[] = ";";
	53	const char line_comment_chars[] = "#";
3739860c	54	const char line_separator_chars[] = "";
a40cbfa3 NC	55	const char EXP_CHARS[] = "eE";
	56	const char FLT_CHARS[] = "dD";
	57
ea1562b3 NC	58	/* Flag to detect when switching to code section where insn alignment is
	59	implied. */
	60	static int force_code_align = 0;
	61
	62	/* Mach selected from command line. */
	63	static int ip2k_mach = 0;
	64	static unsigned ip2k_mach_bitmask = 0;
	65
	66
	67	static void
	68	ip2k_elf_section_rtn (int i)
	69	{
	70	obj_elf_section(i);
	71
	72	if (force_code_align)
	73	{
f86f5863	74	do_align (1, NULL, 0, 0);
ea1562b3	75	force_code_align = 0;
ea1562b3 NC	76	}
	77	}
	78
	79	static void
	80	ip2k_elf_section_text (int i)
	81	{
ea1562b3 NC	82	obj_elf_text(i);
ea1562b3 NC	83
f86f5863	84	do_align (1, NULL, 0, 0);
ea1562b3	85	force_code_align = 0;
ea1562b3	86	}
a40cbfa3 NC	87
	88	/* The target specific pseudo-ops which we support. */
	89	const pseudo_typeS md_pseudo_table[] =
	90	{
a40cbfa3 NC	91	{ "text", ip2k_elf_section_text, 0 },
	92	{ "sect", ip2k_elf_section_rtn, 0 },
	93	{ NULL, NULL, 0 }
	94	};
	95
	96	\f
	97
ea1562b3 NC	98	enum options
	99	{
	100	OPTION_CPU_IP2022 = OPTION_MD_BASE,
	101	OPTION_CPU_IP2022EXT
	102	};
a40cbfa3	103
3739860c	104	struct option md_longopts[] =
a40cbfa3 NC	105	{
	106	{ "mip2022", no_argument, NULL, OPTION_CPU_IP2022 },
	107	{ "mip2022ext", no_argument, NULL, OPTION_CPU_IP2022EXT },
	108	{ NULL, no_argument, NULL, 0 },
	109	};
	110	size_t md_longopts_size = sizeof (md_longopts);
	111
	112	const char * md_shortopts = "";
	113
a40cbfa3	114	int
17b9d67d	115	md_parse_option (int c ATTRIBUTE_UNUSED, const char * arg ATTRIBUTE_UNUSED)
a40cbfa3 NC	116	{
	117	switch (c)
	118	{
	119	case OPTION_CPU_IP2022:
	120	ip2k_mach = bfd_mach_ip2022;
	121	ip2k_mach_bitmask = 1 << MACH_IP2022;
	122	break;
	123
	124	case OPTION_CPU_IP2022EXT:
	125	ip2k_mach = bfd_mach_ip2022ext;
	126	ip2k_mach_bitmask = 1 << MACH_IP2022EXT;
	127	break;
	128
	129	default:
	130	return 0;
	131	}
	132
	133	return 1;
	134	}
	135
a40cbfa3	136	void
ea1562b3	137	md_show_usage (FILE * stream)
a40cbfa3 NC	138	{
	139	fprintf (stream, _("IP2K specific command line options:\n"));
	140	fprintf (stream, _(" -mip2022 restrict to IP2022 insns \n"));
	141	fprintf (stream, _(" -mip2022ext permit extended IP2022 insn\n"));
	142	}
	143
	144	\f
	145	void
ea1562b3	146	md_begin (void)
a40cbfa3 NC	147	{
a40cbfa3 NC	148	/* Initialize the `cgen' interface. */
3739860c	149
a40cbfa3 NC	150	/* Set the machine number and endian. */
	151	gas_cgen_cpu_desc = ip2k_cgen_cpu_open (CGEN_CPU_OPEN_MACHS,
	152	ip2k_mach_bitmask,
	153	CGEN_CPU_OPEN_ENDIAN,
	154	CGEN_ENDIAN_BIG,
	155	CGEN_CPU_OPEN_END);
	156	ip2k_cgen_init_asm (gas_cgen_cpu_desc);
	157
	158	/* This is a callback from cgen to gas to parse operands. */
	159	cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
	160
	161	/* Set the machine type. */
	162	bfd_default_set_arch_mach (stdoutput, bfd_arch_ip2k, ip2k_mach);
e2d15955 JD	163
e2d15955 JD	164	literal_prefix_dollar_hex = TRUE;
a40cbfa3 NC	165	}
	166
	167
	168	void
ea1562b3	169	md_assemble (char * str)
a40cbfa3 NC	170	{
	171	ip2k_insn insn;
	172	char * errmsg;
	173
	174	/* Initialize GAS's cgen interface for a new instruction. */
	175	gas_cgen_init_parse ();
	176
	177	insn.insn = ip2k_cgen_assemble_insn
	178	(gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
	179
	180	if (!insn.insn)
	181	{
	182	as_bad ("%s", errmsg);
	183	return;
	184	}
	185
	186	/* Check for special relocation required by SKIP instructions. */
	187	if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SKIPA))
	188	/* Unconditional skip has a 1-bit relocation of the current pc, so
	189	that we emit either sb pcl.0 or snb pcl.0 depending on whether
	190	the PCL (pc + 2) >> 1 is odd or even. */
	191	{
	192	enum cgen_parse_operand_result result_type;
2132e3a3	193	bfd_vma value;
a40cbfa3	194	const char *curpc_plus_2 = ".+2";
64384dfd	195	const char *err;
a40cbfa3	196
64384dfd AM	197	err = cgen_parse_address (gas_cgen_cpu_desc, & curpc_plus_2,
	198	IP2K_OPERAND_ADDR16CJP,
	199	BFD_RELOC_IP2K_PC_SKIP,
	200	& result_type, & value);
	201	if (err)
a40cbfa3	202	{
64384dfd	203	as_bad ("%s", err);
a40cbfa3 NC	204	return;
	205	}
	206	}
	207
	208	/* Doesn't really matter what we pass for RELAX_P here. */
	209	gas_cgen_finish_insn (insn.insn, insn.buffer,
	210	CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
	211	}
	212
	213	valueT
ea1562b3	214	md_section_align (segT segment, valueT size)
a40cbfa3	215	{
fd361982	216	int align = bfd_section_alignment (segment);
a40cbfa3	217
8d3842cd	218	return ((size + (1 << align) - 1) & -(1 << align));
a40cbfa3 NC	219	}
	220
	221
	222	symbolS *
ea1562b3	223	md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
a40cbfa3 NC	224	{
	225	return 0;
	226	}
	227	\f
	228	int
ea1562b3 NC	229	md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
ea1562b3 NC	230	segT segment ATTRIBUTE_UNUSED)
a40cbfa3	231	{
b2f58c0c	232	as_fatal (_("relaxation not supported\n"));
a40cbfa3	233	return 1;
3739860c	234	}
a40cbfa3 NC	235
	236
	237	/* *fragP has been relaxed to its final size, and now needs to have
	238	the bytes inside it modified to conform to the new size.
	239
	240	Called after relaxation is finished.
	241	fragP->fr_type == rs_machine_dependent.
	242	fragP->fr_subtype is the subtype of what the address relaxed to. */
	243
	244	void
ea1562b3 NC	245	md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
	246	segT sec ATTRIBUTE_UNUSED,
	247	fragS * fragP ATTRIBUTE_UNUSED)
a40cbfa3 NC	248	{
	249	}
	250
	251	\f
	252	/* Functions concerning relocs. */
	253
	254	long
b2f58c0c	255	md_pcrel_from (fixS *fixP ATTRIBUTE_UNUSED)
a40cbfa3	256	{
b2f58c0c	257	abort ();
a40cbfa3 NC	258	}
	259
	260
	261	/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
	262	Returns BFD_RELOC_NONE if no reloc type can be found.
	263	FIXP may be modified if desired. /
	264
	265	bfd_reloc_code_real_type
ea1562b3 NC	266	md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED,
	267	const CGEN_OPERAND * operand,
	268	fixS * fixP ATTRIBUTE_UNUSED)
a40cbfa3 NC	269	{
	270	bfd_reloc_code_real_type result;
	271
	272	result = BFD_RELOC_NONE;
	273
	274	switch (operand->type)
	275	{
	276	case IP2K_OPERAND_FR:
	277	case IP2K_OPERAND_ADDR16L:
	278	case IP2K_OPERAND_ADDR16H:
	279	case IP2K_OPERAND_LIT8:
	280	/* These may have been processed at parse time. */
	281	if (fixP->fx_cgen.opinfo != 0)
	282	result = fixP->fx_cgen.opinfo;
	283	fixP->fx_no_overflow = 1;
	284	break;
	285
	286	case IP2K_OPERAND_ADDR16CJP:
	287	result = fixP->fx_cgen.opinfo;
	288	if (result == 0 \|\| result == BFD_RELOC_NONE)
	289	result = BFD_RELOC_IP2K_ADDR16CJP;
	290	fixP->fx_no_overflow = 1;
	291	break;
	292
	293	case IP2K_OPERAND_ADDR16P:
	294	result = BFD_RELOC_IP2K_PAGE3;
	295	fixP->fx_no_overflow = 1;
	296	break;
	297
	298	default:
	299	result = BFD_RELOC_NONE;
	300	break;
	301	}
	302
	303	return result;
	304	}
	305
	306
	307	/* Write a value out to the object file, using the appropriate endianness. */
	308
	309	void
ea1562b3	310	md_number_to_chars (char * buf, valueT val, int n)
a40cbfa3 NC	311	{
	312	number_to_chars_bigendian (buf, val, n);
	313	}
	314
6d4af3c2	315	const char *
ea1562b3	316	md_atof (int type, char * litP, int * sizeP)
a40cbfa3	317	{
499ac353	318	return ieee_md_atof (type, litP, sizeP, TRUE);
a40cbfa3 NC	319	}
	320
	321
	322	/* See whether we need to force a relocation into the output file.
	323	Force most of them, since the linker's bfd relocation engine
	324	understands range limits better than gas' cgen fixup engine.
	325	Consider the case of a fixup intermediate value being larger than
	326	the instruction it will be eventually encoded within. */
	327
	328	int
ea1562b3	329	ip2k_force_relocation (fixS * fix)
a40cbfa3 NC	330	{
	331	switch (fix->fx_r_type)
	332	{
a40cbfa3 NC	333	case BFD_RELOC_IP2K_FR9:
	334	case BFD_RELOC_IP2K_FR_OFFSET:
	335	case BFD_RELOC_IP2K_BANK:
	336	case BFD_RELOC_IP2K_ADDR16CJP:
	337	case BFD_RELOC_IP2K_PAGE3:
	338	case BFD_RELOC_IP2K_LO8DATA:
	339	case BFD_RELOC_IP2K_HI8DATA:
	340	case BFD_RELOC_IP2K_EX8DATA:
	341	case BFD_RELOC_IP2K_LO8INSN:
	342	case BFD_RELOC_IP2K_HI8INSN:
	343	case BFD_RELOC_IP2K_PC_SKIP:
	344	case BFD_RELOC_IP2K_TEXT:
	345	return 1;
	346
	347	case BFD_RELOC_16:
a161fe53	348	if (fix->fx_subsy && S_IS_DEFINED (fix->fx_subsy)
a40cbfa3 NC	349	&& fix->fx_addsy && S_IS_DEFINED (fix->fx_addsy)
	350	&& (S_GET_SEGMENT (fix->fx_addsy)->flags & SEC_CODE))
	351	{
	352	fix->fx_r_type = BFD_RELOC_IP2K_TEXT;
	353	return 0;
	354	}
a161fe53	355	break;
a40cbfa3 NC	356
a40cbfa3 NC	357	default:
a161fe53	358	break;
a40cbfa3	359	}
a161fe53	360
ae6063d4	361	return generic_force_reloc (fix);
a40cbfa3 NC	362	}
	363
	364	void
55cf6793	365	ip2k_apply_fix (fixS fixP, valueT valueP, segT seg)
a40cbfa3 NC	366	{
	367	if (fixP->fx_r_type == BFD_RELOC_IP2K_TEXT
	368	&& ! fixP->fx_addsy
	369	&& ! fixP->fx_subsy)
	370	{
ea1562b3	371	valueP = ((int)( valueP)) / 2;
a40cbfa3 NC	372	fixP->fx_r_type = BFD_RELOC_16;
	373	}
	374	else if (fixP->fx_r_type == BFD_RELOC_UNUSED + IP2K_OPERAND_FR)
	375	{
	376	/* Must be careful when we are fixing up an FR. We could be
	377	fixing up an offset to (SP) or (DP) in which case we don't
	378	want to step on the top 2 bits of the FR operand. The
55cf6793	379	gas_cgen_md_apply_fix doesn't know any better and overwrites
a40cbfa3 NC	380	the entire operand. We counter this by adding the bits
	381	to the new value. */
	382	char *where = fixP->fx_frag->fr_literal + fixP->fx_where;
	383
	384	/* Canonical name, since used a lot. */
	385	CGEN_CPU_DESC cd = gas_cgen_cpu_desc;
	386	CGEN_INSN_INT insn_value
2132e3a3	387	= cgen_get_insn_value (cd, (unsigned char *) where,
d413a623 L	388	CGEN_INSN_BITSIZE (fixP->fx_cgen.insn),
d413a623 L	389	gas_cgen_cpu_desc->insn_endian);
a40cbfa3 NC	390	/* Preserve (DP) or (SP) specification. */
	391	*valueP += (insn_value & 0x180);
	392	}
	393
55cf6793	394	gas_cgen_md_apply_fix (fixP, valueP, seg);
a40cbfa3 NC	395	}
	396
	397	int
01e1a5bc NC	398	ip2k_elf_section_flags (flagword flags,
01e1a5bc NC	399	bfd_vma attr ATTRIBUTE_UNUSED,
ea1562b3	400	int type ATTRIBUTE_UNUSED)
a40cbfa3 NC	401	{
	402	/* This is used to detect when the section changes to an executable section.
	403	This function is called by the elf section processing. When we note an
	404	executable section specifier we set an internal flag to denote when
	405	word alignment should be forced. */
	406	if (flags & SEC_CODE)
	407	force_code_align = 1;
3739860c	408
a40cbfa3 NC	409	return flags;
	410	}
	411