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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
fd67aa11 2 Copyright (C) 1987-2024 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
252b5132 21#include "as.h"
3882b010 22#include "safe-ctype.h"
252b5132
RH		 23#include "obstack.h"
24#include "subsegs.h"
f27a3839 25#include "dwarf2dbg.h"
c04898f8 26#include "dw2gencfi.h"
252b5132
RH		 27
28#include "opcode/m68k.h"
29#include "m68k-parse.h"
0d96863f 30#include "elf/m68k.h"
31302357 31
cf869cce 32static void m68k_elf_cons (int);
85f7484a 33static void m68k_elf_gnu_attribute (int);
cf869cce 34
252b5132
RH		 35/* This string holds the chars that always start a comment. If the
36 pre-processor is disabled, these aren't very useful. The macro
37 tc_comment_chars points to this. We use this, rather than the
38 usual comment_chars, so that the --bitwise-or option will work. */
39#if defined (TE_SVR4) || defined (TE_DELTA)
40const char *m68k_comment_chars = "|#";
41#else
42const char *m68k_comment_chars = "|";
43#endif
44
45/* This array holds the chars that only start a comment at the beginning of
46 a line. If the line seems to have the form '# 123 filename'
47 .line and .file directives will appear in the pre-processed output */
48/* Note that input_file.c hand checks for '#' at the beginning of the
49 first line of the input file. This is because the compiler outputs
92774660
KH		 50 #NO_APP at the beginning of its output. */
51/* Also note that comments like this one will always work. */
252b5132
RH		 52const char line_comment_chars[] = "#*";
53
63a0b638 54const char line_separator_chars[] = ";";
252b5132 55
36759679 56/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 57const char EXP_CHARS[] = "eE";
252b5132
RH		 58
59/* Chars that mean this number is a floating point constant, as
60 in "0f12.456" or "0d1.2345e12". */
61
5a38dc70 62const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 63
64/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
65 changed in read.c . Ideally it shouldn't have to know about it at all,
66 but nothing is ideal around here. */
67
252b5132
RH		 68/* Are we trying to generate PIC code? If so, absolute references
69 ought to be made into linkage table references or pc-relative
92774660 70 references. Not implemented. For ELF there are other means
252b5132
RH		 71 to denote pic relocations. */
72int flag_want_pic;
73
36759679
NC		 74static int flag_short_refs; /* -l option. */
75static int flag_long_jumps; /* -S option. */
28e7409f 76static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 77
78#ifdef REGISTER_PREFIX_OPTIONAL
79int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
80#else
81int flag_reg_prefix_optional;
82#endif
83
84/* Whether --register-prefix-optional was used on the command line. */
85static int reg_prefix_optional_seen;
86
87/* The floating point coprocessor to use by default. */
88static enum m68k_register m68k_float_copnum = COP1;
89
90/* If this is non-zero, then references to number(%pc) will be taken
91 to refer to number, rather than to %pc + number. */
92static int m68k_abspcadd;
93
94/* If this is non-zero, then the quick forms of the move, add, and sub
95 instructions are used when possible. */
96static int m68k_quick = 1;
97
98/* If this is non-zero, then if the size is not specified for a base
99 or outer displacement, the assembler assumes that the size should
100 be 32 bits. */
101static int m68k_rel32 = 1;
102
103/* This is non-zero if m68k_rel32 was set from the command line. */
104static int m68k_rel32_from_cmdline;
105
106/* The default width to use for an index register when using a base
107 displacement. */
108static enum m68k_size m68k_index_width_default = SIZE_LONG;
109
252b5132
RH		 110/* The current label. */
111
c641fe0d 112static struct m68k_tc_sy *current_label;
252b5132 113
60fed2d3
NC		 114/* Pointer to list holding the opcodes sorted by name. */
115static struct m68k_opcode const ** m68k_sorted_opcodes;
116
33eaf5de 117/* It's an arbitrary name: This means I don't approve of it.
36759679 118 See flames below. */
252b5132
RH		 119static struct obstack robyn;
120
252b5132
RH		 121struct m68k_incant
122 {
123 const char *m_operands;
124 unsigned long m_opcode;
125 short m_opnum;
126 short m_codenum;
127 int m_arch;
128 struct m68k_incant *m_next;
129 };
130
131#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
132#define gettwo(x) (((x)->m_opcode)&0xffff)
133
2da12c60
NS		 134static const enum m68k_register m68000_ctrl[] = { 0 };
135static const enum m68k_register m68010_ctrl[] = {
252b5132
RH		 136 SFC, DFC, USP, VBR,
137 0
138};
2da12c60 139static const enum m68k_register m68020_ctrl[] = {
252b5132
RH		 140 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
141 0
142};
2da12c60 143static const enum m68k_register m68040_ctrl[] = {
252b5132
RH		 144 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
145 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
146 0
147};
2da12c60 148static const enum m68k_register m68060_ctrl[] = {
252b5132
RH		 149 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
150 USP, VBR, URP, SRP, PCR,
151 0
152};
2da12c60 153static const enum m68k_register mcf_ctrl[] = {
3e602632 154 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
78336706
NS		 155 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
156 0
157};
87298967
NS		 158static const enum m68k_register mcf51_ctrl[] = {
159 VBR, CPUCR,
f75192f2
KH		 160 0
161};
78336706 162static const enum m68k_register mcf5206_ctrl[] = {
0d999f33 163 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
252b5132
RH		 164 0
165};
2da12c60 166static const enum m68k_register mcf5208_ctrl[] = {
78336706 167 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
266abb8f
NS		 168 0
169};
96e0bbcc 170static const enum m68k_register mcf5210a_ctrl[] = {
78336706 171 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
96e0bbcc
NS		 172 0
173};
2da12c60 174static const enum m68k_register mcf5213_ctrl[] = {
78336706 175 VBR, RAMBAR, RAMBAR1, FLASHBAR,
266abb8f
NS		 176 0
177};
2da12c60 178static const enum m68k_register mcf5216_ctrl[] = {
78336706 179 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
266abb8f
NS		 180 0
181};
46203761
MK		 182static const enum m68k_register mcf5221x_ctrl[] = {
183 VBR, FLASHBAR, RAMBAR, RAMBAR1,
184 0
185};
d5be9593 186static const enum m68k_register mcf52223_ctrl[] = {
0d999f33 187 VBR, FLASHBAR, RAMBAR, RAMBAR1,
d5be9593
NS		 188 0
189};
96e0bbcc 190static const enum m68k_register mcf52235_ctrl[] = {
b345c8c2 191 VBR, FLASHBAR, RAMBAR, RAMBAR1,
96e0bbcc
NS		 192 0
193};
194static const enum m68k_register mcf5225_ctrl[] = {
78336706 195 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
96e0bbcc
NS		 196 0
197};
87298967
NS		 198static const enum m68k_register mcf52259_ctrl[] = {
199 VBR, FLASHBAR, RAMBAR, RAMBAR1,
200 0
201};
202static const enum m68k_register mcf52277_ctrl[] = {
203 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
204 0
205};
2da12c60 206static const enum m68k_register mcf5235_ctrl[] = {
78336706 207 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
e80e0390
NC		 208 0
209};
2da12c60 210static const enum m68k_register mcf5249_ctrl[] = {
78336706 211 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
3e602632
NC		 212 0
213};
2da12c60
NS		 214static const enum m68k_register mcf5250_ctrl[] = {
215 VBR,
216 0
217};
d5be9593 218static const enum m68k_register mcf5253_ctrl[] = {
def8fc92 219 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
d5be9593
NS		 220 0
221};
2da12c60 222static const enum m68k_register mcf5271_ctrl[] = {
78336706 223 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 224 0
225};
226static const enum m68k_register mcf5272_ctrl[] = {
78336706 227 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
2da12c60
NS		 228 0
229};
230static const enum m68k_register mcf5275_ctrl[] = {
78336706 231 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 232 0
233};
234static const enum m68k_register mcf5282_ctrl[] = {
78336706
NS		 235 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
236 0
237};
87298967 238static const enum m68k_register mcf53017_ctrl[] = {
b345c8c2 239 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
87298967
NS		 240 0
241};
78336706 242static const enum m68k_register mcf5307_ctrl[] = {
87298967 243 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR,
2da12c60
NS		 244 0
245};
246static const enum m68k_register mcf5329_ctrl[] = {
78336706 247 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 248 0
249};
250static const enum m68k_register mcf5373_ctrl[] = {
78336706 251 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 252 0
253};
254static const enum m68k_register mcfv4e_ctrl[] = {
a8e24a56
NS		 255 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
256 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
257 MBAR, SECMBAR,
258 MPCR /* Multiprocessor Control register */,
259 EDRAMBAR /* Embedded DRAM Base Address Register */,
260 /* Permutation control registers. */
3e602632
NC		 261 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
262 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
a8e24a56
NS		 263 /* Legacy names */
264 TC /* ASID */, BUSCR /* MMUBAR */,
265 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
266 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
78336706 267 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 268 0
269};
def8fc92
KH		 270static const enum m68k_register mcf5407_ctrl[] = {
271 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
272 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
273 /* Legacy names */
274 TC /* ASID */,
275 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
276 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
277 0
278};
0d999f33
MK		 279static const enum m68k_register mcf54418_ctrl[] = {
280 CACR, ASID, ACR0, ACR1, ACR2, ACR3, ACR4, ACR5, ACR6, ACR7, MMUBAR, RGPIOBAR,
281 VBR, PC, RAMBAR1,
282 /* Legacy names */
283 TC /* ASID */, BUSCR /* MMUBAR */,
284 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
285 RAMBAR /* RAMBAR1 */,
286 0
287};
9a2e615a
NS		 288static const enum m68k_register mcf54455_ctrl[] = {
289 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
0d999f33 290 VBR, PC, RAMBAR1,
9a2e615a
NS		 291 /* Legacy names */
292 TC /* ASID */, BUSCR /* MMUBAR */,
293 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
0d999f33 294 RAMBAR /* RAMBAR1 */,
9a2e615a
NS		 295 0
296};
a8e24a56
NS		 297static const enum m68k_register mcf5475_ctrl[] = {
298 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
299 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
300 /* Legacy names */
301 TC /* ASID */, BUSCR /* MMUBAR */,
302 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 303 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 304 0
305};
306static const enum m68k_register mcf5485_ctrl[] = {
307 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
308 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
309 /* Legacy names */
310 TC /* ASID */, BUSCR /* MMUBAR */,
311 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 312 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
3e602632
NC		 313 0
314};
f7ec513b 315static const enum m68k_register fido_ctrl[] = {
d0fa1372 316 SFC, DFC, USP, VBR, CAC, MBO,
f7ec513b
KH		 317 0
318};
2da12c60 319#define cpu32_ctrl m68010_ctrl
252b5132
RH		 320
321static const enum m68k_register *control_regs;
322
36759679 323/* Internal form of a 68020 instruction. */
252b5132
RH		 324struct m68k_it
325{
326 const char *error;
36759679 327 const char *args; /* List of opcode info. */
252b5132
RH		 328 int numargs;
329
36759679 330 int numo; /* Number of shorts in opcode. */
252b5132
RH		 331 short opcode[11];
332
333 struct m68k_op operands[6];
334
36759679 335 int nexp; /* Number of exprs in use. */
252b5132
RH		 336 struct m68k_exp exprs[4];
337
36759679 338 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 339 struct
340 {
36759679 341 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 342 symbolS *fadd;
343 offsetT foff;
344 int fragty;
345 }
346 fragb[4];
347
33eaf5de 348 int nrel; /* Num of reloc structs in use. */
252b5132
RH		 349 struct
350 {
351 int n;
352 expressionS exp;
353 char wid;
354 char pcrel;
355 /* In a pc relative address the difference between the address
356 of the offset and the address that the offset is relative
357 to. This depends on the addressing mode. Basically this
358 is the value to put in the offset field to address the
359 first byte of the offset, without regarding the special
360 significance of some values (in the branch instruction, for
361 example). */
362 int pcrel_fix;
252b5132
RH		 363 /* Whether this expression needs special pic relocation, and if
364 so, which. */
365 enum pic_relocation pic_reloc;
252b5132 366 }
36759679 367 reloc[5]; /* Five is enough??? */
252b5132
RH		 368};
369
9840d27e 370#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
252b5132
RH		 371#define float_of_arch(x) ((x) & mfloat)
372#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 373#define arch_coldfire_p(x) ((x) & mcfisa_a)
374#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 375
36759679 376/* Macros for determining if cpu supports a specific addressing mode. */
9a2e615a
NS		 377#define HAVE_LONG_DISP(x) \
378 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
379#define HAVE_LONG_CALL(x) \
380 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
381#define HAVE_LONG_COND(x) \
382 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
383#define HAVE_LONG_BRANCH(x) \
384 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
cac27205 385#define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
252b5132 386
36759679 387static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 388
389#define op(ex) ((ex)->exp.X_op)
390#define adds(ex) ((ex)->exp.X_add_symbol)
391#define subs(ex) ((ex)->exp.X_op_symbol)
392#define offs(ex) ((ex)->exp.X_add_number)
393
36759679 394/* Macros for adding things to the m68k_it struct. */
31302357 395#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 396
36759679
NC		 397/* Like addword, but goes BEFORE general operands. */
398
252b5132 399static void
31302357 400insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 401{
402 int z;
07726851 403 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 404 the_ins.opcode[z] = the_ins.opcode[z - 1];
405 for (z = 0; z < the_ins.nrel; z++)
406 the_ins.reloc[z].n += 2;
252b5132
RH		 407 for (z = 0; z < the_ins.nfrag; z++)
408 the_ins.fragb[z].fragoff++;
8a104df9 409 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 410 the_ins.numo++;
411}
412
413/* The numo+1 kludge is so we can hit the low order byte of the prev word.
414 Blecch. */
415static void
31302357 416add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 417{
31302357
AS		 418 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
419 ? the_ins.numo * 2 - 1
420 : (width == 'b'
421 ? the_ins.numo * 2 + 1
422 : the_ins.numo * 2));
252b5132
RH		 423 the_ins.reloc[the_ins.nrel].exp = exp->exp;
424 the_ins.reloc[the_ins.nrel].wid = width;
425 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
252b5132 426 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
252b5132
RH		 427 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
428}
429
430/* Cause an extra frag to be generated here, inserting up to 10 bytes
431 (that value is chosen in the frag_var call in md_assemble). TYPE
432 is the subtype of the frag to be generated; its primary type is
433 rs_machine_dependent.
434
435 The TYPE parameter is also used by md_convert_frag_1 and
436 md_estimate_size_before_relax. The appropriate type of fixup will
437 be emitted by md_convert_frag_1.
438
439 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
440static void
31302357 441add_frag (symbolS *add, offsetT off, int type)
252b5132 442{
8a104df9
KH		 443 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
444 the_ins.fragb[the_ins.nfrag].fadd = add;
445 the_ins.fragb[the_ins.nfrag].foff = off;
446 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 447}
448
449#define isvar(ex) \
450 (op (ex) != O_constant && op (ex) != O_big)
451
31302357
AS		 452static char *crack_operand (char *str, struct m68k_op *opP);
453static int get_num (struct m68k_exp *exp, int ok);
454static int reverse_16_bits (int in);
455static int reverse_8_bits (int in);
456static void install_gen_operand (int mode, int val);
457static void install_operand (int mode, int val);
31302357
AS		 458static void s_data1 (int);
459static void s_data2 (int);
460static void s_even (int);
461static void s_proc (int);
462static void s_chip (int);
463static void s_fopt (int);
464static void s_opt (int);
465static void s_reg (int);
466static void s_restore (int);
467static void s_save (int);
468static void s_mri_if (int);
469static void s_mri_else (int);
470static void s_mri_endi (int);
471static void s_mri_break (int);
472static void s_mri_next (int);
473static void s_mri_for (int);
474static void s_mri_endf (int);
475static void s_mri_repeat (int);
476static void s_mri_until (int);
477static void s_mri_while (int);
478static void s_mri_endw (int);
266abb8f
NS		 479static void s_m68k_cpu (int);
480static void s_m68k_arch (int);
481
482struct m68k_cpu
483{
484 unsigned long arch; /* Architecture features. */
2da12c60 485 const enum m68k_register *control_regs; /* Control regs on chip */
266abb8f 486 const char *name; /* Name */
2b0f3761 487 int alias; /* Alias for a canonical name. If 1, then
0b2e31dc
NS		 488 succeeds canonical name, if -1 then
489 succeeds canonical name, if <-1 ||>1 this is a
490 deprecated name, and the next/previous name
491 should be used. */
266abb8f 492};
252b5132 493
266abb8f
NS		 494/* We hold flags for features explicitly enabled and explicitly
495 disabled. */
252b5132 496static int current_architecture;
266abb8f 497static int not_current_architecture;
266abb8f
NS		 498static const struct m68k_cpu *selected_arch;
499static const struct m68k_cpu *selected_cpu;
500static int initialized;
252b5132 501
266abb8f
NS		 502/* Architecture models. */
503static const struct m68k_cpu m68k_archs[] =
504{
2da12c60
NS		 505 {m68000, m68000_ctrl, "68000", 0},
506 {m68010, m68010_ctrl, "68010", 0},
507 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
508 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
509 {m68040, m68040_ctrl, "68040", 0},
510 {m68060, m68060_ctrl, "68060", 0},
511 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
3bdcfdf4 512 {fido_a, fido_ctrl, "fidoa", 0},
2da12c60
NS		 513 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
514 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
515 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
9a2e615a 516 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
2da12c60
NS		 517 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
518 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
266abb8f
NS		 519 {0,0,NULL, 0}
520};
252b5132 521
87298967
NS		 522/* For -mno-mac we want to turn off all types of mac. */
523static const unsigned no_mac = mcfmac | mcfemac;
524
0b2e31dc
NS		 525/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
526 for either. */
266abb8f
NS		 527static const struct m68k_cpu m68k_extensions[] =
528{
2da12c60
NS		 529 {m68851, NULL, "68851", -1},
530 {m68881, NULL, "68881", -1},
531 {m68881, NULL, "68882", -1},
cf869cce 532
2da12c60 533 {cfloat|m68881, NULL, "float", 0},
cf869cce 534
2da12c60
NS		 535 {mcfhwdiv, NULL, "div", 1},
536 {mcfusp, NULL, "usp", 1},
87298967 537 {mcfmac, (void *)&no_mac, "mac", 1},
2da12c60 538 {mcfemac, NULL, "emac", 1},
cf869cce 539
2da12c60 540 {0,NULL,NULL, 0}
266abb8f
NS		 541};
542
543/* Processor list */
544static const struct m68k_cpu m68k_cpus[] =
545{
2da12c60
NS		 546 {m68000, m68000_ctrl, "68000", 0},
547 {m68000, m68000_ctrl, "68ec000", 1},
548 {m68000, m68000_ctrl, "68hc000", 1},
549 {m68000, m68000_ctrl, "68hc001", 1},
550 {m68000, m68000_ctrl, "68008", 1},
551 {m68000, m68000_ctrl, "68302", 1},
552 {m68000, m68000_ctrl, "68306", 1},
553 {m68000, m68000_ctrl, "68307", 1},
554 {m68000, m68000_ctrl, "68322", 1},
555 {m68000, m68000_ctrl, "68356", 1},
556 {m68010, m68010_ctrl, "68010", 0},
557 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
558 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
559 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
560 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
561 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
562 {m68040, m68040_ctrl, "68040", 0},
563 {m68040, m68040_ctrl, "68ec040", 1},
564 {m68060, m68060_ctrl, "68060", 0},
565 {m68060, m68060_ctrl, "68ec060", 1},
cf869cce 566
2da12c60
NS		 567 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
568 {cpu32|m68881, cpu32_ctrl, "68330", 1},
569 {cpu32|m68881, cpu32_ctrl, "68331", 1},
570 {cpu32|m68881, cpu32_ctrl, "68332", 1},
571 {cpu32|m68881, cpu32_ctrl, "68333", 1},
572 {cpu32|m68881, cpu32_ctrl, "68334", 1},
573 {cpu32|m68881, cpu32_ctrl, "68336", 1},
574 {cpu32|m68881, cpu32_ctrl, "68340", 1},
575 {cpu32|m68881, cpu32_ctrl, "68341", 1},
576 {cpu32|m68881, cpu32_ctrl, "68349", 1},
577 {cpu32|m68881, cpu32_ctrl, "68360", 1},
f75192f2 578
87298967
NS		 579 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0},
580 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1},
c1c30076 581 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ag", 1},
87298967
NS		 582 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1},
583 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1},
c1c30076
NS		 584 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51je", 1},
585 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jf", 1},
586 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jg", 1},
87298967 587 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1},
c1c30076 588 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51mm", 1},
87298967 589 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1},
c1c30076 590 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51qm", 1},
cf869cce 591
2da12c60
NS		 592 {mcfisa_a, mcf_ctrl, "5200", 0},
593 {mcfisa_a, mcf_ctrl, "5202", 1},
594 {mcfisa_a, mcf_ctrl, "5204", 1},
78336706 595 {mcfisa_a, mcf5206_ctrl, "5206", 1},
cf869cce 596
78336706 597 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
cf869cce 598
2da12c60
NS		 599 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
600 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
cf869cce 601
96e0bbcc
NS		 602 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
603 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
cf869cce 604
2da12c60
NS		 605 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
606 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
607 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
cf869cce 608
2da12c60
NS		 609 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
610 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
611 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
612
46203761
MK		 613 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5221x_ctrl, "5221x", 0},
614
d5be9593
NS		 615 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
616 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
617
96e0bbcc
NS		 618 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
619 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
620 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
cf869cce 622
96e0bbcc
NS		 623 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
624 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
cf869cce 625
87298967
NS		 626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0},
3739860c 628
2da12c60
NS		 629 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
630 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
633 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
3739860c 634
2da12c60
NS		 635 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
636 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
d5be9593 637 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
87298967
NS		 638
639 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1},
640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1},
641 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1},
642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1},
643 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1},
644 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0},
3739860c 645
2da12c60
NS		 646 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
647 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
3739860c 648
2da12c60 649 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
3739860c 650
2da12c60
NS		 651 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
652 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
3739860c 653
2da12c60
NS		 654 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
655 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
656 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
657 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
3739860c 658
87298967
NS		 659 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1},
660 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1},
661 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1},
662 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1},
663 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1},
664 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1},
665 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0},
3739860c 666
78336706 667 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
3739860c 668
2da12c60
NS		 669 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
670 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
671 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
672 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
3739860c 673
2da12c60
NS		 674 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
675 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
676 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
3739860c 677
def8fc92 678 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
9a2e615a 679
0d999f33
MK		 680 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54410", -1},
681 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54415", -1},
682 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54416", -1},
683 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54417", -1},
684 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54418", 0},
685
9a2e615a
NS		 686 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
687 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
688 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
689 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
690 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
691 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
3739860c 692
a8e24a56
NS		 693 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
694 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
695 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
696 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
697 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
698 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
699 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
3739860c 700
a8e24a56
NS		 701 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
702 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
703 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
704 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
705 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
706 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
707 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
3739860c 708
b3768379 709 {fido_a, fido_ctrl, "fidoa", 0},
3bdcfdf4 710 {fido_a, fido_ctrl, "fido", 1},
9840d27e 711
2da12c60 712 {0,NULL,NULL, 0}
dc84e067 713 };
252b5132 714
266abb8f
NS		 715static const struct m68k_cpu *m68k_lookup_cpu
716(const char *, const struct m68k_cpu *, int, int *);
717static int m68k_set_arch (const char *, int, int);
718static int m68k_set_cpu (const char *, int, int);
719static int m68k_set_extension (const char *, int, int);
720static void m68k_init_arch (void);
252b5132 721
151337e8
NC		 722/* This is the assembler relaxation table for m68k. m68k is a rich CISC
723 architecture and we have a lot of relaxation modes. */
252b5132 724
151337e8
NC		 725/* Macros used in the relaxation code. */
726#define TAB(x,y) (((x) << 2) + (y))
727#define TABTYPE(x) ((x) >> 2)
728
729/* Relaxation states. */
730#define BYTE 0
731#define SHORT 1
732#define LONG 2
733#define SZ_UNDEF 3
734
735/* Here are all the relaxation modes we support. First we can relax ordinary
736 branches. On 68020 and higher and on CPU32 all branch instructions take
737 three forms, so on these CPUs all branches always remain as such. When we
738 have to expand to the LONG form on a 68000, though, we substitute an
739 absolute jump instead. This is a direct replacement for unconditional
740 branches and a branch over a jump for conditional branches. However, if the
741 user requires PIC and disables this with --pcrel, we can only relax between
742 BYTE and SHORT forms, punting if that isn't enough. This gives us four
743 different relaxation modes for branches: */
744
36759679
NC		 745#define BRANCHBWL 0 /* Branch byte, word, or long. */
746#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
747#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
748#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 749
750/* We also relax coprocessor branches and DBcc's. All CPUs that support
751 coprocessor branches support them in word and long forms, so we have only
752 one relaxation mode for them. DBcc's are word only on all CPUs. We can
753 relax them to the LONG form with a branch-around sequence. This sequence
754 can use a long branch (if available) or an absolute jump (if acceptable).
755 This gives us two relaxation modes. If long branches are not available and
756 absolute jumps are not acceptable, we don't relax DBcc's. */
757
36759679
NC		 758#define FBRANCH 4 /* Coprocessor branch. */
759#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
760#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 761
762/* That's all for instruction relaxation. However, we also relax PC-relative
763 operands. Specifically, we have three operand relaxation modes. On the
764 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
765 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
766 two. Also PC+displacement+index operands in their simple form (with a non-
767 suppressed index without memory indirection) are supported on all CPUs, but
768 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
769 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
770 form of the PC+displacement+index operand. Finally, some absolute operands
771 can be relaxed down to 16-bit PC-relative. */
772
36759679
NC		 773#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
774#define PCINDEX 8 /* PC + displacement + index. */
775#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132 776
cac27205
NC		 777/* This relaxation is required for branches where there is no long
778 branch and we are in pcrel mode. We generate a bne/beq pair. */
779#define BRANCHBWPL 10 /* Branch byte, word or pair of longs
780 */
781
252b5132 782/* Note that calls to frag_var need to specify the maximum expansion
cac27205
NC		 783 needed; this is currently 12 bytes for bne/beq pair. */
784#define FRAG_VAR_SIZE 12
252b5132
RH		 785
786/* The fields are:
787 How far Forward this mode will reach:
788 How far Backward this mode will reach:
789 How many bytes this mode will add to the size of the frag
790 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 791
792 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 793relax_typeS md_relax_table[] =
794{
ac62c346
AM		 795 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
796 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
797 { 0, 0, 4, 0 },
798 { 1, 1, 0, 0 },
799
800 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
801 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
802 { 0, 0, 4, 0 },
803 { 1, 1, 0, 0 },
804
805 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
806 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
807 { 0, 0, 6, 0 },
808 { 1, 1, 0, 0 },
809
810 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
811 { 0, 0, 2, 0 },
812 { 1, 1, 0, 0 },
813 { 1, 1, 0, 0 },
814
36759679 815 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 816 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
817 { 0, 0, 4, 0 },
818 { 1, 1, 0, 0 },
819
36759679 820 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 821 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
822 { 0, 0, 10, 0 },
823 { 1, 1, 0, 0 },
824
36759679 825 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 826 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
827 { 0, 0, 10, 0 },
828 { 1, 1, 0, 0 },
829
36759679 830 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 831 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
832 { 0, 0, 6, 0 },
833 { 1, 1, 0, 0 },
834
835 { 125, -130, 0, TAB (PCINDEX, SHORT) },
836 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
837 { 0, 0, 4, 0 },
838 { 1, 1, 0, 0 },
839
36759679 840 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 841 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
842 { 0, 0, 4, 0 },
843 { 1, 1, 0, 0 },
3739860c 844
cac27205
NC		 845 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
846 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
847 { 0, 0, 10, 0 },
848 { 1, 1, 0, 0 },
252b5132
RH		 849};
850
851/* These are the machine dependent pseudo-ops. These are included so
852 the assembler can work on the output from the SUN C compiler, which
36759679 853 generates these. */
252b5132
RH		 854
855/* This table describes all the machine specific pseudo-ops the assembler
856 has to support. The fields are:
857 pseudo-op name without dot
858 function to call to execute this pseudo-op
36759679 859 Integer arg to pass to the function. */
252b5132
RH		 860const pseudo_typeS md_pseudo_table[] =
861{
862 {"data1", s_data1, 0},
863 {"data2", s_data2, 0},
252b5132
RH		 864 {"even", s_even, 0},
865 {"skip", s_space, 0},
866 {"proc", s_proc, 0},
252b5132 867 {"align", s_align_bytes, 0},
252b5132 868 {"swbeg", s_ignore, 0},
cf869cce 869 {"long", m68k_elf_cons, 4},
252b5132
RH		 870 {"extend", float_cons, 'x'},
871 {"ldouble", float_cons, 'x'},
872
266abb8f
NS		 873 {"arch", s_m68k_arch, 0},
874 {"cpu", s_m68k_cpu, 0},
85f7484a 875 {"gnu_attribute", m68k_elf_gnu_attribute, 0},
266abb8f 876
252b5132
RH		 877 /* The following pseudo-ops are supported for MRI compatibility. */
878 {"chip", s_chip, 0},
879 {"comline", s_space, 1},
880 {"fopt", s_fopt, 0},
881 {"mask2", s_ignore, 0},
882 {"opt", s_opt, 0},
883 {"reg", s_reg, 0},
884 {"restore", s_restore, 0},
885 {"save", s_save, 0},
886
887 {"if", s_mri_if, 0},
888 {"if.b", s_mri_if, 'b'},
889 {"if.w", s_mri_if, 'w'},
890 {"if.l", s_mri_if, 'l'},
891 {"else", s_mri_else, 0},
892 {"else.s", s_mri_else, 's'},
893 {"else.l", s_mri_else, 'l'},
894 {"endi", s_mri_endi, 0},
895 {"break", s_mri_break, 0},
896 {"break.s", s_mri_break, 's'},
897 {"break.l", s_mri_break, 'l'},
898 {"next", s_mri_next, 0},
899 {"next.s", s_mri_next, 's'},
900 {"next.l", s_mri_next, 'l'},
901 {"for", s_mri_for, 0},
902 {"for.b", s_mri_for, 'b'},
903 {"for.w", s_mri_for, 'w'},
904 {"for.l", s_mri_for, 'l'},
905 {"endf", s_mri_endf, 0},
906 {"repeat", s_mri_repeat, 0},
907 {"until", s_mri_until, 0},
908 {"until.b", s_mri_until, 'b'},
909 {"until.w", s_mri_until, 'w'},
910 {"until.l", s_mri_until, 'l'},
911 {"while", s_mri_while, 0},
912 {"while.b", s_mri_while, 'b'},
913 {"while.w", s_mri_while, 'w'},
914 {"while.l", s_mri_while, 'l'},
915 {"endw", s_mri_endw, 0},
916
917 {0, 0, 0}
918};
919
252b5132 920/* The mote pseudo ops are put into the opcode table, since they
31302357 921 don't start with a . they look like opcodes to gas. */
252b5132 922
5a38dc70 923const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 924{
925
926 {"dcl", cons, 4},
927 {"dc", cons, 2},
928 {"dcw", cons, 2},
929 {"dcb", cons, 1},
930
931 {"dsl", s_space, 4},
932 {"ds", s_space, 2},
933 {"dsw", s_space, 2},
934 {"dsb", s_space, 1},
935
936 {"xdef", s_globl, 0},
252b5132 937 {"align", s_align_bytes, 0},
252b5132
RH		 938 {0, 0, 0}
939};
940
bd17c2c3
AM		 941/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
942 gives identical results to a 32-bit host. */
943#define TRUNC(X) ((valueT) (X) & 0xffffffff)
944#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
945
946#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
947#define isubyte(x) ((valueT) TRUNC (x) < 0x100)
948#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
949#define isuword(x) ((valueT) TRUNC (x) < 0x10000)
950
951#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
952#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
252b5132
RH		 953#define islong(x) (1)
954
252b5132
RH		 955static char notend_table[256];
956static char alt_notend_table[256];
957#define notend(s) \
958 (! (notend_table[(unsigned char) *s] \
959 || (*s == ':' \
960 && alt_notend_table[(unsigned char) s[1]])))
961
252b5132 962
c801568a
AM		 963/* Return zero if the reference to SYMBOL from within the same segment may
964 be relaxed. */
965
966/* On an ELF system, we can't relax an externally visible symbol,
967 because it may be overridden by a shared library. However, if
968 TARGET_OS is "elf", then we presume that we are assembling for an
969 embedded system, in which case we don't have to worry about shared
970 libraries, and we can relax any external sym. */
971
972#define relaxable_symbol(symbol) \
6358301e 973 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 974 || S_IS_WEAK (symbol)))
975
252b5132
RH		 976/* Compute the relocation code for a fixup of SIZE bytes, using pc
977 relative relocation if PCREL is non-zero. PIC says whether a special
978 pic relocation was requested. */
979
252b5132 980static bfd_reloc_code_real_type
31302357 981get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 982{
983 switch (pic)
984 {
985 case pic_got_pcrel:
986 switch (size)
987 {
988 case 1:
989 return BFD_RELOC_8_GOT_PCREL;
990 case 2:
991 return BFD_RELOC_16_GOT_PCREL;
992 case 4:
993 return BFD_RELOC_32_GOT_PCREL;
994 }
995 break;
996
997 case pic_got_off:
998 switch (size)
999 {
1000 case 1:
1001 return BFD_RELOC_8_GOTOFF;
1002 case 2:
1003 return BFD_RELOC_16_GOTOFF;
1004 case 4:
1005 return BFD_RELOC_32_GOTOFF;
1006 }
1007 break;
1008
1009 case pic_plt_pcrel:
1010 switch (size)
1011 {
1012 case 1:
1013 return BFD_RELOC_8_PLT_PCREL;
1014 case 2:
1015 return BFD_RELOC_16_PLT_PCREL;
1016 case 4:
1017 return BFD_RELOC_32_PLT_PCREL;
1018 }
1019 break;
1020
1021 case pic_plt_off:
1022 switch (size)
1023 {
1024 case 1:
1025 return BFD_RELOC_8_PLTOFF;
1026 case 2:
1027 return BFD_RELOC_16_PLTOFF;
1028 case 4:
1029 return BFD_RELOC_32_PLTOFF;
1030 }
1031 break;
1032
cf869cce
NC		 1033 case pic_tls_gd:
1034 switch (size)
1035 {
1036 case 1:
1037 return BFD_RELOC_68K_TLS_GD8;
1038 case 2:
1039 return BFD_RELOC_68K_TLS_GD16;
1040 case 4:
1041 return BFD_RELOC_68K_TLS_GD32;
1042 }
1043 break;
1044
1045 case pic_tls_ldm:
1046 switch (size)
1047 {
1048 case 1:
1049 return BFD_RELOC_68K_TLS_LDM8;
1050 case 2:
1051 return BFD_RELOC_68K_TLS_LDM16;
1052 case 4:
1053 return BFD_RELOC_68K_TLS_LDM32;
1054 }
1055 break;
1056
1057 case pic_tls_ldo:
1058 switch (size)
1059 {
1060 case 1:
1061 return BFD_RELOC_68K_TLS_LDO8;
1062 case 2:
1063 return BFD_RELOC_68K_TLS_LDO16;
1064 case 4:
1065 return BFD_RELOC_68K_TLS_LDO32;
1066 }
1067 break;
1068
1069 case pic_tls_ie:
1070 switch (size)
1071 {
1072 case 1:
1073 return BFD_RELOC_68K_TLS_IE8;
1074 case 2:
1075 return BFD_RELOC_68K_TLS_IE16;
1076 case 4:
1077 return BFD_RELOC_68K_TLS_IE32;
1078 }
1079 break;
1080
1081 case pic_tls_le:
1082 switch (size)
1083 {
1084 case 1:
1085 return BFD_RELOC_68K_TLS_LE8;
1086 case 2:
1087 return BFD_RELOC_68K_TLS_LE16;
1088 case 4:
1089 return BFD_RELOC_68K_TLS_LE32;
1090 }
1091 break;
1092
252b5132
RH		 1093 case pic_none:
1094 if (pcrel)
1095 {
1096 switch (size)
1097 {
1098 case 1:
1099 return BFD_RELOC_8_PCREL;
1100 case 2:
1101 return BFD_RELOC_16_PCREL;
1102 case 4:
1103 return BFD_RELOC_32_PCREL;
1104 }
1105 }
1106 else
1107 {
1108 switch (size)
1109 {
1110 case 1:
1111 return BFD_RELOC_8;
1112 case 2:
1113 return BFD_RELOC_16;
1114 case 4:
1115 return BFD_RELOC_32;
1116 }
1117 }
1118 }
1119
1120 if (pcrel)
1121 {
1122 if (pic == pic_none)
1123 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1124 else
1125 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1126 }
1127 else
1128 {
1129 if (pic == pic_none)
1130 as_bad (_("Can not do %d byte relocation"), size);
1131 else
1132 as_bad (_("Can not do %d byte pic relocation"), size);
1133 }
1134
1135 return BFD_RELOC_NONE;
1136}
1137
1138/* Here we decide which fixups can be adjusted to make them relative
1139 to the beginning of the section instead of the symbol. Basically
1140 we need to make sure that the dynamic relocations are done
1141 correctly, so in some cases we force the original symbol to be
1142 used. */
1143int
31302357 1144tc_m68k_fix_adjustable (fixS *fixP)
252b5132 1145{
36759679 1146 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1147 switch (fixP->fx_r_type)
1148 {
1149 case BFD_RELOC_8_GOT_PCREL:
1150 case BFD_RELOC_16_GOT_PCREL:
1151 case BFD_RELOC_32_GOT_PCREL:
1152 case BFD_RELOC_8_GOTOFF:
1153 case BFD_RELOC_16_GOTOFF:
1154 case BFD_RELOC_32_GOTOFF:
1155 case BFD_RELOC_8_PLT_PCREL:
1156 case BFD_RELOC_16_PLT_PCREL:
1157 case BFD_RELOC_32_PLT_PCREL:
1158 case BFD_RELOC_8_PLTOFF:
1159 case BFD_RELOC_16_PLTOFF:
1160 case BFD_RELOC_32_PLTOFF:
cf869cce
NC		 1161 case BFD_RELOC_68K_TLS_GD32:
1162 case BFD_RELOC_68K_TLS_GD16:
1163 case BFD_RELOC_68K_TLS_GD8:
1164 case BFD_RELOC_68K_TLS_LDM32:
1165 case BFD_RELOC_68K_TLS_LDM16:
1166 case BFD_RELOC_68K_TLS_LDM8:
1167 case BFD_RELOC_68K_TLS_LDO32:
1168 case BFD_RELOC_68K_TLS_LDO16:
1169 case BFD_RELOC_68K_TLS_LDO8:
1170 case BFD_RELOC_68K_TLS_IE32:
1171 case BFD_RELOC_68K_TLS_IE16:
1172 case BFD_RELOC_68K_TLS_IE8:
1173 case BFD_RELOC_68K_TLS_LE32:
1174 case BFD_RELOC_68K_TLS_LE16:
1175 case BFD_RELOC_68K_TLS_LE8:
252b5132
RH		 1176 return 0;
1177
1178 case BFD_RELOC_VTABLE_INHERIT:
1179 case BFD_RELOC_VTABLE_ENTRY:
1180 return 0;
1181
1182 default:
1183 return 1;
1184 }
1185}
1186
252b5132 1187arelent *
31302357 1188tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 1189{
1190 arelent *reloc;
1191 bfd_reloc_code_real_type code;
1192
8ec6253e
NC		 1193 /* If the tcbit is set, then this was a fixup of a negative value
1194 that was never resolved. We do not have a reloc to handle this,
1195 so just return. We assume that other code will have detected this
1196 situation and produced a helpful error message, so we just tell the
1197 user that the reloc cannot be produced. */
252b5132 1198 if (fixp->fx_tcbit)
8ec6253e
NC		 1199 {
1200 if (fixp->fx_addsy)
b091f402
AM		 1201 as_bad_where (fixp->fx_file, fixp->fx_line,
1202 _("Unable to produce reloc against symbol '%s'"),
1203 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 1204 return NULL;
1205 }
252b5132
RH		 1206
1207 if (fixp->fx_r_type != BFD_RELOC_NONE)
1208 {
1209 code = fixp->fx_r_type;
1210
1211 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1212 that fixup_segment converted a non-PC relative reloc into a
1213 PC relative reloc. In such a case, we need to convert the
1214 reloc code. */
1215 if (fixp->fx_pcrel)
1216 {
1217 switch (code)
1218 {
1219 case BFD_RELOC_8:
1220 code = BFD_RELOC_8_PCREL;
1221 break;
1222 case BFD_RELOC_16:
1223 code = BFD_RELOC_16_PCREL;
1224 break;
1225 case BFD_RELOC_32:
1226 code = BFD_RELOC_32_PCREL;
1227 break;
1228 case BFD_RELOC_8_PCREL:
1229 case BFD_RELOC_16_PCREL:
1230 case BFD_RELOC_32_PCREL:
1231 case BFD_RELOC_8_GOT_PCREL:
1232 case BFD_RELOC_16_GOT_PCREL:
1233 case BFD_RELOC_32_GOT_PCREL:
1234 case BFD_RELOC_8_GOTOFF:
1235 case BFD_RELOC_16_GOTOFF:
1236 case BFD_RELOC_32_GOTOFF:
1237 case BFD_RELOC_8_PLT_PCREL:
1238 case BFD_RELOC_16_PLT_PCREL:
1239 case BFD_RELOC_32_PLT_PCREL:
1240 case BFD_RELOC_8_PLTOFF:
1241 case BFD_RELOC_16_PLTOFF:
1242 case BFD_RELOC_32_PLTOFF:
cf869cce
NC		 1243 case BFD_RELOC_68K_TLS_GD32:
1244 case BFD_RELOC_68K_TLS_GD16:
1245 case BFD_RELOC_68K_TLS_GD8:
1246 case BFD_RELOC_68K_TLS_LDM32:
1247 case BFD_RELOC_68K_TLS_LDM16:
1248 case BFD_RELOC_68K_TLS_LDM8:
1249 case BFD_RELOC_68K_TLS_LDO32:
1250 case BFD_RELOC_68K_TLS_LDO16:
1251 case BFD_RELOC_68K_TLS_LDO8:
1252 case BFD_RELOC_68K_TLS_IE32:
1253 case BFD_RELOC_68K_TLS_IE16:
1254 case BFD_RELOC_68K_TLS_IE8:
1255 case BFD_RELOC_68K_TLS_LE32:
1256 case BFD_RELOC_68K_TLS_LE16:
1257 case BFD_RELOC_68K_TLS_LE8:
252b5132
RH		 1258 break;
1259 default:
1260 as_bad_where (fixp->fx_file, fixp->fx_line,
1261 _("Cannot make %s relocation PC relative"),
1262 bfd_get_reloc_code_name (code));
1263 }
1264 }
1265 }
1266 else
1267 {
1268#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1269 switch (F (fixp->fx_size, fixp->fx_pcrel))
1270 {
1271#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1272 MAP (1, 0, BFD_RELOC_8);
1273 MAP (2, 0, BFD_RELOC_16);
1274 MAP (4, 0, BFD_RELOC_32);
1275 MAP (1, 1, BFD_RELOC_8_PCREL);
1276 MAP (2, 1, BFD_RELOC_16_PCREL);
1277 MAP (4, 1, BFD_RELOC_32_PCREL);
1278 default:
1279 abort ();
1280 }
1281 }
1282#undef F
1283#undef MAP
1284
add39d23
TS		 1285 reloc = XNEW (arelent);
1286 reloc->sym_ptr_ptr = XNEW (asymbol *);
49309057 1287 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132 1288 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
252b5132
RH		 1289 if (!fixp->fx_pcrel)
1290 reloc->addend = fixp->fx_addnumber;
1291 else
1292 reloc->addend = (section->vma
552c607f 1293 + fixp->fx_pcrel_adjust
252b5132
RH		 1294 + fixp->fx_addnumber
1295 + md_pcrel_from (fixp));
252b5132
RH		 1296
1297 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
9c2799c2 1298 gas_assert (reloc->howto != 0);
252b5132
RH		 1299
1300 return reloc;
1301}
1302
252b5132
RH		 1303/* Handle of the OPCODE hash table. NULL means any use before
1304 m68k_ip_begin() will crash. */
629310ab 1305static htab_t op_hash;
252b5132
RH		 1306\f
1307/* Assemble an m68k instruction. */
1308
1309static void
31302357 1310m68k_ip (char *instring)
252b5132 1311{
ed9e98c2
AM		 1312 char *p;
1313 struct m68k_op *opP;
1314 const struct m68k_incant *opcode;
1315 const char *s;
1316 int tmpreg = 0, baseo = 0, outro = 0, nextword;
252b5132
RH		 1317 char *pdot, *pdotmove;
1318 enum m68k_size siz1, siz2;
1319 char c;
1320 int losing;
1321 int opsfound;
03b13e59 1322 struct m68k_op operands_backup[6];
252b5132
RH		 1323 LITTLENUM_TYPE words[6];
1324 LITTLENUM_TYPE *wordp;
1325 unsigned long ok_arch = 0;
1326
1327 if (*instring == ' ')
36759679 1328 instring++; /* Skip leading whitespace. */
252b5132
RH		 1329
1330 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1331 or exactly 1 space. */
252b5132
RH		 1332 pdot = 0;
1333 for (p = instring; *p != '\0'; p++)
1334 {
1335 if (*p == ' ')
1336 break;
1337 if (*p == '.')
1338 pdot = p;
1339 }
1340
1341 if (p == instring)
1342 {
1343 the_ins.error = _("No operator");
1344 return;
1345 }
1346
1347 /* p now points to the end of the opcode name, probably whitespace.
1348 Make sure the name is null terminated by clobbering the
1349 whitespace, look it up in the hash table, then fix it back.
1350 Remove a dot, first, since the opcode tables have none. */
1351 if (pdot != NULL)
1352 {
1353 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1354 *pdotmove = pdotmove[1];
1355 p--;
1356 }
1357
1358 c = *p;
1359 *p = '\0';
629310ab 1360 opcode = (const struct m68k_incant *) str_hash_find (op_hash, instring);
252b5132
RH		 1361 *p = c;
1362
1363 if (pdot != NULL)
1364 {
1365 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1366 *pdotmove = pdotmove[-1];
1367 *pdot = '.';
1368 ++p;
1369 }
1370
1371 if (opcode == NULL)
1372 {
1373 the_ins.error = _("Unknown operator");
1374 return;
1375 }
1376
36759679 1377 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1378 while (*p == ' ')
1379 ++p;
1380
1381 if (opcode->m_operands == 0)
1382 {
1383 char *old = input_line_pointer;
1384 *old = '\n';
1385 input_line_pointer = p;
2b0f3761 1386 /* Ahh - it's a motorola style pseudo op. */
252b5132
RH		 1387 mote_pseudo_table[opcode->m_opnum].poc_handler
1388 (mote_pseudo_table[opcode->m_opnum].poc_val);
1389 input_line_pointer = old;
1390 *old = 0;
1391
1392 return;
1393 }
1394
1395 if (flag_mri && opcode->m_opnum == 0)
1396 {
1397 /* In MRI mode, random garbage is allowed after an instruction
1398 which accepts no operands. */
1399 the_ins.args = opcode->m_operands;
1400 the_ins.numargs = opcode->m_opnum;
1401 the_ins.numo = opcode->m_codenum;
1402 the_ins.opcode[0] = getone (opcode);
1403 the_ins.opcode[1] = gettwo (opcode);
1404 return;
1405 }
1406
1407 for (opP = &the_ins.operands[0]; *p; opP++)
1408 {
1409 p = crack_operand (p, opP);
1410
1411 if (opP->error)
1412 {
1413 the_ins.error = opP->error;
1414 return;
1415 }
1416 }
1417
1418 opsfound = opP - &the_ins.operands[0];
1419
1420 /* This ugly hack is to support the floating pt opcodes in their
33eaf5de 1421 standard form. Essentially, we fake a first entry of type COP#1 */
252b5132
RH		 1422 if (opcode->m_operands[0] == 'I')
1423 {
1424 int n;
1425
1426 for (n = opsfound; n > 0; --n)
1427 the_ins.operands[n] = the_ins.operands[n - 1];
1428
31302357 1429 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1430 the_ins.operands[0].mode = CONTROL;
1431 the_ins.operands[0].reg = m68k_float_copnum;
1432 opsfound++;
1433 }
1434
36759679 1435 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1436 for (losing = 0;;)
1437 {
1438 /* If we didn't get the right number of ops, or we have no
92774660 1439 common model with this pattern then reject this pattern. */
252b5132
RH		 1440
1441 ok_arch |= opcode->m_arch;
1442 if (opsfound != opcode->m_opnum
1443 || ((opcode->m_arch & current_architecture) == 0))
1444 ++losing;
1445 else
1446 {
03b13e59
NC		 1447 int i;
1448
1449 /* Make a copy of the operands of this insn so that
1450 we can modify them safely, should we want to. */
9c2799c2 1451 gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
03b13e59
NC		 1452 for (i = 0; i < opsfound; i++)
1453 operands_backup[i] = the_ins.operands[i];
1454
1455 for (s = opcode->m_operands, opP = &operands_backup[0];
252b5132
RH		 1456 *s && !losing;
1457 s += 2, opP++)
1458 {
1459 /* Warning: this switch is huge! */
1460 /* I've tried to organize the cases into this order:
1461 non-alpha first, then alpha by letter. Lower-case
1462 goes directly before uppercase counterpart. */
1463 /* Code with multiple case ...: gets sorted by the lowest
1464 case ... it belongs to. I hope this makes sense. */
1465 switch (*s)
1466 {
1467 case '!':
1468 switch (opP->mode)
1469 {
1470 case IMMED:
1471 case DREG:
1472 case AREG:
1473 case FPREG:
1474 case CONTROL:
1475 case AINC:
1476 case ADEC:
1477 case REGLST:
1478 losing++;
1479 break;
1480 default:
1481 break;
1482 }
1483 break;
1484
1485 case '<':
1486 switch (opP->mode)
1487 {
1488 case DREG:
1489 case AREG:
1490 case FPREG:
1491 case CONTROL:
1492 case IMMED:
1493 case ADEC:
1494 case REGLST:
1495 losing++;
1496 break;
1497 default:
1498 break;
1499 }
1500 break;
1501
1502 case '>':
1503 switch (opP->mode)
1504 {
1505 case DREG:
1506 case AREG:
1507 case FPREG:
1508 case CONTROL:
1509 case IMMED:
1510 case AINC:
1511 case REGLST:
1512 losing++;
1513 break;
1514 case ABSL:
1515 break;
1516 default:
1517 if (opP->reg == PC
1518 || opP->reg == ZPC)
1519 losing++;
1520 break;
1521 }
1522 break;
1523
1524 case 'm':
1525 switch (opP->mode)
1526 {
1527 case DREG:
1528 case AREG:
1529 case AINDR:
1530 case AINC:
1531 case ADEC:
1532 break;
1533 default:
1534 losing++;
1535 }
8a104df9 1536 break;
252b5132
RH		 1537
1538 case 'n':
1539 switch (opP->mode)
1540 {
1541 case DISP:
1542 break;
1543 default:
1544 losing++;
1545 }
8a104df9 1546 break;
252b5132
RH		 1547
1548 case 'o':
1549 switch (opP->mode)
1550 {
1551 case BASE:
1552 case ABSL:
1553 case IMMED:
1554 break;
1555 default:
1556 losing++;
1557 }
8a104df9 1558 break;
252b5132
RH		 1559
1560 case 'p':
1561 switch (opP->mode)
1562 {
1563 case DREG:
1564 case AREG:
1565 case AINDR:
1566 case AINC:
1567 case ADEC:
1568 break;
1569 case DISP:
1570 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1571 losing++;
252b5132
RH		 1572 break;
1573 default:
1574 losing++;
1575 }
8a104df9 1576 break;
252b5132
RH		 1577
1578 case 'q':
1579 switch (opP->mode)
1580 {
1581 case DREG:
1582 case AINDR:
1583 case AINC:
1584 case ADEC:
1585 break;
1586 case DISP:
1587 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1588 losing++;
252b5132
RH		 1589 break;
1590 default:
1591 losing++;
1592 break;
1593 }
8a104df9 1594 break;
252b5132
RH		 1595
1596 case 'v':
1597 switch (opP->mode)
1598 {
1599 case DREG:
1600 case AINDR:
1601 case AINC:
1602 case ADEC:
1603 case ABSL:
1604 break;
1605 case DISP:
1606 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1607 losing++;
252b5132
RH		 1608 break;
1609 default:
1610 losing++;
1611 break;
1612 }
1613 break;
1614
1615 case '#':
1616 if (opP->mode != IMMED)
1617 losing++;
1618 else if (s[1] == 'b'
1619 && ! isvar (&opP->disp)
1620 && (opP->disp.exp.X_op != O_constant
1621 || ! isbyte (opP->disp.exp.X_add_number)))
1622 losing++;
1623 else if (s[1] == 'B'
1624 && ! isvar (&opP->disp)
1625 && (opP->disp.exp.X_op != O_constant
1626 || ! issbyte (opP->disp.exp.X_add_number)))
1627 losing++;
1628 else if (s[1] == 'w'
1629 && ! isvar (&opP->disp)
1630 && (opP->disp.exp.X_op != O_constant
1631 || ! isword (opP->disp.exp.X_add_number)))
1632 losing++;
1633 else if (s[1] == 'W'
1634 && ! isvar (&opP->disp)
1635 && (opP->disp.exp.X_op != O_constant
1636 || ! issword (opP->disp.exp.X_add_number)))
1637 losing++;
1638 break;
1639
1640 case '^':
1641 case 'T':
1642 if (opP->mode != IMMED)
1643 losing++;
1644 break;
1645
1646 case '$':
1647 if (opP->mode == AREG
1648 || opP->mode == CONTROL
1649 || opP->mode == FPREG
1650 || opP->mode == IMMED
1651 || opP->mode == REGLST
1652 || (opP->mode != ABSL
1653 && (opP->reg == PC
1654 || opP->reg == ZPC)))
1655 losing++;
1656 break;
1657
1658 case '%':
1659 if (opP->mode == CONTROL
1660 || opP->mode == FPREG
1661 || opP->mode == REGLST
1662 || opP->mode == IMMED
1663 || (opP->mode != ABSL
1664 && (opP->reg == PC
1665 || opP->reg == ZPC)))
1666 losing++;
1667 break;
1668
1669 case '&':
1670 switch (opP->mode)
1671 {
1672 case DREG:
1673 case AREG:
1674 case FPREG:
1675 case CONTROL:
1676 case IMMED:
1677 case AINC:
1678 case ADEC:
1679 case REGLST:
1680 losing++;
1681 break;
1682 case ABSL:
1683 break;
1684 default:
1685 if (opP->reg == PC
1686 || opP->reg == ZPC)
1687 losing++;
1688 break;
1689 }
1690 break;
1691
1692 case '*':
1693 if (opP->mode == CONTROL
1694 || opP->mode == FPREG
1695 || opP->mode == REGLST)
1696 losing++;
1697 break;
1698
1699 case '+':
1700 if (opP->mode != AINC)
1701 losing++;
1702 break;
1703
1704 case '-':
1705 if (opP->mode != ADEC)
1706 losing++;
1707 break;
1708
1709 case '/':
1710 switch (opP->mode)
1711 {
1712 case AREG:
1713 case CONTROL:
1714 case FPREG:
1715 case AINC:
1716 case ADEC:
1717 case IMMED:
1718 case REGLST:
1719 losing++;
1720 break;
1721 default:
1722 break;
1723 }
1724 break;
1725
1726 case ';':
1727 switch (opP->mode)
1728 {
1729 case AREG:
1730 case CONTROL:
1731 case FPREG:
1732 case REGLST:
1733 losing++;
1734 break;
1735 default:
1736 break;
1737 }
1738 break;
1739
1740 case '?':
1741 switch (opP->mode)
1742 {
1743 case AREG:
1744 case CONTROL:
1745 case FPREG:
1746 case AINC:
1747 case ADEC:
1748 case IMMED:
1749 case REGLST:
1750 losing++;
1751 break;
1752 case ABSL:
1753 break;
1754 default:
1755 if (opP->reg == PC || opP->reg == ZPC)
1756 losing++;
1757 break;
1758 }
1759 break;
1760
1761 case '@':
1762 switch (opP->mode)
1763 {
1764 case AREG:
1765 case CONTROL:
1766 case FPREG:
1767 case IMMED:
1768 case REGLST:
1769 losing++;
1770 break;
1771 default:
1772 break;
1773 }
1774 break;
1775
1776 case '~': /* For now! (JF FOO is this right?) */
1777 switch (opP->mode)
1778 {
1779 case DREG:
1780 case AREG:
1781 case CONTROL:
1782 case FPREG:
1783 case IMMED:
1784 case REGLST:
1785 losing++;
1786 break;
1787 case ABSL:
1788 break;
1789 default:
1790 if (opP->reg == PC
1791 || opP->reg == ZPC)
1792 losing++;
1793 break;
1794 }
1795 break;
1796
1797 case '3':
1798 if (opP->mode != CONTROL
1799 || (opP->reg != TT0 && opP->reg != TT1))
1800 losing++;
1801 break;
1802
1803 case 'A':
1804 if (opP->mode != AREG)
1805 losing++;
1806 break;
1807
1808 case 'a':
1809 if (opP->mode != AINDR)
1810 ++losing;
1811 break;
1812
fd99574b
NC		 1813 case '4':
1814 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1815 && (opP->mode != DISP
1816 || opP->reg < ADDR0
1817 || opP->reg > ADDR7))
1818 ++losing;
1819 break;
1820
252b5132
RH		 1821 case 'B': /* FOO */
1822 if (opP->mode != ABSL
1823 || (flag_long_jumps
d34049e8 1824 && startswith (instring, "jbsr")))
252b5132
RH		 1825 losing++;
1826 break;
1827
3e602632
NC		 1828 case 'b':
1829 switch (opP->mode)
1830 {
1831 case IMMED:
1832 case ABSL:
1833 case AREG:
1834 case FPREG:
1835 case CONTROL:
1836 case POST:
1837 case PRE:
1838 case REGLST:
1839 losing++;
1840 break;
1841 default:
1842 break;
1843 }
1844 break;
1845
252b5132
RH		 1846 case 'C':
1847 if (opP->mode != CONTROL || opP->reg != CCR)
1848 losing++;
1849 break;
1850
1851 case 'd':
1852 if (opP->mode != DISP
1853 || opP->reg < ADDR0
1854 || opP->reg > ADDR7)
1855 losing++;
1856 break;
1857
1858 case 'D':
1859 if (opP->mode != DREG)
1860 losing++;
1861 break;
1862
6da466c7
ILT		 1863 case 'E':
1864 if (opP->reg != ACC)
1865 losing++;
1866 break;
1867
fd99574b
NC		 1868 case 'e':
1869 if (opP->reg != ACC && opP->reg != ACC1
1870 && opP->reg != ACC2 && opP->reg != ACC3)
1871 losing++;
1872 break;
1873
252b5132
RH		 1874 case 'F':
1875 if (opP->mode != FPREG)
1876 losing++;
1877 break;
1878
6da466c7
ILT		 1879 case 'G':
1880 if (opP->reg != MACSR)
1881 losing++;
1882 break;
1883
fd99574b
NC		 1884 case 'g':
1885 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1886 losing++;
1887 break;
1888
6da466c7
ILT		 1889 case 'H':
1890 if (opP->reg != MASK)
1891 losing++;
1892 break;
1893
252b5132
RH		 1894 case 'I':
1895 if (opP->mode != CONTROL
1896 || opP->reg < COP0
1897 || opP->reg > COP7)
1898 losing++;
1899 break;
1900
fd99574b
NC		 1901 case 'i':
1902 if (opP->mode != LSH && opP->mode != RSH)
1903 losing++;
1904 break;
1905
252b5132
RH		 1906 case 'J':
1907 if (opP->mode != CONTROL
1908 || opP->reg < USP
0b2e31dc
NS		 1909 || opP->reg > last_movec_reg
1910 || !control_regs)
252b5132
RH		 1911 losing++;
1912 else
1913 {
1914 const enum m68k_register *rp;
3739860c 1915
252b5132 1916 for (rp = control_regs; *rp; rp++)
78336706
NS		 1917 {
1918 if (*rp == opP->reg)
1919 break;
1920 /* In most CPUs RAMBAR refers to control reg
1921 c05 (RAMBAR1), but a few CPUs have it
1922 refer to c04 (RAMBAR0). */
1923 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1924 {
1925 opP->reg = RAMBAR_ALT;
1926 break;
1927 }
1928 }
252b5132
RH		 1929 if (*rp == 0)
1930 losing++;
1931 }
1932 break;
1933
1934 case 'k':
1935 if (opP->mode != IMMED)
1936 losing++;
1937 break;
1938
1939 case 'l':
1940 case 'L':
1941 if (opP->mode == DREG
1942 || opP->mode == AREG
1943 || opP->mode == FPREG)
1944 {
1945 if (s[1] == '8')
1946 losing++;
1947 else
1948 {
1949 switch (opP->mode)
1950 {
1951 case DREG:
1952 opP->mask = 1 << (opP->reg - DATA0);
1953 break;
1954 case AREG:
1955 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1956 break;
1957 case FPREG:
1958 opP->mask = 1 << (opP->reg - FP0 + 16);
1959 break;
1960 default:
1961 abort ();
1962 }
1963 opP->mode = REGLST;
1964 }
1965 }
1966 else if (opP->mode == CONTROL)
1967 {
1968 if (s[1] != '8')
1969 losing++;
1970 else
1971 {
1972 switch (opP->reg)
1973 {
1974 case FPI:
1975 opP->mask = 1 << 24;
1976 break;
1977 case FPS:
1978 opP->mask = 1 << 25;
1979 break;
1980 case FPC:
1981 opP->mask = 1 << 26;
1982 break;
1983 default:
1984 losing++;
1985 break;
1986 }
1987 opP->mode = REGLST;
1988 }
1989 }
1990 else if (opP->mode != REGLST)
1991 losing++;
1992 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1993 losing++;
1994 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1995 losing++;
1996 break;
1997
1998 case 'M':
1999 if (opP->mode != IMMED)
2000 losing++;
2001 else if (opP->disp.exp.X_op != O_constant
2002 || ! issbyte (opP->disp.exp.X_add_number))
2003 losing++;
2004 else if (! m68k_quick
2005 && instring[3] != 'q'
2006 && instring[4] != 'q')
2007 losing++;
2008 break;
2009
2010 case 'O':
2011 if (opP->mode != DREG
2012 && opP->mode != IMMED
2013 && opP->mode != ABSL)
2014 losing++;
2015 break;
2016
2017 case 'Q':
2018 if (opP->mode != IMMED)
2019 losing++;
2020 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 2021 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
252b5132
RH		 2022 losing++;
2023 else if (! m68k_quick
d34049e8
ML		 2024 && (startswith (instring, "add")
2025 || startswith (instring, "sub"))
252b5132
RH		 2026 && instring[3] != 'q')
2027 losing++;
2028 break;
2029
2030 case 'R':
2031 if (opP->mode != DREG && opP->mode != AREG)
2032 losing++;
2033 break;
2034
2035 case 'r':
2036 if (opP->mode != AINDR
2037 && (opP->mode != BASE
2038 || (opP->reg != 0
2039 && opP->reg != ZADDR0)
2040 || opP->disp.exp.X_op != O_absent
2041 || ((opP->index.reg < DATA0
2042 || opP->index.reg > DATA7)
2043 && (opP->index.reg < ADDR0
2044 || opP->index.reg > ADDR7))
2045 || opP->index.size != SIZE_UNSPEC
2046 || opP->index.scale != 1))
2047 losing++;
2048 break;
2049
2050 case 's':
2051 if (opP->mode != CONTROL
2052 || ! (opP->reg == FPI
2053 || opP->reg == FPS
2054 || opP->reg == FPC))
2055 losing++;
2056 break;
2057
2058 case 'S':
2059 if (opP->mode != CONTROL || opP->reg != SR)
2060 losing++;
2061 break;
2062
2063 case 't':
2064 if (opP->mode != IMMED)
2065 losing++;
2066 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 2067 || TRUNC (opP->disp.exp.X_add_number) > 7)
252b5132
RH		 2068 losing++;
2069 break;
2070
2071 case 'U':
2072 if (opP->mode != CONTROL || opP->reg != USP)
2073 losing++;
2074 break;
2075
3e602632
NC		 2076 case 'x':
2077 if (opP->mode != IMMED)
2078 losing++;
2079 else if (opP->disp.exp.X_op != O_constant
bd17c2c3
AM		 2080 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
2081 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
3e602632
NC		 2082 losing++;
2083 break;
2084
afa2158f
NS		 2085 case 'j':
2086 if (opP->mode != IMMED)
2087 losing++;
2088 else if (opP->disp.exp.X_op != O_constant
2089 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2090 losing++;
2091 break;
2092
2093 case 'K':
2094 if (opP->mode != IMMED)
2095 losing++;
2096 else if (opP->disp.exp.X_op != O_constant
2097 || TRUNC (opP->disp.exp.X_add_number) > 511)
2098 losing++;
2099 break;
2100
252b5132
RH		 2101 /* JF these are out of order. We could put them
2102 in order if we were willing to put up with
2103 bunches of #ifdef m68851s in the code.
2104
2105 Don't forget that you need these operands
2106 to use 68030 MMU instructions. */
2107#ifndef NO_68851
36759679 2108 /* Memory addressing mode used by pflushr. */
252b5132
RH		 2109 case '|':
2110 if (opP->mode == CONTROL
2111 || opP->mode == FPREG
2112 || opP->mode == DREG
2113 || opP->mode == AREG
2114 || opP->mode == REGLST)
2115 losing++;
2116 /* We should accept immediate operands, but they
2117 supposedly have to be quad word, and we don't
2118 handle that. I would like to see what a Motorola
2119 assembler does before doing something here. */
2120 if (opP->mode == IMMED)
2121 losing++;
2122 break;
2123
2124 case 'f':
2125 if (opP->mode != CONTROL
2126 || (opP->reg != SFC && opP->reg != DFC))
2127 losing++;
2128 break;
2129
2130 case '0':
2131 if (opP->mode != CONTROL || opP->reg != TC)
2132 losing++;
2133 break;
2134
2135 case '1':
2136 if (opP->mode != CONTROL || opP->reg != AC)
2137 losing++;
2138 break;
2139
2140 case '2':
2141 if (opP->mode != CONTROL
2142 || (opP->reg != CAL
2143 && opP->reg != VAL
2144 && opP->reg != SCC))
2145 losing++;
2146 break;
2147
2148 case 'V':
2149 if (opP->mode != CONTROL
2150 || opP->reg != VAL)
2151 losing++;
2152 break;
2153
2154 case 'W':
2155 if (opP->mode != CONTROL
2156 || (opP->reg != DRP
2157 && opP->reg != SRP
2158 && opP->reg != CRP))
2159 losing++;
2160 break;
2161
3e602632
NC		 2162 case 'w':
2163 switch (opP->mode)
2164 {
2165 case IMMED:
2166 case ABSL:
2167 case AREG:
2168 case DREG:
2169 case FPREG:
2170 case CONTROL:
2171 case POST:
2172 case PRE:
2173 case REGLST:
2174 losing++;
2175 break;
2176 default:
2177 break;
2178 }
2179 break;
2180
252b5132
RH		 2181 case 'X':
2182 if (opP->mode != CONTROL
2183 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2184 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2185 losing++;
2186 break;
2187
2188 case 'Y':
2189 if (opP->mode != CONTROL || opP->reg != PSR)
2190 losing++;
2191 break;
2192
2193 case 'Z':
2194 if (opP->mode != CONTROL || opP->reg != PCSR)
2195 losing++;
2196 break;
2197#endif
2198 case 'c':
2199 if (opP->mode != CONTROL
2200 || (opP->reg != NC
2201 && opP->reg != IC
2202 && opP->reg != DC
2203 && opP->reg != BC))
36759679 2204 losing++;
252b5132
RH		 2205 break;
2206
2207 case '_':
2208 if (opP->mode != ABSL)
2209 ++losing;
2210 break;
2211
6da466c7
ILT		 2212 case 'u':
2213 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2214 losing++;
2215 /* FIXME: kludge instead of fixing parser:
2216 upper/lower registers are *not* CONTROL
92774660 2217 registers, but ordinary ones. */
6da466c7
ILT		 2218 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2219 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2220 opP->mode = DREG;
2221 else
2222 opP->mode = AREG;
2223 break;
2224
3e602632
NC		 2225 case 'y':
2226 if (!(opP->mode == AINDR
31302357
AS		 2227 || (opP->mode == DISP
2228 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 2229 losing++;
2230 break;
2231
2232 case 'z':
2233 if (!(opP->mode == AINDR || opP->mode == DISP))
2234 losing++;
2235 break;
2236
252b5132
RH		 2237 default:
2238 abort ();
36759679 2239 }
252b5132
RH		 2240
2241 if (losing)
2242 break;
36759679 2243 }
03b13e59
NC		 2244
2245 /* Since we have found the correct instruction, copy
2246 in the modifications that we may have made. */
2247 if (!losing)
2248 for (i = 0; i < opsfound; i++)
2249 the_ins.operands[i] = operands_backup[i];
36759679 2250 }
252b5132
RH		 2251
2252 if (!losing)
36759679 2253 break;
252b5132
RH		 2254
2255 opcode = opcode->m_next;
2256
2257 if (!opcode)
2258 {
2259 if (ok_arch
2260 && !(ok_arch & current_architecture))
2261 {
6d89cc8f
NS		 2262 const struct m68k_cpu *cpu;
2263 int any = 0;
2264 size_t space = 400;
325801bd 2265 char *buf = XNEWVEC (char, space + 1);
6d89cc8f
NS		 2266 size_t len;
2267 int paren = 1;
2268
2269 the_ins.error = buf;
2270 /* Make sure there's a NUL at the end of the buffer -- strncpy
b2f58c0c 2271 won't write one when it runs out of buffer. */
6d89cc8f
NS		 2272 buf[space] = 0;
2273#define APPEND(STRING) \
2274 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2275
2276 APPEND (_("invalid instruction for this architecture; needs "));
252b5132
RH		 2277 switch (ok_arch)
2278 {
6b6e92f4 2279 case mcfisa_a:
b2f58c0c 2280 APPEND ("ColdFire ISA_A");
6b6e92f4
NC		 2281 break;
2282 case mcfhwdiv:
b2f58c0c
NC		 2283 APPEND ("ColdFire ");
2284 APPEND (_("hardware divide"));
6b6e92f4
NC		 2285 break;
2286 case mcfisa_aa:
b2f58c0c 2287 APPEND ("ColdFire ISA_A+");
6b6e92f4
NC		 2288 break;
2289 case mcfisa_b:
b2f58c0c 2290 APPEND ("ColdFire ISA_B");
6b6e92f4 2291 break;
8d100c32 2292 case mcfisa_c:
b2f58c0c 2293 APPEND ("ColdFire ISA_C");
8d100c32 2294 break;
3e602632 2295 case cfloat:
b2f58c0c 2296 APPEND ("ColdFire fpu");
3e602632 2297 break;
252b5132 2298 case mfloat:
b2f58c0c 2299 APPEND ("M68K fpu");
252b5132
RH		 2300 break;
2301 case mmmu:
b2f58c0c 2302 APPEND ("M68K mmu");
252b5132
RH		 2303 break;
2304 case m68020up:
b2f58c0c
NC		 2305 APPEND ("68020 ");
2306 APPEND (_("or higher"));
252b5132
RH		 2307 break;
2308 case m68000up:
b2f58c0c
NC		 2309 APPEND ("68000 ");
2310 APPEND (_("or higher"));
252b5132
RH		 2311 break;
2312 case m68010up:
b2f58c0c
NC		 2313 APPEND ("68010 ");
2314 APPEND (_("or higher"));
252b5132
RH		 2315 break;
2316 default:
6d89cc8f
NS		 2317 paren = 0;
2318 }
2319 if (paren)
2320 APPEND (" (");
6b6e92f4 2321
6d89cc8f
NS		 2322 for (cpu = m68k_cpus; cpu->name; cpu++)
2323 if (!cpu->alias && (cpu->arch & ok_arch))
2324 {
2325 const struct m68k_cpu *alias;
869ddf2a 2326 int seen_master = 0;
3739860c 2327
6d89cc8f
NS		 2328 if (any)
2329 APPEND (", ");
2330 any = 0;
2331 APPEND (cpu->name);
869ddf2a
NS		 2332 for (alias = cpu; alias != m68k_cpus; alias--)
2333 if (alias[-1].alias >= 0)
2334 break;
2335 for (; !seen_master || alias->alias > 0; alias++)
6d89cc8f 2336 {
869ddf2a
NS		 2337 if (!alias->alias)
2338 seen_master = 1;
2339 else
2340 {
2341 if (any)
2342 APPEND (", ");
2343 else
2344 APPEND (" [");
2345 APPEND (alias->name);
2346 any = 1;
2347 }
6d89cc8f 2348 }
869ddf2a
NS		 2349 if (any)
2350 APPEND ("]");
6d89cc8f 2351 any = 1;
252b5132 2352 }
6d89cc8f
NS		 2353 if (paren)
2354 APPEND (")");
2355#undef APPEND
2356 if (!space)
2357 {
b2f58c0c 2358 /* We ran out of space, so replace the end of the list
6d89cc8f
NS		 2359 with ellipsis. */
2360 buf -= 4;
2361 while (*buf != ' ')
2362 buf--;
2363 strcpy (buf, " ...");
252b5132 2364 }
252b5132
RH		 2365 }
2366 else
2367 the_ins.error = _("operands mismatch");
2368 return;
36759679 2369 }
252b5132
RH		 2370
2371 losing = 0;
2372 }
2373
36759679 2374 /* Now assemble it. */
252b5132
RH		 2375 the_ins.args = opcode->m_operands;
2376 the_ins.numargs = opcode->m_opnum;
2377 the_ins.numo = opcode->m_codenum;
2378 the_ins.opcode[0] = getone (opcode);
2379 the_ins.opcode[1] = gettwo (opcode);
2380
2381 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2382 {
9a2e615a 2383 int have_disp = 0;
cac27205 2384 int use_pl = 0;
3739860c 2385
252b5132 2386 /* This switch is a doozy.
33eaf5de 2387 Watch the first step; it's a big one! */
252b5132
RH		 2388 switch (s[0])
2389 {
2390
2391 case '*':
2392 case '~':
2393 case '%':
2394 case ';':
2395 case '@':
2396 case '!':
2397 case '&':
2398 case '$':
2399 case '?':
2400 case '/':
2401 case '<':
2402 case '>':
3e602632 2403 case 'b':
252b5132
RH		 2404 case 'm':
2405 case 'n':
2406 case 'o':
2407 case 'p':
2408 case 'q':
2409 case 'v':
3e602632
NC		 2410 case 'w':
2411 case 'y':
2412 case 'z':
fd99574b 2413 case '4':
252b5132
RH		 2414#ifndef NO_68851
2415 case '|':
2416#endif
2417 switch (opP->mode)
2418 {
2419 case IMMED:
2420 tmpreg = 0x3c; /* 7.4 */
2421 if (strchr ("bwl", s[1]))
3e602632 2422 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2423 else
2424 nextword = get_num (&opP->disp, 0);
2425 if (isvar (&opP->disp))
2426 add_fix (s[1], &opP->disp, 0, 0);
2427 switch (s[1])
2428 {
2429 case 'b':
2430 if (!isbyte (nextword))
2431 opP->error = _("operand out of range");
2432 addword (nextword);
2433 baseo = 0;
2434 break;
2435 case 'w':
2436 if (!isword (nextword))
2437 opP->error = _("operand out of range");
2438 addword (nextword);
2439 baseo = 0;
2440 break;
2441 case 'W':
2442 if (!issword (nextword))
2443 opP->error = _("operand out of range");
2444 addword (nextword);
2445 baseo = 0;
2446 break;
2447 case 'l':
2448 addword (nextword >> 16);
2449 addword (nextword);
2450 baseo = 0;
2451 break;
2452
2453 case 'f':
2454 baseo = 2;
2455 outro = 8;
2456 break;
2457 case 'F':
2458 baseo = 4;
2459 outro = 11;
2460 break;
2461 case 'x':
2462 baseo = 6;
2463 outro = 15;
2464 break;
2465 case 'p':
2466 baseo = 6;
2467 outro = -1;
2468 break;
2469 default:
2470 abort ();
2471 }
2472 if (!baseo)
2473 break;
2474
36759679 2475 /* We gotta put out some float. */
252b5132
RH		 2476 if (op (&opP->disp) != O_big)
2477 {
2478 valueT val;
2479 int gencnt;
2480
2481 /* Can other cases happen here? */
2482 if (op (&opP->disp) != O_constant)
2483 abort ();
2484
2485 val = (valueT) offs (&opP->disp);
2486 gencnt = 0;
2487 do
2488 {
2489 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2490 val >>= LITTLENUM_NUMBER_OF_BITS;
2491 ++gencnt;
2492 }
2493 while (val != 0);
2494 offs (&opP->disp) = gencnt;
2495 }
2496 if (offs (&opP->disp) > 0)
2497 {
2498 if (offs (&opP->disp) > baseo)
2499 {
2500 as_warn (_("Bignum too big for %c format; truncated"),
2501 s[1]);
2502 offs (&opP->disp) = baseo;
2503 }
2504 baseo -= offs (&opP->disp);
2505 while (baseo--)
2506 addword (0);
2507 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2508 offs (&opP->disp)--;
2509 --wordp)
2510 addword (*wordp);
2511 break;
2512 }
2513 gen_to_words (words, baseo, (long) outro);
2514 for (wordp = words; baseo--; wordp++)
2515 addword (*wordp);
2516 break;
2517 case DREG:
2518 tmpreg = opP->reg - DATA; /* 0.dreg */
2519 break;
2520 case AREG:
2521 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2522 break;
2523 case AINDR:
2524 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2525 break;
2526 case ADEC:
2527 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2528 break;
2529 case AINC:
2530 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2531 break;
2532 case DISP:
2533
3e602632 2534 nextword = get_num (&opP->disp, 90);
252b5132 2535
580b9172
NC		 2536 /* Convert mode 5 addressing with a zero offset into
2537 mode 2 addressing to reduce the instruction size by a
2538 word. */
2539 if (! isvar (&opP->disp)
2540 && (nextword == 0)
2541 && (opP->disp.size == SIZE_UNSPEC)
2542 && (opP->reg >= ADDR0)
2543 && (opP->reg <= ADDR7))
2544 {
2545 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2546 break;
2547 }
2548
252b5132
RH		 2549 if (opP->reg == PC
2550 && ! isvar (&opP->disp)
2551 && m68k_abspcadd)
2552 {
2553 opP->disp.exp.X_op = O_symbol;
252b5132
RH		 2554 opP->disp.exp.X_add_symbol =
2555 section_symbol (absolute_section);
252b5132
RH		 2556 }
2557
36759679 2558 /* Force into index mode. Hope this works. */
252b5132
RH		 2559
2560 /* We do the first bit for 32-bit displacements, and the
2561 second bit for 16 bit ones. It is possible that we
2562 should make the default be WORD instead of LONG, but
2563 I think that'd break GCC, so we put up with a little
2564 inefficiency for the sake of working output. */
2565
2566 if (!issword (nextword)
2567 || (isvar (&opP->disp)
2568 && ((opP->disp.size == SIZE_UNSPEC
2569 && flag_short_refs == 0
2570 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2571 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2572 || opP->disp.size == SIZE_LONG)))
2573 {
2574 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2575 || arch_coldfire_p (current_architecture))
252b5132
RH		 2576 opP->error =
2577 _("displacement too large for this architecture; needs 68020 or higher");
2578 if (opP->reg == PC)
2579 tmpreg = 0x3B; /* 7.3 */
2580 else
2581 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2582 if (isvar (&opP->disp))
2583 {
2584 if (opP->reg == PC)
2585 {
2586 if (opP->disp.size == SIZE_LONG
252b5132
RH		 2587 /* If the displacement needs pic
2588 relocation it cannot be relaxed. */
dc12032b 2589 || opP->disp.pic_reloc != pic_none)
252b5132
RH		 2590 {
2591 addword (0x0170);
2592 add_fix ('l', &opP->disp, 1, 2);
2593 }
2594 else
2595 {
2596 add_frag (adds (&opP->disp),
bd17c2c3 2597 SEXT (offs (&opP->disp)),
151337e8 2598 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2599 break;
2600 }
2601 }
2602 else
2603 {
2604 addword (0x0170);
2605 add_fix ('l', &opP->disp, 0, 0);
2606 }
2607 }
2608 else
2609 addword (0x0170);
2610 addword (nextword >> 16);
2611 }
2612 else
2613 {
2614 if (opP->reg == PC)
2615 tmpreg = 0x3A; /* 7.2 */
2616 else
2617 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2618
2619 if (isvar (&opP->disp))
2620 {
2621 if (opP->reg == PC)
2622 {
2623 add_fix ('w', &opP->disp, 1, 0);
2624 }
2625 else
2626 add_fix ('w', &opP->disp, 0, 0);
2627 }
2628 }
2629 addword (nextword);
2630 break;
2631
2632 case POST:
2633 case PRE:
2634 case BASE:
2635 nextword = 0;
3e602632 2636 baseo = get_num (&opP->disp, 90);
252b5132 2637 if (opP->mode == POST || opP->mode == PRE)
3e602632 2638 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2639 /* Figure out the `addressing mode'.
2640 Also turn on the BASE_DISABLE bit, if needed. */
2641 if (opP->reg == PC || opP->reg == ZPC)
2642 {
2643 tmpreg = 0x3b; /* 7.3 */
2644 if (opP->reg == ZPC)
2645 nextword |= 0x80;
2646 }
2647 else if (opP->reg == 0)
2648 {
2649 nextword |= 0x80;
2650 tmpreg = 0x30; /* 6.garbage */
2651 }
2652 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2653 {
2654 nextword |= 0x80;
2655 tmpreg = 0x30 + opP->reg - ZADDR0;
2656 }
2657 else
2658 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2659
2660 siz1 = opP->disp.size;
2661 if (opP->mode == POST || opP->mode == PRE)
2662 siz2 = opP->odisp.size;
2663 else
2664 siz2 = SIZE_UNSPEC;
2665
36759679 2666 /* Index register stuff. */
252b5132
RH		 2667 if (opP->index.reg != 0
2668 && opP->index.reg >= DATA
2669 && opP->index.reg <= ADDR7)
2670 {
2671 nextword |= (opP->index.reg - DATA) << 12;
2672
2673 if (opP->index.size == SIZE_LONG
2674 || (opP->index.size == SIZE_UNSPEC
2675 && m68k_index_width_default == SIZE_LONG))
2676 nextword |= 0x800;
2677
92774660 2678 if ((opP->index.scale != 1
252b5132 2679 && cpu_of_arch (current_architecture) < m68020)
92774660 2680 || (opP->index.scale == 8
3e602632 2681 && (arch_coldfire_p (current_architecture)
6b6e92f4 2682 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2683 {
2684 opP->error =
2685 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2686 }
2687
6da466c7
ILT		 2688 if (arch_coldfire_p (current_architecture)
2689 && opP->index.size == SIZE_WORD)
2690 opP->error = _("invalid index size for coldfire");
2691
252b5132
RH		 2692 switch (opP->index.scale)
2693 {
2694 case 1:
2695 break;
2696 case 2:
2697 nextword |= 0x200;
2698 break;
2699 case 4:
2700 nextword |= 0x400;
2701 break;
2702 case 8:
2703 nextword |= 0x600;
2704 break;
2705 default:
2706 abort ();
2707 }
33eaf5de 2708 /* IF it's simple,
252b5132
RH		 2709 GET US OUT OF HERE! */
2710
2711 /* Must be INDEX, with an index register. Address
2712 register cannot be ZERO-PC, and either :b was
2713 forced, or we know it will fit. For a 68000 or
2714 68010, force this mode anyways, because the
2715 larger modes aren't supported. */
2716 if (opP->mode == BASE
2717 && ((opP->reg >= ADDR0
2718 && opP->reg <= ADDR7)
2719 || opP->reg == PC))
2720 {
2721 if (siz1 == SIZE_BYTE
2722 || cpu_of_arch (current_architecture) < m68020
6da466c7 2723 || arch_coldfire_p (current_architecture)
252b5132
RH		 2724 || (siz1 == SIZE_UNSPEC
2725 && ! isvar (&opP->disp)
2726 && issbyte (baseo)))
2727 {
2728 nextword += baseo & 0xff;
2729 addword (nextword);
2730 if (isvar (&opP->disp))
2731 {
2732 /* Do a byte relocation. If it doesn't
2733 fit (possible on m68000) let the
2734 fixup processing complain later. */
2735 if (opP->reg == PC)
2736 add_fix ('B', &opP->disp, 1, 1);
2737 else
2738 add_fix ('B', &opP->disp, 0, 0);
2739 }
2740 else if (siz1 != SIZE_BYTE)
2741 {
2742 if (siz1 != SIZE_UNSPEC)
2743 as_warn (_("Forcing byte displacement"));
2744 if (! issbyte (baseo))
2745 opP->error = _("byte displacement out of range");
2746 }
2747
2748 break;
2749 }
2750 else if (siz1 == SIZE_UNSPEC
2751 && opP->reg == PC
2752 && isvar (&opP->disp)
2753 && subs (&opP->disp) == NULL
252b5132
RH		 2754 /* If the displacement needs pic
2755 relocation it cannot be relaxed. */
dc12032b 2756 && opP->disp.pic_reloc == pic_none)
252b5132
RH		 2757 {
2758 /* The code in md_convert_frag_1 needs to be
2759 able to adjust nextword. Call frag_grow
2760 to ensure that we have enough space in
2761 the frag obstack to make all the bytes
2762 contiguous. */
2763 frag_grow (14);
8a104df9
KH		 2764 nextword += baseo & 0xff;
2765 addword (nextword);
bd17c2c3
AM		 2766 add_frag (adds (&opP->disp),
2767 SEXT (offs (&opP->disp)),
8a104df9 2768 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2769
2770 break;
8a104df9 2771 }
252b5132
RH		 2772 }
2773 }
2774 else
2775 {
36759679 2776 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2777 if (opP->index.reg >= ZDATA0
2778 && opP->index.reg <= ZDATA7)
2779 nextword |= (opP->index.reg - ZDATA0) << 12;
2780 else if (opP->index.reg >= ZADDR0
59e28a97 2781 && opP->index.reg <= ZADDR7)
252b5132
RH		 2782 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2783 }
2784
2785 /* It isn't simple. */
2786
2787 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2788 || arch_coldfire_p (current_architecture))
252b5132
RH		 2789 opP->error =
2790 _("invalid operand mode for this architecture; needs 68020 or higher");
2791
2792 nextword |= 0x100;
2793 /* If the guy specified a width, we assume that it is
2794 wide enough. Maybe it isn't. If so, we lose. */
2795 switch (siz1)
2796 {
2797 case SIZE_UNSPEC:
2798 if (isvar (&opP->disp)
2799 ? m68k_rel32
2800 : ! issword (baseo))
2801 {
2802 siz1 = SIZE_LONG;
2803 nextword |= 0x30;
2804 }
2805 else if (! isvar (&opP->disp) && baseo == 0)
2806 nextword |= 0x10;
2807 else
2808 {
2809 nextword |= 0x20;
2810 siz1 = SIZE_WORD;
2811 }
2812 break;
2813 case SIZE_BYTE:
2814 as_warn (_(":b not permitted; defaulting to :w"));
2815 /* Fall through. */
2816 case SIZE_WORD:
2817 nextword |= 0x20;
2818 break;
2819 case SIZE_LONG:
2820 nextword |= 0x30;
2821 break;
2822 }
2823
67c1ffbe 2824 /* Figure out inner displacement stuff. */
252b5132
RH		 2825 if (opP->mode == POST || opP->mode == PRE)
2826 {
2827 if (cpu_of_arch (current_architecture) & cpu32)
2828 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2829 switch (siz2)
2830 {
2831 case SIZE_UNSPEC:
2832 if (isvar (&opP->odisp)
2833 ? m68k_rel32
2834 : ! issword (outro))
2835 {
2836 siz2 = SIZE_LONG;
2837 nextword |= 0x3;
2838 }
2839 else if (! isvar (&opP->odisp) && outro == 0)
2840 nextword |= 0x1;
2841 else
2842 {
2843 nextword |= 0x2;
2844 siz2 = SIZE_WORD;
2845 }
2846 break;
2847 case 1:
2848 as_warn (_(":b not permitted; defaulting to :w"));
2849 /* Fall through. */
2850 case 2:
2851 nextword |= 0x2;
2852 break;
2853 case 3:
2854 nextword |= 0x3;
2855 break;
2856 }
2857 if (opP->mode == POST
2858 && (nextword & 0x40) == 0)
2859 nextword |= 0x04;
2860 }
2861 addword (nextword);
2862
2863 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2864 {
2865 if (opP->reg == PC || opP->reg == ZPC)
2866 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2867 else
2868 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2869 }
2870 if (siz1 == SIZE_LONG)
2871 addword (baseo >> 16);
2872 if (siz1 != SIZE_UNSPEC)
2873 addword (baseo);
2874
2875 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2876 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2877 if (siz2 == SIZE_LONG)
2878 addword (outro >> 16);
2879 if (siz2 != SIZE_UNSPEC)
2880 addword (outro);
2881
2882 break;
2883
2884 case ABSL:
3e602632 2885 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2886 switch (opP->disp.size)
2887 {
2888 default:
2889 abort ();
2890 case SIZE_UNSPEC:
2891 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2892 {
2893 tmpreg = 0x38; /* 7.0 */
2894 addword (nextword);
2895 break;
2896 }
252b5132
RH		 2897 if (isvar (&opP->disp)
2898 && !subs (&opP->disp)
2899 && adds (&opP->disp)
252b5132
RH		 2900 /* If the displacement needs pic relocation it
2901 cannot be relaxed. */
2902 && opP->disp.pic_reloc == pic_none
252b5132
RH		 2903 && !flag_long_jumps
2904 && !strchr ("~%&$?", s[0]))
2905 {
2906 tmpreg = 0x3A; /* 7.2 */
2907 add_frag (adds (&opP->disp),
bd17c2c3 2908 SEXT (offs (&opP->disp)),
151337e8 2909 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2910 break;
2911 }
1a0670f3 2912 /* Fall through. */
252b5132
RH		 2913 case SIZE_LONG:
2914 if (isvar (&opP->disp))
2915 add_fix ('l', &opP->disp, 0, 0);
2916
2917 tmpreg = 0x39;/* 7.1 mode */
2918 addword (nextword >> 16);
2919 addword (nextword);
2920 break;
2921
2922 case SIZE_BYTE:
2923 as_bad (_("unsupported byte value; use a different suffix"));
2924 /* Fall through. */
36759679
NC		 2925
2926 case SIZE_WORD:
252b5132
RH		 2927 if (isvar (&opP->disp))
2928 add_fix ('w', &opP->disp, 0, 0);
2929
2930 tmpreg = 0x38;/* 7.0 mode */
2931 addword (nextword);
2932 break;
2933 }
2934 break;
2935 case CONTROL:
2936 case FPREG:
2937 default:
2938 as_bad (_("unknown/incorrect operand"));
bc805888 2939 /* abort (); */
252b5132 2940 }
fd99574b
NC		 2941
2942 /* If s[0] is '4', then this is for the mac instructions
2943 that can have a trailing_ampersand set. If so, set 0x100
2944 bit on tmpreg so install_gen_operand can check for it and
2945 set the appropriate bit (word2, bit 5). */
2946 if (s[0] == '4')
2947 {
2948 if (opP->trailing_ampersand)
2949 tmpreg |= 0x100;
2950 }
252b5132
RH		 2951 install_gen_operand (s[1], tmpreg);
2952 break;
2953
2954 case '#':
2955 case '^':
2956 switch (s[1])
2957 { /* JF: I hate floating point! */
2958 case 'j':
2959 tmpreg = 70;
2960 break;
2961 case '8':
2962 tmpreg = 20;
2963 break;
2964 case 'C':
2965 tmpreg = 50;
2966 break;
2967 case '3':
2968 default:
3e602632 2969 tmpreg = 90;
252b5132
RH		 2970 break;
2971 }
2972 tmpreg = get_num (&opP->disp, tmpreg);
2973 if (isvar (&opP->disp))
2974 add_fix (s[1], &opP->disp, 0, 0);
2975 switch (s[1])
2976 {
2977 case 'b': /* Danger: These do no check for
2978 certain types of overflow.
2979 user beware! */
2980 if (!isbyte (tmpreg))
2981 opP->error = _("out of range");
2982 insop (tmpreg, opcode);
2983 if (isvar (&opP->disp))
2984 the_ins.reloc[the_ins.nrel - 1].n =
2985 (opcode->m_codenum) * 2 + 1;
2986 break;
2987 case 'B':
2988 if (!issbyte (tmpreg))
2989 opP->error = _("out of range");
2990 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2991 if (isvar (&opP->disp))
2992 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2993 break;
2994 case 'w':
2995 if (!isword (tmpreg))
2996 opP->error = _("out of range");
2997 insop (tmpreg, opcode);
2998 if (isvar (&opP->disp))
2999 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3000 break;
3001 case 'W':
3002 if (!issword (tmpreg))
3003 opP->error = _("out of range");
3004 insop (tmpreg, opcode);
3005 if (isvar (&opP->disp))
3006 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3007 break;
3008 case 'l':
3009 /* Because of the way insop works, we put these two out
3010 backwards. */
3011 insop (tmpreg, opcode);
3012 insop (tmpreg >> 16, opcode);
3013 if (isvar (&opP->disp))
3014 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3015 break;
3016 case '3':
3017 tmpreg &= 0xFF;
1a0670f3 3018 /* Fall through. */
252b5132
RH		 3019 case '8':
3020 case 'C':
3021 case 'j':
3022 install_operand (s[1], tmpreg);
3023 break;
3024 default:
3025 abort ();
3026 }
3027 break;
3028
3029 case '+':
3030 case '-':
3031 case 'A':
3032 case 'a':
3033 install_operand (s[1], opP->reg - ADDR);
3034 break;
3035
3036 case 'B':
3e602632 3037 tmpreg = get_num (&opP->disp, 90);
3739860c 3038
252b5132
RH		 3039 switch (s[1])
3040 {
3041 case 'B':
8390138c 3042 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 3043 break;
3044 case 'W':
3045 add_fix ('w', &opP->disp, 1, 0);
3046 addword (0);
3047 break;
3048 case 'L':
3049 long_branch:
151337e8 3050 the_ins.opcode[0] |= 0xff;
252b5132
RH		 3051 add_fix ('l', &opP->disp, 1, 0);
3052 addword (0);
3053 addword (0);
3054 break;
9a2e615a
NS		 3055 case 'g': /* Conditional branch */
3056 have_disp = HAVE_LONG_CALL (current_architecture);
3057 goto var_branch;
3739860c 3058
9a2e615a
NS		 3059 case 'b': /* Unconditional branch */
3060 have_disp = HAVE_LONG_BRANCH (current_architecture);
cac27205 3061 use_pl = LONG_BRANCH_VIA_COND (current_architecture);
9a2e615a 3062 goto var_branch;
3739860c 3063
9a2e615a
NS		 3064 case 's': /* Unconditional subroutine */
3065 have_disp = HAVE_LONG_CALL (current_architecture);
3739860c 3066
9a2e615a
NS		 3067 var_branch:
3068 if (subs (&opP->disp) /* We can't relax it. */
9a2e615a
NS		 3069 /* If the displacement needs pic relocation it cannot be
3070 relaxed. */
dc12032b 3071 || opP->disp.pic_reloc != pic_none)
9a2e615a
NS		 3072 {
3073 if (!have_disp)
3074 as_warn (_("Can't use long branches on this architecture"));
3075 goto long_branch;
3076 }
3739860c 3077
252b5132 3078 /* This could either be a symbol, or an absolute
151337e8
NC		 3079 address. If it's an absolute address, turn it into
3080 an absolute jump right here and keep it out of the
3081 relaxer. */
3082 if (adds (&opP->disp) == 0)
3083 {
3084 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 3085 the_ins.opcode[0] = 0x4EF9;
151337e8 3086 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 3087 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 3088 else /* jCC */
3089 {
3090 the_ins.opcode[0] ^= 0x0100;
3091 the_ins.opcode[0] |= 0x0006;
18566f55 3092 addword (0x4EF9);
151337e8
NC		 3093 }
3094 add_fix ('l', &opP->disp, 0, 0);
3095 addword (0);
3096 addword (0);
3097 break;
3098 }
3099
3100 /* Now we know it's going into the relaxer. Now figure
3101 out which mode. We try in this order of preference:
3102 long branch, absolute jump, byte/word branches only. */
9a2e615a 3103 if (have_disp)
bd17c2c3
AM		 3104 add_frag (adds (&opP->disp),
3105 SEXT (offs (&opP->disp)),
151337e8
NC		 3106 TAB (BRANCHBWL, SZ_UNDEF));
3107 else if (! flag_keep_pcrel)
3108 {
3109 if ((the_ins.opcode[0] == 0x6000)
3110 || (the_ins.opcode[0] == 0x6100))
bd17c2c3
AM		 3111 add_frag (adds (&opP->disp),
3112 SEXT (offs (&opP->disp)),
151337e8
NC		 3113 TAB (BRABSJUNC, SZ_UNDEF));
3114 else
bd17c2c3
AM		 3115 add_frag (adds (&opP->disp),
3116 SEXT (offs (&opP->disp)),
151337e8
NC		 3117 TAB (BRABSJCOND, SZ_UNDEF));
3118 }
252b5132 3119 else
bd17c2c3
AM		 3120 add_frag (adds (&opP->disp),
3121 SEXT (offs (&opP->disp)),
cac27205
NC		 3122 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3123 : TAB (BRANCHBW, SZ_UNDEF)));
252b5132
RH		 3124 break;
3125 case 'w':
3126 if (isvar (&opP->disp))
3127 {
151337e8
NC		 3128 /* Check for DBcc instructions. We can relax them,
3129 but only if we have long branches and/or absolute
3130 jumps. */
3131 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3132 && (HAVE_LONG_BRANCH (current_architecture)
9a2e615a 3133 || ! flag_keep_pcrel))
252b5132 3134 {
151337e8 3135 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 3136 add_frag (adds (&opP->disp),
3137 SEXT (offs (&opP->disp)),
151337e8
NC		 3138 TAB (DBCCLBR, SZ_UNDEF));
3139 else
bd17c2c3
AM		 3140 add_frag (adds (&opP->disp),
3141 SEXT (offs (&opP->disp)),
151337e8 3142 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 3143 break;
3144 }
252b5132
RH		 3145 add_fix ('w', &opP->disp, 1, 0);
3146 }
3147 addword (0);
3148 break;
36759679 3149 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 3150 add_fix ('l', &opP->disp, 1, 0);
3151 addword (0);
3152 addword (0);
3153 break;
36759679 3154 case 'c': /* Var size Coprocesssor branches. */
151337e8 3155 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 3156 {
252b5132
RH		 3157 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3158 add_fix ('l', &opP->disp, 1, 0);
3159 addword (0);
3160 addword (0);
3161 }
151337e8 3162 else
bd17c2c3
AM		 3163 add_frag (adds (&opP->disp),
3164 SEXT (offs (&opP->disp)),
151337e8 3165 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 3166 break;
3167 default:
3168 abort ();
3169 }
3170 break;
3171
36759679 3172 case 'C': /* Ignore it. */
252b5132
RH		 3173 break;
3174
36759679 3175 case 'd': /* JF this is a kludge. */
252b5132 3176 install_operand ('s', opP->reg - ADDR);
3e602632 3177 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3178 if (!issword (tmpreg))
3179 {
3180 as_warn (_("Expression out of range, using 0"));
3181 tmpreg = 0;
3182 }
3183 addword (tmpreg);
3184 break;
3185
3186 case 'D':
3187 install_operand (s[1], opP->reg - DATA);
3188 break;
3189
fd99574b
NC		 3190 case 'e': /* EMAC ACCx, reg/reg. */
3191 install_operand (s[1], opP->reg - ACC);
3192 break;
3739860c 3193
36759679 3194 case 'E': /* Ignore it. */
6da466c7
ILT		 3195 break;
3196
252b5132
RH		 3197 case 'F':
3198 install_operand (s[1], opP->reg - FP0);
3199 break;
3200
fd99574b
NC		 3201 case 'g': /* EMAC ACCEXTx. */
3202 install_operand (s[1], opP->reg - ACCEXT01);
3203 break;
3204
36759679 3205 case 'G': /* Ignore it. */
6da466c7
ILT		 3206 case 'H':
3207 break;
3208
252b5132
RH		 3209 case 'I':
3210 tmpreg = opP->reg - COP0;
3211 install_operand (s[1], tmpreg);
3212 break;
3213
fd99574b
NC		 3214 case 'i': /* MAC/EMAC scale factor. */
3215 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3216 break;
3217
36759679 3218 case 'J': /* JF foo. */
252b5132
RH		 3219 switch (opP->reg)
3220 {
3221 case SFC:
3222 tmpreg = 0x000;
3223 break;
3224 case DFC:
3225 tmpreg = 0x001;
3226 break;
3227 case CACR:
3228 tmpreg = 0x002;
3229 break;
3230 case TC:
a8e24a56 3231 case ASID:
252b5132
RH		 3232 tmpreg = 0x003;
3233 break;
3e602632 3234 case ACR0:
252b5132
RH		 3235 case ITT0:
3236 tmpreg = 0x004;
3237 break;
3e602632 3238 case ACR1:
252b5132
RH		 3239 case ITT1:
3240 tmpreg = 0x005;
3241 break;
3e602632 3242 case ACR2:
252b5132
RH		 3243 case DTT0:
3244 tmpreg = 0x006;
3245 break;
3e602632 3246 case ACR3:
252b5132
RH		 3247 case DTT1:
3248 tmpreg = 0x007;
3249 break;
3250 case BUSCR:
a8e24a56 3251 case MMUBAR:
252b5132
RH		 3252 tmpreg = 0x008;
3253 break;
0d999f33
MK		 3254 case RGPIOBAR:
3255 tmpreg = 0x009;
3256 break;
3257 case ACR4:
3258 case ACR5:
3259 case ACR6:
3260 case ACR7:
3261 tmpreg = 0x00c + (opP->reg - ACR4);
3262 break;
252b5132
RH		 3263
3264 case USP:
3265 tmpreg = 0x800;
3266 break;
3267 case VBR:
3268 tmpreg = 0x801;
3269 break;
3270 case CAAR:
87298967 3271 case CPUCR:
252b5132
RH		 3272 tmpreg = 0x802;
3273 break;
3274 case MSP:
3275 tmpreg = 0x803;
3276 break;
3277 case ISP:
3278 tmpreg = 0x804;
3279 break;
3280 case MMUSR:
3281 tmpreg = 0x805;
3282 break;
3283 case URP:
3284 tmpreg = 0x806;
3285 break;
3286 case SRP:
3287 tmpreg = 0x807;
3288 break;
3289 case PCR:
3290 tmpreg = 0x808;
3291 break;
3292 case ROMBAR:
a8e24a56 3293 case ROMBAR0:
252b5132
RH		 3294 tmpreg = 0xC00;
3295 break;
3e602632
NC		 3296 case ROMBAR1:
3297 tmpreg = 0xC01;
3298 break;
3299 case FLASHBAR:
252b5132 3300 case RAMBAR0:
78336706 3301 case RAMBAR_ALT:
252b5132
RH		 3302 tmpreg = 0xC04;
3303 break;
3e602632 3304 case RAMBAR:
252b5132
RH		 3305 case RAMBAR1:
3306 tmpreg = 0xC05;
3307 break;
3e602632
NC		 3308 case MPCR:
3309 tmpreg = 0xC0C;
3310 break;
3311 case EDRAMBAR:
3312 tmpreg = 0xC0D;
3313 break;
3314 case MBAR0:
e80e0390 3315 case MBAR2:
3e602632
NC		 3316 case SECMBAR:
3317 tmpreg = 0xC0E;
3318 break;
3319 case MBAR1:
252b5132
RH		 3320 case MBAR:
3321 tmpreg = 0xC0F;
3322 break;
3e602632
NC		 3323 case PCR1U0:
3324 tmpreg = 0xD02;
3325 break;
3326 case PCR1L0:
3327 tmpreg = 0xD03;
3328 break;
3329 case PCR2U0:
3330 tmpreg = 0xD04;
3331 break;
3332 case PCR2L0:
3333 tmpreg = 0xD05;
3334 break;
3335 case PCR3U0:
3336 tmpreg = 0xD06;
3337 break;
3338 case PCR3L0:
3339 tmpreg = 0xD07;
3340 break;
3341 case PCR1L1:
3342 tmpreg = 0xD0A;
3343 break;
3344 case PCR1U1:
3345 tmpreg = 0xD0B;
3346 break;
3347 case PCR2L1:
3348 tmpreg = 0xD0C;
3349 break;
3350 case PCR2U1:
3351 tmpreg = 0xD0D;
3352 break;
3353 case PCR3L1:
3354 tmpreg = 0xD0E;
3355 break;
3356 case PCR3U1:
3357 tmpreg = 0xD0F;
3358 break;
f7ec513b
KH		 3359 case CAC:
3360 tmpreg = 0xFFE;
3361 break;
d0fa1372 3362 case MBO:
f7ec513b
KH		 3363 tmpreg = 0xFFF;
3364 break;
252b5132
RH		 3365 default:
3366 abort ();
3367 }
3368 install_operand (s[1], tmpreg);
3369 break;
3370
3371 case 'k':
3372 tmpreg = get_num (&opP->disp, 55);
3373 install_operand (s[1], tmpreg & 0x7f);
3374 break;
3375
3376 case 'l':
3377 tmpreg = opP->mask;
3378 if (s[1] == 'w')
3379 {
3380 if (tmpreg & 0x7FF0000)
3381 as_bad (_("Floating point register in register list"));
3382 insop (reverse_16_bits (tmpreg), opcode);
3383 }
3384 else
3385 {
3386 if (tmpreg & 0x700FFFF)
3387 as_bad (_("Wrong register in floating-point reglist"));
3388 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3389 }
3390 break;
3391
3392 case 'L':
3393 tmpreg = opP->mask;
3394 if (s[1] == 'w')
3395 {
3396 if (tmpreg & 0x7FF0000)
3397 as_bad (_("Floating point register in register list"));
3398 insop (tmpreg, opcode);
3399 }
3400 else if (s[1] == '8')
3401 {
3402 if (tmpreg & 0x0FFFFFF)
3403 as_bad (_("incorrect register in reglist"));
3404 install_operand (s[1], tmpreg >> 24);
3405 }
3406 else
3407 {
3408 if (tmpreg & 0x700FFFF)
3409 as_bad (_("wrong register in floating-point reglist"));
3410 else
3411 install_operand (s[1], tmpreg >> 16);
3412 }
3413 break;
3414
3415 case 'M':
3416 install_operand (s[1], get_num (&opP->disp, 60));
3417 break;
3418
3419 case 'O':
3420 tmpreg = ((opP->mode == DREG)
8fce3f5e 3421 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3422 : (get_num (&opP->disp, 40) & 0x1F));
3423 install_operand (s[1], tmpreg);
3424 break;
3425
3426 case 'Q':
3427 tmpreg = get_num (&opP->disp, 10);
3428 if (tmpreg == 8)
3429 tmpreg = 0;
3430 install_operand (s[1], tmpreg);
3431 break;
3432
3433 case 'R':
3434 /* This depends on the fact that ADDR registers are eight
3435 more than their corresponding DATA regs, so the result
36759679 3436 will have the ADDR_REG bit set. */
252b5132
RH		 3437 install_operand (s[1], opP->reg - DATA);
3438 break;
3439
3440 case 'r':
3441 if (opP->mode == AINDR)
3442 install_operand (s[1], opP->reg - DATA);
3443 else
3444 install_operand (s[1], opP->index.reg - DATA);
3445 break;
3446
3447 case 's':
3448 if (opP->reg == FPI)
3449 tmpreg = 0x1;
3450 else if (opP->reg == FPS)
3451 tmpreg = 0x2;
3452 else if (opP->reg == FPC)
3453 tmpreg = 0x4;
3454 else
3455 abort ();
3456 install_operand (s[1], tmpreg);
3457 break;
3458
36759679 3459 case 'S': /* Ignore it. */
252b5132
RH		 3460 break;
3461
3462 case 'T':
3463 install_operand (s[1], get_num (&opP->disp, 30));
3464 break;
3465
36759679 3466 case 'U': /* Ignore it. */
252b5132
RH		 3467 break;
3468
3469 case 'c':
3470 switch (opP->reg)
3471 {
3472 case NC:
3473 tmpreg = 0;
3474 break;
3475 case DC:
3476 tmpreg = 1;
3477 break;
3478 case IC:
3479 tmpreg = 2;
3480 break;
3481 case BC:
3482 tmpreg = 3;
3483 break;
3484 default:
3485 as_fatal (_("failed sanity check"));
36759679 3486 } /* switch on cache token. */
252b5132
RH		 3487 install_operand (s[1], tmpreg);
3488 break;
3489#ifndef NO_68851
92774660 3490 /* JF: These are out of order, I fear. */
252b5132
RH		 3491 case 'f':
3492 switch (opP->reg)
3493 {
3494 case SFC:
3495 tmpreg = 0;
3496 break;
3497 case DFC:
3498 tmpreg = 1;
3499 break;
3500 default:
3501 abort ();
3502 }
3503 install_operand (s[1], tmpreg);
3504 break;
3505
3506 case '0':
3507 case '1':
3508 case '2':
3509 switch (opP->reg)
3510 {
3511 case TC:
3512 tmpreg = 0;
3513 break;
3514 case CAL:
3515 tmpreg = 4;
3516 break;
3517 case VAL:
3518 tmpreg = 5;
3519 break;
3520 case SCC:
3521 tmpreg = 6;
3522 break;
3523 case AC:
3524 tmpreg = 7;
3525 break;
3526 default:
3527 abort ();
3528 }
3529 install_operand (s[1], tmpreg);
3530 break;
3531
3532 case 'V':
3533 if (opP->reg == VAL)
3534 break;
3535 abort ();
3536
3537 case 'W':
3538 switch (opP->reg)
3539 {
3540 case DRP:
3541 tmpreg = 1;
3542 break;
3543 case SRP:
3544 tmpreg = 2;
3545 break;
3546 case CRP:
3547 tmpreg = 3;
3548 break;
3549 default:
3550 abort ();
3551 }
3552 install_operand (s[1], tmpreg);
3553 break;
3554
3555 case 'X':
3556 switch (opP->reg)
3557 {
3558 case BAD:
3559 case BAD + 1:
3560 case BAD + 2:
3561 case BAD + 3:
3562 case BAD + 4:
3563 case BAD + 5:
3564 case BAD + 6:
3565 case BAD + 7:
3566 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3567 break;
3568
3569 case BAC:
3570 case BAC + 1:
3571 case BAC + 2:
3572 case BAC + 3:
3573 case BAC + 4:
3574 case BAC + 5:
3575 case BAC + 6:
3576 case BAC + 7:
3577 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3578 break;
3579
3580 default:
3581 abort ();
3582 }
3583 install_operand (s[1], tmpreg);
3584 break;
3585 case 'Y':
3586 know (opP->reg == PSR);
3587 break;
3588 case 'Z':
3589 know (opP->reg == PCSR);
3590 break;
3591#endif /* m68851 */
3592 case '3':
3593 switch (opP->reg)
3594 {
3595 case TT0:
3596 tmpreg = 2;
3597 break;
3598 case TT1:
3599 tmpreg = 3;
3600 break;
3601 default:
3602 abort ();
3603 }
3604 install_operand (s[1], tmpreg);
3605 break;
3606 case 't':
3607 tmpreg = get_num (&opP->disp, 20);
3608 install_operand (s[1], tmpreg);
3609 break;
36759679 3610 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3611 if (isvar (&opP->disp))
3612 add_fix ('l', &opP->disp, 0, 0);
3e602632 3613 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3614 addword (tmpreg >> 16);
3615 addword (tmpreg & 0xFFFF);
3616 break;
6da466c7
ILT		 3617 case 'u':
3618 install_operand (s[1], opP->reg - DATA0L);
3619 opP->reg -= (DATA0L);
36759679 3620 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3621 break;
3e602632
NC		 3622 case 'x':
3623 tmpreg = get_num (&opP->disp, 80);
3624 if (tmpreg == -1)
3625 tmpreg = 0;
3626 install_operand (s[1], tmpreg);
3627 break;
afa2158f
NS		 3628 case 'j':
3629 tmpreg = get_num (&opP->disp, 10);
3630 install_operand (s[1], tmpreg - 1);
3631 break;
3632 case 'K':
3633 tmpreg = get_num (&opP->disp, 65);
3634 install_operand (s[1], tmpreg);
3635 break;
252b5132
RH		 3636 default:
3637 abort ();
3638 }
3639 }
3640
33eaf5de 3641 /* By the time when get here (FINALLY) the_ins contains the complete
92774660 3642 instruction, ready to be emitted. . . */
252b5132
RH		 3643}
3644
3645static int
31302357 3646reverse_16_bits (int in)
252b5132
RH		 3647{
3648 int out = 0;
3649 int n;
3650
3651 static int mask[16] =
3652 {
3653 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3654 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3655 };
3656 for (n = 0; n < 16; n++)
3657 {
3658 if (in & mask[n])
3659 out |= mask[15 - n];
3660 }
3661 return out;
3662} /* reverse_16_bits() */
3663
3664static int
31302357 3665reverse_8_bits (int in)
252b5132
RH		 3666{
3667 int out = 0;
3668 int n;
3669
3670 static int mask[8] =
3671 {
3672 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3673 };
3674
3675 for (n = 0; n < 8; n++)
3676 {
3677 if (in & mask[n])
3678 out |= mask[7 - n];
3679 }
3680 return out;
3681} /* reverse_8_bits() */
3682
cac27205
NC		 3683/* Cause an extra frag to be generated here, inserting up to
3684 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3685 generated; its primary type is rs_machine_dependent.
252b5132
RH		 3686
3687 The TYPE parameter is also used by md_convert_frag_1 and
3688 md_estimate_size_before_relax. The appropriate type of fixup will
3689 be emitted by md_convert_frag_1.
3690
3691 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3692static void
31302357 3693install_operand (int mode, int val)
252b5132
RH		 3694{
3695 switch (mode)
3696 {
3697 case 's':
36759679 3698 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3699 break;
3700 case 'd':
3701 the_ins.opcode[0] |= val << 9;
3702 break;
afa2158f
NS		 3703 case 'E':
3704 the_ins.opcode[1] |= val << 9;
3705 break;
252b5132
RH		 3706 case '1':
3707 the_ins.opcode[1] |= val << 12;
3708 break;
3709 case '2':
3710 the_ins.opcode[1] |= val << 6;
3711 break;
3712 case '3':
3713 the_ins.opcode[1] |= val;
3714 break;
3715 case '4':
3716 the_ins.opcode[2] |= val << 12;
3717 break;
3718 case '5':
3719 the_ins.opcode[2] |= val << 6;
3720 break;
3721 case '6':
3722 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3723 three words long! */
3724 the_ins.numo++;
3725 the_ins.opcode[2] |= val;
3726 break;
3727 case '7':
3728 the_ins.opcode[1] |= val << 7;
3729 break;
3730 case '8':
3731 the_ins.opcode[1] |= val << 10;
3732 break;
3733#ifndef NO_68851
3734 case '9':
3735 the_ins.opcode[1] |= val << 5;
3736 break;
3737#endif
3738
3739 case 't':
3740 the_ins.opcode[1] |= (val << 10) | (val << 7);
3741 break;
3742 case 'D':
3743 the_ins.opcode[1] |= (val << 12) | val;
3744 break;
3745 case 'g':
3746 the_ins.opcode[0] |= val = 0xff;
3747 break;
3748 case 'i':
3749 the_ins.opcode[0] |= val << 9;
3750 break;
3751 case 'C':
3752 the_ins.opcode[1] |= val;
3753 break;
3754 case 'j':
3755 the_ins.opcode[1] |= val;
36759679 3756 the_ins.numo++; /* What a hack. */
252b5132
RH		 3757 break;
3758 case 'k':
3759 the_ins.opcode[1] |= val << 4;
3760 break;
3761 case 'b':
3762 case 'w':
3763 case 'W':
3764 case 'l':
3765 break;
3766 case 'e':
3767 the_ins.opcode[0] |= (val << 6);
3768 break;
3769 case 'L':
3770 the_ins.opcode[1] = (val >> 16);
3771 the_ins.opcode[2] = val & 0xffff;
3772 break;
6da466c7
ILT		 3773 case 'm':
3774 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3775 the_ins.opcode[0] |= ((val & 0x7) << 9);
3776 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3777 break;
fd99574b 3778 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3779 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3780 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3781 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3782 break;
fd99574b 3783 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3784 the_ins.opcode[1] |= val << 12;
3785 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3786 break;
fd99574b 3787 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3788 the_ins.opcode[0] |= (val & 0xF);
3789 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3790 break;
fd99574b 3791 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3792 the_ins.opcode[1] |= (val & 0xF);
3793 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3794 break;
3795 case 'h':
3796 the_ins.opcode[1] |= ((val != 1) << 10);
3797 break;
fd99574b
NC		 3798 case 'F':
3799 the_ins.opcode[0] |= ((val & 0x3) << 9);
3800 break;
3801 case 'f':
3802 the_ins.opcode[0] |= ((val & 0x3) << 0);
3803 break;
be8c092b 3804 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3805 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3806 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3807 break;
be8c092b 3808 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3809 the_ins.opcode[0] |= ((val & 0x1) << 7);
3810 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3811 break;
3812 case 'I':
3813 the_ins.opcode[1] |= ((val & 0x3) << 9);
3814 break;
3815 case ']':
3816 the_ins.opcode[0] |= (val & 0x1) <<10;
3817 break;
252b5132
RH		 3818 case 'c':
3819 default:
3820 as_fatal (_("failed sanity check."));
3821 }
6b6e92f4 3822}
252b5132
RH		 3823
3824static void
31302357 3825install_gen_operand (int mode, int val)
252b5132
RH		 3826{
3827 switch (mode)
3828 {
fd99574b 3829 case '/': /* Special for mask loads for mac/msac insns with
33eaf5de 3830 possible mask; trailing_ampersand set in bit 8. */
fd99574b
NC		 3831 the_ins.opcode[0] |= (val & 0x3f);
3832 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3833 break;
252b5132
RH		 3834 case 's':
3835 the_ins.opcode[0] |= val;
3836 break;
3837 case 'd':
3838 /* This is a kludge!!! */
3839 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3840 break;
3841 case 'b':
3842 case 'w':
3843 case 'l':
3844 case 'f':
3845 case 'F':
3846 case 'x':
3847 case 'p':
3848 the_ins.opcode[0] |= val;
3849 break;
36759679 3850 /* more stuff goes here. */
252b5132
RH		 3851 default:
3852 as_fatal (_("failed sanity check."));
3853 }
6b6e92f4 3854}
252b5132 3855
6b6e92f4
NC		 3856/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3857 then deal with the bitfield hack. */
252b5132
RH		 3858
3859static char *
31302357 3860crack_operand (char *str, struct m68k_op *opP)
252b5132 3861{
ed9e98c2
AM		 3862 int parens;
3863 int c;
3864 char *beg_str;
252b5132
RH		 3865 int inquote = 0;
3866
3867 if (!str)
3868 {
3869 return str;
3870 }
3871 beg_str = str;
3872 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3873 {
3874 if (! inquote)
3875 {
3876 if (*str == '(')
3877 parens++;
3878 else if (*str == ')')
3879 {
3880 if (!parens)
36759679 3881 { /* ERROR. */
252b5132
RH		 3882 opP->error = _("Extra )");
3883 return str;
3884 }
3885 --parens;
3886 }
3887 }
3888 if (flag_mri && *str == '\'')
3889 inquote = ! inquote;
3890 }
3891 if (!*str && parens)
36759679 3892 { /* ERROR. */
252b5132
RH		 3893 opP->error = _("Missing )");
3894 return str;
3895 }
3896 c = *str;
3897 *str = '\0';
3898 if (m68k_ip_op (beg_str, opP) != 0)
3899 {
3900 *str = c;
3901 return str;
3902 }
3903 *str = c;
3904 if (c == '}')
36759679 3905 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3906 if (c)
3907 {
3908 c = *++str;
3909 if (!c)
3910 as_bad (_("Missing operand"));
3911 }
3912
3913 /* Detect MRI REG symbols and convert them to REGLSTs. */
3914 if (opP->mode == CONTROL && (int)opP->reg < 0)
3915 {
3916 opP->mode = REGLST;
3917 opP->mask = ~(int)opP->reg;
3918 opP->reg = 0;
3919 }
3920
3921 return str;
3922}
3923
3924/* This is the guts of the machine-dependent assembler. STR points to a
3925 machine dependent instruction. This function is supposed to emit
3926 the frags/bytes it assembles to.
3927 */
3928
3929static void
31302357 3930insert_reg (const char *regname, int regnum)
252b5132
RH		 3931{
3932 char buf[100];
3933 int i;
3934
3935#ifdef REGISTER_PREFIX
3936 if (!flag_reg_prefix_optional)
3937 {
3938 buf[0] = REGISTER_PREFIX;
3939 strcpy (buf + 1, regname);
3940 regname = buf;
3941 }
3942#endif
3943
e01e1cee
AM		 3944 symbol_table_insert (symbol_new (regname, reg_section,
3945 &zero_address_frag, regnum));
252b5132
RH		 3946
3947 for (i = 0; regname[i]; i++)
3882b010 3948 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3949 buf[i] = '\0';
3950
e01e1cee
AM		 3951 symbol_table_insert (symbol_new (buf, reg_section,
3952 &zero_address_frag, regnum));
252b5132
RH		 3953}
3954
3955struct init_entry
3956 {
3957 const char *name;
3958 int number;
3959 };
3960
3961static const struct init_entry init_table[] =
3962{
3963 { "d0", DATA0 },
3964 { "d1", DATA1 },
3965 { "d2", DATA2 },
3966 { "d3", DATA3 },
3967 { "d4", DATA4 },
3968 { "d5", DATA5 },
3969 { "d6", DATA6 },
3970 { "d7", DATA7 },
3971 { "a0", ADDR0 },
3972 { "a1", ADDR1 },
3973 { "a2", ADDR2 },
3974 { "a3", ADDR3 },
3975 { "a4", ADDR4 },
3976 { "a5", ADDR5 },
3977 { "a6", ADDR6 },
3978 { "fp", ADDR6 },
3979 { "a7", ADDR7 },
3980 { "sp", ADDR7 },
3981 { "ssp", ADDR7 },
3982 { "fp0", FP0 },
3983 { "fp1", FP1 },
3984 { "fp2", FP2 },
3985 { "fp3", FP3 },
3986 { "fp4", FP4 },
3987 { "fp5", FP5 },
3988 { "fp6", FP6 },
3989 { "fp7", FP7 },
3990 { "fpi", FPI },
3991 { "fpiar", FPI },
3992 { "fpc", FPI },
3993 { "fps", FPS },
3994 { "fpsr", FPS },
3995 { "fpc", FPC },
3996 { "fpcr", FPC },
3997 { "control", FPC },
3998 { "status", FPS },
3999 { "iaddr", FPI },
4000
4001 { "cop0", COP0 },
4002 { "cop1", COP1 },
4003 { "cop2", COP2 },
4004 { "cop3", COP3 },
4005 { "cop4", COP4 },
4006 { "cop5", COP5 },
4007 { "cop6", COP6 },
4008 { "cop7", COP7 },
4009 { "pc", PC },
4010 { "zpc", ZPC },
4011 { "sr", SR },
4012
4013 { "ccr", CCR },
4014 { "cc", CCR },
4015
6da466c7 4016 { "acc", ACC },
fd99574b
NC		 4017 { "acc0", ACC },
4018 { "acc1", ACC1 },
4019 { "acc2", ACC2 },
4020 { "acc3", ACC3 },
4021 { "accext01", ACCEXT01 },
4022 { "accext23", ACCEXT23 },
6da466c7
ILT		 4023 { "macsr", MACSR },
4024 { "mask", MASK },
4025
36759679
NC		 4026 /* Control registers. */
4027 { "sfc", SFC }, /* Source Function Code. */
252b5132 4028 { "sfcr", SFC },
36759679 4029 { "dfc", DFC }, /* Destination Function Code. */
252b5132 4030 { "dfcr", DFC },
36759679
NC		 4031 { "cacr", CACR }, /* Cache Control Register. */
4032 { "caar", CAAR }, /* Cache Address Register. */
87298967 4033 { "cpucr", CPUCR }, /* CPU Control Register. */
252b5132 4034
36759679
NC		 4035 { "usp", USP }, /* User Stack Pointer. */
4036 { "vbr", VBR }, /* Vector Base Register. */
4037 { "msp", MSP }, /* Master Stack Pointer. */
4038 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 4039
36759679
NC		 4040 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
4041 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
4042 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
4043 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 4044
4045 /* 68ec040 versions of same */
36759679
NC		 4046 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
4047 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
4048 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
4049 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132 4050
a8e24a56 4051 /* Coldfire versions of same. The ColdFire programmer's reference
252b5132
RH		 4052 manual indicated that the order is 2,3,0,1, but Ken Rose
4053 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 4054 { "acr0", ACR0 }, /* Access Control Unit 0. */
4055 { "acr1", ACR1 }, /* Access Control Unit 1. */
4056 { "acr2", ACR2 }, /* Access Control Unit 2. */
4057 { "acr3", ACR3 }, /* Access Control Unit 3. */
0d999f33
MK		 4058 { "acr4", ACR4 }, /* Access Control Unit 4. */
4059 { "acr5", ACR5 }, /* Access Control Unit 5. */
4060 { "acr6", ACR6 }, /* Access Control Unit 6. */
4061 { "acr7", ACR7 }, /* Access Control Unit 7. */
252b5132 4062
36759679 4063 { "tc", TC }, /* MMU Translation Control Register. */
252b5132 4064 { "tcr", TC },
a8e24a56 4065 { "asid", ASID },
252b5132 4066
36759679
NC		 4067 { "mmusr", MMUSR }, /* MMU Status Register. */
4068 { "srp", SRP }, /* User Root Pointer. */
4069 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 4070
4071 { "buscr", BUSCR },
a8e24a56 4072 { "mmubar", MMUBAR },
252b5132
RH		 4073 { "pcr", PCR },
4074
36759679
NC		 4075 { "rombar", ROMBAR }, /* ROM Base Address Register. */
4076 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
4077 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
4078 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 4079
4080 { "mbar0", MBAR0 }, /* mcfv4e registers. */
4081 { "mbar1", MBAR1 }, /* mcfv4e registers. */
a8e24a56 4082 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3e602632
NC		 4083 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
4084 { "mpcr", MPCR }, /* mcfv4e registers. */
4085 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
4086 { "secmbar", SECMBAR }, /* mcfv4e registers. */
4087 { "asid", TC }, /* mcfv4e registers. */
4088 { "mmubar", BUSCR }, /* mcfv4e registers. */
4089 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
4090 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
4091 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
4092 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
4093 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
4094 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
4095 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
4096 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
4097 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
4098 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
4099 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
4100 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
4101
4102 { "flashbar", FLASHBAR }, /* mcf528x registers. */
4103 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 4104
4105 { "mbar2", MBAR2 }, /* mcf5249 registers. */
f7ec513b 4106
0d999f33
MK		 4107 { "rgpiobar", RGPIOBAR }, /* mcf54418 registers. */
4108
f7ec513b 4109 { "cac", CAC }, /* fido registers. */
d0fa1372
KH		 4110 { "mbb", MBO }, /* fido registers (obsolete). */
4111 { "mbo", MBO }, /* fido registers. */
36759679 4112 /* End of control registers. */
252b5132
RH		 4113
4114 { "ac", AC },
4115 { "bc", BC },
4116 { "cal", CAL },
4117 { "crp", CRP },
4118 { "drp", DRP },
4119 { "pcsr", PCSR },
4120 { "psr", PSR },
4121 { "scc", SCC },
4122 { "val", VAL },
4123 { "bad0", BAD0 },
4124 { "bad1", BAD1 },
4125 { "bad2", BAD2 },
4126 { "bad3", BAD3 },
4127 { "bad4", BAD4 },
4128 { "bad5", BAD5 },
4129 { "bad6", BAD6 },
4130 { "bad7", BAD7 },
4131 { "bac0", BAC0 },
4132 { "bac1", BAC1 },
4133 { "bac2", BAC2 },
4134 { "bac3", BAC3 },
4135 { "bac4", BAC4 },
4136 { "bac5", BAC5 },
4137 { "bac6", BAC6 },
4138 { "bac7", BAC7 },
4139
4140 { "ic", IC },
4141 { "dc", DC },
4142 { "nc", NC },
4143
4144 { "tt0", TT0 },
4145 { "tt1", TT1 },
36759679 4146 /* 68ec030 versions of same. */
252b5132
RH		 4147 { "ac0", TT0 },
4148 { "ac1", TT1 },
36759679 4149 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 4150 { "acusr", PSR },
4151
4152 /* Suppressed data and address registers. */
4153 { "zd0", ZDATA0 },
4154 { "zd1", ZDATA1 },
4155 { "zd2", ZDATA2 },
4156 { "zd3", ZDATA3 },
4157 { "zd4", ZDATA4 },
4158 { "zd5", ZDATA5 },
4159 { "zd6", ZDATA6 },
4160 { "zd7", ZDATA7 },
4161 { "za0", ZADDR0 },
4162 { "za1", ZADDR1 },
4163 { "za2", ZADDR2 },
4164 { "za3", ZADDR3 },
4165 { "za4", ZADDR4 },
4166 { "za5", ZADDR5 },
4167 { "za6", ZADDR6 },
4168 { "za7", ZADDR7 },
4169
92774660 4170 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 4171 { "d0l", DATA0L },
4172 { "d1l", DATA1L },
4173 { "d2l", DATA2L },
4174 { "d3l", DATA3L },
4175 { "d4l", DATA4L },
4176 { "d5l", DATA5L },
4177 { "d6l", DATA6L },
4178 { "d7l", DATA7L },
4179
4180 { "a0l", ADDR0L },
4181 { "a1l", ADDR1L },
4182 { "a2l", ADDR2L },
4183 { "a3l", ADDR3L },
4184 { "a4l", ADDR4L },
4185 { "a5l", ADDR5L },
4186 { "a6l", ADDR6L },
4187 { "a7l", ADDR7L },
4188
4189 { "d0u", DATA0U },
4190 { "d1u", DATA1U },
4191 { "d2u", DATA2U },
4192 { "d3u", DATA3U },
4193 { "d4u", DATA4U },
4194 { "d5u", DATA5U },
4195 { "d6u", DATA6U },
4196 { "d7u", DATA7U },
4197
4198 { "a0u", ADDR0U },
4199 { "a1u", ADDR1U },
4200 { "a2u", ADDR2U },
4201 { "a3u", ADDR3U },
4202 { "a4u", ADDR4U },
4203 { "a5u", ADDR5U },
4204 { "a6u", ADDR6U },
4205 { "a7u", ADDR7U },
4206
252b5132
RH		 4207 { 0, 0 }
4208};
4209
4210static void
31302357 4211init_regtable (void)
252b5132
RH		 4212{
4213 int i;
4214 for (i = 0; init_table[i].name; i++)
4215 insert_reg (init_table[i].name, init_table[i].number);
4216}
4217
252b5132 4218void
31302357 4219md_assemble (char *str)
252b5132
RH		 4220{
4221 const char *er;
4222 short *fromP;
4223 char *toP = NULL;
4224 int m, n = 0;
4225 char *to_beg_P;
4226 int shorts_this_frag;
4227 fixS *fixP;
4228
266abb8f
NS		 4229 if (!selected_cpu && !selected_arch)
4230 {
4231 /* We've not selected an architecture yet. Set the default
4232 now. We do this lazily so that an initial .cpu or .arch directive
4233 can specify. */
4234 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4235 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4236 }
4237 if (!initialized)
4238 m68k_init_arch ();
3739860c 4239
252b5132
RH		 4240 /* In MRI mode, the instruction and operands are separated by a
4241 space. Anything following the operands is a comment. The label
4242 has already been removed. */
4243 if (flag_mri)
4244 {
4245 char *s;
4246 int fields = 0;
4247 int infield = 0;
4248 int inquote = 0;
4249
4250 for (s = str; *s != '\0'; s++)
4251 {
4252 if ((*s == ' ' || *s == '\t') && ! inquote)
4253 {
4254 if (infield)
4255 {
4256 ++fields;
4257 if (fields >= 2)
4258 {
4259 *s = '\0';
4260 break;
4261 }
4262 infield = 0;
4263 }
4264 }
4265 else
4266 {
4267 if (! infield)
4268 infield = 1;
4269 if (*s == '\'')
4270 inquote = ! inquote;
4271 }
4272 }
4273 }
4274
31302357 4275 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 4276 m68k_ip (str);
4277 er = the_ins.error;
4278 if (!er)
4279 {
4280 for (n = 0; n < the_ins.numargs; n++)
4281 if (the_ins.operands[n].error)
4282 {
4283 er = the_ins.operands[n].error;
4284 break;
4285 }
4286 }
4287 if (er)
4288 {
4289 as_bad (_("%s -- statement `%s' ignored"), er, str);
4290 return;
4291 }
4292
4293 /* If there is a current label, record that it marks an instruction. */
4294 if (current_label != NULL)
4295 {
4296 current_label->text = 1;
4297 current_label = NULL;
4298 }
4299
f27a3839
AS		 4300 /* Tie dwarf2 debug info to the address at the start of the insn. */
4301 dwarf2_emit_insn (0);
f27a3839 4302
252b5132
RH		 4303 if (the_ins.nfrag == 0)
4304 {
36759679 4305 /* No frag hacking involved; just put it out. */
252b5132
RH		 4306 toP = frag_more (2 * the_ins.numo);
4307 fromP = &the_ins.opcode[0];
4308 for (m = the_ins.numo; m; --m)
4309 {
4310 md_number_to_chars (toP, (long) (*fromP), 2);
4311 toP += 2;
4312 fromP++;
4313 }
36759679 4314 /* Put out symbol-dependent info. */
252b5132
RH		 4315 for (m = 0; m < the_ins.nrel; m++)
4316 {
4317 switch (the_ins.reloc[m].wid)
4318 {
4319 case 'B':
4320 n = 1;
4321 break;
4322 case 'b':
4323 n = 1;
4324 break;
4325 case '3':
4326 n = 1;
4327 break;
4328 case 'w':
4329 case 'W':
4330 n = 2;
4331 break;
4332 case 'l':
4333 n = 4;
4334 break;
4335 default:
33eaf5de 4336 as_fatal (_("Don't know how to figure out width of %c in md_assemble()"),
252b5132
RH		 4337 the_ins.reloc[m].wid);
4338 }
4339
4340 fixP = fix_new_exp (frag_now,
4341 ((toP - frag_now->fr_literal)
4342 - the_ins.numo * 2 + the_ins.reloc[m].n),
4343 n,
4344 &the_ins.reloc[m].exp,
4345 the_ins.reloc[m].pcrel,
4346 get_reloc_code (n, the_ins.reloc[m].pcrel,
4347 the_ins.reloc[m].pic_reloc));
4348 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4349 if (the_ins.reloc[m].wid == 'B')
4350 fixP->fx_signed = 1;
4351 }
4352 return;
4353 }
4354
36759679 4355 /* There's some frag hacking. */
fbe572f9
AM		 4356 {
4357 /* Calculate the max frag size. */
4358 int wid;
4359
4360 wid = 2 * the_ins.fragb[0].fragoff;
4361 for (n = 1; n < the_ins.nfrag; n++)
4362 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4363 /* frag_var part. */
cac27205 4364 wid += FRAG_VAR_SIZE;
fbe572f9
AM		 4365 /* Make sure the whole insn fits in one chunk, in particular that
4366 the var part is attached, as we access one byte before the
4367 variable frag for byte branches. */
4368 frag_grow (wid);
4369 }
4370
252b5132
RH		 4371 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4372 {
4373 int wid;
4374
4375 if (n == 0)
4376 wid = 2 * the_ins.fragb[n].fragoff;
4377 else
4378 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4379 toP = frag_more (wid);
4380 to_beg_P = toP;
4381 shorts_this_frag = 0;
4382 for (m = wid / 2; m; --m)
4383 {
4384 md_number_to_chars (toP, (long) (*fromP), 2);
4385 toP += 2;
4386 fromP++;
4387 shorts_this_frag++;
4388 }
4389 for (m = 0; m < the_ins.nrel; m++)
4390 {
4391 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4392 {
4393 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4394 break;
4395 }
4396 wid = the_ins.reloc[m].wid;
4397 if (wid == 0)
4398 continue;
4399 the_ins.reloc[m].wid = 0;
4400 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4401
4402 fixP = fix_new_exp (frag_now,
4403 ((toP - frag_now->fr_literal)
4404 - the_ins.numo * 2 + the_ins.reloc[m].n),
4405 wid,
4406 &the_ins.reloc[m].exp,
4407 the_ins.reloc[m].pcrel,
4408 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4409 the_ins.reloc[m].pic_reloc));
4410 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4411 }
cac27205 4412 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
252b5132
RH		 4413 (relax_substateT) (the_ins.fragb[n].fragty),
4414 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4415 }
28a0da39
AM		 4416 gas_assert (the_ins.nfrag >= 1);
4417 n = the_ins.numo - the_ins.fragb[the_ins.nfrag - 1].fragoff;
252b5132
RH		 4418 shorts_this_frag = 0;
4419 if (n)
4420 {
055d1eb0 4421 toP = frag_more (n * 2);
252b5132
RH		 4422 while (n--)
4423 {
4424 md_number_to_chars (toP, (long) (*fromP), 2);
4425 toP += 2;
4426 fromP++;
4427 shorts_this_frag++;
4428 }
4429 }
4430 for (m = 0; m < the_ins.nrel; m++)
4431 {
4432 int wid;
4433
4434 wid = the_ins.reloc[m].wid;
4435 if (wid == 0)
4436 continue;
4437 the_ins.reloc[m].wid = 0;
4438 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4439
4440 fixP = fix_new_exp (frag_now,
4441 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4442 - shorts_this_frag * 2),
4443 wid,
4444 &the_ins.reloc[m].exp,
4445 the_ins.reloc[m].pcrel,
4446 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4447 the_ins.reloc[m].pic_reloc));
4448 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4449 }
4450}
4451
60fed2d3
NC		 4452/* Comparison function used by qsort to rank the opcode entries by name. */
4453
4454static int
4455m68k_compare_opcode (const void * v1, const void * v2)
4456{
4457 struct m68k_opcode * op1, * op2;
4458 int ret;
4459
03b13e59
NC		 4460 if (v1 == v2)
4461 return 0;
4462
60fed2d3
NC		 4463 op1 = *(struct m68k_opcode **) v1;
4464 op2 = *(struct m68k_opcode **) v2;
4465
4466 /* Compare the two names. If different, return the comparison.
4467 If the same, return the order they are in the opcode table. */
4468 ret = strcmp (op1->name, op2->name);
4469 if (ret)
4470 return ret;
4471 if (op1 < op2)
4472 return -1;
03b13e59 4473 return 1;
60fed2d3
NC		 4474}
4475
252b5132 4476void
60fed2d3 4477md_begin (void)
252b5132 4478{
60fed2d3
NC		 4479 const struct m68k_opcode *ins;
4480 struct m68k_incant *hack, *slak;
60fed2d3
NC		 4481 int i;
4482
4483 /* Set up hash tables with 68000 instructions.
4484 similar to what the vax assembler does. */
252b5132
RH		 4485 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4486 a copy of it at runtime, adding in the information we want but isn't
4487 there. I think it'd be better to have an awk script hack the table
4488 at compile time. Or even just xstr the table and use it as-is. But
4489 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4490 names. */
4491
252b5132
RH		 4492 if (flag_mri)
4493 {
4494 flag_reg_prefix_optional = 1;
4495 m68k_abspcadd = 1;
4496 if (! m68k_rel32_from_cmdline)
4497 m68k_rel32 = 0;
4498 }
4499
2b0f3761 4500 /* First sort the opcode table into alphabetical order to separate
60fed2d3
NC		 4501 the order that the assembler wants to see the opcodes from the
4502 order that the disassembler wants to see them. */
325801bd 4503 m68k_sorted_opcodes = XNEWVEC (const struct m68k_opcode *, m68k_numopcodes);
60fed2d3
NC		 4504
4505 for (i = m68k_numopcodes; i--;)
4506 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4507
4508 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4509 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4510
629310ab 4511 op_hash = str_htab_create ();
252b5132
RH		 4512
4513 obstack_begin (&robyn, 4000);
4514 for (i = 0; i < m68k_numopcodes; i++)
4515 {
aff7ae12 4516 hack = slak = XOBNEW (&robyn, struct m68k_incant);
252b5132
RH		 4517 do
4518 {
60fed2d3
NC		 4519 ins = m68k_sorted_opcodes[i];
4520
afa2158f
NS		 4521 /* We must enter all insns into the table, because .arch and
4522 .cpu directives can change things. */
252b5132 4523 slak->m_operands = ins->args;
252b5132
RH		 4524 slak->m_arch = ins->arch;
4525 slak->m_opcode = ins->opcode;
3739860c 4526
afa2158f
NS		 4527 /* In most cases we can determine the number of opcode words
4528 by checking the second word of the mask. Unfortunately
4529 some instructions have 2 opcode words, but no fixed bits
4530 in the second word. A leading dot in the operands
4531 string also indicates 2 opcodes. */
4532 if (*slak->m_operands == '.')
4533 {
4534 slak->m_operands++;
4535 slak->m_codenum = 2;
4536 }
4537 else if (ins->match & 0xffffL)
4538 slak->m_codenum = 2;
4539 else
4540 slak->m_codenum = 1;
4541 slak->m_opnum = strlen (slak->m_operands) / 2;
3739860c 4542
252b5132 4543 if (i + 1 != m68k_numopcodes
60fed2d3 4544 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4545 {
aff7ae12 4546 slak->m_next = XOBNEW (&robyn, struct m68k_incant);
252b5132
RH		 4547 i++;
4548 }
4549 else
4550 slak->m_next = 0;
4551 slak = slak->m_next;
4552 }
4553 while (slak);
4554
fe0e921f
AM		 4555 if (str_hash_insert (op_hash, ins->name, hack, 0) != NULL)
4556 as_fatal (_("duplicate %s"), ins->name);
252b5132
RH		 4557 }
4558
4559 for (i = 0; i < m68k_numaliases; i++)
4560 {
4561 const char *name = m68k_opcode_aliases[i].primary;
4562 const char *alias = m68k_opcode_aliases[i].alias;
fe0e921f 4563 void *val = (void *) str_hash_find (op_hash, name);
60fed2d3 4564
252b5132
RH		 4565 if (!val)
4566 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
fe0e921f
AM		 4567 if (str_hash_insert (op_hash, alias, val, 0) != NULL)
4568 as_fatal (_("duplicate %s"), alias);
252b5132
RH		 4569 }
4570
4571 /* In MRI mode, all unsized branches are variable sized. Normally,
4572 they are word sized. */
4573 if (flag_mri)
4574 {
4575 static struct m68k_opcode_alias mri_aliases[] =
4576 {
4577 { "bhi", "jhi", },
4578 { "bls", "jls", },
4579 { "bcc", "jcc", },
4580 { "bcs", "jcs", },
4581 { "bne", "jne", },
4582 { "beq", "jeq", },
4583 { "bvc", "jvc", },
4584 { "bvs", "jvs", },
4585 { "bpl", "jpl", },
4586 { "bmi", "jmi", },
4587 { "bge", "jge", },
4588 { "blt", "jlt", },
4589 { "bgt", "jgt", },
4590 { "ble", "jle", },
4591 { "bra", "jra", },
4592 { "bsr", "jbsr", },
4593 };
4594
8fce3f5e
AM		 4595 for (i = 0;
4596 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4597 i++)
252b5132
RH		 4598 {
4599 const char *name = mri_aliases[i].primary;
4600 const char *alias = mri_aliases[i].alias;
fe0e921f 4601 void *val = (void *) str_hash_find (op_hash, name);
60fed2d3 4602
252b5132
RH		 4603 if (!val)
4604 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
fe0e921f 4605 str_hash_insert (op_hash, alias, val, 1);
252b5132
RH		 4606 }
4607 }
4608
8fce3f5e 4609 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4610 {
4611 notend_table[i] = 0;
4612 alt_notend_table[i] = 0;
4613 }
60fed2d3 4614
252b5132
RH		 4615 notend_table[','] = 1;
4616 notend_table['{'] = 1;
4617 notend_table['}'] = 1;
4618 alt_notend_table['a'] = 1;
4619 alt_notend_table['A'] = 1;
4620 alt_notend_table['d'] = 1;
4621 alt_notend_table['D'] = 1;
4622 alt_notend_table['#'] = 1;
4623 alt_notend_table['&'] = 1;
4624 alt_notend_table['f'] = 1;
4625 alt_notend_table['F'] = 1;
4626#ifdef REGISTER_PREFIX
4627 alt_notend_table[REGISTER_PREFIX] = 1;
4628#endif
4629
4630 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4631 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4632 alt_notend_table['('] = 1;
4633
4634 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4635 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4636 alt_notend_table['@'] = 1;
4637
4638 /* We need to put digits in alt_notend_table to handle
60fed2d3 4639 bfextu %d0{24:1},%d0 */
252b5132
RH		 4640 alt_notend_table['0'] = 1;
4641 alt_notend_table['1'] = 1;
4642 alt_notend_table['2'] = 1;
4643 alt_notend_table['3'] = 1;
4644 alt_notend_table['4'] = 1;
4645 alt_notend_table['5'] = 1;
4646 alt_notend_table['6'] = 1;
4647 alt_notend_table['7'] = 1;
4648 alt_notend_table['8'] = 1;
4649 alt_notend_table['9'] = 1;
4650
4651#ifndef MIT_SYNTAX_ONLY
4652 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4653 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4654 {
4655 int n = 0;
60fed2d3 4656
252b5132
RH		 4657 while (mote_pseudo_table[n].poc_name)
4658 {
aff7ae12 4659 hack = XOBNEW (&robyn, struct m68k_incant);
629310ab 4660 str_hash_insert (op_hash,
fe0e921f 4661 mote_pseudo_table[n].poc_name, hack, 0);
252b5132
RH		 4662 hack->m_operands = 0;
4663 hack->m_opnum = n;
4664 n++;
4665 }
4666 }
4667#endif
4668
4669 init_regtable ();
4670
252b5132
RH		 4671 record_alignment (text_section, 2);
4672 record_alignment (data_section, 2);
4673 record_alignment (bss_section, 2);
252b5132
RH		 4674}
4675
252b5132
RH		 4676\f
4677/* This is called when a label is defined. */
4678
4679void
31302357 4680m68k_frob_label (symbolS *sym)
252b5132 4681{
c641fe0d 4682 struct m68k_tc_sy *n;
252b5132 4683
c641fe0d 4684 n = symbol_get_tc (sym);
3b4dbbbf 4685 n->file = as_where (&n->line);
252b5132 4686 n->text = 0;
252b5132 4687 current_label = n;
07a53e5c 4688
07a53e5c 4689 dwarf2_emit_label (sym);
252b5132
RH		 4690}
4691
4692/* This is called when a value that is not an instruction is emitted. */
4693
4694void
31302357 4695m68k_flush_pending_output (void)
252b5132
RH		 4696{
4697 current_label = NULL;
4698}
4699
4700/* This is called at the end of the assembly, when the final value of
4701 the label is known. We warn if this is a text symbol aligned at an
4702 odd location. */
4703
4704void
31302357 4705m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4706{
4707 if (S_GET_SEGMENT (sym) == reg_section
4708 && (int) S_GET_VALUE (sym) < 0)
4709 {
4710 S_SET_SEGMENT (sym, absolute_section);
4711 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4712 }
4713 else if ((S_GET_VALUE (sym) & 1) != 0)
4714 {
c641fe0d
ST		 4715 struct m68k_tc_sy *l;
4716 l = symbol_get_tc (sym);
252b5132 4717
c641fe0d
ST		 4718 if (l->text)
4719 as_warn_where (l->file, l->line,
4720 _("text label `%s' aligned to odd boundary"),
4721 S_GET_NAME (sym));
252b5132
RH		 4722 }
4723}
4724\f
4725/* This is called if we go in or out of MRI mode because of the .mri
4726 pseudo-op. */
4727
4728void
31302357 4729m68k_mri_mode_change (int on)
252b5132
RH		 4730{
4731 if (on)
4732 {
4733 if (! flag_reg_prefix_optional)
4734 {
4735 flag_reg_prefix_optional = 1;
4736#ifdef REGISTER_PREFIX
4737 init_regtable ();
4738#endif
4739 }
4740 m68k_abspcadd = 1;
4741 if (! m68k_rel32_from_cmdline)
4742 m68k_rel32 = 0;
4743 }
4744 else
4745 {
4746 if (! reg_prefix_optional_seen)
4747 {
4748#ifdef REGISTER_PREFIX_OPTIONAL
4749 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4750#else
4751 flag_reg_prefix_optional = 0;
4752#endif
4753#ifdef REGISTER_PREFIX
4754 init_regtable ();
4755#endif
4756 }
4757 m68k_abspcadd = 0;
4758 if (! m68k_rel32_from_cmdline)
4759 m68k_rel32 = 1;
4760 }
4761}
4762
6d4af3c2 4763const char *
31302357 4764md_atof (int type, char *litP, int *sizeP)
252b5132 4765{
5b7c81bd 4766 return ieee_md_atof (type, litP, sizeP, true);
252b5132
RH		 4767}
4768
4769void
31302357 4770md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4771{
4772 number_to_chars_bigendian (buf, val, n);
4773}
4774
94f592af 4775void
55cf6793 4776md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4777{
bbe8ef22 4778 offsetT val = *valP;
252b5132
RH		 4779 addressT upper_limit;
4780 offsetT lower_limit;
4781
4782 /* This is unnecessary but it convinces the native rs6000 compiler
4783 to generate the code we want. */
4784 char *buf = fixP->fx_frag->fr_literal;
4785 buf += fixP->fx_where;
36759679 4786 /* End ibm compiler workaround. */
252b5132 4787
bd17c2c3 4788 val = SEXT (val);
252b5132 4789
94f592af
NC		 4790 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4791 fixP->fx_done = 1;
4792
252b5132
RH		 4793 if (fixP->fx_addsy)
4794 {
4795 memset (buf, 0, fixP->fx_size);
36759679 4796 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4797
4798 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4799 && !S_IS_DEFINED (fixP->fx_addsy)
4800 && !S_IS_WEAK (fixP->fx_addsy))
4801 S_SET_WEAK (fixP->fx_addsy);
cf869cce
NC		 4802
4803 switch (fixP->fx_r_type)
4804 {
4805 case BFD_RELOC_68K_TLS_GD32:
4806 case BFD_RELOC_68K_TLS_GD16:
4807 case BFD_RELOC_68K_TLS_GD8:
4808 case BFD_RELOC_68K_TLS_LDM32:
4809 case BFD_RELOC_68K_TLS_LDM16:
4810 case BFD_RELOC_68K_TLS_LDM8:
4811 case BFD_RELOC_68K_TLS_LDO32:
4812 case BFD_RELOC_68K_TLS_LDO16:
4813 case BFD_RELOC_68K_TLS_LDO8:
4814 case BFD_RELOC_68K_TLS_IE32:
4815 case BFD_RELOC_68K_TLS_IE16:
4816 case BFD_RELOC_68K_TLS_IE8:
4817 case BFD_RELOC_68K_TLS_LE32:
4818 case BFD_RELOC_68K_TLS_LE16:
4819 case BFD_RELOC_68K_TLS_LE8:
4820 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4821 break;
4822
4823 default:
4824 break;
4825 }
4826
252b5132
RH		 4827 return;
4828 }
252b5132 4829
252b5132
RH		 4830 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4831 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4832 return;
252b5132
RH		 4833
4834 switch (fixP->fx_size)
4835 {
94f592af
NC		 4836 /* The cast to offsetT below are necessary to make code
4837 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4838 case 1:
4839 *buf++ = val;
4840 upper_limit = 0x7f;
4841 lower_limit = - (offsetT) 0x80;
4842 break;
4843 case 2:
4844 *buf++ = (val >> 8);
4845 *buf++ = val;
4846 upper_limit = 0x7fff;
4847 lower_limit = - (offsetT) 0x8000;
4848 break;
4849 case 4:
4850 *buf++ = (val >> 24);
4851 *buf++ = (val >> 16);
4852 *buf++ = (val >> 8);
4853 *buf++ = val;
4854 upper_limit = 0x7fffffff;
36759679 4855 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4856 break;
4857 default:
4858 BAD_CASE (fixP->fx_size);
4859 }
4860
4861 /* Fix up a negative reloc. */
4862 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4863 {
4864 fixP->fx_addsy = fixP->fx_subsy;
4865 fixP->fx_subsy = NULL;
4866 fixP->fx_tcbit = 1;
4867 }
4868
4869 /* For non-pc-relative values, it's conceivable we might get something
4870 like "0xff" for a byte field. So extend the upper part of the range
4871 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4872 so that we can do any range checking at all. */
4873 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4874 upper_limit = upper_limit * 2 + 1;
4875
4876 if ((addressT) val > upper_limit
4877 && (val > 0 || val < lower_limit))
2b878742
NS		 4878 as_bad_where (fixP->fx_file, fixP->fx_line,
4879 _("value %ld out of range"), (long)val);
252b5132
RH		 4880
4881 /* A one byte PC-relative reloc means a short branch. We can't use
4882 a short branch with a value of 0 or -1, because those indicate
4883 different opcodes (branches with longer offsets). fixup_segment
4884 in write.c may have clobbered fx_pcrel, so we need to examine the
4885 reloc type. */
4886 if ((fixP->fx_pcrel
7be1c489 4887 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
252b5132
RH		 4888 && fixP->fx_size == 1
4889 && (fixP->fx_addsy == NULL
4890 || S_IS_DEFINED (fixP->fx_addsy))
4891 && (val == 0 || val == -1))
2b878742
NS		 4892 as_bad_where (fixP->fx_file, fixP->fx_line,
4893 _("invalid byte branch offset"));
252b5132
RH		 4894}
4895
252b5132
RH		 4896/* *fragP has been relaxed to its final size, and now needs to have
4897 the bytes inside it modified to conform to the new size There is UGLY
4898 MAGIC here. ..
4899 */
4900static void
31302357 4901md_convert_frag_1 (fragS *fragP)
252b5132
RH		 4902{
4903 long disp;
2b878742 4904 fixS *fixP = NULL;
252b5132
RH		 4905
4906 /* Address in object code of the displacement. */
ed9e98c2 4907 int object_address = fragP->fr_fix + fragP->fr_address;
252b5132
RH		 4908
4909 /* Address in gas core of the place to store the displacement. */
4910 /* This convinces the native rs6000 compiler to generate the code we
92774660 4911 want. */
ed9e98c2 4912 char *buffer_address = fragP->fr_literal;
252b5132 4913 buffer_address += fragP->fr_fix;
36759679 4914 /* End ibm compiler workaround. */
252b5132
RH		 4915
4916 /* The displacement of the address, from current location. */
4917 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4918 disp = (disp + fragP->fr_offset) - object_address;
4919
252b5132
RH		 4920 switch (fragP->fr_subtype)
4921 {
151337e8
NC		 4922 case TAB (BRANCHBWL, BYTE):
4923 case TAB (BRABSJUNC, BYTE):
4924 case TAB (BRABSJCOND, BYTE):
4925 case TAB (BRANCHBW, BYTE):
cac27205 4926 case TAB (BRANCHBWPL, BYTE):
252b5132
RH		 4927 know (issbyte (disp));
4928 if (disp == 0)
b091f402
AM		 4929 as_bad_where (fragP->fr_file, fragP->fr_line,
4930 _("short branch with zero offset: use :w"));
151337e8 4931 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4932 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4933 fixP->fx_pcrel_adjust = -1;
252b5132 4934 break;
151337e8
NC		 4935 case TAB (BRANCHBWL, SHORT):
4936 case TAB (BRABSJUNC, SHORT):
4937 case TAB (BRABSJCOND, SHORT):
4938 case TAB (BRANCHBW, SHORT):
cac27205 4939 case TAB (BRANCHBWPL, SHORT):
252b5132 4940 fragP->fr_opcode[1] = 0x00;
2b878742
NS		 4941 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4942 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 4943 fragP->fr_fix += 2;
4944 break;
4945 case TAB (BRANCHBWL, LONG):
4946 fragP->fr_opcode[1] = (char) 0xFF;
2b878742
NS		 4947 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4948 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8 4949 fragP->fr_fix += 4;
252b5132 4950 break;
cac27205
NC		 4951 case TAB (BRANCHBWPL, LONG):
4952 /* Here we are converting an unconditional branch into a pair of
4953 conditional branches, in order to get the range. */
4954 fragP->fr_opcode[0] = 0x66; /* bne */
4955 fragP->fr_opcode[1] = 0xFF;
4956 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4957 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4958 fixP->fx_file = fragP->fr_file;
4959 fixP->fx_line = fragP->fr_line;
4960 fragP->fr_fix += 4; /* Skip first offset */
4961 buffer_address += 4;
4962 *buffer_address++ = 0x67; /* beq */
4963 *buffer_address++ = 0xff;
4964 fragP->fr_fix += 2; /* Skip second branch opcode */
4965 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4966 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4967 fragP->fr_fix += 4;
4968 break;
151337e8
NC		 4969 case TAB (BRABSJUNC, LONG):
4970 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4971 {
36759679 4972 if (flag_keep_pcrel)
2b878742
NS		 4973 as_bad_where (fragP->fr_file, fragP->fr_line,
4974 _("Conversion of PC relative BSR to absolute JSR"));
151337e8 4975 fragP->fr_opcode[0] = 0x4E;
36759679 4976 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
2b878742
NS		 4977 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4978 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4979 fragP->fr_fix += 4;
4980 }
4981 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4982 {
36759679 4983 if (flag_keep_pcrel)
2b878742
NS		 4984 as_bad_where (fragP->fr_file, fragP->fr_line,
4985 _("Conversion of PC relative branch to absolute jump"));
151337e8 4986 fragP->fr_opcode[0] = 0x4E;
36759679 4987 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
2b878742
NS		 4988 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4989 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 4990 fragP->fr_fix += 4;
252b5132
RH		 4991 }
4992 else
4993 {
151337e8
NC		 4994 /* This cannot happen, because jbsr and jbra are the only two
4995 unconditional branches. */
4996 abort ();
252b5132
RH		 4997 }
4998 break;
151337e8 4999 case TAB (BRABSJCOND, LONG):
36759679 5000 if (flag_keep_pcrel)
2b878742
NS		 5001 as_bad_where (fragP->fr_file, fragP->fr_line,
5002 _("Conversion of PC relative conditional branch to absolute jump"));
92774660 5003
36759679
NC		 5004 /* Only Bcc 68000 instructions can come here
5005 Change bcc into b!cc/jmp absl long. */
5006 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
5007 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 5008
5009 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 5010 different frag, in which case referring to them is a no-no.
92774660 5011 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 5012 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
5013 *buffer_address++ = (char) 0xf9;
36759679 5014 fragP->fr_fix += 2; /* Account for jmp instruction. */
2b878742
NS		 5015 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5016 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 5017 fragP->fr_fix += 4;
5018 break;
5019 case TAB (FBRANCH, SHORT):
5020 know ((fragP->fr_opcode[1] & 0x40) == 0);
2b878742
NS		 5021 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5022 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5023 fragP->fr_fix += 2;
5024 break;
5025 case TAB (FBRANCH, LONG):
36759679 5026 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
2b878742
NS		 5027 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5028 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 5029 fragP->fr_fix += 4;
252b5132 5030 break;
151337e8
NC		 5031 case TAB (DBCCLBR, SHORT):
5032 case TAB (DBCCABSJ, SHORT):
2b878742
NS		 5033 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5034 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5035 fragP->fr_fix += 2;
5036 break;
5037 case TAB (DBCCLBR, LONG):
36759679
NC		 5038 /* Only DBcc instructions can come here.
5039 Change dbcc into dbcc/bral.
5040 JF: these used to be fr_opcode[2-7], but that's wrong. */
36759679 5041 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 5042 *buffer_address++ = 0x04;
36759679 5043 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 5044 *buffer_address++ = 0x06;
151337e8
NC		 5045 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
5046 *buffer_address++ = (char) 0xff;
252b5132 5047
36759679 5048 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 5049 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5050 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 5051 fragP->fr_fix += 4;
252b5132 5052 break;
151337e8 5053 case TAB (DBCCABSJ, LONG):
36759679
NC		 5054 /* Only DBcc instructions can come here.
5055 Change dbcc into dbcc/jmp.
5056 JF: these used to be fr_opcode[2-7], but that's wrong. */
5057 if (flag_keep_pcrel)
2b878742
NS		 5058 as_bad_where (fragP->fr_file, fragP->fr_line,
5059 _("Conversion of PC relative conditional branch to absolute jump"));
151337e8 5060
36759679 5061 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 5062 *buffer_address++ = 0x04;
36759679 5063 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 5064 *buffer_address++ = 0x06;
36759679 5065 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 5066 *buffer_address++ = (char) 0xf9;
5067
36759679 5068 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 5069 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5070 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
252b5132 5071 fragP->fr_fix += 4;
252b5132 5072 break;
151337e8 5073 case TAB (PCREL1632, SHORT):
252b5132
RH		 5074 fragP->fr_opcode[1] &= ~0x3F;
5075 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
2b878742
NS		 5076 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5077 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 5078 fragP->fr_fix += 2;
252b5132 5079 break;
151337e8 5080 case TAB (PCREL1632, LONG):
252b5132
RH		 5081 /* Already set to mode 7.3; this indicates: PC indirect with
5082 suppressed index, 32-bit displacement. */
5083 *buffer_address++ = 0x01;
5084 *buffer_address++ = 0x70;
5085 fragP->fr_fix += 2;
151337e8 5086 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 5087 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 5088 fixP->fx_pcrel_adjust = 2;
5089 fragP->fr_fix += 4;
252b5132 5090 break;
252b5132 5091 case TAB (PCINDEX, BYTE):
9c2799c2 5092 gas_assert (fragP->fr_fix >= 2);
252b5132 5093 buffer_address[-2] &= ~1;
151337e8 5094 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 5095 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 5096 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 5097 break;
5098 case TAB (PCINDEX, SHORT):
9c2799c2 5099 gas_assert (fragP->fr_fix >= 2);
252b5132
RH		 5100 buffer_address[-2] |= 0x1;
5101 buffer_address[-1] = 0x20;
5102 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 5103 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 5104 fixP->fx_pcrel_adjust = 2;
151337e8 5105 fragP->fr_fix += 2;
252b5132
RH		 5106 break;
5107 case TAB (PCINDEX, LONG):
9c2799c2 5108 gas_assert (fragP->fr_fix >= 2);
252b5132
RH		 5109 buffer_address[-2] |= 0x1;
5110 buffer_address[-1] = 0x30;
151337e8 5111 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 5112 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 5113 fixP->fx_pcrel_adjust = 2;
5114 fragP->fr_fix += 4;
5115 break;
5116 case TAB (ABSTOPCREL, SHORT):
2b878742
NS		 5117 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5118 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5119 fragP->fr_fix += 2;
5120 break;
5121 case TAB (ABSTOPCREL, LONG):
36759679 5122 if (flag_keep_pcrel)
025987ea
NS		 5123 as_bad_where (fragP->fr_file, fragP->fr_line,
5124 _("Conversion of PC relative displacement to absolute"));
151337e8 5125 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 5126 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 5127 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5128 abort ();
5129 fragP->fr_opcode[1] &= ~0x3F;
5130 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
2b878742
NS		 5131 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5132 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 5133 fragP->fr_fix += 4;
252b5132 5134 break;
252b5132 5135 }
2b878742
NS		 5136 if (fixP)
5137 {
5138 fixP->fx_file = fragP->fr_file;
5139 fixP->fx_line = fragP->fr_line;
5140 }
252b5132
RH		 5141}
5142
252b5132 5143void
31302357
AS		 5144md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5145 segT sec ATTRIBUTE_UNUSED,
5146 fragS *fragP)
252b5132
RH		 5147{
5148 md_convert_frag_1 (fragP);
5149}
252b5132
RH		 5150
5151/* Force truly undefined symbols to their maximum size, and generally set up
5152 the frag list to be relaxed
5153 */
5154int
31302357 5155md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 5156{
151337e8 5157 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 5158 switch (fragP->fr_subtype)
5159 {
151337e8 5160 case TAB (BRANCHBWL, SZ_UNDEF):
cac27205 5161 case TAB (BRANCHBWPL, SZ_UNDEF):
151337e8 5162 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 5163 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 5164 {
151337e8
NC		 5165 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5166 && relaxable_symbol (fragP->fr_symbol))
252b5132 5167 {
151337e8
NC		 5168 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5169 }
5170 else if (flag_short_refs)
5171 {
5172 /* Symbol is undefined and we want short ref. */
5173 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5174 }
5175 else
5176 {
151337e8
NC		 5177 /* Symbol is still undefined. Make it LONG. */
5178 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5179 }
5180 break;
151337e8 5181 }
252b5132 5182
151337e8 5183 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 5184 {
151337e8
NC		 5185 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5186 && relaxable_symbol (fragP->fr_symbol))
252b5132 5187 {
151337e8 5188 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 5189 }
5190 else
5191 {
151337e8
NC		 5192 /* Symbol is undefined and we don't have long branches. */
5193 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5194 }
5195 break;
151337e8 5196 }
252b5132 5197
151337e8 5198 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 5199 case TAB (DBCCLBR, SZ_UNDEF):
5200 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 5201 case TAB (PCREL1632, SZ_UNDEF):
252b5132 5202 {
8ec6253e
NC		 5203 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5204 && relaxable_symbol (fragP->fr_symbol))
151337e8 5205 || flag_short_refs)
252b5132 5206 {
151337e8 5207 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5208 }
5209 else
5210 {
151337e8 5211 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5212 }
5213 break;
151337e8 5214 }
81d4177b 5215
252b5132
RH		 5216 case TAB (PCINDEX, SZ_UNDEF):
5217 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 5218 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 5219 {
5220 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5221 }
5222 else
5223 {
5224 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 5225 }
5226 break;
5227
151337e8
NC		 5228 case TAB (ABSTOPCREL, SZ_UNDEF):
5229 {
5230 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5231 && relaxable_symbol (fragP->fr_symbol)))
5232 {
5233 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 5234 }
5235 else
5236 {
5237 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 5238 }
5239 break;
5240 }
5241
252b5132
RH		 5242 default:
5243 break;
5244 }
5245
151337e8 5246 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 5247 switch (fragP->fr_subtype)
5248 {
151337e8
NC		 5249 case TAB (BRANCHBWL, BYTE):
5250 case TAB (BRABSJUNC, BYTE):
5251 case TAB (BRABSJCOND, BYTE):
5252 case TAB (BRANCHBW, BYTE):
252b5132 5253 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 5254 case we force word mode. If the symbol is at the start of a
5255 frag, and it is the next frag with any data in it (usually
5256 this is just the next frag, but assembler listings may
5257 introduce empty frags), we must use word mode. */
5258 if (fragP->fr_symbol)
252b5132 5259 {
ac62c346 5260 fragS *sym_frag;
252b5132 5261
ac62c346
AM		 5262 sym_frag = symbol_get_frag (fragP->fr_symbol);
5263 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 5264 {
ac62c346
AM		 5265 fragS *l;
5266
23b7f870 5267 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 5268 if (l->fr_fix != 0)
5269 break;
5270 if (l == sym_frag)
5271 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5272 }
5273 }
5274 break;
5275 default:
5276 break;
5277 }
ac62c346 5278 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 5279}
5280
252b5132 5281#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5282int md_short_jump_size = 4;
5283int md_long_jump_size = 6;
252b5132
RH		 5284
5285void
31302357
AS		 5286md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5287 fragS *frag ATTRIBUTE_UNUSED,
5288 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5289{
5290 valueT offset;
5291
5292 offset = to_addr - (from_addr + 2);
5293
5294 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5295 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5296}
5297
5298void
31302357
AS		 5299md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5300 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5301{
5302 valueT offset;
5303
6b6e92f4 5304 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5305 {
36759679 5306 if (flag_keep_pcrel)
6b6e92f4 5307 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5308 offset = to_addr - S_GET_VALUE (to_symbol);
5309 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5310 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5311 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5312 0, NO_RELOC);
5313 }
5314 else
5315 {
5316 offset = to_addr - (from_addr + 2);
5317 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5318 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5319 }
5320}
5321
5322#endif
5323
33eaf5de 5324/* Different values of OK tell what it's OK to return. Things that
252b5132
RH		 5325 aren't OK are an error (what a shock, no?)
5326
5327 0: Everything is OK
3e602632
NC		 5328 10: Absolute 1:8 only
5329 20: Absolute 0:7 only
5330 30: absolute 0:15 only
5331 40: Absolute 0:31 only
5332 50: absolute 0:127 only
252b5132 5333 55: absolute -64:63 only
3e602632 5334 60: absolute -128:127 only
afa2158f 5335 65: absolute 0:511 only
3e602632
NC		 5336 70: absolute 0:4095 only
5337 80: absolute -1, 1:7 only
5338 90: No bignums. */
252b5132
RH		 5339
5340static int
31302357 5341get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5342{
5343 if (exp->exp.X_op == O_absent)
5344 {
36759679 5345 /* Do the same thing the VAX asm does. */
252b5132
RH		 5346 op (exp) = O_constant;
5347 adds (exp) = 0;
5348 subs (exp) = 0;
5349 offs (exp) = 0;
5350 if (ok == 10)
5351 {
5352 as_warn (_("expression out of range: defaulting to 1"));
5353 offs (exp) = 1;
5354 }
5355 }
5356 else if (exp->exp.X_op == O_constant)
5357 {
5358 switch (ok)
5359 {
5360 case 10:
bd17c2c3 5361 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
252b5132
RH		 5362 {
5363 as_warn (_("expression out of range: defaulting to 1"));
5364 offs (exp) = 1;
5365 }
5366 break;
5367 case 20:
bd17c2c3 5368 if ((valueT) TRUNC (offs (exp)) > 7)
252b5132
RH		 5369 goto outrange;
5370 break;
5371 case 30:
bd17c2c3 5372 if ((valueT) TRUNC (offs (exp)) > 15)
252b5132
RH		 5373 goto outrange;
5374 break;
5375 case 40:
bd17c2c3 5376 if ((valueT) TRUNC (offs (exp)) > 32)
252b5132
RH		 5377 goto outrange;
5378 break;
5379 case 50:
bd17c2c3 5380 if ((valueT) TRUNC (offs (exp)) > 127)
252b5132
RH		 5381 goto outrange;
5382 break;
5383 case 55:
bd17c2c3 5384 if ((valueT) SEXT (offs (exp)) + 64 > 127)
252b5132
RH		 5385 goto outrange;
5386 break;
5387 case 60:
bd17c2c3 5388 if ((valueT) SEXT (offs (exp)) + 128 > 255)
252b5132 5389 goto outrange;
afa2158f
NS		 5390 break;
5391 case 65:
5392 if ((valueT) TRUNC (offs (exp)) > 511)
5393 goto outrange;
252b5132
RH		 5394 break;
5395 case 70:
bd17c2c3 5396 if ((valueT) TRUNC (offs (exp)) > 4095)
252b5132
RH		 5397 {
5398 outrange:
5399 as_warn (_("expression out of range: defaulting to 0"));
5400 offs (exp) = 0;
5401 }
5402 break;
3e602632 5403 case 80:
bd17c2c3
AM		 5404 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5405 && (valueT) TRUNC (offs (exp)) - 1 > 6)
3e602632
NC		 5406 {
5407 as_warn (_("expression out of range: defaulting to 1"));
5408 offs (exp) = 1;
5409 }
5410 break;
252b5132
RH		 5411 default:
5412 break;
5413 }
5414 }
5415 else if (exp->exp.X_op == O_big)
5416 {
36759679 5417 if (offs (exp) <= 0 /* flonum. */
3e602632 5418 && (ok == 90 /* no bignums */
36759679 5419 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5420 /* If we have a flonum zero, a zero integer should
5421 do as well (e.g., in moveq). */
5422 && generic_floating_point_number.exponent == 0
5423 && generic_floating_point_number.low[0] == 0)))
5424 {
36759679 5425 /* HACK! Turn it into a long. */
252b5132
RH		 5426 LITTLENUM_TYPE words[6];
5427
36759679 5428 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5429 op (exp) = O_constant;
5430 adds (exp) = 0;
5431 subs (exp) = 0;
5432 offs (exp) = words[1] | (words[0] << 16);
5433 }
5434 else if (ok != 0)
5435 {
5436 op (exp) = O_constant;
5437 adds (exp) = 0;
5438 subs (exp) = 0;
5439 offs (exp) = (ok == 10) ? 1 : 0;
5440 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5441 (long) offs (exp));
252b5132
RH		 5442 }
5443 }
5444 else
5445 {
3e602632 5446 if (ok >= 10 && ok <= 80)
252b5132
RH		 5447 {
5448 op (exp) = O_constant;
5449 adds (exp) = 0;
5450 subs (exp) = 0;
5451 offs (exp) = (ok == 10) ? 1 : 0;
5452 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5453 (long) offs (exp));
252b5132
RH		 5454 }
5455 }
5456
5457 if (exp->size != SIZE_UNSPEC)
5458 {
5459 switch (exp->size)
5460 {
5461 case SIZE_UNSPEC:
5462 case SIZE_LONG:
5463 break;
5464 case SIZE_BYTE:
5465 if (!isbyte (offs (exp)))
5466 as_warn (_("expression doesn't fit in BYTE"));
5467 break;
5468 case SIZE_WORD:
5469 if (!isword (offs (exp)))
5470 as_warn (_("expression doesn't fit in WORD"));
5471 break;
5472 }
5473 }
5474
5475 return offs (exp);
5476}
5477
5478/* These are the back-ends for the various machine dependent pseudo-ops. */
5479
5480static void
31302357 5481s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5482{
5483 subseg_set (data_section, 1);
5484 demand_empty_rest_of_line ();
5485}
5486
5487static void
31302357 5488s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5489{
5490 subseg_set (data_section, 2);
5491 demand_empty_rest_of_line ();
5492}
5493
252b5132 5494static void
31302357 5495s_even (int ignore ATTRIBUTE_UNUSED)
252b5132 5496{
ed9e98c2
AM		 5497 int temp;
5498 long temp_fill;
252b5132
RH		 5499
5500 temp = 1; /* JF should be 2? */
5501 temp_fill = get_absolute_expression ();
92774660 5502 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5503 frag_align (temp, (int) temp_fill, 0);
5504 demand_empty_rest_of_line ();
5505 record_alignment (now_seg, temp);
5506}
5507
5508static void
31302357 5509s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5510{
5511 demand_empty_rest_of_line ();
5512}
5513\f
5514/* Pseudo-ops handled for MRI compatibility. */
5515
5516/* This function returns non-zero if the argument is a conditional
5517 pseudo-op. This is called when checking whether a pending
5518 alignment is needed. */
5519
5520int
32e4c1c2 5521m68k_conditional_pseudoop (const pseudo_typeS *pop)
252b5132
RH		 5522{
5523 return (pop->poc_handler == s_mri_if
5524 || pop->poc_handler == s_mri_else);
5525}
5526
5527/* Handle an MRI style chip specification. */
5528
5529static void
31302357 5530mri_chip (void)
252b5132
RH		 5531{
5532 char *s;
5533 char c;
5534 int i;
5535
5536 s = input_line_pointer;
d02603dc 5537 /* We can't use get_symbol_name since the processor names are not proper
252b5132
RH		 5538 symbols. */
5539 while (is_part_of_name (c = *input_line_pointer++))
5540 ;
5541 *--input_line_pointer = 0;
266abb8f
NS		 5542 for (i = 0; m68k_cpus[i].name; i++)
5543 if (strcasecmp (s, m68k_cpus[i].name) == 0)
252b5132 5544 break;
266abb8f 5545 if (!m68k_cpus[i].name)
252b5132
RH		 5546 {
5547 as_bad (_("%s: unrecognized processor name"), s);
5548 *input_line_pointer = c;
5549 ignore_rest_of_line ();
5550 return;
5551 }
5552 *input_line_pointer = c;
5553
5554 if (*input_line_pointer == '/')
5555 current_architecture = 0;
5556 else
5557 current_architecture &= m68881 | m68851;
266abb8f 5558 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
2da12c60 5559 control_regs = m68k_cpus[i].control_regs;
252b5132
RH		 5560
5561 while (*input_line_pointer == '/')
5562 {
5563 ++input_line_pointer;
5564 s = input_line_pointer;
d02603dc 5565 /* We can't use get_symbol_name since the processor names are not
252b5132
RH		 5566 proper symbols. */
5567 while (is_part_of_name (c = *input_line_pointer++))
5568 ;
5569 *--input_line_pointer = 0;
5570 if (strcmp (s, "68881") == 0)
5571 current_architecture |= m68881;
5572 else if (strcmp (s, "68851") == 0)
5573 current_architecture |= m68851;
5574 *input_line_pointer = c;
5575 }
252b5132
RH		 5576}
5577
5578/* The MRI CHIP pseudo-op. */
5579
5580static void
31302357 5581s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5582{
5583 char *stop = NULL;
5584 char stopc;
5585
5586 if (flag_mri)
5587 stop = mri_comment_field (&stopc);
5588 mri_chip ();
5589 if (flag_mri)
5590 mri_comment_end (stop, stopc);
5591 demand_empty_rest_of_line ();
5592}
5593
5594/* The MRI FOPT pseudo-op. */
5595
5596static void
31302357 5597s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5598{
5599 SKIP_WHITESPACE ();
5600
5601 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5602 {
5603 int temp;
5604
5605 input_line_pointer += 3;
5606 temp = get_absolute_expression ();
5607 if (temp < 0 || temp > 7)
5608 as_bad (_("bad coprocessor id"));
5609 else
5610 m68k_float_copnum = COP0 + temp;
5611 }
5612 else
5613 {
5614 as_bad (_("unrecognized fopt option"));
5615 ignore_rest_of_line ();
5616 return;
5617 }
5618
5619 demand_empty_rest_of_line ();
5620}
5621
5622/* The structure used to handle the MRI OPT pseudo-op. */
5623
5624struct opt_action
5625{
5626 /* The name of the option. */
5627 const char *name;
5628
5629 /* If this is not NULL, just call this function. The first argument
5630 is the ARG field of this structure, the second argument is
5631 whether the option was negated. */
31302357 5632 void (*pfn) (int arg, int on);
252b5132
RH		 5633
5634 /* If this is not NULL, and the PFN field is NULL, set the variable
5635 this points to. Set it to the ARG field if the option was not
5636 negated, and the NOTARG field otherwise. */
5637 int *pvar;
5638
5639 /* The value to pass to PFN or to assign to *PVAR. */
5640 int arg;
5641
5642 /* The value to assign to *PVAR if the option is negated. If PFN is
5643 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5644 the option may not be negated. */
5645 int notarg;
5646};
5647
5648/* The table used to handle the MRI OPT pseudo-op. */
5649
31302357
AS		 5650static void skip_to_comma (int, int);
5651static void opt_nest (int, int);
5652static void opt_chip (int, int);
5653static void opt_list (int, int);
5654static void opt_list_symbols (int, int);
252b5132
RH		 5655
5656static const struct opt_action opt_table[] =
5657{
5658 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5659
5660 /* We do relaxing, so there is little use for these options. */
5661 { "b", 0, 0, 0, 0 },
5662 { "brs", 0, 0, 0, 0 },
5663 { "brb", 0, 0, 0, 0 },
5664 { "brl", 0, 0, 0, 0 },
5665 { "brw", 0, 0, 0, 0 },
5666
5667 { "c", 0, 0, 0, 0 },
5668 { "cex", 0, 0, 0, 0 },
5669 { "case", 0, &symbols_case_sensitive, 1, 0 },
5670 { "cl", 0, 0, 0, 0 },
5671 { "cre", 0, 0, 0, 0 },
5672 { "d", 0, &flag_keep_locals, 1, 0 },
5673 { "e", 0, 0, 0, 0 },
5674 { "f", 0, &flag_short_refs, 1, 0 },
5675 { "frs", 0, &flag_short_refs, 1, 0 },
5676 { "frl", 0, &flag_short_refs, 0, 1 },
5677 { "g", 0, 0, 0, 0 },
5678 { "i", 0, 0, 0, 0 },
5679 { "m", 0, 0, 0, 0 },
5680 { "mex", 0, 0, 0, 0 },
5681 { "mc", 0, 0, 0, 0 },
5682 { "md", 0, 0, 0, 0 },
5683 { "nest", opt_nest, 0, 0, 0 },
5684 { "next", skip_to_comma, 0, 0, 0 },
5685 { "o", 0, 0, 0, 0 },
5686 { "old", 0, 0, 0, 0 },
5687 { "op", skip_to_comma, 0, 0, 0 },
5688 { "pco", 0, 0, 0, 0 },
5689 { "p", opt_chip, 0, 0, 0 },
5690 { "pcr", 0, 0, 0, 0 },
5691 { "pcs", 0, 0, 0, 0 },
5692 { "r", 0, 0, 0, 0 },
5693 { "quick", 0, &m68k_quick, 1, 0 },
5694 { "rel32", 0, &m68k_rel32, 1, 0 },
5695 { "s", opt_list, 0, 0, 0 },
5696 { "t", opt_list_symbols, 0, 0, 0 },
5697 { "w", 0, &flag_no_warnings, 0, 1 },
5698 { "x", 0, 0, 0, 0 }
5699};
5700
8fce3f5e 5701#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5702
5703/* The MRI OPT pseudo-op. */
5704
5705static void
31302357 5706s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5707{
5708 do
5709 {
5710 int t;
5711 char *s;
5712 char c;
5713 int i;
5714 const struct opt_action *o;
5715
5716 SKIP_WHITESPACE ();
5717
5718 t = 1;
5719 if (*input_line_pointer == '-')
5720 {
5721 ++input_line_pointer;
5722 t = 0;
5723 }
5724 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5725 {
5726 input_line_pointer += 2;
5727 t = 0;
5728 }
5729
d02603dc 5730 c = get_symbol_name (&s);
252b5132
RH		 5731
5732 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5733 {
5734 if (strcasecmp (s, o->name) == 0)
5735 {
5736 if (o->pfn)
5737 {
5738 /* Restore input_line_pointer now in case the option
5739 takes arguments. */
d02603dc 5740 (void) restore_line_pointer (c);
252b5132
RH		 5741 (*o->pfn) (o->arg, t);
5742 }
5743 else if (o->pvar != NULL)
5744 {
5745 if (! t && o->arg == o->notarg)
5746 as_bad (_("option `%s' may not be negated"), s);
d02603dc 5747 restore_line_pointer (c);
252b5132
RH		 5748 *o->pvar = t ? o->arg : o->notarg;
5749 }
5750 else
5751 *input_line_pointer = c;
5752 break;
5753 }
5754 }
5755 if (i >= OPTCOUNT)
5756 {
5757 as_bad (_("option `%s' not recognized"), s);
d02603dc 5758 restore_line_pointer (c);
252b5132
RH		 5759 }
5760 }
5761 while (*input_line_pointer++ == ',');
5762
5763 /* Move back to terminating character. */
5764 --input_line_pointer;
5765 demand_empty_rest_of_line ();
5766}
5767
5768/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5769 not support and which take arguments. */
252b5132
RH		 5770
5771static void
31302357 5772skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5773{
5774 while (*input_line_pointer != ','
5775 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5776 ++input_line_pointer;
5777}
5778
5779/* Handle the OPT NEST=depth option. */
5780
5781static void
31302357 5782opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5783{
5784 if (*input_line_pointer != '=')
5785 {
5786 as_bad (_("bad format of OPT NEST=depth"));
5787 return;
5788 }
5789
5790 ++input_line_pointer;
5791 max_macro_nest = get_absolute_expression ();
5792}
5793
5794/* Handle the OPT P=chip option. */
5795
5796static void
31302357 5797opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5798{
5799 if (*input_line_pointer != '=')
5800 {
5801 /* This is just OPT P, which we do not support. */
5802 return;
5803 }
5804
5805 ++input_line_pointer;
5806 mri_chip ();
5807}
5808
5809/* Handle the OPT S option. */
5810
5811static void
31302357 5812opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5813{
5814 listing_list (on);
5815}
5816
5817/* Handle the OPT T option. */
5818
5819static void
31302357 5820opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5821{
5822 if (on)
5823 listing |= LISTING_SYMBOLS;
5824 else
8a104df9 5825 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5826}
5827
5828/* Handle the MRI REG pseudo-op. */
5829
5830static void
31302357 5831s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5832{
5833 char *s;
5834 int c;
5835 struct m68k_op rop;
5836 int mask;
5837 char *stop = NULL;
5838 char stopc;
5839
5840 if (line_label == NULL)
5841 {
5842 as_bad (_("missing label"));
5843 ignore_rest_of_line ();
5844 return;
5845 }
5846
5847 if (flag_mri)
5848 stop = mri_comment_field (&stopc);
5849
5850 SKIP_WHITESPACE ();
5851
5852 s = input_line_pointer;
3882b010 5853 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5854#ifdef REGISTER_PREFIX
5855 || *input_line_pointer == REGISTER_PREFIX
5856#endif
5857 || *input_line_pointer == '/'
5858 || *input_line_pointer == '-')
5859 ++input_line_pointer;
5860 c = *input_line_pointer;
5861 *input_line_pointer = '\0';
5862
5863 if (m68k_ip_op (s, &rop) != 0)
5864 {
5865 if (rop.error == NULL)
5866 as_bad (_("bad register list"));
5867 else
5868 as_bad (_("bad register list: %s"), rop.error);
5869 *input_line_pointer = c;
5870 ignore_rest_of_line ();
5871 return;
5872 }
5873
5874 *input_line_pointer = c;
5875
5876 if (rop.mode == REGLST)
5877 mask = rop.mask;
5878 else if (rop.mode == DREG)
5879 mask = 1 << (rop.reg - DATA0);
5880 else if (rop.mode == AREG)
5881 mask = 1 << (rop.reg - ADDR0 + 8);
5882 else if (rop.mode == FPREG)
5883 mask = 1 << (rop.reg - FP0 + 16);
5884 else if (rop.mode == CONTROL
5885 && rop.reg == FPI)
5886 mask = 1 << 24;
5887 else if (rop.mode == CONTROL
5888 && rop.reg == FPS)
5889 mask = 1 << 25;
5890 else if (rop.mode == CONTROL
5891 && rop.reg == FPC)
5892 mask = 1 << 26;
5893 else
5894 {
5895 as_bad (_("bad register list"));
5896 ignore_rest_of_line ();
5897 return;
5898 }
5899
5900 S_SET_SEGMENT (line_label, reg_section);
5901 S_SET_VALUE (line_label, ~mask);
49309057 5902 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5903
5904 if (flag_mri)
5905 mri_comment_end (stop, stopc);
5906
5907 demand_empty_rest_of_line ();
5908}
5909
5910/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5911
5912struct save_opts
5913{
5914 struct save_opts *next;
5915 int abspcadd;
5916 int symbols_case_sensitive;
5917 int keep_locals;
5918 int short_refs;
5919 int architecture;
2da12c60 5920 const enum m68k_register *control_regs;
252b5132
RH		 5921 int quick;
5922 int rel32;
5923 int listing;
5924 int no_warnings;
5925 /* FIXME: We don't save OPT S. */
5926};
5927
5928/* This variable holds the stack of saved options. */
5929
5930static struct save_opts *save_stack;
5931
5932/* The MRI SAVE pseudo-op. */
5933
5934static void
31302357 5935s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5936{
5937 struct save_opts *s;
5938
add39d23 5939 s = XNEW (struct save_opts);
252b5132
RH		 5940 s->abspcadd = m68k_abspcadd;
5941 s->symbols_case_sensitive = symbols_case_sensitive;
5942 s->keep_locals = flag_keep_locals;
5943 s->short_refs = flag_short_refs;
5944 s->architecture = current_architecture;
2da12c60 5945 s->control_regs = control_regs;
252b5132
RH		 5946 s->quick = m68k_quick;
5947 s->rel32 = m68k_rel32;
5948 s->listing = listing;
5949 s->no_warnings = flag_no_warnings;
5950
5951 s->next = save_stack;
5952 save_stack = s;
5953
5954 demand_empty_rest_of_line ();
5955}
5956
5957/* The MRI RESTORE pseudo-op. */
5958
5959static void
31302357 5960s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5961{
5962 struct save_opts *s;
5963
5964 if (save_stack == NULL)
5965 {
5966 as_bad (_("restore without save"));
5967 ignore_rest_of_line ();
5968 return;
5969 }
5970
5971 s = save_stack;
5972 save_stack = s->next;
5973
5974 m68k_abspcadd = s->abspcadd;
5975 symbols_case_sensitive = s->symbols_case_sensitive;
5976 flag_keep_locals = s->keep_locals;
5977 flag_short_refs = s->short_refs;
5978 current_architecture = s->architecture;
2da12c60 5979 control_regs = s->control_regs;
252b5132
RH		 5980 m68k_quick = s->quick;
5981 m68k_rel32 = s->rel32;
5982 listing = s->listing;
5983 flag_no_warnings = s->no_warnings;
5984
5985 free (s);
5986
5987 demand_empty_rest_of_line ();
5988}
5989
5990/* Types of MRI structured control directives. */
5991
5992enum mri_control_type
5993{
5994 mri_for,
5995 mri_if,
5996 mri_repeat,
5997 mri_while
5998};
5999
6000/* This structure is used to stack the MRI structured control
6001 directives. */
6002
6003struct mri_control_info
6004{
6005 /* The directive within which this one is enclosed. */
6006 struct mri_control_info *outer;
6007
6008 /* The type of directive. */
6009 enum mri_control_type type;
6010
6011 /* Whether an ELSE has been in an IF. */
6012 int else_seen;
6013
6014 /* The add or sub statement at the end of a FOR. */
6015 char *incr;
6016
6017 /* The label of the top of a FOR or REPEAT loop. */
6018 char *top;
6019
6020 /* The label to jump to for the next iteration, or the else
6021 expression of a conditional. */
6022 char *next;
6023
6024 /* The label to jump to to break out of the loop, or the label past
6025 the end of a conditional. */
6026 char *bottom;
6027};
6028
6029/* The stack of MRI structured control directives. */
6030
6031static struct mri_control_info *mri_control_stack;
6032
6033/* The current MRI structured control directive index number, used to
6034 generate label names. */
6035
6036static int mri_control_index;
6037
252b5132
RH		 6038/* Assemble an instruction for an MRI structured control directive. */
6039
6040static void
31302357 6041mri_assemble (char *str)
252b5132
RH		 6042{
6043 char *s;
6044
6045 /* md_assemble expects the opcode to be in lower case. */
6046 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 6047 *s = TOLOWER (*s);
252b5132
RH		 6048
6049 md_assemble (str);
6050}
6051
6052/* Generate a new MRI label structured control directive label name. */
6053
6054static char *
31302357 6055mri_control_label (void)
252b5132
RH		 6056{
6057 char *n;
6058
add39d23 6059 n = XNEWVEC (char, 20);
252b5132
RH		 6060 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6061 ++mri_control_index;
6062 return n;
6063}
6064
6065/* Create a new MRI structured control directive. */
6066
6067static struct mri_control_info *
31302357 6068push_mri_control (enum mri_control_type type)
252b5132
RH		 6069{
6070 struct mri_control_info *n;
6071
add39d23 6072 n = XNEW (struct mri_control_info);
252b5132
RH		 6073
6074 n->type = type;
6075 n->else_seen = 0;
6076 if (type == mri_if || type == mri_while)
6077 n->top = NULL;
6078 else
6079 n->top = mri_control_label ();
6080 n->next = mri_control_label ();
6081 n->bottom = mri_control_label ();
6082
6083 n->outer = mri_control_stack;
6084 mri_control_stack = n;
6085
6086 return n;
6087}
6088
6089/* Pop off the stack of MRI structured control directives. */
6090
6091static void
31302357 6092pop_mri_control (void)
252b5132
RH		 6093{
6094 struct mri_control_info *n;
6095
6096 n = mri_control_stack;
6097 mri_control_stack = n->outer;
9fbb53c7 6098 free (n->top);
252b5132
RH		 6099 free (n->next);
6100 free (n->bottom);
6101 free (n);
6102}
6103
6104/* Recognize a condition code in an MRI structured control expression. */
6105
6106static int
31302357 6107parse_mri_condition (int *pcc)
252b5132
RH		 6108{
6109 char c1, c2;
6110
6111 know (*input_line_pointer == '<');
6112
6113 ++input_line_pointer;
6114 c1 = *input_line_pointer++;
6115 c2 = *input_line_pointer++;
6116
6117 if (*input_line_pointer != '>')
6118 {
6119 as_bad (_("syntax error in structured control directive"));
6120 return 0;
6121 }
6122
6123 ++input_line_pointer;
6124 SKIP_WHITESPACE ();
6125
3882b010
L		 6126 c1 = TOLOWER (c1);
6127 c2 = TOLOWER (c2);
252b5132
RH		 6128
6129 *pcc = (c1 << 8) | c2;
6130
6131 return 1;
6132}
6133
6134/* Parse a single operand in an MRI structured control expression. */
6135
6136static int
31302357
AS		 6137parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6138 char **rightstart, char **rightstop)
252b5132
RH		 6139{
6140 char *s;
6141
6142 SKIP_WHITESPACE ();
6143
6144 *pcc = -1;
6145 *leftstart = NULL;
6146 *leftstop = NULL;
6147 *rightstart = NULL;
6148 *rightstop = NULL;
6149
6150 if (*input_line_pointer == '<')
6151 {
6152 /* It's just a condition code. */
6153 return parse_mri_condition (pcc);
6154 }
6155
6156 /* Look ahead for the condition code. */
6157 for (s = input_line_pointer; *s != '\0'; ++s)
6158 {
6159 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6160 break;
6161 }
6162 if (*s == '\0')
6163 {
6164 as_bad (_("missing condition code in structured control directive"));
6165 return 0;
6166 }
6167
6168 *leftstart = input_line_pointer;
6169 *leftstop = s;
6170 if (*leftstop > *leftstart
6171 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6172 --*leftstop;
6173
6174 input_line_pointer = s;
6175 if (! parse_mri_condition (pcc))
6176 return 0;
6177
6178 /* Look ahead for AND or OR or end of line. */
6179 for (s = input_line_pointer; *s != '\0'; ++s)
6180 {
e1f44d10
NC		 6181 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6182 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6183 ^^^ ^^ */
8a104df9
KH		 6184 if ((s == input_line_pointer
6185 || *(s-1) == ' '
6186 || *(s-1) == '\t')
6187 && ((strncasecmp (s, "AND", 3) == 0
6188 && (s[3] == '.' || ! is_part_of_name (s[3])))
6189 || (strncasecmp (s, "OR", 2) == 0
6190 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6191 break;
252b5132
RH		 6192 }
6193
6194 *rightstart = input_line_pointer;
6195 *rightstop = s;
6196 if (*rightstop > *rightstart
6197 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6198 --*rightstop;
6199
6200 input_line_pointer = s;
6201
6202 return 1;
6203}
6204
6205#define MCC(b1, b2) (((b1) << 8) | (b2))
6206
6207/* Swap the sense of a condition. This changes the condition so that
6208 it generates the same result when the operands are swapped. */
6209
6210static int
31302357 6211swap_mri_condition (int cc)
252b5132
RH		 6212{
6213 switch (cc)
6214 {
6215 case MCC ('h', 'i'): return MCC ('c', 's');
6216 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 6217 /* <HS> is an alias for <CC>. */
e1f44d10 6218 case MCC ('h', 's'):
252b5132 6219 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 6220 /* <LO> is an alias for <CS>. */
e1f44d10 6221 case MCC ('l', 'o'):
252b5132
RH		 6222 case MCC ('c', 's'): return MCC ('h', 'i');
6223 case MCC ('p', 'l'): return MCC ('m', 'i');
6224 case MCC ('m', 'i'): return MCC ('p', 'l');
6225 case MCC ('g', 'e'): return MCC ('l', 'e');
6226 case MCC ('l', 't'): return MCC ('g', 't');
6227 case MCC ('g', 't'): return MCC ('l', 't');
6228 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 6229 /* Issue a warning for conditions we can not swap. */
8fc4ee9b
AM		 6230 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6231 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
e1f44d10
NC		 6232 case MCC ('v', 'c'):
6233 case MCC ('v', 's'):
6234 default :
6235 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6236 (char) (cc >> 8), (char) (cc));
6237 break;
252b5132
RH		 6238 }
6239 return cc;
6240}
6241
6242/* Reverse the sense of a condition. */
6243
6244static int
31302357 6245reverse_mri_condition (int cc)
252b5132
RH		 6246{
6247 switch (cc)
6248 {
6249 case MCC ('h', 'i'): return MCC ('l', 's');
6250 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 6251 /* <HS> is an alias for <CC> */
6252 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6253 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6254 /* <LO> is an alias for <CS> */
6255 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6256 case MCC ('c', 's'): return MCC ('c', 'c');
6257 case MCC ('n', 'e'): return MCC ('e', 'q');
6258 case MCC ('e', 'q'): return MCC ('n', 'e');
6259 case MCC ('v', 'c'): return MCC ('v', 's');
6260 case MCC ('v', 's'): return MCC ('v', 'c');
6261 case MCC ('p', 'l'): return MCC ('m', 'i');
6262 case MCC ('m', 'i'): return MCC ('p', 'l');
6263 case MCC ('g', 'e'): return MCC ('l', 't');
6264 case MCC ('l', 't'): return MCC ('g', 'e');
6265 case MCC ('g', 't'): return MCC ('l', 'e');
6266 case MCC ('l', 'e'): return MCC ('g', 't');
6267 }
6268 return cc;
6269}
6270
6271/* Build an MRI structured control expression. This generates test
6272 and branch instructions. It goes to TRUELAB if the condition is
6273 true, and to FALSELAB if the condition is false. Exactly one of
6274 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6275 is the size qualifier for the expression. EXTENT is the size to
6276 use for the branch. */
6277
6278static void
31302357
AS		 6279build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6280 char *rightstart, char *rightstop,
6281 const char *truelab, const char *falselab,
6282 int extent)
252b5132
RH		 6283{
6284 char *buf;
6285 char *s;
6286
6287 if (leftstart != NULL)
6288 {
6289 struct m68k_op leftop, rightop;
6290 char c;
6291
6292 /* Swap the compare operands, if necessary, to produce a legal
6293 m68k compare instruction. Comparing a register operand with
6294 a non-register operand requires the register to be on the
6295 right (cmp, cmpa). Comparing an immediate value with
6296 anything requires the immediate value to be on the left
6297 (cmpi). */
6298
6299 c = *leftstop;
6300 *leftstop = '\0';
6301 (void) m68k_ip_op (leftstart, &leftop);
6302 *leftstop = c;
6303
6304 c = *rightstop;
6305 *rightstop = '\0';
6306 (void) m68k_ip_op (rightstart, &rightop);
6307 *rightstop = c;
6308
6309 if (rightop.mode == IMMED
6310 || ((leftop.mode == DREG || leftop.mode == AREG)
6311 && (rightop.mode != DREG && rightop.mode != AREG)))
6312 {
6313 char *temp;
6314
31302357
AS		 6315 /* Correct conditional handling:
6316 if #1 <lt> d0 then ;means if (1 < d0)
6317 ...
6318 endi
e1f44d10 6319
31302357 6320 should assemble to:
e1f44d10 6321
31302357
AS		 6322 cmp #1,d0 if we do *not* swap the operands
6323 bgt true we need the swapped condition!
6324 ble false
6325 true:
6326 ...
6327 false:
6328 */
252b5132
RH		 6329 temp = leftstart;
6330 leftstart = rightstart;
6331 rightstart = temp;
6332 temp = leftstop;
6333 leftstop = rightstop;
6334 rightstop = temp;
8a104df9
KH		 6335 }
6336 else
6337 {
e1f44d10 6338 cc = swap_mri_condition (cc);
252b5132
RH		 6339 }
6340 }
6341
6342 if (truelab == NULL)
6343 {
6344 cc = reverse_mri_condition (cc);
6345 truelab = falselab;
6346 }
92774660 6347
252b5132
RH		 6348 if (leftstart != NULL)
6349 {
add39d23
TS		 6350 buf = XNEWVEC (char, (20
6351 + (leftstop - leftstart)
6352 + (rightstop - rightstart)));
252b5132
RH		 6353 s = buf;
6354 *s++ = 'c';
6355 *s++ = 'm';
6356 *s++ = 'p';
6357 if (qual != '\0')
3882b010 6358 *s++ = TOLOWER (qual);
252b5132
RH		 6359 *s++ = ' ';
6360 memcpy (s, leftstart, leftstop - leftstart);
6361 s += leftstop - leftstart;
6362 *s++ = ',';
6363 memcpy (s, rightstart, rightstop - rightstart);
6364 s += rightstop - rightstart;
6365 *s = '\0';
6366 mri_assemble (buf);
6367 free (buf);
6368 }
92774660 6369
add39d23 6370 buf = XNEWVEC (char, 20 + strlen (truelab));
252b5132
RH		 6371 s = buf;
6372 *s++ = 'b';
6373 *s++ = cc >> 8;
6374 *s++ = cc & 0xff;
6375 if (extent != '\0')
3882b010 6376 *s++ = TOLOWER (extent);
252b5132
RH		 6377 *s++ = ' ';
6378 strcpy (s, truelab);
6379 mri_assemble (buf);
6380 free (buf);
6381}
6382
6383/* Parse an MRI structured control expression. This generates test
6384 and branch instructions. STOP is where the expression ends. It
6385 goes to TRUELAB if the condition is true, and to FALSELAB if the
6386 condition is false. Exactly one of TRUELAB and FALSELAB will be
6387 NULL, meaning to fall through. QUAL is the size qualifier for the
6388 expression. EXTENT is the size to use for the branch. */
6389
6390static void
31302357
AS		 6391parse_mri_control_expression (char *stop, int qual, const char *truelab,
6392 const char *falselab, int extent)
252b5132
RH		 6393{
6394 int c;
6395 int cc;
6396 char *leftstart;
6397 char *leftstop;
6398 char *rightstart;
6399 char *rightstop;
6400
6401 c = *stop;
6402 *stop = '\0';
6403
6404 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6405 &rightstart, &rightstop))
6406 {
6407 *stop = c;
6408 return;
6409 }
6410
6411 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6412 {
6413 const char *flab;
6414
6415 if (falselab != NULL)
6416 flab = falselab;
6417 else
6418 flab = mri_control_label ();
6419
6420 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6421 rightstop, (const char *) NULL, flab, extent);
6422
6423 input_line_pointer += 3;
6424 if (*input_line_pointer != '.'
6425 || input_line_pointer[1] == '\0')
6426 qual = '\0';
6427 else
6428 {
6429 qual = input_line_pointer[1];
6430 input_line_pointer += 2;
6431 }
6432
6433 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6434 &rightstart, &rightstop))
6435 {
6436 *stop = c;
6437 return;
6438 }
6439
6440 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6441 rightstop, truelab, falselab, extent);
6442
6443 if (falselab == NULL)
6444 colon (flab);
6445 }
6446 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6447 {
6448 const char *tlab;
6449
6450 if (truelab != NULL)
6451 tlab = truelab;
6452 else
6453 tlab = mri_control_label ();
6454
6455 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6456 rightstop, tlab, (const char *) NULL, extent);
6457
6458 input_line_pointer += 2;
6459 if (*input_line_pointer != '.'
6460 || input_line_pointer[1] == '\0')
6461 qual = '\0';
6462 else
6463 {
6464 qual = input_line_pointer[1];
6465 input_line_pointer += 2;
6466 }
6467
6468 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6469 &rightstart, &rightstop))
6470 {
6471 *stop = c;
6472 return;
6473 }
6474
6475 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6476 rightstop, truelab, falselab, extent);
6477
6478 if (truelab == NULL)
6479 colon (tlab);
6480 }
6481 else
6482 {
6483 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6484 rightstop, truelab, falselab, extent);
6485 }
6486
6487 *stop = c;
6488 if (input_line_pointer != stop)
6489 as_bad (_("syntax error in structured control directive"));
6490}
6491
6492/* Handle the MRI IF pseudo-op. This may be a structured control
6493 directive, or it may be a regular assembler conditional, depending
6494 on its operands. */
6495
6496static void
31302357 6497s_mri_if (int qual)
252b5132
RH		 6498{
6499 char *s;
6500 int c;
6501 struct mri_control_info *n;
6502
6503 /* A structured control directive must end with THEN with an
6504 optional qualifier. */
6505 s = input_line_pointer;
e1f44d10
NC		 6506 /* We only accept '*' as introduction of comments if preceded by white space
6507 or at first column of a line (I think this can't actually happen here?)
6508 This is important when assembling:
6509 if d0 <ne> 12(a0,d0*2) then
36759679 6510 if d0 <ne> #CONST*20 then. */
31302357
AS		 6511 while (! (is_end_of_line[(unsigned char) *s]
6512 || (flag_mri
6513 && *s == '*'
6514 && (s == input_line_pointer
6515 || *(s-1) == ' '
6516 || *(s-1) == '\t'))))
252b5132
RH		 6517 ++s;
6518 --s;
6519 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6520 --s;
6521
6522 if (s - input_line_pointer > 1
6523 && s[-1] == '.')
6524 s -= 2;
6525
6526 if (s - input_line_pointer < 3
6527 || strncasecmp (s - 3, "THEN", 4) != 0)
6528 {
6529 if (qual != '\0')
6530 {
6531 as_bad (_("missing then"));
6532 ignore_rest_of_line ();
6533 return;
6534 }
6535
6536 /* It's a conditional. */
6537 s_if (O_ne);
6538 return;
6539 }
6540
6541 /* Since this might be a conditional if, this pseudo-op will be
6542 called even if we are supported to be ignoring input. Double
6543 check now. Clobber *input_line_pointer so that ignore_input
6544 thinks that this is not a special pseudo-op. */
6545 c = *input_line_pointer;
6546 *input_line_pointer = 0;
6547 if (ignore_input ())
6548 {
6549 *input_line_pointer = c;
6550 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6551 ++input_line_pointer;
6552 demand_empty_rest_of_line ();
6553 return;
6554 }
6555 *input_line_pointer = c;
6556
6557 n = push_mri_control (mri_if);
6558
6559 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6560 n->next, s[1] == '.' ? s[2] : '\0');
6561
6562 if (s[1] == '.')
6563 input_line_pointer = s + 3;
6564 else
6565 input_line_pointer = s + 1;
6566
6567 if (flag_mri)
6568 {
6569 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6570 ++input_line_pointer;
6571 }
6572
6573 demand_empty_rest_of_line ();
6574}
6575
6576/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6577 structured IF, associate the ELSE with the IF. Otherwise, assume
6578 it is a conditional else. */
6579
6580static void
31302357 6581s_mri_else (int qual)
252b5132
RH		 6582{
6583 int c;
6584 char *buf;
6585 char q[2];
6586
6587 if (qual == '\0'
6588 && (mri_control_stack == NULL
6589 || mri_control_stack->type != mri_if
6590 || mri_control_stack->else_seen))
6591 {
6592 s_else (0);
6593 return;
6594 }
6595
6596 c = *input_line_pointer;
6597 *input_line_pointer = 0;
6598 if (ignore_input ())
6599 {
6600 *input_line_pointer = c;
6601 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6602 ++input_line_pointer;
6603 demand_empty_rest_of_line ();
6604 return;
6605 }
6606 *input_line_pointer = c;
6607
6608 if (mri_control_stack == NULL
6609 || mri_control_stack->type != mri_if
6610 || mri_control_stack->else_seen)
6611 {
6612 as_bad (_("else without matching if"));
6613 ignore_rest_of_line ();
6614 return;
6615 }
6616
6617 mri_control_stack->else_seen = 1;
6618
add39d23 6619 buf = XNEWVEC (char, 20 + strlen (mri_control_stack->bottom));
3882b010 6620 q[0] = TOLOWER (qual);
252b5132
RH		 6621 q[1] = '\0';
6622 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6623 mri_assemble (buf);
6624 free (buf);
6625
6626 colon (mri_control_stack->next);
6627
6628 if (flag_mri)
6629 {
6630 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6631 ++input_line_pointer;
6632 }
6633
6634 demand_empty_rest_of_line ();
6635}
6636
6637/* Handle the MRI ENDI pseudo-op. */
6638
6639static void
31302357 6640s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6641{
6642 if (mri_control_stack == NULL
6643 || mri_control_stack->type != mri_if)
6644 {
6645 as_bad (_("endi without matching if"));
6646 ignore_rest_of_line ();
6647 return;
6648 }
6649
6650 /* ignore_input will not return true for ENDI, so we don't need to
6651 worry about checking it again here. */
6652
6653 if (! mri_control_stack->else_seen)
6654 colon (mri_control_stack->next);
6655 colon (mri_control_stack->bottom);
6656
6657 pop_mri_control ();
6658
6659 if (flag_mri)
6660 {
6661 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6662 ++input_line_pointer;
6663 }
6664
6665 demand_empty_rest_of_line ();
6666}
6667
6668/* Handle the MRI BREAK pseudo-op. */
6669
6670static void
31302357 6671s_mri_break (int extent)
252b5132
RH		 6672{
6673 struct mri_control_info *n;
6674 char *buf;
6675 char ex[2];
6676
6677 n = mri_control_stack;
6678 while (n != NULL
6679 && n->type != mri_for
6680 && n->type != mri_repeat
6681 && n->type != mri_while)
6682 n = n->outer;
6683 if (n == NULL)
6684 {
6685 as_bad (_("break outside of structured loop"));
6686 ignore_rest_of_line ();
6687 return;
6688 }
6689
add39d23 6690 buf = XNEWVEC (char, 20 + strlen (n->bottom));
3882b010 6691 ex[0] = TOLOWER (extent);
252b5132
RH		 6692 ex[1] = '\0';
6693 sprintf (buf, "bra%s %s", ex, n->bottom);
6694 mri_assemble (buf);
6695 free (buf);
6696
6697 if (flag_mri)
6698 {
6699 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6700 ++input_line_pointer;
6701 }
6702
6703 demand_empty_rest_of_line ();
6704}
6705
6706/* Handle the MRI NEXT pseudo-op. */
6707
6708static void
31302357 6709s_mri_next (int extent)
252b5132
RH		 6710{
6711 struct mri_control_info *n;
6712 char *buf;
6713 char ex[2];
6714
6715 n = mri_control_stack;
6716 while (n != NULL
6717 && n->type != mri_for
6718 && n->type != mri_repeat
6719 && n->type != mri_while)
6720 n = n->outer;
6721 if (n == NULL)
6722 {
6723 as_bad (_("next outside of structured loop"));
6724 ignore_rest_of_line ();
6725 return;
6726 }
6727
add39d23 6728 buf = XNEWVEC (char, 20 + strlen (n->next));
3882b010 6729 ex[0] = TOLOWER (extent);
252b5132
RH		 6730 ex[1] = '\0';
6731 sprintf (buf, "bra%s %s", ex, n->next);
6732 mri_assemble (buf);
6733 free (buf);
6734
6735 if (flag_mri)
6736 {
6737 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6738 ++input_line_pointer;
6739 }
6740
6741 demand_empty_rest_of_line ();
6742}
6743
6744/* Handle the MRI FOR pseudo-op. */
6745
6746static void
31302357 6747s_mri_for (int qual)
252b5132
RH		 6748{
6749 const char *varstart, *varstop;
6750 const char *initstart, *initstop;
6751 const char *endstart, *endstop;
6752 const char *bystart, *bystop;
6753 int up;
6754 int by;
6755 int extent;
6756 struct mri_control_info *n;
6757 char *buf;
6758 char *s;
6759 char ex[2];
6760
6761 /* The syntax is
6762 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6763 */
6764
6765 SKIP_WHITESPACE ();
6766 varstart = input_line_pointer;
6767
6768 /* Look for the '='. */
6769 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6770 && *input_line_pointer != '=')
6771 ++input_line_pointer;
6772 if (*input_line_pointer != '=')
6773 {
6774 as_bad (_("missing ="));
6775 ignore_rest_of_line ();
6776 return;
6777 }
6778
6779 varstop = input_line_pointer;
6780 if (varstop > varstart
6781 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6782 --varstop;
6783
6784 ++input_line_pointer;
6785
6786 initstart = input_line_pointer;
6787
6788 /* Look for TO or DOWNTO. */
6789 up = 1;
6790 initstop = NULL;
6791 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6792 {
6793 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6794 && ! is_part_of_name (input_line_pointer[2]))
6795 {
6796 initstop = input_line_pointer;
6797 input_line_pointer += 2;
6798 break;
6799 }
6800 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6801 && ! is_part_of_name (input_line_pointer[6]))
6802 {
6803 initstop = input_line_pointer;
6804 up = 0;
6805 input_line_pointer += 6;
6806 break;
6807 }
6808 ++input_line_pointer;
6809 }
6810 if (initstop == NULL)
6811 {
6812 as_bad (_("missing to or downto"));
6813 ignore_rest_of_line ();
6814 return;
6815 }
6816 if (initstop > initstart
6817 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6818 --initstop;
6819
6820 SKIP_WHITESPACE ();
6821 endstart = input_line_pointer;
6822
6823 /* Look for BY or DO. */
6824 by = 0;
6825 endstop = NULL;
6826 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6827 {
6828 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6829 && ! is_part_of_name (input_line_pointer[2]))
6830 {
6831 endstop = input_line_pointer;
6832 by = 1;
6833 input_line_pointer += 2;
6834 break;
6835 }
6836 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6837 && (input_line_pointer[2] == '.'
6838 || ! is_part_of_name (input_line_pointer[2])))
6839 {
6840 endstop = input_line_pointer;
6841 input_line_pointer += 2;
6842 break;
6843 }
6844 ++input_line_pointer;
6845 }
6846 if (endstop == NULL)
6847 {
6848 as_bad (_("missing do"));
6849 ignore_rest_of_line ();
6850 return;
6851 }
6852 if (endstop > endstart
6853 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6854 --endstop;
6855
6856 if (! by)
6857 {
6858 bystart = "#1";
6859 bystop = bystart + 2;
6860 }
6861 else
6862 {
6863 SKIP_WHITESPACE ();
6864 bystart = input_line_pointer;
6865
6866 /* Look for DO. */
6867 bystop = NULL;
6868 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6869 {
6870 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6871 && (input_line_pointer[2] == '.'
6872 || ! is_part_of_name (input_line_pointer[2])))
6873 {
6874 bystop = input_line_pointer;
6875 input_line_pointer += 2;
6876 break;
6877 }
6878 ++input_line_pointer;
6879 }
6880 if (bystop == NULL)
6881 {
6882 as_bad (_("missing do"));
6883 ignore_rest_of_line ();
6884 return;
6885 }
6886 if (bystop > bystart
6887 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6888 --bystop;
6889 }
6890
6891 if (*input_line_pointer != '.')
6892 extent = '\0';
6893 else
6894 {
6895 extent = input_line_pointer[1];
6896 input_line_pointer += 2;
6897 }
6898
6899 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 6900 n = push_mri_control (mri_for);
6901
add39d23 6902 buf = XNEWVEC (char, 50 + (input_line_pointer - varstart));
252b5132 6903
36759679 6904 /* Move init,var. */
252b5132
RH		 6905 s = buf;
6906 *s++ = 'm';
6907 *s++ = 'o';
6908 *s++ = 'v';
6909 *s++ = 'e';
6910 if (qual != '\0')
3882b010 6911 *s++ = TOLOWER (qual);
252b5132
RH		 6912 *s++ = ' ';
6913 memcpy (s, initstart, initstop - initstart);
6914 s += initstop - initstart;
6915 *s++ = ',';
6916 memcpy (s, varstart, varstop - varstart);
6917 s += varstop - varstart;
6918 *s = '\0';
6919 mri_assemble (buf);
6920
6921 colon (n->top);
6922
36759679 6923 /* cmp end,var. */
252b5132
RH		 6924 s = buf;
6925 *s++ = 'c';
6926 *s++ = 'm';
6927 *s++ = 'p';
6928 if (qual != '\0')
3882b010 6929 *s++ = TOLOWER (qual);
252b5132
RH		 6930 *s++ = ' ';
6931 memcpy (s, endstart, endstop - endstart);
6932 s += endstop - endstart;
6933 *s++ = ',';
6934 memcpy (s, varstart, varstop - varstart);
6935 s += varstop - varstart;
6936 *s = '\0';
6937 mri_assemble (buf);
6938
36759679 6939 /* bcc bottom. */
3882b010 6940 ex[0] = TOLOWER (extent);
252b5132
RH		 6941 ex[1] = '\0';
6942 if (up)
6943 sprintf (buf, "blt%s %s", ex, n->bottom);
6944 else
6945 sprintf (buf, "bgt%s %s", ex, n->bottom);
6946 mri_assemble (buf);
6947
6948 /* Put together the add or sub instruction used by ENDF. */
6949 s = buf;
6950 if (up)
6951 strcpy (s, "add");
6952 else
6953 strcpy (s, "sub");
6954 s += 3;
6955 if (qual != '\0')
3882b010 6956 *s++ = TOLOWER (qual);
252b5132
RH		 6957 *s++ = ' ';
6958 memcpy (s, bystart, bystop - bystart);
6959 s += bystop - bystart;
6960 *s++ = ',';
6961 memcpy (s, varstart, varstop - varstart);
6962 s += varstop - varstart;
6963 *s = '\0';
6964 n->incr = buf;
6965
6966 if (flag_mri)
6967 {
6968 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6969 ++input_line_pointer;
6970 }
6971
6972 demand_empty_rest_of_line ();
6973}
6974
6975/* Handle the MRI ENDF pseudo-op. */
6976
6977static void
31302357 6978s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6979{
6980 if (mri_control_stack == NULL
6981 || mri_control_stack->type != mri_for)
6982 {
6983 as_bad (_("endf without for"));
6984 ignore_rest_of_line ();
6985 return;
6986 }
6987
6988 colon (mri_control_stack->next);
6989
6990 mri_assemble (mri_control_stack->incr);
6991
6992 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6993 mri_assemble (mri_control_stack->incr);
6994
6995 free (mri_control_stack->incr);
6996
6997 colon (mri_control_stack->bottom);
6998
6999 pop_mri_control ();
7000
7001 if (flag_mri)
7002 {
7003 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7004 ++input_line_pointer;
7005 }
7006
7007 demand_empty_rest_of_line ();
7008}
7009
7010/* Handle the MRI REPEAT pseudo-op. */
7011
7012static void
31302357 7013s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7014{
7015 struct mri_control_info *n;
7016
7017 n = push_mri_control (mri_repeat);
7018 colon (n->top);
7019 if (flag_mri)
7020 {
7021 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7022 ++input_line_pointer;
7023 }
7024 demand_empty_rest_of_line ();
7025}
7026
7027/* Handle the MRI UNTIL pseudo-op. */
7028
7029static void
31302357 7030s_mri_until (int qual)
252b5132
RH		 7031{
7032 char *s;
7033
7034 if (mri_control_stack == NULL
7035 || mri_control_stack->type != mri_repeat)
7036 {
7037 as_bad (_("until without repeat"));
7038 ignore_rest_of_line ();
7039 return;
7040 }
7041
7042 colon (mri_control_stack->next);
7043
7044 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7045 ;
7046
7047 parse_mri_control_expression (s, qual, (const char *) NULL,
7048 mri_control_stack->top, '\0');
7049
7050 colon (mri_control_stack->bottom);
7051
7052 input_line_pointer = s;
7053
7054 pop_mri_control ();
7055
7056 if (flag_mri)
7057 {
7058 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7059 ++input_line_pointer;
7060 }
7061
7062 demand_empty_rest_of_line ();
7063}
7064
7065/* Handle the MRI WHILE pseudo-op. */
7066
7067static void
31302357 7068s_mri_while (int qual)
252b5132
RH		 7069{
7070 char *s;
7071
7072 struct mri_control_info *n;
7073
7074 s = input_line_pointer;
e1f44d10
NC		 7075 /* We only accept '*' as introduction of comments if preceded by white space
7076 or at first column of a line (I think this can't actually happen here?)
7077 This is important when assembling:
7078 while d0 <ne> 12(a0,d0*2) do
36759679 7079 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 7080 while (! (is_end_of_line[(unsigned char) *s]
7081 || (flag_mri
7082 && *s == '*'
7083 && (s == input_line_pointer
7084 || *(s-1) == ' '
7085 || *(s-1) == '\t'))))
252b5132
RH		 7086 s++;
7087 --s;
7088 while (*s == ' ' || *s == '\t')
7089 --s;
7090 if (s - input_line_pointer > 1
7091 && s[-1] == '.')
7092 s -= 2;
7093 if (s - input_line_pointer < 2
7094 || strncasecmp (s - 1, "DO", 2) != 0)
7095 {
7096 as_bad (_("missing do"));
7097 ignore_rest_of_line ();
7098 return;
7099 }
7100
7101 n = push_mri_control (mri_while);
7102
7103 colon (n->next);
7104
7105 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7106 s[1] == '.' ? s[2] : '\0');
7107
7108 input_line_pointer = s + 1;
7109 if (*input_line_pointer == '.')
7110 input_line_pointer += 2;
7111
7112 if (flag_mri)
7113 {
7114 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7115 ++input_line_pointer;
7116 }
7117
7118 demand_empty_rest_of_line ();
7119}
7120
7121/* Handle the MRI ENDW pseudo-op. */
7122
7123static void
31302357 7124s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7125{
7126 char *buf;
7127
7128 if (mri_control_stack == NULL
7129 || mri_control_stack->type != mri_while)
7130 {
7131 as_bad (_("endw without while"));
7132 ignore_rest_of_line ();
7133 return;
7134 }
7135
add39d23 7136 buf = XNEWVEC (char, 20 + strlen (mri_control_stack->next));
252b5132
RH		 7137 sprintf (buf, "bra %s", mri_control_stack->next);
7138 mri_assemble (buf);
7139 free (buf);
7140
7141 colon (mri_control_stack->bottom);
7142
7143 pop_mri_control ();
7144
7145 if (flag_mri)
7146 {
7147 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7148 ++input_line_pointer;
7149 }
7150
7151 demand_empty_rest_of_line ();
7152}
7153\f
266abb8f
NS		 7154/* Parse a .cpu directive. */
7155
7156static void
7157s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7158{
7159 char saved_char;
7160 char *name;
7161
7162 if (initialized)
7163 {
7164 as_bad (_("already assembled instructions"));
7165 ignore_rest_of_line ();
7166 return;
7167 }
3739860c 7168
266abb8f
NS		 7169 name = input_line_pointer;
7170 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7171 input_line_pointer++;
7172 saved_char = *input_line_pointer;
7173 *input_line_pointer = 0;
7174
7175 m68k_set_cpu (name, 1, 0);
3739860c 7176
266abb8f
NS		 7177 *input_line_pointer = saved_char;
7178 demand_empty_rest_of_line ();
7179 return;
7180}
7181
7182/* Parse a .arch directive. */
7183
7184static void
7185s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7186{
7187 char saved_char;
7188 char *name;
7189
7190 if (initialized)
7191 {
7192 as_bad (_("already assembled instructions"));
7193 ignore_rest_of_line ();
7194 return;
7195 }
3739860c 7196
266abb8f
NS		 7197 name = input_line_pointer;
7198 while (*input_line_pointer && *input_line_pointer != ','
7199 && !ISSPACE (*input_line_pointer))
7200 input_line_pointer++;
7201 saved_char = *input_line_pointer;
7202 *input_line_pointer = 0;
7203
7204 if (m68k_set_arch (name, 1, 0))
7205 {
7206 /* Scan extensions. */
7207 do
7208 {
7209 *input_line_pointer++ = saved_char;
7210 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7211 break;
7212 name = input_line_pointer;
7213 while (*input_line_pointer && *input_line_pointer != ','
7214 && !ISSPACE (*input_line_pointer))
7215 input_line_pointer++;
7216 saved_char = *input_line_pointer;
7217 *input_line_pointer = 0;
7218 }
7219 while (m68k_set_extension (name, 1, 0));
7220 }
3739860c 7221
266abb8f
NS		 7222 *input_line_pointer = saved_char;
7223 demand_empty_rest_of_line ();
7224 return;
7225}
7226\f
7227/* Lookup a cpu name in TABLE and return the slot found. Return NULL
7228 if none is found, the caller is responsible for emitting an error
7229 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7230 cpu name, if it begins with a '6' (possibly skipping an intervening
7231 'c'. We also allow a 'c' in the same place. if NEGATED is
7232 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7233 the option is indeed negated. */
7234
7235static const struct m68k_cpu *
7236m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7237 int allow_m, int *negated)
7238{
7239 /* allow negated value? */
7240 if (negated)
7241 {
7242 *negated = 0;
7243
7244 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7245 {
7246 arg += 3;
7247 *negated = 1;
7248 }
7249 }
3739860c 7250
266abb8f
NS		 7251 /* Remove 'm' or 'mc' prefix from 68k variants. */
7252 if (allow_m)
7253 {
7254 if (arg[0] == 'm')
7255 {
7256 if (arg[1] == '6')
7257 arg += 1;
7258 else if (arg[1] == 'c' && arg[2] == '6')
7259 arg += 2;
7260 }
7261 }
7262 else if (arg[0] == 'c' && arg[1] == '6')
7263 arg += 1;
7264
7265 for (; table->name; table++)
7266 if (!strcmp (arg, table->name))
2da12c60
NS		 7267 {
7268 if (table->alias < -1 || table->alias > 1)
7269 as_bad (_("`%s' is deprecated, use `%s'"),
7270 table->name, table[table->alias < 0 ? 1 : -1].name);
7271 return table;
7272 }
266abb8f
NS		 7273 return 0;
7274}
7275
bfbba8e4 7276/* Set the cpu, issuing errors if it is unrecognized. */
266abb8f
NS		 7277
7278static int
7279m68k_set_cpu (char const *name, int allow_m, int silent)
7280{
7281 const struct m68k_cpu *cpu;
7282
7283 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7284
7285 if (!cpu)
7286 {
7287 if (!silent)
7288 as_bad (_("cpu `%s' unrecognized"), name);
7289 return 0;
7290 }
266abb8f
NS		 7291 selected_cpu = cpu;
7292 return 1;
7293}
7294
bfbba8e4 7295/* Set the architecture, issuing errors if it is unrecognized. */
266abb8f
NS		 7296
7297static int
7298m68k_set_arch (char const *name, int allow_m, int silent)
7299{
7300 const struct m68k_cpu *arch;
7301
7302 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7303
7304 if (!arch)
7305 {
7306 if (!silent)
7307 as_bad (_("architecture `%s' unrecognized"), name);
7308 return 0;
7309 }
266abb8f
NS		 7310 selected_arch = arch;
7311 return 1;
7312}
7313
7314/* Set the architecture extension, issuing errors if it is
7315 unrecognized, or invalid */
7316
7317static int
7318m68k_set_extension (char const *name, int allow_m, int silent)
7319{
7320 int negated;
7321 const struct m68k_cpu *ext;
7322
7323 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7324
7325 if (!ext)
7326 {
7327 if (!silent)
7328 as_bad (_("extension `%s' unrecognized"), name);
7329 return 0;
7330 }
7331
7332 if (negated)
87298967
NS		 7333 not_current_architecture |= (ext->control_regs
7334 ? *(unsigned *)ext->control_regs: ext->arch);
266abb8f
NS		 7335 else
7336 current_architecture |= ext->arch;
7337 return 1;
7338}
7339
31302357
AS		 7340/* md_parse_option
7341 Invocation line includes a switch not recognized by the base assembler.
266abb8f 7342 */
252b5132 7343
5a38dc70 7344const char *md_shortopts = "lSA:m:kQ:V";
252b5132
RH		 7345
7346struct option md_longopts[] = {
7347#define OPTION_PIC (OPTION_MD_BASE)
7348 {"pic", no_argument, NULL, OPTION_PIC},
7349#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7350 {"register-prefix-optional", no_argument, NULL,
7351 OPTION_REGISTER_PREFIX_OPTIONAL},
7352#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7353 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7354#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7355 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7356#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7357 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7358#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7359 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7360#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7361 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7362#define OPTION_PCREL (OPTION_MD_BASE + 7)
7363 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7364 {NULL, no_argument, NULL, 0}
7365};
bc805888 7366size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7367
7368int
17b9d67d 7369md_parse_option (int c, const char *arg)
252b5132
RH		 7370{
7371 switch (c)
7372 {
7373 case 'l': /* -l means keep external to 2 bit offset
36759679 7374 rather than 16 bit one. */
252b5132
RH		 7375 flag_short_refs = 1;
7376 break;
7377
7378 case 'S': /* -S means that jbsr's always turn into
7379 jsr's. */
7380 flag_long_jumps = 1;
7381 break;
7382
28e7409f
NC		 7383 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7384 branches into absolute jumps. */
7385 flag_keep_pcrel = 1;
7386 break;
7387
252b5132
RH		 7388 case OPTION_PIC:
7389 case 'k':
7390 flag_want_pic = 1;
36759679 7391 break; /* -pic, Position Independent Code. */
252b5132
RH		 7392
7393 case OPTION_REGISTER_PREFIX_OPTIONAL:
7394 flag_reg_prefix_optional = 1;
7395 reg_prefix_optional_seen = 1;
7396 break;
7397
7398 /* -V: SVR4 argument to print version ID. */
7399 case 'V':
7400 print_version_id ();
7401 break;
7402
7403 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7404 should be emitted or not. FIXME: Not implemented. */
7405 case 'Q':
7406 break;
7407
7408 case OPTION_BITWISE_OR:
7409 {
7410 char *n, *t;
7411 const char *s;
7412
add39d23 7413 n = XNEWVEC (char, strlen (m68k_comment_chars) + 1);
252b5132
RH		 7414 t = n;
7415 for (s = m68k_comment_chars; *s != '\0'; s++)
7416 if (*s != '|')
7417 *t++ = *s;
7418 *t = '\0';
7419 m68k_comment_chars = n;
7420 }
7421 break;
7422
7423 case OPTION_BASE_SIZE_DEFAULT_16:
7424 m68k_index_width_default = SIZE_WORD;
7425 break;
7426
7427 case OPTION_BASE_SIZE_DEFAULT_32:
7428 m68k_index_width_default = SIZE_LONG;
7429 break;
7430
7431 case OPTION_DISP_SIZE_DEFAULT_16:
7432 m68k_rel32 = 0;
7433 m68k_rel32_from_cmdline = 1;
7434 break;
7435
7436 case OPTION_DISP_SIZE_DEFAULT_32:
7437 m68k_rel32 = 1;
7438 m68k_rel32_from_cmdline = 1;
7439 break;
7440
266abb8f
NS		 7441 case 'A':
7442#if WARN_DEPRECATED
7443 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7444 arg, arg));
7445#endif
7446 /* Intentional fall-through. */
7447 case 'm':
d34049e8 7448 if (startswith (arg, "arch="))
266abb8f 7449 m68k_set_arch (arg + 5, 1, 0);
d34049e8 7450 else if (startswith (arg, "cpu="))
266abb8f
NS		 7451 m68k_set_cpu (arg + 4, 1, 0);
7452 else if (m68k_set_extension (arg, 0, 1))
7453 ;
0b2e31dc
NS		 7454 else if (m68k_set_arch (arg, 0, 1))
7455 ;
266abb8f
NS		 7456 else if (m68k_set_cpu (arg, 0, 1))
7457 ;
7458 else
7459 return 0;
7460 break;
7461
252b5132
RH		 7462 default:
7463 return 0;
7464 }
7465
7466 return 1;
7467}
7468
266abb8f
NS		 7469/* Setup tables from the selected arch and/or cpu */
7470
7471static void
7472m68k_init_arch (void)
7473{
266abb8f
NS		 7474 if (not_current_architecture & current_architecture)
7475 {
7476 as_bad (_("architecture features both enabled and disabled"));
7477 not_current_architecture &= ~current_architecture;
7478 }
7479 if (selected_arch)
2da12c60
NS		 7480 {
7481 current_architecture |= selected_arch->arch;
7482 control_regs = selected_arch->control_regs;
7483 }
0b2e31dc
NS		 7484 else
7485 current_architecture |= selected_cpu->arch;
3739860c 7486
2da12c60
NS		 7487 current_architecture &= ~not_current_architecture;
7488
377260ba
NS		 7489 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7490 {
7491 /* Determine which float is really meant. */
7492 if (current_architecture & (m68k_mask & ~m68881))
7493 current_architecture ^= cfloat;
7494 else
7495 current_architecture ^= m68881;
7496 }
7497
0b2e31dc 7498 if (selected_cpu)
266abb8f 7499 {
2da12c60 7500 control_regs = selected_cpu->control_regs;
0b2e31dc 7501 if (current_architecture & ~selected_cpu->arch)
266abb8f 7502 {
0b2e31dc
NS		 7503 as_bad (_("selected processor does not have all features of selected architecture"));
7504 current_architecture
7505 = selected_cpu->arch & ~not_current_architecture;
266abb8f
NS		 7506 }
7507 }
266abb8f 7508
266abb8f
NS		 7509 if ((current_architecture & m68k_mask)
7510 && (current_architecture & ~m68k_mask))
7511 {
7512 as_bad (_ ("m68k and cf features both selected"));
0b2e31dc 7513 if (current_architecture & m68k_mask)
266abb8f
NS		 7514 current_architecture &= m68k_mask;
7515 else
7516 current_architecture &= ~m68k_mask;
7517 }
3739860c 7518
266abb8f
NS		 7519 /* Permit m68881 specification with all cpus; those that can't work
7520 with a coprocessor could be doing emulation. */
7521 if (current_architecture & m68851)
7522 {
7523 if (current_architecture & m68040)
7524 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7525 }
7526 /* What other incompatibilities could we check for? */
7527
266abb8f
NS		 7528 if (cpu_of_arch (current_architecture) < m68020
7529 || arch_coldfire_p (current_architecture))
7530 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3739860c 7531
266abb8f
NS		 7532 initialized = 1;
7533}
7534
252b5132 7535void
31302357 7536md_show_usage (FILE *stream)
252b5132 7537{
76f57f3a 7538 const char *default_cpu = TARGET_CPU;
f1f5ef86 7539 int i;
76f57f3a 7540
8a104df9 7541 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7542 if (*default_cpu == 'm')
7543 default_cpu++;
266abb8f 7544 for (i = 0; m68k_cpus[i].name; i++)
76f57f3a 7545 {
266abb8f 7546 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
76f57f3a 7547 {
2da12c60
NS		 7548 while (m68k_cpus[i].alias > 0)
7549 i--;
7550 while (m68k_cpus[i].alias < 0)
7551 i++;
7552 default_cpu = m68k_cpus[i].name;
76f57f3a
JT		 7553 }
7554 }
7555
bc805888 7556 fprintf (stream, _("\
266abb8f
NS		 7557-march=<arch> set architecture\n\
7558-mcpu=<cpu> set cpu [default %s]\n\
7559"), default_cpu);
7560 for (i = 0; m68k_extensions[i].name; i++)
7561 fprintf (stream, _("\
33eaf5de 7562-m[no-]%-16s enable/disable %s architecture extension\n\
0b2e31dc
NS		 7563"), m68k_extensions[i].name,
7564 m68k_extensions[i].alias > 0 ? " ColdFire"
7565 : m68k_extensions[i].alias < 0 ? " m68k" : "");
3739860c 7566
bc805888 7567 fprintf (stream, _("\
266abb8f 7568-l use 1 word for refs to undefined symbols [default 2]\n\
252b5132
RH		 7569-pic, -k generate position independent code\n\
7570-S turn jbsr into jsr\n\
28e7409f 7571--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7572--register-prefix-optional\n\
7573 recognize register names without prefix character\n\
266abb8f 7574--bitwise-or do not treat `|' as a comment character\n\
252b5132
RH		 7575--base-size-default-16 base reg without size is 16 bits\n\
7576--base-size-default-32 base reg without size is 32 bits (default)\n\
7577--disp-size-default-16 displacement with unknown size is 16 bits\n\
266abb8f
NS		 7578--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7579"));
3739860c 7580
266abb8f
NS		 7581 fprintf (stream, _("Architecture variants are: "));
7582 for (i = 0; m68k_archs[i].name; i++)
7583 {
7584 if (i)
7585 fprintf (stream, " | ");
87298967 7586 fprintf (stream, "%s", m68k_archs[i].name);
266abb8f
NS		 7587 }
7588 fprintf (stream, "\n");
7589
7590 fprintf (stream, _("Processor variants are: "));
7591 for (i = 0; m68k_cpus[i].name; i++)
7592 {
7593 if (i)
7594 fprintf (stream, " | ");
87298967 7595 fprintf (stream, "%s", m68k_cpus[i].name);
266abb8f
NS		 7596 }
7597 fprintf (stream, _("\n"));
252b5132
RH		 7598}
7599\f
7600#ifdef TEST2
7601
7602/* TEST2: Test md_assemble() */
36759679
NC		 7603/* Warning, this routine probably doesn't work anymore. */
7604int
31302357 7605main (void)
252b5132
RH		 7606{
7607 struct m68k_it the_ins;
7608 char buf[120];
7609 char *cp;
7610 int n;
7611
7612 m68k_ip_begin ();
7613 for (;;)
7614 {
7615 if (!gets (buf) || !*buf)
7616 break;
7617 if (buf[0] == '|' || buf[1] == '.')
7618 continue;
7619 for (cp = buf; *cp; cp++)
7620 if (*cp == '\t')
7621 *cp = ' ';
7622 if (is_label (buf))
7623 continue;
7624 memset (&the_ins, '\0', sizeof (the_ins));
7625 m68k_ip (&the_ins, buf);
7626 if (the_ins.error)
7627 {
7628 printf (_("Error %s in %s\n"), the_ins.error, buf);
7629 }
7630 else
7631 {
7632 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7633 for (n = 0; n < the_ins.numo; n++)
7634 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7635 printf (" ");
7636 print_the_insn (&the_ins.opcode[0], stdout);
7637 (void) putchar ('\n');
7638 }
7639 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7640 {
7641 if (the_ins.operands[n].error)
7642 {
7643 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7644 continue;
7645 }
31302357
AS		 7646 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7647 the_ins.operands[n].reg);
252b5132 7648 if (the_ins.operands[n].b_const)
31302357
AS		 7649 printf ("Constant: '%.*s', ",
7650 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7651 the_ins.operands[n].b_const);
7652 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7653 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7654 if (the_ins.operands[n].b_iadd)
31302357
AS		 7655 printf ("Iadd: '%.*s',",
7656 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7657 the_ins.operands[n].b_iadd);
7658 putchar ('\n');
252b5132
RH		 7659 }
7660 }
7661 m68k_ip_end ();
7662 return 0;
7663}
7664
31302357
AS		 7665int
7666is_label (char *str)
252b5132
RH		 7667{
7668 while (*str == ' ')
7669 str++;
7670 while (*str && *str != ' ')
7671 str++;
7672 if (str[-1] == ':' || str[1] == '=')
7673 return 1;
7674 return 0;
7675}
7676
7677#endif
7678
7679/* Possible states for relaxation:
7680
7681 0 0 branch offset byte (bra, etc)
7682 0 1 word
7683 0 2 long
7684
7685 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7686 1 1 word
7687 1 2 long
7688
7689 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7690 2 1 word-long
7691 2 2 long-word
7692 2 3 long-long
7693
7694 */
7695
7696/* We have no need to default values of symbols. */
7697
252b5132 7698symbolS *
31302357 7699md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7700{
7701 return 0;
7702}
7703
7704/* Round up a section size to the appropriate boundary. */
7705valueT
31302357 7706md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 7707{
252b5132
RH		 7708 return size;
7709}
7710
7711/* Exactly what point is a PC-relative offset relative TO?
7712 On the 68k, it is relative to the address of the first extension
7713 word. The difference between the addresses of the offset and the
92774660 7714 first extension word is stored in fx_pcrel_adjust. */
252b5132 7715long
31302357 7716md_pcrel_from (fixS *fixP)
252b5132
RH		 7717{
7718 int adjust;
7719
552c607f 7720 adjust = fixP->fx_pcrel_adjust;
252b5132
RH		 7721 if (adjust == 64)
7722 adjust = -1;
7723 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7724}
7725
8a104df9 7726void
31302357 7727m68k_elf_final_processing (void)
0d96863f 7728{
266abb8f 7729 unsigned flags = 0;
3739860c 7730
238d258f 7731 if (arch_coldfire_fpu (current_architecture))
266abb8f
NS		 7732 flags |= EF_M68K_CFV4E;
7733 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9 7734 if (cpu_of_arch (current_architecture) & cpu32)
3bdcfdf4
KH		 7735 flags |= EF_M68K_CPU32;
7736 else if (cpu_of_arch (current_architecture) & fido_a)
7737 flags |= EF_M68K_FIDO;
8a104df9
KH		 7738 else if ((cpu_of_arch (current_architecture) & m68000up)
7739 && !(cpu_of_arch (current_architecture) & m68020up))
266abb8f 7740 flags |= EF_M68K_M68000;
3739860c 7741
266abb8f
NS		 7742 if (current_architecture & mcfisa_a)
7743 {
0b2e31dc
NS		 7744 static const unsigned isa_features[][2] =
7745 {
9a2e615a 7746 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
c694fd50 7747 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
9a2e615a 7748 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
c694fd50
KH		 7749 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7750 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
9a2e615a 7751 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
8d100c32 7752 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
0b2e31dc
NS		 7753 {0,0},
7754 };
7755 static const unsigned mac_features[][2] =
7756 {
c694fd50
KH		 7757 {EF_M68K_CF_MAC, mcfmac},
7758 {EF_M68K_CF_EMAC, mcfemac},
0b2e31dc
NS		 7759 {0,0},
7760 };
7761 unsigned ix;
7762 unsigned pattern;
3739860c 7763
0b2e31dc 7764 pattern = (current_architecture
9a2e615a 7765 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
0b2e31dc
NS		 7766 for (ix = 0; isa_features[ix][1]; ix++)
7767 {
7768 if (pattern == isa_features[ix][1])
7769 {
7770 flags |= isa_features[ix][0];
7771 break;
7772 }
7773 }
7774 if (!isa_features[ix][1])
7775 {
7776 cf_bad:
7777 as_warn (_("Not a defined coldfire architecture"));
7778 }
7779 else
7780 {
7781 if (current_architecture & cfloat)
c694fd50 7782 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
266abb8f 7783
0b2e31dc
NS		 7784 pattern = current_architecture & (mcfmac|mcfemac);
7785 if (pattern)
7786 {
7787 for (ix = 0; mac_features[ix][1]; ix++)
7788 {
7789 if (pattern == mac_features[ix][1])
7790 {
7791 flags |= mac_features[ix][0];
7792 break;
7793 }
7794 }
7795 if (!mac_features[ix][1])
7796 goto cf_bad;
7797 }
7798 }
266abb8f
NS		 7799 }
7800 elf_elfheader (stdoutput)->e_flags |= flags;
0d96863f 7801}
cf869cce
NC		 7802
7803/* Parse @TLSLDO and return the desired relocation. */
7804static bfd_reloc_code_real_type
7805m68k_elf_suffix (char **str_p, expressionS *exp_p)
7806{
7807 char ident[20];
7808 char *str = *str_p;
7809 char *str2;
7810 int ch;
7811 int len;
7812
7813 if (*str++ != '@')
7814 return BFD_RELOC_UNUSED;
7815
7816 for (ch = *str, str2 = ident;
7817 (str2 < ident + sizeof (ident) - 1
7818 && (ISALNUM (ch) || ch == '@'));
7819 ch = *++str)
7820 {
7821 *str2++ = ch;
7822 }
7823
7824 *str2 = '\0';
7825 len = str2 - ident;
7826
d34049e8 7827 if (startswith (ident, "TLSLDO")
cf869cce
NC		 7828 && len == 6)
7829 {
7830 /* Now check for identifier@suffix+constant. */
7831 if (*str == '-' || *str == '+')
7832 {
7833 char *orig_line = input_line_pointer;
7834 expressionS new_exp;
7835
7836 input_line_pointer = str;
7837 expression (&new_exp);
7838 if (new_exp.X_op == O_constant)
7839 {
7840 exp_p->X_add_number += new_exp.X_add_number;
7841 str = input_line_pointer;
7842 }
7843
7844 if (&input_line_pointer != str_p)
7845 input_line_pointer = orig_line;
7846 }
7847 *str_p = str;
7848
7849 return BFD_RELOC_68K_TLS_LDO32;
7850 }
7851
7852 return BFD_RELOC_UNUSED;
7853}
7854
7855/* Handles .long <tls_symbol>+0x8000 debug info.
7856 Clobbers input_line_pointer, checks end-of-line.
7857 Adapted from tc-ppc.c:ppc_elf_cons. */
7858static void
7859m68k_elf_cons (int nbytes /* 4=.long */)
7860{
7861 if (is_it_end_of_statement ())
7862 {
7863 demand_empty_rest_of_line ();
7864 return;
7865 }
7866
7867 do
7868 {
7869 expressionS exp;
7870 bfd_reloc_code_real_type reloc;
7871
7872 expression (&exp);
7873 if (exp.X_op == O_symbol
7874 && *input_line_pointer == '@'
7875 && (reloc = m68k_elf_suffix (&input_line_pointer,
7876 &exp)) != BFD_RELOC_UNUSED)
7877 {
7878 reloc_howto_type *reloc_howto;
7879 int size;
7880
7881 reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc);
7882 size = bfd_get_reloc_size (reloc_howto);
7883
7884 if (size > nbytes)
7885 {
992a06ee
AM		 7886 as_bad (ngettext ("%s relocations do not fit in %u byte",
7887 "%s relocations do not fit in %u bytes",
7888 nbytes),
cf869cce
NC		 7889 reloc_howto->name, nbytes);
7890 }
7891 else
7892 {
7893 char *p;
7894 int offset;
7895
7896 p = frag_more (nbytes);
7897 offset = 0;
7898 if (target_big_endian)
7899 offset = nbytes - size;
7900 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
7901 &exp, 0, reloc);
7902 }
7903 }
7904 else
7905 emit_expr (&exp, (unsigned int) nbytes);
7906 }
7907 while (*input_line_pointer++ == ',');
7908
7909 /* Put terminator back into stream. */
7910 input_line_pointer--;
7911 demand_empty_rest_of_line ();
7912}
c04898f8 7913
85f7484a
PB		 7914/* Parse a .gnu_attribute directive. */
7915static void
7916m68k_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED)
7917{
7918 int tag = obj_elf_vendor_attribute (OBJ_ATTR_GNU);
7919
7920 /* Check validity of defined m68k tags. */
7921 if (tag == Tag_GNU_M68K_ABI_FP)
7922 {
7923 unsigned int val;
7924
7925 val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, tag);
7926
7927 if (tag == Tag_GNU_M68K_ABI_FP && val > 2)
7928 as_warn (_("unknown .gnu_attribute value"));
7929 }
7930}
7931
c04898f8 7932int
e0471c16 7933tc_m68k_regname_to_dw2regnum (const char *regname)
c04898f8
AS		 7934{
7935 unsigned int regnum;
7936 static const char *const regnames[] =
7937 {
7938 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7939 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7940 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7941 "pc"
7942 };
7943
7944 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7945 if (strcmp (regname, regnames[regnum]) == 0)
7946 return regnum;
7947
7948 return -1;
7949}
7950
7951void
7952tc_m68k_frame_initial_instructions (void)
7953{
7954 static int sp_regno = -1;
7955
7956 if (sp_regno < 0)
7957 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7958
7959 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7960 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7961}
909c7f9c
NC		 7962
7963/* Check and emit error if broken-word handling has failed to fix up a
7964 case-table. This is called from write.c, after doing everything it
7965 knows about how to handle broken words. */
7966
7967void
7968tc_m68k_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP)
7969{
7970 if (new_offset > 32767 || new_offset < -32768)
7971 as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line,
7972 _("Adjusted signed .word (%#lx) overflows: `switch'-statement too large."),
7973 (long) new_offset);
7974}
7975
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