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3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
65d2c7d3 | 2 | Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
efec4a28 DP |
39 | #include "itbl-ops.h" |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
3d3c5039 | 46 | |
739708fa KR |
47 | #ifdef OBJ_MAYBE_ELF |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
7cd06f44 | 49 | static int mips_output_flavor PARAMS ((void)); |
739708fa KR |
50 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } |
51 | #undef OBJ_PROCESS_STAB | |
52 | #undef OUTPUT_FLAVOR | |
53 | #undef S_GET_ALIGN | |
54 | #undef S_GET_SIZE | |
55 | #undef S_SET_ALIGN | |
56 | #undef S_SET_SIZE | |
57 | #undef TARGET_SYMBOL_FIELDS | |
58 | #undef obj_frob_file | |
cc5703cd | 59 | #undef obj_frob_file_after_relocs |
739708fa KR |
60 | #undef obj_frob_symbol |
61 | #undef obj_pop_insert | |
62 | #undef obj_sec_sym_ok_for_reloc | |
a3e8c5b7 | 63 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES |
739708fa KR |
64 | |
65 | #include "obj-elf.h" | |
66 | /* Fix any of them that we actually care about. */ | |
67 | #undef OUTPUT_FLAVOR | |
68 | #define OUTPUT_FLAVOR mips_output_flavor() | |
69 | #endif | |
70 | ||
71 | #if defined (OBJ_ELF) | |
f2a663d3 | 72 | #include "elf/mips.h" |
1dc1e798 | 73 | #endif |
f2a663d3 | 74 | |
739708fa | 75 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 76 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
77 | #define ECOFF_DEBUGGING 0 |
78 | #endif | |
79 | ||
22ba90ce ILT |
80 | #include "ecoff.h" |
81 | ||
a8aed9dd | 82 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 83 | static char *mips_regmask_frag; |
a8aed9dd | 84 | #endif |
f2a663d3 | 85 | |
3d3c5039 | 86 | #define AT 1 |
cc5703cd | 87 | #define TREG 24 |
9226253a | 88 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
89 | #define KT0 26 |
90 | #define KT1 27 | |
670a50eb | 91 | #define GP 28 |
9226253a ILT |
92 | #define SP 29 |
93 | #define FP 30 | |
3d3c5039 ILT |
94 | #define RA 31 |
95 | ||
cc5703cd ILT |
96 | #define ILLEGAL_REG (32) |
97 | ||
af942793 SS |
98 | /* Allow override of standard little-endian ECOFF format. */ |
99 | ||
100 | #ifndef ECOFF_LITTLE_FORMAT | |
101 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
102 | #endif | |
103 | ||
1dc1e798 | 104 | extern int target_big_endian; |
88225433 | 105 | |
7f9880e5 | 106 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
6fd819cf GRK |
107 | 32 bit ABI. This has no meaning for ECOFF. |
108 | Note that the default is always 32 bit, even if "configured" for | |
109 | 64 bit [e.g. --target=mips64-elf]. */ | |
7f9880e5 ILT |
110 | static int mips_64; |
111 | ||
04cb3372 | 112 | /* The default target format to use. */ |
1dc1e798 KR |
113 | const char * |
114 | mips_target_format () | |
115 | { | |
116 | switch (OUTPUT_FLAVOR) | |
117 | { | |
118 | case bfd_target_aout_flavour: | |
119 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
120 | case bfd_target_ecoff_flavour: | |
af942793 | 121 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; |
1dc1e798 | 122 | case bfd_target_elf_flavour: |
7f9880e5 ILT |
123 | return (target_big_endian |
124 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
125 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
126 | default: |
127 | abort (); | |
a3e8c5b7 | 128 | return NULL; |
1dc1e798 KR |
129 | } |
130 | } | |
04cb3372 | 131 | |
d2c71068 | 132 | /* The name of the readonly data section. */ |
1dc1e798 KR |
133 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
134 | ? ".data" \ | |
135 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
136 | ? ".rdata" \ | |
137 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
138 | ? ".rodata" \ | |
139 | : (abort (), "")) | |
d2c71068 | 140 | |
3c83da8a JW |
141 | /* This is the set of options which may be modified by the .set |
142 | pseudo-op. We use a struct so that .set push and .set pop are more | |
de484a06 | 143 | reliable. */ |
3c83da8a JW |
144 | |
145 | struct mips_set_options | |
146 | { | |
147 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 | |
148 | if it has not been initialized. Changed by `.set mipsN', and the | |
149 | -mipsN command line option, and the default CPU. */ | |
150 | int isa; | |
151 | /* Whether we are assembling for the mips16 processor. 0 if we are | |
152 | not, 1 if we are, and -1 if the value has not been initialized. | |
153 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
154 | -nomips16 command line options, and the default CPU. */ | |
155 | int mips16; | |
156 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
157 | reorder' and `.set noreorder'. */ | |
158 | int noreorder; | |
159 | /* Non-zero if we should not permit the $at ($1) register to be used | |
160 | in instructions. Changed by `.set at' and `.set noat'. */ | |
161 | int noat; | |
162 | /* Non-zero if we should warn when a macro instruction expands into | |
163 | more than one machine instruction. Changed by `.set nomacro' and | |
164 | `.set macro'. */ | |
165 | int warn_about_macros; | |
166 | /* Non-zero if we should not move instructions. Changed by `.set | |
167 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
168 | int nomove; | |
169 | /* Non-zero if we should not optimize branches by moving the target | |
170 | of the branch into the delay slot. Actually, we don't perform | |
171 | this optimization anyhow. Changed by `.set bopt' and `.set | |
172 | nobopt'. */ | |
173 | int nobopt; | |
174 | /* Non-zero if we should not autoextend mips16 instructions. | |
175 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
176 | int noautoextend; | |
177 | }; | |
178 | ||
179 | /* This is the struct we use to hold the current set of options. Note | |
180 | that we must set the isa and mips16 fields to -1 to indicate that | |
181 | they have not been initialized. */ | |
182 | ||
183 | static struct mips_set_options mips_opts = { -1, -1 }; | |
184 | ||
1aa6938e ILT |
185 | /* These variables are filled in with the masks of registers used. |
186 | The object format code reads them and puts them in the appropriate | |
187 | place. */ | |
188 | unsigned long mips_gprmask; | |
189 | unsigned long mips_cprmask[4]; | |
190 | ||
1051c97f ILT |
191 | /* MIPS ISA we are using for this output file. */ |
192 | static int file_mips_isa; | |
193 | ||
8c63448a | 194 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 195 | static int mips_cpu = -1; |
8c63448a | 196 | |
02650bd0 GRK |
197 | /* The argument of the -mabi= flag. */ |
198 | static char* mips_abi_string = 0; | |
199 | ||
d95b7328 GRK |
200 | /* Wether we should mark the file EABI64 or EABI32. */ |
201 | static int mips_eabi64 = 0; | |
202 | ||
c625fc23 | 203 | |
de484a06 JB |
204 | /* Whether the processor uses hardware interlocks to protect |
205 | reads from the HI and LO registers, and thus does not | |
206 | require nops to be inserted. | |
aa2e0460 | 207 | |
de484a06 JB |
208 | FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO: |
209 | -mcpu=FOO schedules for FOO, but still produces code that meets the | |
210 | requirements of MIPS ISA I. For example, it won't generate any | |
211 | FOO-specific instructions, and it will still assume that any | |
212 | scheduling hazards described in MIPS ISA I are there, even if FOO | |
213 | has interlocks. -mFOO gives GCC permission to generate code that | |
214 | will only run on a FOO; it will generate FOO-specific instructions, | |
215 | and assume interlocks provided by a FOO. | |
276c2d7d | 216 | |
de484a06 JB |
217 | However, GAS currently doesn't make this distinction; before Jan 28 |
218 | 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's | |
219 | assumptions. The GCC driver passes these flags through to GAS, so | |
220 | if GAS actually does anything that doesn't meet MIPS ISA I with | |
221 | -mFOO, then GCC's -mcpu=FOO flag isn't going to work. | |
5c6f5923 | 222 | |
de484a06 JB |
223 | And furthermore, it did not assume that -mFOO implied -mcpu=FOO, |
224 | which seems senseless --- why generate code which will only run on | |
225 | a FOO, but schedule for something else? | |
42444087 | 226 | |
de484a06 | 227 | So now, at least, -mcpu=FOO and -mFOO are exactly equivalent. |
4e96260f | 228 | |
de484a06 | 229 | -- Jim Blandy <jimb@cygnus.com> */ |
622b1860 | 230 | |
de484a06 | 231 | #define hilo_interlocks (mips_cpu == 4010 \ |
4ebda395 | 232 | /* start-sanitize-tx49 */ \ |
de484a06 | 233 | || mips_cpu == 4900 \ |
4ebda395 | 234 | /* end-sanitize-tx49 */ \ |
2d035a50 GRK |
235 | /* start-sanitize-vr4320 */ \ |
236 | || mips_cpu == 4320 \ | |
237 | /* end-sanitize-vr4320 */ \ | |
be294de6 | 238 | /* start-sanitize-r5900 */ \ |
de484a06 | 239 | || mips_cpu == 5900 \ |
be294de6 | 240 | /* end-sanitize-r5900 */ \ |
4ebda395 | 241 | ) |
5c6f5923 | 242 | |
a3e8c5b7 ILT |
243 | /* Whether the processor uses hardware interlocks to protect reads |
244 | from the GPRs, and thus does not require nops to be inserted. */ | |
3b35597c JL |
245 | #define gpr_interlocks \ |
246 | (mips_opts.isa >= 2 \ | |
247 | /* start-sanitize-cygnus */ \ | |
de484a06 | 248 | || mips_cpu == 5400 \ |
3b35597c JL |
249 | /* end-sanitize-cygnus */ \ |
250 | /* start-sanitize-r5900 */ \ | |
de484a06 | 251 | || mips_cpu == 5900 \ |
3b35597c | 252 | /* end-sanitize-r5900 */ \ |
de484a06 | 253 | || mips_cpu == 3900) |
e532b44c | 254 | |
5c6f5923 | 255 | /* As with other "interlocks" this is used by hardware that has FP |
344a8d61 | 256 | (co-processor) interlocks. */ |
efec4a28 | 257 | /* Itbl support may require additional care here. */ |
2d035a50 GRK |
258 | #define cop_interlocks (mips_cpu == 4300 \ |
259 | /* start-sanitize-vr4320 */ \ | |
260 | || mips_cpu == 4320 \ | |
261 | /* end-sanitize-vr4320 */ \ | |
6b34ac5a | 262 | /* start-sanitize-cygnus */ \ |
2d035a50 | 263 | || mips_cpu == 5400 \ |
6b34ac5a | 264 | /* end-sanitize-cygnus */ \ |
2d035a50 | 265 | ) |
344a8d61 | 266 | |
d9aba805 ILT |
267 | /* MIPS PIC level. */ |
268 | ||
269 | enum mips_pic_level | |
270 | { | |
271 | /* Do not generate PIC code. */ | |
272 | NO_PIC, | |
273 | ||
274 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
275 | not sure what it is supposed to do. */ | |
276 | IRIX4_PIC, | |
277 | ||
278 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
279 | SVR4_PIC, | |
280 | ||
281 | /* Generate PIC code without using a global offset table: the data | |
282 | segment has a maximum size of 64K, all data references are off | |
283 | the $gp register, and all text references are PC relative. This | |
284 | is used on some embedded systems. */ | |
285 | EMBEDDED_PIC | |
286 | }; | |
287 | ||
288 | static enum mips_pic_level mips_pic; | |
9226253a | 289 | |
fb251650 ILT |
290 | /* 1 if we should generate 32 bit offsets from the GP register in |
291 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
292 | static int mips_big_got; | |
293 | ||
8ea7f4e8 ILT |
294 | /* 1 if trap instructions should used for overflow rather than break |
295 | instructions. */ | |
296 | static int mips_trap; | |
297 | ||
3c83da8a | 298 | /* Non-zero if any .set noreorder directives were used. */ |
cc5703cd | 299 | |
0dd2d296 | 300 | static int mips_any_noreorder; |
3d3c5039 | 301 | |
670a50eb ILT |
302 | /* The size of the small data section. */ |
303 | static int g_switch_value = 8; | |
42562568 ILT |
304 | /* Whether the -G option was used. */ |
305 | static int g_switch_seen = 0; | |
670a50eb | 306 | |
3d3c5039 ILT |
307 | #define N_RMASK 0xc4 |
308 | #define N_VFP 0xd4 | |
309 | ||
d8a1c247 KR |
310 | /* If we can determine in advance that GP optimization won't be |
311 | possible, we can skip the relaxation stuff that tries to produce | |
312 | GP-relative references. This makes delay slot optimization work | |
313 | better. | |
314 | ||
315 | This function can only provide a guess, but it seems to work for | |
316 | gcc output. If it guesses wrong, the only loss should be in | |
317 | efficiency; it shouldn't introduce any bugs. | |
318 | ||
319 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
320 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
85ce5635 | 321 | static int nopic_need_relax PARAMS ((symbolS *, int)); |
d8a1c247 | 322 | |
3d3c5039 ILT |
323 | /* handle of the OPCODE hash table */ |
324 | static struct hash_control *op_hash = NULL; | |
325 | ||
cc5703cd ILT |
326 | /* The opcode hash table we use for the mips16. */ |
327 | static struct hash_control *mips16_op_hash = NULL; | |
328 | ||
3d3c5039 ILT |
329 | /* This array holds the chars that always start a comment. If the |
330 | pre-processor is disabled, these aren't very useful */ | |
331 | const char comment_chars[] = "#"; | |
332 | ||
333 | /* This array holds the chars that only start a comment at the beginning of | |
334 | a line. If the line seems to have the form '# 123 filename' | |
335 | .line and .file directives will appear in the pre-processed output */ | |
336 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
337 | first line of the input file. This is because the compiler outputs | |
338 | #NO_APP at the beginning of its output. */ | |
339 | /* Also note that C style comments are always supported. */ | |
340 | const char line_comment_chars[] = "#"; | |
341 | ||
342 | /* This array holds machine specific line separator characters. */ | |
343 | const char line_separator_chars[] = ""; | |
344 | ||
345 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
346 | const char EXP_CHARS[] = "eE"; | |
347 | ||
348 | /* Chars that mean this number is a floating point constant */ | |
349 | /* As in 0f12.456 */ | |
350 | /* or 0d1.2345e12 */ | |
351 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
352 | ||
353 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
354 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
355 | but nothing is ideal around here. | |
356 | */ | |
357 | ||
670a50eb | 358 | static char *insn_error; |
3d3c5039 | 359 | |
3d3c5039 | 360 | static int auto_align = 1; |
becfe05e | 361 | |
9226253a ILT |
362 | /* When outputting SVR4 PIC code, the assembler needs to know the |
363 | offset in the stack frame from which to restore the $gp register. | |
364 | This is set by the .cprestore pseudo-op, and saved in this | |
365 | variable. */ | |
0dd2d296 ILT |
366 | static offsetT mips_cprestore_offset = -1; |
367 | ||
368 | /* This is the register which holds the stack frame, as set by the | |
369 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
370 | static int mips_frame_reg = SP; | |
9226253a | 371 | |
becfe05e ILT |
372 | /* To output NOP instructions correctly, we need to keep information |
373 | about the previous two instructions. */ | |
374 | ||
0aa07269 ILT |
375 | /* Whether we are optimizing. The default value of 2 means to remove |
376 | unneeded NOPs and swap branch instructions when possible. A value | |
377 | of 1 means to not swap branches. A value of 0 means to always | |
378 | insert NOPs. */ | |
379 | static int mips_optimize = 2; | |
4e95866e | 380 | |
22ba90ce ILT |
381 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
382 | equivalent to seeing no -g option at all. */ | |
383 | static int mips_debug = 0; | |
384 | ||
becfe05e ILT |
385 | /* The previous instruction. */ |
386 | static struct mips_cl_insn prev_insn; | |
387 | ||
388 | /* The instruction before prev_insn. */ | |
389 | static struct mips_cl_insn prev_prev_insn; | |
390 | ||
391 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
392 | point the insn_mo field at this dummy integer. */ | |
393 | static const struct mips_opcode dummy_opcode = { 0 }; | |
394 | ||
395 | /* Non-zero if prev_insn is valid. */ | |
396 | static int prev_insn_valid; | |
397 | ||
398 | /* The frag for the previous instruction. */ | |
399 | static struct frag *prev_insn_frag; | |
400 | ||
401 | /* The offset into prev_insn_frag for the previous instruction. */ | |
402 | static long prev_insn_where; | |
403 | ||
a677feeb ILT |
404 | /* The reloc type for the previous instruction, if any. */ |
405 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
406 | ||
becfe05e ILT |
407 | /* The reloc for the previous instruction, if any. */ |
408 | static fixS *prev_insn_fixp; | |
409 | ||
410 | /* Non-zero if the previous instruction was in a delay slot. */ | |
411 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
412 | |
413 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
414 | static int prev_insn_unreordered; | |
415 | ||
cc5703cd ILT |
416 | /* Non-zero if the previous instruction uses an extend opcode (if |
417 | mips16). */ | |
418 | static int prev_insn_extended; | |
419 | ||
4e95866e ILT |
420 | /* Non-zero if the previous previous instruction was in a .set |
421 | noreorder. */ | |
422 | static int prev_prev_insn_unreordered; | |
867a58b3 | 423 | |
7e656649 RH |
424 | /* start-sanitize-branchbug4011 */ |
425 | /* Non-zero if the previous insn had one or more labels */ | |
426 | static int prev_insn_labels; | |
427 | ||
428 | /* end-sanitize-branchbug4011 */ | |
4a1cb507 ILT |
429 | /* If this is set, it points to a frag holding nop instructions which |
430 | were inserted before the start of a noreorder section. If those | |
431 | nops turn out to be unnecessary, the size of the frag can be | |
432 | decreased. */ | |
433 | static fragS *prev_nop_frag; | |
434 | ||
435 | /* The number of nop instructions we created in prev_nop_frag. */ | |
436 | static int prev_nop_frag_holds; | |
437 | ||
438 | /* The number of nop instructions that we know we need in | |
439 | prev_nop_frag. */ | |
440 | static int prev_nop_frag_required; | |
441 | ||
442 | /* The number of instructions we've seen since prev_nop_frag. */ | |
443 | static int prev_nop_frag_since; | |
444 | ||
867a58b3 ILT |
445 | /* For ECOFF and ELF, relocations against symbols are done in two |
446 | parts, with a HI relocation and a LO relocation. Each relocation | |
447 | has only 16 bits of space to store an addend. This means that in | |
448 | order for the linker to handle carries correctly, it must be able | |
449 | to locate both the HI and the LO relocation. This means that the | |
450 | relocations must appear in order in the relocation table. | |
451 | ||
452 | In order to implement this, we keep track of each unmatched HI | |
453 | relocation. We then sort them so that they immediately precede the | |
454 | corresponding LO relocation. */ | |
455 | ||
456 | struct mips_hi_fixup | |
457 | { | |
458 | /* Next HI fixup. */ | |
459 | struct mips_hi_fixup *next; | |
460 | /* This fixup. */ | |
461 | fixS *fixp; | |
462 | /* The section this fixup is in. */ | |
463 | segT seg; | |
464 | }; | |
465 | ||
466 | /* The list of unmatched HI relocs. */ | |
467 | ||
468 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
469 | |
470 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
471 | ||
472 | #define X ILLEGAL_REG | |
473 | static const int mips32_to_16_reg_map[] = | |
474 | { | |
475 | X, X, 2, 3, 4, 5, 6, 7, | |
476 | X, X, X, X, X, X, X, X, | |
477 | 0, 1, X, X, X, X, X, X, | |
478 | X, X, X, X, X, X, X, X | |
479 | }; | |
480 | #undef X | |
481 | ||
482 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
483 | ||
484 | static const int mips16_to_32_reg_map[] = | |
485 | { | |
486 | 16, 17, 2, 3, 4, 5, 6, 7 | |
487 | }; | |
3d3c5039 | 488 | \f |
0dd2d296 ILT |
489 | /* Since the MIPS does not have multiple forms of PC relative |
490 | instructions, we do not have to do relaxing as is done on other | |
491 | platforms. However, we do have to handle GP relative addressing | |
492 | correctly, which turns out to be a similar problem. | |
493 | ||
494 | Every macro that refers to a symbol can occur in (at least) two | |
495 | forms, one with GP relative addressing and one without. For | |
496 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 497 | a macro instruction like this: |
0dd2d296 ILT |
498 | lw $4,i |
499 | If i can be addressed off the GP register (this is true if it is in | |
500 | the .sbss or .sdata section, or if it is known to be smaller than | |
501 | the -G argument) this will generate the following instruction: | |
502 | lw $4,i($gp) | |
503 | This instruction will use a GPREL reloc. If i can not be addressed | |
504 | off the GP register, the following instruction sequence will be used: | |
505 | lui $at,i | |
506 | lw $4,i($at) | |
507 | In this case the first instruction will have a HI16 reloc, and the | |
508 | second reloc will have a LO16 reloc. Both relocs will be against | |
509 | the symbol i. | |
510 | ||
511 | The issue here is that we may not know whether i is GP addressable | |
512 | until after we see the instruction that uses it. Therefore, we | |
513 | want to be able to choose the final instruction sequence only at | |
514 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 515 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
516 | end of assembly. |
517 | ||
518 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
519 | addressing in quite the same way, but the issue still arises as |
520 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
521 | |
522 | We handle these issues by actually generating both possible | |
523 | instruction sequences. The longer one is put in a frag_var with | |
524 | type rs_machine_dependent. We encode what to do with the frag in | |
525 | the subtype field. We encode (1) the number of existing bytes to | |
526 | replace, (2) the number of new bytes to use, (3) the offset from | |
527 | the start of the existing bytes to the first reloc we must generate | |
528 | (that is, the offset is applied from the start of the existing | |
529 | bytes after they are replaced by the new bytes, if any), (4) the | |
530 | offset from the start of the existing bytes to the second reloc, | |
531 | (5) whether a third reloc is needed (the third reloc is always four | |
532 | bytes after the second reloc), and (6) whether to warn if this | |
533 | variant is used (this is sometimes needed if .set nomacro or .set | |
534 | noat is in effect). All these numbers are reasonably small. | |
535 | ||
536 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
537 | ensure that delay slots are handled correctly. Fortunately, there |
538 | are a limited number of cases. When the second instruction | |
539 | sequence is generated, append_insn is directed to maintain the | |
540 | existing delay slot information, so it continues to apply to any | |
541 | code after the second instruction sequence. This means that the | |
542 | second instruction sequence must not impose any requirements not | |
543 | required by the first instruction sequence. | |
0dd2d296 ILT |
544 | |
545 | These variant frags are then handled in functions called by the | |
546 | machine independent code. md_estimate_size_before_relax returns | |
547 | the final size of the frag. md_convert_frag sets up the final form | |
548 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
549 | one if needed. */ | |
550 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
551 | ((relax_substateT) \ | |
cc5703cd | 552 | (((old) << 23) \ |
0dd2d296 ILT |
553 | | ((new) << 16) \ |
554 | | (((reloc1) + 64) << 9) \ | |
555 | | (((reloc2) + 64) << 2) \ | |
556 | | ((reloc3) ? (1 << 1) : 0) \ | |
557 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
558 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
559 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
560 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
561 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
562 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
563 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
564 | |
565 | /* For mips16 code, we use an entirely different form of relaxation. | |
566 | mips16 supports two versions of most instructions which take | |
567 | immediate values: a small one which takes some small value, and a | |
568 | larger one which takes a 16 bit value. Since branches also follow | |
569 | this pattern, relaxing these values is required. | |
570 | ||
571 | We can assemble both mips16 and normal MIPS code in a single | |
572 | object. Therefore, we need to support this type of relaxation at | |
573 | the same time that we support the relaxation described above. We | |
574 | use the high bit of the subtype field to distinguish these cases. | |
575 | ||
a677feeb ILT |
576 | The information we store for this type of relaxation is the |
577 | argument code found in the opcode file for this relocation, whether | |
578 | the user explicitly requested a small or extended form, and whether | |
579 | the relocation is in a jump or jal delay slot. That tells us the | |
580 | size of the value, and how it should be stored. We also store | |
581 | whether the fragment is considered to be extended or not. We also | |
582 | store whether this is known to be a branch to a different section, | |
583 | whether we have tried to relax this frag yet, and whether we have | |
584 | ever extended a PC relative fragment because of a shift count. */ | |
585 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
586 | (0x80000000 \ | |
587 | | ((type) & 0xff) \ | |
588 | | ((small) ? 0x100 : 0) \ | |
589 | | ((ext) ? 0x200 : 0) \ | |
590 | | ((dslot) ? 0x400 : 0) \ | |
591 | | ((jal_dslot) ? 0x800 : 0)) | |
cc5703cd ILT |
592 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
593 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
8728fa92 ILT |
594 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
595 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
a677feeb ILT |
596 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
597 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
598 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
599 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
600 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
601 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
602 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
603 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
7e656649 RH |
604 | /* start-sanitize-branchbug4011 */ |
605 | /* The 4011 core has a bug in it's branch processing that | |
606 | an be avoided if branches never branches (where branches | |
607 | are defined as those starting with 'b'). We do this here | |
608 | by insuring that labels are not directly on branch instructions, | |
609 | and if they are inserting a no-op between the label and the | |
610 | branch. */ | |
611 | static int mips_fix_4011_branch_bug = 0; | |
612 | /* end-sanitize-branchbug4011 */ | |
0dd2d296 | 613 | \f |
3d3c5039 ILT |
614 | /* Prototypes for static functions. */ |
615 | ||
616 | #ifdef __STDC__ | |
617 | #define internalError() \ | |
48401fcf | 618 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
3d3c5039 | 619 | #else |
48401fcf | 620 | #define internalError() as_fatal (_("MIPS internal Error")); |
3d3c5039 ILT |
621 | #endif |
622 | ||
cc5703cd ILT |
623 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
624 | ||
becfe05e | 625 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 626 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 627 | static int reg_needs_delay PARAMS ((int)); |
3c83da8a | 628 | static void mips16_mark_labels PARAMS ((void)); |
0dd2d296 ILT |
629 | static void append_insn PARAMS ((char *place, |
630 | struct mips_cl_insn * ip, | |
670a50eb | 631 | expressionS * p, |
867a58b3 ILT |
632 | bfd_reloc_code_real_type r, |
633 | boolean)); | |
4a1cb507 | 634 | static void mips_no_prev_insn PARAMS ((int)); |
fbcfacb7 | 635 | static void mips_emit_delays PARAMS ((boolean)); |
c625fc23 | 636 | #ifdef USE_STDARG |
0dd2d296 | 637 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
638 | const char *name, const char *fmt, |
639 | ...)); | |
c625fc23 JSC |
640 | #else |
641 | static void macro_build (); | |
642 | #endif | |
cc5703cd ILT |
643 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
644 | const char *, const char *, | |
645 | va_list)); | |
0dd2d296 ILT |
646 | static void macro_build_lui PARAMS ((char *place, int *counter, |
647 | expressionS * ep, int regnum)); | |
6e8dda9c | 648 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 649 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 650 | expressionS *)); |
d8a1c247 | 651 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 652 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 653 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 654 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
655 | #ifdef LOSING_COMPILER |
656 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
657 | #endif | |
670a50eb | 658 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd | 659 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
15e69f98 ILT |
660 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
661 | boolean, boolean, unsigned long *, | |
662 | boolean *, unsigned short *)); | |
670a50eb ILT |
663 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
664 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 665 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 666 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
667 | static void s_align PARAMS ((int)); |
668 | static void s_change_sec PARAMS ((int)); | |
669 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 670 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 671 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
672 | static void s_option PARAMS ((int)); |
673 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
674 | static void s_abicalls PARAMS ((int)); |
675 | static void s_cpload PARAMS ((int)); | |
676 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
677 | static void s_gpword PARAMS ((int)); |
678 | static void s_cpadd PARAMS ((int)); | |
ed3eb786 | 679 | static void s_insn PARAMS ((int)); |
3d3c5039 ILT |
680 | static void md_obj_begin PARAMS ((void)); |
681 | static void md_obj_end PARAMS ((void)); | |
682 | static long get_number PARAMS ((void)); | |
993b4e8d RU |
683 | static void s_mips_ent PARAMS ((int)); |
684 | static void s_mips_end PARAMS ((int)); | |
685 | static void s_mips_frame PARAMS ((int)); | |
686 | static void s_mips_mask PARAMS ((int)); | |
3c83da8a | 687 | static void s_mips_stab PARAMS ((int)); |
3c69baf9 | 688 | static void s_mips_weakext PARAMS ((int)); |
993b4e8d | 689 | static void s_file PARAMS ((int)); |
cc5703cd | 690 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
aa2e0460 | 691 | |
3c69baf9 | 692 | |
aa2e0460 | 693 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); |
3d3c5039 ILT |
694 | \f |
695 | /* Pseudo-op table. | |
696 | ||
697 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
698 | should be defined here, but are currently unsupported: .alias, | |
699 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
700 | ||
701 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
702 | specific to the type of debugging information being generated, and | |
703 | should be defined by the object format: .aent, .begin, .bend, | |
704 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
705 | .vreg. | |
706 | ||
707 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
708 | not MIPS CPU specific, but are also not specific to the object file | |
709 | format. This file is probably the best place to define them, but | |
710 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
3c69baf9 | 711 | .struct. */ |
3d3c5039 | 712 | |
739708fa | 713 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 714 | { |
670a50eb ILT |
715 | /* MIPS specific pseudo-ops. */ |
716 | {"option", s_option, 0}, | |
717 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
718 | {"rdata", s_change_sec, 'r'}, |
719 | {"sdata", s_change_sec, 's'}, | |
720 | {"livereg", s_ignore, 0}, | |
739708fa KR |
721 | {"abicalls", s_abicalls, 0}, |
722 | {"cpload", s_cpload, 0}, | |
723 | {"cprestore", s_cprestore, 0}, | |
724 | {"gpword", s_gpword, 0}, | |
725 | {"cpadd", s_cpadd, 0}, | |
ed3eb786 | 726 | {"insn", s_insn, 0}, |
3d3c5039 | 727 | |
670a50eb | 728 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 729 | chips. */ |
739708fa | 730 | {"asciiz", stringer, 1}, |
670a50eb ILT |
731 | {"bss", s_change_sec, 'b'}, |
732 | {"err", s_err, 0}, | |
733 | {"half", s_cons, 1}, | |
52aa70b5 | 734 | {"dword", s_cons, 3}, |
3c69baf9 | 735 | {"weakext", s_mips_weakext, 0}, |
3d3c5039 | 736 | |
670a50eb | 737 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 738 | here for one reason or another. */ |
670a50eb ILT |
739 | {"align", s_align, 0}, |
740 | {"byte", s_cons, 0}, | |
741 | {"data", s_change_sec, 'd'}, | |
becfe05e | 742 | {"double", s_float_cons, 'd'}, |
becfe05e | 743 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
744 | {"globl", s_mips_globl, 0}, |
745 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
746 | {"hword", s_cons, 1}, |
747 | {"int", s_cons, 2}, | |
748 | {"long", s_cons, 2}, | |
749 | {"octa", s_cons, 4}, | |
750 | {"quad", s_cons, 3}, | |
751 | {"short", s_cons, 1}, | |
752 | {"single", s_float_cons, 'f'}, | |
3c83da8a | 753 | {"stabn", s_mips_stab, 'n'}, |
670a50eb ILT |
754 | {"text", s_change_sec, 't'}, |
755 | {"word", s_cons, 2}, | |
739708fa KR |
756 | { 0 }, |
757 | }; | |
3d3c5039 | 758 | |
739708fa | 759 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 760 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 761 | However, a.out doesn't support them, so we have versions here. */ |
993b4e8d | 762 | {"aent", s_mips_ent, 1}, |
9226253a | 763 | {"bgnb", s_ignore, 0}, |
993b4e8d | 764 | {"end", s_mips_end, 0}, |
9226253a | 765 | {"endb", s_ignore, 0}, |
993b4e8d | 766 | {"ent", s_mips_ent, 0}, |
670a50eb | 767 | {"file", s_file, 0}, |
993b4e8d RU |
768 | {"fmask", s_mips_mask, 'F'}, |
769 | {"frame", s_mips_frame, 0}, | |
670a50eb | 770 | {"loc", s_ignore, 0}, |
993b4e8d | 771 | {"mask", s_mips_mask, 'R'}, |
670a50eb | 772 | {"verstamp", s_ignore, 0}, |
739708fa KR |
773 | { 0 }, |
774 | }; | |
61420a20 | 775 | |
739708fa KR |
776 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
777 | ||
778 | void | |
779 | mips_pop_insert () | |
780 | { | |
781 | pop_insert (mips_pseudo_table); | |
782 | if (! ECOFF_DEBUGGING) | |
783 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 784 | } |
3d3c5039 | 785 | \f |
fbcfacb7 ILT |
786 | /* Symbols labelling the current insn. */ |
787 | ||
788 | struct insn_label_list | |
789 | { | |
790 | struct insn_label_list *next; | |
791 | symbolS *label; | |
792 | }; | |
793 | ||
794 | static struct insn_label_list *insn_labels; | |
795 | static struct insn_label_list *free_insn_labels; | |
796 | ||
797 | static void mips_clear_insn_labels PARAMS ((void)); | |
798 | ||
799 | static inline void | |
800 | mips_clear_insn_labels () | |
801 | { | |
802 | register struct insn_label_list **pl; | |
803 | ||
804 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
805 | ; | |
806 | *pl = insn_labels; | |
807 | insn_labels = NULL; | |
808 | } | |
809 | \f | |
3d3c5039 ILT |
810 | static char *expr_end; |
811 | ||
867a58b3 ILT |
812 | /* Expressions which appear in instructions. These are set by |
813 | mips_ip. */ | |
814 | ||
3d3c5039 ILT |
815 | static expressionS imm_expr; |
816 | static expressionS offset_expr; | |
867a58b3 ILT |
817 | |
818 | /* Relocs associated with imm_expr and offset_expr. */ | |
819 | ||
3d3c5039 ILT |
820 | static bfd_reloc_code_real_type imm_reloc; |
821 | static bfd_reloc_code_real_type offset_reloc; | |
822 | ||
867a58b3 ILT |
823 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
824 | ||
825 | static boolean imm_unmatched_hi; | |
826 | ||
8728fa92 ILT |
827 | /* These are set by mips16_ip if an explicit extension is used. */ |
828 | ||
829 | static boolean mips16_small, mips16_ext; | |
830 | ||
993b4e8d RU |
831 | #ifdef MIPS_STABS_ELF |
832 | /* The pdr segment for per procedure frame/regmask info */ | |
833 | ||
834 | static segT pdr_seg; | |
835 | #endif | |
836 | ||
3d3c5039 ILT |
837 | /* |
838 | * This function is called once, at assembler startup time. It should | |
839 | * set up all the tables, etc. that the MD part of the assembler will need. | |
840 | */ | |
841 | void | |
670a50eb | 842 | md_begin () |
3d3c5039 | 843 | { |
0dd2d296 | 844 | boolean ok = false; |
604633ae | 845 | register const char *retval = NULL; |
670a50eb | 846 | register unsigned int i = 0; |
1724c79e GRK |
847 | const char *cpu; |
848 | char *a = NULL; | |
aa2e0460 | 849 | int broken = 0; |
3d3c5039 | 850 | |
1724c79e GRK |
851 | cpu = TARGET_CPU; |
852 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
8358c818 | 853 | { |
1724c79e GRK |
854 | a = xmalloc (sizeof TARGET_CPU); |
855 | strcpy (a, TARGET_CPU); | |
856 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
857 | cpu = a; | |
858 | } | |
8c63448a | 859 | |
1724c79e GRK |
860 | if (mips_cpu < 0) |
861 | { | |
862 | /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is | |
863 | just the generic 'mips', in which case set mips_cpu based | |
864 | on the given ISA, if any. */ | |
8c63448a ILT |
865 | |
866 | if (strcmp (cpu, "mips") == 0) | |
1724c79e GRK |
867 | { |
868 | if (mips_opts.isa < 0) | |
869 | mips_cpu = 3000; | |
870 | ||
871 | else if (mips_opts.isa == 2) | |
872 | mips_cpu = 6000; | |
873 | ||
874 | else if (mips_opts.isa == 3) | |
875 | mips_cpu = 4000; | |
876 | ||
877 | else if (mips_opts.isa == 4) | |
878 | mips_cpu = 8000; | |
879 | ||
880 | else | |
881 | mips_cpu = 3000; | |
882 | } | |
883 | ||
5c6f5923 | 884 | else if (strcmp (cpu, "r3900") == 0 |
6fd819cf | 885 | || strcmp (cpu, "mipstx39") == 0 |
4e96260f JL |
886 | /* start-sanitize-tx19 */ |
887 | || strcmp (cpu, "r1900") == 0 | |
888 | || strcmp (cpu, "mipstx19") == 0 | |
889 | /* end-sanitize-tx19 */ | |
890 | ) | |
1724c79e GRK |
891 | mips_cpu = 3900; |
892 | ||
8c63448a ILT |
893 | else if (strcmp (cpu, "r6000") == 0 |
894 | || strcmp (cpu, "mips2") == 0) | |
1724c79e GRK |
895 | mips_cpu = 6000; |
896 | ||
8c63448a ILT |
897 | else if (strcmp (cpu, "mips64") == 0 |
898 | || strcmp (cpu, "r4000") == 0 | |
899 | || strcmp (cpu, "mips3") == 0) | |
1724c79e GRK |
900 | mips_cpu = 4000; |
901 | ||
8c63448a | 902 | else if (strcmp (cpu, "r4400") == 0) |
1724c79e GRK |
903 | mips_cpu = 4400; |
904 | ||
8c63448a ILT |
905 | else if (strcmp (cpu, "mips64orion") == 0 |
906 | || strcmp (cpu, "r4600") == 0) | |
1724c79e GRK |
907 | mips_cpu = 4600; |
908 | ||
b2b8c24e | 909 | else if (strcmp (cpu, "r4650") == 0) |
1724c79e GRK |
910 | mips_cpu = 4650; |
911 | ||
c625fc23 | 912 | else if (strcmp (cpu, "mips64vr4300") == 0) |
1724c79e GRK |
913 | mips_cpu = 4300; |
914 | ||
3b35597c JL |
915 | /* start-sanitize-vr4xxx */ |
916 | else if (strcmp (cpu, "mips64vr4xxx") == 0) | |
917 | mips_cpu = 4300; | |
918 | ||
919 | /* end-sanitize-vr4xxx */ | |
2d035a50 GRK |
920 | /* start-sanitize-vr4320 */ |
921 | else if (strcmp (cpu, "r4320") == 0 | |
922 | || strcmp (cpu, "mips64vr4320") == 0) | |
923 | mips_cpu = 4320; | |
924 | ||
925 | /* end-sanitize-vr4320 */ | |
e599ab16 | 926 | else if (strcmp (cpu, "mips64vr4100") == 0) |
1724c79e GRK |
927 | mips_cpu = 4100; |
928 | ||
f14397f0 GRK |
929 | /* start-sanitize-vr4xxx */ |
930 | else if (strcmp (cpu, "vr4121") == 0 | |
931 | || strcmp (cpu, "mips64vr4121") == 0) | |
932 | mips_cpu = 4121; | |
933 | ||
934 | /* end-sanitize-vr4xxx */ | |
e532b44c | 935 | else if (strcmp (cpu, "r4010") == 0) |
1724c79e GRK |
936 | mips_cpu = 4010; |
937 | ||
4ebda395 GRK |
938 | /* start-sanitize-tx49 */ |
939 | else if (strcmp (cpu, "mips64tx49") == 0) | |
1724c79e | 940 | mips_cpu = 4900; |
4ebda395 | 941 | /* end-sanitize-tx49 */ |
1724c79e | 942 | |
517078c1 ILT |
943 | else if (strcmp (cpu, "r5000") == 0 |
944 | || strcmp (cpu, "mips64vr5000") == 0) | |
1724c79e GRK |
945 | mips_cpu = 5000; |
946 | ||
6b34ac5a | 947 | /* start-sanitize-cygnus */ |
aa2e0460 | 948 | else if (strcmp (cpu, "r5400") == 0 |
b3ed1af3 KR |
949 | || strcmp (cpu, "mips64vr5400") == 0) |
950 | mips_cpu = 5400; | |
6b34ac5a | 951 | /* end-sanitize-cygnus */ |
1724c79e | 952 | |
276c2d7d GRK |
953 | /* start-sanitize-r5900 */ |
954 | else if (strcmp (cpu, "r5900") == 0 | |
1724c79e GRK |
955 | || strcmp (cpu, "mips64r5900") == 0) |
956 | mips_cpu = 5900; | |
276c2d7d | 957 | /* end-sanitize-r5900 */ |
1724c79e | 958 | |
d8a1c247 KR |
959 | else if (strcmp (cpu, "r8000") == 0 |
960 | || strcmp (cpu, "mips4") == 0) | |
1724c79e GRK |
961 | mips_cpu = 8000; |
962 | ||
d8a1c247 | 963 | else if (strcmp (cpu, "r10000") == 0) |
1724c79e GRK |
964 | mips_cpu = 10000; |
965 | ||
cc5703cd | 966 | else if (strcmp (cpu, "mips16") == 0) |
1724c79e GRK |
967 | mips_cpu = 0; /* FIXME */ |
968 | ||
8358c818 | 969 | else |
1724c79e GRK |
970 | mips_cpu = 3000; |
971 | } | |
8c63448a | 972 | |
1724c79e GRK |
973 | if (mips_opts.isa == -1) |
974 | { | |
975 | if (mips_cpu == 3000 | |
976 | || mips_cpu == 3900) | |
977 | mips_opts.isa = 1; | |
978 | ||
979 | else if (mips_cpu == 6000 | |
980 | || mips_cpu == 4010) | |
981 | mips_opts.isa = 2; | |
982 | ||
983 | else if (mips_cpu == 4000 | |
984 | || mips_cpu == 4100 | |
f14397f0 | 985 | /* start-sanitize-vr4xxx */ |
d95b7328 | 986 | || mips_cpu == 4111 |
f14397f0 GRK |
987 | || mips_cpu == 4121 |
988 | /* end-sanitize-vr4xxx */ | |
1724c79e GRK |
989 | || mips_cpu == 4400 |
990 | || mips_cpu == 4300 | |
2d035a50 GRK |
991 | /* start-sanitize-vr4320 */ |
992 | || mips_cpu == 4320 | |
059a6388 | 993 | /* end-sanitize-vr4320 */ |
1724c79e GRK |
994 | || mips_cpu == 4600 |
995 | /* start-sanitize-tx49 */ | |
996 | || mips_cpu == 4900 | |
997 | /* end-sanitize-tx49 */ | |
998 | /* start-sanitize-r5900 */ | |
999 | || mips_cpu == 5900 | |
1000 | /* end-sanitize-r5900 */ | |
1001 | || mips_cpu == 4650) | |
1002 | mips_opts.isa = 3; | |
1003 | ||
1004 | else if (mips_cpu == 5000 | |
6b34ac5a | 1005 | /* start-sanitize-cygnus */ |
1724c79e | 1006 | || mips_cpu == 5400 |
6b34ac5a | 1007 | /* end-sanitize-cygnus */ |
1724c79e GRK |
1008 | || mips_cpu == 8000 |
1009 | || mips_cpu == 10000) | |
1010 | mips_opts.isa = 4; | |
1011 | ||
1012 | else | |
1013 | mips_opts.isa = 1; | |
8358c818 ILT |
1014 | } |
1015 | ||
3c83da8a | 1016 | if (mips_opts.mips16 < 0) |
cc5703cd ILT |
1017 | { |
1018 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
3c83da8a | 1019 | mips_opts.mips16 = 1; |
cc5703cd | 1020 | else |
3c83da8a | 1021 | mips_opts.mips16 = 0; |
cc5703cd ILT |
1022 | } |
1023 | ||
1724c79e GRK |
1024 | /* End of TARGET_CPU processing, get rid of malloced memory |
1025 | if necessary. */ | |
1026 | cpu = NULL; | |
1027 | if (a != NULL) | |
1028 | { | |
1029 | free (a); | |
1030 | a = NULL; | |
1031 | } | |
1032 | ||
3c83da8a | 1033 | if (mips_opts.isa < 2 && mips_trap) |
48401fcf | 1034 | as_bad (_("trap exception not supported at ISA 1")); |
8ea7f4e8 | 1035 | |
d95b7328 GRK |
1036 | /* Set the EABI kind based on the ISA before the user gets |
1037 | to change the ISA with directives. This isn't really | |
1038 | the best, but then neither is basing the abi on the isa. */ | |
ffa3e186 GRK |
1039 | if (mips_opts.isa > 2 |
1040 | && mips_abi_string | |
1041 | && 0 == strcmp (mips_abi_string,"eabi")) | |
d95b7328 GRK |
1042 | mips_eabi64 = 1; |
1043 | ||
9a1f3160 | 1044 | if (mips_cpu != 0 && mips_cpu != -1) |
97f99d11 | 1045 | { |
9a1f3160 JL |
1046 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu); |
1047 | } | |
1048 | else | |
1049 | { | |
1050 | switch (mips_opts.isa) | |
1051 | { | |
1052 | case 1: | |
1053 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
1054 | break; | |
1055 | case 2: | |
1056 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
1057 | break; | |
1058 | case 3: | |
1059 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
1060 | break; | |
1061 | case 4: | |
1062 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
1063 | break; | |
1064 | } | |
97f99d11 | 1065 | } |
9a1f3160 | 1066 | |
97f99d11 | 1067 | if (! ok) |
48401fcf | 1068 | as_warn (_("Could not set architecture and machine")); |
97f99d11 | 1069 | |
3c83da8a | 1070 | file_mips_isa = mips_opts.isa; |
1051c97f | 1071 | |
13fe1379 ILT |
1072 | op_hash = hash_new (); |
1073 | ||
670a50eb ILT |
1074 | for (i = 0; i < NUMOPCODES;) |
1075 | { | |
1076 | const char *name = mips_opcodes[i].name; | |
1077 | ||
604633ae | 1078 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 1079 | if (retval != NULL) |
670a50eb | 1080 | { |
48401fcf | 1081 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), |
670a50eb | 1082 | mips_opcodes[i].name, retval); |
aa2e0460 | 1083 | /* Probably a memory allocation problem? Give up now. */ |
48401fcf | 1084 | as_fatal (_("Broken assembler. No assembly attempted.")); |
670a50eb ILT |
1085 | } |
1086 | do | |
1087 | { | |
aa2e0460 | 1088 | if (mips_opcodes[i].pinfo != INSN_MACRO) |
670a50eb | 1089 | { |
aa2e0460 KR |
1090 | if (!validate_mips_insn (&mips_opcodes[i])) |
1091 | broken = 1; | |
3d3c5039 | 1092 | } |
670a50eb ILT |
1093 | ++i; |
1094 | } | |
1095 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
1096 | } |
1097 | ||
cc5703cd ILT |
1098 | mips16_op_hash = hash_new (); |
1099 | ||
1100 | i = 0; | |
1101 | while (i < bfd_mips16_num_opcodes) | |
1102 | { | |
1103 | const char *name = mips16_opcodes[i].name; | |
1104 | ||
1105 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1106 | if (retval != NULL) | |
48401fcf | 1107 | as_fatal (_("internal: can't hash `%s': %s"), |
cc5703cd ILT |
1108 | mips16_opcodes[i].name, retval); |
1109 | do | |
1110 | { | |
1111 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1112 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1113 | != mips16_opcodes[i].match)) | |
aa2e0460 | 1114 | { |
48401fcf | 1115 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), |
aa2e0460 KR |
1116 | mips16_opcodes[i].name, mips16_opcodes[i].args); |
1117 | broken = 1; | |
1118 | } | |
cc5703cd ILT |
1119 | ++i; |
1120 | } | |
1121 | while (i < bfd_mips16_num_opcodes | |
1122 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1123 | } | |
1124 | ||
aa2e0460 | 1125 | if (broken) |
48401fcf | 1126 | as_fatal (_("Broken assembler. No assembly attempted.")); |
aa2e0460 | 1127 | |
ebf28372 ILT |
1128 | /* We add all the general register names to the symbol table. This |
1129 | helps us detect invalid uses of them. */ | |
1130 | for (i = 0; i < 32; i++) | |
1131 | { | |
1132 | char buf[5]; | |
1133 | ||
1134 | sprintf (buf, "$%d", i); | |
1135 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1136 | &zero_address_frag)); | |
1137 | } | |
1138 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1139 | &zero_address_frag)); | |
1140 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1141 | &zero_address_frag)); | |
1142 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1143 | &zero_address_frag)); | |
1144 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1145 | &zero_address_frag)); | |
1146 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1147 | &zero_address_frag)); | |
1148 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1149 | &zero_address_frag)); | |
1150 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1151 | &zero_address_frag)); | |
1152 | ||
4a1cb507 | 1153 | mips_no_prev_insn (false); |
becfe05e | 1154 | |
1aa6938e ILT |
1155 | mips_gprmask = 0; |
1156 | mips_cprmask[0] = 0; | |
1157 | mips_cprmask[1] = 0; | |
1158 | mips_cprmask[2] = 0; | |
1159 | mips_cprmask[3] = 0; | |
1160 | ||
8358c818 | 1161 | /* set the default alignment for the text section (2**2) */ |
f5e38044 | 1162 | record_alignment (text_section, 2); |
8358c818 | 1163 | |
1dc1e798 KR |
1164 | if (USE_GLOBAL_POINTER_OPT) |
1165 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 1166 | |
1dc1e798 KR |
1167 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1168 | { | |
08e17202 ILT |
1169 | /* On a native system, sections must be aligned to 16 byte |
1170 | boundaries. When configured for an embedded ELF target, we | |
1171 | don't bother. */ | |
1172 | if (strcmp (TARGET_OS, "elf") != 0) | |
1173 | { | |
1174 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1175 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1176 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1177 | } | |
1dc1e798 KR |
1178 | |
1179 | /* Create a .reginfo section for register masks and a .mdebug | |
1180 | section for debugging information. */ | |
1181 | { | |
1182 | segT seg; | |
1183 | subsegT subseg; | |
b3a64736 | 1184 | flagword flags; |
1dc1e798 KR |
1185 | segT sec; |
1186 | ||
1187 | seg = now_seg; | |
1188 | subseg = now_subseg; | |
1dc1e798 | 1189 | |
b3a64736 ILT |
1190 | /* The ABI says this section should be loaded so that the |
1191 | running program can access it. However, we don't load it | |
1192 | if we are configured for an embedded target */ | |
1193 | flags = SEC_READONLY | SEC_DATA; | |
1194 | if (strcmp (TARGET_OS, "elf") != 0) | |
1195 | flags |= SEC_ALLOC | SEC_LOAD; | |
1196 | ||
87178180 ILT |
1197 | if (! mips_64) |
1198 | { | |
1199 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 1200 | |
b3a64736 ILT |
1201 | |
1202 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
87178180 ILT |
1203 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
1204 | ||
f2a663d3 | 1205 | #ifdef OBJ_ELF |
87178180 | 1206 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 1207 | #endif |
87178180 ILT |
1208 | } |
1209 | else | |
1210 | { | |
1211 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1212 | .reginfo section. */ | |
1213 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
b3a64736 | 1214 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
87178180 ILT |
1215 | (void) bfd_set_section_alignment (stdoutput, sec, 3); |
1216 | ||
1217 | #ifdef OBJ_ELF | |
1218 | /* Set up the option header. */ | |
1219 | { | |
1220 | Elf_Internal_Options opthdr; | |
1221 | char *f; | |
1222 | ||
1223 | opthdr.kind = ODK_REGINFO; | |
1224 | opthdr.size = (sizeof (Elf_External_Options) | |
1225 | + sizeof (Elf64_External_RegInfo)); | |
1226 | opthdr.section = 0; | |
1227 | opthdr.info = 0; | |
1228 | f = frag_more (sizeof (Elf_External_Options)); | |
1229 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1230 | (Elf_External_Options *) f); | |
1231 | ||
1232 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1233 | } | |
1234 | #endif | |
1235 | } | |
f2a663d3 | 1236 | |
739708fa KR |
1237 | if (ECOFF_DEBUGGING) |
1238 | { | |
1239 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1240 | (void) bfd_set_section_flags (stdoutput, sec, | |
1241 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1242 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1243 | } | |
0dd2d296 | 1244 | |
993b4e8d RU |
1245 | #ifdef MIPS_STABS_ELF |
1246 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1247 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1248 | SEC_READONLY | SEC_RELOC | SEC_DEBUGGING); | |
1249 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1250 | #endif | |
1251 | ||
1dc1e798 KR |
1252 | subseg_set (seg, subseg); |
1253 | } | |
1254 | } | |
f2a663d3 | 1255 | |
739708fa KR |
1256 | if (! ECOFF_DEBUGGING) |
1257 | md_obj_begin (); | |
3d3c5039 ILT |
1258 | } |
1259 | ||
1260 | void | |
13fe1379 | 1261 | md_mips_end () |
3d3c5039 | 1262 | { |
739708fa KR |
1263 | if (! ECOFF_DEBUGGING) |
1264 | md_obj_end (); | |
3d3c5039 ILT |
1265 | } |
1266 | ||
1267 | void | |
670a50eb ILT |
1268 | md_assemble (str) |
1269 | char *str; | |
3d3c5039 | 1270 | { |
670a50eb | 1271 | struct mips_cl_insn insn; |
3d3c5039 | 1272 | |
5ac34ac3 | 1273 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
1274 | imm_reloc = BFD_RELOC_UNUSED; |
1275 | imm_unmatched_hi = false; | |
5ac34ac3 | 1276 | offset_expr.X_op = O_absent; |
867a58b3 | 1277 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 1278 | |
3c83da8a | 1279 | if (mips_opts.mips16) |
cc5703cd ILT |
1280 | mips16_ip (str, &insn); |
1281 | else | |
efec4a28 | 1282 | { |
9218cee0 | 1283 | mips_ip (str, &insn); |
48401fcf | 1284 | DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
efec4a28 DP |
1285 | str, insn.insn_opcode)); |
1286 | } | |
cc5703cd | 1287 | |
670a50eb ILT |
1288 | if (insn_error) |
1289 | { | |
1290 | as_bad ("%s `%s'", insn_error, str); | |
1291 | return; | |
1292 | } | |
cc5703cd | 1293 | |
670a50eb ILT |
1294 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1295 | { | |
3c83da8a | 1296 | if (mips_opts.mips16) |
cc5703cd ILT |
1297 | mips16_macro (&insn); |
1298 | else | |
1299 | macro (&insn); | |
3d3c5039 | 1300 | } |
670a50eb ILT |
1301 | else |
1302 | { | |
5ac34ac3 | 1303 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1304 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1305 | imm_unmatched_hi); | |
5ac34ac3 | 1306 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1307 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1308 | else |
867a58b3 | 1309 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1310 | } |
1311 | } | |
1312 | ||
cc5703cd ILT |
1313 | /* See whether instruction IP reads register REG. CLASS is the type |
1314 | of register. */ | |
becfe05e ILT |
1315 | |
1316 | static int | |
cc5703cd | 1317 | insn_uses_reg (ip, reg, class) |
becfe05e | 1318 | struct mips_cl_insn *ip; |
604633ae | 1319 | unsigned int reg; |
cc5703cd | 1320 | enum mips_regclass class; |
becfe05e | 1321 | { |
cc5703cd ILT |
1322 | if (class == MIPS16_REG) |
1323 | { | |
3c83da8a | 1324 | assert (mips_opts.mips16); |
cc5703cd ILT |
1325 | reg = mips16_to_32_reg_map[reg]; |
1326 | class = MIPS_GR_REG; | |
1327 | } | |
1328 | ||
becfe05e | 1329 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1330 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1331 | return 0; |
1332 | ||
cc5703cd | 1333 | if (class == MIPS_FP_REG) |
becfe05e | 1334 | { |
3c83da8a | 1335 | assert (! mips_opts.mips16); |
becfe05e ILT |
1336 | /* If we are called with either $f0 or $f1, we must check $f0. |
1337 | This is not optimal, because it will introduce an unnecessary | |
1338 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1339 | need to distinguish reading both $f0 and $f1 or just one of | |
1340 | them. Note that we don't have to check the other way, | |
1341 | because there is no instruction that sets both $f0 and $f1 | |
1342 | and requires a delay. */ | |
1343 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
68952421 | 1344 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) |
604633ae | 1345 | == (reg &~ (unsigned) 1))) |
becfe05e ILT |
1346 | return 1; |
1347 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
68952421 | 1348 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) |
604633ae | 1349 | == (reg &~ (unsigned) 1))) |
becfe05e ILT |
1350 | return 1; |
1351 | } | |
3c83da8a | 1352 | else if (! mips_opts.mips16) |
becfe05e ILT |
1353 | { |
1354 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1355 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1356 | return 1; | |
1357 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1358 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1359 | return 1; | |
1360 | } | |
cc5703cd ILT |
1361 | else |
1362 | { | |
1363 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
23ac3ca1 ILT |
1364 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) |
1365 | & MIPS16OP_MASK_RX)] | |
1366 | == reg)) | |
cc5703cd ILT |
1367 | return 1; |
1368 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
23ac3ca1 ILT |
1369 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) |
1370 | & MIPS16OP_MASK_RY)] | |
1371 | == reg)) | |
cc5703cd ILT |
1372 | return 1; |
1373 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
23ac3ca1 ILT |
1374 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) |
1375 | & MIPS16OP_MASK_MOVE32Z)] | |
1376 | == reg)) | |
cc5703cd ILT |
1377 | return 1; |
1378 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1379 | return 1; | |
1380 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1381 | return 1; | |
1382 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1383 | return 1; | |
1384 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1385 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1386 | & MIPS16OP_MASK_REGR32) == reg) | |
1387 | return 1; | |
1388 | } | |
becfe05e ILT |
1389 | |
1390 | return 0; | |
1391 | } | |
1392 | ||
fb251650 ILT |
1393 | /* This function returns true if modifying a register requires a |
1394 | delay. */ | |
1395 | ||
1396 | static int | |
1397 | reg_needs_delay (reg) | |
1398 | int reg; | |
1399 | { | |
1400 | unsigned long prev_pinfo; | |
1401 | ||
1402 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
3c83da8a JW |
1403 | if (! mips_opts.noreorder |
1404 | && mips_opts.isa < 4 | |
fb251650 | 1405 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
5c6f5923 | 1406 | || (! gpr_interlocks |
fb251650 ILT |
1407 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
1408 | { | |
1409 | /* A load from a coprocessor or from memory. All load | |
1410 | delays delay the use of general register rt for one | |
1411 | instruction on the r3000. The r6000 and r4000 use | |
1412 | interlocks. */ | |
efec4a28 | 1413 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
1414 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1415 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1416 | return 1; | |
1417 | } | |
1418 | ||
1419 | return 0; | |
1420 | } | |
1421 | ||
3c83da8a JW |
1422 | /* Mark instruction labels in mips16 mode. This permits the linker to |
1423 | handle them specially, such as generating jalx instructions when | |
1424 | needed. We also make them odd for the duration of the assembly, in | |
1425 | order to generate the right sort of code. We will make them even | |
1426 | in the adjust_symtab routine, while leaving them marked. This is | |
1427 | convenient for the debugger and the disassembler. The linker knows | |
1428 | to make them odd again. */ | |
1429 | ||
1430 | static void | |
1431 | mips16_mark_labels () | |
1432 | { | |
1433 | if (mips_opts.mips16) | |
1434 | { | |
1435 | struct insn_label_list *l; | |
1436 | ||
1437 | for (l = insn_labels; l != NULL; l = l->next) | |
1438 | { | |
68952421 | 1439 | #ifdef OBJ_ELF |
3c83da8a JW |
1440 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1441 | S_SET_OTHER (l->label, STO_MIPS16); | |
1442 | #endif | |
1443 | if ((l->label->sy_value.X_add_number & 1) == 0) | |
1444 | ++l->label->sy_value.X_add_number; | |
1445 | } | |
1446 | } | |
1447 | } | |
1448 | ||
0dd2d296 ILT |
1449 | /* Output an instruction. PLACE is where to put the instruction; if |
1450 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1451 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1452 | used with RELOC_TYPE. */ | |
3d3c5039 | 1453 | |
3d3c5039 | 1454 | static void |
867a58b3 | 1455 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1456 | char *place; |
670a50eb ILT |
1457 | struct mips_cl_insn *ip; |
1458 | expressionS *address_expr; | |
1459 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1460 | boolean unmatched_hi; |
3d3c5039 | 1461 | { |
1aa6938e | 1462 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1463 | char *f; |
becfe05e ILT |
1464 | fixS *fixp; |
1465 | int nops = 0; | |
7e656649 RH |
1466 | /* start-sanitize-branchbug4011 */ |
1467 | int label_nop = 0; /* True if a no-op needs to appear between | |
1468 | the current insn and the current labels */ | |
1469 | /* end-sanitize-branchbug4011 */ | |
3d3c5039 | 1470 | |
3c83da8a JW |
1471 | /* Mark instruction labels in mips16 mode. */ |
1472 | if (mips_opts.mips16) | |
1473 | mips16_mark_labels (); | |
fbcfacb7 | 1474 | |
1aa6938e ILT |
1475 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1476 | pinfo = ip->insn_mo->pinfo; | |
1477 | ||
3c83da8a | 1478 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) |
becfe05e | 1479 | { |
4a1cb507 ILT |
1480 | int prev_prev_nop; |
1481 | ||
becfe05e | 1482 | /* If the previous insn required any delay slots, see if we need |
8358c818 | 1483 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1484 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1485 | (1) a load from memory delay |
1486 | (2) a load from a coprocessor delay | |
1487 | (3) an unconditional branch delay | |
1488 | (4) a conditional branch delay | |
1489 | (5) a move to coprocessor register delay | |
1490 | (6) a load coprocessor register from memory delay | |
1491 | (7) a coprocessor condition code delay | |
1492 | (8) a HI/LO special register delay | |
becfe05e ILT |
1493 | |
1494 | There are a lot of optimizations we could do that we don't. | |
1495 | In particular, we do not, in general, reorder instructions. | |
1496 | If you use gcc with optimization, it will reorder | |
1497 | instructions and generally do much more optimization then we | |
1498 | do here; repeating all that work in the assembler would only | |
1499 | benefit hand written assembly code, and does not seem worth | |
1500 | it. */ | |
1501 | ||
1502 | /* This is how a NOP is emitted. */ | |
cc5703cd | 1503 | #define emit_nop() \ |
3c83da8a | 1504 | (mips_opts.mips16 \ |
cc5703cd ILT |
1505 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ |
1506 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1507 | |
1508 | /* The previous insn might require a delay slot, depending upon | |
1509 | the contents of the current insn. */ | |
3c83da8a JW |
1510 | if (! mips_opts.mips16 |
1511 | && mips_opts.isa < 4 | |
5af96dce ILT |
1512 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1513 | && ! cop_interlocks) | |
5c6f5923 | 1514 | || (! gpr_interlocks |
d8a1c247 | 1515 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
8358c818 ILT |
1516 | { |
1517 | /* A load from a coprocessor or from memory. All load | |
1518 | delays delay the use of general register rt for one | |
1519 | instruction on the r3000. The r6000 and r4000 use | |
1520 | interlocks. */ | |
efec4a28 | 1521 | /* Itbl support may require additional care here. */ |
1aa6938e | 1522 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1523 | if (mips_optimize == 0 |
1524 | || insn_uses_reg (ip, | |
1525 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1526 | & OP_MASK_RT), | |
cc5703cd | 1527 | MIPS_GR_REG)) |
becfe05e ILT |
1528 | ++nops; |
1529 | } | |
3c83da8a JW |
1530 | else if (! mips_opts.mips16 |
1531 | && mips_opts.isa < 4 | |
5af96dce ILT |
1532 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1533 | && ! cop_interlocks) | |
3c83da8a | 1534 | || (mips_opts.isa < 2 |
d8a1c247 | 1535 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
becfe05e ILT |
1536 | { |
1537 | /* A generic coprocessor delay. The previous instruction | |
1538 | modified a coprocessor general or control register. If | |
1539 | it modified a control register, we need to avoid any | |
1540 | coprocessor instruction (this is probably not always | |
1541 | required, but it sometimes is). If it modified a general | |
1542 | register, we avoid using that register. | |
1543 | ||
8358c818 ILT |
1544 | On the r6000 and r4000 loading a coprocessor register |
1545 | from memory is interlocked, and does not require a delay. | |
1546 | ||
becfe05e ILT |
1547 | This case is not handled very well. There is no special |
1548 | knowledge of CP0 handling, and the coprocessors other | |
1549 | than the floating point unit are not distinguished at | |
1550 | all. */ | |
efec4a28 DP |
1551 | /* Itbl support may require additional care here. FIXME! |
1552 | Need to modify this to include knowledge about | |
1553 | user specified delays! */ | |
1aa6938e | 1554 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1555 | { |
0aa07269 ILT |
1556 | if (mips_optimize == 0 |
1557 | || insn_uses_reg (ip, | |
8358c818 ILT |
1558 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1559 | & OP_MASK_FT), | |
cc5703cd | 1560 | MIPS_FP_REG)) |
becfe05e ILT |
1561 | ++nops; |
1562 | } | |
1aa6938e | 1563 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1564 | { |
0aa07269 ILT |
1565 | if (mips_optimize == 0 |
1566 | || insn_uses_reg (ip, | |
8358c818 ILT |
1567 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1568 | & OP_MASK_FS), | |
cc5703cd | 1569 | MIPS_FP_REG)) |
becfe05e ILT |
1570 | ++nops; |
1571 | } | |
1572 | else | |
1573 | { | |
1574 | /* We don't know exactly what the previous instruction | |
1575 | does. If the current instruction uses a coprocessor | |
1576 | register, we must insert a NOP. If previous | |
1577 | instruction may set the condition codes, and the | |
1578 | current instruction uses them, we must insert two | |
1579 | NOPS. */ | |
efec4a28 | 1580 | /* Itbl support may require additional care here. */ |
0aa07269 | 1581 | if (mips_optimize == 0 |
1aa6938e ILT |
1582 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1583 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1584 | nops += 2; |
1aa6938e | 1585 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1586 | ++nops; |
1587 | } | |
1588 | } | |
3c83da8a JW |
1589 | else if (! mips_opts.mips16 |
1590 | && mips_opts.isa < 4 | |
344a8d61 JSC |
1591 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1592 | && ! cop_interlocks) | |
becfe05e ILT |
1593 | { |
1594 | /* The previous instruction sets the coprocessor condition | |
1595 | codes, but does not require a general coprocessor delay | |
1596 | (this means it is a floating point comparison | |
1597 | instruction). If this instruction uses the condition | |
1598 | codes, we need to insert a single NOP. */ | |
efec4a28 | 1599 | /* Itbl support may require additional care here. */ |
0aa07269 | 1600 | if (mips_optimize == 0 |
1aa6938e | 1601 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1602 | ++nops; |
1603 | } | |
1aa6938e | 1604 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1605 | { |
1606 | /* The previous instruction reads the LO register; if the | |
1607 | current instruction writes to the LO register, we must | |
3b35597c JL |
1608 | insert two NOPS. Some newer processors have interlocks. |
1609 | Also the tx39's multiply instructions can be exectuted | |
1610 | immediatly after a read from HI/LO (without the delay), | |
1611 | though the tx39's divide insns still do require the | |
1612 | delay. */ | |
1613 | if (! (hilo_interlocks | |
de484a06 | 1614 | || (mips_cpu == 3900 && (pinfo & INSN_MULT))) |
b2b8c24e ILT |
1615 | && (mips_optimize == 0 |
1616 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e | 1617 | nops += 2; |
2e23624e GRK |
1618 | /* Most mips16 branch insns don't have a delay slot. |
1619 | If a read from LO is immediately followed by a branch | |
1620 | to a write to LO we have a read followed by a write | |
1621 | less than 2 insns away. We assume the target of | |
1622 | a branch might be a write to LO, and insert a nop | |
1623 | between a read and an immediately following branch. */ | |
1624 | else if (mips_opts.mips16 | |
1625 | && (mips_optimize == 0 | |
1626 | || (pinfo & MIPS16_INSN_BRANCH))) | |
1627 | nops += 1; | |
becfe05e ILT |
1628 | } |
1629 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1630 | { | |
1631 | /* The previous instruction reads the HI register; if the | |
1632 | current instruction writes to the HI register, we must | |
3b35597c JL |
1633 | insert a NOP. Some newer processors have interlocks. |
1634 | Also the note tx39's multiply above. */ | |
1635 | if (! (hilo_interlocks | |
de484a06 | 1636 | || (mips_cpu == 3900 && (pinfo & INSN_MULT))) |
b2b8c24e ILT |
1637 | && (mips_optimize == 0 |
1638 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e | 1639 | nops += 2; |
2e23624e GRK |
1640 | /* Most mips16 branch insns don't have a delay slot. |
1641 | If a read from HI is immediately followed by a branch | |
1642 | to a write to HI we have a read followed by a write | |
1643 | less than 2 insns away. We assume the target of | |
1644 | a branch might be a write to HI, and insert a nop | |
1645 | between a read and an immediately following branch. */ | |
1646 | else if (mips_opts.mips16 | |
1647 | && (mips_optimize == 0 | |
1648 | || (pinfo & MIPS16_INSN_BRANCH))) | |
1649 | nops += 1; | |
becfe05e ILT |
1650 | } |
1651 | ||
4a1cb507 ILT |
1652 | /* If the previous instruction was in a noreorder section, then |
1653 | we don't want to insert the nop after all. */ | |
efec4a28 | 1654 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
1655 | if (prev_insn_unreordered) |
1656 | nops = 0; | |
1657 | ||
becfe05e ILT |
1658 | /* There are two cases which require two intervening |
1659 | instructions: 1) setting the condition codes using a move to | |
1660 | coprocessor instruction which requires a general coprocessor | |
1661 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1662 | or LO register and then writing to it (except on processors |
1663 | which have interlocks). If we are not already emitting a NOP | |
1664 | instruction, we must check for these cases compared to the | |
1665 | instruction previous to the previous instruction. */ | |
3c83da8a JW |
1666 | if ((! mips_opts.mips16 |
1667 | && mips_opts.isa < 4 | |
4a1cb507 ILT |
1668 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1669 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1670 | && (pinfo & INSN_READ_COND_CODE) | |
1671 | && ! cop_interlocks) | |
1672 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1673 | && (pinfo & INSN_WRITE_LO) | |
3b35597c | 1674 | && ! (hilo_interlocks |
de484a06 | 1675 | || (mips_cpu == 3900 && (pinfo & INSN_MULT)))) |
4a1cb507 ILT |
1676 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1677 | && (pinfo & INSN_WRITE_HI) | |
3b35597c | 1678 | && ! (hilo_interlocks |
de484a06 | 1679 | || (mips_cpu == 3900 && (pinfo & INSN_MULT))))) |
4a1cb507 ILT |
1680 | prev_prev_nop = 1; |
1681 | else | |
1682 | prev_prev_nop = 0; | |
1683 | ||
1684 | if (prev_prev_insn_unreordered) | |
1685 | prev_prev_nop = 0; | |
1686 | ||
1687 | if (prev_prev_nop && nops == 0) | |
becfe05e ILT |
1688 | ++nops; |
1689 | ||
0dd2d296 ILT |
1690 | /* If we are being given a nop instruction, don't bother with |
1691 | one of the nops we would otherwise output. This will only | |
1692 | happen when a nop instruction is used with mips_optimize set | |
1693 | to 0. */ | |
4a1cb507 | 1694 | if (nops > 0 |
3c83da8a JW |
1695 | && ! mips_opts.noreorder |
1696 | && ip->insn_opcode == (mips_opts.mips16 ? 0x6500 : 0)) | |
0dd2d296 ILT |
1697 | --nops; |
1698 | ||
7e656649 RH |
1699 | /* start-sanitize-branchbug4011 */ |
1700 | /* If we have a label on a branch insn, we need at least one no-op | |
1701 | between the label and the branch. The pinfo flags in this test | |
1702 | must cover all the kinds of branches. */ | |
1703 | if (mips_fix_4011_branch_bug | |
1704 | && insn_labels != NULL | |
1705 | && (ip->insn_mo->pinfo | |
1706 | & (INSN_UNCOND_BRANCH_DELAY | |
1707 | |INSN_COND_BRANCH_DELAY | |
1708 | |INSN_COND_BRANCH_LIKELY))) | |
1709 | { | |
1710 | label_nop = 1; | |
1711 | ||
1712 | /* Make sure we've got at least one nop. */ | |
1713 | if (nops == 0) | |
1714 | nops = 1; | |
1715 | } | |
1716 | ||
1717 | /* end-sanitize-branchbug4011 */ | |
becfe05e | 1718 | /* Now emit the right number of NOP instructions. */ |
3c83da8a | 1719 | if (nops > 0 && ! mips_opts.noreorder) |
becfe05e | 1720 | { |
5af96dce ILT |
1721 | fragS *old_frag; |
1722 | unsigned long old_frag_offset; | |
8c63448a | 1723 | int i; |
fbcfacb7 | 1724 | struct insn_label_list *l; |
8c63448a | 1725 | |
5af96dce ILT |
1726 | old_frag = frag_now; |
1727 | old_frag_offset = frag_now_fix (); | |
1728 | ||
7e656649 RH |
1729 | /* start-sanitize-branchbug4011 */ |
1730 | /* Emit the nops that should be before the label. */ | |
1731 | if (label_nop) | |
1732 | nops -= 1; | |
1733 | ||
1734 | /* end-sanitize-branchbug4011 */ | |
8c63448a | 1735 | for (i = 0; i < nops; i++) |
becfe05e | 1736 | emit_nop (); |
5af96dce | 1737 | |
af255ca0 | 1738 | if (listing) |
546f5536 ILT |
1739 | { |
1740 | listing_prev_line (); | |
1741 | /* We may be at the start of a variant frag. In case we | |
1742 | are, make sure there is enough space for the frag | |
1743 | after the frags created by listing_prev_line. The | |
1744 | argument to frag_grow here must be at least as large | |
1745 | as the argument to all other calls to frag_grow in | |
1746 | this file. We don't have to worry about being in the | |
1747 | middle of a variant frag, because the variants insert | |
1748 | all needed nop instructions themselves. */ | |
1749 | frag_grow (40); | |
1750 | } | |
5af96dce | 1751 | |
fbcfacb7 | 1752 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1753 | { |
fbcfacb7 ILT |
1754 | assert (S_GET_SEGMENT (l->label) == now_seg); |
1755 | l->label->sy_frag = frag_now; | |
1756 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
1757 | /* mips16 text labels are stored as odd. */ | |
3c83da8a | 1758 | if (mips_opts.mips16) |
fbcfacb7 | 1759 | ++l->label->sy_value.X_add_number; |
becfe05e | 1760 | } |
5af96dce ILT |
1761 | |
1762 | #ifndef NO_ECOFF_DEBUGGING | |
1763 | if (ECOFF_DEBUGGING) | |
1764 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1765 | #endif | |
7e656649 RH |
1766 | /* start-sanitize-branchbug4011 */ |
1767 | if (label_nop) | |
1768 | { | |
1769 | /* Emit the nop after the label, and return the | |
1770 | nop count to it's proper value. */ | |
1771 | emit_nop (); | |
1772 | nops += 1; | |
1773 | } | |
1774 | /* end-sanitize-branchbug4011 */ | |
becfe05e | 1775 | } |
4a1cb507 ILT |
1776 | else if (prev_nop_frag != NULL) |
1777 | { | |
1778 | /* We have a frag holding nops we may be able to remove. If | |
1779 | we don't need any nops, we can decrease the size of | |
1780 | prev_nop_frag by the size of one instruction. If we do | |
1781 | need some nops, we count them in prev_nops_required. */ | |
1782 | if (prev_nop_frag_since == 0) | |
1783 | { | |
1784 | if (nops == 0) | |
1785 | { | |
3c83da8a | 1786 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
4a1cb507 ILT |
1787 | --prev_nop_frag_holds; |
1788 | } | |
1789 | else | |
1790 | prev_nop_frag_required += nops; | |
1791 | } | |
1792 | else | |
1793 | { | |
1794 | if (prev_prev_nop == 0) | |
1795 | { | |
3c83da8a | 1796 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
4a1cb507 ILT |
1797 | --prev_nop_frag_holds; |
1798 | } | |
1799 | else | |
1800 | ++prev_nop_frag_required; | |
1801 | } | |
1802 | ||
1803 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1804 | prev_nop_frag = NULL; | |
1805 | ||
1806 | ++prev_nop_frag_since; | |
1807 | ||
1808 | /* Sanity check: by the time we reach the second instruction | |
1809 | after prev_nop_frag, we should have used up all the nops | |
1810 | one way or another. */ | |
1811 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1812 | } | |
becfe05e | 1813 | } |
4a1cb507 | 1814 | |
cc5703cd ILT |
1815 | if (reloc_type > BFD_RELOC_UNUSED) |
1816 | { | |
1817 | /* We need to set up a variant frag. */ | |
3c83da8a | 1818 | assert (mips_opts.mips16 && address_expr != NULL); |
cc5703cd | 1819 | f = frag_var (rs_machine_dependent, 4, 0, |
8728fa92 | 1820 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
a677feeb ILT |
1821 | mips16_small, mips16_ext, |
1822 | (prev_pinfo | |
1823 | & INSN_UNCOND_BRANCH_DELAY), | |
1824 | (prev_insn_reloc_type | |
1825 | == BFD_RELOC_MIPS16_JMP)), | |
f59fb6ca | 1826 | make_expr_symbol (address_expr), (offsetT) 0, |
cc5703cd ILT |
1827 | (char *) NULL); |
1828 | } | |
1829 | else if (place != NULL) | |
0dd2d296 | 1830 | f = place; |
3c83da8a JW |
1831 | else if (mips_opts.mips16 |
1832 | && ! ip->use_extend | |
1833 | && reloc_type != BFD_RELOC_MIPS16_JMP) | |
08e17202 ILT |
1834 | { |
1835 | /* Make sure there is enough room to swap this instruction with | |
1836 | a following jump instruction. */ | |
1837 | frag_grow (6); | |
1838 | f = frag_more (2); | |
1839 | } | |
cc5703cd | 1840 | else |
035936da | 1841 | { |
3c83da8a JW |
1842 | if (mips_opts.mips16 |
1843 | && mips_opts.noreorder | |
035936da | 1844 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) |
48401fcf | 1845 | as_warn (_("extended instruction in delay slot")); |
035936da ILT |
1846 | |
1847 | f = frag_more (4); | |
1848 | } | |
1849 | ||
becfe05e | 1850 | fixp = NULL; |
cc5703cd | 1851 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1852 | { |
5ac34ac3 | 1853 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1854 | { |
1855 | switch (reloc_type) | |
1856 | { | |
3d3c5039 | 1857 | case BFD_RELOC_32: |
670a50eb ILT |
1858 | ip->insn_opcode |= address_expr->X_add_number; |
1859 | break; | |
3d3c5039 ILT |
1860 | |
1861 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1862 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1863 | break; | |
3d3c5039 ILT |
1864 | |
1865 | case BFD_RELOC_MIPS_JMP: | |
39bb58e0 | 1866 | if ((address_expr->X_add_number & 3) != 0) |
48401fcf | 1867 | as_bad (_("jump to misaligned address (0x%lx)"), |
39bb58e0 | 1868 | (unsigned long) address_expr->X_add_number); |
5e1e8f23 ILT |
1869 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1870 | break; | |
1871 | ||
cc5703cd | 1872 | case BFD_RELOC_MIPS16_JMP: |
39bb58e0 | 1873 | if ((address_expr->X_add_number & 3) != 0) |
48401fcf | 1874 | as_bad (_("jump to misaligned address (0x%lx)"), |
39bb58e0 | 1875 | (unsigned long) address_expr->X_add_number); |
cc5703cd ILT |
1876 | ip->insn_opcode |= |
1877 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1878 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1879 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1880 | break; | |
1881 | ||
3c69baf9 | 1882 | /* start-sanitize-r5900 */ |
0bc0e337 JL |
1883 | case BFD_RELOC_MIPS15_S3: |
1884 | ip->insn_opcode |= ((imm_expr.X_add_number & 0x7fff) >> 3) << 6; | |
1885 | break; | |
3c69baf9 | 1886 | /* end-sanitize-r5900 */ |
0bc0e337 | 1887 | |
3d3c5039 | 1888 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1889 | goto need_reloc; |
3d3c5039 ILT |
1890 | |
1891 | default: | |
670a50eb | 1892 | internalError (); |
3d3c5039 | 1893 | } |
670a50eb ILT |
1894 | } |
1895 | else | |
1896 | { | |
3d3c5039 | 1897 | need_reloc: |
0dd2d296 ILT |
1898 | /* Don't generate a reloc if we are writing into a variant |
1899 | frag. */ | |
1900 | if (place == NULL) | |
867a58b3 ILT |
1901 | { |
1902 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1903 | address_expr, | |
1904 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1905 | reloc_type); | |
1906 | if (unmatched_hi) | |
1907 | { | |
1908 | struct mips_hi_fixup *hi_fixup; | |
1909 | ||
1910 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1911 | hi_fixup = ((struct mips_hi_fixup *) | |
1912 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1913 | hi_fixup->fixp = fixp; | |
1914 | hi_fixup->seg = now_seg; | |
1915 | hi_fixup->next = mips_hi_fixup_list; | |
1916 | mips_hi_fixup_list = hi_fixup; | |
1917 | } | |
1918 | } | |
3d3c5039 ILT |
1919 | } |
1920 | } | |
becfe05e | 1921 | |
3c83da8a | 1922 | if (! mips_opts.mips16) |
cc5703cd | 1923 | md_number_to_chars (f, ip->insn_opcode, 4); |
16262668 ILT |
1924 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) |
1925 | { | |
1926 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1927 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1928 | } | |
cc5703cd ILT |
1929 | else |
1930 | { | |
1931 | if (ip->use_extend) | |
1932 | { | |
1933 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1934 | f += 2; | |
1935 | } | |
1936 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1937 | } | |
670a50eb | 1938 | |
1aa6938e | 1939 | /* Update the register mask information. */ |
3c83da8a | 1940 | if (! mips_opts.mips16) |
cc5703cd ILT |
1941 | { |
1942 | if (pinfo & INSN_WRITE_GPR_D) | |
1943 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1944 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1945 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1946 | if (pinfo & INSN_READ_GPR_S) | |
1947 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1948 | if (pinfo & INSN_WRITE_GPR_31) | |
1949 | mips_gprmask |= 1 << 31; | |
1950 | if (pinfo & INSN_WRITE_FPR_D) | |
1951 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1952 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1953 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1954 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1955 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1956 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1957 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1958 | if (pinfo & INSN_COP) | |
1959 | { | |
efec4a28 DP |
1960 | /* We don't keep enough information to sort these cases out. |
1961 | The itbl support does keep this information however, although | |
1962 | we currently don't support itbl fprmats as part of the cop | |
1963 | instruction. May want to add this support in the future. */ | |
cc5703cd ILT |
1964 | } |
1965 | /* Never set the bit for $0, which is always zero. */ | |
1966 | mips_gprmask &=~ 1 << 0; | |
1967 | } | |
1968 | else | |
1aa6938e | 1969 | { |
cc5703cd ILT |
1970 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1971 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1972 | & MIPS16OP_MASK_RX); | |
1973 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1974 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1975 | & MIPS16OP_MASK_RY); | |
1976 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1977 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1978 | & MIPS16OP_MASK_RZ); | |
1979 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1980 | mips_gprmask |= 1 << TREG; | |
1981 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1982 | mips_gprmask |= 1 << SP; | |
1983 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1984 | mips_gprmask |= 1 << RA; | |
1985 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1986 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1987 | if (pinfo & MIPS16_INSN_READ_Z) | |
1988 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1989 | & MIPS16OP_MASK_MOVE32Z); | |
1990 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1991 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1992 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1993 | } |
1aa6938e | 1994 | |
3c83da8a | 1995 | if (place == NULL && ! mips_opts.noreorder) |
670a50eb | 1996 | { |
becfe05e ILT |
1997 | /* Filling the branch delay slot is more complex. We try to |
1998 | switch the branch with the previous instruction, which we can | |
1999 | do if the previous instruction does not set up a condition | |
2000 | that the branch tests and if the branch is not itself the | |
2001 | target of any branch. */ | |
1aa6938e ILT |
2002 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
2003 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 2004 | { |
0aa07269 | 2005 | if (mips_optimize < 2 |
19ed8960 ILT |
2006 | /* If we have seen .set volatile or .set nomove, don't |
2007 | optimize. */ | |
3c83da8a | 2008 | || mips_opts.nomove != 0 |
4e95866e ILT |
2009 | /* If we had to emit any NOP instructions, then we |
2010 | already know we can not swap. */ | |
2011 | || nops != 0 | |
becfe05e ILT |
2012 | /* If we don't even know the previous insn, we can not |
2013 | swap. */ | |
2014 | || ! prev_insn_valid | |
2015 | /* If the previous insn is already in a branch delay | |
2016 | slot, then we can not swap. */ | |
2017 | || prev_insn_is_delay_slot | |
7e656649 RH |
2018 | /* start-sanitize-branchbug4011 */ |
2019 | /* We can't swap the branch back to a previous label */ | |
2020 | || (mips_fix_4011_branch_bug && prev_insn_labels) | |
2021 | /* end-sanitize-branchbug4011 */ | |
4e95866e ILT |
2022 | /* If the previous previous insn was in a .set |
2023 | noreorder, we can't swap. Actually, the MIPS | |
2024 | assembler will swap in this situation. However, gcc | |
2025 | configured -with-gnu-as will generate code like | |
2026 | .set noreorder | |
2027 | lw $4,XXX | |
2028 | .set reorder | |
2029 | INSN | |
2030 | bne $4,$0,foo | |
2031 | in which we can not swap the bne and INSN. If gcc is | |
2032 | not configured -with-gnu-as, it does not output the | |
2033 | .set pseudo-ops. We don't have to check | |
2034 | prev_insn_unreordered, because prev_insn_valid will | |
2035 | be 0 in that case. We don't want to use | |
2036 | prev_prev_insn_valid, because we do want to be able | |
2037 | to swap at the start of a function. */ | |
2038 | || prev_prev_insn_unreordered | |
becfe05e ILT |
2039 | /* If the branch is itself the target of a branch, we |
2040 | can not swap. We cheat on this; all we check for is | |
2041 | whether there is a label on this instruction. If | |
2042 | there are any branches to anything other than a | |
2043 | label, users must use .set noreorder. */ | |
fbcfacb7 | 2044 | || insn_labels != NULL |
777ad64d | 2045 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
2046 | can not do the swap. This does not apply to the |
2047 | mips16, which uses variant frags for different | |
2048 | purposes. */ | |
3c83da8a | 2049 | || (! mips_opts.mips16 |
cc5703cd | 2050 | && prev_insn_frag->fr_type == rs_machine_dependent) |
becfe05e ILT |
2051 | /* If the branch reads the condition codes, we don't |
2052 | even try to swap, because in the sequence | |
2053 | ctc1 $X,$31 | |
2054 | INSN | |
2055 | INSN | |
2056 | bc1t LABEL | |
2057 | we can not swap, and I don't feel like handling that | |
2058 | case. */ | |
3c83da8a JW |
2059 | || (! mips_opts.mips16 |
2060 | && mips_opts.isa < 4 | |
d8a1c247 | 2061 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
2062 | /* We can not swap with an instruction that requires a |
2063 | delay slot, becase the target of the branch might | |
2064 | interfere with that instruction. */ | |
3c83da8a JW |
2065 | || (! mips_opts.mips16 |
2066 | && mips_opts.isa < 4 | |
d8a1c247 | 2067 | && (prev_pinfo |
efec4a28 | 2068 | /* Itbl support may require additional care here. */ |
d8a1c247 KR |
2069 | & (INSN_LOAD_COPROC_DELAY |
2070 | | INSN_COPROC_MOVE_DELAY | |
2071 | | INSN_WRITE_COND_CODE))) | |
de484a06 JB |
2072 | || (! (hilo_interlocks |
2073 | || (mips_cpu == 3900 && (pinfo & INSN_MULT))) | |
b2b8c24e ILT |
2074 | && (prev_pinfo |
2075 | & (INSN_READ_LO | |
2076 | | INSN_READ_HI))) | |
5c6f5923 GRK |
2077 | || (! mips_opts.mips16 |
2078 | && ! gpr_interlocks | |
2079 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
3c83da8a JW |
2080 | || (! mips_opts.mips16 |
2081 | && mips_opts.isa < 2 | |
5c6f5923 GRK |
2082 | /* Itbl support may require additional care here. */ |
2083 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) | |
becfe05e | 2084 | /* We can not swap with a branch instruction. */ |
1aa6938e | 2085 | || (prev_pinfo |
6e8dda9c ILT |
2086 | & (INSN_UNCOND_BRANCH_DELAY |
2087 | | INSN_COND_BRANCH_DELAY | |
2088 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
2089 | /* We do not swap with a trap instruction, since it |
2090 | complicates trap handlers to have the trap | |
2091 | instruction be in a delay slot. */ | |
1aa6938e | 2092 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
2093 | /* If the branch reads a register that the previous |
2094 | instruction sets, we can not swap. */ | |
3c83da8a | 2095 | || (! mips_opts.mips16 |
cc5703cd | 2096 | && (prev_pinfo & INSN_WRITE_GPR_T) |
becfe05e ILT |
2097 | && insn_uses_reg (ip, |
2098 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2099 | & OP_MASK_RT), | |
cc5703cd | 2100 | MIPS_GR_REG)) |
3c83da8a | 2101 | || (! mips_opts.mips16 |
cc5703cd | 2102 | && (prev_pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
2103 | && insn_uses_reg (ip, |
2104 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2105 | & OP_MASK_RD), | |
cc5703cd | 2106 | MIPS_GR_REG)) |
3c83da8a | 2107 | || (mips_opts.mips16 |
cc5703cd ILT |
2108 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) |
2109 | && insn_uses_reg (ip, | |
2110 | ((prev_insn.insn_opcode | |
2111 | >> MIPS16OP_SH_RX) | |
2112 | & MIPS16OP_MASK_RX), | |
2113 | MIPS16_REG)) | |
2114 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2115 | && insn_uses_reg (ip, | |
2116 | ((prev_insn.insn_opcode | |
2117 | >> MIPS16OP_SH_RY) | |
2118 | & MIPS16OP_MASK_RY), | |
2119 | MIPS16_REG)) | |
2120 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2121 | && insn_uses_reg (ip, | |
2122 | ((prev_insn.insn_opcode | |
2123 | >> MIPS16OP_SH_RZ) | |
2124 | & MIPS16OP_MASK_RZ), | |
2125 | MIPS16_REG)) | |
2126 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2127 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2128 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2129 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2130 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2131 | && insn_uses_reg (ip, | |
2132 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2133 | insn_opcode), | |
2134 | MIPS_GR_REG)))) | |
1849d646 ILT |
2135 | /* If the branch writes a register that the previous |
2136 | instruction sets, we can not swap (we know that | |
2137 | branches write only to RD or to $31). */ | |
3c83da8a | 2138 | || (! mips_opts.mips16 |
cc5703cd | 2139 | && (prev_pinfo & INSN_WRITE_GPR_T) |
1aa6938e | 2140 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
2141 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
2142 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 2143 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
2144 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
2145 | & OP_MASK_RT) | |
2146 | == 31)))) | |
3c83da8a | 2147 | || (! mips_opts.mips16 |
cc5703cd | 2148 | && (prev_pinfo & INSN_WRITE_GPR_D) |
1aa6938e | 2149 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
2150 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
2151 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 2152 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
2153 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
2154 | & OP_MASK_RD) | |
2155 | == 31)))) | |
3c83da8a | 2156 | || (mips_opts.mips16 |
cc5703cd ILT |
2157 | && (pinfo & MIPS16_INSN_WRITE_31) |
2158 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2159 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2160 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2161 | == RA)))) | |
becfe05e ILT |
2162 | /* If the branch writes a register that the previous |
2163 | instruction reads, we can not swap (we know that | |
2164 | branches only write to RD or to $31). */ | |
3c83da8a | 2165 | || (! mips_opts.mips16 |
cc5703cd | 2166 | && (pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
2167 | && insn_uses_reg (&prev_insn, |
2168 | ((ip->insn_opcode >> OP_SH_RD) | |
2169 | & OP_MASK_RD), | |
cc5703cd | 2170 | MIPS_GR_REG)) |
3c83da8a | 2171 | || (! mips_opts.mips16 |
cc5703cd ILT |
2172 | && (pinfo & INSN_WRITE_GPR_31) |
2173 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
3c83da8a | 2174 | || (mips_opts.mips16 |
cc5703cd ILT |
2175 | && (pinfo & MIPS16_INSN_WRITE_31) |
2176 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
2177 | /* If we are generating embedded PIC code, the branch |
2178 | might be expanded into a sequence which uses $at, so | |
2179 | we can't swap with an instruction which reads it. */ | |
2180 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 2181 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
2182 | /* If the previous previous instruction has a load |
2183 | delay, and sets a register that the branch reads, we | |
2184 | can not swap. */ | |
3c83da8a JW |
2185 | || (! mips_opts.mips16 |
2186 | && mips_opts.isa < 4 | |
efec4a28 | 2187 | /* Itbl support may require additional care here. */ |
d8a1c247 | 2188 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
5c6f5923 | 2189 | || (! gpr_interlocks |
d8a1c247 KR |
2190 | && (prev_prev_insn.insn_mo->pinfo |
2191 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
2192 | && insn_uses_reg (ip, |
2193 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2194 | & OP_MASK_RT), | |
cc5703cd | 2195 | MIPS_GR_REG)) |
d31a3f5e ILT |
2196 | /* If one instruction sets a condition code and the |
2197 | other one uses a condition code, we can not swap. */ | |
2198 | || ((pinfo & INSN_READ_COND_CODE) | |
2199 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2200 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
2201 | && (prev_pinfo & INSN_READ_COND_CODE)) |
2202 | /* If the previous instruction uses the PC, we can not | |
2203 | swap. */ | |
3c83da8a | 2204 | || (mips_opts.mips16 |
cc5703cd ILT |
2205 | && (prev_pinfo & MIPS16_INSN_READ_PC)) |
2206 | /* If the previous instruction was extended, we can not | |
2207 | swap. */ | |
3c83da8a | 2208 | || (mips_opts.mips16 && prev_insn_extended) |
cc5703cd ILT |
2209 | /* If the previous instruction had a fixup in mips16 |
2210 | mode, we can not swap. This normally means that the | |
2211 | previous instruction was a 4 byte branch anyhow. */ | |
d734c861 DE |
2212 | || (mips_opts.mips16 && prev_insn_fixp) |
2213 | /* If the previous instruction is a sync, sync.l, or | |
2214 | sync.p, we can not swap. */ | |
2215 | || (prev_pinfo && INSN_SYNC)) | |
becfe05e ILT |
2216 | { |
2217 | /* We could do even better for unconditional branches to | |
2218 | portions of this object file; we could pick up the | |
2219 | instruction at the destination, put it in the delay | |
2220 | slot, and bump the destination address. */ | |
2221 | emit_nop (); | |
2222 | /* Update the previous insn information. */ | |
2223 | prev_prev_insn = *ip; | |
2224 | prev_insn.insn_mo = &dummy_opcode; | |
2225 | } | |
2226 | else | |
2227 | { | |
becfe05e | 2228 | /* It looks like we can actually do the swap. */ |
3c83da8a | 2229 | if (! mips_opts.mips16) |
cc5703cd ILT |
2230 | { |
2231 | char *prev_f; | |
2232 | char temp[4]; | |
2233 | ||
2234 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2235 | memcpy (temp, prev_f, 4); | |
2236 | memcpy (prev_f, f, 4); | |
2237 | memcpy (f, temp, 4); | |
2238 | if (prev_insn_fixp) | |
2239 | { | |
2240 | prev_insn_fixp->fx_frag = frag_now; | |
2241 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
2242 | } | |
2243 | if (fixp) | |
2244 | { | |
2245 | fixp->fx_frag = prev_insn_frag; | |
2246 | fixp->fx_where = prev_insn_where; | |
2247 | } | |
2248 | } | |
cc5703cd | 2249 | else |
becfe05e | 2250 | { |
cc5703cd ILT |
2251 | char *prev_f; |
2252 | char temp[2]; | |
2253 | ||
2254 | assert (prev_insn_fixp == NULL); | |
2255 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2256 | memcpy (temp, prev_f, 2); | |
2257 | memcpy (prev_f, f, 2); | |
2258 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
9cd4e6cc ILT |
2259 | { |
2260 | assert (reloc_type == BFD_RELOC_UNUSED); | |
2261 | memcpy (f, temp, 2); | |
2262 | } | |
cc5703cd ILT |
2263 | else |
2264 | { | |
2265 | memcpy (f, f + 2, 2); | |
2266 | memcpy (f + 2, temp, 2); | |
2267 | } | |
2268 | if (fixp) | |
2269 | { | |
2270 | fixp->fx_frag = prev_insn_frag; | |
2271 | fixp->fx_where = prev_insn_where; | |
2272 | } | |
becfe05e | 2273 | } |
cc5703cd | 2274 | |
becfe05e ILT |
2275 | /* Update the previous insn information; leave prev_insn |
2276 | unchanged. */ | |
2277 | prev_prev_insn = *ip; | |
2278 | } | |
2279 | prev_insn_is_delay_slot = 1; | |
2280 | ||
2281 | /* If that was an unconditional branch, forget the previous | |
2282 | insn information. */ | |
1aa6938e | 2283 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
2284 | { |
2285 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2286 | prev_insn.insn_mo = &dummy_opcode; | |
2287 | } | |
a677feeb ILT |
2288 | |
2289 | prev_insn_fixp = NULL; | |
2290 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2291 | prev_insn_extended = 0; | |
becfe05e | 2292 | } |
1aa6938e | 2293 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
2294 | { |
2295 | /* We don't yet optimize a branch likely. What we should do | |
2296 | is look at the target, copy the instruction found there | |
2297 | into the delay slot, and increment the branch to jump to | |
2298 | the next instruction. */ | |
2299 | emit_nop (); | |
2300 | /* Update the previous insn information. */ | |
2301 | prev_prev_insn = *ip; | |
2302 | prev_insn.insn_mo = &dummy_opcode; | |
a677feeb ILT |
2303 | prev_insn_fixp = NULL; |
2304 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2305 | prev_insn_extended = 0; | |
8358c818 | 2306 | } |
becfe05e | 2307 | else |
670a50eb | 2308 | { |
becfe05e ILT |
2309 | /* Update the previous insn information. */ |
2310 | if (nops > 0) | |
2311 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2312 | else | |
2313 | prev_prev_insn = prev_insn; | |
2314 | prev_insn = *ip; | |
2315 | ||
2316 | /* Any time we see a branch, we always fill the delay slot | |
2317 | immediately; since this insn is not a branch, we know it | |
2318 | is not in a delay slot. */ | |
2319 | prev_insn_is_delay_slot = 0; | |
a677feeb ILT |
2320 | |
2321 | prev_insn_fixp = fixp; | |
2322 | prev_insn_reloc_type = reloc_type; | |
3c83da8a | 2323 | if (mips_opts.mips16) |
a677feeb ILT |
2324 | prev_insn_extended = (ip->use_extend |
2325 | || reloc_type > BFD_RELOC_UNUSED); | |
becfe05e ILT |
2326 | } |
2327 | ||
4e95866e ILT |
2328 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2329 | prev_insn_unreordered = 0; | |
becfe05e ILT |
2330 | prev_insn_frag = frag_now; |
2331 | prev_insn_where = f - frag_now->fr_literal; | |
becfe05e | 2332 | prev_insn_valid = 1; |
7e656649 RH |
2333 | /* start-sanitize-branchbug4011 */ |
2334 | prev_insn_labels = !! insn_labels; | |
2335 | /* end-sanitize-branchbug4011 */ | |
becfe05e | 2336 | } |
fbcfacb7 | 2337 | else if (place == NULL) |
a677feeb | 2338 | { |
fbcfacb7 | 2339 | /* We need to record a bit of information even when we are not |
a677feeb ILT |
2340 | reordering, in order to determine the base address for mips16 |
2341 | PC relative relocs. */ | |
4a1cb507 | 2342 | prev_prev_insn = prev_insn; |
a677feeb ILT |
2343 | prev_insn = *ip; |
2344 | prev_insn_reloc_type = reloc_type; | |
4a1cb507 ILT |
2345 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2346 | prev_insn_unreordered = 1; | |
7e656649 RH |
2347 | /* start-sanitize-branchbug4011 */ |
2348 | prev_insn_labels = !! insn_labels; | |
2349 | /* end-sanitize-branchbug4011 */ | |
a677feeb | 2350 | } |
3d3c5039 | 2351 | |
becfe05e | 2352 | /* We just output an insn, so the next one doesn't have a label. */ |
fbcfacb7 | 2353 | mips_clear_insn_labels (); |
b073d428 ILT |
2354 | |
2355 | /* We must ensure that a fixup associated with an unmatched %hi | |
2356 | reloc does not become a variant frag. Otherwise, the | |
2357 | rearrangement of %hi relocs in frob_file may confuse | |
2358 | tc_gen_reloc. */ | |
2359 | if (unmatched_hi) | |
2360 | { | |
2361 | frag_wane (frag_now); | |
2362 | frag_new (0); | |
2363 | } | |
becfe05e ILT |
2364 | } |
2365 | ||
2366 | /* This function forgets that there was any previous instruction or | |
4a1cb507 ILT |
2367 | label. If PRESERVE is non-zero, it remembers enough information to |
2368 | know whether nops are needed before a noreorder section. */ | |
becfe05e ILT |
2369 | |
2370 | static void | |
4a1cb507 ILT |
2371 | mips_no_prev_insn (preserve) |
2372 | int preserve; | |
becfe05e | 2373 | { |
4a1cb507 ILT |
2374 | if (! preserve) |
2375 | { | |
2376 | prev_insn.insn_mo = &dummy_opcode; | |
2377 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2378 | prev_nop_frag = NULL; | |
2379 | prev_nop_frag_holds = 0; | |
2380 | prev_nop_frag_required = 0; | |
2381 | prev_nop_frag_since = 0; | |
2382 | } | |
becfe05e ILT |
2383 | prev_insn_valid = 0; |
2384 | prev_insn_is_delay_slot = 0; | |
4e95866e | 2385 | prev_insn_unreordered = 0; |
cc5703cd | 2386 | prev_insn_extended = 0; |
7e656649 RH |
2387 | /* start-sanitize-branchbug4011 */ |
2388 | prev_insn_labels = 0; | |
2389 | /* end-sanitize-branchbug4011 */ | |
a677feeb | 2390 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
4e95866e | 2391 | prev_prev_insn_unreordered = 0; |
fbcfacb7 | 2392 | mips_clear_insn_labels (); |
becfe05e ILT |
2393 | } |
2394 | ||
2395 | /* This function must be called whenever we turn on noreorder or emit | |
2396 | something other than instructions. It inserts any NOPS which might | |
2397 | be needed by the previous instruction, and clears the information | |
fbcfacb7 ILT |
2398 | kept for the previous instructions. The INSNS parameter is true if |
2399 | instructions are to follow. */ | |
becfe05e ILT |
2400 | |
2401 | static void | |
fbcfacb7 ILT |
2402 | mips_emit_delays (insns) |
2403 | boolean insns; | |
becfe05e | 2404 | { |
3c83da8a | 2405 | if (! mips_opts.noreorder) |
becfe05e | 2406 | { |
4a1cb507 | 2407 | int nops; |
becfe05e | 2408 | |
4a1cb507 | 2409 | nops = 0; |
3c83da8a JW |
2410 | if ((! mips_opts.mips16 |
2411 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2412 | && (! cop_interlocks |
2413 | && (prev_insn.insn_mo->pinfo | |
2414 | & (INSN_LOAD_COPROC_DELAY | |
2415 | | INSN_COPROC_MOVE_DELAY | |
2416 | | INSN_WRITE_COND_CODE)))) | |
5c6f5923 | 2417 | || (! hilo_interlocks |
b2b8c24e ILT |
2418 | && (prev_insn.insn_mo->pinfo |
2419 | & (INSN_READ_LO | |
2420 | | INSN_READ_HI))) | |
5c6f5923 GRK |
2421 | || (! mips_opts.mips16 |
2422 | && ! gpr_interlocks | |
2423 | && (prev_insn.insn_mo->pinfo | |
2424 | & INSN_LOAD_MEMORY_DELAY)) | |
3c83da8a JW |
2425 | || (! mips_opts.mips16 |
2426 | && mips_opts.isa < 2 | |
8358c818 | 2427 | && (prev_insn.insn_mo->pinfo |
5c6f5923 | 2428 | & INSN_COPROC_MEMORY_DELAY))) |
becfe05e | 2429 | { |
efec4a28 | 2430 | /* Itbl support may require additional care here. */ |
4a1cb507 | 2431 | ++nops; |
3c83da8a JW |
2432 | if ((! mips_opts.mips16 |
2433 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2434 | && (! cop_interlocks |
2435 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
5c6f5923 | 2436 | || (! hilo_interlocks |
b2b8c24e ILT |
2437 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2438 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 ILT |
2439 | ++nops; |
2440 | ||
2441 | if (prev_insn_unreordered) | |
2442 | nops = 0; | |
becfe05e | 2443 | } |
3c83da8a JW |
2444 | else if ((! mips_opts.mips16 |
2445 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2446 | && (! cop_interlocks |
2447 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
5c6f5923 | 2448 | || (! hilo_interlocks |
b2b8c24e ILT |
2449 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2450 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 | 2451 | { |
efec4a28 | 2452 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
2453 | if (! prev_prev_insn_unreordered) |
2454 | ++nops; | |
2455 | } | |
2456 | ||
2457 | if (nops > 0) | |
670a50eb | 2458 | { |
fbcfacb7 ILT |
2459 | struct insn_label_list *l; |
2460 | ||
4a1cb507 ILT |
2461 | if (insns) |
2462 | { | |
2463 | /* Record the frag which holds the nop instructions, so | |
2464 | that we can remove them if we don't need them. */ | |
3c83da8a | 2465 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); |
4a1cb507 ILT |
2466 | prev_nop_frag = frag_now; |
2467 | prev_nop_frag_holds = nops; | |
2468 | prev_nop_frag_required = 0; | |
2469 | prev_nop_frag_since = 0; | |
2470 | } | |
2471 | ||
2472 | for (; nops > 0; --nops) | |
2473 | emit_nop (); | |
2474 | ||
2475 | if (insns) | |
2476 | { | |
2477 | /* Move on to a new frag, so that it is safe to simply | |
2478 | decrease the size of prev_nop_frag. */ | |
2479 | frag_wane (frag_now); | |
2480 | frag_new (0); | |
2481 | } | |
2482 | ||
fbcfacb7 | 2483 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 2484 | { |
fbcfacb7 ILT |
2485 | assert (S_GET_SEGMENT (l->label) == now_seg); |
2486 | l->label->sy_frag = frag_now; | |
2487 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
2488 | /* mips16 text labels are stored as odd. */ | |
3c83da8a | 2489 | if (mips_opts.mips16) |
fbcfacb7 | 2490 | ++l->label->sy_value.X_add_number; |
becfe05e | 2491 | } |
3d3c5039 ILT |
2492 | } |
2493 | } | |
0221ddf7 | 2494 | |
3c83da8a JW |
2495 | /* Mark instruction labels in mips16 mode. */ |
2496 | if (mips_opts.mips16 && insns) | |
2497 | mips16_mark_labels (); | |
fbcfacb7 | 2498 | |
4a1cb507 | 2499 | mips_no_prev_insn (insns); |
3d3c5039 ILT |
2500 | } |
2501 | ||
670a50eb ILT |
2502 | /* Build an instruction created by a macro expansion. This is passed |
2503 | a pointer to the count of instructions created so far, an | |
2504 | expression, the name of the instruction to build, an operand format | |
2505 | string, and corresponding arguments. */ | |
2506 | ||
1dc1e798 | 2507 | #ifdef USE_STDARG |
3d3c5039 | 2508 | static void |
0dd2d296 ILT |
2509 | macro_build (char *place, |
2510 | int *counter, | |
670a50eb | 2511 | expressionS * ep, |
3d3c5039 ILT |
2512 | const char *name, |
2513 | const char *fmt, | |
2514 | ...) | |
1dc1e798 | 2515 | #else |
3d3c5039 | 2516 | static void |
0dd2d296 ILT |
2517 | macro_build (place, counter, ep, name, fmt, va_alist) |
2518 | char *place; | |
3d3c5039 ILT |
2519 | int *counter; |
2520 | expressionS *ep; | |
2521 | const char *name; | |
2522 | const char *fmt; | |
2523 | va_dcl | |
1dc1e798 | 2524 | #endif |
3d3c5039 | 2525 | { |
670a50eb ILT |
2526 | struct mips_cl_insn insn; |
2527 | bfd_reloc_code_real_type r; | |
2528 | va_list args; | |
931a1858 | 2529 | int insn_isa; |
3d3c5039 | 2530 | |
1dc1e798 | 2531 | #ifdef USE_STDARG |
670a50eb | 2532 | va_start (args, fmt); |
3d3c5039 | 2533 | #else |
670a50eb | 2534 | va_start (args); |
3d3c5039 ILT |
2535 | #endif |
2536 | ||
670a50eb ILT |
2537 | /* |
2538 | * If the macro is about to expand into a second instruction, | |
2539 | * print a warning if needed. We need to pass ip as a parameter | |
2540 | * to generate a better warning message here... | |
2541 | */ | |
3c83da8a | 2542 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
48401fcf | 2543 | as_warn (_("Macro instruction expanded into multiple instructions")); |
670a50eb | 2544 | |
0dd2d296 ILT |
2545 | if (place == NULL) |
2546 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 2547 | |
3c83da8a | 2548 | if (mips_opts.mips16) |
cc5703cd ILT |
2549 | { |
2550 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2551 | va_end (args); | |
2552 | return; | |
2553 | } | |
2554 | ||
670a50eb ILT |
2555 | r = BFD_RELOC_UNUSED; |
2556 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2557 | assert (insn.insn_mo); | |
2558 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2559 | ||
931a1858 JL |
2560 | /* Search until we get a match for NAME. */ |
2561 | while (1) | |
670a50eb | 2562 | { |
1c6f3441 | 2563 | if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA1) |
931a1858 JL |
2564 | insn_isa = 1; |
2565 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA2) | |
2566 | insn_isa = 2; | |
2567 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA3) | |
2568 | insn_isa = 3; | |
2569 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA4) | |
2570 | insn_isa = 4; | |
2571 | else | |
2572 | insn_isa = 15; | |
2573 | ||
a652f74c ILT |
2574 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2575 | && insn.insn_mo->pinfo != INSN_MACRO | |
2576 | && (insn_isa <= mips_opts.isa | |
de484a06 | 2577 | || (mips_cpu == 4650 |
a652f74c | 2578 | && (insn.insn_mo->membership & INSN_4650) != 0) |
de484a06 | 2579 | || (mips_cpu == 4010 |
a652f74c | 2580 | && (insn.insn_mo->membership & INSN_4010) != 0) |
de484a06 JB |
2581 | || ((mips_cpu == 4100 |
2582 | /* start-sanitize-vr4xxx */ | |
2583 | || mips_cpu == 4111 | |
2584 | /* end-sanitize-vr4xxx */ | |
2585 | ) | |
a652f74c | 2586 | && (insn.insn_mo->membership & INSN_4100) != 0) |
f14397f0 | 2587 | /* start-sanitize-vr4xxx */ |
de484a06 | 2588 | || (mips_cpu == 4121 |
f14397f0 GRK |
2589 | && (insn.insn_mo->membership & INSN_4121) != 0) |
2590 | /* end-sanitize-vr4xxx */ | |
2d035a50 | 2591 | /* start-sanitize-vr4320 */ |
de484a06 | 2592 | || (mips_cpu == 4320 |
2d035a50 GRK |
2593 | && (insn.insn_mo->membership & INSN_4320) != 0) |
2594 | /* end-sanitize-vr4320 */ | |
42444087 | 2595 | /* start-sanitize-tx49 */ |
de484a06 | 2596 | || (mips_cpu == 4900 |
42444087 GRK |
2597 | && (insn.insn_mo->membership & INSN_4900) != 0) |
2598 | /* end-sanitize-tx49 */ | |
a652f74c | 2599 | /* start-sanitize-r5900 */ |
de484a06 | 2600 | || (mips_cpu == 5900 |
a652f74c ILT |
2601 | && (insn.insn_mo->membership & INSN_5900) != 0) |
2602 | /* end-sanitize-r5900 */ | |
6b34ac5a | 2603 | /* start-sanitize-cygnus */ |
de484a06 | 2604 | || (mips_cpu == 5400 |
aa2e0460 | 2605 | && (insn.insn_mo->membership & INSN_5400) != 0) |
6b34ac5a | 2606 | /* end-sanitize-cygnus */ |
de484a06 | 2607 | || (mips_cpu == 3900 |
a652f74c ILT |
2608 | && (insn.insn_mo->membership & INSN_3900) != 0)) |
2609 | /* start-sanitize-r5900 */ | |
de484a06 | 2610 | && (mips_cpu != 5900 || (insn.insn_mo->pinfo & FP_D) == 0) |
a652f74c | 2611 | /* end-sanitize-r5900 */ |
de484a06 | 2612 | && (mips_cpu != 4650 || (insn.insn_mo->pinfo & FP_D) == 0)) |
a652f74c | 2613 | break; |
931a1858 | 2614 | |
a652f74c ILT |
2615 | ++insn.insn_mo; |
2616 | assert (insn.insn_mo->name); | |
2617 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 2618 | } |
931a1858 | 2619 | |
670a50eb ILT |
2620 | insn.insn_opcode = insn.insn_mo->match; |
2621 | for (;;) | |
2622 | { | |
2623 | switch (*fmt++) | |
2624 | { | |
3d3c5039 | 2625 | case '\0': |
670a50eb | 2626 | break; |
3d3c5039 ILT |
2627 | |
2628 | case ',': | |
2629 | case '(': | |
2630 | case ')': | |
670a50eb | 2631 | continue; |
3d3c5039 ILT |
2632 | |
2633 | case 't': | |
2634 | case 'w': | |
918692a5 | 2635 | case 'E': |
670a50eb ILT |
2636 | insn.insn_opcode |= va_arg (args, int) << 16; |
2637 | continue; | |
3d3c5039 ILT |
2638 | |
2639 | case 'c': | |
2640 | case 'T': | |
2641 | case 'W': | |
670a50eb ILT |
2642 | insn.insn_opcode |= va_arg (args, int) << 16; |
2643 | continue; | |
3d3c5039 ILT |
2644 | |
2645 | case 'd': | |
918692a5 | 2646 | case 'G': |
670a50eb ILT |
2647 | insn.insn_opcode |= va_arg (args, int) << 11; |
2648 | continue; | |
3d3c5039 ILT |
2649 | |
2650 | case 'V': | |
2651 | case 'S': | |
670a50eb ILT |
2652 | insn.insn_opcode |= va_arg (args, int) << 11; |
2653 | continue; | |
3d3c5039 | 2654 | |
ff3a5c18 ILT |
2655 | case 'z': |
2656 | continue; | |
2657 | ||
3d3c5039 | 2658 | case '<': |
670a50eb ILT |
2659 | insn.insn_opcode |= va_arg (args, int) << 6; |
2660 | continue; | |
3d3c5039 ILT |
2661 | |
2662 | case 'D': | |
670a50eb ILT |
2663 | insn.insn_opcode |= va_arg (args, int) << 6; |
2664 | continue; | |
3d3c5039 | 2665 | |
918692a5 ILT |
2666 | case 'B': |
2667 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2668 | continue; | |
2669 | ||
40f0c904 FCE |
2670 | case 'q': |
2671 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2672 | continue; | |
2673 | ||
3d3c5039 ILT |
2674 | case 'b': |
2675 | case 's': | |
2676 | case 'r': | |
2677 | case 'v': | |
670a50eb ILT |
2678 | insn.insn_opcode |= va_arg (args, int) << 21; |
2679 | continue; | |
3d3c5039 ILT |
2680 | |
2681 | case 'i': | |
2682 | case 'j': | |
2683 | case 'o': | |
9226253a | 2684 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2685 | assert (r == BFD_RELOC_MIPS_GPREL |
2686 | || r == BFD_RELOC_MIPS_LITERAL | |
2687 | || r == BFD_RELOC_LO16 | |
2688 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2689 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2690 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2691 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2692 | || (ep->X_op == O_subtract |
2693 | && now_seg == text_section | |
ecd4ca1c | 2694 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2695 | continue; |
3d3c5039 | 2696 | |
6e8dda9c | 2697 | case 'u': |
ecd4ca1c ILT |
2698 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2699 | assert (ep != NULL | |
2700 | && (ep->X_op == O_constant | |
2701 | || (ep->X_op == O_symbol | |
2702 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2703 | || r == BFD_RELOC_HI16 |
2704 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2705 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2706 | || (ep->X_op == O_subtract |
2707 | && now_seg == text_section | |
ecd4ca1c ILT |
2708 | && r == BFD_RELOC_PCREL_HI16_S))); |
2709 | if (ep->X_op == O_constant) | |
2710 | { | |
2711 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2712 | ep = NULL; | |
2713 | r = BFD_RELOC_UNUSED; | |
2714 | } | |
6e8dda9c ILT |
2715 | continue; |
2716 | ||
3d3c5039 | 2717 | case 'p': |
670a50eb ILT |
2718 | assert (ep != NULL); |
2719 | /* | |
2720 | * This allows macro() to pass an immediate expression for | |
2721 | * creating short branches without creating a symbol. | |
2722 | * Note that the expression still might come from the assembly | |
2723 | * input, in which case the value is not checked for range nor | |
2724 | * is a relocation entry generated (yuck). | |
2725 | */ | |
5ac34ac3 | 2726 | if (ep->X_op == O_constant) |
670a50eb ILT |
2727 | { |
2728 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2729 | ep = NULL; | |
2730 | } | |
2731 | else | |
2732 | r = BFD_RELOC_16_PCREL_S2; | |
2733 | continue; | |
3d3c5039 | 2734 | |
9226253a ILT |
2735 | case 'a': |
2736 | assert (ep != NULL); | |
2737 | r = BFD_RELOC_MIPS_JMP; | |
2738 | continue; | |
2739 | ||
65d2c7d3 JL |
2740 | case 'C': |
2741 | insn.insn_opcode |= va_arg (args, unsigned long); | |
2742 | continue; | |
2743 | ||
3d3c5039 | 2744 | default: |
670a50eb | 2745 | internalError (); |
3d3c5039 | 2746 | } |
670a50eb | 2747 | break; |
3d3c5039 | 2748 | } |
670a50eb ILT |
2749 | va_end (args); |
2750 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2751 | ||
867a58b3 | 2752 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2753 | } |
2754 | ||
cc5703cd ILT |
2755 | static void |
2756 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2757 | char *place; | |
2758 | int *counter; | |
2759 | expressionS *ep; | |
2760 | const char *name; | |
2761 | const char *fmt; | |
2762 | va_list args; | |
2763 | { | |
2764 | struct mips_cl_insn insn; | |
2765 | bfd_reloc_code_real_type r; | |
2766 | ||
2767 | r = BFD_RELOC_UNUSED; | |
2768 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2769 | assert (insn.insn_mo); | |
2770 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2771 | ||
2772 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2773 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2774 | { | |
2775 | ++insn.insn_mo; | |
2776 | assert (insn.insn_mo->name); | |
2777 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2778 | } | |
2779 | ||
2780 | insn.insn_opcode = insn.insn_mo->match; | |
2781 | insn.use_extend = false; | |
2782 | ||
2783 | for (;;) | |
2784 | { | |
2785 | int c; | |
2786 | ||
2787 | c = *fmt++; | |
2788 | switch (c) | |
2789 | { | |
2790 | case '\0': | |
2791 | break; | |
2792 | ||
2793 | case ',': | |
2794 | case '(': | |
2795 | case ')': | |
2796 | continue; | |
2797 | ||
2798 | case 'y': | |
2799 | case 'w': | |
2800 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2801 | continue; | |
2802 | ||
2803 | case 'x': | |
2804 | case 'v': | |
2805 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2806 | continue; | |
2807 | ||
2808 | case 'z': | |
2809 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2810 | continue; | |
2811 | ||
2812 | case 'Z': | |
2813 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2814 | continue; | |
2815 | ||
2816 | case '0': | |
2817 | case 'S': | |
2818 | case 'P': | |
2819 | case 'R': | |
2820 | continue; | |
2821 | ||
2822 | case 'X': | |
2823 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2824 | continue; | |
2825 | ||
2826 | case 'Y': | |
2827 | { | |
2828 | int regno; | |
2829 | ||
2830 | regno = va_arg (args, int); | |
2831 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2832 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2833 | } | |
2834 | continue; | |
2835 | ||
2836 | case '<': | |
2837 | case '>': | |
2838 | case '4': | |
2839 | case '5': | |
2840 | case 'H': | |
2841 | case 'W': | |
2842 | case 'D': | |
2843 | case 'j': | |
2844 | case '8': | |
2845 | case 'V': | |
2846 | case 'C': | |
2847 | case 'U': | |
2848 | case 'k': | |
2849 | case 'K': | |
2850 | case 'p': | |
2851 | case 'q': | |
2852 | { | |
2853 | assert (ep != NULL); | |
2854 | ||
2855 | if (ep->X_op != O_constant) | |
2856 | r = BFD_RELOC_UNUSED + c; | |
2857 | else | |
2858 | { | |
15e69f98 ILT |
2859 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
2860 | false, false, &insn.insn_opcode, | |
2861 | &insn.use_extend, &insn.extend); | |
cc5703cd ILT |
2862 | ep = NULL; |
2863 | r = BFD_RELOC_UNUSED; | |
2864 | } | |
2865 | } | |
2866 | continue; | |
2867 | ||
2868 | case '6': | |
2869 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2870 | continue; | |
2871 | } | |
2872 | ||
2873 | break; | |
2874 | } | |
2875 | ||
2876 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2877 | ||
2878 | append_insn (place, &insn, ep, r, false); | |
2879 | } | |
2880 | ||
3d3c5039 ILT |
2881 | /* |
2882 | * Generate a "lui" instruction. | |
2883 | */ | |
2884 | static void | |
0dd2d296 ILT |
2885 | macro_build_lui (place, counter, ep, regnum) |
2886 | char *place; | |
3d3c5039 ILT |
2887 | int *counter; |
2888 | expressionS *ep; | |
2889 | int regnum; | |
2890 | { | |
670a50eb ILT |
2891 | expressionS high_expr; |
2892 | struct mips_cl_insn insn; | |
2893 | bfd_reloc_code_real_type r; | |
2894 | CONST char *name = "lui"; | |
2895 | CONST char *fmt = "t,u"; | |
2896 | ||
3c83da8a | 2897 | assert (! mips_opts.mips16); |
cc5703cd | 2898 | |
0dd2d296 ILT |
2899 | if (place == NULL) |
2900 | high_expr = *ep; | |
2901 | else | |
2902 | { | |
2903 | high_expr.X_op = O_constant; | |
fb251650 | 2904 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2905 | } |
670a50eb | 2906 | |
5ac34ac3 | 2907 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2908 | { |
2909 | /* we can compute the instruction now without a relocation entry */ | |
2910 | if (high_expr.X_add_number & 0x8000) | |
2911 | high_expr.X_add_number += 0x10000; | |
2912 | high_expr.X_add_number = | |
2913 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2914 | r = BFD_RELOC_UNUSED; | |
2915 | } | |
2916 | else | |
0dd2d296 ILT |
2917 | { |
2918 | assert (ep->X_op == O_symbol); | |
2919 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2920 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2921 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2922 | r = BFD_RELOC_HI16_S; | |
2923 | } | |
670a50eb ILT |
2924 | |
2925 | /* | |
2926 | * If the macro is about to expand into a second instruction, | |
2927 | * print a warning if needed. We need to pass ip as a parameter | |
2928 | * to generate a better warning message here... | |
2929 | */ | |
3c83da8a | 2930 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
48401fcf | 2931 | as_warn (_("Macro instruction expanded into multiple instructions")); |
670a50eb | 2932 | |
0dd2d296 ILT |
2933 | if (place == NULL) |
2934 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2935 | |
2936 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2937 | assert (insn.insn_mo); | |
2938 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2939 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2940 | ||
0dd2d296 | 2941 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2942 | if (r == BFD_RELOC_UNUSED) |
2943 | { | |
2944 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2945 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2946 | } |
2947 | else | |
867a58b3 | 2948 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2949 | } |
2950 | ||
2951 | /* set_at() | |
2952 | * Generates code to set the $at register to true (one) | |
2953 | * if reg is less than the immediate expression. | |
2954 | */ | |
2955 | static void | |
6e8dda9c | 2956 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2957 | int *counter; |
2958 | int reg; | |
6e8dda9c | 2959 | int unsignedp; |
3d3c5039 | 2960 | { |
5c6f5923 GRK |
2961 | if (imm_expr.X_op == O_constant |
2962 | && imm_expr.X_add_number >= -0x8000 | |
2963 | && imm_expr.X_add_number < 0x8000) | |
0dd2d296 | 2964 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2965 | unsignedp ? "sltiu" : "slti", |
9226253a | 2966 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2967 | else |
670a50eb | 2968 | { |
d8a1c247 | 2969 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2970 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2971 | unsignedp ? "sltu" : "slt", |
2972 | "d,v,t", AT, reg, AT); | |
670a50eb | 2973 | } |
3d3c5039 ILT |
2974 | } |
2975 | ||
6e8dda9c | 2976 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2977 | |
2978 | static void | |
19ed8960 | 2979 | check_absolute_expr (ip, ex) |
3d3c5039 | 2980 | struct mips_cl_insn *ip; |
19ed8960 | 2981 | expressionS *ex; |
3d3c5039 | 2982 | { |
5c6f5923 | 2983 | if (ex->X_op == O_big) |
48401fcf | 2984 | as_bad (_("unsupported large constant")); |
5c6f5923 | 2985 | else if (ex->X_op != O_constant) |
48401fcf | 2986 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); |
3d3c5039 ILT |
2987 | } |
2988 | ||
ff8716f5 JSC |
2989 | /* Count the leading zeroes by performing a binary chop. This is a |
2990 | bulky bit of source, but performance is a LOT better for the | |
2991 | majority of values than a simple loop to count the bits: | |
2992 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2993 | if ((v) & (1 << (31 - lcnt))) | |
2994 | break; | |
2995 | However it is not code size friendly, and the gain will drop a bit | |
2996 | on certain cached systems. | |
2997 | */ | |
2998 | #define COUNT_TOP_ZEROES(v) \ | |
2999 | (((v) & ~0xffff) == 0 \ | |
3000 | ? ((v) & ~0xff) == 0 \ | |
3001 | ? ((v) & ~0xf) == 0 \ | |
3002 | ? ((v) & ~0x3) == 0 \ | |
3003 | ? ((v) & ~0x1) == 0 \ | |
3004 | ? !(v) \ | |
3005 | ? 32 \ | |
3006 | : 31 \ | |
3007 | : 30 \ | |
3008 | : ((v) & ~0x7) == 0 \ | |
3009 | ? 29 \ | |
3010 | : 28 \ | |
3011 | : ((v) & ~0x3f) == 0 \ | |
3012 | ? ((v) & ~0x1f) == 0 \ | |
3013 | ? 27 \ | |
3014 | : 26 \ | |
3015 | : ((v) & ~0x7f) == 0 \ | |
3016 | ? 25 \ | |
3017 | : 24 \ | |
3018 | : ((v) & ~0xfff) == 0 \ | |
3019 | ? ((v) & ~0x3ff) == 0 \ | |
3020 | ? ((v) & ~0x1ff) == 0 \ | |
3021 | ? 23 \ | |
3022 | : 22 \ | |
3023 | : ((v) & ~0x7ff) == 0 \ | |
3024 | ? 21 \ | |
3025 | : 20 \ | |
3026 | : ((v) & ~0x3fff) == 0 \ | |
3027 | ? ((v) & ~0x1fff) == 0 \ | |
3028 | ? 19 \ | |
3029 | : 18 \ | |
3030 | : ((v) & ~0x7fff) == 0 \ | |
3031 | ? 17 \ | |
3032 | : 16 \ | |
3033 | : ((v) & ~0xffffff) == 0 \ | |
3034 | ? ((v) & ~0xfffff) == 0 \ | |
3035 | ? ((v) & ~0x3ffff) == 0 \ | |
3036 | ? ((v) & ~0x1ffff) == 0 \ | |
3037 | ? 15 \ | |
3038 | : 14 \ | |
3039 | : ((v) & ~0x7ffff) == 0 \ | |
3040 | ? 13 \ | |
3041 | : 12 \ | |
3042 | : ((v) & ~0x3fffff) == 0 \ | |
3043 | ? ((v) & ~0x1fffff) == 0 \ | |
3044 | ? 11 \ | |
3045 | : 10 \ | |
3046 | : ((v) & ~0x7fffff) == 0 \ | |
3047 | ? 9 \ | |
3048 | : 8 \ | |
3049 | : ((v) & ~0xfffffff) == 0 \ | |
3050 | ? ((v) & ~0x3ffffff) == 0 \ | |
3051 | ? ((v) & ~0x1ffffff) == 0 \ | |
3052 | ? 7 \ | |
3053 | : 6 \ | |
3054 | : ((v) & ~0x7ffffff) == 0 \ | |
3055 | ? 5 \ | |
3056 | : 4 \ | |
3057 | : ((v) & ~0x3fffffff) == 0 \ | |
3058 | ? ((v) & ~0x1fffffff) == 0 \ | |
3059 | ? 3 \ | |
3060 | : 2 \ | |
3061 | : ((v) & ~0x7fffffff) == 0 \ | |
3062 | ? 1 \ | |
3063 | : 0) | |
3064 | ||
3d3c5039 ILT |
3065 | /* load_register() |
3066 | * This routine generates the least number of instructions neccessary to load | |
3067 | * an absolute expression value into a register. | |
3068 | */ | |
3069 | static void | |
d8a1c247 | 3070 | load_register (counter, reg, ep, dbl) |
670a50eb | 3071 | int *counter; |
670a50eb ILT |
3072 | int reg; |
3073 | expressionS *ep; | |
d8a1c247 | 3074 | int dbl; |
3d3c5039 | 3075 | { |
c36a90ef ILT |
3076 | int freg; |
3077 | expressionS hi32, lo32; | |
847a01cd ILT |
3078 | |
3079 | if (ep->X_op != O_big) | |
6e8dda9c | 3080 | { |
847a01cd | 3081 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
3082 | if (ep->X_add_number < 0x8000 |
3083 | && (ep->X_add_number >= 0 | |
3084 | || (ep->X_add_number >= -0x8000 | |
3085 | && (! dbl | |
3086 | || ! ep->X_unsigned | |
3087 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
3088 | { |
3089 | /* We can handle 16 bit signed values with an addiu to | |
3090 | $zero. No need to ever use daddiu here, since $zero and | |
3091 | the result are always correct in 32 bit mode. */ | |
3092 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3093 | (int) BFD_RELOC_LO16); | |
3094 | return; | |
3095 | } | |
3096 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3097 | { | |
3098 | /* We can handle 16 bit unsigned values with an ori to | |
3099 | $zero. */ | |
3100 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
3101 | (int) BFD_RELOC_LO16); | |
3102 | return; | |
3103 | } | |
98bfd087 ILT |
3104 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
3105 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
3106 | == ~ (offsetT) 0x7fffffff)) | |
3107 | && (! dbl | |
3108 | || ! ep->X_unsigned | |
3109 | || sizeof (ep->X_add_number) > 4 | |
3110 | || (ep->X_add_number & 0x80000000) == 0)) | |
3c83da8a | 3111 | || ((mips_opts.isa < 3 || ! dbl) |
f59fb6ca | 3112 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
3c83da8a | 3113 | || (mips_opts.isa < 3 |
f59fb6ca ILT |
3114 | && ! dbl |
3115 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3116 | == ~ (offsetT) 0xffffffff))) | |
847a01cd ILT |
3117 | { |
3118 | /* 32 bit values require an lui. */ | |
3119 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3120 | (int) BFD_RELOC_HI16); | |
3121 | if ((ep->X_add_number & 0xffff) != 0) | |
3122 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3123 | (int) BFD_RELOC_LO16); | |
3124 | return; | |
3125 | } | |
6e8dda9c | 3126 | } |
847a01cd ILT |
3127 | |
3128 | /* The value is larger than 32 bits. */ | |
3129 | ||
3c83da8a | 3130 | if (mips_opts.isa < 3) |
670a50eb | 3131 | { |
48401fcf | 3132 | as_bad (_("Number larger than 32 bits")); |
0dd2d296 | 3133 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 3134 | (int) BFD_RELOC_LO16); |
847a01cd | 3135 | return; |
6e8dda9c | 3136 | } |
6e8dda9c | 3137 | |
847a01cd ILT |
3138 | if (ep->X_op != O_big) |
3139 | { | |
6e8dda9c | 3140 | hi32 = *ep; |
c36a90ef ILT |
3141 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
3142 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6e8dda9c | 3143 | hi32.X_add_number &= 0xffffffff; |
6e8dda9c ILT |
3144 | lo32 = *ep; |
3145 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 3146 | } |
847a01cd ILT |
3147 | else |
3148 | { | |
3149 | assert (ep->X_add_number > 2); | |
3150 | if (ep->X_add_number == 3) | |
3151 | generic_bignum[3] = 0; | |
3152 | else if (ep->X_add_number > 4) | |
48401fcf | 3153 | as_bad (_("Number larger than 64 bits")); |
847a01cd ILT |
3154 | lo32.X_op = O_constant; |
3155 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3156 | hi32.X_op = O_constant; | |
3157 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3158 | } | |
3159 | ||
d8a1c247 KR |
3160 | if (hi32.X_add_number == 0) |
3161 | freg = 0; | |
3162 | else | |
3163 | { | |
c36a90ef ILT |
3164 | int shift, bit; |
3165 | unsigned long hi, lo; | |
3166 | ||
fb251650 ILT |
3167 | if (hi32.X_add_number == 0xffffffff) |
3168 | { | |
3169 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3170 | { | |
c36a90ef ILT |
3171 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
3172 | reg, 0, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
3173 | return; |
3174 | } | |
3175 | if (lo32.X_add_number & 0x80000000) | |
3176 | { | |
3177 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3178 | (int) BFD_RELOC_HI16); | |
c36a90ef ILT |
3179 | if (lo32.X_add_number & 0xffff) |
3180 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3181 | reg, reg, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
3182 | return; |
3183 | } | |
3184 | } | |
ff8716f5 | 3185 | |
c36a90ef ILT |
3186 | /* Check for 16bit shifted constant. We know that hi32 is |
3187 | non-zero, so start the mask on the first bit of the hi32 | |
3188 | value. */ | |
ff8716f5 JSC |
3189 | shift = 17; |
3190 | do | |
3191 | { | |
c36a90ef ILT |
3192 | unsigned long himask, lomask; |
3193 | ||
3194 | if (shift < 32) | |
3195 | { | |
3196 | himask = 0xffff >> (32 - shift); | |
3197 | lomask = (0xffff << shift) & 0xffffffff; | |
3198 | } | |
3199 | else | |
3200 | { | |
3201 | himask = 0xffff << (shift - 32); | |
3202 | lomask = 0; | |
3203 | } | |
3204 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
3205 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
3206 | { | |
3207 | expressionS tmp; | |
3208 | ||
3209 | tmp.X_op = O_constant; | |
3210 | if (shift < 32) | |
3211 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3212 | | (lo32.X_add_number >> shift)); | |
3213 | else | |
3214 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3215 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
3216 | (int) BFD_RELOC_LO16); | |
3217 | macro_build ((char *) NULL, counter, NULL, | |
3218 | (shift >= 32) ? "dsll32" : "dsll", | |
3219 | "d,w,<", reg, reg, | |
3220 | (shift >= 32) ? shift - 32 : shift); | |
3221 | return; | |
3222 | } | |
ff8716f5 JSC |
3223 | shift++; |
3224 | } while (shift <= (64 - 16)); | |
3225 | ||
c36a90ef ILT |
3226 | /* Find the bit number of the lowest one bit, and store the |
3227 | shifted value in hi/lo. */ | |
3228 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3229 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3230 | if (lo != 0) | |
3231 | { | |
3232 | bit = 0; | |
3233 | while ((lo & 1) == 0) | |
3234 | { | |
3235 | lo >>= 1; | |
3236 | ++bit; | |
3237 | } | |
3238 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3239 | hi >>= bit; | |
3240 | } | |
3241 | else | |
3242 | { | |
3243 | bit = 32; | |
3244 | while ((hi & 1) == 0) | |
3245 | { | |
3246 | hi >>= 1; | |
3247 | ++bit; | |
3248 | } | |
3249 | lo = hi; | |
3250 | hi = 0; | |
3251 | } | |
3252 | ||
3253 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3254 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3255 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
ff8716f5 | 3256 | { |
c36a90ef | 3257 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
ff8716f5 JSC |
3258 | if (shift != 0) |
3259 | { | |
c36a90ef ILT |
3260 | expressionS tmp; |
3261 | ||
3262 | /* This instruction will set the register to be all | |
3263 | ones. */ | |
ff8716f5 | 3264 | tmp.X_op = O_constant; |
c36a90ef ILT |
3265 | tmp.X_add_number = (offsetT) -1; |
3266 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
3267 | reg, 0, (int) BFD_RELOC_LO16); | |
3268 | if (bit != 0) | |
ff8716f5 | 3269 | { |
c36a90ef | 3270 | bit += shift; |
ff8716f5 | 3271 | macro_build ((char *) NULL, counter, NULL, |
c36a90ef | 3272 | (bit >= 32) ? "dsll32" : "dsll", |
ff8716f5 | 3273 | "d,w,<", reg, reg, |
c36a90ef | 3274 | (bit >= 32) ? bit - 32 : bit); |
ff8716f5 | 3275 | } |
c36a90ef ILT |
3276 | macro_build ((char *) NULL, counter, NULL, |
3277 | (shift >= 32) ? "dsrl32" : "dsrl", | |
3278 | "d,w,<", reg, reg, | |
3279 | (shift >= 32) ? shift - 32 : shift); | |
ff8716f5 JSC |
3280 | return; |
3281 | } | |
3282 | } | |
c36a90ef ILT |
3283 | |
3284 | /* Sign extend hi32 before calling load_register, because we can | |
3285 | generally get better code when we load a sign extended value. */ | |
3286 | if ((hi32.X_add_number & 0x80000000) != 0) | |
3287 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
d8a1c247 KR |
3288 | load_register (counter, reg, &hi32, 0); |
3289 | freg = reg; | |
3290 | } | |
847a01cd | 3291 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
3292 | { |
3293 | if (freg != 0) | |
3294 | { | |
3295 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
3296 | freg, 0); | |
3297 | freg = reg; | |
3298 | } | |
3299 | } | |
847a01cd ILT |
3300 | else |
3301 | { | |
3302 | expressionS mid16; | |
3303 | ||
fb251650 ILT |
3304 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
3305 | { | |
3306 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3307 | (int) BFD_RELOC_HI16); | |
3308 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 3309 | reg, 0); |
fb251650 ILT |
3310 | return; |
3311 | } | |
3312 | ||
d8a1c247 KR |
3313 | if (freg != 0) |
3314 | { | |
3315 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3316 | freg, 16); | |
3317 | freg = reg; | |
3318 | } | |
847a01cd ILT |
3319 | mid16 = lo32; |
3320 | mid16.X_add_number >>= 16; | |
3321 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 3322 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
3323 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
3324 | reg, 16); | |
d8a1c247 | 3325 | freg = reg; |
847a01cd ILT |
3326 | } |
3327 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 3328 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 3329 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
3330 | } |
3331 | ||
0dd2d296 ILT |
3332 | /* Load an address into a register. */ |
3333 | ||
3334 | static void | |
3335 | load_address (counter, reg, ep) | |
3336 | int *counter; | |
3337 | int reg; | |
3338 | expressionS *ep; | |
3339 | { | |
3340 | char *p; | |
3341 | ||
3342 | if (ep->X_op != O_constant | |
3343 | && ep->X_op != O_symbol) | |
3344 | { | |
48401fcf | 3345 | as_bad (_("expression too complex")); |
0dd2d296 ILT |
3346 | ep->X_op = O_constant; |
3347 | } | |
3348 | ||
3349 | if (ep->X_op == O_constant) | |
d9aba805 | 3350 | { |
d8a1c247 | 3351 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
3352 | return; |
3353 | } | |
3354 | ||
3355 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
3356 | { |
3357 | /* If this is a reference to a GP relative symbol, we want | |
3358 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3359 | Otherwise we want | |
04cb3372 | 3360 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
3361 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
3362 | If we have an addend, we always use the latter form. */ | |
7a15a226 | 3363 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 3364 | || nopic_need_relax (ep->X_add_symbol, 1)) |
0dd2d296 ILT |
3365 | p = NULL; |
3366 | else | |
3367 | { | |
8ea7f4e8 | 3368 | frag_grow (20); |
0dd2d296 | 3369 | macro_build ((char *) NULL, counter, ep, |
9a1f3160 JL |
3370 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3371 | || mips_opts.isa < 3) | |
3372 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3373 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3374 | p = frag_var (rs_machine_dependent, 8, 0, | |
3c83da8a JW |
3375 | RELAX_ENCODE (4, 8, 0, 4, 0, |
3376 | mips_opts.warn_about_macros), | |
f59fb6ca | 3377 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 ILT |
3378 | } |
3379 | macro_build_lui (p, counter, ep, reg); | |
3380 | if (p != NULL) | |
3381 | p += 4; | |
3382 | macro_build (p, counter, ep, | |
9a1f3160 JL |
3383 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3384 | || mips_opts.isa < 3) | |
3385 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3386 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3387 | } | |
fb251650 | 3388 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3389 | { |
3390 | expressionS ex; | |
3391 | ||
3392 | /* If this is a reference to an external symbol, we want | |
3393 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3394 | Otherwise we want | |
3395 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3396 | nop | |
3397 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 3398 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
3399 | ex.X_add_number = ep->X_add_number; |
3400 | ep->X_add_number = 0; | |
8ea7f4e8 | 3401 | frag_grow (20); |
0dd2d296 | 3402 | macro_build ((char *) NULL, counter, ep, |
9a1f3160 JL |
3403 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3404 | || mips_opts.isa < 3) | |
3405 | ? "lw" : "ld"), | |
0dd2d296 ILT |
3406 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3407 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3408 | p = frag_var (rs_machine_dependent, 4, 0, | |
3c83da8a | 3409 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), |
f59fb6ca | 3410 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 | 3411 | macro_build (p, counter, ep, |
9a1f3160 JL |
3412 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3413 | || mips_opts.isa < 3) | |
3414 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3415 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3416 | if (ex.X_add_number != 0) | |
3417 | { | |
3418 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
48401fcf | 3419 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
0dd2d296 | 3420 | ex.X_op = O_constant; |
fb251650 | 3421 | macro_build ((char *) NULL, counter, &ex, |
9a1f3160 JL |
3422 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3423 | || mips_opts.isa < 3) | |
3424 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
3425 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3426 | } | |
3427 | } | |
3428 | else if (mips_pic == SVR4_PIC) | |
3429 | { | |
3430 | expressionS ex; | |
3431 | int off; | |
3432 | ||
3433 | /* This is the large GOT case. If this is a reference to an | |
3434 | external symbol, we want | |
3435 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3436 | addu $reg,$reg,$gp | |
3437 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3438 | Otherwise, for a reference to a local symbol, we want | |
3439 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3440 | nop | |
3441 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3442 | If there is a constant, it must be added in after. */ | |
3443 | ex.X_add_number = ep->X_add_number; | |
3444 | ep->X_add_number = 0; | |
3445 | if (reg_needs_delay (GP)) | |
3446 | off = 4; | |
3447 | else | |
3448 | off = 0; | |
3449 | frag_grow (32); | |
3450 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3451 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3452 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
9a1f3160 JL |
3453 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3454 | || mips_opts.isa < 3) | |
3455 | ? "addu" : "daddu"), | |
fb251650 ILT |
3456 | "d,v,t", reg, reg, GP); |
3457 | macro_build ((char *) NULL, counter, ep, | |
9a1f3160 JL |
3458 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3459 | || mips_opts.isa < 3) | |
3460 | ? "lw" : "ld"), | |
fb251650 ILT |
3461 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
3462 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3463 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3c83da8a | 3464 | mips_opts.warn_about_macros), |
f59fb6ca | 3465 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
3466 | if (off > 0) |
3467 | { | |
3468 | /* We need a nop before loading from $gp. This special | |
3469 | check is required because the lui which starts the main | |
3470 | instruction stream does not refer to $gp, and so will not | |
3471 | insert the nop which may be required. */ | |
3472 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3473 | p += 4; | |
3474 | } | |
3475 | macro_build (p, counter, ep, | |
9a1f3160 JL |
3476 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3477 | || mips_opts.isa < 3) | |
3478 | ? "lw" : "ld"), | |
fb251650 ILT |
3479 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3480 | p += 4; | |
3481 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3482 | p += 4; | |
3483 | macro_build (p, counter, ep, | |
9a1f3160 JL |
3484 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3485 | || mips_opts.isa < 3) | |
3486 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
3487 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3488 | if (ex.X_add_number != 0) | |
3489 | { | |
3490 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
48401fcf | 3491 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
fb251650 ILT |
3492 | ex.X_op = O_constant; |
3493 | macro_build ((char *) NULL, counter, &ex, | |
9a1f3160 JL |
3494 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3495 | || mips_opts.isa < 3) | |
3496 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3497 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3498 | } | |
d9aba805 ILT |
3499 | } |
3500 | else if (mips_pic == EMBEDDED_PIC) | |
3501 | { | |
3502 | /* We always do | |
3503 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3504 | */ | |
3505 | macro_build ((char *) NULL, counter, ep, | |
9a1f3160 JL |
3506 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3507 | || mips_opts.isa < 3) | |
3508 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
3509 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3510 | } | |
3511 | else | |
3512 | abort (); | |
0dd2d296 ILT |
3513 | } |
3514 | ||
3d3c5039 ILT |
3515 | /* |
3516 | * Build macros | |
3517 | * This routine implements the seemingly endless macro or synthesized | |
3518 | * instructions and addressing modes in the mips assembly language. Many | |
3519 | * of these macros are simple and are similar to each other. These could | |
3520 | * probably be handled by some kind of table or grammer aproach instead of | |
3521 | * this verbose method. Others are not simple macros but are more like | |
3522 | * optimizing code generation. | |
3523 | * One interesting optimization is when several store macros appear | |
3524 | * consecutivly that would load AT with the upper half of the same address. | |
3525 | * The ensuing load upper instructions are ommited. This implies some kind | |
3526 | * of global optimization. We currently only optimize within a single macro. | |
3527 | * For many of the load and store macros if the address is specified as a | |
3528 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3529 | * first load register 'at' with zero and use it as the base register. The | |
3530 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3531 | * we're missing. | |
3532 | */ | |
3533 | static void | |
3534 | macro (ip) | |
3535 | struct mips_cl_insn *ip; | |
3536 | { | |
670a50eb ILT |
3537 | register int treg, sreg, dreg, breg; |
3538 | int tempreg; | |
3539 | int mask; | |
3540 | int icnt = 0; | |
3541 | int used_at; | |
670a50eb ILT |
3542 | expressionS expr1; |
3543 | const char *s; | |
8358c818 | 3544 | const char *s2; |
670a50eb | 3545 | const char *fmt; |
8358c818 ILT |
3546 | int likely = 0; |
3547 | int dbl = 0; | |
3548 | int coproc = 0; | |
b2b8c24e | 3549 | int lr = 0; |
40f0c904 | 3550 | int imm = 0; |
6e8dda9c | 3551 | offsetT maxnum; |
adcf2b9d | 3552 | int off; |
9226253a | 3553 | bfd_reloc_code_real_type r; |
0dd2d296 | 3554 | char *p; |
55933a58 | 3555 | int hold_mips_optimize; |
670a50eb | 3556 | |
3c83da8a | 3557 | assert (! mips_opts.mips16); |
cc5703cd | 3558 | |
670a50eb ILT |
3559 | treg = (ip->insn_opcode >> 16) & 0x1f; |
3560 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3561 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3562 | mask = ip->insn_mo->mask; | |
3563 | ||
5ac34ac3 ILT |
3564 | expr1.X_op = O_constant; |
3565 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
3566 | expr1.X_add_symbol = NULL; |
3567 | expr1.X_add_number = 1; | |
3568 | ||
3569 | switch (mask) | |
3570 | { | |
6e8dda9c ILT |
3571 | case M_DABS: |
3572 | dbl = 1; | |
3d3c5039 | 3573 | case M_ABS: |
6e8dda9c ILT |
3574 | /* bgez $a0,.+12 |
3575 | move v0,$a0 | |
3576 | sub v0,$zero,$a0 | |
3577 | */ | |
3d3c5039 | 3578 | |
fbcfacb7 | 3579 | mips_emit_delays (true); |
3c83da8a | 3580 | ++mips_opts.noreorder; |
0dd2d296 | 3581 | mips_any_noreorder = 1; |
3d3c5039 | 3582 | |
670a50eb | 3583 | expr1.X_add_number = 8; |
0dd2d296 | 3584 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 3585 | if (dreg == sreg) |
0dd2d296 | 3586 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 3587 | else |
0dd2d296 ILT |
3588 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
3589 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
3590 | dbl ? "dsub" : "sub", |
3591 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 3592 | |
3c83da8a | 3593 | --mips_opts.noreorder; |
670a50eb | 3594 | return; |
3d3c5039 ILT |
3595 | |
3596 | case M_ADD_I: | |
8358c818 ILT |
3597 | s = "addi"; |
3598 | s2 = "add"; | |
3599 | goto do_addi; | |
3d3c5039 | 3600 | case M_ADDU_I: |
8358c818 ILT |
3601 | s = "addiu"; |
3602 | s2 = "addu"; | |
3603 | goto do_addi; | |
3604 | case M_DADD_I: | |
6e8dda9c | 3605 | dbl = 1; |
8358c818 ILT |
3606 | s = "daddi"; |
3607 | s2 = "dadd"; | |
3608 | goto do_addi; | |
3609 | case M_DADDU_I: | |
6e8dda9c | 3610 | dbl = 1; |
8358c818 ILT |
3611 | s = "daddiu"; |
3612 | s2 = "daddu"; | |
3613 | do_addi: | |
5c6f5923 GRK |
3614 | if (imm_expr.X_op == O_constant |
3615 | && imm_expr.X_add_number >= -0x8000 | |
3616 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 3617 | { |
0dd2d296 | 3618 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 3619 | (int) BFD_RELOC_LO16); |
670a50eb | 3620 | return; |
3d3c5039 | 3621 | } |
d8a1c247 | 3622 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 3623 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3624 | break; |
3d3c5039 ILT |
3625 | |
3626 | case M_AND_I: | |
6e8dda9c ILT |
3627 | s = "andi"; |
3628 | s2 = "and"; | |
3629 | goto do_bit; | |
3d3c5039 | 3630 | case M_OR_I: |
6e8dda9c ILT |
3631 | s = "ori"; |
3632 | s2 = "or"; | |
3633 | goto do_bit; | |
3d3c5039 | 3634 | case M_NOR_I: |
6e8dda9c ILT |
3635 | s = ""; |
3636 | s2 = "nor"; | |
3637 | goto do_bit; | |
3d3c5039 | 3638 | case M_XOR_I: |
6e8dda9c ILT |
3639 | s = "xori"; |
3640 | s2 = "xor"; | |
3641 | do_bit: | |
5c6f5923 GRK |
3642 | if (imm_expr.X_op == O_constant |
3643 | && imm_expr.X_add_number >= 0 | |
3644 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 3645 | { |
6e8dda9c | 3646 | if (mask != M_NOR_I) |
0dd2d296 ILT |
3647 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
3648 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 3649 | else |
670a50eb | 3650 | { |
0dd2d296 ILT |
3651 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
3652 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 3653 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 3654 | treg, treg, 0); |
3d3c5039 | 3655 | } |
6e8dda9c | 3656 | return; |
3d3c5039 | 3657 | } |
6e8dda9c | 3658 | |
d8a1c247 | 3659 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3660 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3661 | break; |
3d3c5039 ILT |
3662 | |
3663 | case M_BEQ_I: | |
8358c818 ILT |
3664 | s = "beq"; |
3665 | goto beq_i; | |
3666 | case M_BEQL_I: | |
3667 | s = "beql"; | |
3668 | likely = 1; | |
3669 | goto beq_i; | |
3d3c5039 | 3670 | case M_BNE_I: |
8358c818 ILT |
3671 | s = "bne"; |
3672 | goto beq_i; | |
3673 | case M_BNEL_I: | |
3674 | s = "bnel"; | |
3675 | likely = 1; | |
3676 | beq_i: | |
5c6f5923 | 3677 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3678 | { |
0dd2d296 ILT |
3679 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
3680 | 0); | |
670a50eb ILT |
3681 | return; |
3682 | } | |
d8a1c247 | 3683 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3684 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 3685 | break; |
3d3c5039 | 3686 | |
8358c818 ILT |
3687 | case M_BGEL: |
3688 | likely = 1; | |
3d3c5039 | 3689 | case M_BGE: |
670a50eb ILT |
3690 | if (treg == 0) |
3691 | { | |
0dd2d296 | 3692 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3693 | likely ? "bgezl" : "bgez", |
3694 | "s,p", sreg); | |
670a50eb | 3695 | return; |
3d3c5039 | 3696 | } |
9a7d824a ILT |
3697 | if (sreg == 0) |
3698 | { | |
0dd2d296 | 3699 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3700 | likely ? "blezl" : "blez", |
3701 | "s,p", treg); | |
9a7d824a ILT |
3702 | return; |
3703 | } | |
0dd2d296 ILT |
3704 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3705 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3706 | likely ? "beql" : "beq", |
3707 | "s,t,p", AT, 0); | |
670a50eb | 3708 | break; |
3d3c5039 | 3709 | |
8358c818 ILT |
3710 | case M_BGTL_I: |
3711 | likely = 1; | |
3d3c5039 | 3712 | case M_BGT_I: |
9a7d824a | 3713 | /* check for > max integer */ |
6e8dda9c | 3714 | maxnum = 0x7fffffff; |
5c6f5923 | 3715 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3716 | { |
3717 | maxnum <<= 16; | |
3718 | maxnum |= 0xffff; | |
3719 | maxnum <<= 16; | |
3720 | maxnum |= 0xffff; | |
3721 | } | |
5c6f5923 GRK |
3722 | if (imm_expr.X_op == O_constant |
3723 | && imm_expr.X_add_number >= maxnum | |
3c83da8a | 3724 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a ILT |
3725 | { |
3726 | do_false: | |
3727 | /* result is always false */ | |
8358c818 ILT |
3728 | if (! likely) |
3729 | { | |
48401fcf | 3730 | as_warn (_("Branch %s is always false (nop)"), ip->insn_mo->name); |
0dd2d296 | 3731 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3732 | } |
3733 | else | |
3734 | { | |
48401fcf | 3735 | as_warn (_("Branch likely %s is always false"), ip->insn_mo->name); |
0dd2d296 ILT |
3736 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3737 | "s,t,p", 0, 0); | |
8358c818 | 3738 | } |
9a7d824a ILT |
3739 | return; |
3740 | } | |
5c6f5923 | 3741 | if (imm_expr.X_op != O_constant) |
48401fcf | 3742 | as_bad (_("Unsupported large constant")); |
670a50eb ILT |
3743 | imm_expr.X_add_number++; |
3744 | /* FALLTHROUGH */ | |
3d3c5039 | 3745 | case M_BGE_I: |
8358c818 ILT |
3746 | case M_BGEL_I: |
3747 | if (mask == M_BGEL_I) | |
3748 | likely = 1; | |
5c6f5923 | 3749 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3750 | { |
0dd2d296 | 3751 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3752 | likely ? "bgezl" : "bgez", |
3753 | "s,p", sreg); | |
670a50eb | 3754 | return; |
3d3c5039 | 3755 | } |
5c6f5923 | 3756 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3757 | { |
0dd2d296 | 3758 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3759 | likely ? "bgtzl" : "bgtz", |
3760 | "s,p", sreg); | |
670a50eb | 3761 | return; |
3d3c5039 | 3762 | } |
6e8dda9c | 3763 | maxnum = 0x7fffffff; |
5c6f5923 | 3764 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3765 | { |
3766 | maxnum <<= 16; | |
3767 | maxnum |= 0xffff; | |
3768 | maxnum <<= 16; | |
3769 | maxnum |= 0xffff; | |
3770 | } | |
3771 | maxnum = - maxnum - 1; | |
5c6f5923 GRK |
3772 | if (imm_expr.X_op == O_constant |
3773 | && imm_expr.X_add_number <= maxnum | |
3c83da8a | 3774 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a ILT |
3775 | { |
3776 | do_true: | |
3777 | /* result is always true */ | |
48401fcf | 3778 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); |
0dd2d296 | 3779 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3780 | return; |
3781 | } | |
6e8dda9c | 3782 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3783 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3784 | likely ? "beql" : "beq", |
3785 | "s,t,p", AT, 0); | |
670a50eb | 3786 | break; |
3d3c5039 | 3787 | |
8358c818 ILT |
3788 | case M_BGEUL: |
3789 | likely = 1; | |
3d3c5039 | 3790 | case M_BGEU: |
670a50eb | 3791 | if (treg == 0) |
9a7d824a ILT |
3792 | goto do_true; |
3793 | if (sreg == 0) | |
670a50eb | 3794 | { |
0dd2d296 | 3795 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3796 | likely ? "beql" : "beq", |
3797 | "s,t,p", 0, treg); | |
670a50eb | 3798 | return; |
3d3c5039 | 3799 | } |
0dd2d296 ILT |
3800 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3801 | treg); | |
3802 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3803 | likely ? "beql" : "beq", |
3804 | "s,t,p", AT, 0); | |
670a50eb | 3805 | break; |
3d3c5039 | 3806 | |
8358c818 ILT |
3807 | case M_BGTUL_I: |
3808 | likely = 1; | |
9a7d824a | 3809 | case M_BGTU_I: |
5c6f5923 GRK |
3810 | if (sreg == 0 |
3811 | || (mips_opts.isa < 3 | |
3812 | && imm_expr.X_op == O_constant | |
3813 | && imm_expr.X_add_number == 0xffffffff)) | |
9a7d824a | 3814 | goto do_false; |
5c6f5923 | 3815 | if (imm_expr.X_op != O_constant) |
48401fcf | 3816 | as_bad (_("Unsupported large constant")); |
9a7d824a ILT |
3817 | imm_expr.X_add_number++; |
3818 | /* FALLTHROUGH */ | |
3d3c5039 | 3819 | case M_BGEU_I: |
8358c818 ILT |
3820 | case M_BGEUL_I: |
3821 | if (mask == M_BGEUL_I) | |
3822 | likely = 1; | |
5c6f5923 | 3823 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
9a7d824a | 3824 | goto do_true; |
5c6f5923 | 3825 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3826 | { |
0dd2d296 | 3827 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3828 | likely ? "bnel" : "bne", |
3829 | "s,t,p", sreg, 0); | |
670a50eb | 3830 | return; |
3d3c5039 | 3831 | } |
6e8dda9c | 3832 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3833 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3834 | likely ? "beql" : "beq", |
3835 | "s,t,p", AT, 0); | |
670a50eb | 3836 | break; |
3d3c5039 | 3837 | |
8358c818 ILT |
3838 | case M_BGTL: |
3839 | likely = 1; | |
3d3c5039 | 3840 | case M_BGT: |
670a50eb ILT |
3841 | if (treg == 0) |
3842 | { | |
0dd2d296 | 3843 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3844 | likely ? "bgtzl" : "bgtz", |
3845 | "s,p", sreg); | |
670a50eb | 3846 | return; |
3d3c5039 | 3847 | } |
9a7d824a ILT |
3848 | if (sreg == 0) |
3849 | { | |
0dd2d296 | 3850 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3851 | likely ? "bltzl" : "bltz", |
3852 | "s,p", treg); | |
9a7d824a ILT |
3853 | return; |
3854 | } | |
0dd2d296 ILT |
3855 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3856 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3857 | likely ? "bnel" : "bne", |
3858 | "s,t,p", AT, 0); | |
670a50eb | 3859 | break; |
3d3c5039 | 3860 | |
8358c818 ILT |
3861 | case M_BGTUL: |
3862 | likely = 1; | |
3d3c5039 | 3863 | case M_BGTU: |
670a50eb ILT |
3864 | if (treg == 0) |
3865 | { | |
0dd2d296 | 3866 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3867 | likely ? "bnel" : "bne", |
3868 | "s,t,p", sreg, 0); | |
670a50eb | 3869 | return; |
3d3c5039 | 3870 | } |
9a7d824a ILT |
3871 | if (sreg == 0) |
3872 | goto do_false; | |
0dd2d296 ILT |
3873 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3874 | sreg); | |
3875 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3876 | likely ? "bnel" : "bne", |
3877 | "s,t,p", AT, 0); | |
670a50eb | 3878 | break; |
3d3c5039 | 3879 | |
8358c818 ILT |
3880 | case M_BLEL: |
3881 | likely = 1; | |
3d3c5039 | 3882 | case M_BLE: |
670a50eb ILT |
3883 | if (treg == 0) |
3884 | { | |
0dd2d296 | 3885 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3886 | likely ? "blezl" : "blez", |
3887 | "s,p", sreg); | |
670a50eb ILT |
3888 | return; |
3889 | } | |
9a7d824a ILT |
3890 | if (sreg == 0) |
3891 | { | |
0dd2d296 | 3892 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3893 | likely ? "bgezl" : "bgez", |
3894 | "s,p", treg); | |
9a7d824a ILT |
3895 | return; |
3896 | } | |
0dd2d296 ILT |
3897 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3898 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3899 | likely ? "beql" : "beq", |
3900 | "s,t,p", AT, 0); | |
670a50eb | 3901 | break; |
3d3c5039 | 3902 | |
8358c818 ILT |
3903 | case M_BLEL_I: |
3904 | likely = 1; | |
3d3c5039 | 3905 | case M_BLE_I: |
6e8dda9c | 3906 | maxnum = 0x7fffffff; |
5c6f5923 | 3907 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3908 | { |
3909 | maxnum <<= 16; | |
3910 | maxnum |= 0xffff; | |
3911 | maxnum <<= 16; | |
3912 | maxnum |= 0xffff; | |
3913 | } | |
5c6f5923 GRK |
3914 | if (imm_expr.X_op == O_constant |
3915 | && imm_expr.X_add_number >= maxnum | |
3c83da8a | 3916 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a | 3917 | goto do_true; |
5c6f5923 | 3918 | if (imm_expr.X_op != O_constant) |
48401fcf | 3919 | as_bad (_("Unsupported large constant")); |
9a7d824a ILT |
3920 | imm_expr.X_add_number++; |
3921 | /* FALLTHROUGH */ | |
9a7d824a | 3922 | case M_BLT_I: |
8358c818 ILT |
3923 | case M_BLTL_I: |
3924 | if (mask == M_BLTL_I) | |
3925 | likely = 1; | |
5c6f5923 | 3926 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3927 | { |
0dd2d296 | 3928 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3929 | likely ? "bltzl" : "bltz", |
3930 | "s,p", sreg); | |
670a50eb ILT |
3931 | return; |
3932 | } | |
5c6f5923 | 3933 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3934 | { |
0dd2d296 | 3935 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3936 | likely ? "blezl" : "blez", |
3937 | "s,p", sreg); | |
670a50eb ILT |
3938 | return; |
3939 | } | |
6e8dda9c | 3940 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3941 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3942 | likely ? "bnel" : "bne", |
3943 | "s,t,p", AT, 0); | |
670a50eb | 3944 | break; |
3d3c5039 | 3945 | |
8358c818 ILT |
3946 | case M_BLEUL: |
3947 | likely = 1; | |
3d3c5039 | 3948 | case M_BLEU: |
670a50eb ILT |
3949 | if (treg == 0) |
3950 | { | |
0dd2d296 | 3951 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3952 | likely ? "beql" : "beq", |
3953 | "s,t,p", sreg, 0); | |
670a50eb | 3954 | return; |
3d3c5039 | 3955 | } |
9a7d824a ILT |
3956 | if (sreg == 0) |
3957 | goto do_true; | |
0dd2d296 ILT |
3958 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3959 | sreg); | |
3960 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3961 | likely ? "beql" : "beq", |
3962 | "s,t,p", AT, 0); | |
670a50eb | 3963 | break; |
3d3c5039 | 3964 | |
8358c818 ILT |
3965 | case M_BLEUL_I: |
3966 | likely = 1; | |
3d3c5039 | 3967 | case M_BLEU_I: |
5c6f5923 GRK |
3968 | if (sreg == 0 |
3969 | || (mips_opts.isa < 3 | |
3970 | && imm_expr.X_op == O_constant | |
3971 | && imm_expr.X_add_number == 0xffffffff)) | |
9a7d824a | 3972 | goto do_true; |
5c6f5923 | 3973 | if (imm_expr.X_op != O_constant) |
48401fcf | 3974 | as_bad (_("Unsupported large constant")); |
9a7d824a ILT |
3975 | imm_expr.X_add_number++; |
3976 | /* FALLTHROUGH */ | |
9a7d824a | 3977 | case M_BLTU_I: |
8358c818 ILT |
3978 | case M_BLTUL_I: |
3979 | if (mask == M_BLTUL_I) | |
3980 | likely = 1; | |
5c6f5923 | 3981 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
9a7d824a | 3982 | goto do_false; |
5c6f5923 | 3983 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3984 | { |
0dd2d296 | 3985 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3986 | likely ? "beql" : "beq", |
3987 | "s,t,p", sreg, 0); | |
670a50eb | 3988 | return; |
3d3c5039 | 3989 | } |
6e8dda9c | 3990 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3991 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3992 | likely ? "bnel" : "bne", |
3993 | "s,t,p", AT, 0); | |
670a50eb | 3994 | break; |
3d3c5039 | 3995 | |
8358c818 ILT |
3996 | case M_BLTL: |
3997 | likely = 1; | |
3d3c5039 | 3998 | case M_BLT: |
670a50eb ILT |
3999 | if (treg == 0) |
4000 | { | |
0dd2d296 | 4001 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
4002 | likely ? "bltzl" : "bltz", |
4003 | "s,p", sreg); | |
670a50eb | 4004 | return; |
3d3c5039 | 4005 | } |
9a7d824a | 4006 | if (sreg == 0) |
670a50eb | 4007 | { |
0dd2d296 | 4008 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
4009 | likely ? "bgtzl" : "bgtz", |
4010 | "s,p", treg); | |
670a50eb | 4011 | return; |
3d3c5039 | 4012 | } |
0dd2d296 ILT |
4013 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
4014 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
4015 | likely ? "bnel" : "bne", |
4016 | "s,t,p", AT, 0); | |
670a50eb | 4017 | break; |
3d3c5039 | 4018 | |
8358c818 ILT |
4019 | case M_BLTUL: |
4020 | likely = 1; | |
3d3c5039 | 4021 | case M_BLTU: |
670a50eb | 4022 | if (treg == 0) |
9a7d824a ILT |
4023 | goto do_false; |
4024 | if (sreg == 0) | |
670a50eb | 4025 | { |
0dd2d296 | 4026 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
4027 | likely ? "bnel" : "bne", |
4028 | "s,t,p", 0, treg); | |
670a50eb ILT |
4029 | return; |
4030 | } | |
0dd2d296 ILT |
4031 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
4032 | treg); | |
4033 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
4034 | likely ? "bnel" : "bne", |
4035 | "s,t,p", AT, 0); | |
670a50eb | 4036 | break; |
3d3c5039 | 4037 | |
8358c818 ILT |
4038 | case M_DDIV_3: |
4039 | dbl = 1; | |
3d3c5039 | 4040 | case M_DIV_3: |
8358c818 ILT |
4041 | s = "mflo"; |
4042 | goto do_div3; | |
4043 | case M_DREM_3: | |
4044 | dbl = 1; | |
3d3c5039 | 4045 | case M_REM_3: |
8358c818 ILT |
4046 | s = "mfhi"; |
4047 | do_div3: | |
670a50eb ILT |
4048 | if (treg == 0) |
4049 | { | |
48401fcf | 4050 | as_warn (_("Divide by zero.")); |
8ea7f4e8 ILT |
4051 | if (mips_trap) |
4052 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
4053 | else | |
d9c2c0c5 | 4054 | /* start-sanitize-r5900 */ |
de484a06 | 4055 | if (mips_cpu == 5900) |
d9c2c0c5 FCE |
4056 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); |
4057 | else | |
4058 | /* end-sanitize-r5900 */ | |
4059 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
4060 | return; |
4061 | } | |
4062 | ||
fbcfacb7 | 4063 | mips_emit_delays (true); |
3c83da8a | 4064 | ++mips_opts.noreorder; |
0dd2d296 | 4065 | mips_any_noreorder = 1; |
8ea7f4e8 | 4066 | if (mips_trap) |
6c4b811d JL |
4067 | { |
4068 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
4069 | macro_build ((char *) NULL, &icnt, NULL, | |
4070 | dbl ? "ddiv" : "div", | |
4071 | "z,s,t", sreg, treg); | |
4072 | } | |
8ea7f4e8 ILT |
4073 | else |
4074 | { | |
4075 | expr1.X_add_number = 8; | |
4076 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
6c4b811d JL |
4077 | macro_build ((char *) NULL, &icnt, NULL, |
4078 | dbl ? "ddiv" : "div", | |
4079 | "z,s,t", sreg, treg); | |
d9c2c0c5 | 4080 | /* start-sanitize-r5900 */ |
de484a06 | 4081 | if (mips_cpu == 5900) |
d9c2c0c5 FCE |
4082 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); |
4083 | else | |
4084 | /* end-sanitize-r5900 */ | |
4085 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
8ea7f4e8 | 4086 | } |
670a50eb | 4087 | expr1.X_add_number = -1; |
0dd2d296 | 4088 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 4089 | dbl ? "daddiu" : "addiu", |
9226253a | 4090 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 4091 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 4092 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
4093 | if (dbl) |
4094 | { | |
4095 | expr1.X_add_number = 1; | |
0dd2d296 | 4096 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 4097 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
4098 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
4099 | 31); | |
8358c818 ILT |
4100 | } |
4101 | else | |
4102 | { | |
4103 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
4104 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
4105 | (int) BFD_RELOC_HI16); | |
8358c818 | 4106 | } |
8ea7f4e8 | 4107 | if (mips_trap) |
edc8f76e JL |
4108 | { |
4109 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
4110 | /* We want to close the noreorder block as soon as possible, so | |
4111 | that later insns are available for delay slot filling. */ | |
4112 | --mips_opts.noreorder; | |
4113 | } | |
8ea7f4e8 ILT |
4114 | else |
4115 | { | |
4116 | expr1.X_add_number = 8; | |
4117 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
4118 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
d9c2c0c5 | 4119 | |
edc8f76e JL |
4120 | /* We want to close the noreorder block as soon as possible, so |
4121 | that later insns are available for delay slot filling. */ | |
4122 | --mips_opts.noreorder; | |
4123 | ||
d9c2c0c5 | 4124 | /* start-sanitize-r5900 */ |
de484a06 | 4125 | if (mips_cpu == 5900) |
d9c2c0c5 FCE |
4126 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 6); |
4127 | else | |
4128 | /* end-sanitize-r5900 */ | |
4129 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
8ea7f4e8 | 4130 | } |
0dd2d296 | 4131 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 4132 | break; |
3d3c5039 ILT |
4133 | |
4134 | case M_DIV_3I: | |
8358c818 ILT |
4135 | s = "div"; |
4136 | s2 = "mflo"; | |
4137 | goto do_divi; | |
3d3c5039 | 4138 | case M_DIVU_3I: |
8358c818 ILT |
4139 | s = "divu"; |
4140 | s2 = "mflo"; | |
4141 | goto do_divi; | |
3d3c5039 | 4142 | case M_REM_3I: |
8358c818 ILT |
4143 | s = "div"; |
4144 | s2 = "mfhi"; | |
4145 | goto do_divi; | |
3d3c5039 | 4146 | case M_REMU_3I: |
8358c818 ILT |
4147 | s = "divu"; |
4148 | s2 = "mfhi"; | |
4149 | goto do_divi; | |
4150 | case M_DDIV_3I: | |
4151 | dbl = 1; | |
4152 | s = "ddiv"; | |
4153 | s2 = "mflo"; | |
4154 | goto do_divi; | |
4155 | case M_DDIVU_3I: | |
4156 | dbl = 1; | |
4157 | s = "ddivu"; | |
4158 | s2 = "mflo"; | |
4159 | goto do_divi; | |
4160 | case M_DREM_3I: | |
4161 | dbl = 1; | |
4162 | s = "ddiv"; | |
4163 | s2 = "mfhi"; | |
4164 | goto do_divi; | |
4165 | case M_DREMU_3I: | |
4166 | dbl = 1; | |
4167 | s = "ddivu"; | |
4168 | s2 = "mfhi"; | |
4169 | do_divi: | |
5c6f5923 | 4170 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 4171 | { |
48401fcf | 4172 | as_warn (_("Divide by zero.")); |
8ea7f4e8 ILT |
4173 | if (mips_trap) |
4174 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
4175 | else | |
d9c2c0c5 | 4176 | /* start-sanitize-r5900 */ |
de484a06 | 4177 | if (mips_cpu == 5900) |
d9c2c0c5 FCE |
4178 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); |
4179 | else | |
4180 | /* end-sanitize-r5900 */ | |
4181 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
4182 | return; |
4183 | } | |
5c6f5923 | 4184 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 4185 | { |
8358c818 | 4186 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
4187 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
4188 | sreg); | |
3d3c5039 | 4189 | else |
0dd2d296 | 4190 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
4191 | return; |
4192 | } | |
5c6f5923 GRK |
4193 | if (imm_expr.X_op == O_constant |
4194 | && imm_expr.X_add_number == -1 | |
8358c818 ILT |
4195 | && s[strlen (s) - 1] != 'u') |
4196 | { | |
4197 | if (strcmp (s2, "mflo") == 0) | |
4198 | { | |
4199 | if (dbl) | |
0dd2d296 ILT |
4200 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
4201 | sreg); | |
8358c818 | 4202 | else |
0dd2d296 ILT |
4203 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
4204 | sreg); | |
8358c818 ILT |
4205 | } |
4206 | else | |
0dd2d296 | 4207 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
4208 | return; |
4209 | } | |
3d3c5039 | 4210 | |
d8a1c247 | 4211 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
4212 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
4213 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
4214 | break; |
4215 | ||
4216 | case M_DIVU_3: | |
8358c818 ILT |
4217 | s = "divu"; |
4218 | s2 = "mflo"; | |
4219 | goto do_divu3; | |
670a50eb | 4220 | case M_REMU_3: |
8358c818 ILT |
4221 | s = "divu"; |
4222 | s2 = "mfhi"; | |
4223 | goto do_divu3; | |
4224 | case M_DDIVU_3: | |
4225 | s = "ddivu"; | |
4226 | s2 = "mflo"; | |
4227 | goto do_divu3; | |
4228 | case M_DREMU_3: | |
4229 | s = "ddivu"; | |
4230 | s2 = "mfhi"; | |
4231 | do_divu3: | |
fbcfacb7 | 4232 | mips_emit_delays (true); |
3c83da8a | 4233 | ++mips_opts.noreorder; |
0dd2d296 | 4234 | mips_any_noreorder = 1; |
8ea7f4e8 | 4235 | if (mips_trap) |
6c4b811d JL |
4236 | { |
4237 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
4238 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
edc8f76e JL |
4239 | /* We want to close the noreorder block as soon as possible, so |
4240 | that later insns are available for delay slot filling. */ | |
4241 | --mips_opts.noreorder; | |
6c4b811d | 4242 | } |
8ea7f4e8 ILT |
4243 | else |
4244 | { | |
4245 | expr1.X_add_number = 8; | |
4246 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
6c4b811d | 4247 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); |
edc8f76e JL |
4248 | |
4249 | /* We want to close the noreorder block as soon as possible, so | |
4250 | that later insns are available for delay slot filling. */ | |
4251 | --mips_opts.noreorder; | |
d9c2c0c5 | 4252 | /* start-sanitize-r5900 */ |
de484a06 | 4253 | if (mips_cpu == 5900) |
d9c2c0c5 FCE |
4254 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); |
4255 | else | |
4256 | /* end-sanitize-r5900 */ | |
4257 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
8ea7f4e8 | 4258 | } |
0dd2d296 | 4259 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 4260 | return; |
3d3c5039 | 4261 | |
d8a1c247 KR |
4262 | case M_DLA_AB: |
4263 | dbl = 1; | |
0dd2d296 | 4264 | case M_LA_AB: |
d9aba805 ILT |
4265 | /* Load the address of a symbol into a register. If breg is not |
4266 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
4267 | |
4268 | /* When generating embedded PIC code, we permit expressions of | |
4269 | the form | |
4270 | la $4,foo-bar | |
4271 | where bar is an address in the .text section. These are used | |
4272 | when getting the addresses of functions. We don't permit | |
4273 | X_add_number to be non-zero, because if the symbol is | |
4274 | external the relaxing code needs to know that any addend is | |
4275 | purely the offset to X_op_symbol. */ | |
4276 | if (mips_pic == EMBEDDED_PIC | |
4277 | && offset_expr.X_op == O_subtract | |
4278 | && now_seg == text_section | |
847a01cd ILT |
4279 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
4280 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
4281 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
4282 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
4283 | ->sy_value.X_add_symbol) | |
4284 | == text_section))) | |
ecd4ca1c ILT |
4285 | && breg == 0 |
4286 | && offset_expr.X_add_number == 0) | |
4287 | { | |
4288 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4289 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
4290 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4291 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4292 | || mips_opts.isa < 3) | |
4293 | ? "addiu" : "daddiu"), | |
ecd4ca1c ILT |
4294 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); |
4295 | return; | |
4296 | } | |
4297 | ||
0dd2d296 ILT |
4298 | if (offset_expr.X_op != O_symbol |
4299 | && offset_expr.X_op != O_constant) | |
670a50eb | 4300 | { |
48401fcf | 4301 | as_bad (_("expression too complex")); |
0dd2d296 ILT |
4302 | offset_expr.X_op = O_constant; |
4303 | } | |
4304 | ||
4305 | if (treg == breg) | |
4306 | { | |
4307 | tempreg = AT; | |
4308 | used_at = 1; | |
3d3c5039 | 4309 | } |
670a50eb ILT |
4310 | else |
4311 | { | |
0dd2d296 ILT |
4312 | tempreg = treg; |
4313 | used_at = 0; | |
670a50eb | 4314 | } |
3d3c5039 | 4315 | |
5ac34ac3 | 4316 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 4317 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 4318 | else if (mips_pic == NO_PIC) |
670a50eb | 4319 | { |
0dd2d296 ILT |
4320 | /* If this is a reference to an GP relative symbol, we want |
4321 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4322 | Otherwise we want | |
4323 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4324 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4325 | If we have a constant, we need two instructions anyhow, | |
4326 | so we may as well always use the latter form. */ | |
7a15a226 | 4327 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4328 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4329 | p = NULL; |
4330 | else | |
4331 | { | |
8ea7f4e8 | 4332 | frag_grow (20); |
0dd2d296 | 4333 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a1f3160 JL |
4334 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4335 | || mips_opts.isa < 3) | |
4336 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4337 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4338 | p = frag_var (rs_machine_dependent, 8, 0, | |
4339 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3c83da8a | 4340 | mips_opts.warn_about_macros), |
f59fb6ca | 4341 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4342 | (char *) NULL); |
4343 | } | |
4344 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4345 | if (p != NULL) | |
4346 | p += 4; | |
4347 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
4348 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4349 | || mips_opts.isa < 3) | |
4350 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4351 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4352 | } | |
fb251650 | 4353 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
4354 | { |
4355 | /* If this is a reference to an external symbol, and there | |
4356 | is no constant, we want | |
4357 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4358 | For a local symbol, we want | |
4359 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4360 | nop | |
4361 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4362 | ||
4363 | If we have a small constant, and this is a reference to | |
4364 | an external symbol, we want | |
4365 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4366 | nop | |
4367 | addiu $tempreg,$tempreg,<constant> | |
4368 | For a local symbol, we want the same instruction | |
4369 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4370 | addiu instruction. | |
4371 | ||
4372 | If we have a large constant, and this is a reference to | |
4373 | an external symbol, we want | |
4374 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4375 | lui $at,<hiconstant> | |
4376 | addiu $at,$at,<loconstant> | |
4377 | addu $tempreg,$tempreg,$at | |
4378 | For a local symbol, we want the same instruction | |
4379 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4380 | addiu instruction. */ | |
4381 | expr1.X_add_number = offset_expr.X_add_number; | |
4382 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 4383 | frag_grow (32); |
0dd2d296 | 4384 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 4385 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
4386 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
4387 | if (expr1.X_add_number == 0) | |
4388 | { | |
4389 | int off; | |
4390 | ||
4391 | if (breg == 0) | |
4392 | off = 0; | |
4393 | else | |
4394 | { | |
4395 | /* We're going to put in an addu instruction using | |
4396 | tempreg, so we may as well insert the nop right | |
4397 | now. */ | |
4398 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4399 | "nop", ""); | |
4400 | off = 4; | |
4401 | } | |
4402 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4403 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4404 | (breg == 0 | |
3c83da8a | 4405 | ? mips_opts.warn_about_macros |
0dd2d296 | 4406 | : 0)), |
f59fb6ca | 4407 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4408 | (char *) NULL); |
4409 | if (breg == 0) | |
4410 | { | |
4411 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4412 | p += 4; | |
4413 | } | |
4414 | macro_build (p, &icnt, &expr1, | |
9a1f3160 JL |
4415 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4416 | || mips_opts.isa < 3) | |
4417 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4418 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4419 | /* FIXME: If breg == 0, and the next instruction uses | |
4420 | $tempreg, then if this variant case is used an extra | |
4421 | nop will be generated. */ | |
4422 | } | |
4423 | else if (expr1.X_add_number >= -0x8000 | |
4424 | && expr1.X_add_number < 0x8000) | |
4425 | { | |
4426 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4427 | "nop", ""); | |
4428 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4429 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4430 | || mips_opts.isa < 3) | |
4431 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4432 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4433 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4434 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
f59fb6ca | 4435 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4436 | (char *) NULL); |
4437 | } | |
4438 | else | |
4439 | { | |
4440 | int off1; | |
4441 | ||
4442 | /* If we are going to add in a base register, and the | |
4443 | target register and the base register are the same, | |
4444 | then we are using AT as a temporary register. Since | |
4445 | we want to load the constant into AT, we add our | |
4446 | current AT (from the global offset table) and the | |
4447 | register into the register now, and pretend we were | |
4448 | not using a base register. */ | |
4449 | if (breg != treg) | |
4450 | off1 = 0; | |
4451 | else | |
4452 | { | |
4453 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4454 | "nop", ""); | |
4455 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4456 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4457 | || mips_opts.isa < 3) | |
4458 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4459 | "d,v,t", treg, AT, breg); |
4460 | breg = 0; | |
4461 | tempreg = treg; | |
4462 | off1 = -8; | |
4463 | } | |
4464 | ||
55933a58 ILT |
4465 | /* Set mips_optimize around the lui instruction to avoid |
4466 | inserting an unnecessary nop after the lw. */ | |
4467 | hold_mips_optimize = mips_optimize; | |
4468 | mips_optimize = 2; | |
0dd2d296 | 4469 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
4470 | mips_optimize = hold_mips_optimize; |
4471 | ||
0dd2d296 | 4472 | macro_build ((char *) NULL, &icnt, &expr1, |
9a1f3160 JL |
4473 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4474 | || mips_opts.isa < 3) | |
4475 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4476 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4477 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4478 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4479 | || mips_opts.isa < 3) | |
4480 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4481 | "d,v,t", tempreg, tempreg, AT); |
4482 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4483 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
f59fb6ca | 4484 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4485 | (char *) NULL); |
4486 | used_at = 1; | |
4487 | } | |
670a50eb | 4488 | } |
fb251650 ILT |
4489 | else if (mips_pic == SVR4_PIC) |
4490 | { | |
4491 | int gpdel; | |
4492 | ||
4493 | /* This is the large GOT case. If this is a reference to an | |
4494 | external symbol, and there is no constant, we want | |
4495 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4496 | addu $tempreg,$tempreg,$gp | |
4497 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4498 | For a local symbol, we want | |
4499 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4500 | nop | |
4501 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4502 | ||
4503 | If we have a small constant, and this is a reference to | |
4504 | an external symbol, we want | |
4505 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4506 | addu $tempreg,$tempreg,$gp | |
4507 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4508 | nop | |
4509 | addiu $tempreg,$tempreg,<constant> | |
4510 | For a local symbol, we want | |
4511 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4512 | nop | |
4513 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4514 | ||
4515 | If we have a large constant, and this is a reference to | |
4516 | an external symbol, we want | |
4517 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4518 | addu $tempreg,$tempreg,$gp | |
4519 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4520 | lui $at,<hiconstant> | |
4521 | addiu $at,$at,<loconstant> | |
4522 | addu $tempreg,$tempreg,$at | |
4523 | For a local symbol, we want | |
4524 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4525 | lui $at,<hiconstant> | |
4526 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4527 | addu $tempreg,$tempreg,$at | |
4528 | */ | |
4529 | expr1.X_add_number = offset_expr.X_add_number; | |
4530 | offset_expr.X_add_number = 0; | |
4531 | frag_grow (52); | |
4532 | if (reg_needs_delay (GP)) | |
4533 | gpdel = 4; | |
4534 | else | |
4535 | gpdel = 0; | |
4536 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4537 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4538 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4539 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4540 | || mips_opts.isa < 3) | |
4541 | ? "addu" : "daddu"), | |
fb251650 ILT |
4542 | "d,v,t", tempreg, tempreg, GP); |
4543 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4544 | dbl ? "ld" : "lw", | |
4545 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
4546 | tempreg); | |
4547 | if (expr1.X_add_number == 0) | |
4548 | { | |
4549 | int off; | |
4550 | ||
4551 | if (breg == 0) | |
4552 | off = 0; | |
4553 | else | |
4554 | { | |
4555 | /* We're going to put in an addu instruction using | |
4556 | tempreg, so we may as well insert the nop right | |
4557 | now. */ | |
4558 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4559 | "nop", ""); | |
4560 | off = 4; | |
4561 | } | |
4562 | ||
4563 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4564 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4565 | 8 + gpdel, 0, | |
4566 | (breg == 0 | |
3c83da8a | 4567 | ? mips_opts.warn_about_macros |
fb251650 | 4568 | : 0)), |
f59fb6ca | 4569 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4570 | (char *) NULL); |
4571 | } | |
4572 | else if (expr1.X_add_number >= -0x8000 | |
4573 | && expr1.X_add_number < 0x8000) | |
4574 | { | |
4575 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4576 | "nop", ""); | |
4577 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4578 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4579 | || mips_opts.isa < 3) | |
4580 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4581 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4582 | ||
4583 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4584 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4585 | (breg == 0 | |
3c83da8a | 4586 | ? mips_opts.warn_about_macros |
fb251650 | 4587 | : 0)), |
f59fb6ca | 4588 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4589 | (char *) NULL); |
4590 | } | |
4591 | else | |
4592 | { | |
4593 | int adj, dreg; | |
4594 | ||
4595 | /* If we are going to add in a base register, and the | |
4596 | target register and the base register are the same, | |
4597 | then we are using AT as a temporary register. Since | |
4598 | we want to load the constant into AT, we add our | |
4599 | current AT (from the global offset table) and the | |
4600 | register into the register now, and pretend we were | |
4601 | not using a base register. */ | |
4602 | if (breg != treg) | |
4603 | { | |
4604 | adj = 0; | |
4605 | dreg = tempreg; | |
4606 | } | |
4607 | else | |
4608 | { | |
4609 | assert (tempreg == AT); | |
4610 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4611 | "nop", ""); | |
4612 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4613 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4614 | || mips_opts.isa < 3) | |
4615 | ? "addu" : "daddu"), | |
fb251650 ILT |
4616 | "d,v,t", treg, AT, breg); |
4617 | dreg = treg; | |
4618 | adj = 8; | |
4619 | } | |
4620 | ||
4621 | /* Set mips_optimize around the lui instruction to avoid | |
4622 | inserting an unnecessary nop after the lw. */ | |
4623 | hold_mips_optimize = mips_optimize; | |
4624 | mips_optimize = 2; | |
4625 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4626 | mips_optimize = hold_mips_optimize; | |
4627 | ||
4628 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4629 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4630 | || mips_opts.isa < 3) | |
4631 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4632 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4633 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4634 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4635 | || mips_opts.isa < 3) | |
4636 | ? "addu" : "daddu"), | |
fb251650 ILT |
4637 | "d,v,t", dreg, dreg, AT); |
4638 | ||
4639 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4640 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4641 | 8 + gpdel, 0, | |
4642 | (breg == 0 | |
3c83da8a | 4643 | ? mips_opts.warn_about_macros |
fb251650 | 4644 | : 0)), |
f59fb6ca | 4645 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4646 | (char *) NULL); |
4647 | ||
4648 | used_at = 1; | |
4649 | } | |
4650 | ||
4651 | if (gpdel > 0) | |
4652 | { | |
4653 | /* This is needed because this instruction uses $gp, but | |
4654 | the first instruction on the main stream does not. */ | |
4655 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4656 | p += 4; | |
4657 | } | |
4658 | macro_build (p, &icnt, &offset_expr, | |
4659 | dbl ? "ld" : "lw", | |
4660 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4661 | p += 4; | |
4662 | if (expr1.X_add_number >= -0x8000 | |
4663 | && expr1.X_add_number < 0x8000) | |
4664 | { | |
4665 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4666 | p += 4; | |
4667 | macro_build (p, &icnt, &expr1, | |
9a1f3160 JL |
4668 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4669 | || mips_opts.isa < 3) | |
4670 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4671 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4672 | /* FIXME: If add_number is 0, and there was no base | |
4673 | register, the external symbol case ended with a load, | |
4674 | so if the symbol turns out to not be external, and | |
4675 | the next instruction uses tempreg, an unnecessary nop | |
4676 | will be inserted. */ | |
4677 | } | |
4678 | else | |
4679 | { | |
4680 | if (breg == treg) | |
4681 | { | |
4682 | /* We must add in the base register now, as in the | |
4683 | external symbol case. */ | |
4684 | assert (tempreg == AT); | |
4685 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4686 | p += 4; | |
4687 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4688 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4689 | || mips_opts.isa < 3) | |
4690 | ? "addu" : "daddu"), | |
fb251650 ILT |
4691 | "d,v,t", treg, AT, breg); |
4692 | p += 4; | |
4693 | tempreg = treg; | |
4694 | /* We set breg to 0 because we have arranged to add | |
4695 | it in in both cases. */ | |
4696 | breg = 0; | |
4697 | } | |
4698 | ||
4699 | macro_build_lui (p, &icnt, &expr1, AT); | |
4700 | p += 4; | |
4701 | macro_build (p, &icnt, &expr1, | |
9a1f3160 JL |
4702 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4703 | || mips_opts.isa < 3) | |
4704 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4705 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4706 | p += 4; | |
4707 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4708 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4709 | || mips_opts.isa < 3) | |
4710 | ? "addu" : "daddu"), | |
fb251650 ILT |
4711 | "d,v,t", tempreg, tempreg, AT); |
4712 | p += 4; | |
4713 | } | |
4714 | } | |
d9aba805 ILT |
4715 | else if (mips_pic == EMBEDDED_PIC) |
4716 | { | |
4717 | /* We use | |
4718 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4719 | */ | |
4720 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4721 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4722 | || mips_opts.isa < 3) | |
4723 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
4724 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4725 | } | |
4726 | else | |
4727 | abort (); | |
0dd2d296 | 4728 | |
670a50eb | 4729 | if (breg != 0) |
0dd2d296 | 4730 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
4731 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4732 | || mips_opts.isa < 3) | |
4733 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4734 | "d,v,t", treg, tempreg, breg); |
4735 | ||
4736 | if (! used_at) | |
4737 | return; | |
4738 | ||
4739 | break; | |
4740 | ||
4741 | case M_J_A: | |
4742 | /* The j instruction may not be used in PIC code, since it | |
4743 | requires an absolute address. We convert it to a b | |
4744 | instruction. */ | |
d9aba805 | 4745 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
4746 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
4747 | else | |
4748 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 4749 | return; |
3d3c5039 | 4750 | |
9226253a ILT |
4751 | /* The jal instructions must be handled as macros because when |
4752 | generating PIC code they expand to multi-instruction | |
4753 | sequences. Normally they are simple instructions. */ | |
4754 | case M_JAL_1: | |
4755 | dreg = RA; | |
4756 | /* Fall through. */ | |
4757 | case M_JAL_2: | |
d9aba805 ILT |
4758 | if (mips_pic == NO_PIC |
4759 | || mips_pic == EMBEDDED_PIC) | |
4760 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4761 | "d,s", dreg, sreg); | |
4762 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4763 | { |
d9aba805 | 4764 | if (sreg != PIC_CALL_REG) |
48401fcf | 4765 | as_warn (_("MIPS PIC call to register other than $25")); |
d9aba805 | 4766 | |
0dd2d296 ILT |
4767 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4768 | "d,s", dreg, sreg); | |
d9aba805 | 4769 | if (mips_cprestore_offset < 0) |
48401fcf | 4770 | as_warn (_("No .cprestore pseudo-op used in PIC code")); |
d9aba805 ILT |
4771 | else |
4772 | { | |
4773 | expr1.X_add_number = mips_cprestore_offset; | |
4774 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4775 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4776 | || mips_opts.isa < 3) | |
4777 | ? "lw" : "ld"), | |
d9aba805 ILT |
4778 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); |
4779 | } | |
9226253a | 4780 | } |
0dd2d296 | 4781 | else |
d9aba805 ILT |
4782 | abort (); |
4783 | ||
9226253a ILT |
4784 | return; |
4785 | ||
4786 | case M_JAL_A: | |
d9aba805 ILT |
4787 | if (mips_pic == NO_PIC) |
4788 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4789 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4790 | { |
fb251650 ILT |
4791 | /* If this is a reference to an external symbol, and we are |
4792 | using a small GOT, we want | |
d9aba805 ILT |
4793 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4794 | nop | |
4795 | jalr $25 | |
4796 | nop | |
4797 | lw $gp,cprestore($sp) | |
4798 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
4799 | pseudo-op. If we are using a big GOT, we want |
4800 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4801 | addu $25,$25,$gp | |
4802 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4803 | nop | |
4804 | jalr $25 | |
4805 | nop | |
4806 | lw $gp,cprestore($sp) | |
4807 | If the symbol is not external, we want | |
d9aba805 ILT |
4808 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4809 | nop | |
4810 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4811 | jalr $25 | |
4812 | nop | |
fb251650 ILT |
4813 | lw $gp,cprestore($sp) */ |
4814 | frag_grow (40); | |
4815 | if (! mips_big_got) | |
4816 | { | |
4817 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4818 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4819 | || mips_opts.isa < 3) | |
4820 | ? "lw" : "ld"), | |
fb251650 ILT |
4821 | "t,o(b)", PIC_CALL_REG, |
4822 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4823 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4824 | "nop", ""); | |
4825 | p = frag_var (rs_machine_dependent, 4, 0, | |
4826 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca ILT |
4827 | offset_expr.X_add_symbol, (offsetT) 0, |
4828 | (char *) NULL); | |
fb251650 ILT |
4829 | } |
4830 | else | |
4831 | { | |
4832 | int gpdel; | |
4833 | ||
4834 | if (reg_needs_delay (GP)) | |
4835 | gpdel = 4; | |
4836 | else | |
4837 | gpdel = 0; | |
4838 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4839 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4840 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4841 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4842 | || mips_opts.isa < 3) | |
4843 | ? "addu" : "daddu"), | |
fb251650 ILT |
4844 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); |
4845 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4846 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4847 | || mips_opts.isa < 3) | |
4848 | ? "lw" : "ld"), | |
fb251650 ILT |
4849 | "t,o(b)", PIC_CALL_REG, |
4850 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4851 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4852 | "nop", ""); | |
4853 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4854 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4855 | 0, 0), | |
f59fb6ca ILT |
4856 | offset_expr.X_add_symbol, (offsetT) 0, |
4857 | (char *) NULL); | |
fb251650 ILT |
4858 | if (gpdel > 0) |
4859 | { | |
4860 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4861 | p += 4; | |
4862 | } | |
4863 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
4864 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4865 | || mips_opts.isa < 3) | |
4866 | ? "lw" : "ld"), | |
fb251650 ILT |
4867 | "t,o(b)", PIC_CALL_REG, |
4868 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4869 | p += 4; | |
4870 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4871 | p += 4; | |
4872 | } | |
d9aba805 | 4873 | macro_build (p, &icnt, &offset_expr, |
9a1f3160 JL |
4874 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4875 | || mips_opts.isa < 3) | |
4876 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
4877 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
4878 | (int) BFD_RELOC_LO16); | |
4879 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4880 | "jalr", "s", PIC_CALL_REG); | |
4881 | if (mips_cprestore_offset < 0) | |
48401fcf | 4882 | as_warn (_("No .cprestore pseudo-op used in PIC code")); |
d9aba805 ILT |
4883 | else |
4884 | { | |
3c83da8a | 4885 | if (mips_opts.noreorder) |
d9aba805 ILT |
4886 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4887 | "nop", ""); | |
4888 | expr1.X_add_number = mips_cprestore_offset; | |
4889 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4890 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4891 | || mips_opts.isa < 3) | |
4892 | ? "lw" : "ld"), | |
d9aba805 ILT |
4893 | "t,o(b)", GP, (int) BFD_RELOC_LO16, |
4894 | mips_frame_reg); | |
4895 | } | |
0dd2d296 | 4896 | } |
d9aba805 | 4897 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4898 | { |
4899 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4900 | /* The linker may expand the call to a longer sequence which | |
4901 | uses $at, so we must break rather than return. */ | |
4902 | break; | |
4903 | } | |
d9aba805 ILT |
4904 | else |
4905 | abort (); | |
4906 | ||
9226253a ILT |
4907 | return; |
4908 | ||
3d3c5039 | 4909 | case M_LB_AB: |
670a50eb ILT |
4910 | s = "lb"; |
4911 | goto ld; | |
3d3c5039 | 4912 | case M_LBU_AB: |
670a50eb ILT |
4913 | s = "lbu"; |
4914 | goto ld; | |
3d3c5039 | 4915 | case M_LH_AB: |
670a50eb ILT |
4916 | s = "lh"; |
4917 | goto ld; | |
3d3c5039 | 4918 | case M_LHU_AB: |
670a50eb ILT |
4919 | s = "lhu"; |
4920 | goto ld; | |
3d3c5039 | 4921 | case M_LW_AB: |
670a50eb ILT |
4922 | s = "lw"; |
4923 | goto ld; | |
3d3c5039 | 4924 | case M_LWC0_AB: |
670a50eb | 4925 | s = "lwc0"; |
efec4a28 | 4926 | /* Itbl support may require additional care here. */ |
8358c818 | 4927 | coproc = 1; |
670a50eb | 4928 | goto ld; |
3d3c5039 | 4929 | case M_LWC1_AB: |
670a50eb | 4930 | s = "lwc1"; |
efec4a28 | 4931 | /* Itbl support may require additional care here. */ |
8358c818 | 4932 | coproc = 1; |
670a50eb | 4933 | goto ld; |
3d3c5039 | 4934 | case M_LWC2_AB: |
670a50eb | 4935 | s = "lwc2"; |
efec4a28 | 4936 | /* Itbl support may require additional care here. */ |
8358c818 | 4937 | coproc = 1; |
670a50eb | 4938 | goto ld; |
3d3c5039 | 4939 | case M_LWC3_AB: |
670a50eb | 4940 | s = "lwc3"; |
efec4a28 | 4941 | /* Itbl support may require additional care here. */ |
8358c818 | 4942 | coproc = 1; |
670a50eb | 4943 | goto ld; |
3d3c5039 | 4944 | case M_LWL_AB: |
670a50eb | 4945 | s = "lwl"; |
b2b8c24e | 4946 | lr = 1; |
670a50eb | 4947 | goto ld; |
3d3c5039 | 4948 | case M_LWR_AB: |
670a50eb | 4949 | s = "lwr"; |
b2b8c24e | 4950 | lr = 1; |
8358c818 ILT |
4951 | goto ld; |
4952 | case M_LDC1_AB: | |
de484a06 | 4953 | if (mips_cpu == 4650) |
1c6f3441 | 4954 | { |
48401fcf | 4955 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
4956 | return; |
4957 | } | |
8358c818 | 4958 | s = "ldc1"; |
efec4a28 | 4959 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4960 | coproc = 1; |
4961 | goto ld; | |
4962 | case M_LDC2_AB: | |
4963 | s = "ldc2"; | |
efec4a28 | 4964 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4965 | coproc = 1; |
4966 | goto ld; | |
4967 | case M_LDC3_AB: | |
4968 | s = "ldc3"; | |
efec4a28 | 4969 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4970 | coproc = 1; |
4971 | goto ld; | |
4972 | case M_LDL_AB: | |
4973 | s = "ldl"; | |
b2b8c24e | 4974 | lr = 1; |
8358c818 ILT |
4975 | goto ld; |
4976 | case M_LDR_AB: | |
4977 | s = "ldr"; | |
b2b8c24e | 4978 | lr = 1; |
8358c818 ILT |
4979 | goto ld; |
4980 | case M_LL_AB: | |
4981 | s = "ll"; | |
4982 | goto ld; | |
4983 | case M_LLD_AB: | |
4984 | s = "lld"; | |
4985 | goto ld; | |
4986 | case M_LWU_AB: | |
4987 | s = "lwu"; | |
3d3c5039 | 4988 | ld: |
b2b8c24e | 4989 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4990 | { |
4991 | tempreg = AT; | |
4992 | used_at = 1; | |
4993 | } | |
4994 | else | |
4995 | { | |
4996 | tempreg = treg; | |
4997 | used_at = 0; | |
4998 | } | |
4999 | goto ld_st; | |
3d3c5039 | 5000 | case M_SB_AB: |
670a50eb ILT |
5001 | s = "sb"; |
5002 | goto st; | |
3d3c5039 | 5003 | case M_SH_AB: |
670a50eb ILT |
5004 | s = "sh"; |
5005 | goto st; | |
3d3c5039 | 5006 | case M_SW_AB: |
670a50eb ILT |
5007 | s = "sw"; |
5008 | goto st; | |
3d3c5039 | 5009 | case M_SWC0_AB: |
670a50eb | 5010 | s = "swc0"; |
efec4a28 | 5011 | /* Itbl support may require additional care here. */ |
8358c818 | 5012 | coproc = 1; |
670a50eb | 5013 | goto st; |
3d3c5039 | 5014 | case M_SWC1_AB: |
670a50eb | 5015 | s = "swc1"; |
efec4a28 | 5016 | /* Itbl support may require additional care here. */ |
8358c818 | 5017 | coproc = 1; |
670a50eb | 5018 | goto st; |
3d3c5039 | 5019 | case M_SWC2_AB: |
670a50eb | 5020 | s = "swc2"; |
efec4a28 | 5021 | /* Itbl support may require additional care here. */ |
8358c818 | 5022 | coproc = 1; |
670a50eb | 5023 | goto st; |
3d3c5039 | 5024 | case M_SWC3_AB: |
670a50eb | 5025 | s = "swc3"; |
efec4a28 | 5026 | /* Itbl support may require additional care here. */ |
8358c818 | 5027 | coproc = 1; |
670a50eb | 5028 | goto st; |
3d3c5039 | 5029 | case M_SWL_AB: |
670a50eb ILT |
5030 | s = "swl"; |
5031 | goto st; | |
3d3c5039 | 5032 | case M_SWR_AB: |
670a50eb | 5033 | s = "swr"; |
8358c818 ILT |
5034 | goto st; |
5035 | case M_SC_AB: | |
5036 | s = "sc"; | |
5037 | goto st; | |
5038 | case M_SCD_AB: | |
5039 | s = "scd"; | |
5040 | goto st; | |
5041 | case M_SDC1_AB: | |
de484a06 | 5042 | if (mips_cpu == 4650) |
1c6f3441 | 5043 | { |
48401fcf | 5044 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
5045 | return; |
5046 | } | |
8358c818 ILT |
5047 | s = "sdc1"; |
5048 | coproc = 1; | |
efec4a28 | 5049 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
5050 | goto st; |
5051 | case M_SDC2_AB: | |
5052 | s = "sdc2"; | |
efec4a28 | 5053 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
5054 | coproc = 1; |
5055 | goto st; | |
5056 | case M_SDC3_AB: | |
5057 | s = "sdc3"; | |
efec4a28 | 5058 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
5059 | coproc = 1; |
5060 | goto st; | |
5061 | case M_SDL_AB: | |
5062 | s = "sdl"; | |
5063 | goto st; | |
5064 | case M_SDR_AB: | |
5065 | s = "sdr"; | |
3d3c5039 | 5066 | st: |
670a50eb ILT |
5067 | tempreg = AT; |
5068 | used_at = 1; | |
3d3c5039 | 5069 | ld_st: |
efec4a28 | 5070 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
5071 | if (mask == M_LWC1_AB |
5072 | || mask == M_SWC1_AB | |
8358c818 | 5073 | || mask == M_LDC1_AB |
0dd2d296 ILT |
5074 | || mask == M_SDC1_AB |
5075 | || mask == M_L_DAB | |
5076 | || mask == M_S_DAB) | |
670a50eb | 5077 | fmt = "T,o(b)"; |
8358c818 | 5078 | else if (coproc) |
19ed8960 | 5079 | fmt = "E,o(b)"; |
670a50eb ILT |
5080 | else |
5081 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
5082 | |
5083 | if (offset_expr.X_op != O_constant | |
5084 | && offset_expr.X_op != O_symbol) | |
5085 | { | |
48401fcf | 5086 | as_bad (_("expression too complex")); |
0dd2d296 ILT |
5087 | offset_expr.X_op = O_constant; |
5088 | } | |
5089 | ||
5090 | /* A constant expression in PIC code can be handled just as it | |
5091 | is in non PIC code. */ | |
d9aba805 | 5092 | if (mips_pic == NO_PIC |
0dd2d296 | 5093 | || offset_expr.X_op == O_constant) |
670a50eb | 5094 | { |
0dd2d296 ILT |
5095 | /* If this is a reference to a GP relative symbol, and there |
5096 | is no base register, we want | |
5097 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 5098 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
5099 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
5100 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5101 | If we have a constant, we need two instructions anyhow, | |
5102 | so we always use the latter form. | |
5103 | ||
5104 | If we have a base register, and this is a reference to a | |
5105 | GP relative symbol, we want | |
5106 | addu $tempreg,$breg,$gp | |
5107 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
5108 | Otherwise we want | |
5109 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5110 | addu $tempreg,$tempreg,$breg | |
5111 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5112 | With a constant we always use the latter case. */ | |
670a50eb ILT |
5113 | if (breg == 0) |
5114 | { | |
7a15a226 | 5115 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 5116 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
5117 | p = NULL; |
5118 | else | |
5119 | { | |
8ea7f4e8 | 5120 | frag_grow (20); |
0dd2d296 ILT |
5121 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5122 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5123 | p = frag_var (rs_machine_dependent, 8, 0, | |
5124 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3c83da8a JW |
5125 | (mips_opts.warn_about_macros |
5126 | || (used_at | |
5127 | && mips_opts.noat))), | |
f59fb6ca | 5128 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5129 | (char *) NULL); |
8197b589 | 5130 | used_at = 0; |
0dd2d296 ILT |
5131 | } |
5132 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5133 | if (p != NULL) | |
5134 | p += 4; | |
5135 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5136 | (int) BFD_RELOC_LO16, tempreg); | |
5137 | } | |
5138 | else | |
5139 | { | |
7a15a226 | 5140 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 5141 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
5142 | p = NULL; |
5143 | else | |
5144 | { | |
8ea7f4e8 | 5145 | frag_grow (28); |
0dd2d296 | 5146 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5147 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5148 | || mips_opts.isa < 3) | |
5149 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5150 | "d,v,t", tempreg, breg, GP); |
5151 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5152 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5153 | p = frag_var (rs_machine_dependent, 12, 0, | |
5154 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
f59fb6ca | 5155 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
5156 | (char *) NULL); |
5157 | } | |
5158 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5159 | if (p != NULL) | |
5160 | p += 4; | |
5161 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5162 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5163 | || mips_opts.isa < 3) | |
5164 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5165 | "d,v,t", tempreg, tempreg, breg); |
5166 | if (p != NULL) | |
5167 | p += 4; | |
5168 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5169 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 5170 | } |
670a50eb | 5171 | } |
fb251650 | 5172 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5173 | { |
0dd2d296 ILT |
5174 | /* If this is a reference to an external symbol, we want |
5175 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5176 | nop | |
5177 | <op> $treg,0($tempreg) | |
5178 | Otherwise we want | |
5179 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5180 | nop | |
5181 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5182 | <op> $treg,0($tempreg) | |
5183 | If there is a base register, we add it to $tempreg before | |
5184 | the <op>. If there is a constant, we stick it in the | |
5185 | <op> instruction. We don't handle constants larger than | |
5186 | 16 bits, because we have no way to load the upper 16 bits | |
5187 | (actually, we could handle them for the subset of cases | |
5188 | in which we are not using $at). */ | |
5189 | assert (offset_expr.X_op == O_symbol); | |
5190 | expr1.X_add_number = offset_expr.X_add_number; | |
5191 | offset_expr.X_add_number = 0; | |
5192 | if (expr1.X_add_number < -0x8000 | |
5193 | || expr1.X_add_number >= 0x8000) | |
48401fcf | 5194 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
8ea7f4e8 | 5195 | frag_grow (20); |
0dd2d296 | 5196 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a1f3160 JL |
5197 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5198 | || mips_opts.isa < 3) | |
5199 | ? "lw" : "ld"), | |
0dd2d296 ILT |
5200 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
5201 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5202 | p = frag_var (rs_machine_dependent, 4, 0, | |
5203 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca | 5204 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
5205 | (char *) NULL); |
5206 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5207 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5208 | || mips_opts.isa < 3) | |
5209 | ? "addiu" : "daddiu"), | |
0dd2d296 | 5210 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
670a50eb | 5211 | if (breg != 0) |
0dd2d296 | 5212 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5213 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5214 | || mips_opts.isa < 3) | |
5215 | ? "addu" : "daddu"), | |
6e8dda9c | 5216 | "d,v,t", tempreg, tempreg, breg); |
0dd2d296 ILT |
5217 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
5218 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 5219 | } |
fb251650 ILT |
5220 | else if (mips_pic == SVR4_PIC) |
5221 | { | |
5222 | int gpdel; | |
5223 | ||
5224 | /* If this is a reference to an external symbol, we want | |
5225 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5226 | addu $tempreg,$tempreg,$gp | |
5227 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5228 | <op> $treg,0($tempreg) | |
5229 | Otherwise we want | |
5230 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5231 | nop | |
5232 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5233 | <op> $treg,0($tempreg) | |
5234 | If there is a base register, we add it to $tempreg before | |
5235 | the <op>. If there is a constant, we stick it in the | |
5236 | <op> instruction. We don't handle constants larger than | |
5237 | 16 bits, because we have no way to load the upper 16 bits | |
5238 | (actually, we could handle them for the subset of cases | |
5239 | in which we are not using $at). */ | |
5240 | assert (offset_expr.X_op == O_symbol); | |
5241 | expr1.X_add_number = offset_expr.X_add_number; | |
5242 | offset_expr.X_add_number = 0; | |
5243 | if (expr1.X_add_number < -0x8000 | |
5244 | || expr1.X_add_number >= 0x8000) | |
48401fcf | 5245 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
fb251650 ILT |
5246 | if (reg_needs_delay (GP)) |
5247 | gpdel = 4; | |
5248 | else | |
5249 | gpdel = 0; | |
5250 | frag_grow (36); | |
5251 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5252 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5253 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5254 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5255 | || mips_opts.isa < 3) | |
5256 | ? "addu" : "daddu"), | |
fb251650 ILT |
5257 | "d,v,t", tempreg, tempreg, GP); |
5258 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5259 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5260 | || mips_opts.isa < 3) | |
5261 | ? "lw" : "ld"), | |
867a58b3 ILT |
5262 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
5263 | tempreg); | |
fb251650 ILT |
5264 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
5265 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
f59fb6ca | 5266 | offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
5267 | if (gpdel > 0) |
5268 | { | |
5269 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5270 | p += 4; | |
5271 | } | |
5272 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5273 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5274 | || mips_opts.isa < 3) | |
5275 | ? "lw" : "ld"), | |
867a58b3 | 5276 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
5277 | p += 4; |
5278 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5279 | p += 4; | |
5280 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5281 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5282 | || mips_opts.isa < 3) | |
5283 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
5284 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5285 | if (breg != 0) | |
5286 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5287 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5288 | || mips_opts.isa < 3) | |
5289 | ? "addu" : "daddu"), | |
fb251650 ILT |
5290 | "d,v,t", tempreg, tempreg, breg); |
5291 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5292 | (int) BFD_RELOC_LO16, tempreg); | |
5293 | } | |
d9aba805 ILT |
5294 | else if (mips_pic == EMBEDDED_PIC) |
5295 | { | |
5296 | /* If there is no base register, we want | |
5297 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5298 | If there is a base register, we want | |
5299 | addu $tempreg,$breg,$gp | |
5300 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
5301 | */ | |
5302 | assert (offset_expr.X_op == O_symbol); | |
5303 | if (breg == 0) | |
5304 | { | |
5305 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5306 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5307 | used_at = 0; | |
5308 | } | |
5309 | else | |
5310 | { | |
5311 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5312 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5313 | || mips_opts.isa < 3) | |
5314 | ? "addu" : "daddu"), | |
d9aba805 ILT |
5315 | "d,v,t", tempreg, breg, GP); |
5316 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5317 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5318 | } | |
5319 | } | |
5320 | else | |
5321 | abort (); | |
0dd2d296 ILT |
5322 | |
5323 | if (! used_at) | |
5324 | return; | |
5325 | ||
5326 | break; | |
3d3c5039 ILT |
5327 | |
5328 | case M_LI: | |
19ed8960 | 5329 | case M_LI_S: |
d8a1c247 KR |
5330 | load_register (&icnt, treg, &imm_expr, 0); |
5331 | return; | |
5332 | ||
5333 | case M_DLI: | |
5334 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 5335 | return; |
3d3c5039 | 5336 | |
0dd2d296 | 5337 | case M_LI_SS: |
55933a58 | 5338 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 5339 | { |
d8a1c247 | 5340 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
5341 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
5342 | "mtc1", "t,G", AT, treg); | |
5343 | break; | |
0dd2d296 | 5344 | } |
d9aba805 | 5345 | else |
d2c71068 | 5346 | { |
55933a58 ILT |
5347 | assert (offset_expr.X_op == O_symbol |
5348 | && strcmp (segment_name (S_GET_SEGMENT | |
5349 | (offset_expr.X_add_symbol)), | |
5350 | ".lit4") == 0 | |
5351 | && offset_expr.X_add_number == 0); | |
5352 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5353 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
5354 | return; |
5355 | } | |
0dd2d296 | 5356 | |
3d3c5039 | 5357 | case M_LI_D: |
a5586bdc ILT |
5358 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is |
5359 | the entire value, and in mips1 mode it is the high order 32 | |
5360 | bits of the value and the low order 32 bits are either zero | |
5361 | or in offset_expr. */ | |
5362 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5363 | { | |
517640d9 ILT |
5364 | if (mips_opts.isa >= 3) |
5365 | load_register (&icnt, treg, &imm_expr, 1); | |
5366 | else | |
a5586bdc | 5367 | { |
517640d9 ILT |
5368 | int hreg, lreg; |
5369 | ||
5370 | if (target_big_endian) | |
5371 | { | |
5372 | hreg = treg; | |
5373 | lreg = treg + 1; | |
5374 | } | |
a5586bdc ILT |
5375 | else |
5376 | { | |
517640d9 ILT |
5377 | hreg = treg + 1; |
5378 | lreg = treg; | |
5379 | } | |
5380 | ||
5381 | if (hreg <= 31) | |
5382 | load_register (&icnt, hreg, &imm_expr, 0); | |
5383 | if (lreg <= 31) | |
5384 | { | |
5385 | if (offset_expr.X_op == O_absent) | |
5386 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", | |
5387 | lreg, 0); | |
5388 | else | |
5389 | { | |
5390 | assert (offset_expr.X_op == O_constant); | |
5391 | load_register (&icnt, lreg, &offset_expr, 0); | |
5392 | } | |
a5586bdc ILT |
5393 | } |
5394 | } | |
5395 | return; | |
5396 | } | |
5397 | ||
d9aba805 ILT |
5398 | /* We know that sym is in the .rdata section. First we get the |
5399 | upper 16 bits of the address. */ | |
5400 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
5401 | { |
5402 | /* FIXME: This won't work for a 64 bit address. */ | |
5403 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5404 | } | |
d9aba805 | 5405 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
5406 | { |
5407 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5408 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5409 | || mips_opts.isa < 3) | |
5410 | ? "lw" : "ld"), | |
0dd2d296 ILT |
5411 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5412 | } | |
d9aba805 ILT |
5413 | else if (mips_pic == EMBEDDED_PIC) |
5414 | { | |
5415 | /* For embedded PIC we pick up the entire address off $gp in | |
5416 | a single instruction. */ | |
5417 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5418 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5419 | || mips_opts.isa < 3) | |
5420 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
5421 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); |
5422 | offset_expr.X_op = O_constant; | |
5423 | offset_expr.X_add_number = 0; | |
5424 | } | |
5425 | else | |
5426 | abort (); | |
5427 | ||
0dd2d296 | 5428 | /* Now we load the register(s). */ |
3c83da8a | 5429 | if (mips_opts.isa >= 3) |
0dd2d296 ILT |
5430 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
5431 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
5432 | else |
5433 | { | |
0dd2d296 ILT |
5434 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
5435 | treg, (int) BFD_RELOC_LO16, AT); | |
5436 | if (treg != 31) | |
5437 | { | |
5438 | /* FIXME: How in the world do we deal with the possible | |
5439 | overflow here? */ | |
5440 | offset_expr.X_add_number += 4; | |
5441 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5442 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
5443 | } | |
8358c818 | 5444 | } |
d2c71068 ILT |
5445 | |
5446 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5447 | does not become a variant frag. */ | |
5448 | frag_wane (frag_now); | |
5449 | frag_new (0); | |
5450 | ||
670a50eb | 5451 | break; |
3d3c5039 ILT |
5452 | |
5453 | case M_LI_DD: | |
a5586bdc ILT |
5454 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is |
5455 | the entire value, and in mips1 mode it is the high order 32 | |
5456 | bits of the value and the low order 32 bits are either zero | |
5457 | or in offset_expr. */ | |
5458 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5459 | { | |
5460 | load_register (&icnt, AT, &imm_expr, mips_opts.isa >= 3); | |
5461 | if (mips_opts.isa >= 3) | |
5462 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5463 | "dmtc1", "t,S", AT, treg); | |
5464 | else | |
5465 | { | |
5466 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5467 | "mtc1", "t,G", AT, treg + 1); | |
5468 | if (offset_expr.X_op == O_absent) | |
5469 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5470 | "mtc1", "t,G", 0, treg); | |
5471 | else | |
5472 | { | |
5473 | assert (offset_expr.X_op == O_constant); | |
5474 | load_register (&icnt, AT, &offset_expr, 0); | |
5475 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5476 | "mtc1", "t,G", AT, treg); | |
5477 | } | |
5478 | } | |
5479 | break; | |
5480 | } | |
5481 | ||
55933a58 ILT |
5482 | assert (offset_expr.X_op == O_symbol |
5483 | && offset_expr.X_add_number == 0); | |
5484 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
5485 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 5486 | { |
3c83da8a | 5487 | if (mips_opts.isa >= 2) |
0dd2d296 ILT |
5488 | { |
5489 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5490 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5491 | return; | |
5492 | } | |
5493 | breg = GP; | |
5494 | r = BFD_RELOC_MIPS_LITERAL; | |
5495 | goto dob; | |
5496 | } | |
55933a58 | 5497 | else |
0dd2d296 | 5498 | { |
55933a58 ILT |
5499 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
5500 | if (mips_pic == SVR4_PIC) | |
5501 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5502 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5503 | || mips_opts.isa < 3) | |
5504 | ? "lw" : "ld"), | |
55933a58 ILT |
5505 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5506 | else | |
5507 | { | |
5508 | /* FIXME: This won't work for a 64 bit address. */ | |
5509 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5510 | } | |
5511 | ||
3c83da8a | 5512 | if (mips_opts.isa >= 2) |
0dd2d296 ILT |
5513 | { |
5514 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 5515 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
5516 | |
5517 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5518 | that this does not become a variant frag. */ | |
5519 | frag_wane (frag_now); | |
5520 | frag_new (0); | |
5521 | ||
0dd2d296 ILT |
5522 | break; |
5523 | } | |
5524 | breg = AT; | |
5525 | r = BFD_RELOC_LO16; | |
5526 | goto dob; | |
8358c818 | 5527 | } |
9226253a | 5528 | |
3d3c5039 | 5529 | case M_L_DOB: |
de484a06 | 5530 | if (mips_cpu == 4650) |
1c6f3441 | 5531 | { |
48401fcf | 5532 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
5533 | return; |
5534 | } | |
9a7d824a ILT |
5535 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5536 | to adjust when loading from memory. */ | |
9226253a ILT |
5537 | r = BFD_RELOC_LO16; |
5538 | dob: | |
3c83da8a | 5539 | assert (mips_opts.isa < 2); |
0dd2d296 | 5540 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 5541 | target_big_endian ? treg + 1 : treg, |
9226253a | 5542 | (int) r, breg); |
0dd2d296 ILT |
5543 | /* FIXME: A possible overflow which I don't know how to deal |
5544 | with. */ | |
670a50eb | 5545 | offset_expr.X_add_number += 4; |
0dd2d296 | 5546 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 5547 | target_big_endian ? treg : treg + 1, |
9226253a | 5548 | (int) r, breg); |
d2c71068 ILT |
5549 | |
5550 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5551 | does not become a variant frag. */ | |
5552 | frag_wane (frag_now); | |
5553 | frag_new (0); | |
5554 | ||
0dd2d296 ILT |
5555 | if (breg != AT) |
5556 | return; | |
5557 | break; | |
3d3c5039 ILT |
5558 | |
5559 | case M_L_DAB: | |
670a50eb ILT |
5560 | /* |
5561 | * The MIPS assembler seems to check for X_add_number not | |
5562 | * being double aligned and generating: | |
5563 | * lui at,%hi(foo+1) | |
5564 | * addu at,at,v1 | |
5565 | * addiu at,at,%lo(foo+1) | |
5566 | * lwc1 f2,0(at) | |
5567 | * lwc1 f3,4(at) | |
5568 | * But, the resulting address is the same after relocation so why | |
5569 | * generate the extra instruction? | |
5570 | */ | |
de484a06 | 5571 | if (mips_cpu == 4650) |
1c6f3441 | 5572 | { |
48401fcf | 5573 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
5574 | return; |
5575 | } | |
efec4a28 | 5576 | /* Itbl support may require additional care here. */ |
4032d3f0 | 5577 | coproc = 1; |
3c83da8a | 5578 | if (mips_opts.isa >= 2) |
670a50eb | 5579 | { |
0dd2d296 ILT |
5580 | s = "ldc1"; |
5581 | goto ld; | |
670a50eb | 5582 | } |
0dd2d296 ILT |
5583 | |
5584 | s = "lwc1"; | |
5585 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
5586 | goto ldd_std; |
5587 | ||
5588 | case M_S_DAB: | |
de484a06 | 5589 | if (mips_cpu == 4650) |
1c6f3441 | 5590 | { |
48401fcf | 5591 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
5592 | return; |
5593 | } | |
5594 | ||
3c83da8a | 5595 | if (mips_opts.isa >= 2) |
8358c818 | 5596 | { |
0dd2d296 ILT |
5597 | s = "sdc1"; |
5598 | goto st; | |
8358c818 | 5599 | } |
3d3c5039 | 5600 | |
0dd2d296 ILT |
5601 | s = "swc1"; |
5602 | fmt = "T,o(b)"; | |
efec4a28 | 5603 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5604 | coproc = 1; |
5605 | goto ldd_std; | |
3d3c5039 ILT |
5606 | |
5607 | case M_LD_AB: | |
3c83da8a | 5608 | if (mips_opts.isa >= 3) |
670a50eb | 5609 | { |
0dd2d296 ILT |
5610 | s = "ld"; |
5611 | goto ld; | |
670a50eb | 5612 | } |
0dd2d296 ILT |
5613 | |
5614 | s = "lw"; | |
5615 | fmt = "t,o(b)"; | |
5616 | goto ldd_std; | |
5617 | ||
5618 | case M_SD_AB: | |
3c83da8a | 5619 | if (mips_opts.isa >= 3) |
670a50eb | 5620 | { |
0dd2d296 ILT |
5621 | s = "sd"; |
5622 | goto st; | |
670a50eb | 5623 | } |
0dd2d296 | 5624 | |
670a50eb | 5625 | s = "sw"; |
0dd2d296 ILT |
5626 | fmt = "t,o(b)"; |
5627 | ||
5628 | ldd_std: | |
5629 | if (offset_expr.X_op != O_symbol | |
5630 | && offset_expr.X_op != O_constant) | |
670a50eb | 5631 | { |
48401fcf | 5632 | as_bad (_("expression too complex")); |
0dd2d296 ILT |
5633 | offset_expr.X_op = O_constant; |
5634 | } | |
5635 | ||
5636 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5637 | to adjust when loading from memory. We set coproc if we must | |
5638 | load $fn+1 first. */ | |
efec4a28 | 5639 | /* Itbl support may require additional care here. */ |
b9129c6f | 5640 | if (! target_big_endian) |
0dd2d296 ILT |
5641 | coproc = 0; |
5642 | ||
d9aba805 | 5643 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
5644 | || offset_expr.X_op == O_constant) |
5645 | { | |
5646 | /* If this is a reference to a GP relative symbol, we want | |
5647 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5648 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5649 | If we have a base register, we use this | |
5650 | addu $at,$breg,$gp | |
5651 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5652 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5653 | If this is not a GP relative symbol, we want | |
5654 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5655 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5656 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5657 | If there is a base register, we add it to $at after the | |
5658 | lui instruction. If there is a constant, we always use | |
5659 | the last case. */ | |
7a15a226 | 5660 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 5661 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
670a50eb | 5662 | { |
0dd2d296 ILT |
5663 | p = NULL; |
5664 | used_at = 1; | |
670a50eb ILT |
5665 | } |
5666 | else | |
0dd2d296 ILT |
5667 | { |
5668 | int off; | |
5669 | ||
5670 | if (breg == 0) | |
5671 | { | |
8ea7f4e8 | 5672 | frag_grow (28); |
0dd2d296 ILT |
5673 | tempreg = GP; |
5674 | off = 0; | |
5675 | used_at = 0; | |
5676 | } | |
5677 | else | |
5678 | { | |
8ea7f4e8 | 5679 | frag_grow (36); |
0dd2d296 | 5680 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5681 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5682 | || mips_opts.isa < 3) | |
5683 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5684 | "d,v,t", AT, breg, GP); |
5685 | tempreg = AT; | |
5686 | off = 4; | |
5687 | used_at = 1; | |
5688 | } | |
5689 | ||
efec4a28 | 5690 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5691 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5692 | coproc ? treg + 1 : treg, | |
5693 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5694 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
5695 | |
5696 | /* Set mips_optimize to 2 to avoid inserting an | |
5697 | undesired nop. */ | |
5698 | hold_mips_optimize = mips_optimize; | |
5699 | mips_optimize = 2; | |
efec4a28 | 5700 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5701 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5702 | coproc ? treg : treg + 1, | |
5703 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
5704 | mips_optimize = hold_mips_optimize; |
5705 | ||
0dd2d296 ILT |
5706 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
5707 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
3c83da8a | 5708 | used_at && mips_opts.noat), |
f59fb6ca | 5709 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5710 | (char *) NULL); |
777ad64d ILT |
5711 | |
5712 | /* We just generated two relocs. When tc_gen_reloc | |
5713 | handles this case, it will skip the first reloc and | |
5714 | handle the second. The second reloc already has an | |
5715 | extra addend of 4, which we added above. We must | |
5716 | subtract it out, and then subtract another 4 to make | |
5717 | the first reloc come out right. The second reloc | |
5718 | will come out right because we are going to add 4 to | |
703f5e6e ILT |
5719 | offset_expr when we build its instruction below. |
5720 | ||
5721 | If we have a symbol, then we don't want to include | |
5722 | the offset, because it will wind up being included | |
5723 | when we generate the reloc. */ | |
5724 | ||
5725 | if (offset_expr.X_op == O_constant) | |
5726 | offset_expr.X_add_number -= 8; | |
5727 | else | |
5728 | { | |
5729 | offset_expr.X_add_number = -4; | |
5730 | offset_expr.X_op = O_constant; | |
5731 | } | |
0dd2d296 ILT |
5732 | } |
5733 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
5734 | if (p != NULL) | |
5735 | p += 4; | |
5736 | if (breg != 0) | |
5737 | { | |
5738 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5739 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5740 | || mips_opts.isa < 3) | |
5741 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5742 | "d,v,t", AT, breg, AT); |
5743 | if (p != NULL) | |
5744 | p += 4; | |
5745 | } | |
efec4a28 | 5746 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5747 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5748 | coproc ? treg + 1 : treg, | |
5749 | (int) BFD_RELOC_LO16, AT); | |
5750 | if (p != NULL) | |
5751 | p += 4; | |
5752 | /* FIXME: How do we handle overflow here? */ | |
5753 | offset_expr.X_add_number += 4; | |
efec4a28 | 5754 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5755 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5756 | coproc ? treg : treg + 1, | |
5757 | (int) BFD_RELOC_LO16, AT); | |
5758 | } | |
fb251650 | 5759 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5760 | { |
0dd2d296 ILT |
5761 | int off; |
5762 | ||
5763 | /* If this is a reference to an external symbol, we want | |
5764 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5765 | nop | |
5766 | <op> $treg,0($at) | |
5767 | <op> $treg+1,4($at) | |
5768 | Otherwise we want | |
5769 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5770 | nop | |
5771 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5772 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5773 | If there is a base register we add it to $at before the | |
5774 | lwc1 instructions. If there is a constant we include it | |
5775 | in the lwc1 instructions. */ | |
5776 | used_at = 1; | |
5777 | expr1.X_add_number = offset_expr.X_add_number; | |
5778 | offset_expr.X_add_number = 0; | |
5779 | if (expr1.X_add_number < -0x8000 | |
5780 | || expr1.X_add_number >= 0x8000 - 4) | |
48401fcf | 5781 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
0dd2d296 ILT |
5782 | if (breg == 0) |
5783 | off = 0; | |
5784 | else | |
5785 | off = 4; | |
8ea7f4e8 | 5786 | frag_grow (24 + off); |
0dd2d296 | 5787 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a1f3160 JL |
5788 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5789 | || mips_opts.isa < 3) | |
5790 | ? "lw" : "ld"), | |
0dd2d296 ILT |
5791 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5792 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 5793 | if (breg != 0) |
0dd2d296 | 5794 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5795 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5796 | || mips_opts.isa < 3) | |
5797 | ? "addu" : "daddu"), | |
0dd2d296 | 5798 | "d,v,t", AT, breg, AT); |
efec4a28 | 5799 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5800 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5801 | coproc ? treg + 1 : treg, | |
5802 | (int) BFD_RELOC_LO16, AT); | |
5803 | expr1.X_add_number += 4; | |
55933a58 ILT |
5804 | |
5805 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5806 | nop. */ | |
5807 | hold_mips_optimize = mips_optimize; | |
5808 | mips_optimize = 2; | |
efec4a28 | 5809 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5810 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5811 | coproc ? treg : treg + 1, | |
5812 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
5813 | mips_optimize = hold_mips_optimize; |
5814 | ||
0dd2d296 ILT |
5815 | (void) frag_var (rs_machine_dependent, 0, 0, |
5816 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
f59fb6ca | 5817 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5818 | (char *) NULL); |
8358c818 | 5819 | } |
fb251650 ILT |
5820 | else if (mips_pic == SVR4_PIC) |
5821 | { | |
5822 | int gpdel, off; | |
5823 | ||
5824 | /* If this is a reference to an external symbol, we want | |
5825 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5826 | addu $at,$at,$gp | |
5827 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5828 | nop | |
5829 | <op> $treg,0($at) | |
5830 | <op> $treg+1,4($at) | |
5831 | Otherwise we want | |
5832 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5833 | nop | |
5834 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5835 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5836 | If there is a base register we add it to $at before the | |
5837 | lwc1 instructions. If there is a constant we include it | |
5838 | in the lwc1 instructions. */ | |
5839 | used_at = 1; | |
5840 | expr1.X_add_number = offset_expr.X_add_number; | |
5841 | offset_expr.X_add_number = 0; | |
5842 | if (expr1.X_add_number < -0x8000 | |
5843 | || expr1.X_add_number >= 0x8000 - 4) | |
48401fcf | 5844 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
fb251650 ILT |
5845 | if (reg_needs_delay (GP)) |
5846 | gpdel = 4; | |
5847 | else | |
5848 | gpdel = 0; | |
5849 | if (breg == 0) | |
5850 | off = 0; | |
5851 | else | |
5852 | off = 4; | |
5853 | frag_grow (56); | |
5854 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5855 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5856 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5857 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5858 | || mips_opts.isa < 3) | |
5859 | ? "addu" : "daddu"), | |
fb251650 ILT |
5860 | "d,v,t", AT, AT, GP); |
5861 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5862 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5863 | || mips_opts.isa < 3) | |
5864 | ? "lw" : "ld"), | |
fb251650 ILT |
5865 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
5866 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5867 | if (breg != 0) | |
5868 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5869 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5870 | || mips_opts.isa < 3) | |
5871 | ? "addu" : "daddu"), | |
fb251650 | 5872 | "d,v,t", AT, breg, AT); |
efec4a28 | 5873 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5874 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5875 | coproc ? treg + 1 : treg, | |
5876 | (int) BFD_RELOC_LO16, AT); | |
5877 | expr1.X_add_number += 4; | |
5878 | ||
5879 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5880 | nop. */ | |
5881 | hold_mips_optimize = mips_optimize; | |
5882 | mips_optimize = 2; | |
efec4a28 | 5883 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5884 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5885 | coproc ? treg : treg + 1, | |
5886 | (int) BFD_RELOC_LO16, AT); | |
5887 | mips_optimize = hold_mips_optimize; | |
5888 | expr1.X_add_number -= 4; | |
5889 | ||
5890 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5891 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5892 | 8 + gpdel + off, 1, 0), | |
f59fb6ca | 5893 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
5894 | (char *) NULL); |
5895 | if (gpdel > 0) | |
5896 | { | |
5897 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5898 | p += 4; | |
5899 | } | |
5900 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5901 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5902 | || mips_opts.isa < 3) | |
5903 | ? "lw" : "ld"), | |
fb251650 ILT |
5904 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5905 | p += 4; | |
5906 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5907 | p += 4; | |
5908 | if (breg != 0) | |
5909 | { | |
5910 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5911 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5912 | || mips_opts.isa < 3) | |
5913 | ? "addu" : "daddu"), | |
fb251650 ILT |
5914 | "d,v,t", AT, breg, AT); |
5915 | p += 4; | |
5916 | } | |
efec4a28 | 5917 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5918 | macro_build (p, &icnt, &expr1, s, fmt, |
5919 | coproc ? treg + 1 : treg, | |
5920 | (int) BFD_RELOC_LO16, AT); | |
5921 | p += 4; | |
5922 | expr1.X_add_number += 4; | |
5923 | ||
5924 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5925 | nop. */ | |
5926 | hold_mips_optimize = mips_optimize; | |
5927 | mips_optimize = 2; | |
efec4a28 | 5928 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5929 | macro_build (p, &icnt, &expr1, s, fmt, |
5930 | coproc ? treg : treg + 1, | |
5931 | (int) BFD_RELOC_LO16, AT); | |
5932 | mips_optimize = hold_mips_optimize; | |
5933 | } | |
d9aba805 ILT |
5934 | else if (mips_pic == EMBEDDED_PIC) |
5935 | { | |
5936 | /* If there is no base register, we use | |
5937 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5938 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5939 | If we have a base register, we use | |
5940 | addu $at,$breg,$gp | |
5941 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5942 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5943 | */ | |
5944 | if (breg == 0) | |
5945 | { | |
5946 | tempreg = GP; | |
5947 | used_at = 0; | |
5948 | } | |
5949 | else | |
5950 | { | |
5951 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5952 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5953 | || mips_opts.isa < 3) | |
5954 | ? "addu" : "daddu"), | |
d9aba805 ILT |
5955 | "d,v,t", AT, breg, GP); |
5956 | tempreg = AT; | |
5957 | used_at = 1; | |
5958 | } | |
5959 | ||
efec4a28 | 5960 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5961 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5962 | coproc ? treg + 1 : treg, | |
5963 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5964 | offset_expr.X_add_number += 4; | |
efec4a28 | 5965 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5966 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5967 | coproc ? treg : treg + 1, | |
5968 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5969 | } | |
5970 | else | |
5971 | abort (); | |
0dd2d296 ILT |
5972 | |
5973 | if (! used_at) | |
5974 | return; | |
5975 | ||
5976 | break; | |
5977 | ||
5978 | case M_LD_OB: | |
5979 | s = "lw"; | |
5980 | goto sd_ob; | |
5981 | case M_SD_OB: | |
5982 | s = "sw"; | |
5983 | sd_ob: | |
9a1f3160 | 5984 | assert (bfd_arch_bits_per_address (stdoutput) == 32 || mips_opts.isa < 3); |
0dd2d296 ILT |
5985 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
5986 | (int) BFD_RELOC_LO16, breg); | |
5987 | offset_expr.X_add_number += 4; | |
5988 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5989 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 5990 | return; |
efec4a28 DP |
5991 | |
5992 | /* New code added to support COPZ instructions. | |
5993 | This code builds table entries out of the macros in mip_opcodes. | |
5994 | R4000 uses interlocks to handle coproc delays. | |
5995 | Other chips (like the R3000) require nops to be inserted for delays. | |
5996 | ||
5997 | FIXME: Currently, we require that the user handle delays. | |
5998 | In order to fill delay slots for non-interlocked chips, | |
5999 | we must have a way to specify delays based on the coprocessor. | |
6000 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6001 | What are the side-effects of the cop instruction? | |
6002 | What cache support might we have and what are its effects? | |
6003 | Both coprocessor & memory require delays. how long??? | |
6004 | What registers are read/set/modified? | |
6005 | ||
6006 | If an itbl is provided to interpret cop instructions, | |
6007 | this knowledge can be encoded in the itbl spec. */ | |
6008 | ||
6009 | case M_COP0: | |
65d2c7d3 | 6010 | s = "c0"; |
efec4a28 DP |
6011 | goto copz; |
6012 | case M_COP1: | |
65d2c7d3 | 6013 | s = "c1"; |
efec4a28 DP |
6014 | goto copz; |
6015 | case M_COP2: | |
65d2c7d3 | 6016 | s = "c2"; |
efec4a28 DP |
6017 | goto copz; |
6018 | case M_COP3: | |
65d2c7d3 | 6019 | s = "c3"; |
efec4a28 | 6020 | copz: |
65d2c7d3 JL |
6021 | /* For now we just do C (same as Cz). The parameter will be |
6022 | stored in insn_opcode by mips_ip. */ | |
6023 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
6024 | ip->insn_opcode); | |
efec4a28 DP |
6025 | return; |
6026 | ||
917fae09 SS |
6027 | #ifdef LOSING_COMPILER |
6028 | default: | |
efec4a28 DP |
6029 | /* Try and see if this is a new itbl instruction. |
6030 | This code builds table entries out of the macros in mip_opcodes. | |
6031 | FIXME: For now we just assemble the expression and pass it's | |
6032 | value along as a 32-bit immediate. | |
6033 | We may want to have the assembler assemble this value, | |
6034 | so that we gain the assembler's knowledge of delay slots, | |
6035 | symbols, etc. | |
6036 | Would it be more efficient to use mask (id) here? */ | |
6037 | if (itbl_have_entries | |
9218cee0 | 6038 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
efec4a28 DP |
6039 | { |
6040 | s = ip->insn_mo->name; | |
6041 | s2 = "cop3"; | |
9218cee0 | 6042 | coproc = ITBL_DECODE_PNUM (immed_expr);; |
efec4a28 DP |
6043 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); |
6044 | return; | |
6045 | } | |
917fae09 SS |
6046 | macro2 (ip); |
6047 | return; | |
6048 | } | |
3c83da8a | 6049 | if (mips_opts.noat) |
48401fcf | 6050 | as_warn (_("Macro used $at after \".set noat\"")); |
917fae09 SS |
6051 | } |
6052 | ||
6053 | static void | |
6054 | macro2 (ip) | |
6055 | struct mips_cl_insn *ip; | |
6056 | { | |
6057 | register int treg, sreg, dreg, breg; | |
6058 | int tempreg; | |
6059 | int mask; | |
6060 | int icnt = 0; | |
6061 | int used_at; | |
6062 | expressionS expr1; | |
6063 | const char *s; | |
6064 | const char *s2; | |
6065 | const char *fmt; | |
6066 | int likely = 0; | |
6067 | int dbl = 0; | |
6068 | int coproc = 0; | |
adcf2b9d | 6069 | int lr = 0; |
40f0c904 | 6070 | int imm = 0; |
adcf2b9d | 6071 | int off; |
917fae09 SS |
6072 | offsetT maxnum; |
6073 | bfd_reloc_code_real_type r; | |
6074 | char *p; | |
6075 | ||
6076 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
6077 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6078 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6079 | mask = ip->insn_mo->mask; | |
6080 | ||
6081 | expr1.X_op = O_constant; | |
6082 | expr1.X_op_symbol = NULL; | |
6083 | expr1.X_add_symbol = NULL; | |
6084 | expr1.X_add_number = 1; | |
6085 | ||
6086 | switch (mask) | |
6087 | { | |
6088 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 6089 | |
8358c818 ILT |
6090 | case M_DMUL: |
6091 | dbl = 1; | |
3d3c5039 | 6092 | case M_MUL: |
0dd2d296 | 6093 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6094 | dbl ? "dmultu" : "multu", |
6095 | "s,t", sreg, treg); | |
0dd2d296 | 6096 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 6097 | return; |
3d3c5039 | 6098 | |
8358c818 ILT |
6099 | case M_DMUL_I: |
6100 | dbl = 1; | |
3d3c5039 | 6101 | case M_MUL_I: |
8358c818 ILT |
6102 | /* The MIPS assembler some times generates shifts and adds. I'm |
6103 | not trying to be that fancy. GCC should do this for us | |
6104 | anyway. */ | |
d8a1c247 | 6105 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6106 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6107 | dbl ? "dmult" : "mult", |
6108 | "s,t", sreg, AT); | |
0dd2d296 | 6109 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 6110 | break; |
3d3c5039 | 6111 | |
40f0c904 FCE |
6112 | case M_DMULO_I: |
6113 | dbl = 1; | |
6114 | case M_MULO_I: | |
6115 | imm = 1; | |
6116 | goto do_mulo; | |
6117 | ||
8358c818 ILT |
6118 | case M_DMULO: |
6119 | dbl = 1; | |
6120 | case M_MULO: | |
40f0c904 | 6121 | do_mulo: |
fbcfacb7 | 6122 | mips_emit_delays (true); |
3c83da8a | 6123 | ++mips_opts.noreorder; |
0dd2d296 | 6124 | mips_any_noreorder = 1; |
40f0c904 FCE |
6125 | if (imm) |
6126 | load_register (&icnt, AT, &imm_expr, dbl); | |
0dd2d296 | 6127 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 | 6128 | dbl ? "dmult" : "mult", |
40f0c904 | 6129 | "s,t", sreg, imm ? AT : treg); |
0dd2d296 ILT |
6130 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
6131 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
6132 | dbl ? "dsra32" : "sra", |
6133 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 6134 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
6135 | if (mips_trap) |
6136 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
6137 | else | |
6138 | { | |
6139 | expr1.X_add_number = 8; | |
6140 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
6141 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
d9c2c0c5 | 6142 | /* start-sanitize-r5900 */ |
de484a06 | 6143 | if (mips_cpu == 5900) |
d9c2c0c5 FCE |
6144 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 6); |
6145 | else | |
6146 | /* end-sanitize-r5900 */ | |
6147 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
8ea7f4e8 | 6148 | } |
3c83da8a | 6149 | --mips_opts.noreorder; |
0dd2d296 | 6150 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
6151 | break; |
6152 | ||
40f0c904 FCE |
6153 | case M_DMULOU_I: |
6154 | dbl = 1; | |
6155 | case M_MULOU_I: | |
6156 | imm = 1; | |
6157 | goto do_mulou; | |
6158 | ||
8358c818 ILT |
6159 | case M_DMULOU: |
6160 | dbl = 1; | |
6161 | case M_MULOU: | |
40f0c904 | 6162 | do_mulou: |
fbcfacb7 | 6163 | mips_emit_delays (true); |
3c83da8a | 6164 | ++mips_opts.noreorder; |
0dd2d296 | 6165 | mips_any_noreorder = 1; |
40f0c904 FCE |
6166 | if (imm) |
6167 | load_register (&icnt, AT, &imm_expr, dbl); | |
0dd2d296 | 6168 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 | 6169 | dbl ? "dmultu" : "multu", |
40f0c904 | 6170 | "s,t", sreg, imm ? AT : treg); |
0dd2d296 ILT |
6171 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
6172 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
6173 | if (mips_trap) |
6174 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
6175 | else | |
6176 | { | |
6177 | expr1.X_add_number = 8; | |
6178 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
6179 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
d9c2c0c5 | 6180 | /* start-sanitize-r5900 */ |
de484a06 | 6181 | if (mips_cpu == 5900) |
d9c2c0c5 FCE |
6182 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 6); |
6183 | else | |
6184 | /* end-sanitize-r5900 */ | |
6185 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
8ea7f4e8 | 6186 | } |
3c83da8a | 6187 | --mips_opts.noreorder; |
8358c818 ILT |
6188 | break; |
6189 | ||
3d3c5039 | 6190 | case M_ROL: |
0dd2d296 ILT |
6191 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
6192 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6193 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
6194 | treg); | |
6195 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 6196 | break; |
3d3c5039 ILT |
6197 | |
6198 | case M_ROL_I: | |
5c6f5923 | 6199 | if (imm_expr.X_op != O_constant) |
48401fcf | 6200 | as_bad (_("rotate count too large")); |
0dd2d296 | 6201 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 6202 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 6203 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 6204 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 6205 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 6206 | break; |
3d3c5039 ILT |
6207 | |
6208 | case M_ROR: | |
0dd2d296 ILT |
6209 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
6210 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6211 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
6212 | treg); | |
6213 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 6214 | break; |
3d3c5039 ILT |
6215 | |
6216 | case M_ROR_I: | |
5c6f5923 | 6217 | if (imm_expr.X_op != O_constant) |
48401fcf | 6218 | as_bad (_("rotate count too large")); |
0dd2d296 | 6219 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 6220 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 6221 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 6222 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 6223 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 6224 | break; |
3d3c5039 ILT |
6225 | |
6226 | case M_S_DOB: | |
de484a06 | 6227 | if (mips_cpu == 4650) |
1c6f3441 | 6228 | { |
48401fcf | 6229 | as_bad (_("opcode not supported on this processor")); |
1c6f3441 ILT |
6230 | return; |
6231 | } | |
3c83da8a | 6232 | assert (mips_opts.isa < 2); |
9a7d824a ILT |
6233 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6234 | to adjust when storing to memory. */ | |
0dd2d296 | 6235 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 6236 | target_big_endian ? treg + 1 : treg, |
9226253a | 6237 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6238 | offset_expr.X_add_number += 4; |
0dd2d296 | 6239 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 6240 | target_big_endian ? treg : treg + 1, |
9226253a | 6241 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6242 | return; |
3d3c5039 | 6243 | |
3d3c5039 | 6244 | case M_SEQ: |
670a50eb | 6245 | if (sreg == 0) |
0dd2d296 ILT |
6246 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6247 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 6248 | else if (treg == 0) |
0dd2d296 ILT |
6249 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6250 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
6251 | else |
6252 | { | |
0dd2d296 ILT |
6253 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6254 | sreg, treg); | |
6255 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6256 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 6257 | } |
670a50eb | 6258 | return; |
3d3c5039 ILT |
6259 | |
6260 | case M_SEQ_I: | |
5c6f5923 | 6261 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 6262 | { |
0dd2d296 ILT |
6263 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6264 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6265 | return; |
3d3c5039 | 6266 | } |
670a50eb ILT |
6267 | if (sreg == 0) |
6268 | { | |
48401fcf | 6269 | as_warn (_("Instruction %s: result is always false"), |
6e8dda9c | 6270 | ip->insn_mo->name); |
0dd2d296 | 6271 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 6272 | return; |
3d3c5039 | 6273 | } |
5c6f5923 GRK |
6274 | if (imm_expr.X_op == O_constant |
6275 | && imm_expr.X_add_number >= 0 | |
6276 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 6277 | { |
0dd2d296 ILT |
6278 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
6279 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6280 | used_at = 0; |
6e8dda9c | 6281 | } |
5c6f5923 GRK |
6282 | else if (imm_expr.X_op == O_constant |
6283 | && imm_expr.X_add_number > -0x8000 | |
6284 | && imm_expr.X_add_number < 0) | |
6e8dda9c ILT |
6285 | { |
6286 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6287 | macro_build ((char *) NULL, &icnt, &imm_expr, |
9a1f3160 JL |
6288 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6289 | || mips_opts.isa < 3) | |
6290 | ? "addiu" : "daddiu"), | |
9226253a ILT |
6291 | "t,r,j", dreg, sreg, |
6292 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
6293 | used_at = 0; |
6294 | } | |
6295 | else | |
6296 | { | |
d8a1c247 | 6297 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6298 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6299 | sreg, AT); | |
670a50eb ILT |
6300 | used_at = 1; |
6301 | } | |
0dd2d296 | 6302 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 6303 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
6304 | if (used_at) |
6305 | break; | |
6306 | return; | |
3d3c5039 ILT |
6307 | |
6308 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
6309 | s = "slt"; |
6310 | goto sge; | |
3d3c5039 | 6311 | case M_SGEU: |
670a50eb | 6312 | s = "sltu"; |
3d3c5039 | 6313 | sge: |
0dd2d296 ILT |
6314 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
6315 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6316 | (int) BFD_RELOC_LO16); |
670a50eb | 6317 | return; |
3d3c5039 | 6318 | |
670a50eb | 6319 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 6320 | case M_SGEU_I: |
5c6f5923 GRK |
6321 | if (imm_expr.X_op == O_constant |
6322 | && imm_expr.X_add_number >= -0x8000 | |
6323 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6324 | { |
6b34ac5a | 6325 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 6326 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 6327 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
6328 | used_at = 0; |
6329 | } | |
6330 | else | |
6331 | { | |
d8a1c247 | 6332 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6333 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
6334 | mask == M_SGE_I ? "slt" : "sltu", |
6335 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
6336 | used_at = 1; |
6337 | } | |
0dd2d296 | 6338 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 6339 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
6340 | if (used_at) |
6341 | break; | |
6342 | return; | |
3d3c5039 ILT |
6343 | |
6344 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
6345 | s = "slt"; |
6346 | goto sgt; | |
3d3c5039 | 6347 | case M_SGTU: |
670a50eb | 6348 | s = "sltu"; |
3d3c5039 | 6349 | sgt: |
0dd2d296 | 6350 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 6351 | return; |
3d3c5039 | 6352 | |
670a50eb ILT |
6353 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
6354 | s = "slt"; | |
6355 | goto sgti; | |
3d3c5039 | 6356 | case M_SGTU_I: |
670a50eb | 6357 | s = "sltu"; |
3d3c5039 | 6358 | sgti: |
d8a1c247 | 6359 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6360 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 6361 | break; |
3d3c5039 | 6362 | |
670a50eb ILT |
6363 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
6364 | s = "slt"; | |
6365 | goto sle; | |
3d3c5039 | 6366 | case M_SLEU: |
670a50eb | 6367 | s = "sltu"; |
3d3c5039 | 6368 | sle: |
0dd2d296 ILT |
6369 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
6370 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6371 | (int) BFD_RELOC_LO16); |
670a50eb | 6372 | return; |
3d3c5039 | 6373 | |
670a50eb ILT |
6374 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
6375 | s = "slt"; | |
6376 | goto slei; | |
3d3c5039 | 6377 | case M_SLEU_I: |
670a50eb | 6378 | s = "sltu"; |
3d3c5039 | 6379 | slei: |
d8a1c247 | 6380 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6381 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
6382 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6383 | (int) BFD_RELOC_LO16); |
670a50eb | 6384 | break; |
3d3c5039 ILT |
6385 | |
6386 | case M_SLT_I: | |
5c6f5923 GRK |
6387 | if (imm_expr.X_op == O_constant |
6388 | && imm_expr.X_add_number >= -0x8000 | |
6389 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6390 | { |
0dd2d296 ILT |
6391 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
6392 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6393 | return; |
3d3c5039 | 6394 | } |
d8a1c247 | 6395 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6396 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 6397 | break; |
3d3c5039 ILT |
6398 | |
6399 | case M_SLTU_I: | |
5c6f5923 GRK |
6400 | if (imm_expr.X_op == O_constant |
6401 | && imm_expr.X_add_number >= -0x8000 | |
6402 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6403 | { |
0dd2d296 ILT |
6404 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
6405 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6406 | return; |
3d3c5039 | 6407 | } |
d8a1c247 | 6408 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6409 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
6410 | AT); | |
670a50eb | 6411 | break; |
3d3c5039 ILT |
6412 | |
6413 | case M_SNE: | |
670a50eb | 6414 | if (sreg == 0) |
0dd2d296 ILT |
6415 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6416 | treg); | |
670a50eb | 6417 | else if (treg == 0) |
0dd2d296 ILT |
6418 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6419 | sreg); | |
670a50eb ILT |
6420 | else |
6421 | { | |
0dd2d296 ILT |
6422 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6423 | sreg, treg); | |
6424 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6425 | dreg); | |
3d3c5039 | 6426 | } |
670a50eb | 6427 | return; |
3d3c5039 ILT |
6428 | |
6429 | case M_SNE_I: | |
5c6f5923 | 6430 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 6431 | { |
0dd2d296 ILT |
6432 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6433 | sreg); | |
670a50eb | 6434 | return; |
3d3c5039 | 6435 | } |
670a50eb ILT |
6436 | if (sreg == 0) |
6437 | { | |
48401fcf | 6438 | as_warn (_("Instruction %s: result is always true"), |
6e8dda9c | 6439 | ip->insn_mo->name); |
0dd2d296 | 6440 | macro_build ((char *) NULL, &icnt, &expr1, |
9a1f3160 JL |
6441 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6442 | || mips_opts.isa < 3) | |
6443 | ? "addiu" : "daddiu"), | |
9226253a | 6444 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 6445 | return; |
3d3c5039 | 6446 | } |
5c6f5923 GRK |
6447 | if (imm_expr.X_op == O_constant |
6448 | && imm_expr.X_add_number >= 0 | |
6449 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 6450 | { |
0dd2d296 ILT |
6451 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
6452 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6453 | used_at = 0; |
6e8dda9c | 6454 | } |
5c6f5923 GRK |
6455 | else if (imm_expr.X_op == O_constant |
6456 | && imm_expr.X_add_number > -0x8000 | |
6457 | && imm_expr.X_add_number < 0) | |
6e8dda9c ILT |
6458 | { |
6459 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6460 | macro_build ((char *) NULL, &icnt, &imm_expr, |
9a1f3160 JL |
6461 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6462 | || mips_opts.isa < 3) | |
6463 | ? "addiu" : "daddiu"), | |
9226253a | 6464 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
6465 | used_at = 0; |
6466 | } | |
6467 | else | |
6468 | { | |
d8a1c247 | 6469 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6470 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6471 | sreg, AT); | |
670a50eb ILT |
6472 | used_at = 1; |
6473 | } | |
0dd2d296 | 6474 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
6475 | if (used_at) |
6476 | break; | |
6477 | return; | |
3d3c5039 | 6478 | |
8358c818 ILT |
6479 | case M_DSUB_I: |
6480 | dbl = 1; | |
3d3c5039 | 6481 | case M_SUB_I: |
5c6f5923 GRK |
6482 | if (imm_expr.X_op == O_constant |
6483 | && imm_expr.X_add_number > -0x8000 | |
6484 | && imm_expr.X_add_number <= 0x8000) | |
670a50eb ILT |
6485 | { |
6486 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6487 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 6488 | dbl ? "daddi" : "addi", |
9226253a | 6489 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 6490 | return; |
3d3c5039 | 6491 | } |
d8a1c247 | 6492 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6493 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6494 | dbl ? "dsub" : "sub", |
6495 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 6496 | break; |
3d3c5039 | 6497 | |
8358c818 ILT |
6498 | case M_DSUBU_I: |
6499 | dbl = 1; | |
3d3c5039 | 6500 | case M_SUBU_I: |
5c6f5923 GRK |
6501 | if (imm_expr.X_op == O_constant |
6502 | && imm_expr.X_add_number > -0x8000 | |
6503 | && imm_expr.X_add_number <= 0x8000) | |
670a50eb ILT |
6504 | { |
6505 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6506 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 6507 | dbl ? "daddiu" : "addiu", |
9226253a | 6508 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 6509 | return; |
3d3c5039 | 6510 | } |
d8a1c247 | 6511 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6512 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6513 | dbl ? "dsubu" : "subu", |
6514 | "d,v,t", dreg, sreg, AT); | |
6515 | break; | |
6516 | ||
6517 | case M_TEQ_I: | |
6518 | s = "teq"; | |
6519 | goto trap; | |
6520 | case M_TGE_I: | |
6521 | s = "tge"; | |
6522 | goto trap; | |
6523 | case M_TGEU_I: | |
6524 | s = "tgeu"; | |
6525 | goto trap; | |
6526 | case M_TLT_I: | |
6527 | s = "tlt"; | |
6528 | goto trap; | |
6529 | case M_TLTU_I: | |
6530 | s = "tltu"; | |
6531 | goto trap; | |
6532 | case M_TNE_I: | |
6533 | s = "tne"; | |
6534 | trap: | |
d8a1c247 | 6535 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6536 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 6537 | break; |
3d3c5039 ILT |
6538 | |
6539 | case M_TRUNCWD: | |
6540 | case M_TRUNCWS: | |
3c83da8a | 6541 | assert (mips_opts.isa < 2); |
670a50eb ILT |
6542 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
6543 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
6544 | ||
6545 | /* | |
6546 | * Is the double cfc1 instruction a bug in the mips assembler; | |
6547 | * or is there a reason for it? | |
6548 | */ | |
fbcfacb7 | 6549 | mips_emit_delays (true); |
3c83da8a | 6550 | ++mips_opts.noreorder; |
0dd2d296 ILT |
6551 | mips_any_noreorder = 1; |
6552 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6553 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6554 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 6555 | expr1.X_add_number = 3; |
0dd2d296 | 6556 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 6557 | (int) BFD_RELOC_LO16); |
670a50eb | 6558 | expr1.X_add_number = 2; |
0dd2d296 | 6559 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 6560 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
6561 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
6562 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6563 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 6564 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
6565 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
6566 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
3c83da8a | 6567 | --mips_opts.noreorder; |
670a50eb | 6568 | break; |
3d3c5039 ILT |
6569 | |
6570 | case M_ULH: | |
670a50eb ILT |
6571 | s = "lb"; |
6572 | goto ulh; | |
3d3c5039 | 6573 | case M_ULHU: |
670a50eb | 6574 | s = "lbu"; |
3d3c5039 | 6575 | ulh: |
8ea7f4e8 | 6576 | if (offset_expr.X_add_number >= 0x7fff) |
48401fcf | 6577 | as_bad (_("operand overflow")); |
670a50eb | 6578 | /* avoid load delay */ |
b9129c6f | 6579 | if (! target_big_endian) |
8ea7f4e8 | 6580 | offset_expr.X_add_number += 1; |
0dd2d296 | 6581 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 6582 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6583 | if (! target_big_endian) |
8ea7f4e8 ILT |
6584 | offset_expr.X_add_number -= 1; |
6585 | else | |
6586 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6587 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 6588 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
6589 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
6590 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 6591 | break; |
3d3c5039 | 6592 | |
adcf2b9d ILT |
6593 | case M_ULD: |
6594 | s = "ldl"; | |
6595 | s2 = "ldr"; | |
6596 | off = 7; | |
6597 | goto ulw; | |
3d3c5039 | 6598 | case M_ULW: |
adcf2b9d ILT |
6599 | s = "lwl"; |
6600 | s2 = "lwr"; | |
6601 | off = 3; | |
6602 | ulw: | |
6603 | if (offset_expr.X_add_number >= 0x8000 - off) | |
48401fcf | 6604 | as_bad (_("operand overflow")); |
b9129c6f | 6605 | if (! target_big_endian) |
adcf2b9d ILT |
6606 | offset_expr.X_add_number += off; |
6607 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6608 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6609 | if (! target_big_endian) |
adcf2b9d | 6610 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6611 | else |
adcf2b9d ILT |
6612 | offset_expr.X_add_number += off; |
6613 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6614 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6615 | return; |
3d3c5039 | 6616 | |
adcf2b9d ILT |
6617 | case M_ULD_A: |
6618 | s = "ldl"; | |
6619 | s2 = "ldr"; | |
6620 | off = 7; | |
6621 | goto ulwa; | |
6622 | case M_ULW_A: | |
6623 | s = "lwl"; | |
6624 | s2 = "lwr"; | |
6625 | off = 3; | |
6626 | ulwa: | |
6627 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6628 | if (breg != 0) |
6629 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6630 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6631 | || mips_opts.isa < 3) | |
6632 | ? "addu" : "daddu"), | |
c625fc23 | 6633 | "d,v,t", AT, AT, breg); |
b9129c6f | 6634 | if (! target_big_endian) |
adcf2b9d ILT |
6635 | expr1.X_add_number = off; |
6636 | else | |
6637 | expr1.X_add_number = 0; | |
6638 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6639 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6640 | if (! target_big_endian) |
adcf2b9d ILT |
6641 | expr1.X_add_number = 0; |
6642 | else | |
6643 | expr1.X_add_number = off; | |
6644 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6645 | (int) BFD_RELOC_LO16, AT); | |
6646 | break; | |
6647 | ||
3d3c5039 ILT |
6648 | case M_ULH_A: |
6649 | case M_ULHU_A: | |
0dd2d296 | 6650 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6651 | if (breg != 0) |
6652 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6653 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6654 | || mips_opts.isa < 3) | |
6655 | ? "addu" : "daddu"), | |
c625fc23 | 6656 | "d,v,t", AT, AT, breg); |
b9129c6f | 6657 | if (target_big_endian) |
adcf2b9d ILT |
6658 | expr1.X_add_number = 0; |
6659 | macro_build ((char *) NULL, &icnt, &expr1, | |
6660 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
6661 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6662 | if (target_big_endian) |
adcf2b9d | 6663 | expr1.X_add_number = 1; |
670a50eb | 6664 | else |
adcf2b9d ILT |
6665 | expr1.X_add_number = 0; |
6666 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6667 | (int) BFD_RELOC_LO16, AT); | |
6668 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6669 | treg, 8); | |
6670 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6671 | treg, AT); | |
670a50eb | 6672 | break; |
3d3c5039 ILT |
6673 | |
6674 | case M_USH: | |
8ea7f4e8 | 6675 | if (offset_expr.X_add_number >= 0x7fff) |
48401fcf | 6676 | as_bad (_("operand overflow")); |
b9129c6f | 6677 | if (target_big_endian) |
8ea7f4e8 | 6678 | offset_expr.X_add_number += 1; |
0dd2d296 | 6679 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 6680 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 6681 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
b9129c6f | 6682 | if (target_big_endian) |
8ea7f4e8 ILT |
6683 | offset_expr.X_add_number -= 1; |
6684 | else | |
6685 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6686 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 6687 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6688 | break; |
3d3c5039 | 6689 | |
adcf2b9d ILT |
6690 | case M_USD: |
6691 | s = "sdl"; | |
6692 | s2 = "sdr"; | |
6693 | off = 7; | |
6694 | goto usw; | |
3d3c5039 | 6695 | case M_USW: |
adcf2b9d ILT |
6696 | s = "swl"; |
6697 | s2 = "swr"; | |
6698 | off = 3; | |
6699 | usw: | |
6700 | if (offset_expr.X_add_number >= 0x8000 - off) | |
48401fcf | 6701 | as_bad (_("operand overflow")); |
b9129c6f | 6702 | if (! target_big_endian) |
adcf2b9d ILT |
6703 | offset_expr.X_add_number += off; |
6704 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6705 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6706 | if (! target_big_endian) |
adcf2b9d | 6707 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6708 | else |
adcf2b9d ILT |
6709 | offset_expr.X_add_number += off; |
6710 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6711 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6712 | return; |
3d3c5039 | 6713 | |
adcf2b9d ILT |
6714 | case M_USD_A: |
6715 | s = "sdl"; | |
6716 | s2 = "sdr"; | |
6717 | off = 7; | |
6718 | goto uswa; | |
3d3c5039 | 6719 | case M_USW_A: |
adcf2b9d ILT |
6720 | s = "swl"; |
6721 | s2 = "swr"; | |
6722 | off = 3; | |
6723 | uswa: | |
0dd2d296 | 6724 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6725 | if (breg != 0) |
6726 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6727 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6728 | || mips_opts.isa < 3) | |
6729 | ? "addu" : "daddu"), | |
c625fc23 | 6730 | "d,v,t", AT, AT, breg); |
b9129c6f | 6731 | if (! target_big_endian) |
adcf2b9d | 6732 | expr1.X_add_number = off; |
670a50eb | 6733 | else |
adcf2b9d ILT |
6734 | expr1.X_add_number = 0; |
6735 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6736 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6737 | if (! target_big_endian) |
adcf2b9d ILT |
6738 | expr1.X_add_number = 0; |
6739 | else | |
6740 | expr1.X_add_number = off; | |
6741 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6742 | (int) BFD_RELOC_LO16, AT); | |
6743 | break; | |
6744 | ||
6745 | case M_USH_A: | |
6746 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6747 | if (breg != 0) |
6748 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6749 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6750 | || mips_opts.isa < 3) | |
6751 | ? "addu" : "daddu"), | |
c625fc23 | 6752 | "d,v,t", AT, AT, breg); |
b9129c6f | 6753 | if (! target_big_endian) |
adcf2b9d ILT |
6754 | expr1.X_add_number = 0; |
6755 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6756 | (int) BFD_RELOC_LO16, AT); | |
6757 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
6758 | treg, 8); | |
b9129c6f | 6759 | if (! target_big_endian) |
adcf2b9d ILT |
6760 | expr1.X_add_number = 1; |
6761 | else | |
6762 | expr1.X_add_number = 0; | |
6763 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6764 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6765 | if (! target_big_endian) |
adcf2b9d ILT |
6766 | expr1.X_add_number = 0; |
6767 | else | |
6768 | expr1.X_add_number = 1; | |
6769 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6770 | (int) BFD_RELOC_LO16, AT); | |
6771 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6772 | treg, 8); | |
6773 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6774 | treg, AT); | |
670a50eb | 6775 | break; |
3d3c5039 ILT |
6776 | |
6777 | default: | |
9218cee0 ILT |
6778 | /* FIXME: Check if this is one of the itbl macros, since they |
6779 | are added dynamically. */ | |
48401fcf | 6780 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
8358c818 | 6781 | break; |
3d3c5039 | 6782 | } |
3c83da8a | 6783 | if (mips_opts.noat) |
48401fcf | 6784 | as_warn (_("Macro used $at after \".set noat\"")); |
3d3c5039 ILT |
6785 | } |
6786 | ||
cc5703cd | 6787 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 6788 | |
3d3c5039 | 6789 | static void |
cc5703cd | 6790 | mips16_macro (ip) |
3d3c5039 ILT |
6791 | struct mips_cl_insn *ip; |
6792 | { | |
cc5703cd ILT |
6793 | int mask; |
6794 | int xreg, yreg, zreg, tmp; | |
6795 | int icnt; | |
6796 | expressionS expr1; | |
6797 | int dbl; | |
6798 | const char *s, *s2, *s3; | |
3d3c5039 | 6799 | |
cc5703cd | 6800 | mask = ip->insn_mo->mask; |
3d3c5039 | 6801 | |
cc5703cd ILT |
6802 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
6803 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
6804 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 6805 | |
cc5703cd | 6806 | icnt = 0; |
8358c818 | 6807 | |
cc5703cd ILT |
6808 | expr1.X_op = O_constant; |
6809 | expr1.X_op_symbol = NULL; | |
6810 | expr1.X_add_symbol = NULL; | |
6811 | expr1.X_add_number = 1; | |
8358c818 | 6812 | |
cc5703cd | 6813 | dbl = 0; |
517078c1 | 6814 | |
cc5703cd ILT |
6815 | switch (mask) |
6816 | { | |
6817 | default: | |
6818 | internalError (); | |
6819 | ||
6820 | case M_DDIV_3: | |
6821 | dbl = 1; | |
6822 | case M_DIV_3: | |
6823 | s = "mflo"; | |
6824 | goto do_div3; | |
6825 | case M_DREM_3: | |
6826 | dbl = 1; | |
6827 | case M_REM_3: | |
6828 | s = "mfhi"; | |
6829 | do_div3: | |
fbcfacb7 | 6830 | mips_emit_delays (true); |
3c83da8a | 6831 | ++mips_opts.noreorder; |
cc5703cd ILT |
6832 | mips_any_noreorder = 1; |
6833 | macro_build ((char *) NULL, &icnt, NULL, | |
6834 | dbl ? "ddiv" : "div", | |
6835 | "0,x,y", xreg, yreg); | |
8a8121d5 | 6836 | expr1.X_add_number = 2; |
cc5703cd | 6837 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
d9c2c0c5 | 6838 | /* start-sanitize-r5900 */ |
de484a06 | 6839 | if (mips_cpu == 5900) |
d9c2c0c5 FCE |
6840 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); |
6841 | else | |
6842 | /* end-sanitize-r5900 */ | |
6843 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); | |
6844 | ||
cc5703cd ILT |
6845 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
6846 | since that causes an overflow. We should do that as well, | |
6847 | but I don't see how to do the comparisons without a temporary | |
6848 | register. */ | |
3c83da8a | 6849 | --mips_opts.noreorder; |
cc5703cd ILT |
6850 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); |
6851 | break; | |
6852 | ||
6853 | case M_DIVU_3: | |
6854 | s = "divu"; | |
6855 | s2 = "mflo"; | |
6856 | goto do_divu3; | |
6857 | case M_REMU_3: | |
6858 | s = "divu"; | |
6859 | s2 = "mfhi"; | |
6860 | goto do_divu3; | |
6861 | case M_DDIVU_3: | |
6862 | s = "ddivu"; | |
6863 | s2 = "mflo"; | |
6864 | goto do_divu3; | |
6865 | case M_DREMU_3: | |
6866 | s = "ddivu"; | |
6867 | s2 = "mfhi"; | |
6868 | do_divu3: | |
fbcfacb7 | 6869 | mips_emit_delays (true); |
3c83da8a | 6870 | ++mips_opts.noreorder; |
cc5703cd ILT |
6871 | mips_any_noreorder = 1; |
6872 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
8a8121d5 | 6873 | expr1.X_add_number = 2; |
cc5703cd | 6874 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
d9c2c0c5 | 6875 | /* start-sanitize-r5900 */ |
de484a06 | 6876 | if (mips_cpu == 5900) |
d9c2c0c5 FCE |
6877 | macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7); |
6878 | else | |
6879 | /* end-sanitize-r5900 */ | |
6880 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); | |
3c83da8a | 6881 | --mips_opts.noreorder; |
cc5703cd ILT |
6882 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); |
6883 | break; | |
6884 | ||
08438bef ILT |
6885 | case M_DMUL: |
6886 | dbl = 1; | |
6887 | case M_MUL: | |
6888 | macro_build ((char *) NULL, &icnt, NULL, | |
6889 | dbl ? "dmultu" : "multu", | |
6890 | "x,y", xreg, yreg); | |
6891 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "x", zreg); | |
6892 | return; | |
6893 | ||
cc5703cd ILT |
6894 | case M_DSUBU_I: |
6895 | dbl = 1; | |
6896 | goto do_subu; | |
6897 | case M_SUBU_I: | |
6898 | do_subu: | |
5c6f5923 | 6899 | if (imm_expr.X_op != O_constant) |
48401fcf | 6900 | as_bad (_("Unsupported large constant")); |
cc5703cd ILT |
6901 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6902 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6903 | dbl ? "daddiu" : "addiu", | |
6904 | "y,x,4", yreg, xreg); | |
6905 | break; | |
6906 | ||
6907 | case M_SUBU_I_2: | |
5c6f5923 | 6908 | if (imm_expr.X_op != O_constant) |
48401fcf | 6909 | as_bad (_("Unsupported large constant")); |
cc5703cd ILT |
6910 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6911 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
6912 | "x,k", xreg); | |
6913 | break; | |
6914 | ||
6915 | case M_DSUBU_I_2: | |
5c6f5923 | 6916 | if (imm_expr.X_op != O_constant) |
48401fcf | 6917 | as_bad (_("Unsupported large constant")); |
cc5703cd ILT |
6918 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6919 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
6920 | "y,j", yreg); | |
6921 | break; | |
6922 | ||
6923 | case M_BEQ: | |
6924 | s = "cmp"; | |
6925 | s2 = "bteqz"; | |
6926 | goto do_branch; | |
6927 | case M_BNE: | |
6928 | s = "cmp"; | |
6929 | s2 = "btnez"; | |
6930 | goto do_branch; | |
6931 | case M_BLT: | |
6932 | s = "slt"; | |
6933 | s2 = "btnez"; | |
6934 | goto do_branch; | |
6935 | case M_BLTU: | |
6936 | s = "sltu"; | |
6937 | s2 = "btnez"; | |
6938 | goto do_branch; | |
6939 | case M_BLE: | |
6940 | s = "slt"; | |
6941 | s2 = "bteqz"; | |
6942 | goto do_reverse_branch; | |
6943 | case M_BLEU: | |
6944 | s = "sltu"; | |
6945 | s2 = "bteqz"; | |
6946 | goto do_reverse_branch; | |
6947 | case M_BGE: | |
6948 | s = "slt"; | |
6949 | s2 = "bteqz"; | |
6950 | goto do_branch; | |
6951 | case M_BGEU: | |
6952 | s = "sltu"; | |
6953 | s2 = "bteqz"; | |
6954 | goto do_branch; | |
6955 | case M_BGT: | |
6956 | s = "slt"; | |
6957 | s2 = "btnez"; | |
6958 | goto do_reverse_branch; | |
6959 | case M_BGTU: | |
6960 | s = "sltu"; | |
6961 | s2 = "btnez"; | |
6962 | ||
6963 | do_reverse_branch: | |
6964 | tmp = xreg; | |
6965 | xreg = yreg; | |
6966 | yreg = tmp; | |
6967 | ||
6968 | do_branch: | |
6969 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6970 | xreg, yreg); | |
6971 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6972 | break; | |
6973 | ||
6974 | case M_BEQ_I: | |
6975 | s = "cmpi"; | |
6976 | s2 = "bteqz"; | |
6977 | s3 = "x,U"; | |
6978 | goto do_branch_i; | |
6979 | case M_BNE_I: | |
6980 | s = "cmpi"; | |
6981 | s2 = "btnez"; | |
6982 | s3 = "x,U"; | |
6983 | goto do_branch_i; | |
6984 | case M_BLT_I: | |
6985 | s = "slti"; | |
6986 | s2 = "btnez"; | |
6987 | s3 = "x,8"; | |
6988 | goto do_branch_i; | |
6989 | case M_BLTU_I: | |
6990 | s = "sltiu"; | |
6991 | s2 = "btnez"; | |
6992 | s3 = "x,8"; | |
6993 | goto do_branch_i; | |
6994 | case M_BLE_I: | |
6995 | s = "slti"; | |
6996 | s2 = "btnez"; | |
6997 | s3 = "x,8"; | |
6998 | goto do_addone_branch_i; | |
6999 | case M_BLEU_I: | |
7000 | s = "sltiu"; | |
7001 | s2 = "btnez"; | |
7002 | s3 = "x,8"; | |
7003 | goto do_addone_branch_i; | |
7004 | case M_BGE_I: | |
7005 | s = "slti"; | |
7006 | s2 = "bteqz"; | |
7007 | s3 = "x,8"; | |
7008 | goto do_branch_i; | |
7009 | case M_BGEU_I: | |
7010 | s = "sltiu"; | |
7011 | s2 = "bteqz"; | |
7012 | s3 = "x,8"; | |
7013 | goto do_branch_i; | |
7014 | case M_BGT_I: | |
7015 | s = "slti"; | |
7016 | s2 = "bteqz"; | |
7017 | s3 = "x,8"; | |
7018 | goto do_addone_branch_i; | |
7019 | case M_BGTU_I: | |
7020 | s = "sltiu"; | |
7021 | s2 = "bteqz"; | |
7022 | s3 = "x,8"; | |
7023 | ||
7024 | do_addone_branch_i: | |
5c6f5923 | 7025 | if (imm_expr.X_op != O_constant) |
48401fcf | 7026 | as_bad (_("Unsupported large constant")); |
cc5703cd ILT |
7027 | ++imm_expr.X_add_number; |
7028 | ||
7029 | do_branch_i: | |
7030 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
7031 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
7032 | break; | |
18e0764d ILT |
7033 | |
7034 | case M_ABS: | |
7035 | expr1.X_add_number = 0; | |
7036 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
7037 | if (xreg != yreg) | |
7038 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
7039 | "move", "y,X", xreg, yreg); | |
7040 | expr1.X_add_number = 2; | |
7041 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
7042 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
7043 | "neg", "x,w", xreg, xreg); | |
cc5703cd ILT |
7044 | } |
7045 | } | |
7046 | ||
aa2e0460 KR |
7047 | /* For consistency checking, verify that all bits are specified either |
7048 | by the match/mask part of the instruction definition, or by the | |
7049 | operand list. */ | |
7050 | static int | |
7051 | validate_mips_insn (opc) | |
7052 | const struct mips_opcode *opc; | |
7053 | { | |
7054 | const char *p = opc->args; | |
7055 | char c; | |
7056 | unsigned long used_bits = opc->mask; | |
7057 | ||
7058 | if ((used_bits & opc->match) != opc->match) | |
7059 | { | |
48401fcf | 7060 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), |
aa2e0460 KR |
7061 | opc->name, opc->args); |
7062 | return 0; | |
7063 | } | |
7064 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7065 | while (*p) | |
7066 | switch (c = *p++) | |
7067 | { | |
7068 | case ',': break; | |
7069 | case '(': break; | |
7070 | case ')': break; | |
7071 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7072 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7073 | case 'A': break; | |
7074 | case 'B': USE_BITS (OP_MASK_SYSCALL, OP_SH_SYSCALL); break; | |
7075 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; | |
7076 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7077 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7078 | case 'F': break; | |
7079 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7080 | case 'I': break; | |
7081 | case 'L': break; | |
7082 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7083 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
7084 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; | |
7085 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7086 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7087 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7088 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7089 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; | |
7090 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7091 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7092 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7093 | case 'f': break; | |
7094 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7095 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7096 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7097 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7098 | case 'l': break; | |
7099 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7100 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
40f0c904 | 7101 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; |
aa2e0460 KR |
7102 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; |
7103 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7104 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7105 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7106 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7107 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7108 | case 'x': break; | |
7109 | case 'z': break; | |
aa2e0460 | 7110 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; |
3c69baf9 GRK |
7111 | /* start-sanitize-r5900 */ |
7112 | case '0': USE_BITS (OP_MASK_VADDI, OP_SH_VADDI); break; | |
7113 | case '1': USE_BITS (OP_MASK_VUTREG, OP_SH_VUTREG); break; | |
7114 | case '2': USE_BITS (OP_MASK_VUSREG, OP_SH_VUSREG); break; | |
7115 | case '3': USE_BITS (OP_MASK_VUDREG, OP_SH_VUDREG); break; | |
7116 | case '4': USE_BITS (OP_MASK_VUTREG, OP_SH_VUTREG); break; | |
7117 | case '5': USE_BITS (OP_MASK_VUSREG, OP_SH_VUSREG); break; | |
7118 | case '6': USE_BITS (OP_MASK_VUDREG, OP_SH_VUDREG); break; | |
7119 | case '7': | |
7120 | USE_BITS (OP_MASK_VUTREG, OP_SH_VUTREG); | |
7121 | USE_BITS (OP_MASK_VUFTF, OP_SH_VUFTF); | |
7122 | break; | |
7123 | case '8': | |
7124 | USE_BITS (OP_MASK_VUSREG, OP_SH_VUSREG); | |
7125 | USE_BITS (OP_MASK_VUFSF, OP_SH_VUFSF); | |
7126 | break; | |
7127 | case '9': break; | |
7128 | case 'K': break; | |
7129 | case 'X': break; | |
7130 | case 'U': break; | |
7131 | case 'Q': break; | |
7132 | case 'J': break; | |
7133 | case 'O': USE_BITS (OP_MASK_VUCALLMS, OP_SH_VUCALLMS);break; | |
7134 | case '&': USE_BITS (OP_MASK_VUDEST, OP_SH_VUDEST); break; | |
be294de6 | 7135 | case ';': break; |
3c69baf9 GRK |
7136 | case '#': |
7137 | p++; | |
7138 | break; | |
7139 | case '-': break; | |
7140 | case '+': break; | |
7141 | /* end-sanitize-r5900 */ | |
6b34ac5a | 7142 | /* start-sanitize-cygnus */ |
aa2e0460 KR |
7143 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7144 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7145 | case '[': break; | |
7146 | case ']': break; | |
6b34ac5a | 7147 | /* end-sanitize-cygnus */ |
aa2e0460 | 7148 | default: |
48401fcf | 7149 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), |
aa2e0460 KR |
7150 | c, opc->name, opc->args); |
7151 | return 0; | |
7152 | } | |
7153 | #undef USE_BITS | |
aa2e0460 KR |
7154 | if (used_bits != 0xffffffff) |
7155 | { | |
48401fcf | 7156 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), |
aa2e0460 KR |
7157 | ~used_bits & 0xffffffff, opc->name, opc->args); |
7158 | return 0; | |
7159 | } | |
7160 | return 1; | |
7161 | } | |
7162 | ||
cc5703cd ILT |
7163 | /* This routine assembles an instruction into its binary format. As a |
7164 | side effect, it sets one of the global variables imm_reloc or | |
7165 | offset_reloc to the type of relocation to do if one of the operands | |
7166 | is an address expression. */ | |
7167 | ||
7168 | static void | |
7169 | mips_ip (str, ip) | |
7170 | char *str; | |
7171 | struct mips_cl_insn *ip; | |
7172 | { | |
7173 | char *s; | |
7174 | const char *args; | |
7175 | char c; | |
7176 | struct mips_opcode *insn; | |
7177 | char *argsStart; | |
7178 | unsigned int regno; | |
7179 | unsigned int lastregno = 0; | |
7180 | char *s_reset; | |
059a6388 | 7181 | char save_c = 0; |
48401fcf | 7182 | int full_opcode_match = 1; |
cc5703cd ILT |
7183 | |
7184 | insn_error = NULL; | |
7185 | ||
059a6388 JL |
7186 | /* If the instruction contains a '.', we first try to match an instruction |
7187 | including the '.'. Then we try again without the '.'. */ | |
7188 | insn = NULL; | |
e2e5acfa | 7189 | for (s = str; *s != '\0' && !isspace(*s); ++s) |
cc5703cd | 7190 | continue; |
059a6388 JL |
7191 | |
7192 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7193 | the call to hash_find. Save the character we replaced just in case we | |
7194 | have to re-parse the instruction. */ | |
1857d1e6 | 7195 | if (isspace (*s)) |
059a6388 JL |
7196 | { |
7197 | save_c = *s; | |
7198 | *s++ = '\0'; | |
7199 | } | |
7200 | ||
7201 | insn = (struct mips_opcode *) hash_find (op_hash, str); | |
1857d1e6 | 7202 | |
059a6388 JL |
7203 | /* If we didn't find the instruction in the opcode table, try again, but |
7204 | this time with just the instruction up to, but not including the | |
7205 | first '.'. */ | |
7206 | if (insn == NULL) | |
cc5703cd | 7207 | { |
059a6388 JL |
7208 | /* Restore the character we overwrite above (if any). */ |
7209 | if (save_c) | |
7210 | *(--s) = save_c; | |
7211 | ||
7212 | /* Scan up to the first '.' or whitespace. */ | |
7213 | for (s = str; *s != '\0' && *s != '.' && !isspace (*s); ++s) | |
7214 | continue; | |
7215 | ||
7216 | /* If we did not find a '.', then we can quit now. */ | |
7217 | if (*s != '.') | |
7218 | { | |
7219 | insn_error = "unrecognized opcode"; | |
7220 | return; | |
7221 | } | |
7222 | ||
7223 | /* Lookup the instruction in the hash table. */ | |
7224 | *s++ = '\0'; | |
7225 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7226 | { | |
7227 | insn_error = "unrecognized opcode"; | |
7228 | return; | |
7229 | } | |
48401fcf TT |
7230 | |
7231 | full_opcode_match = 0; | |
cc5703cd | 7232 | } |
059a6388 | 7233 | |
cc5703cd ILT |
7234 | argsStart = s; |
7235 | for (;;) | |
7236 | { | |
7237 | int insn_isa; | |
a652f74c | 7238 | boolean ok; |
cc5703cd ILT |
7239 | |
7240 | assert (strcmp (insn->name, str) == 0); | |
7241 | ||
1c6f3441 | 7242 | if ((insn->membership & INSN_ISA) == INSN_ISA1) |
931a1858 | 7243 | insn_isa = 1; |
5c6f5923 | 7244 | else if ((insn->membership & INSN_ISA) == INSN_ISA2) |
cc5703cd | 7245 | insn_isa = 2; |
5c6f5923 | 7246 | else if ((insn->membership & INSN_ISA) == INSN_ISA3) |
cc5703cd | 7247 | insn_isa = 3; |
5c6f5923 | 7248 | else if ((insn->membership & INSN_ISA) == INSN_ISA4) |
cc5703cd ILT |
7249 | insn_isa = 4; |
7250 | else | |
931a1858 | 7251 | insn_isa = 15; |
cc5703cd | 7252 | |
a652f74c ILT |
7253 | if (insn_isa <= mips_opts.isa) |
7254 | ok = true; | |
7255 | else if (insn->pinfo == INSN_MACRO) | |
7256 | ok = false; | |
de484a06 JB |
7257 | else if ((mips_cpu == 4650 && (insn->membership & INSN_4650) != 0) |
7258 | || (mips_cpu == 4010 && (insn->membership & INSN_4010) != 0) | |
7259 | || ((mips_cpu == 4100 | |
7260 | /* start-sanitize-vr4xxx */ | |
7261 | || mips_cpu == 4111 | |
7262 | /* end-sanitize-vr4xxx */ | |
7263 | ) | |
7264 | && (insn->membership & INSN_4100) != 0) | |
f14397f0 | 7265 | /* start-sanitize-vr4xxx */ |
de484a06 | 7266 | || (mips_cpu == 4121 && (insn->membership & INSN_4121) != 0) |
f14397f0 | 7267 | /* end-sanitize-vr4xxx */ |
2d035a50 | 7268 | /* start-sanitize-vr4320 */ |
de484a06 | 7269 | || (mips_cpu == 4320 && (insn->membership & INSN_4320) != 0) |
2d035a50 | 7270 | /* end-sanitize-vr4320 */ |
42444087 | 7271 | /* start-sanitize-tx49 */ |
de484a06 | 7272 | || (mips_cpu == 4900 && (insn->membership & INSN_4900) != 0) |
42444087 | 7273 | /* end-sanitize-tx49 */ |
a652f74c | 7274 | /* start-sanitize-r5900 */ |
de484a06 | 7275 | || (mips_cpu == 5900 && (insn->membership & INSN_5900) != 0) |
a652f74c | 7276 | /* end-sanitize-r5900 */ |
6b34ac5a | 7277 | /* start-sanitize-cygnus */ |
de484a06 | 7278 | || (mips_cpu == 5400 && (insn->membership & INSN_5400) != 0) |
6b34ac5a | 7279 | /* end-sanitize-cygnus */ |
de484a06 | 7280 | || (mips_cpu == 3900 && (insn->membership & INSN_3900) != 0)) |
1c6f3441 | 7281 | ok = true; |
a652f74c ILT |
7282 | else |
7283 | ok = false; | |
7284 | ||
b2cf4548 DE |
7285 | if (insn->pinfo != INSN_MACRO) |
7286 | { | |
de484a06 | 7287 | if (mips_cpu == 4650 && (insn->pinfo & FP_D) != 0) |
b2cf4548 DE |
7288 | ok = false; |
7289 | /* start-sanitize-r5900 */ | |
de484a06 | 7290 | if (mips_cpu == 5900 && (insn->pinfo & FP_D) != 0) |
b2cf4548 DE |
7291 | ok = false; |
7292 | /* end-sanitize-r5900 */ | |
7293 | } | |
1c6f3441 | 7294 | |
a652f74c | 7295 | if (! ok) |
cc5703cd ILT |
7296 | { |
7297 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7298 | && strcmp (insn->name, insn[1].name) == 0) | |
7299 | { | |
7300 | ++insn; | |
7301 | continue; | |
7302 | } | |
6fd819cf GRK |
7303 | if (insn_isa == 15 |
7304 | || insn_isa <= mips_opts.isa) | |
48401fcf | 7305 | insn_error = _("opcode not supported on this processor"); |
cc5703cd ILT |
7306 | else |
7307 | { | |
7308 | static char buf[100]; | |
7309 | ||
48401fcf | 7310 | sprintf (buf, _("opcode requires -mips%d or greater"), insn_isa); |
cc5703cd ILT |
7311 | insn_error = buf; |
7312 | } | |
7313 | return; | |
7314 | } | |
8358c818 | 7315 | |
670a50eb ILT |
7316 | ip->insn_mo = insn; |
7317 | ip->insn_opcode = insn->match; | |
7318 | for (args = insn->args;; ++args) | |
7319 | { | |
7320 | if (*s == ' ') | |
7321 | ++s; | |
7322 | switch (*args) | |
7323 | { | |
7324 | case '\0': /* end of args */ | |
7325 | if (*s == '\0') | |
7326 | return; | |
7327 | break; | |
3d3c5039 ILT |
7328 | |
7329 | case ',': | |
670a50eb ILT |
7330 | if (*s++ == *args) |
7331 | continue; | |
7332 | s--; | |
7333 | switch (*++args) | |
7334 | { | |
3d3c5039 ILT |
7335 | case 'r': |
7336 | case 'v': | |
670a50eb ILT |
7337 | ip->insn_opcode |= lastregno << 21; |
7338 | continue; | |
3d3c5039 ILT |
7339 | |
7340 | case 'w': | |
7341 | case 'W': | |
670a50eb ILT |
7342 | ip->insn_opcode |= lastregno << 16; |
7343 | continue; | |
3d3c5039 ILT |
7344 | |
7345 | case 'V': | |
670a50eb ILT |
7346 | ip->insn_opcode |= lastregno << 11; |
7347 | continue; | |
3d3c5039 | 7348 | } |
670a50eb | 7349 | break; |
3d3c5039 ILT |
7350 | |
7351 | case '(': | |
059a6388 | 7352 | /* Handle optional base register. |
670a50eb ILT |
7353 | Either the base register is omitted or |
7354 | we must have a left paren. */ | |
059a6388 JL |
7355 | /* This is dependent on the next operand specifier |
7356 | is a base register specification. */ | |
7357 | assert (args[1] == 'b' || args[1] == '5' | |
7358 | || args[1] == '-' || args[1] == '4'); | |
670a50eb ILT |
7359 | if (*s == '\0') |
7360 | return; | |
3d3c5039 | 7361 | |
670a50eb | 7362 | case ')': /* these must match exactly */ |
6b34ac5a | 7363 | /* start-sanitize-cygnus */ |
aa2e0460 KR |
7364 | case '[': |
7365 | case ']': | |
6b34ac5a | 7366 | /* end-sanitize-cygnus */ |
059a6388 JL |
7367 | /* start-sanitize-r5900 */ |
7368 | case '-': | |
7369 | case '+': | |
7370 | /* end-sanitize-r5900 */ | |
670a50eb | 7371 | if (*s++ == *args) |
3d3c5039 | 7372 | continue; |
670a50eb ILT |
7373 | break; |
7374 | ||
7375 | case '<': /* must be at least one digit */ | |
7376 | /* | |
7377 | * According to the manual, if the shift amount is greater | |
7378 | * than 31 or less than 0 the the shift amount should be | |
7379 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 7380 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
7381 | */ |
7382 | my_getExpression (&imm_expr, s); | |
7383 | check_absolute_expr (ip, &imm_expr); | |
7384 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7385 | { | |
48401fcf | 7386 | as_warn (_("Improper shift amount (%ld)"), |
58d4951d | 7387 | (long) imm_expr.X_add_number); |
9226253a | 7388 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
7389 | } |
7390 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 7391 | imm_expr.X_op = O_absent; |
670a50eb ILT |
7392 | s = expr_end; |
7393 | continue; | |
7394 | ||
56c96faa ILT |
7395 | case '>': /* shift amount minus 32 */ |
7396 | my_getExpression (&imm_expr, s); | |
7397 | check_absolute_expr (ip, &imm_expr); | |
7398 | if ((unsigned long) imm_expr.X_add_number < 32 | |
7399 | || (unsigned long) imm_expr.X_add_number > 63) | |
7400 | break; | |
7401 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
7402 | imm_expr.X_op = O_absent; | |
7403 | s = expr_end; | |
7404 | continue; | |
7405 | ||
059a6388 JL |
7406 | /* start-sanitize-r5900 */ |
7407 | case '0': /* 5 bit signed immediate at 6 */ | |
7408 | my_getExpression (&imm_expr, s); | |
7409 | check_absolute_expr (ip, &imm_expr); | |
7410 | if ((c == '\0' && imm_expr.X_op != O_constant) | |
7411 | || ((imm_expr.X_add_number < -16 | |
7412 | || imm_expr.X_add_number >= 16) | |
7413 | && imm_expr.X_op == O_constant)) | |
7414 | { | |
7415 | if (imm_expr.X_op != O_constant | |
7416 | && imm_expr.X_op != O_big) | |
7417 | insn_error = "absolute expression required"; | |
7418 | else | |
48401fcf | 7419 | as_bad (_("5 bit expression not in range -16..15")); |
059a6388 JL |
7420 | } |
7421 | ip->insn_opcode |= (imm_expr.X_add_number) << 6; | |
7422 | imm_expr.X_op = O_absent; | |
7423 | s = expr_end; | |
7424 | continue; | |
7425 | ||
65a17223 | 7426 | case '9': /* vi27 for vcallmsr */ |
7e656649 RH |
7427 | if (strncmp (s, "$vi27", 5) == 0) |
7428 | s += 5; | |
7429 | else if (strncmp (s, "vi27", 4) == 0) | |
059a6388 JL |
7430 | s += 4; |
7431 | else | |
48401fcf | 7432 | as_bad (_("expected vi27")); |
059a6388 JL |
7433 | continue; |
7434 | ||
981ce186 JL |
7435 | case '#': /* escape character */ |
7436 | /* '#' specifies that we've got an optional suffix to this | |
059a6388 JL |
7437 | operand that must match exactly (if it exists). */ |
7438 | if (*s != '\0' && *s != ',' | |
7439 | && *s != ' ' && *s != '\t' && *s != '\n') | |
7440 | { | |
7441 | if (*s == *(args + 1)) | |
7442 | { | |
7443 | s++; | |
7444 | args++; | |
7445 | continue; | |
7446 | } | |
7447 | break; | |
7448 | } | |
7449 | args++; | |
7450 | continue; | |
7451 | ||
7452 | case 'K': /* DEST operand completer (optional), must | |
7453 | match previous dest if specified. */ | |
7454 | case '&': /* DEST instruction completer */ | |
be294de6 | 7455 | case ';': /* DEST instruction completer, must be xyz */ |
059a6388 JL |
7456 | { |
7457 | int w,x,y,z; | |
7458 | static int last_h; | |
7459 | ||
7460 | w = x = y = z = 0; | |
7461 | ||
7462 | /* Parse the completer. */ | |
7463 | s_reset = s; | |
48401fcf TT |
7464 | while ((!full_opcode_match || *args == 'K') |
7465 | && *s != '\0' && *s != ' ' && *s != ',') | |
059a6388 JL |
7466 | { |
7467 | if (*s == 'w') | |
7468 | w++; | |
7469 | else if (*s == 'x') | |
7470 | x++; | |
7471 | else if (*s == 'y') | |
7472 | y++; | |
7473 | else if (*s == 'z') | |
7474 | z++; | |
7475 | else | |
7476 | { | |
7477 | insn_error = "Invalid dest specification"; | |
48401fcf | 7478 | break; |
059a6388 JL |
7479 | } |
7480 | s++; | |
7481 | } | |
7482 | ||
48401fcf TT |
7483 | if (insn_error) |
7484 | continue; | |
7485 | ||
059a6388 JL |
7486 | /* Each completer can only appear once. */ |
7487 | if (w > 1 || x > 1 || y > 1 || z > 1) | |
7488 | { | |
7489 | insn_error = "Invalid dest specification"; | |
7490 | continue; | |
7491 | } | |
7492 | ||
7493 | /* If this is the opcode completer, then we must insert | |
7494 | the appropriate value into the insn. */ | |
7495 | if (*args == '&') | |
7496 | { | |
48401fcf TT |
7497 | /* Not strictly in the specs, but requested by users. */ |
7498 | if (w == 0 && x == 0 && y == 0 && z == 0) | |
7499 | w = x = y = z = 1; | |
7500 | ||
059a6388 JL |
7501 | ip->insn_opcode |= ((w << 21) | (x << 24) |
7502 | | (y << 23) | (z << 22)); | |
7503 | last_h = (w << 3) | (x << 0) | (y << 1) | (z << 2); | |
7504 | } | |
be294de6 JL |
7505 | else if (*args == ';') |
7506 | { | |
7507 | /* This implicitly has the .xyz completer. */ | |
7508 | if (w == 0 && x == 0 && y == 0 && z == 0) | |
7509 | x = y = z = 1; | |
7510 | ||
7511 | if (w != 0 || x != 1 || y != 1 || z != 1) | |
7512 | { | |
7513 | insn_error = "Invalid dest specification"; | |
7514 | continue; | |
7515 | } | |
7516 | ||
7517 | last_h = (w << 3) | (x << 0) | (y << 1) | (z << 2); | |
7518 | } | |
059a6388 JL |
7519 | else |
7520 | { | |
7521 | int temp; | |
7522 | ||
7523 | /* This is the operand completer, make sure it matches | |
7524 | the previous opcode completer. */ | |
7525 | temp = (w << 3) | (x << 0) | (y << 1) | (z << 2); | |
7526 | if (temp && temp != last_h) | |
7527 | { | |
7528 | insn_error = "DEST field in operand does not match DEST field in instruction"; | |
7529 | continue; | |
7530 | } | |
7531 | ||
7532 | } | |
7533 | ||
7534 | continue; | |
7535 | } | |
7536 | ||
7537 | case 'J': /* vu0 I register */ | |
7538 | if (s[0] == 'I') | |
7539 | s += 1; | |
7540 | else | |
7541 | insn_error = "operand `I' expected"; | |
7542 | continue; | |
7543 | ||
7544 | case 'Q': /* vu0 Q register */ | |
7545 | if (s[0] == 'Q') | |
7546 | s += 1; | |
7547 | else | |
7548 | insn_error = "operand `Q' expected"; | |
7549 | continue; | |
7550 | ||
7551 | case 'X': /* vu0 R register */ | |
7552 | if (s[0] == 'R') | |
7553 | s += 1; | |
7554 | else | |
7555 | insn_error = "operand `R' expected"; | |
7556 | continue; | |
7557 | ||
7558 | case 'U': /* vu0 ACC register */ | |
7559 | if (s[0] == 'A' && s[1] == 'C' && s[2] == 'C') | |
7560 | s += 3; | |
7561 | else | |
7562 | insn_error = "operand `ACC' expected"; | |
7563 | continue; | |
0bc0e337 JL |
7564 | |
7565 | case 'O': | |
7566 | my_getSmallExpression (&imm_expr, s); | |
7567 | imm_reloc = BFD_RELOC_MIPS15_S3; | |
7568 | s = expr_end; | |
7569 | continue; | |
059a6388 JL |
7570 | /* end-sanitize-r5900 */ |
7571 | ||
9226253a | 7572 | case 'k': /* cache code */ |
d8a1c247 | 7573 | case 'h': /* prefx code */ |
9226253a ILT |
7574 | my_getExpression (&imm_expr, s); |
7575 | check_absolute_expr (ip, &imm_expr); | |
7576 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7577 | { | |
48401fcf | 7578 | as_warn (_("Invalid value for `%s' (%lu)"), |
d8a1c247 | 7579 | ip->insn_mo->name, |
9226253a ILT |
7580 | (unsigned long) imm_expr.X_add_number); |
7581 | imm_expr.X_add_number &= 0x1f; | |
7582 | } | |
d8a1c247 KR |
7583 | if (*args == 'k') |
7584 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
7585 | else | |
7586 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
7587 | imm_expr.X_op = O_absent; |
7588 | s = expr_end; | |
7589 | continue; | |
7590 | ||
670a50eb ILT |
7591 | case 'c': /* break code */ |
7592 | my_getExpression (&imm_expr, s); | |
7593 | check_absolute_expr (ip, &imm_expr); | |
7594 | if ((unsigned) imm_expr.X_add_number > 1023) | |
40f0c904 FCE |
7595 | { |
7596 | as_warn (_("Illegal break code (%ld)"), | |
7597 | (long) imm_expr.X_add_number); | |
7598 | imm_expr.X_add_number &= 0x3ff; | |
7599 | } | |
670a50eb | 7600 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 7601 | imm_expr.X_op = O_absent; |
670a50eb ILT |
7602 | s = expr_end; |
7603 | continue; | |
7604 | ||
40f0c904 FCE |
7605 | case 'q': /* lower break code */ |
7606 | my_getExpression (&imm_expr, s); | |
7607 | check_absolute_expr (ip, &imm_expr); | |
7608 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7609 | { | |
7610 | as_warn (_("Illegal lower break code (%ld)"), | |
7611 | (long) imm_expr.X_add_number); | |
7612 | imm_expr.X_add_number &= 0x3ff; | |
7613 | } | |
7614 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
7615 | imm_expr.X_op = O_absent; | |
7616 | s = expr_end; | |
7617 | continue; | |
7618 | ||
918692a5 ILT |
7619 | case 'B': /* syscall code */ |
7620 | my_getExpression (&imm_expr, s); | |
7621 | check_absolute_expr (ip, &imm_expr); | |
7622 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
48401fcf | 7623 | as_warn (_("Illegal syscall code (%ld)"), |
58d4951d | 7624 | (long) imm_expr.X_add_number); |
918692a5 | 7625 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 7626 | imm_expr.X_op = O_absent; |
918692a5 ILT |
7627 | s = expr_end; |
7628 | continue; | |
7629 | ||
0aa07269 ILT |
7630 | case 'C': /* Coprocessor code */ |
7631 | my_getExpression (&imm_expr, s); | |
7632 | check_absolute_expr (ip, &imm_expr); | |
7633 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
7634 | { | |
48401fcf | 7635 | as_warn (_("Coproccesor code > 25 bits (%ld)"), |
58d4951d | 7636 | (long) imm_expr.X_add_number); |
0aa07269 ILT |
7637 | imm_expr.X_add_number &= ((1<<25) - 1); |
7638 | } | |
7639 | ip->insn_opcode |= imm_expr.X_add_number; | |
7640 | imm_expr.X_op = O_absent; | |
7641 | s = expr_end; | |
7642 | continue; | |
7643 | ||
65d2c7d3 JL |
7644 | case 'P': /* Performance register */ |
7645 | my_getExpression (&imm_expr, s); | |
7646 | check_absolute_expr (ip, &imm_expr); | |
7647 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) | |
7648 | { | |
48401fcf | 7649 | as_warn (_("Invalidate performance regster (%ld)"), |
65d2c7d3 JL |
7650 | (long) imm_expr.X_add_number); |
7651 | imm_expr.X_add_number &= 1; | |
7652 | } | |
7653 | ip->insn_opcode |= (imm_expr.X_add_number << 1); | |
7654 | imm_expr.X_op = O_absent; | |
7655 | s = expr_end; | |
7656 | continue; | |
7657 | ||
670a50eb ILT |
7658 | case 'b': /* base register */ |
7659 | case 'd': /* destination register */ | |
7660 | case 's': /* source register */ | |
7661 | case 't': /* target register */ | |
7662 | case 'r': /* both target and source */ | |
7663 | case 'v': /* both dest and source */ | |
7664 | case 'w': /* both dest and target */ | |
918692a5 ILT |
7665 | case 'E': /* coprocessor target register */ |
7666 | case 'G': /* coprocessor destination register */ | |
8358c818 | 7667 | case 'x': /* ignore register name */ |
ff3a5c18 | 7668 | case 'z': /* must be zero register */ |
670a50eb ILT |
7669 | s_reset = s; |
7670 | if (s[0] == '$') | |
7671 | { | |
7e656649 RH |
7672 | /* start-sanitize-r5900 */ |
7673 | /* Allow "$viNN" as coprocessor register name */ | |
de484a06 | 7674 | if (mips_cpu == 5900 |
7e656649 RH |
7675 | && *args == 'G' |
7676 | && s[1] == 'v' | |
7677 | && s[2] == 'i') | |
7678 | { | |
7679 | s += 2; | |
7680 | } | |
7681 | /* end-sanitize-r5900 */ | |
7682 | ||
670a50eb ILT |
7683 | if (isdigit (s[1])) |
7684 | { | |
7685 | ++s; | |
7686 | regno = 0; | |
7687 | do | |
7688 | { | |
7689 | regno *= 10; | |
7690 | regno += *s - '0'; | |
7691 | ++s; | |
7692 | } | |
7693 | while (isdigit (*s)); | |
0aa07269 | 7694 | if (regno > 31) |
48401fcf | 7695 | as_bad (_("Invalid register number (%d)"), regno); |
670a50eb | 7696 | } |
0dd2d296 ILT |
7697 | else if (*args == 'E' || *args == 'G') |
7698 | goto notreg; | |
7699 | else | |
670a50eb | 7700 | { |
0aa07269 ILT |
7701 | if (s[1] == 'f' && s[2] == 'p') |
7702 | { | |
7703 | s += 3; | |
9226253a | 7704 | regno = FP; |
0aa07269 ILT |
7705 | } |
7706 | else if (s[1] == 's' && s[2] == 'p') | |
7707 | { | |
7708 | s += 3; | |
9226253a | 7709 | regno = SP; |
0aa07269 ILT |
7710 | } |
7711 | else if (s[1] == 'g' && s[2] == 'p') | |
7712 | { | |
7713 | s += 3; | |
9226253a | 7714 | regno = GP; |
0aa07269 ILT |
7715 | } |
7716 | else if (s[1] == 'a' && s[2] == 't') | |
7717 | { | |
7718 | s += 3; | |
9226253a | 7719 | regno = AT; |
0aa07269 | 7720 | } |
b2b8c24e ILT |
7721 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
7722 | { | |
7723 | s += 4; | |
7724 | regno = KT0; | |
7725 | } | |
7726 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7727 | { | |
7728 | s += 4; | |
7729 | regno = KT1; | |
7730 | } | |
efec4a28 DP |
7731 | else if (itbl_have_entries) |
7732 | { | |
7733 | char *p, *n; | |
7734 | int r; | |
7735 | ||
7736 | p = s+1; /* advance past '$' */ | |
9218cee0 | 7737 | n = itbl_get_field (&p); /* n is name */ |
efec4a28 DP |
7738 | |
7739 | /* See if this is a register defined in an | |
7740 | itbl entry */ | |
9218cee0 ILT |
7741 | r = itbl_get_reg_val (n); |
7742 | if (r) | |
efec4a28 | 7743 | { |
9218cee0 ILT |
7744 | /* Get_field advances to the start of |
7745 | the next field, so we need to back | |
7746 | rack to the end of the last field. */ | |
efec4a28 | 7747 | if (p) |
9218cee0 | 7748 | s = p - 1; |
efec4a28 | 7749 | else |
9218cee0 | 7750 | s = strchr (s,'\0'); |
efec4a28 DP |
7751 | regno = r; |
7752 | } | |
7753 | else | |
7754 | goto notreg; | |
7755 | } | |
0aa07269 ILT |
7756 | else |
7757 | goto notreg; | |
670a50eb | 7758 | } |
9753202d | 7759 | if (regno == AT |
3c83da8a | 7760 | && ! mips_opts.noat |
9753202d ILT |
7761 | && *args != 'E' |
7762 | && *args != 'G') | |
48401fcf | 7763 | as_warn (_("Used $at without \".set noat\"")); |
670a50eb ILT |
7764 | c = *args; |
7765 | if (*s == ' ') | |
7766 | s++; | |
7767 | if (args[1] != *s) | |
7768 | { | |
7769 | if (c == 'r' || c == 'v' || c == 'w') | |
7770 | { | |
7771 | regno = lastregno; | |
7772 | s = s_reset; | |
7773 | args++; | |
7774 | } | |
7775 | } | |
ff3a5c18 ILT |
7776 | /* 'z' only matches $0. */ |
7777 | if (c == 'z' && regno != 0) | |
7778 | break; | |
efec4a28 DP |
7779 | |
7780 | /* Now that we have assembled one operand, we use the args string | |
7781 | * to figure out where it goes in the instruction. */ | |
670a50eb ILT |
7782 | switch (c) |
7783 | { | |
3d3c5039 ILT |
7784 | case 'r': |
7785 | case 's': | |
7786 | case 'v': | |
7787 | case 'b': | |
670a50eb ILT |
7788 | ip->insn_opcode |= regno << 21; |
7789 | break; | |
3d3c5039 | 7790 | case 'd': |
918692a5 | 7791 | case 'G': |
670a50eb ILT |
7792 | ip->insn_opcode |= regno << 11; |
7793 | break; | |
3d3c5039 ILT |
7794 | case 'w': |
7795 | case 't': | |
918692a5 | 7796 | case 'E': |
670a50eb | 7797 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
7798 | break; |
7799 | case 'x': | |
7800 | /* This case exists because on the r3000 trunc | |
7801 | expands into a macro which requires a gp | |
7802 | register. On the r6000 or r4000 it is | |
7803 | assembled into a single instruction which | |
7804 | ignores the register. Thus the insn version | |
7805 | is MIPS_ISA2 and uses 'x', and the macro | |
7806 | version is MIPS_ISA1 and uses 't'. */ | |
7807 | break; | |
ff3a5c18 ILT |
7808 | case 'z': |
7809 | /* This case is for the div instruction, which | |
7810 | acts differently if the destination argument | |
7811 | is $0. This only matches $0, and is checked | |
7812 | outside the switch. */ | |
7813 | break; | |
efec4a28 DP |
7814 | case 'D': |
7815 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
7816 | break; | |
9218cee0 ILT |
7817 | /* What about all other operands like 'i', which |
7818 | can be specified in the opcode table? */ | |
3d3c5039 | 7819 | } |
670a50eb ILT |
7820 | lastregno = regno; |
7821 | continue; | |
3d3c5039 ILT |
7822 | } |
7823 | notreg: | |
670a50eb ILT |
7824 | switch (*args++) |
7825 | { | |
3d3c5039 ILT |
7826 | case 'r': |
7827 | case 'v': | |
670a50eb ILT |
7828 | ip->insn_opcode |= lastregno << 21; |
7829 | continue; | |
3d3c5039 | 7830 | case 'w': |
670a50eb ILT |
7831 | ip->insn_opcode |= lastregno << 16; |
7832 | continue; | |
3d3c5039 | 7833 | } |
670a50eb | 7834 | break; |
3d3c5039 | 7835 | |
670a50eb ILT |
7836 | case 'D': /* floating point destination register */ |
7837 | case 'S': /* floating point source register */ | |
7838 | case 'T': /* floating point target register */ | |
d8a1c247 | 7839 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
7840 | case 'V': |
7841 | case 'W': | |
059a6388 JL |
7842 | /* start-sanitize-r5900 */ |
7843 | case '1': /* vu0 fp reg position 1 */ | |
7844 | case '2': /* vu0 fp reg position 2 */ | |
7845 | case '3': /* vu0 fp reg position 3 */ | |
7846 | case '4': /* vu0 int reg position 1 */ | |
7847 | case '5': /* vu0 int reg position 2 */ | |
7848 | case '6': /* vu0 int reg position 3 */ | |
7849 | case '7': /* vu0 fp reg with ftf modifier */ | |
7850 | case '8': /* vu0 fp reg with fsf modifier */ | |
7851 | /* end-sanitize-r5900 */ | |
670a50eb ILT |
7852 | s_reset = s; |
7853 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
7854 | { | |
7855 | s += 2; | |
7856 | regno = 0; | |
7857 | do | |
7858 | { | |
7859 | regno *= 10; | |
7860 | regno += *s - '0'; | |
7861 | ++s; | |
7862 | } | |
7863 | while (isdigit (*s)); | |
7864 | ||
7865 | if (regno > 31) | |
48401fcf | 7866 | as_bad (_("Invalid float register number (%d)"), regno); |
670a50eb | 7867 | |
9226253a | 7868 | if ((regno & 1) != 0 |
3c83da8a | 7869 | && mips_opts.isa < 3 |
538034cf ILT |
7870 | && ! (strcmp (str, "mtc1") == 0 |
7871 | || strcmp (str, "mfc1") == 0 | |
7872 | || strcmp (str, "lwc1") == 0 | |
7873 | || strcmp (str, "swc1") == 0 | |
7874 | || strcmp (str, "l.s") == 0 | |
7875 | || strcmp (str, "s.s") == 0)) | |
48401fcf | 7876 | as_warn (_("Float register should be even, was %d"), |
670a50eb ILT |
7877 | regno); |
7878 | ||
7879 | c = *args; | |
7880 | if (*s == ' ') | |
7881 | s++; | |
7882 | if (args[1] != *s) | |
7883 | { | |
7884 | if (c == 'V' || c == 'W') | |
7885 | { | |
7886 | regno = lastregno; | |
7887 | s = s_reset; | |
7888 | args++; | |
3d3c5039 ILT |
7889 | } |
7890 | } | |
670a50eb ILT |
7891 | switch (c) |
7892 | { | |
3d3c5039 | 7893 | case 'D': |
670a50eb ILT |
7894 | ip->insn_opcode |= regno << 6; |
7895 | break; | |
3d3c5039 ILT |
7896 | case 'V': |
7897 | case 'S': | |
670a50eb ILT |
7898 | ip->insn_opcode |= regno << 11; |
7899 | break; | |
3d3c5039 ILT |
7900 | case 'W': |
7901 | case 'T': | |
670a50eb | 7902 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
7903 | break; |
7904 | case 'R': | |
7905 | ip->insn_opcode |= regno << 21; | |
7906 | break; | |
3d3c5039 | 7907 | } |
670a50eb ILT |
7908 | lastregno = regno; |
7909 | continue; | |
3d3c5039 | 7910 | } |
059a6388 JL |
7911 | |
7912 | /* start-sanitize-r5900 */ | |
7e656649 RH |
7913 | /* Handle vf and vi regsiters for vu0. Handle optional |
7914 | `$' prefix. */ | |
7915 | ||
7916 | if ((s[0] == 'v' | |
7917 | && (s[1] == 'f' || s[1] == 'i') | |
7918 | && isdigit (s[2])) | |
7919 | || | |
7920 | (s[0] == '$' | |
7921 | && s[1] == 'v' | |
7922 | && (s[2] == 'f' || s[2] == 'i') | |
7923 | && isdigit (s[3]))) | |
7924 | { | |
7925 | if(s[0] == '$') | |
7926 | ++s; | |
059a6388 JL |
7927 | s += 2; |
7928 | regno = 0; | |
7929 | do | |
7930 | { | |
7931 | regno *= 10; | |
7932 | regno += *s - '0'; | |
7933 | ++s; | |
7934 | } | |
7935 | while (isdigit (*s)); | |
7936 | ||
7937 | if (regno > 31) | |
48401fcf | 7938 | as_bad (_("Invalid vu0 register number (%d)"), regno); |
059a6388 JL |
7939 | |
7940 | c = *args; | |
7941 | ||
7942 | if (c == '7' || c == '8') | |
7943 | { | |
7944 | int value; | |
7945 | ||
7946 | switch (*s) | |
7947 | { | |
7948 | case 'w': | |
7949 | value = 3; | |
7950 | s++; | |
7951 | ip->insn_opcode |= value << (c == '7' ? 23 : 21); | |
7952 | break; | |
7953 | case 'x': | |
7954 | value = 0; | |
7955 | s++; | |
7956 | ip->insn_opcode |= value << (c == '7' ? 23 : 21); | |
7957 | break; | |
7958 | case 'y': | |
7959 | value = 1; | |
7960 | s++; | |
7961 | ip->insn_opcode |= value << (c == '7' ? 23 : 21); | |
7962 | break; | |
7963 | case 'z': | |
7964 | value = 2; | |
7965 | s++; | |
7966 | ip->insn_opcode |= value << (c == '7' ? 23 : 21); | |
7967 | break; | |
7968 | default: | |
48401fcf | 7969 | as_bad (_("Invalid FSF/FTF specification")); |
059a6388 JL |
7970 | } |
7971 | } | |
7972 | ||
7973 | if (*s == ' ') | |
7974 | s++; | |
7975 | if (args[1] != *s) | |
7976 | { | |
7977 | if (c == 'V' || c == 'W') | |
7978 | { | |
7979 | regno = lastregno; | |
7980 | s = s_reset; | |
7981 | args++; | |
7982 | } | |
7983 | } | |
7984 | switch (c) | |
7985 | { | |
7986 | case '1': | |
7987 | case '4': | |
7988 | case '7': | |
7989 | ip->insn_opcode |= regno << 16; | |
7990 | break; | |
7991 | case '2': | |
7992 | case '5': | |
7993 | case '8': | |
7994 | ip->insn_opcode |= regno << 11; | |
7995 | break; | |
7996 | case '3': | |
7997 | case '6': | |
7998 | ip->insn_opcode |= regno << 6; | |
7999 | break; | |
8000 | } | |
8001 | lastregno = regno; | |
8002 | continue; | |
8003 | } | |
8004 | /* end-sanitize-r5900 */ | |
8005 | ||
670a50eb ILT |
8006 | switch (*args++) |
8007 | { | |
3d3c5039 | 8008 | case 'V': |
670a50eb ILT |
8009 | ip->insn_opcode |= lastregno << 11; |
8010 | continue; | |
3d3c5039 | 8011 | case 'W': |
670a50eb ILT |
8012 | ip->insn_opcode |= lastregno << 16; |
8013 | continue; | |
3d3c5039 | 8014 | } |
670a50eb | 8015 | break; |
3d3c5039 ILT |
8016 | |
8017 | case 'I': | |
670a50eb | 8018 | my_getExpression (&imm_expr, s); |
9753202d ILT |
8019 | if (imm_expr.X_op != O_big |
8020 | && imm_expr.X_op != O_constant) | |
48401fcf | 8021 | insn_error = _("absolute expression required"); |
670a50eb ILT |
8022 | s = expr_end; |
8023 | continue; | |
3d3c5039 ILT |
8024 | |
8025 | case 'A': | |
670a50eb ILT |
8026 | my_getExpression (&offset_expr, s); |
8027 | imm_reloc = BFD_RELOC_32; | |
8028 | s = expr_end; | |
8029 | continue; | |
3d3c5039 ILT |
8030 | |
8031 | case 'F': | |
19ed8960 ILT |
8032 | case 'L': |
8033 | case 'f': | |
8034 | case 'l': | |
8035 | { | |
8036 | int f64; | |
8037 | char *save_in; | |
8038 | char *err; | |
8039 | unsigned char temp[8]; | |
604633ae ILT |
8040 | int len; |
8041 | unsigned int length; | |
19ed8960 ILT |
8042 | segT seg; |
8043 | subsegT subseg; | |
8044 | char *p; | |
8045 | ||
8046 | /* These only appear as the last operand in an | |
8047 | instruction, and every instruction that accepts | |
8048 | them in any variant accepts them in all variants. | |
8049 | This means we don't have to worry about backing out | |
8050 | any changes if the instruction does not match. | |
8051 | ||
8052 | The difference between them is the size of the | |
8053 | floating point constant and where it goes. For 'F' | |
8054 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8055 | is 32 bits. Where the constant is placed is based | |
8056 | on how the MIPS assembler does things: | |
8057 | F -- .rdata | |
8058 | L -- .lit8 | |
8059 | f -- immediate value | |
8060 | l -- .lit4 | |
0dd2d296 | 8061 | |
55933a58 ILT |
8062 | The .lit4 and .lit8 sections are only used if |
8063 | permitted by the -G argument. | |
8064 | ||
8065 | When generating embedded PIC code, we use the | |
8066 | .lit8 section but not the .lit4 section (we can do | |
8067 | .lit4 inline easily; we need to put .lit8 | |
8068 | somewhere in the data segment, and using .lit8 | |
8069 | permits the linker to eventually combine identical | |
8070 | .lit8 entries). */ | |
19ed8960 ILT |
8071 | |
8072 | f64 = *args == 'F' || *args == 'L'; | |
8073 | ||
8074 | save_in = input_line_pointer; | |
8075 | input_line_pointer = s; | |
604633ae ILT |
8076 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
8077 | length = len; | |
19ed8960 ILT |
8078 | s = input_line_pointer; |
8079 | input_line_pointer = save_in; | |
8080 | if (err != NULL && *err != '\0') | |
8081 | { | |
48401fcf | 8082 | as_bad (_("Bad floating point constant: %s"), err); |
19ed8960 ILT |
8083 | memset (temp, '\0', sizeof temp); |
8084 | length = f64 ? 8 : 4; | |
8085 | } | |
8086 | ||
8087 | assert (length == (f64 ? 8 : 4)); | |
8088 | ||
0dd2d296 | 8089 | if (*args == 'f' |
55933a58 | 8090 | || (*args == 'l' |
1dc1e798 KR |
8091 | && (! USE_GLOBAL_POINTER_OPT |
8092 | || mips_pic == EMBEDDED_PIC | |
a5586bdc ILT |
8093 | || g_switch_value < 4 |
8094 | || (temp[0] == 0 && temp[1] == 0) | |
8095 | || (temp[2] == 0 && temp[3] == 0)))) | |
19ed8960 ILT |
8096 | { |
8097 | imm_expr.X_op = O_constant; | |
b9129c6f | 8098 | if (! target_big_endian) |
a5586bdc | 8099 | imm_expr.X_add_number = bfd_getl32 (temp); |
19ed8960 | 8100 | else |
a5586bdc ILT |
8101 | imm_expr.X_add_number = bfd_getb32 (temp); |
8102 | } | |
8103 | else if (length > 4 | |
8104 | && ((temp[0] == 0 && temp[1] == 0) | |
8105 | || (temp[2] == 0 && temp[3] == 0)) | |
8106 | && ((temp[4] == 0 && temp[5] == 0) | |
8107 | || (temp[6] == 0 && temp[7] == 0))) | |
8108 | { | |
8109 | /* The value is simple enough to load with a | |
8110 | couple of instructions. In mips1 mode, set | |
8111 | imm_expr to the high order 32 bits and | |
8112 | offset_expr to the low order 32 bits. | |
8113 | Otherwise, set imm_expr to the entire 64 bit | |
8114 | constant. */ | |
8115 | if (mips_opts.isa < 3) | |
8116 | { | |
8117 | imm_expr.X_op = O_constant; | |
8118 | offset_expr.X_op = O_constant; | |
8119 | if (! target_big_endian) | |
8120 | { | |
8121 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8122 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8123 | } | |
8124 | else | |
8125 | { | |
8126 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8127 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8128 | } | |
8129 | if (offset_expr.X_add_number == 0) | |
8130 | offset_expr.X_op = O_absent; | |
8131 | } | |
8132 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8133 | { | |
8134 | imm_expr.X_op = O_constant; | |
8135 | if (! target_big_endian) | |
8136 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8137 | else | |
8138 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8139 | } | |
8140 | else | |
8141 | { | |
8142 | imm_expr.X_op = O_big; | |
8143 | imm_expr.X_add_number = 4; | |
8144 | if (! target_big_endian) | |
8145 | { | |
8146 | generic_bignum[0] = bfd_getl16 (temp); | |
8147 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8148 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8149 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8150 | } | |
8151 | else | |
8152 | { | |
8153 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8154 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8155 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8156 | generic_bignum[3] = bfd_getb16 (temp); | |
8157 | } | |
8158 | } | |
19ed8960 ILT |
8159 | } |
8160 | else | |
8161 | { | |
0dd2d296 ILT |
8162 | const char *newname; |
8163 | segT new_seg; | |
8164 | ||
19ed8960 ILT |
8165 | /* Switch to the right section. */ |
8166 | seg = now_seg; | |
8167 | subseg = now_subseg; | |
8168 | switch (*args) | |
8169 | { | |
0dd2d296 | 8170 | default: /* unused default case avoids warnings. */ |
19ed8960 | 8171 | case 'L': |
1113140a | 8172 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 8173 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 8174 | newname = ".lit8"; |
0dd2d296 ILT |
8175 | break; |
8176 | case 'F': | |
d2c71068 | 8177 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
8178 | break; |
8179 | case 'l': | |
1dc1e798 KR |
8180 | assert (!USE_GLOBAL_POINTER_OPT |
8181 | || g_switch_value >= 4); | |
0dd2d296 | 8182 | newname = ".lit4"; |
19ed8960 ILT |
8183 | break; |
8184 | } | |
0dd2d296 | 8185 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
8186 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
8187 | bfd_set_section_flags (stdoutput, new_seg, | |
8188 | (SEC_ALLOC | |
8189 | | SEC_LOAD | |
8190 | | SEC_READONLY | |
8191 | | SEC_DATA)); | |
e2e5acfa JW |
8192 | frag_align (*args == 'l' ? 2 : 3, 0, 0); |
8193 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8194 | && strcmp (TARGET_OS, "elf") != 0) | |
1dc1e798 KR |
8195 | record_alignment (new_seg, 4); |
8196 | else | |
8197 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 | 8198 | if (seg == now_seg) |
48401fcf | 8199 | as_bad (_("Can't use floating point insn in this section")); |
19ed8960 ILT |
8200 | |
8201 | /* Set the argument to the current address in the | |
6e8dda9c | 8202 | section. */ |
19ed8960 ILT |
8203 | offset_expr.X_op = O_symbol; |
8204 | offset_expr.X_add_symbol = | |
8205 | symbol_new ("L0\001", now_seg, | |
8206 | (valueT) frag_now_fix (), frag_now); | |
8207 | offset_expr.X_add_number = 0; | |
8208 | ||
8209 | /* Put the floating point number into the section. */ | |
604633ae | 8210 | p = frag_more ((int) length); |
19ed8960 ILT |
8211 | memcpy (p, temp, length); |
8212 | ||
8213 | /* Switch back to the original section. */ | |
8214 | subseg_set (seg, subseg); | |
8215 | } | |
8216 | } | |
670a50eb ILT |
8217 | continue; |
8218 | ||
8219 | case 'i': /* 16 bit unsigned immediate */ | |
8220 | case 'j': /* 16 bit signed immediate */ | |
8221 | imm_reloc = BFD_RELOC_LO16; | |
8222 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 8223 | if (c != '\0') |
670a50eb ILT |
8224 | { |
8225 | if (c != 'l') | |
8226 | { | |
5ac34ac3 | 8227 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
8228 | imm_expr.X_add_number = |
8229 | (imm_expr.X_add_number >> 16) & 0xffff; | |
8230 | else if (c == 'h') | |
867a58b3 ILT |
8231 | { |
8232 | imm_reloc = BFD_RELOC_HI16_S; | |
8233 | imm_unmatched_hi = true; | |
8234 | } | |
670a50eb ILT |
8235 | else |
8236 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 8237 | } |
6b34ac5a ILT |
8238 | else if (imm_expr.X_op == O_constant) |
8239 | imm_expr.X_add_number &= 0xffff; | |
670a50eb | 8240 | } |
670a50eb ILT |
8241 | if (*args == 'i') |
8242 | { | |
344a8d61 | 8243 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
8244 | || ((imm_expr.X_add_number < 0 |
8245 | || imm_expr.X_add_number >= 0x10000) | |
8246 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
8247 | { |
8248 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8249 | !strcmp (insn->name, insn[1].name)) | |
8250 | break; | |
9753202d ILT |
8251 | if (imm_expr.X_op != O_constant |
8252 | && imm_expr.X_op != O_big) | |
48401fcf | 8253 | insn_error = _("absolute expression required"); |
9753202d | 8254 | else |
48401fcf | 8255 | as_bad (_("16 bit expression not in range 0..65535")); |
99c24539 | 8256 | } |
670a50eb ILT |
8257 | } |
8258 | else | |
8259 | { | |
d9aba805 ILT |
8260 | int more; |
8261 | offsetT max; | |
8262 | ||
be22008b ILT |
8263 | /* The upper bound should be 0x8000, but |
8264 | unfortunately the MIPS assembler accepts numbers | |
8265 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
8266 | we want to be compatible. We only permit this |
8267 | extended range for an instruction which does not | |
8268 | provide any further alternates, since those | |
8269 | alternates may handle other cases. People should | |
8270 | use the numbers they mean, rather than relying on | |
8271 | a mysterious sign extension. */ | |
8272 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8273 | strcmp (insn->name, insn[1].name) == 0); | |
8274 | if (more) | |
8275 | max = 0x8000; | |
8276 | else | |
8277 | max = 0x10000; | |
344a8d61 | 8278 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
8279 | || ((imm_expr.X_add_number < -0x8000 |
8280 | || imm_expr.X_add_number >= max) | |
8281 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
8282 | || (more |
8283 | && imm_expr.X_add_number < 0 | |
3c83da8a | 8284 | && mips_opts.isa >= 3 |
d8a1c247 KR |
8285 | && imm_expr.X_unsigned |
8286 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 8287 | { |
d9aba805 | 8288 | if (more) |
99c24539 | 8289 | break; |
9753202d ILT |
8290 | if (imm_expr.X_op != O_constant |
8291 | && imm_expr.X_op != O_big) | |
48401fcf | 8292 | insn_error = _("absolute expression required"); |
9753202d | 8293 | else |
48401fcf | 8294 | as_bad (_("16 bit expression not in range -32768..32767")); |
99c24539 | 8295 | } |
3d3c5039 | 8296 | } |
670a50eb ILT |
8297 | s = expr_end; |
8298 | continue; | |
8299 | ||
8300 | case 'o': /* 16 bit offset */ | |
8301 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
8302 | |
8303 | /* If this value won't fit into a 16 bit offset, then go | |
8304 | find a macro that will generate the 32 bit offset | |
8305 | code pattern. As a special hack, we accept the | |
8306 | difference of two local symbols as a constant. This | |
8307 | is required to suppose embedded PIC switches, which | |
8308 | use an instruction which looks like | |
8309 | lw $4,$L12-$LS12($4) | |
8310 | The problem with handling this in a more general | |
8311 | fashion is that the macro function doesn't expect to | |
8312 | see anything which can be handled in a single | |
8313 | constant instruction. */ | |
6f0b87c3 SS |
8314 | if (c == 0 |
8315 | && (offset_expr.X_op != O_constant | |
8316 | || offset_expr.X_add_number >= 0x8000 | |
8317 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
8318 | && (mips_pic != EMBEDDED_PIC |
8319 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
8320 | || now_seg != text_section |
8321 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
8322 | != text_section))) | |
670a50eb | 8323 | break; |
3d3c5039 | 8324 | |
670a50eb ILT |
8325 | offset_reloc = BFD_RELOC_LO16; |
8326 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
8327 | { |
8328 | assert (offset_expr.X_op == O_constant); | |
8329 | offset_expr.X_add_number = | |
8330 | (offset_expr.X_add_number >> 16) & 0xffff; | |
8331 | } | |
cc5703cd ILT |
8332 | s = expr_end; |
8333 | continue; | |
8334 | ||
8335 | case 'p': /* pc relative offset */ | |
8336 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
8337 | my_getExpression (&offset_expr, s); | |
8338 | s = expr_end; | |
8339 | continue; | |
8340 | ||
8341 | case 'u': /* upper 16 bits */ | |
8342 | c = my_getSmallExpression (&imm_expr, s); | |
cc5703cd ILT |
8343 | imm_reloc = BFD_RELOC_LO16; |
8344 | if (c) | |
8345 | { | |
8346 | if (c != 'l') | |
8347 | { | |
8348 | if (imm_expr.X_op == O_constant) | |
8349 | imm_expr.X_add_number = | |
8350 | (imm_expr.X_add_number >> 16) & 0xffff; | |
8351 | else if (c == 'h') | |
8352 | { | |
8353 | imm_reloc = BFD_RELOC_HI16_S; | |
8354 | imm_unmatched_hi = true; | |
8355 | } | |
8356 | else | |
8357 | imm_reloc = BFD_RELOC_HI16; | |
8358 | } | |
6b34ac5a ILT |
8359 | else if (imm_expr.X_op == O_constant) |
8360 | imm_expr.X_add_number &= 0xffff; | |
cc5703cd | 8361 | } |
6b34ac5a ILT |
8362 | if (imm_expr.X_op == O_constant |
8363 | && (imm_expr.X_add_number < 0 | |
8364 | || imm_expr.X_add_number >= 0x10000)) | |
8365 | as_bad (_("lui expression not in range 0..65535")); | |
cc5703cd ILT |
8366 | s = expr_end; |
8367 | continue; | |
8368 | ||
8369 | case 'a': /* 26 bit address */ | |
8370 | my_getExpression (&offset_expr, s); | |
8371 | s = expr_end; | |
8372 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
8373 | continue; | |
8374 | ||
8375 | case 'N': /* 3 bit branch condition code */ | |
8376 | case 'M': /* 3 bit compare condition code */ | |
8377 | if (strncmp (s, "$fcc", 4) != 0) | |
8378 | break; | |
8379 | s += 4; | |
8380 | regno = 0; | |
8381 | do | |
8382 | { | |
8383 | regno *= 10; | |
8384 | regno += *s - '0'; | |
8385 | ++s; | |
8386 | } | |
8387 | while (isdigit (*s)); | |
8388 | if (regno > 7) | |
48401fcf | 8389 | as_bad (_("invalid condition code register $fcc%d"), regno); |
cc5703cd ILT |
8390 | if (*args == 'N') |
8391 | ip->insn_opcode |= regno << OP_SH_BCC; | |
8392 | else | |
8393 | ip->insn_opcode |= regno << OP_SH_CCC; | |
8394 | continue; | |
8395 | ||
6b34ac5a | 8396 | /* start-sanitize-cygnus */ |
b3ed1af3 KR |
8397 | case 'e': /* must be at least one digit */ |
8398 | my_getExpression (&imm_expr, s); | |
8399 | check_absolute_expr (ip, &imm_expr); | |
8400 | if ((unsigned long) imm_expr.X_add_number > (unsigned long) OP_MASK_VECBYTE) | |
8401 | { | |
48401fcf | 8402 | as_bad (_("bad byte vector index (%ld)"), |
b3ed1af3 KR |
8403 | (long) imm_expr.X_add_number); |
8404 | imm_expr.X_add_number = imm_expr.X_add_number; | |
8405 | } | |
8406 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
8407 | imm_expr.X_op = O_absent; | |
8408 | s = expr_end; | |
8409 | continue; | |
8410 | ||
8411 | case '%': | |
8412 | my_getExpression (&imm_expr, s); | |
8413 | check_absolute_expr (ip, &imm_expr); | |
8414 | if ((unsigned long) imm_expr.X_add_number > (unsigned long) OP_MASK_VECALIGN) | |
8415 | { | |
48401fcf | 8416 | as_bad (_("bad byte vector index (%ld)"), |
b3ed1af3 KR |
8417 | (long) imm_expr.X_add_number); |
8418 | imm_expr.X_add_number = imm_expr.X_add_number; | |
8419 | } | |
8420 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
8421 | imm_expr.X_op = O_absent; | |
8422 | s = expr_end; | |
8423 | continue; | |
8424 | ||
6b34ac5a | 8425 | /* end-sanitize-cygnus */ |
cc5703cd | 8426 | default: |
48401fcf | 8427 | as_bad (_("bad char = '%c'\n"), *args); |
cc5703cd ILT |
8428 | internalError (); |
8429 | } | |
8430 | break; | |
8431 | } | |
8432 | /* Args don't match. */ | |
8433 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8434 | !strcmp (insn->name, insn[1].name)) | |
8435 | { | |
8436 | ++insn; | |
8437 | s = argsStart; | |
8438 | continue; | |
8439 | } | |
48401fcf | 8440 | insn_error = _("illegal operands"); |
cc5703cd ILT |
8441 | return; |
8442 | } | |
8443 | } | |
8444 | ||
8445 | /* This routine assembles an instruction into its binary format when | |
8446 | assembling for the mips16. As a side effect, it sets one of the | |
8447 | global variables imm_reloc or offset_reloc to the type of | |
8728fa92 ILT |
8448 | relocation to do if one of the operands is an address expression. |
8449 | It also sets mips16_small and mips16_ext if the user explicitly | |
8450 | requested a small or extended instruction. */ | |
cc5703cd ILT |
8451 | |
8452 | static void | |
8453 | mips16_ip (str, ip) | |
8454 | char *str; | |
8455 | struct mips_cl_insn *ip; | |
8456 | { | |
8457 | char *s; | |
cc5703cd ILT |
8458 | const char *args; |
8459 | struct mips_opcode *insn; | |
8460 | char *argsstart; | |
8461 | unsigned int regno; | |
8462 | unsigned int lastregno = 0; | |
8463 | char *s_reset; | |
8464 | ||
8465 | insn_error = NULL; | |
8466 | ||
8728fa92 ILT |
8467 | mips16_small = false; |
8468 | mips16_ext = false; | |
cc5703cd ILT |
8469 | |
8470 | for (s = str; islower (*s); ++s) | |
8471 | ; | |
8472 | switch (*s) | |
8473 | { | |
8474 | case '\0': | |
8475 | break; | |
8476 | ||
8477 | case ' ': | |
8478 | *s++ = '\0'; | |
8479 | break; | |
8480 | ||
8481 | case '.': | |
8482 | if (s[1] == 't' && s[2] == ' ') | |
8483 | { | |
8484 | *s = '\0'; | |
8728fa92 | 8485 | mips16_small = true; |
cc5703cd ILT |
8486 | s += 3; |
8487 | break; | |
8488 | } | |
8489 | else if (s[1] == 'e' && s[2] == ' ') | |
8490 | { | |
8491 | *s = '\0'; | |
8728fa92 | 8492 | mips16_ext = true; |
cc5703cd ILT |
8493 | s += 3; |
8494 | break; | |
8495 | } | |
8496 | /* Fall through. */ | |
8497 | default: | |
48401fcf | 8498 | insn_error = _("unknown opcode"); |
cc5703cd ILT |
8499 | return; |
8500 | } | |
8501 | ||
3c83da8a | 8502 | if (mips_opts.noautoextend && ! mips16_ext) |
8728fa92 ILT |
8503 | mips16_small = true; |
8504 | ||
cc5703cd ILT |
8505 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
8506 | { | |
48401fcf | 8507 | insn_error = _("unrecognized opcode"); |
cc5703cd ILT |
8508 | return; |
8509 | } | |
8510 | ||
8511 | argsstart = s; | |
8512 | for (;;) | |
8513 | { | |
8514 | assert (strcmp (insn->name, str) == 0); | |
8515 | ||
8516 | ip->insn_mo = insn; | |
8517 | ip->insn_opcode = insn->match; | |
8518 | ip->use_extend = false; | |
8519 | imm_expr.X_op = O_absent; | |
8520 | imm_reloc = BFD_RELOC_UNUSED; | |
8521 | offset_expr.X_op = O_absent; | |
8522 | offset_reloc = BFD_RELOC_UNUSED; | |
8523 | for (args = insn->args; 1; ++args) | |
8524 | { | |
8525 | int c; | |
8526 | ||
8527 | if (*s == ' ') | |
8528 | ++s; | |
8529 | ||
8530 | /* In this switch statement we call break if we did not find | |
8531 | a match, continue if we did find a match, or return if we | |
8532 | are done. */ | |
8533 | ||
8534 | c = *args; | |
8535 | switch (c) | |
8536 | { | |
8537 | case '\0': | |
8538 | if (*s == '\0') | |
8539 | { | |
8540 | /* Stuff the immediate value in now, if we can. */ | |
8541 | if (imm_expr.X_op == O_constant | |
8542 | && imm_reloc > BFD_RELOC_UNUSED | |
8543 | && insn->pinfo != INSN_MACRO) | |
8544 | { | |
15e69f98 ILT |
8545 | mips16_immed ((char *) NULL, 0, |
8546 | imm_reloc - BFD_RELOC_UNUSED, | |
8728fa92 ILT |
8547 | imm_expr.X_add_number, true, mips16_small, |
8548 | mips16_ext, &ip->insn_opcode, | |
8549 | &ip->use_extend, &ip->extend); | |
cc5703cd ILT |
8550 | imm_expr.X_op = O_absent; |
8551 | imm_reloc = BFD_RELOC_UNUSED; | |
8552 | } | |
8553 | ||
8554 | return; | |
8555 | } | |
8556 | break; | |
8557 | ||
8558 | case ',': | |
8559 | if (*s++ == c) | |
8560 | continue; | |
8561 | s--; | |
8562 | switch (*++args) | |
8563 | { | |
8564 | case 'v': | |
8565 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8566 | continue; | |
8567 | case 'w': | |
8568 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8569 | continue; | |
8570 | } | |
8571 | break; | |
8572 | ||
8573 | case '(': | |
8574 | case ')': | |
8575 | if (*s++ == c) | |
8576 | continue; | |
8577 | break; | |
8578 | ||
8579 | case 'v': | |
8580 | case 'w': | |
8581 | if (s[0] != '$') | |
8582 | { | |
8583 | if (c == 'v') | |
8584 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8585 | else | |
8586 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8587 | ++args; | |
8588 | continue; | |
8589 | } | |
8590 | /* Fall through. */ | |
8591 | case 'x': | |
8592 | case 'y': | |
8593 | case 'z': | |
8594 | case 'Z': | |
8595 | case '0': | |
8596 | case 'S': | |
8597 | case 'R': | |
8598 | case 'X': | |
8599 | case 'Y': | |
8600 | if (s[0] != '$') | |
8601 | break; | |
8602 | s_reset = s; | |
8603 | if (isdigit (s[1])) | |
8604 | { | |
8605 | ++s; | |
8606 | regno = 0; | |
8607 | do | |
8608 | { | |
8609 | regno *= 10; | |
8610 | regno += *s - '0'; | |
8611 | ++s; | |
8612 | } | |
8613 | while (isdigit (*s)); | |
8614 | if (regno > 31) | |
8615 | { | |
48401fcf | 8616 | as_bad (_("invalid register number (%d)"), regno); |
cc5703cd ILT |
8617 | regno = 2; |
8618 | } | |
8619 | } | |
8620 | else | |
8621 | { | |
8622 | if (s[1] == 'f' && s[2] == 'p') | |
8623 | { | |
8624 | s += 3; | |
8625 | regno = FP; | |
8626 | } | |
8627 | else if (s[1] == 's' && s[2] == 'p') | |
8628 | { | |
8629 | s += 3; | |
8630 | regno = SP; | |
8631 | } | |
8632 | else if (s[1] == 'g' && s[2] == 'p') | |
8633 | { | |
8634 | s += 3; | |
8635 | regno = GP; | |
8636 | } | |
8637 | else if (s[1] == 'a' && s[2] == 't') | |
8638 | { | |
8639 | s += 3; | |
8640 | regno = AT; | |
8641 | } | |
8642 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8643 | { | |
8644 | s += 4; | |
8645 | regno = KT0; | |
8646 | } | |
8647 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8648 | { | |
8649 | s += 4; | |
8650 | regno = KT1; | |
8651 | } | |
8652 | else | |
8653 | break; | |
8654 | } | |
8655 | ||
8656 | if (*s == ' ') | |
8657 | ++s; | |
8658 | if (args[1] != *s) | |
8659 | { | |
8660 | if (c == 'v' || c == 'w') | |
8661 | { | |
8662 | regno = mips16_to_32_reg_map[lastregno]; | |
8663 | s = s_reset; | |
8664 | args++; | |
8665 | } | |
8666 | } | |
8667 | ||
8668 | switch (c) | |
8669 | { | |
8670 | case 'x': | |
8671 | case 'y': | |
8672 | case 'z': | |
8673 | case 'v': | |
8674 | case 'w': | |
8675 | case 'Z': | |
8676 | regno = mips32_to_16_reg_map[regno]; | |
8677 | break; | |
8678 | ||
8679 | case '0': | |
8680 | if (regno != 0) | |
8681 | regno = ILLEGAL_REG; | |
8682 | break; | |
8683 | ||
8684 | case 'S': | |
8685 | if (regno != SP) | |
8686 | regno = ILLEGAL_REG; | |
8687 | break; | |
8688 | ||
8689 | case 'R': | |
8690 | if (regno != RA) | |
8691 | regno = ILLEGAL_REG; | |
8692 | break; | |
8693 | ||
8694 | case 'X': | |
8695 | case 'Y': | |
3c83da8a | 8696 | if (regno == AT && ! mips_opts.noat) |
48401fcf | 8697 | as_warn (_("used $at without \".set noat\"")); |
cc5703cd ILT |
8698 | break; |
8699 | ||
8700 | default: | |
8701 | internalError (); | |
8702 | } | |
8703 | ||
8704 | if (regno == ILLEGAL_REG) | |
8705 | break; | |
8706 | ||
8707 | switch (c) | |
8708 | { | |
8709 | case 'x': | |
8710 | case 'v': | |
8711 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
8712 | break; | |
8713 | case 'y': | |
8714 | case 'w': | |
8715 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
8716 | break; | |
8717 | case 'z': | |
8718 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
8719 | break; | |
8720 | case 'Z': | |
8721 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
8722 | case '0': | |
8723 | case 'S': | |
8724 | case 'R': | |
8725 | break; | |
8726 | case 'X': | |
8727 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
8728 | break; | |
8729 | case 'Y': | |
8730 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
8731 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
8732 | break; | |
8733 | default: | |
8734 | internalError (); | |
8735 | } | |
8736 | ||
8737 | lastregno = regno; | |
8738 | continue; | |
8739 | ||
8740 | case 'P': | |
8741 | if (strncmp (s, "$pc", 3) == 0) | |
8742 | { | |
8743 | s += 3; | |
8744 | continue; | |
8745 | } | |
8746 | break; | |
8747 | ||
8748 | case '<': | |
8749 | case '>': | |
8750 | case '[': | |
8751 | case ']': | |
8752 | case '4': | |
8753 | case '5': | |
8754 | case 'H': | |
8755 | case 'W': | |
8756 | case 'D': | |
8757 | case 'j': | |
8758 | case '8': | |
8759 | case 'V': | |
8760 | case 'C': | |
8761 | case 'U': | |
8762 | case 'k': | |
8763 | case 'K': | |
16262668 ILT |
8764 | if (s[0] == '%' |
8765 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
8766 | { | |
8767 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
8768 | and generate the appropriate reloc. If the text | |
8769 | inside %gprel is not a symbol name with an | |
8770 | optional offset, then we generate a normal reloc | |
8771 | and will probably fail later. */ | |
8772 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
8773 | if (imm_expr.X_op == O_symbol) | |
8774 | { | |
8775 | mips16_ext = true; | |
8776 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
8777 | s = expr_end; | |
8778 | ip->use_extend = true; | |
8779 | ip->extend = 0; | |
8780 | continue; | |
8781 | } | |
8782 | } | |
8783 | else | |
8784 | { | |
8785 | /* Just pick up a normal expression. */ | |
8786 | my_getExpression (&imm_expr, s); | |
8787 | } | |
8788 | ||
ebf28372 ILT |
8789 | if (imm_expr.X_op == O_register) |
8790 | { | |
8791 | /* What we thought was an expression turned out to | |
8792 | be a register. */ | |
8793 | ||
8794 | if (s[0] == '(' && args[1] == '(') | |
8795 | { | |
8796 | /* It looks like the expression was omitted | |
8797 | before a register indirection, which means | |
8798 | that the expression is implicitly zero. We | |
8799 | still set up imm_expr, so that we handle | |
8800 | explicit extensions correctly. */ | |
8801 | imm_expr.X_op = O_constant; | |
8802 | imm_expr.X_add_number = 0; | |
8803 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8804 | continue; | |
8805 | } | |
8806 | ||
8807 | break; | |
8808 | } | |
8809 | ||
cc5703cd ILT |
8810 | /* We need to relax this instruction. */ |
8811 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8812 | s = expr_end; | |
8813 | continue; | |
8814 | ||
8815 | case 'p': | |
8816 | case 'q': | |
8817 | case 'A': | |
8818 | case 'B': | |
8819 | case 'E': | |
8820 | /* We use offset_reloc rather than imm_reloc for the PC | |
8821 | relative operands. This lets macros with both | |
8822 | immediate and address operands work correctly. */ | |
670a50eb | 8823 | my_getExpression (&offset_expr, s); |
ebf28372 ILT |
8824 | |
8825 | if (offset_expr.X_op == O_register) | |
8826 | break; | |
8827 | ||
cc5703cd ILT |
8828 | /* We need to relax this instruction. */ |
8829 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
8830 | s = expr_end; |
8831 | continue; | |
8832 | ||
cc5703cd ILT |
8833 | case '6': /* break code */ |
8834 | my_getExpression (&imm_expr, s); | |
8835 | check_absolute_expr (ip, &imm_expr); | |
8836 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 8837 | { |
48401fcf | 8838 | as_warn (_("Invalid value for `%s' (%lu)"), |
cc5703cd ILT |
8839 | ip->insn_mo->name, |
8840 | (unsigned long) imm_expr.X_add_number); | |
8841 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 8842 | } |
cc5703cd ILT |
8843 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
8844 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
8845 | s = expr_end; |
8846 | continue; | |
3d3c5039 | 8847 | |
670a50eb ILT |
8848 | case 'a': /* 26 bit address */ |
8849 | my_getExpression (&offset_expr, s); | |
8850 | s = expr_end; | |
cc5703cd ILT |
8851 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
8852 | ip->insn_opcode <<= 16; | |
670a50eb | 8853 | continue; |
3d3c5039 | 8854 | |
cc5703cd ILT |
8855 | case 'l': /* register list for entry macro */ |
8856 | case 'L': /* register list for exit macro */ | |
8857 | { | |
8858 | int mask; | |
8859 | ||
8860 | if (c == 'l') | |
8861 | mask = 0; | |
8862 | else | |
8863 | mask = 7 << 3; | |
8864 | while (*s != '\0') | |
8865 | { | |
c9167640 | 8866 | int freg, reg1, reg2; |
cc5703cd ILT |
8867 | |
8868 | while (*s == ' ' || *s == ',') | |
8869 | ++s; | |
8870 | if (*s != '$') | |
8871 | { | |
48401fcf | 8872 | as_bad (_("can't parse register list")); |
cc5703cd ILT |
8873 | break; |
8874 | } | |
8875 | ++s; | |
c9167640 ILT |
8876 | if (*s != 'f') |
8877 | freg = 0; | |
8878 | else | |
8879 | { | |
8880 | freg = 1; | |
8881 | ++s; | |
8882 | } | |
cc5703cd ILT |
8883 | reg1 = 0; |
8884 | while (isdigit (*s)) | |
8885 | { | |
8886 | reg1 *= 10; | |
8887 | reg1 += *s - '0'; | |
8888 | ++s; | |
8889 | } | |
8890 | if (*s == ' ') | |
8891 | ++s; | |
8892 | if (*s != '-') | |
8893 | reg2 = reg1; | |
8894 | else | |
8895 | { | |
8896 | ++s; | |
8897 | if (*s != '$') | |
8898 | break; | |
8899 | ++s; | |
c9167640 ILT |
8900 | if (freg) |
8901 | { | |
8902 | if (*s == 'f') | |
8903 | ++s; | |
8904 | else | |
8905 | { | |
48401fcf | 8906 | as_bad (_("invalid register list")); |
c9167640 ILT |
8907 | break; |
8908 | } | |
8909 | } | |
cc5703cd ILT |
8910 | reg2 = 0; |
8911 | while (isdigit (*s)) | |
8912 | { | |
8913 | reg2 *= 10; | |
8914 | reg2 += *s - '0'; | |
8915 | ++s; | |
8916 | } | |
8917 | } | |
c9167640 ILT |
8918 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') |
8919 | { | |
8920 | mask &= ~ (7 << 3); | |
8921 | mask |= 5 << 3; | |
8922 | } | |
8923 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
8924 | { | |
8925 | mask &= ~ (7 << 3); | |
8926 | mask |= 6 << 3; | |
8927 | } | |
8928 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
cc5703cd ILT |
8929 | mask |= (reg2 - 3) << 3; |
8930 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
8931 | mask |= (reg2 - 15) << 1; | |
8932 | else if (reg1 == 31 && reg2 == 31) | |
8933 | mask |= 1; | |
8934 | else | |
c9167640 | 8935 | { |
48401fcf | 8936 | as_bad (_("invalid register list")); |
c9167640 ILT |
8937 | break; |
8938 | } | |
cc5703cd | 8939 | } |
c9167640 ILT |
8940 | /* The mask is filled in in the opcode table for the |
8941 | benefit of the disassembler. We remove it before | |
8942 | applying the actual mask. */ | |
8943 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
cc5703cd ILT |
8944 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; |
8945 | } | |
8946 | continue; | |
d8a1c247 | 8947 | |
56bb6eee ILT |
8948 | case 'e': /* extend code */ |
8949 | my_getExpression (&imm_expr, s); | |
8950 | check_absolute_expr (ip, &imm_expr); | |
8951 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
8952 | { | |
48401fcf | 8953 | as_warn (_("Invalid value for `%s' (%lu)"), |
56bb6eee ILT |
8954 | ip->insn_mo->name, |
8955 | (unsigned long) imm_expr.X_add_number); | |
8956 | imm_expr.X_add_number &= 0x7ff; | |
8957 | } | |
8958 | ip->insn_opcode |= imm_expr.X_add_number; | |
8959 | imm_expr.X_op = O_absent; | |
8960 | s = expr_end; | |
8961 | continue; | |
8962 | ||
3d3c5039 | 8963 | default: |
670a50eb | 8964 | internalError (); |
3d3c5039 | 8965 | } |
670a50eb | 8966 | break; |
3d3c5039 | 8967 | } |
cc5703cd | 8968 | |
670a50eb | 8969 | /* Args don't match. */ |
cc5703cd ILT |
8970 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
8971 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
8972 | { |
8973 | ++insn; | |
cc5703cd | 8974 | s = argsstart; |
670a50eb | 8975 | continue; |
3d3c5039 | 8976 | } |
cc5703cd | 8977 | |
48401fcf | 8978 | insn_error = _("illegal operands"); |
cc5703cd | 8979 | |
670a50eb | 8980 | return; |
3d3c5039 ILT |
8981 | } |
8982 | } | |
8983 | ||
cc5703cd ILT |
8984 | /* This structure holds information we know about a mips16 immediate |
8985 | argument type. */ | |
8986 | ||
8987 | struct mips16_immed_operand | |
8988 | { | |
8989 | /* The type code used in the argument string in the opcode table. */ | |
8990 | int type; | |
8991 | /* The number of bits in the short form of the opcode. */ | |
8992 | int nbits; | |
8993 | /* The number of bits in the extended form of the opcode. */ | |
8994 | int extbits; | |
8995 | /* The amount by which the short form is shifted when it is used; | |
8996 | for example, the sw instruction has a shift count of 2. */ | |
8997 | int shift; | |
8998 | /* The amount by which the short form is shifted when it is stored | |
8999 | into the instruction code. */ | |
9000 | int op_shift; | |
9001 | /* Non-zero if the short form is unsigned. */ | |
9002 | int unsp; | |
9003 | /* Non-zero if the extended form is unsigned. */ | |
9004 | int extu; | |
9005 | /* Non-zero if the value is PC relative. */ | |
9006 | int pcrel; | |
9007 | }; | |
9008 | ||
9009 | /* The mips16 immediate operand types. */ | |
9010 | ||
9011 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9012 | { | |
9013 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9014 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9015 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9016 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9017 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9018 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9019 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9020 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9021 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9022 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9023 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9024 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9025 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9026 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9027 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9028 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9029 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9030 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9031 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9032 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9033 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9034 | }; | |
9035 | ||
9036 | #define MIPS16_NUM_IMMED \ | |
9037 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9038 | ||
9039 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9040 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9041 | whether an extended value is needed; if one is needed, it sets | |
9042 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9043 | If SMALL is true, an unextended opcode was explicitly requested. | |
9044 | If EXT is true, an extended opcode was explicitly requested. If | |
9045 | WARN is true, warn if EXT does not match reality. */ | |
9046 | ||
9047 | static void | |
15e69f98 ILT |
9048 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
9049 | extend) | |
9050 | char *file; | |
9051 | unsigned int line; | |
cc5703cd ILT |
9052 | int type; |
9053 | offsetT val; | |
9054 | boolean warn; | |
9055 | boolean small; | |
9056 | boolean ext; | |
9057 | unsigned long *insn; | |
9058 | boolean *use_extend; | |
9059 | unsigned short *extend; | |
9060 | { | |
9061 | register const struct mips16_immed_operand *op; | |
9062 | int mintiny, maxtiny; | |
9063 | boolean needext; | |
9064 | ||
9065 | op = mips16_immed_operands; | |
9066 | while (op->type != type) | |
9067 | { | |
9068 | ++op; | |
9069 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9070 | } | |
9071 | ||
9072 | if (op->unsp) | |
9073 | { | |
9074 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9075 | { | |
9076 | mintiny = 1; | |
9077 | maxtiny = 1 << op->nbits; | |
9078 | } | |
9079 | else | |
9080 | { | |
9081 | mintiny = 0; | |
9082 | maxtiny = (1 << op->nbits) - 1; | |
9083 | } | |
9084 | } | |
9085 | else | |
9086 | { | |
9087 | mintiny = - (1 << (op->nbits - 1)); | |
9088 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9089 | } | |
9090 | ||
9091 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9092 | if (type == 'p' || type == 'q') | |
fbcfacb7 | 9093 | val /= 2; |
cc5703cd ILT |
9094 | |
9095 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9096 | || val < (mintiny << op->shift) | |
9097 | || val > (maxtiny << op->shift)) | |
9098 | needext = true; | |
9099 | else | |
9100 | needext = false; | |
9101 | ||
9102 | if (warn && ext && ! needext) | |
48401fcf | 9103 | as_warn_where (file, line, _("extended operand requested but not required")); |
8728fa92 | 9104 | if (small && needext) |
48401fcf | 9105 | as_bad_where (file, line, _("invalid unextended operand value")); |
cc5703cd ILT |
9106 | |
9107 | if (small || (! ext && ! needext)) | |
9108 | { | |
9109 | int insnval; | |
9110 | ||
9111 | *use_extend = false; | |
9112 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
9113 | insnval <<= op->op_shift; | |
9114 | *insn |= insnval; | |
9115 | } | |
9116 | else | |
9117 | { | |
9118 | long minext, maxext; | |
9119 | int extval; | |
9120 | ||
9121 | if (op->extu) | |
9122 | { | |
9123 | minext = 0; | |
9124 | maxext = (1 << op->extbits) - 1; | |
9125 | } | |
9126 | else | |
9127 | { | |
9128 | minext = - (1 << (op->extbits - 1)); | |
9129 | maxext = (1 << (op->extbits - 1)) - 1; | |
9130 | } | |
9131 | if (val < minext || val > maxext) | |
15e69f98 | 9132 | as_bad_where (file, line, |
48401fcf | 9133 | _("operand value out of range for instruction")); |
cc5703cd ILT |
9134 | |
9135 | *use_extend = true; | |
9136 | if (op->extbits == 16) | |
9137 | { | |
9138 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9139 | val &= 0x1f; | |
9140 | } | |
9141 | else if (op->extbits == 15) | |
9142 | { | |
9143 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9144 | val &= 0xf; | |
9145 | } | |
9146 | else | |
9147 | { | |
9148 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9149 | val = 0; | |
9150 | } | |
9151 | ||
9152 | *extend = (unsigned short) extval; | |
9153 | *insn |= val; | |
9154 | } | |
9155 | } | |
9156 | \f | |
3d3c5039 ILT |
9157 | #define LP '(' |
9158 | #define RP ')' | |
9159 | ||
9160 | static int | |
9161 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
9162 | expressionS *ep; |
9163 | char *str; | |
3d3c5039 | 9164 | { |
670a50eb ILT |
9165 | char *sp; |
9166 | int c = 0; | |
9167 | ||
9168 | if (*str == ' ') | |
9169 | str++; | |
9170 | if (*str == LP | |
9171 | || (*str == '%' && | |
9172 | ((str[1] == 'h' && str[2] == 'i') | |
9173 | || (str[1] == 'H' && str[2] == 'I') | |
9174 | || (str[1] == 'l' && str[2] == 'o')) | |
9175 | && str[3] == LP)) | |
9176 | { | |
9177 | if (*str == LP) | |
9178 | c = 0; | |
9179 | else | |
9180 | { | |
9181 | c = str[1]; | |
9182 | str += 3; | |
9183 | } | |
9184 | ||
9185 | /* | |
9186 | * A small expression may be followed by a base register. | |
9187 | * Scan to the end of this operand, and then back over a possible | |
9188 | * base register. Then scan the small expression up to that | |
9189 | * point. (Based on code in sparc.c...) | |
9190 | */ | |
9191 | for (sp = str; *sp && *sp != ','; sp++) | |
9192 | ; | |
9193 | if (sp - 4 >= str && sp[-1] == RP) | |
9194 | { | |
9195 | if (isdigit (sp[-2])) | |
9196 | { | |
9197 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
9198 | ; | |
9199 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
9200 | { | |
9201 | sp--; | |
9202 | goto do_it; | |
3d3c5039 | 9203 | } |
670a50eb ILT |
9204 | } |
9205 | else if (sp - 5 >= str | |
9206 | && sp[-5] == LP | |
9207 | && sp[-4] == '$' | |
9208 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
9209 | || (sp[-3] == 's' && sp[-2] == 'p') | |
9210 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
9211 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
9212 | { | |
9213 | sp -= 5; | |
3d3c5039 | 9214 | do_it: |
670a50eb ILT |
9215 | if (sp == str) |
9216 | { | |
9217 | /* no expression means zero offset */ | |
9218 | if (c) | |
9219 | { | |
9220 | /* %xx(reg) is an error */ | |
5ac34ac3 | 9221 | ep->X_op = O_absent; |
670a50eb | 9222 | expr_end = str - 3; |
3d3c5039 | 9223 | } |
670a50eb ILT |
9224 | else |
9225 | { | |
52aa70b5 | 9226 | ep->X_op = O_constant; |
670a50eb ILT |
9227 | expr_end = sp; |
9228 | } | |
9229 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 9230 | ep->X_op_symbol = NULL; |
670a50eb ILT |
9231 | ep->X_add_number = 0; |
9232 | } | |
9233 | else | |
9234 | { | |
9235 | *sp = '\0'; | |
9236 | my_getExpression (ep, str); | |
9237 | *sp = LP; | |
3d3c5039 | 9238 | } |
670a50eb | 9239 | return c; |
3d3c5039 ILT |
9240 | } |
9241 | } | |
9242 | } | |
670a50eb ILT |
9243 | my_getExpression (ep, str); |
9244 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
9245 | } |
9246 | ||
9247 | static void | |
9248 | my_getExpression (ep, str) | |
670a50eb ILT |
9249 | expressionS *ep; |
9250 | char *str; | |
3d3c5039 | 9251 | { |
670a50eb | 9252 | char *save_in; |
670a50eb ILT |
9253 | |
9254 | save_in = input_line_pointer; | |
9255 | input_line_pointer = str; | |
5ac34ac3 | 9256 | expression (ep); |
670a50eb ILT |
9257 | expr_end = input_line_pointer; |
9258 | input_line_pointer = save_in; | |
eb17f56c ILT |
9259 | |
9260 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9261 | then we bump the value of the symbol by 1 since that is how other | |
9262 | text symbols are handled. We don't bother to handle complex | |
9263 | expressions, just `.' plus or minus a constant. */ | |
3c83da8a | 9264 | if (mips_opts.mips16 |
eb17f56c ILT |
9265 | && ep->X_op == O_symbol |
9266 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9267 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
9268 | && ep->X_add_symbol->sy_frag == frag_now | |
9269 | && ep->X_add_symbol->sy_value.X_op == O_constant | |
9270 | && ep->X_add_symbol->sy_value.X_add_number == frag_now_fix ()) | |
9271 | ++ep->X_add_symbol->sy_value.X_add_number; | |
3d3c5039 ILT |
9272 | } |
9273 | ||
becfe05e ILT |
9274 | /* Turn a string in input_line_pointer into a floating point constant |
9275 | of type type, and store the appropriate bytes in *litP. The number | |
9276 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
9277 | returned, or NULL on OK. */ | |
9278 | ||
3d3c5039 | 9279 | char * |
670a50eb | 9280 | md_atof (type, litP, sizeP) |
becfe05e | 9281 | int type; |
3d3c5039 ILT |
9282 | char *litP; |
9283 | int *sizeP; | |
9284 | { | |
becfe05e ILT |
9285 | int prec; |
9286 | LITTLENUM_TYPE words[4]; | |
9287 | char *t; | |
9288 | int i; | |
9289 | ||
9290 | switch (type) | |
9291 | { | |
9292 | case 'f': | |
9293 | prec = 2; | |
9294 | break; | |
9295 | ||
9296 | case 'd': | |
9297 | prec = 4; | |
9298 | break; | |
9299 | ||
9300 | default: | |
9301 | *sizeP = 0; | |
48401fcf | 9302 | return _("bad call to md_atof"); |
becfe05e ILT |
9303 | } |
9304 | ||
9305 | t = atof_ieee (input_line_pointer, type, words); | |
9306 | if (t) | |
9307 | input_line_pointer = t; | |
9308 | ||
9309 | *sizeP = prec * 2; | |
9310 | ||
b9129c6f | 9311 | if (! target_big_endian) |
becfe05e ILT |
9312 | { |
9313 | for (i = prec - 1; i >= 0; i--) | |
9314 | { | |
9315 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9316 | litP += 2; | |
9317 | } | |
9318 | } | |
9319 | else | |
9320 | { | |
9321 | for (i = 0; i < prec; i++) | |
9322 | { | |
9323 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9324 | litP += 2; | |
9325 | } | |
9326 | } | |
9327 | ||
670a50eb | 9328 | return NULL; |
3d3c5039 ILT |
9329 | } |
9330 | ||
9331 | void | |
9332 | md_number_to_chars (buf, val, n) | |
9333 | char *buf; | |
918692a5 | 9334 | valueT val; |
3d3c5039 ILT |
9335 | int n; |
9336 | { | |
b9129c6f ILT |
9337 | if (target_big_endian) |
9338 | number_to_chars_bigendian (buf, val, n); | |
9339 | else | |
9340 | number_to_chars_littleendian (buf, val, n); | |
3d3c5039 | 9341 | } |
f3d817d8 | 9342 | \f |
e8d4d475 | 9343 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 9344 | |
f3d817d8 DM |
9345 | struct option md_longopts[] = { |
9346 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
9347 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
9348 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
9349 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
9350 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
9351 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
9352 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
9353 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
9354 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
9355 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 9356 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 9357 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 9358 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 9359 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
9360 | {"trap", no_argument, NULL, OPTION_TRAP}, |
9361 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 9362 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
9363 | {"break", no_argument, NULL, OPTION_BREAK}, |
9364 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 9365 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 9366 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 9367 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 9368 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 9369 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 9370 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 9371 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 9372 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
9373 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
9374 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
9375 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
9376 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
9377 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
9378 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
9379 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
9380 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 9381 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 9382 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 9383 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 9384 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
46a92fde | 9385 | /* start-sanitize-r5900 */ |
276c2d7d GRK |
9386 | #define OPTION_M5900 (OPTION_MD_BASE + 24) |
9387 | {"m5900", no_argument, NULL, OPTION_M5900}, | |
9388 | #define OPTION_NO_M5900 (OPTION_MD_BASE + 25) | |
9389 | {"no-m5900", no_argument, NULL, OPTION_NO_M5900}, | |
46a92fde | 9390 | /* end-sanitize-r5900 */ |
5c6f5923 GRK |
9391 | #define OPTION_M3900 (OPTION_MD_BASE + 26) |
9392 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
9393 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 27) | |
9394 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
4e96260f JL |
9395 | |
9396 | /* start-sanitize-tx19 */ | |
9397 | {"m1900", no_argument, NULL, OPTION_M3900}, | |
9398 | {"no-m1900", no_argument, NULL, OPTION_NO_M3900}, | |
9399 | /* end-sanitize-tx19 */ | |
f3d817d8 | 9400 | |
6b34ac5a | 9401 | /* start-sanitize-cygnus */ |
aa2e0460 KR |
9402 | #define OPTION_M5400 (OPTION_MD_BASE + 28) |
9403 | {"m5400", no_argument, NULL, OPTION_M5400}, | |
9404 | #define OPTION_NO_M5400 (OPTION_MD_BASE + 29) | |
9405 | {"no-m5400", no_argument, NULL, OPTION_NO_M5400}, | |
9406 | ||
6b34ac5a | 9407 | /* end-sanitize-cygnus */ |
42444087 GRK |
9408 | /* start-sanitize-tx49 */ |
9409 | #define OPTION_M4900 (OPTION_MD_BASE + 30) | |
9410 | {"m4900", no_argument, NULL, OPTION_M4900}, | |
9411 | #define OPTION_NO_M4900 (OPTION_MD_BASE + 31) | |
9412 | {"no-m4900", no_argument, NULL, OPTION_NO_M4900}, | |
9413 | ||
9414 | /* end-sanitize-tx49 */ | |
2d035a50 GRK |
9415 | /* start-sanitize-vr4320 */ |
9416 | #define OPTION_M4320 (OPTION_MD_BASE + 32) | |
9417 | {"m4320", no_argument, NULL, OPTION_M4320}, | |
9418 | #define OPTION_NO_M4320 (OPTION_MD_BASE + 33) | |
9419 | {"no-m4320", no_argument, NULL, OPTION_NO_M4320}, | |
9420 | ||
9421 | /* end-sanitize-vr4320 */ | |
7e656649 RH |
9422 | /* start-sanitize-branchbug4011 */ |
9423 | #define OPTION_FIX_4011_BRANCH_BUG (OPTION_MD_BASE + 34) | |
9424 | {"fix-4011-branch-bug", no_argument, NULL, OPTION_FIX_4011_BRANCH_BUG}, | |
9425 | #define OPTION_NO_FIX_4011_BRANCH_BUG (OPTION_MD_BASE + 35) | |
9426 | {"no-fix-4011-branch-bug", no_argument, NULL, OPTION_NO_FIX_4011_BRANCH_BUG}, | |
f14397f0 | 9427 | |
02650bd0 | 9428 | /* end-sanitize-branchbug4011 */ |
f14397f0 GRK |
9429 | /* start-sanitize-vr4xxx */ |
9430 | #define OPTION_M4121 (OPTION_MD_BASE + 36) | |
9431 | {"m4121", no_argument, NULL, OPTION_M4121}, | |
9432 | #define OPTION_NO_M4121 (OPTION_MD_BASE + 37) | |
9433 | {"no-m4121", no_argument, NULL, OPTION_NO_M4121}, | |
9434 | ||
9435 | /* end-sanitize-vr4xxx */ | |
02650bd0 GRK |
9436 | #define OPTION_MABI (OPTION_MD_BASE + 38) |
9437 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
9438 | ||
d8a1c247 | 9439 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 9440 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 9441 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
9442 | #define OPTION_32 (OPTION_MD_BASE + 20) |
9443 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 9444 | #ifdef OBJ_ELF |
f3d817d8 | 9445 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 9446 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 9447 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 9448 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
9449 | {"32", no_argument, NULL, OPTION_32}, |
9450 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
9451 | #endif |
9452 | ||
9453 | {NULL, no_argument, NULL, 0} | |
9454 | }; | |
9455 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
9456 | |
9457 | int | |
f3d817d8 DM |
9458 | md_parse_option (c, arg) |
9459 | int c; | |
9460 | char *arg; | |
3d3c5039 | 9461 | { |
f3d817d8 | 9462 | switch (c) |
670a50eb | 9463 | { |
f3d817d8 DM |
9464 | case OPTION_TRAP: |
9465 | mips_trap = 1; | |
9466 | break; | |
670a50eb | 9467 | |
f3d817d8 DM |
9468 | case OPTION_BREAK: |
9469 | mips_trap = 0; | |
9470 | break; | |
9471 | ||
e8d4d475 | 9472 | case OPTION_EB: |
1dc1e798 | 9473 | target_big_endian = 1; |
e8d4d475 | 9474 | break; |
04cb3372 | 9475 | |
e8d4d475 | 9476 | case OPTION_EL: |
1dc1e798 | 9477 | target_big_endian = 0; |
f3d817d8 | 9478 | break; |
670a50eb | 9479 | |
f3d817d8 DM |
9480 | case 'O': |
9481 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
9482 | mips_optimize = 1; |
9483 | else | |
9484 | mips_optimize = 2; | |
f3d817d8 | 9485 | break; |
0aa07269 | 9486 | |
f3d817d8 | 9487 | case 'g': |
22ba90ce ILT |
9488 | if (arg == NULL) |
9489 | mips_debug = 2; | |
9490 | else | |
9491 | mips_debug = atoi (arg); | |
9492 | /* When the MIPS assembler sees -g or -g2, it does not do | |
9493 | optimizations which limit full symbolic debugging. We take | |
9494 | that to be equivalent to -O0. */ | |
9495 | if (mips_debug == 2) | |
05874c2e | 9496 | mips_optimize = 1; |
f3d817d8 | 9497 | break; |
4e95866e | 9498 | |
f3d817d8 | 9499 | case OPTION_MIPS1: |
3c83da8a | 9500 | mips_opts.isa = 1; |
f3d817d8 | 9501 | break; |
8358c818 | 9502 | |
f3d817d8 | 9503 | case OPTION_MIPS2: |
3c83da8a | 9504 | mips_opts.isa = 2; |
f3d817d8 | 9505 | break; |
8358c818 | 9506 | |
f3d817d8 | 9507 | case OPTION_MIPS3: |
3c83da8a | 9508 | mips_opts.isa = 3; |
f3d817d8 | 9509 | break; |
8358c818 | 9510 | |
d8a1c247 | 9511 | case OPTION_MIPS4: |
3c83da8a | 9512 | mips_opts.isa = 4; |
d8a1c247 KR |
9513 | break; |
9514 | ||
f3d817d8 DM |
9515 | case OPTION_MCPU: |
9516 | { | |
9517 | char *p; | |
9518 | ||
9519 | /* Identify the processor type */ | |
9520 | p = arg; | |
9521 | if (strcmp (p, "default") == 0 | |
9522 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 9523 | mips_cpu = -1; |
f3d817d8 DM |
9524 | else |
9525 | { | |
c625fc23 JSC |
9526 | int sv = 0; |
9527 | ||
9528 | /* We need to cope with the various "vr" prefixes for the 4300 | |
9529 | processor. */ | |
9530 | if (*p == 'v' || *p == 'V') | |
9531 | { | |
9532 | sv = 1; | |
9533 | p++; | |
9534 | } | |
9535 | ||
f3d817d8 DM |
9536 | if (*p == 'r' || *p == 'R') |
9537 | p++; | |
8358c818 | 9538 | |
4bb0cc41 | 9539 | mips_cpu = -1; |
f3d817d8 DM |
9540 | switch (*p) |
9541 | { | |
d8a1c247 KR |
9542 | case '1': |
9543 | if (strcmp (p, "10000") == 0 | |
9544 | || strcmp (p, "10k") == 0 | |
9545 | || strcmp (p, "10K") == 0) | |
9546 | mips_cpu = 10000; | |
4e96260f JL |
9547 | /* start-sanitize-tx19 */ |
9548 | else if (strcmp (p, "1900") == 0) | |
9549 | mips_cpu = 3900; | |
9550 | /* end-sanitize-tx19 */ | |
d8a1c247 KR |
9551 | break; |
9552 | ||
f3d817d8 DM |
9553 | case '2': |
9554 | if (strcmp (p, "2000") == 0 | |
9555 | || strcmp (p, "2k") == 0 | |
9556 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 9557 | mips_cpu = 2000; |
f3d817d8 | 9558 | break; |
8358c818 | 9559 | |
f3d817d8 DM |
9560 | case '3': |
9561 | if (strcmp (p, "3000") == 0 | |
9562 | || strcmp (p, "3k") == 0 | |
9563 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 9564 | mips_cpu = 3000; |
5c6f5923 GRK |
9565 | else if (strcmp (p, "3900") == 0) |
9566 | mips_cpu = 3900; | |
f3d817d8 | 9567 | break; |
8358c818 | 9568 | |
f3d817d8 DM |
9569 | case '4': |
9570 | if (strcmp (p, "4000") == 0 | |
9571 | || strcmp (p, "4k") == 0 | |
8c63448a | 9572 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 9573 | mips_cpu = 4000; |
c625fc23 | 9574 | else if (strcmp (p, "4100") == 0) |
c625fc23 | 9575 | mips_cpu = 4100; |
f14397f0 | 9576 | /* start-sanitize-vr4xxx */ |
3105a286 | 9577 | else if (strcmp (p, "4111") == 0) |
d95b7328 | 9578 | mips_cpu = 4111; |
f14397f0 GRK |
9579 | else if (strcmp (p, "4121") == 0) |
9580 | mips_cpu = 4121; | |
9581 | /* end-sanitize-vr4xxx */ | |
c625fc23 JSC |
9582 | else if (strcmp (p, "4300") == 0) |
9583 | mips_cpu = 4300; | |
2d035a50 GRK |
9584 | /* start-sanitize-vr4320 */ |
9585 | else if (strcmp (p, "4320") == 0) | |
9586 | mips_cpu = 4320; | |
9587 | /* end-sanitize-vr4320 */ | |
8c63448a | 9588 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 9589 | mips_cpu = 4400; |
8c63448a | 9590 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 9591 | mips_cpu = 4600; |
b2b8c24e | 9592 | else if (strcmp (p, "4650") == 0) |
b2b8c24e | 9593 | mips_cpu = 4650; |
4ebda395 GRK |
9594 | /* start-sanitize-tx49 */ |
9595 | else if (strcmp (p, "4900") == 0) | |
9596 | mips_cpu = 4900; | |
9597 | /* end-sanitize-tx49 */ | |
e532b44c | 9598 | else if (strcmp (p, "4010") == 0) |
1724c79e | 9599 | mips_cpu = 4010; |
f3d817d8 | 9600 | break; |
8358c818 | 9601 | |
517078c1 ILT |
9602 | case '5': |
9603 | if (strcmp (p, "5000") == 0 | |
9604 | || strcmp (p, "5k") == 0 | |
9605 | || strcmp (p, "5K") == 0) | |
9606 | mips_cpu = 5000; | |
6b34ac5a | 9607 | /* start-sanitize-cygnus */ |
aa2e0460 KR |
9608 | else if (strcmp (p, "5400") == 0) |
9609 | mips_cpu = 5400; | |
6b34ac5a | 9610 | /* end-sanitize-cygnus */ |
276c2d7d GRK |
9611 | /* start-sanitize-r5900 */ |
9612 | else if (strcmp (p, "5900") == 0) | |
9613 | mips_cpu = 5900; | |
9614 | /* end-sanitize-r5900 */ | |
517078c1 ILT |
9615 | break; |
9616 | ||
f3d817d8 DM |
9617 | case '6': |
9618 | if (strcmp (p, "6000") == 0 | |
9619 | || strcmp (p, "6k") == 0 | |
9620 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 9621 | mips_cpu = 6000; |
f3d817d8 | 9622 | break; |
55933a58 | 9623 | |
d8a1c247 KR |
9624 | case '8': |
9625 | if (strcmp (p, "8000") == 0 | |
9626 | || strcmp (p, "8k") == 0 | |
9627 | || strcmp (p, "8K") == 0) | |
9628 | mips_cpu = 8000; | |
9629 | break; | |
9630 | ||
55933a58 ILT |
9631 | case 'o': |
9632 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 9633 | mips_cpu = 4600; |
55933a58 | 9634 | break; |
f3d817d8 | 9635 | } |
8358c818 | 9636 | |
b3ed1af3 KR |
9637 | if (sv |
9638 | && (mips_cpu != 4300 | |
9639 | && mips_cpu != 4100 | |
f14397f0 | 9640 | /* start-sanitize-vr4xxx */ |
3105a286 | 9641 | && mips_cpu != 4111 |
f14397f0 GRK |
9642 | && mips_cpu != 4121 |
9643 | /* end-sanitize-vr4xxx */ | |
2d035a50 GRK |
9644 | /* start-sanitize-vr4320 */ |
9645 | && mips_cpu != 4320 | |
9646 | /* end-sanitize-vr4320 */ | |
6b34ac5a | 9647 | /* start-sanitize-cygnus */ |
b3ed1af3 | 9648 | && mips_cpu != 5400 |
6b34ac5a | 9649 | /* end-sanitize-cygnus */ |
b3ed1af3 | 9650 | && mips_cpu != 5000)) |
c625fc23 | 9651 | { |
48401fcf | 9652 | as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg); |
c625fc23 JSC |
9653 | return 0; |
9654 | } | |
9655 | ||
4bb0cc41 | 9656 | if (mips_cpu == -1) |
f3d817d8 | 9657 | { |
48401fcf | 9658 | as_bad (_("invalid architecture -mcpu=%s"), arg); |
f3d817d8 DM |
9659 | return 0; |
9660 | } | |
9661 | } | |
9662 | } | |
9663 | break; | |
8358c818 | 9664 | |
b2b8c24e | 9665 | case OPTION_M4650: |
de484a06 | 9666 | mips_cpu = 4650; |
b2b8c24e ILT |
9667 | break; |
9668 | ||
9669 | case OPTION_NO_M4650: | |
b2b8c24e ILT |
9670 | break; |
9671 | ||
e532b44c | 9672 | case OPTION_M4010: |
de484a06 | 9673 | mips_cpu = 4010; |
e532b44c ILT |
9674 | break; |
9675 | ||
9676 | case OPTION_NO_M4010: | |
e532b44c ILT |
9677 | break; |
9678 | ||
c625fc23 | 9679 | case OPTION_M4100: |
de484a06 | 9680 | mips_cpu = 4100; |
c625fc23 JSC |
9681 | break; |
9682 | ||
9683 | case OPTION_NO_M4100: | |
c625fc23 JSC |
9684 | break; |
9685 | ||
f14397f0 GRK |
9686 | /* start-sanitize-vr4xxx */ |
9687 | case OPTION_M4121: | |
de484a06 | 9688 | mips_cpu = 4121; |
f14397f0 GRK |
9689 | break; |
9690 | ||
9691 | case OPTION_NO_M4121: | |
f14397f0 GRK |
9692 | break; |
9693 | ||
9694 | /* end-sanitize-vr4xxx */ | |
276c2d7d GRK |
9695 | /* start-sanitize-r5900 */ |
9696 | case OPTION_M5900: | |
de484a06 | 9697 | mips_cpu = 5900; |
276c2d7d GRK |
9698 | break; |
9699 | ||
9700 | case OPTION_NO_M5900: | |
276c2d7d GRK |
9701 | break; |
9702 | /* end-sanitize-r5900 */ | |
9703 | ||
2d035a50 GRK |
9704 | /* start-sanitize-vr4320 */ |
9705 | case OPTION_M4320: | |
de484a06 | 9706 | mips_cpu = 4320; |
2d035a50 GRK |
9707 | break; |
9708 | ||
9709 | case OPTION_NO_M4320: | |
2d035a50 GRK |
9710 | break; |
9711 | ||
9712 | /* end-sanitize-vr4320 */ | |
6b34ac5a | 9713 | /* start-sanitize-cygnus */ |
aa2e0460 | 9714 | case OPTION_M5400: |
de484a06 | 9715 | mips_cpu = 5400; |
aa2e0460 KR |
9716 | break; |
9717 | ||
9718 | case OPTION_NO_M5400: | |
aa2e0460 KR |
9719 | break; |
9720 | ||
6b34ac5a | 9721 | /* end-sanitize-cygnus */ |
5c6f5923 | 9722 | case OPTION_M3900: |
de484a06 | 9723 | mips_cpu = 3900; |
5c6f5923 GRK |
9724 | break; |
9725 | ||
9726 | case OPTION_NO_M3900: | |
5c6f5923 GRK |
9727 | break; |
9728 | ||
42444087 GRK |
9729 | /* start-sanitize-tx49 */ |
9730 | case OPTION_M4900: | |
de484a06 | 9731 | mips_cpu = 4900; |
42444087 GRK |
9732 | break; |
9733 | ||
9734 | case OPTION_NO_M4900: | |
42444087 GRK |
9735 | break; |
9736 | ||
9737 | /* end-sanitize-tx49 */ | |
cc5703cd | 9738 | case OPTION_MIPS16: |
3c83da8a | 9739 | mips_opts.mips16 = 1; |
4a1cb507 | 9740 | mips_no_prev_insn (false); |
cc5703cd ILT |
9741 | break; |
9742 | ||
9743 | case OPTION_NO_MIPS16: | |
3c83da8a | 9744 | mips_opts.mips16 = 0; |
4a1cb507 | 9745 | mips_no_prev_insn (false); |
cc5703cd ILT |
9746 | break; |
9747 | ||
f3d817d8 | 9748 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 9749 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 9750 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 | 9751 | { |
48401fcf | 9752 | as_bad (_("-G may not be used with embedded PIC code")); |
f3d817d8 DM |
9753 | return 0; |
9754 | } | |
5b63f465 | 9755 | g_switch_value = 0x7fffffff; |
f3d817d8 | 9756 | break; |
d9aba805 | 9757 | |
fb251650 ILT |
9758 | /* When generating ELF code, we permit -KPIC and -call_shared to |
9759 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
9760 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 9761 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
9762 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
9763 | { | |
48401fcf | 9764 | as_bad (_("-call_shared is supported only for ELF format")); |
1dc1e798 KR |
9765 | return 0; |
9766 | } | |
d9aba805 ILT |
9767 | mips_pic = SVR4_PIC; |
9768 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 | 9769 | { |
48401fcf | 9770 | as_bad (_("-G may not be used with SVR4 PIC code")); |
f3d817d8 DM |
9771 | return 0; |
9772 | } | |
d9aba805 | 9773 | g_switch_value = 0; |
f3d817d8 DM |
9774 | break; |
9775 | ||
9776 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
9777 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
9778 | { | |
48401fcf | 9779 | as_bad (_("-non_shared is supported only for ELF format")); |
1dc1e798 KR |
9780 | return 0; |
9781 | } | |
d9aba805 | 9782 | mips_pic = NO_PIC; |
f3d817d8 | 9783 | break; |
8358c818 | 9784 | |
fb251650 ILT |
9785 | /* The -xgot option tells the assembler to use 32 offsets when |
9786 | accessing the got in SVR4_PIC mode. It is for Irix | |
9787 | compatibility. */ | |
9788 | case OPTION_XGOT: | |
9789 | mips_big_got = 1; | |
9790 | break; | |
9791 | ||
f3d817d8 | 9792 | case 'G': |
1dc1e798 KR |
9793 | if (! USE_GLOBAL_POINTER_OPT) |
9794 | { | |
48401fcf | 9795 | as_bad (_("-G is not supported for this configuration")); |
1dc1e798 KR |
9796 | return 0; |
9797 | } | |
9798 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 9799 | { |
48401fcf | 9800 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); |
f3d817d8 | 9801 | return 0; |
670a50eb ILT |
9802 | } |
9803 | else | |
f3d817d8 | 9804 | g_switch_value = atoi (arg); |
42562568 | 9805 | g_switch_seen = 1; |
f3d817d8 | 9806 | break; |
4e95866e | 9807 | |
7f9880e5 ILT |
9808 | /* The -32 and -64 options tell the assembler to output the 32 |
9809 | bit or the 64 bit MIPS ELF format. */ | |
9810 | case OPTION_32: | |
9811 | mips_64 = 0; | |
9812 | break; | |
9813 | ||
9814 | case OPTION_64: | |
9c44af60 ILT |
9815 | { |
9816 | const char **list, **l; | |
9817 | ||
9818 | list = bfd_target_list (); | |
9819 | for (l = list; *l != NULL; l++) | |
9820 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9821 | || strcmp (*l, "elf64-littlemips") == 0) | |
9822 | break; | |
9823 | if (*l == NULL) | |
48401fcf | 9824 | as_fatal (_("No compiled in support for 64 bit object file format")); |
9c44af60 ILT |
9825 | free (list); |
9826 | mips_64 = 1; | |
9827 | } | |
7f9880e5 ILT |
9828 | break; |
9829 | ||
7e656649 RH |
9830 | /* start-sanitize-branchbug4011 */ |
9831 | case OPTION_FIX_4011_BRANCH_BUG: | |
9832 | mips_fix_4011_branch_bug = 1; | |
9833 | break; | |
9834 | ||
9835 | case OPTION_NO_FIX_4011_BRANCH_BUG: | |
9836 | mips_fix_4011_branch_bug = 0; | |
9837 | break; | |
9838 | ||
9839 | /* end-sanitize-branchbug4011 */ | |
02650bd0 GRK |
9840 | |
9841 | case OPTION_MABI: | |
9842 | if (strcmp (arg,"32") == 0 | |
9843 | || strcmp (arg,"n32") == 0 | |
9844 | || strcmp (arg,"64") == 0 | |
9845 | || strcmp (arg,"o64") == 0 | |
9846 | || strcmp (arg,"eabi") == 0) | |
9847 | mips_abi_string = arg; | |
9848 | break; | |
9849 | ||
f3d817d8 DM |
9850 | default: |
9851 | return 0; | |
8ea7f4e8 ILT |
9852 | } |
9853 | ||
f3d817d8 | 9854 | return 1; |
8ea7f4e8 ILT |
9855 | } |
9856 | ||
de484a06 JB |
9857 | |
9858 | static void | |
9859 | show (stream, string, col_p, first_p) | |
9860 | FILE *stream; | |
9861 | char *string; | |
9862 | int *col_p; | |
9863 | int *first_p; | |
9864 | { | |
9865 | if (*first_p) | |
9866 | { | |
9867 | fprintf (stream, "%24s", ""); | |
9868 | *col_p = 24; | |
9869 | } | |
9870 | else | |
9871 | { | |
9872 | fprintf (stream, ", "); | |
9873 | *col_p += 2; | |
9874 | } | |
9875 | ||
9876 | if (*col_p + strlen (string) > 72) | |
9877 | { | |
9878 | fprintf (stream, "\n%24s", ""); | |
9879 | *col_p = 24; | |
9880 | } | |
9881 | ||
9882 | fprintf (stream, "%s", string); | |
9883 | *col_p += strlen (string); | |
9884 | ||
9885 | *first_p = 0; | |
9886 | } | |
9887 | ||
9888 | ||
f3d817d8 DM |
9889 | void |
9890 | md_show_usage (stream) | |
9891 | FILE *stream; | |
9892 | { | |
de484a06 JB |
9893 | int column, first; |
9894 | ||
48401fcf | 9895 | fprintf(stream, _("\ |
f3d817d8 DM |
9896 | MIPS options:\n\ |
9897 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
9898 | -EB generate big endian output\n\ |
9899 | -EL generate little endian output\n\ | |
9900 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
9901 | -G NUM allow referencing objects up to NUM bytes\n\ | |
48401fcf TT |
9902 | implicitly with the gp register [default 8]\n")); |
9903 | fprintf(stream, _("\ | |
31493cdf ILT |
9904 | -mips1 generate MIPS ISA I instructions\n\ |
9905 | -mips2 generate MIPS ISA II instructions\n\ | |
9906 | -mips3 generate MIPS ISA III instructions\n\ | |
9907 | -mips4 generate MIPS ISA IV instructions\n\ | |
de484a06 JB |
9908 | -mcpu=CPU generate code for CPU, where CPU is one of:\n")); |
9909 | ||
9910 | first = 1; | |
9911 | ||
9912 | /* start-sanitize-tx19 */ | |
9913 | show (stream, "1900", &column, &first); | |
9914 | /* end-sanitize-tx19 */ | |
9915 | show (stream, "2000", &column, &first); | |
9916 | show (stream, "3000", &column, &first); | |
9917 | show (stream, "3900", &column, &first); | |
9918 | show (stream, "4000", &column, &first); | |
9919 | show (stream, "4010", &column, &first); | |
9920 | show (stream, "4100", &column, &first); | |
f14397f0 | 9921 | /* start-sanitize-vr4xxx */ |
de484a06 JB |
9922 | show (stream, "4111", &column, &first); |
9923 | show (stream, "4121", &column, &first); | |
f14397f0 | 9924 | /* end-sanitize-vr4xxx */ |
de484a06 JB |
9925 | show (stream, "4300", &column, &first); |
9926 | /* start-sanitize-vr4320 */ | |
9927 | show (stream, "4320", &column, &first); | |
9928 | /* end-sanitize-vr4320 */ | |
9929 | show (stream, "4400", &column, &first); | |
9930 | show (stream, "4600", &column, &first); | |
9931 | show (stream, "4650", &column, &first); | |
9932 | /* start-sanitize-tx49 */ | |
9933 | show (stream, "4900", &column, &first); | |
9934 | /* end-sanitize-tx49 */ | |
9935 | show (stream, "5000", &column, &first); | |
9936 | /* start-sanitize-cygnus */ | |
9937 | show (stream, "5400", &column, &first); | |
9938 | /* end-sanitize-cygnus */ | |
9939 | /* start-sanitize-r5900 */ | |
9940 | show (stream, "5900", &column, &first); | |
9941 | /* end-sanitize-r5900 */ | |
9942 | show (stream, "6000", &column, &first); | |
9943 | show (stream, "8000", &column, &first); | |
9944 | show (stream, "10000", &column, &first); | |
9945 | fputc ('\n', stream); | |
9946 | ||
9947 | fprintf (stream, _("\ | |
9948 | -mCPU equivalent to -mcpu=CPU.\n\ | |
9949 | -no-mCPU don't generate code for CPU.\n\ | |
9950 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
9951 | ||
9952 | first = 1; | |
9953 | ||
9954 | /* start-sanitize-tx19 */ | |
9955 | show (stream, "1900", &column, &first); | |
9956 | /* end-sanitize-tx19 */ | |
9957 | show (stream, "3900", &column, &first); | |
9958 | show (stream, "4010", &column, &first); | |
9959 | show (stream, "4100", &column, &first); | |
9960 | /* start-sanitize-vr4xxx */ | |
9961 | show (stream, "4121", &column, &first); | |
9962 | /* end-sanitize-vr4xxx */ | |
9963 | /* start-sanitize-vr4320 */ | |
9964 | show (stream, "4320", &column, &first); | |
9965 | /* end-sanitize-vr4320 */ | |
9966 | show (stream, "4650", &column, &first); | |
9967 | /* start-sanitize-tx49 */ | |
9968 | show (stream, "4900", &column, &first); | |
9969 | /* end-sanitize-tx49 */ | |
9970 | /* start-sanitize-cygnus */ | |
9971 | show (stream, "5400", &column, &first); | |
9972 | /* end-sanitize-cygnus */ | |
9973 | /* start-sanitize-r5900 */ | |
9974 | show (stream, "5900", &column, &first); | |
9975 | /* end-sanitize-r5900 */ | |
9976 | fputc ('\n', stream); | |
9977 | ||
48401fcf | 9978 | fprintf(stream, _("\ |
cc5703cd | 9979 | -mips16 generate mips16 instructions\n\ |
48401fcf TT |
9980 | -no-mips16 do not generate mips16 instructions\n")); |
9981 | fprintf(stream, _("\ | |
f3d817d8 DM |
9982 | -O0 remove unneeded NOPs, do not swap branches\n\ |
9983 | -O remove unneeded NOPs and swap branches\n\ | |
9984 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
48401fcf | 9985 | --break, --no-trap break exception on div by 0 and mult overflow\n")); |
f3d817d8 | 9986 | #ifdef OBJ_ELF |
48401fcf | 9987 | fprintf(stream, _("\ |
f3d817d8 | 9988 | -KPIC, -call_shared generate SVR4 position independent code\n\ |
fb251650 | 9989 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
9990 | -xgot assume a 32 bit GOT\n\ |
9991 | -32 create 32 bit object file (default)\n\ | |
48401fcf | 9992 | -64 create 64 bit object file\n")); |
f3d817d8 DM |
9993 | #endif |
9994 | } | |
9995 | \f | |
efec4a28 DP |
9996 | void |
9997 | mips_init_after_args () | |
9998 | { | |
af942793 SS |
9999 | /* initialize opcodes */ |
10000 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
10001 | mips_opcodes = (struct mips_opcode*) mips_builtin_opcodes; | |
efec4a28 DP |
10002 | } |
10003 | ||
3d3c5039 ILT |
10004 | long |
10005 | md_pcrel_from (fixP) | |
10006 | fixS *fixP; | |
10007 | { | |
1dc1e798 KR |
10008 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
10009 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
10010 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
10011 | { | |
10012 | /* This makes a branch to an undefined symbol be a branch to the | |
10013 | current location. */ | |
10014 | return 4; | |
10015 | } | |
5b63f465 | 10016 | |
670a50eb ILT |
10017 | /* return the address of the delay slot */ |
10018 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
10019 | } |
10020 | ||
abdad6bc ILT |
10021 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
10022 | reloc for a cons. We could use the definition there, except that | |
10023 | we want to handle 64 bit relocs specially. */ | |
10024 | ||
10025 | void | |
10026 | cons_fix_new_mips (frag, where, nbytes, exp) | |
10027 | fragS *frag; | |
10028 | int where; | |
10029 | unsigned int nbytes; | |
10030 | expressionS *exp; | |
10031 | { | |
bf39474f | 10032 | #ifndef OBJ_ELF |
abdad6bc | 10033 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
10034 | 4 byte reloc. */ |
10035 | if (nbytes == 8 && ! mips_64) | |
abdad6bc | 10036 | { |
b9129c6f | 10037 | if (target_big_endian) |
abdad6bc ILT |
10038 | where += 4; |
10039 | nbytes = 4; | |
10040 | } | |
bf39474f | 10041 | #endif |
abdad6bc | 10042 | |
7f9880e5 | 10043 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
48401fcf | 10044 | as_bad (_("Unsupported reloc size %d"), nbytes); |
abdad6bc ILT |
10045 | |
10046 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
10047 | (nbytes == 2 |
10048 | ? BFD_RELOC_16 | |
10049 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
10050 | } |
10051 | ||
23604921 ILT |
10052 | /* This is called before the symbol table is processed. In order to |
10053 | work with gcc when using mips-tfile, we must keep all local labels. | |
10054 | However, in other cases, we want to discard them. If we were | |
10055 | called with -g, but we didn't see any debugging information, it may | |
10056 | mean that gcc is smuggling debugging information through to | |
10057 | mips-tfile, in which case we must generate all local labels. */ | |
10058 | ||
10059 | void | |
10060 | mips_frob_file_before_adjust () | |
10061 | { | |
10062 | #ifndef NO_ECOFF_DEBUGGING | |
10063 | if (ECOFF_DEBUGGING | |
10064 | && mips_debug != 0 | |
10065 | && ! ecoff_debugging_seen) | |
10066 | flag_keep_locals = 1; | |
10067 | #endif | |
10068 | } | |
10069 | ||
867a58b3 ILT |
10070 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
10071 | the corresponding LO reloc. This is called before md_apply_fix and | |
10072 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
10073 | explicit use of the %hi modifier. */ | |
10074 | ||
10075 | void | |
10076 | mips_frob_file () | |
10077 | { | |
10078 | struct mips_hi_fixup *l; | |
10079 | ||
10080 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10081 | { | |
10082 | segment_info_type *seginfo; | |
9b61d62b | 10083 | int pass; |
867a58b3 ILT |
10084 | |
10085 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
10086 | ||
10087 | /* Check quickly whether the next fixup happens to be a matching | |
10088 | %lo. */ | |
10089 | if (l->fixp->fx_next != NULL | |
10090 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
10091 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
10092 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
10093 | continue; | |
10094 | ||
10095 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
10096 | When we find one, move the %hi just in front of it. We do |
10097 | this in two passes. In the first pass, we try to find a | |
10098 | unique %lo. In the second pass, we permit multiple %hi | |
10099 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 10100 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
10101 | for (pass = 0; pass < 2; pass++) |
10102 | { | |
10103 | fixS *f, *prev; | |
10104 | ||
10105 | prev = NULL; | |
10106 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 10107 | { |
9b61d62b ILT |
10108 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
10109 | if (f->fx_r_type == BFD_RELOC_LO16 | |
10110 | && f->fx_addsy == l->fixp->fx_addsy | |
10111 | && f->fx_offset == l->fixp->fx_offset | |
10112 | && (pass == 1 | |
10113 | || prev == NULL | |
10114 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
10115 | || prev->fx_addsy != f->fx_addsy | |
10116 | || prev->fx_offset != f->fx_offset)) | |
10117 | { | |
10118 | fixS **pf; | |
867a58b3 | 10119 | |
9b61d62b ILT |
10120 | /* Move l->fixp before f. */ |
10121 | for (pf = &seginfo->fix_root; | |
10122 | *pf != l->fixp; | |
10123 | pf = &(*pf)->fx_next) | |
10124 | assert (*pf != NULL); | |
867a58b3 | 10125 | |
9b61d62b | 10126 | *pf = l->fixp->fx_next; |
867a58b3 | 10127 | |
9b61d62b ILT |
10128 | l->fixp->fx_next = f; |
10129 | if (prev == NULL) | |
10130 | seginfo->fix_root = l->fixp; | |
10131 | else | |
10132 | prev->fx_next = l->fixp; | |
867a58b3 | 10133 | |
9b61d62b ILT |
10134 | break; |
10135 | } | |
10136 | ||
10137 | prev = f; | |
867a58b3 ILT |
10138 | } |
10139 | ||
9b61d62b ILT |
10140 | if (f != NULL) |
10141 | break; | |
867a58b3 | 10142 | |
de484a06 JB |
10143 | #if 0 /* GCC code motion plus incomplete dead code elimination |
10144 | can leave a %hi without a %lo. */ | |
9b61d62b ILT |
10145 | if (pass == 1) |
10146 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
48401fcf | 10147 | _("Unmatched %%hi reloc")); |
de484a06 | 10148 | #endif |
9b61d62b | 10149 | } |
867a58b3 ILT |
10150 | } |
10151 | } | |
10152 | ||
1c803e52 ILT |
10153 | /* When generating embedded PIC code we need to use a special |
10154 | relocation to represent the difference of two symbols in the .text | |
10155 | section (switch tables use a difference of this sort). See | |
10156 | include/coff/mips.h for details. This macro checks whether this | |
10157 | fixup requires the special reloc. */ | |
10158 | #define SWITCH_TABLE(fixp) \ | |
10159 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
10160 | && (fixp)->fx_addsy != NULL \ | |
10161 | && (fixp)->fx_subsy != NULL \ | |
10162 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
10163 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
10164 | ||
5b63f465 | 10165 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
10166 | relocations, in case the linker has to relax a call. We also need |
10167 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
10168 | |
10169 | /*ARGSUSED*/ | |
10170 | int | |
10171 | mips_force_relocation (fixp) | |
10172 | fixS *fixp; | |
10173 | { | |
7e656649 RH |
10174 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
10175 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
10176 | return 1; | |
10177 | ||
1c803e52 | 10178 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
10179 | && (fixp->fx_pcrel |
10180 | || SWITCH_TABLE (fixp) | |
10181 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
10182 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
10183 | } |
10184 | ||
10185 | /* Apply a fixup to the object file. */ | |
10186 | ||
3d3c5039 ILT |
10187 | int |
10188 | md_apply_fix (fixP, valueP) | |
10189 | fixS *fixP; | |
918692a5 | 10190 | valueT *valueP; |
3d3c5039 | 10191 | { |
670a50eb ILT |
10192 | unsigned char *buf; |
10193 | long insn, value; | |
3d3c5039 | 10194 | |
bf39474f ILT |
10195 | assert (fixP->fx_size == 4 |
10196 | || fixP->fx_r_type == BFD_RELOC_16 | |
7e656649 RH |
10197 | || fixP->fx_r_type == BFD_RELOC_64 |
10198 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
10199 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); | |
3d3c5039 | 10200 | |
670a50eb | 10201 | value = *valueP; |
1748b9d8 ILT |
10202 | |
10203 | /* If we aren't adjusting this fixup to be against the section | |
10204 | symbol, we need to adjust the value. */ | |
68952421 | 10205 | #ifdef OBJ_ELF |
1748b9d8 | 10206 | if (fixP->fx_addsy != NULL |
1748b9d8 | 10207 | && OUTPUT_FLAVOR == bfd_target_elf_flavour |
622b1860 ILT |
10208 | && (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16 |
10209 | || S_IS_WEAK (fixP->fx_addsy))) | |
1748b9d8 ILT |
10210 | { |
10211 | value -= S_GET_VALUE (fixP->fx_addsy); | |
10212 | if (value != 0 && ! fixP->fx_pcrel) | |
10213 | { | |
10214 | /* In this case, the bfd_install_relocation routine will | |
10215 | incorrectly add the symbol value back in. We just want | |
10216 | the addend to appear in the object file. */ | |
10217 | value -= S_GET_VALUE (fixP->fx_addsy); | |
10218 | } | |
10219 | } | |
10220 | #endif | |
10221 | ||
670a50eb | 10222 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ |
3d3c5039 | 10223 | |
5b63f465 ILT |
10224 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
10225 | fixP->fx_done = 1; | |
10226 | ||
670a50eb ILT |
10227 | switch (fixP->fx_r_type) |
10228 | { | |
3d3c5039 ILT |
10229 | case BFD_RELOC_MIPS_JMP: |
10230 | case BFD_RELOC_HI16: | |
10231 | case BFD_RELOC_HI16_S: | |
670a50eb | 10232 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
10233 | case BFD_RELOC_MIPS_LITERAL: |
10234 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
10235 | case BFD_RELOC_MIPS_GOT16: |
10236 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
10237 | case BFD_RELOC_MIPS_GOT_HI16: |
10238 | case BFD_RELOC_MIPS_GOT_LO16: | |
10239 | case BFD_RELOC_MIPS_CALL_HI16: | |
10240 | case BFD_RELOC_MIPS_CALL_LO16: | |
16262668 | 10241 | case BFD_RELOC_MIPS16_GPREL: |
0bc0e337 JL |
10242 | /* start-sanitize-r5900 */ |
10243 | case BFD_RELOC_MIPS15_S3: | |
10244 | /* end-sanitize-r5900 */ | |
ecd4ca1c | 10245 | if (fixP->fx_pcrel) |
7b777690 | 10246 | as_bad_where (fixP->fx_file, fixP->fx_line, |
48401fcf | 10247 | _("Invalid PC relative reloc")); |
670a50eb | 10248 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 10249 | break; |
3d3c5039 | 10250 | |
cc5703cd ILT |
10251 | case BFD_RELOC_MIPS16_JMP: |
10252 | /* We currently always generate a reloc against a symbol, which | |
10253 | means that we don't want an addend even if the symbol is | |
10254 | defined. */ | |
10255 | fixP->fx_addnumber = 0; | |
10256 | break; | |
10257 | ||
ecd4ca1c ILT |
10258 | case BFD_RELOC_PCREL_HI16_S: |
10259 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 10260 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
10261 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
10262 | { | |
10263 | /* For an external symbol adjust by the address to make it | |
10264 | pcrel_offset. We use the address of the RELLO reloc | |
10265 | which follows this one. */ | |
10266 | value += (fixP->fx_next->fx_frag->fr_address | |
10267 | + fixP->fx_next->fx_where); | |
10268 | } | |
10269 | if (value & 0x8000) | |
10270 | value += 0x10000; | |
10271 | value >>= 16; | |
0221ddf7 | 10272 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 10273 | if (target_big_endian) |
ecd4ca1c ILT |
10274 | buf += 2; |
10275 | md_number_to_chars (buf, value, 2); | |
10276 | break; | |
10277 | ||
10278 | case BFD_RELOC_PCREL_LO16: | |
10279 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 10280 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
10281 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
10282 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 10283 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 10284 | if (target_big_endian) |
ecd4ca1c ILT |
10285 | buf += 2; |
10286 | md_number_to_chars (buf, value, 2); | |
10287 | break; | |
10288 | ||
bf39474f ILT |
10289 | case BFD_RELOC_64: |
10290 | /* This is handled like BFD_RELOC_32, but we output a sign | |
10291 | extended value if we are only 32 bits. */ | |
10292 | if (fixP->fx_done | |
10293 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
10294 | { | |
10295 | if (8 <= sizeof (valueT)) | |
10296 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10297 | value, 8); | |
10298 | else | |
10299 | { | |
10300 | long w1, w2; | |
10301 | long hiv; | |
10302 | ||
10303 | w1 = w2 = fixP->fx_where; | |
b9129c6f | 10304 | if (target_big_endian) |
bf39474f ILT |
10305 | w1 += 4; |
10306 | else | |
10307 | w2 += 4; | |
10308 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
10309 | if ((value & 0x80000000) != 0) | |
10310 | hiv = 0xffffffff; | |
10311 | else | |
10312 | hiv = 0; | |
10313 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
10314 | } | |
10315 | } | |
10316 | break; | |
10317 | ||
f3645945 ILT |
10318 | case BFD_RELOC_32: |
10319 | /* If we are deleting this reloc entry, we must fill in the | |
10320 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
10321 | resolved when it appears but is later defined. We also need |
10322 | to fill in the value if this is an embedded PIC switch table | |
10323 | entry. */ | |
10324 | if (fixP->fx_done | |
10325 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
10326 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
10327 | value, 4); | |
10328 | break; | |
10329 | ||
49ad0c4c ILT |
10330 | case BFD_RELOC_16: |
10331 | /* If we are deleting this reloc entry, we must fill in the | |
10332 | value now. */ | |
10333 | assert (fixP->fx_size == 2); | |
10334 | if (fixP->fx_done) | |
10335 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10336 | value, 2); | |
10337 | break; | |
10338 | ||
f3645945 ILT |
10339 | case BFD_RELOC_LO16: |
10340 | /* When handling an embedded PIC switch statement, we can wind | |
10341 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
10342 | if (fixP->fx_done) | |
10343 | { | |
10344 | if (value < -0x8000 || value > 0x7fff) | |
10345 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
48401fcf | 10346 | _("relocation overflow")); |
0221ddf7 | 10347 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 10348 | if (target_big_endian) |
f3645945 ILT |
10349 | buf += 2; |
10350 | md_number_to_chars (buf, value, 2); | |
10351 | } | |
10352 | break; | |
10353 | ||
3d3c5039 | 10354 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
10355 | /* |
10356 | * We need to save the bits in the instruction since fixup_segment() | |
10357 | * might be deleting the relocation entry (i.e., a branch within | |
10358 | * the current segment). | |
10359 | */ | |
fbcfacb7 | 10360 | if ((value & 0x3) != 0) |
3b320c48 | 10361 | as_bad_where (fixP->fx_file, fixP->fx_line, |
48401fcf | 10362 | _("Branch to odd address (%lx)"), value); |
670a50eb | 10363 | value >>= 2; |
670a50eb ILT |
10364 | |
10365 | /* update old instruction data */ | |
10366 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
b9129c6f ILT |
10367 | if (target_big_endian) |
10368 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
10369 | else | |
10370 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9da4c5d1 ILT |
10371 | |
10372 | if (value >= -0x8000 && value < 0x8000) | |
10373 | insn |= value & 0xffff; | |
10374 | else | |
10375 | { | |
10376 | /* The branch offset is too large. If this is an | |
10377 | unconditional branch, and we are not generating PIC code, | |
10378 | we can convert it to an absolute jump instruction. */ | |
10379 | if (mips_pic == NO_PIC | |
10380 | && fixP->fx_done | |
10381 | && fixP->fx_frag->fr_address >= text_section->vma | |
10382 | && (fixP->fx_frag->fr_address | |
10383 | < text_section->vma + text_section->_raw_size) | |
10384 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
10385 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
10386 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
10387 | { | |
10388 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
10389 | insn = 0x0c000000; /* jal */ | |
10390 | else | |
10391 | insn = 0x08000000; /* j */ | |
10392 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
10393 | fixP->fx_done = 0; | |
10394 | fixP->fx_addsy = section_symbol (text_section); | |
10395 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
10396 | } | |
10397 | else | |
10398 | { | |
10399 | /* FIXME. It would be possible in principle to handle | |
10400 | conditional branches which overflow. They could be | |
10401 | transformed into a branch around a jump. This would | |
10402 | require setting up variant frags for each different | |
10403 | branch type. The native MIPS assembler attempts to | |
10404 | handle these cases, but it appears to do it | |
10405 | incorrectly. */ | |
10406 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
48401fcf | 10407 | _("Branch out of range")); |
9da4c5d1 ILT |
10408 | } |
10409 | } | |
10410 | ||
604633ae | 10411 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 10412 | break; |
3d3c5039 | 10413 | |
7e656649 RH |
10414 | case BFD_RELOC_VTABLE_INHERIT: |
10415 | fixP->fx_done = 0; | |
10416 | if (fixP->fx_addsy | |
10417 | && !S_IS_DEFINED (fixP->fx_addsy) | |
10418 | && !S_IS_WEAK (fixP->fx_addsy)) | |
10419 | S_SET_WEAK (fixP->fx_addsy); | |
10420 | break; | |
10421 | ||
10422 | case BFD_RELOC_VTABLE_ENTRY: | |
10423 | fixP->fx_done = 0; | |
10424 | break; | |
10425 | ||
3d3c5039 | 10426 | default: |
670a50eb | 10427 | internalError (); |
3d3c5039 | 10428 | } |
5b63f465 | 10429 | |
670a50eb | 10430 | return 1; |
3d3c5039 ILT |
10431 | } |
10432 | ||
10433 | #if 0 | |
10434 | void | |
670a50eb ILT |
10435 | printInsn (oc) |
10436 | unsigned long oc; | |
3d3c5039 | 10437 | { |
670a50eb ILT |
10438 | const struct mips_opcode *p; |
10439 | int treg, sreg, dreg, shamt; | |
10440 | short imm; | |
10441 | const char *args; | |
10442 | int i; | |
3d3c5039 | 10443 | |
670a50eb ILT |
10444 | for (i = 0; i < NUMOPCODES; ++i) |
10445 | { | |
10446 | p = &mips_opcodes[i]; | |
10447 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
10448 | { | |
10449 | printf ("%08lx %s\t", oc, p->name); | |
10450 | treg = (oc >> 16) & 0x1f; | |
10451 | sreg = (oc >> 21) & 0x1f; | |
10452 | dreg = (oc >> 11) & 0x1f; | |
10453 | shamt = (oc >> 6) & 0x1f; | |
10454 | imm = oc; | |
10455 | for (args = p->args;; ++args) | |
10456 | { | |
10457 | switch (*args) | |
10458 | { | |
3d3c5039 | 10459 | case '\0': |
670a50eb ILT |
10460 | printf ("\n"); |
10461 | break; | |
3d3c5039 ILT |
10462 | |
10463 | case ',': | |
10464 | case '(': | |
10465 | case ')': | |
670a50eb ILT |
10466 | printf ("%c", *args); |
10467 | continue; | |
3d3c5039 ILT |
10468 | |
10469 | case 'r': | |
670a50eb ILT |
10470 | assert (treg == sreg); |
10471 | printf ("$%d,$%d", treg, sreg); | |
10472 | continue; | |
3d3c5039 ILT |
10473 | |
10474 | case 'd': | |
918692a5 | 10475 | case 'G': |
670a50eb ILT |
10476 | printf ("$%d", dreg); |
10477 | continue; | |
3d3c5039 ILT |
10478 | |
10479 | case 't': | |
918692a5 | 10480 | case 'E': |
670a50eb ILT |
10481 | printf ("$%d", treg); |
10482 | continue; | |
3d3c5039 | 10483 | |
9226253a ILT |
10484 | case 'k': |
10485 | printf ("0x%x", treg); | |
10486 | continue; | |
10487 | ||
3d3c5039 ILT |
10488 | case 'b': |
10489 | case 's': | |
670a50eb ILT |
10490 | printf ("$%d", sreg); |
10491 | continue; | |
3d3c5039 ILT |
10492 | |
10493 | case 'a': | |
670a50eb ILT |
10494 | printf ("0x%08lx", oc & 0x1ffffff); |
10495 | continue; | |
3d3c5039 ILT |
10496 | |
10497 | case 'i': | |
10498 | case 'j': | |
10499 | case 'o': | |
10500 | case 'u': | |
670a50eb ILT |
10501 | printf ("%d", imm); |
10502 | continue; | |
3d3c5039 ILT |
10503 | |
10504 | case '<': | |
56c96faa | 10505 | case '>': |
670a50eb ILT |
10506 | printf ("$%d", shamt); |
10507 | continue; | |
3d3c5039 ILT |
10508 | |
10509 | default: | |
670a50eb | 10510 | internalError (); |
3d3c5039 | 10511 | } |
670a50eb | 10512 | break; |
3d3c5039 | 10513 | } |
670a50eb | 10514 | return; |
3d3c5039 ILT |
10515 | } |
10516 | } | |
48401fcf | 10517 | printf (_("%08lx UNDEFINED\n"), oc); |
3d3c5039 ILT |
10518 | } |
10519 | #endif | |
10520 | ||
10521 | static symbolS * | |
10522 | get_symbol () | |
10523 | { | |
670a50eb ILT |
10524 | int c; |
10525 | char *name; | |
10526 | symbolS *p; | |
10527 | ||
10528 | name = input_line_pointer; | |
10529 | c = get_symbol_end (); | |
10530 | p = (symbolS *) symbol_find_or_make (name); | |
10531 | *input_line_pointer = c; | |
10532 | return p; | |
3d3c5039 ILT |
10533 | } |
10534 | ||
becfe05e ILT |
10535 | /* Align the current frag to a given power of two. The MIPS assembler |
10536 | also automatically adjusts any preceding label. */ | |
10537 | ||
10538 | static void | |
23dc1ae3 | 10539 | mips_align (to, fill, label) |
becfe05e ILT |
10540 | int to; |
10541 | int fill; | |
23dc1ae3 | 10542 | symbolS *label; |
becfe05e | 10543 | { |
fbcfacb7 | 10544 | mips_emit_delays (false); |
e2e5acfa | 10545 | frag_align (to, fill, 0); |
becfe05e | 10546 | record_alignment (now_seg, to); |
23dc1ae3 | 10547 | if (label != NULL) |
becfe05e | 10548 | { |
23dc1ae3 ILT |
10549 | assert (S_GET_SEGMENT (label) == now_seg); |
10550 | label->sy_frag = frag_now; | |
10551 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
10552 | } |
10553 | } | |
10554 | ||
10555 | /* Align to a given power of two. .align 0 turns off the automatic | |
10556 | alignment used by the data creating pseudo-ops. */ | |
10557 | ||
3d3c5039 ILT |
10558 | static void |
10559 | s_align (x) | |
10560 | int x; | |
10561 | { | |
670a50eb ILT |
10562 | register int temp; |
10563 | register long temp_fill; | |
10564 | long max_alignment = 15; | |
3d3c5039 | 10565 | |
670a50eb | 10566 | /* |
3d3c5039 ILT |
10567 | |
10568 | o Note that the assembler pulls down any immediately preceeding label | |
10569 | to the aligned address. | |
10570 | o It's not documented but auto alignment is reinstated by | |
10571 | a .align pseudo instruction. | |
10572 | o Note also that after auto alignment is turned off the mips assembler | |
10573 | issues an error on attempt to assemble an improperly aligned data item. | |
10574 | We don't. | |
10575 | ||
10576 | */ | |
10577 | ||
670a50eb ILT |
10578 | temp = get_absolute_expression (); |
10579 | if (temp > max_alignment) | |
48401fcf | 10580 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); |
670a50eb ILT |
10581 | else if (temp < 0) |
10582 | { | |
48401fcf | 10583 | as_warn (_("Alignment negative: 0 assumed.")); |
670a50eb ILT |
10584 | temp = 0; |
10585 | } | |
10586 | if (*input_line_pointer == ',') | |
10587 | { | |
10588 | input_line_pointer++; | |
10589 | temp_fill = get_absolute_expression (); | |
10590 | } | |
10591 | else | |
10592 | temp_fill = 0; | |
10593 | if (temp) | |
10594 | { | |
10595 | auto_align = 1; | |
fbcfacb7 ILT |
10596 | mips_align (temp, (int) temp_fill, |
10597 | insn_labels != NULL ? insn_labels->label : NULL); | |
3d3c5039 | 10598 | } |
670a50eb ILT |
10599 | else |
10600 | { | |
10601 | auto_align = 0; | |
3d3c5039 ILT |
10602 | } |
10603 | ||
670a50eb | 10604 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10605 | } |
10606 | ||
739708fa KR |
10607 | void |
10608 | mips_flush_pending_output () | |
becfe05e | 10609 | { |
fbcfacb7 ILT |
10610 | mips_emit_delays (false); |
10611 | mips_clear_insn_labels (); | |
becfe05e ILT |
10612 | } |
10613 | ||
3d3c5039 ILT |
10614 | static void |
10615 | s_change_sec (sec) | |
10616 | int sec; | |
10617 | { | |
88225433 | 10618 | segT seg; |
becfe05e | 10619 | |
5b63f465 ILT |
10620 | /* When generating embedded PIC code, we only use the .text, .lit8, |
10621 | .sdata and .sbss sections. We change the .data and .rdata | |
10622 | pseudo-ops to use .sdata. */ | |
10623 | if (mips_pic == EMBEDDED_PIC | |
10624 | && (sec == 'd' || sec == 'r')) | |
10625 | sec = 's'; | |
10626 | ||
acdc7ce3 ILT |
10627 | #ifdef OBJ_ELF |
10628 | /* The ELF backend needs to know that we are changing sections, so | |
10629 | that .previous works correctly. We could do something like check | |
10630 | for a obj_section_change_hook macro, but that might be confusing | |
10631 | as it would not be appropriate to use it in the section changing | |
10632 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
10633 | This should be cleaner, somehow. */ | |
10634 | obj_elf_section_change_hook (); | |
10635 | #endif | |
10636 | ||
fbcfacb7 | 10637 | mips_emit_delays (false); |
670a50eb ILT |
10638 | switch (sec) |
10639 | { | |
3d3c5039 | 10640 | case 't': |
604633ae | 10641 | s_text (0); |
670a50eb | 10642 | break; |
3d3c5039 | 10643 | case 'd': |
604633ae | 10644 | s_data (0); |
670a50eb | 10645 | break; |
3d3c5039 | 10646 | case 'b': |
670a50eb | 10647 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
10648 | demand_empty_rest_of_line (); |
10649 | break; | |
88225433 ILT |
10650 | |
10651 | case 'r': | |
1dc1e798 KR |
10652 | if (USE_GLOBAL_POINTER_OPT) |
10653 | { | |
10654 | seg = subseg_new (RDATA_SECTION_NAME, | |
10655 | (subsegT) get_absolute_expression ()); | |
10656 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10657 | { | |
10658 | bfd_set_section_flags (stdoutput, seg, | |
10659 | (SEC_ALLOC | |
10660 | | SEC_LOAD | |
10661 | | SEC_READONLY | |
10662 | | SEC_RELOC | |
10663 | | SEC_DATA)); | |
08e17202 ILT |
10664 | if (strcmp (TARGET_OS, "elf") != 0) |
10665 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
10666 | } |
10667 | demand_empty_rest_of_line (); | |
10668 | } | |
10669 | else | |
10670 | { | |
48401fcf | 10671 | as_bad (_("No read only data section in this object file format")); |
1dc1e798 KR |
10672 | demand_empty_rest_of_line (); |
10673 | return; | |
10674 | } | |
88225433 | 10675 | break; |
88225433 ILT |
10676 | |
10677 | case 's': | |
1dc1e798 KR |
10678 | if (USE_GLOBAL_POINTER_OPT) |
10679 | { | |
10680 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
10681 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10682 | { | |
10683 | bfd_set_section_flags (stdoutput, seg, | |
10684 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
10685 | | SEC_DATA); | |
08e17202 ILT |
10686 | if (strcmp (TARGET_OS, "elf") != 0) |
10687 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
10688 | } |
10689 | demand_empty_rest_of_line (); | |
10690 | break; | |
10691 | } | |
10692 | else | |
10693 | { | |
48401fcf | 10694 | as_bad (_("Global pointers not supported; recompile -G 0")); |
1dc1e798 KR |
10695 | demand_empty_rest_of_line (); |
10696 | return; | |
10697 | } | |
3d3c5039 | 10698 | } |
88225433 | 10699 | |
670a50eb | 10700 | auto_align = 1; |
3d3c5039 ILT |
10701 | } |
10702 | ||
739708fa KR |
10703 | void |
10704 | mips_enable_auto_align () | |
9da4c5d1 | 10705 | { |
9da4c5d1 ILT |
10706 | auto_align = 1; |
10707 | } | |
10708 | ||
3d3c5039 ILT |
10709 | static void |
10710 | s_cons (log_size) | |
10711 | int log_size; | |
10712 | { | |
23dc1ae3 ILT |
10713 | symbolS *label; |
10714 | ||
fbcfacb7 ILT |
10715 | label = insn_labels != NULL ? insn_labels->label : NULL; |
10716 | mips_emit_delays (false); | |
670a50eb | 10717 | if (log_size > 0 && auto_align) |
23dc1ae3 | 10718 | mips_align (log_size, 0, label); |
fbcfacb7 | 10719 | mips_clear_insn_labels (); |
670a50eb | 10720 | cons (1 << log_size); |
3d3c5039 ILT |
10721 | } |
10722 | ||
3d3c5039 | 10723 | static void |
becfe05e ILT |
10724 | s_float_cons (type) |
10725 | int type; | |
3d3c5039 | 10726 | { |
23dc1ae3 ILT |
10727 | symbolS *label; |
10728 | ||
fbcfacb7 | 10729 | label = insn_labels != NULL ? insn_labels->label : NULL; |
23dc1ae3 | 10730 | |
fbcfacb7 | 10731 | mips_emit_delays (false); |
670a50eb ILT |
10732 | |
10733 | if (auto_align) | |
becfe05e | 10734 | if (type == 'd') |
23dc1ae3 | 10735 | mips_align (3, 0, label); |
670a50eb | 10736 | else |
23dc1ae3 | 10737 | mips_align (2, 0, label); |
670a50eb | 10738 | |
fbcfacb7 | 10739 | mips_clear_insn_labels (); |
1849d646 | 10740 | |
becfe05e | 10741 | float_cons (type); |
3d3c5039 ILT |
10742 | } |
10743 | ||
c1444ec4 ILT |
10744 | /* Handle .globl. We need to override it because on Irix 5 you are |
10745 | permitted to say | |
10746 | .globl foo .text | |
10747 | where foo is an undefined symbol, to mean that foo should be | |
10748 | considered to be the address of a function. */ | |
10749 | ||
10750 | static void | |
10751 | s_mips_globl (x) | |
10752 | int x; | |
10753 | { | |
10754 | char *name; | |
10755 | int c; | |
10756 | symbolS *symbolP; | |
fb251650 | 10757 | flagword flag; |
c1444ec4 ILT |
10758 | |
10759 | name = input_line_pointer; | |
10760 | c = get_symbol_end (); | |
10761 | symbolP = symbol_find_or_make (name); | |
10762 | *input_line_pointer = c; | |
10763 | SKIP_WHITESPACE (); | |
fb251650 ILT |
10764 | |
10765 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
10766 | being a function is apparently labelled as being an object. */ | |
10767 | flag = BSF_OBJECT; | |
10768 | ||
c1444ec4 ILT |
10769 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
10770 | { | |
10771 | char *secname; | |
10772 | asection *sec; | |
10773 | ||
10774 | secname = input_line_pointer; | |
10775 | c = get_symbol_end (); | |
10776 | sec = bfd_get_section_by_name (stdoutput, secname); | |
10777 | if (sec == NULL) | |
48401fcf | 10778 | as_bad (_("%s: no such section"), secname); |
c1444ec4 ILT |
10779 | *input_line_pointer = c; |
10780 | ||
10781 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 10782 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
10783 | } |
10784 | ||
fb251650 ILT |
10785 | symbolP->bsym->flags |= flag; |
10786 | ||
c1444ec4 ILT |
10787 | S_SET_EXTERNAL (symbolP); |
10788 | demand_empty_rest_of_line (); | |
10789 | } | |
10790 | ||
3d3c5039 ILT |
10791 | static void |
10792 | s_option (x) | |
10793 | int x; | |
10794 | { | |
dd3f1f76 ILT |
10795 | char *opt; |
10796 | char c; | |
10797 | ||
10798 | opt = input_line_pointer; | |
10799 | c = get_symbol_end (); | |
10800 | ||
dd3f1f76 | 10801 | if (*opt == 'O') |
9226253a ILT |
10802 | { |
10803 | /* FIXME: What does this mean? */ | |
10804 | } | |
dd3f1f76 | 10805 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 10806 | { |
d9aba805 | 10807 | int i; |
42562568 | 10808 | |
d9aba805 ILT |
10809 | i = atoi (opt + 3); |
10810 | if (i == 0) | |
10811 | mips_pic = NO_PIC; | |
10812 | else if (i == 2) | |
10813 | mips_pic = SVR4_PIC; | |
10814 | else | |
48401fcf | 10815 | as_bad (_(".option pic%d not supported"), i); |
d9aba805 | 10816 | |
1dc1e798 | 10817 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
10818 | { |
10819 | if (g_switch_seen && g_switch_value != 0) | |
48401fcf | 10820 | as_warn (_("-G may not be used with SVR4 PIC code")); |
42562568 ILT |
10821 | g_switch_value = 0; |
10822 | bfd_set_gp_size (stdoutput, 0); | |
10823 | } | |
9226253a | 10824 | } |
dd3f1f76 | 10825 | else |
48401fcf | 10826 | as_warn (_("Unrecognized option \"%s\""), opt); |
dd3f1f76 ILT |
10827 | |
10828 | *input_line_pointer = c; | |
670a50eb | 10829 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10830 | } |
10831 | ||
3c83da8a JW |
10832 | /* This structure is used to hold a stack of .set values. */ |
10833 | ||
10834 | struct mips_option_stack | |
10835 | { | |
10836 | struct mips_option_stack *next; | |
10837 | struct mips_set_options options; | |
10838 | }; | |
10839 | ||
10840 | static struct mips_option_stack *mips_opts_stack; | |
10841 | ||
10842 | /* Handle the .set pseudo-op. */ | |
10843 | ||
3d3c5039 ILT |
10844 | static void |
10845 | s_mipsset (x) | |
10846 | int x; | |
10847 | { | |
670a50eb ILT |
10848 | char *name = input_line_pointer, ch; |
10849 | ||
10850 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10851 | input_line_pointer++; | |
10852 | ch = *input_line_pointer; | |
10853 | *input_line_pointer = '\0'; | |
10854 | ||
10855 | if (strcmp (name, "reorder") == 0) | |
10856 | { | |
3c83da8a | 10857 | if (mips_opts.noreorder && prev_nop_frag != NULL) |
4e95866e | 10858 | { |
4a1cb507 ILT |
10859 | /* If we still have pending nops, we can discard them. The |
10860 | usual nop handling will insert any that are still | |
10861 | needed. */ | |
3c83da8a JW |
10862 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
10863 | * (mips_opts.mips16 ? 2 : 4)); | |
4a1cb507 | 10864 | prev_nop_frag = NULL; |
4e95866e | 10865 | } |
3c83da8a | 10866 | mips_opts.noreorder = 0; |
670a50eb ILT |
10867 | } |
10868 | else if (strcmp (name, "noreorder") == 0) | |
10869 | { | |
fbcfacb7 | 10870 | mips_emit_delays (true); |
3c83da8a | 10871 | mips_opts.noreorder = 1; |
0dd2d296 | 10872 | mips_any_noreorder = 1; |
670a50eb ILT |
10873 | } |
10874 | else if (strcmp (name, "at") == 0) | |
10875 | { | |
3c83da8a | 10876 | mips_opts.noat = 0; |
670a50eb ILT |
10877 | } |
10878 | else if (strcmp (name, "noat") == 0) | |
10879 | { | |
3c83da8a | 10880 | mips_opts.noat = 1; |
3d3c5039 | 10881 | } |
670a50eb ILT |
10882 | else if (strcmp (name, "macro") == 0) |
10883 | { | |
3c83da8a | 10884 | mips_opts.warn_about_macros = 0; |
670a50eb ILT |
10885 | } |
10886 | else if (strcmp (name, "nomacro") == 0) | |
10887 | { | |
3c83da8a | 10888 | if (mips_opts.noreorder == 0) |
48401fcf | 10889 | as_bad (_("`noreorder' must be set before `nomacro'")); |
3c83da8a | 10890 | mips_opts.warn_about_macros = 1; |
670a50eb ILT |
10891 | } |
10892 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
10893 | { | |
3c83da8a | 10894 | mips_opts.nomove = 0; |
670a50eb ILT |
10895 | } |
10896 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
10897 | { | |
3c83da8a | 10898 | mips_opts.nomove = 1; |
670a50eb ILT |
10899 | } |
10900 | else if (strcmp (name, "bopt") == 0) | |
10901 | { | |
3c83da8a | 10902 | mips_opts.nobopt = 0; |
670a50eb ILT |
10903 | } |
10904 | else if (strcmp (name, "nobopt") == 0) | |
10905 | { | |
3c83da8a | 10906 | mips_opts.nobopt = 1; |
670a50eb | 10907 | } |
943321c0 ILT |
10908 | else if (strcmp (name, "mips16") == 0 |
10909 | || strcmp (name, "MIPS-16") == 0) | |
3c83da8a | 10910 | mips_opts.mips16 = 1; |
943321c0 ILT |
10911 | else if (strcmp (name, "nomips16") == 0 |
10912 | || strcmp (name, "noMIPS-16") == 0) | |
3c83da8a | 10913 | mips_opts.mips16 = 0; |
1051c97f ILT |
10914 | else if (strncmp (name, "mips", 4) == 0) |
10915 | { | |
10916 | int isa; | |
10917 | ||
10918 | /* Permit the user to change the ISA on the fly. Needless to | |
10919 | say, misuse can cause serious problems. */ | |
10920 | isa = atoi (name + 4); | |
10921 | if (isa == 0) | |
3c83da8a | 10922 | mips_opts.isa = file_mips_isa; |
d8a1c247 | 10923 | else if (isa < 1 || isa > 4) |
48401fcf | 10924 | as_bad (_("unknown ISA level")); |
1051c97f | 10925 | else |
3c83da8a | 10926 | mips_opts.isa = isa; |
1051c97f | 10927 | } |
cc5703cd | 10928 | else if (strcmp (name, "autoextend") == 0) |
3c83da8a | 10929 | mips_opts.noautoextend = 0; |
cc5703cd | 10930 | else if (strcmp (name, "noautoextend") == 0) |
3c83da8a JW |
10931 | mips_opts.noautoextend = 1; |
10932 | else if (strcmp (name, "push") == 0) | |
10933 | { | |
10934 | struct mips_option_stack *s; | |
10935 | ||
10936 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
10937 | s->next = mips_opts_stack; | |
10938 | s->options = mips_opts; | |
10939 | mips_opts_stack = s; | |
10940 | } | |
10941 | else if (strcmp (name, "pop") == 0) | |
10942 | { | |
10943 | struct mips_option_stack *s; | |
10944 | ||
10945 | s = mips_opts_stack; | |
10946 | if (s == NULL) | |
48401fcf | 10947 | as_bad (_(".set pop with no .set push")); |
3c83da8a JW |
10948 | else |
10949 | { | |
10950 | /* If we're changing the reorder mode we need to handle | |
10951 | delay slots correctly. */ | |
10952 | if (s->options.noreorder && ! mips_opts.noreorder) | |
10953 | mips_emit_delays (true); | |
10954 | else if (! s->options.noreorder && mips_opts.noreorder) | |
10955 | { | |
10956 | if (prev_nop_frag != NULL) | |
10957 | { | |
10958 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
10959 | * (mips_opts.mips16 ? 2 : 4)); | |
10960 | prev_nop_frag = NULL; | |
10961 | } | |
10962 | } | |
10963 | ||
10964 | mips_opts = s->options; | |
10965 | mips_opts_stack = s->next; | |
10966 | free (s); | |
10967 | } | |
10968 | } | |
670a50eb ILT |
10969 | else |
10970 | { | |
48401fcf | 10971 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); |
670a50eb ILT |
10972 | } |
10973 | *input_line_pointer = ch; | |
10974 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
10975 | } |
10976 | ||
9226253a ILT |
10977 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
10978 | .option pic2. It means to generate SVR4 PIC calls. */ | |
10979 | ||
10980 | static void | |
10981 | s_abicalls (ignore) | |
10982 | int ignore; | |
10983 | { | |
d9aba805 | 10984 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
10985 | if (USE_GLOBAL_POINTER_OPT) |
10986 | { | |
10987 | if (g_switch_seen && g_switch_value != 0) | |
48401fcf | 10988 | as_warn (_("-G may not be used with SVR4 PIC code")); |
1dc1e798 KR |
10989 | g_switch_value = 0; |
10990 | } | |
d9aba805 | 10991 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
10992 | demand_empty_rest_of_line (); |
10993 | } | |
10994 | ||
10995 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
10996 | PIC code. It sets the $gp register for the function based on the | |
10997 | function address, which is in the register named in the argument. | |
10998 | This uses a relocation against _gp_disp, which is handled specially | |
10999 | by the linker. The result is: | |
11000 | lui $gp,%hi(_gp_disp) | |
11001 | addiu $gp,$gp,%lo(_gp_disp) | |
11002 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 11003 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
11004 | |
11005 | static void | |
11006 | s_cpload (ignore) | |
11007 | int ignore; | |
11008 | { | |
11009 | expressionS ex; | |
11010 | int icnt = 0; | |
11011 | ||
d9aba805 ILT |
11012 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
11013 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
11014 | { |
11015 | s_ignore (0); | |
11016 | return; | |
11017 | } | |
11018 | ||
11019 | /* .cpload should be a in .set noreorder section. */ | |
3c83da8a | 11020 | if (mips_opts.noreorder == 0) |
48401fcf | 11021 | as_warn (_(".cpload not in noreorder section")); |
0dd2d296 | 11022 | |
9226253a ILT |
11023 | ex.X_op = O_symbol; |
11024 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
11025 | ex.X_op_symbol = NULL; | |
11026 | ex.X_add_number = 0; | |
11027 | ||
fb251650 ILT |
11028 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
11029 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
11030 | ||
0dd2d296 ILT |
11031 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
11032 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
11033 | (int) BFD_RELOC_LO16); |
11034 | ||
0dd2d296 ILT |
11035 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
11036 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
11037 | |
11038 | demand_empty_rest_of_line (); | |
11039 | } | |
11040 | ||
11041 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
11042 | offset from $sp. The offset is remembered, and after making a PIC | |
11043 | call $gp is restored from that location. */ | |
11044 | ||
11045 | static void | |
11046 | s_cprestore (ignore) | |
11047 | int ignore; | |
11048 | { | |
11049 | expressionS ex; | |
11050 | int icnt = 0; | |
11051 | ||
d9aba805 ILT |
11052 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
11053 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
11054 | { |
11055 | s_ignore (0); | |
11056 | return; | |
11057 | } | |
11058 | ||
9226253a ILT |
11059 | mips_cprestore_offset = get_absolute_expression (); |
11060 | ||
11061 | ex.X_op = O_constant; | |
11062 | ex.X_add_symbol = NULL; | |
11063 | ex.X_op_symbol = NULL; | |
11064 | ex.X_add_number = mips_cprestore_offset; | |
11065 | ||
0dd2d296 | 11066 | macro_build ((char *) NULL, &icnt, &ex, |
9a1f3160 JL |
11067 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
11068 | || mips_opts.isa < 3) | |
11069 | ? "sw" : "sd"), | |
9226253a ILT |
11070 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); |
11071 | ||
11072 | demand_empty_rest_of_line (); | |
11073 | } | |
11074 | ||
0dd2d296 ILT |
11075 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
11076 | code. It generates a 32 bit GP relative reloc. */ | |
11077 | ||
11078 | static void | |
11079 | s_gpword (ignore) | |
11080 | int ignore; | |
11081 | { | |
23dc1ae3 | 11082 | symbolS *label; |
0dd2d296 ILT |
11083 | expressionS ex; |
11084 | char *p; | |
11085 | ||
11086 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 11087 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
11088 | { |
11089 | s_cons (2); | |
11090 | return; | |
11091 | } | |
11092 | ||
fbcfacb7 ILT |
11093 | label = insn_labels != NULL ? insn_labels->label : NULL; |
11094 | mips_emit_delays (true); | |
0dd2d296 | 11095 | if (auto_align) |
23dc1ae3 | 11096 | mips_align (2, 0, label); |
fbcfacb7 | 11097 | mips_clear_insn_labels (); |
0dd2d296 ILT |
11098 | |
11099 | expression (&ex); | |
11100 | ||
11101 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
11102 | { | |
48401fcf | 11103 | as_bad (_("Unsupported use of .gpword")); |
0dd2d296 ILT |
11104 | ignore_rest_of_line (); |
11105 | } | |
11106 | ||
11107 | p = frag_more (4); | |
11108 | md_number_to_chars (p, (valueT) 0, 4); | |
11109 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
11110 | BFD_RELOC_MIPS_GPREL32); | |
11111 | ||
11112 | demand_empty_rest_of_line (); | |
11113 | } | |
11114 | ||
11115 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
11116 | tables in SVR4 PIC code. */ | |
11117 | ||
11118 | static void | |
11119 | s_cpadd (ignore) | |
11120 | int ignore; | |
11121 | { | |
11122 | int icnt = 0; | |
11123 | int reg; | |
11124 | ||
11125 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 11126 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
11127 | { |
11128 | s_ignore (0); | |
11129 | return; | |
11130 | } | |
11131 | ||
11132 | /* Add $gp to the register named as an argument. */ | |
11133 | reg = tc_get_register (0); | |
11134 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
11135 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
11136 | || mips_opts.isa < 3) | |
11137 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
11138 | "d,v,t", reg, reg, GP); |
11139 | ||
11140 | demand_empty_rest_of_line (); | |
11141 | } | |
11142 | ||
ed3eb786 ILT |
11143 | /* Handle the .insn pseudo-op. This marks instruction labels in |
11144 | mips16 mode. This permits the linker to handle them specially, | |
11145 | such as generating jalx instructions when needed. We also make | |
11146 | them odd for the duration of the assembly, in order to generate the | |
11147 | right sort of code. We will make them even in the adjust_symtab | |
11148 | routine, while leaving them marked. This is convenient for the | |
11149 | debugger and the disassembler. The linker knows to make them odd | |
11150 | again. */ | |
11151 | ||
11152 | static void | |
11153 | s_insn (ignore) | |
11154 | int ignore; | |
11155 | { | |
3c83da8a JW |
11156 | if (mips_opts.mips16) |
11157 | mips16_mark_labels (); | |
ed3eb786 | 11158 | |
3c83da8a JW |
11159 | demand_empty_rest_of_line (); |
11160 | } | |
ed3eb786 | 11161 | |
3c83da8a JW |
11162 | /* Handle a .stabn directive. We need these in order to mark a label |
11163 | as being a mips16 text label correctly. Sometimes the compiler | |
11164 | will emit a label, followed by a .stabn, and then switch sections. | |
11165 | If the label and .stabn are in mips16 mode, then the label is | |
11166 | really a mips16 text label. */ | |
ed3eb786 | 11167 | |
3c83da8a JW |
11168 | static void |
11169 | s_mips_stab (type) | |
11170 | int type; | |
11171 | { | |
11172 | if (type == 'n' && mips_opts.mips16) | |
11173 | mips16_mark_labels (); | |
11174 | ||
11175 | s_stab (type); | |
ed3eb786 ILT |
11176 | } |
11177 | ||
3c69baf9 GRK |
11178 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. |
11179 | */ | |
11180 | ||
11181 | static void | |
11182 | s_mips_weakext (ignore) | |
11183 | int ignore; | |
11184 | { | |
11185 | char *name; | |
11186 | int c; | |
11187 | symbolS *symbolP; | |
11188 | expressionS exp; | |
11189 | ||
11190 | name = input_line_pointer; | |
11191 | c = get_symbol_end (); | |
11192 | symbolP = symbol_find_or_make (name); | |
11193 | S_SET_WEAK (symbolP); | |
11194 | *input_line_pointer = c; | |
11195 | ||
11196 | SKIP_WHITESPACE (); | |
11197 | ||
11198 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11199 | { | |
11200 | if (S_IS_DEFINED (symbolP)) | |
11201 | { | |
11202 | as_bad ("Ignoring attempt to redefine symbol `%s'.", | |
11203 | S_GET_NAME (symbolP)); | |
11204 | ignore_rest_of_line (); | |
11205 | return; | |
11206 | } | |
11207 | ||
11208 | if (*input_line_pointer == ',') | |
11209 | { | |
11210 | ++input_line_pointer; | |
11211 | SKIP_WHITESPACE (); | |
11212 | } | |
11213 | ||
11214 | expression (&exp); | |
11215 | if (exp.X_op != O_symbol) | |
11216 | { | |
11217 | as_bad ("bad .weakext directive"); | |
11218 | ignore_rest_of_line(); | |
11219 | return; | |
11220 | } | |
11221 | symbolP->sy_value = exp; | |
11222 | } | |
11223 | ||
11224 | demand_empty_rest_of_line (); | |
11225 | } | |
11226 | ||
9226253a | 11227 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
11228 | to parse .frame. The argument is non-zero if this is the frame |
11229 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 11230 | |
3d3c5039 | 11231 | int |
0dd2d296 ILT |
11232 | tc_get_register (frame) |
11233 | int frame; | |
3d3c5039 ILT |
11234 | { |
11235 | int reg; | |
11236 | ||
11237 | SKIP_WHITESPACE (); | |
11238 | if (*input_line_pointer++ != '$') | |
11239 | { | |
48401fcf | 11240 | as_warn (_("expected `$'")); |
0dd2d296 | 11241 | reg = 0; |
3d3c5039 | 11242 | } |
0dd2d296 | 11243 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
11244 | { |
11245 | reg = get_absolute_expression (); | |
11246 | if (reg < 0 || reg >= 32) | |
11247 | { | |
48401fcf | 11248 | as_warn (_("Bad register number")); |
3d3c5039 ILT |
11249 | reg = 0; |
11250 | } | |
11251 | } | |
11252 | else | |
11253 | { | |
11254 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 11255 | reg = FP; |
3d3c5039 | 11256 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 11257 | reg = SP; |
3d3c5039 | 11258 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 11259 | reg = GP; |
3d3c5039 | 11260 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 11261 | reg = AT; |
3d3c5039 ILT |
11262 | else |
11263 | { | |
48401fcf | 11264 | as_warn (_("Unrecognized register name")); |
0dd2d296 | 11265 | reg = 0; |
3d3c5039 ILT |
11266 | } |
11267 | input_line_pointer += 2; | |
11268 | } | |
0dd2d296 ILT |
11269 | if (frame) |
11270 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
11271 | return reg; |
11272 | } | |
11273 | ||
0dd2d296 ILT |
11274 | valueT |
11275 | md_section_align (seg, addr) | |
11276 | asection *seg; | |
11277 | valueT addr; | |
11278 | { | |
11279 | int align = bfd_get_section_alignment (stdoutput, seg); | |
11280 | ||
cf32394d ILT |
11281 | #ifdef OBJ_ELF |
11282 | /* We don't need to align ELF sections to the full alignment. | |
11283 | However, Irix 5 may prefer that we align them at least to a 16 | |
08e17202 ILT |
11284 | byte boundary. We don't bother to align the sections if we are |
11285 | targeted for an embedded system. */ | |
11286 | if (strcmp (TARGET_OS, "elf") == 0) | |
11287 | return addr; | |
943321c0 ILT |
11288 | if (align > 4) |
11289 | align = 4; | |
10a14e36 | 11290 | #endif |
cf32394d ILT |
11291 | |
11292 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
11293 | } |
11294 | ||
d8a1c247 KR |
11295 | /* Utility routine, called from above as well. If called while the |
11296 | input file is still being read, it's only an approximation. (For | |
11297 | example, a symbol may later become defined which appeared to be | |
11298 | undefined earlier.) */ | |
22ba90ce ILT |
11299 | |
11300 | static int | |
85ce5635 | 11301 | nopic_need_relax (sym, before_relaxing) |
d8a1c247 | 11302 | symbolS *sym; |
85ce5635 | 11303 | int before_relaxing; |
d8a1c247 KR |
11304 | { |
11305 | if (sym == 0) | |
11306 | return 0; | |
11307 | ||
1dc1e798 KR |
11308 | if (USE_GLOBAL_POINTER_OPT) |
11309 | { | |
11310 | const char *symname; | |
11311 | int change; | |
11312 | ||
11313 | /* Find out whether this symbol can be referenced off the GP | |
11314 | register. It can be if it is smaller than the -G size or if | |
11315 | it is in the .sdata or .sbss section. Certain symbols can | |
11316 | not be referenced off the GP, although it appears as though | |
11317 | they can. */ | |
11318 | symname = S_GET_NAME (sym); | |
11319 | if (symname != (const char *) NULL | |
11320 | && (strcmp (symname, "eprol") == 0 | |
11321 | || strcmp (symname, "etext") == 0 | |
11322 | || strcmp (symname, "_gp") == 0 | |
11323 | || strcmp (symname, "edata") == 0 | |
11324 | || strcmp (symname, "_fbss") == 0 | |
11325 | || strcmp (symname, "_fdata") == 0 | |
11326 | || strcmp (symname, "_ftext") == 0 | |
11327 | || strcmp (symname, "end") == 0 | |
11328 | || strcmp (symname, "_gp_disp") == 0)) | |
11329 | change = 1; | |
23ac3ca1 | 11330 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) |
c625fc23 JSC |
11331 | && (0 |
11332 | #ifndef NO_ECOFF_DEBUGGING | |
11333 | || (sym->ecoff_extern_size != 0 | |
11334 | && sym->ecoff_extern_size <= g_switch_value) | |
a5586bdc | 11335 | #endif |
85ce5635 ILT |
11336 | /* We must defer this decision until after the whole |
11337 | file has been read, since there might be a .extern | |
11338 | after the first use of this symbol. */ | |
a5586bdc ILT |
11339 | || (before_relaxing |
11340 | #ifndef NO_ECOFF_DEBUGGING | |
11341 | && sym->ecoff_extern_size == 0 | |
c625fc23 | 11342 | #endif |
a5586bdc | 11343 | && S_GET_VALUE (sym) == 0) |
1dc1e798 KR |
11344 | || (S_GET_VALUE (sym) != 0 |
11345 | && S_GET_VALUE (sym) <= g_switch_value))) | |
11346 | change = 0; | |
11347 | else | |
11348 | { | |
11349 | const char *segname; | |
d8a1c247 | 11350 | |
1dc1e798 KR |
11351 | segname = segment_name (S_GET_SEGMENT (sym)); |
11352 | assert (strcmp (segname, ".lit8") != 0 | |
11353 | && strcmp (segname, ".lit4") != 0); | |
11354 | change = (strcmp (segname, ".sdata") != 0 | |
11355 | && strcmp (segname, ".sbss") != 0); | |
11356 | } | |
11357 | return change; | |
11358 | } | |
11359 | else | |
11360 | /* We are not optimizing for the GP register. */ | |
11361 | return 1; | |
d8a1c247 KR |
11362 | } |
11363 | ||
cc5703cd ILT |
11364 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
11365 | extended opcode. SEC is the section the frag is in. */ | |
11366 | ||
11367 | static int | |
11368 | mips16_extended_frag (fragp, sec, stretch) | |
11369 | fragS *fragp; | |
11370 | asection *sec; | |
11371 | long stretch; | |
11372 | { | |
11373 | int type; | |
11374 | register const struct mips16_immed_operand *op; | |
11375 | offsetT val; | |
11376 | int mintiny, maxtiny; | |
f74ba7a3 | 11377 | segT symsec; |
cc5703cd | 11378 | |
8728fa92 ILT |
11379 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
11380 | return 0; | |
11381 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
11382 | return 1; | |
11383 | ||
cc5703cd ILT |
11384 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
11385 | op = mips16_immed_operands; | |
11386 | while (op->type != type) | |
11387 | { | |
11388 | ++op; | |
11389 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
11390 | } | |
11391 | ||
11392 | if (op->unsp) | |
11393 | { | |
11394 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
11395 | { | |
11396 | mintiny = 1; | |
11397 | maxtiny = 1 << op->nbits; | |
11398 | } | |
11399 | else | |
11400 | { | |
11401 | mintiny = 0; | |
11402 | maxtiny = (1 << op->nbits) - 1; | |
11403 | } | |
11404 | } | |
11405 | else | |
11406 | { | |
11407 | mintiny = - (1 << (op->nbits - 1)); | |
11408 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
11409 | } | |
11410 | ||
f74ba7a3 ILT |
11411 | /* We can't call S_GET_VALUE here, because we don't want to lock in |
11412 | a particular frag address. */ | |
11413 | if (fragp->fr_symbol->sy_value.X_op == O_constant) | |
11414 | { | |
11415 | val = (fragp->fr_symbol->sy_value.X_add_number | |
11416 | + fragp->fr_symbol->sy_frag->fr_address); | |
11417 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
11418 | } | |
11419 | else if (fragp->fr_symbol->sy_value.X_op == O_symbol | |
11420 | && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op | |
11421 | == O_constant)) | |
11422 | { | |
11423 | val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number | |
11424 | + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address | |
11425 | + fragp->fr_symbol->sy_value.X_add_number | |
11426 | + fragp->fr_symbol->sy_frag->fr_address); | |
11427 | symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); | |
11428 | } | |
11429 | else | |
11430 | return 1; | |
cc5703cd ILT |
11431 | |
11432 | if (op->pcrel) | |
11433 | { | |
11434 | addressT addr; | |
11435 | ||
11436 | /* We won't have the section when we are called from | |
11437 | mips_relax_frag. However, we will always have been called | |
11438 | from md_estimate_size_before_relax first. If this is a | |
11439 | branch to a different section, we mark it as such. If SEC is | |
11440 | NULL, and the frag is not marked, then it must be a branch to | |
11441 | the same section. */ | |
11442 | if (sec == NULL) | |
11443 | { | |
11444 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
11445 | return 1; | |
11446 | } | |
11447 | else | |
11448 | { | |
f74ba7a3 | 11449 | if (symsec != sec) |
cc5703cd ILT |
11450 | { |
11451 | fragp->fr_subtype = | |
11452 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11453 | ||
11454 | /* FIXME: We should support this, and let the linker | |
11455 | catch branches and loads that are out of range. */ | |
11456 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
48401fcf | 11457 | _("unsupported PC relative reference to different section")); |
cc5703cd ILT |
11458 | |
11459 | return 1; | |
11460 | } | |
11461 | } | |
11462 | ||
11463 | /* In this case, we know for sure that the symbol fragment is in | |
11464 | the same section. If the fr_address of the symbol fragment | |
11465 | is greater then the address of this fragment we want to add | |
11466 | in STRETCH in order to get a better estimate of the address. | |
11467 | This particularly matters because of the shift bits. */ | |
11468 | if (stretch != 0 | |
11469 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
11470 | { | |
11471 | fragS *f; | |
11472 | ||
a941619c ILT |
11473 | /* Adjust stretch for any alignment frag. Note that if have |
11474 | been expanding the earlier code, the symbol may be | |
11475 | defined in what appears to be an earlier frag. FIXME: | |
11476 | This doesn't handle the fr_subtype field, which specifies | |
11477 | a maximum number of bytes to skip when doing an | |
11478 | alignment. */ | |
11479 | for (f = fragp; | |
11480 | f != NULL && f != fragp->fr_symbol->sy_frag; | |
11481 | f = f->fr_next) | |
cc5703cd | 11482 | { |
cc5703cd ILT |
11483 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) |
11484 | { | |
11485 | if (stretch < 0) | |
11486 | stretch = - ((- stretch) | |
11487 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
11488 | else | |
11489 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
11490 | if (stretch == 0) | |
11491 | break; | |
11492 | } | |
11493 | } | |
a941619c ILT |
11494 | if (f != NULL) |
11495 | val += stretch; | |
cc5703cd ILT |
11496 | } |
11497 | ||
a677feeb ILT |
11498 | addr = fragp->fr_address + fragp->fr_fix; |
11499 | ||
11500 | /* The base address rules are complicated. The base address of | |
11501 | a branch is the following instruction. The base address of a | |
11502 | PC relative load or add is the instruction itself, but if it | |
319305a7 ILT |
11503 | is in a delay slot (in which case it can not be extended) use |
11504 | the address of the instruction whose delay slot it is in. */ | |
a677feeb | 11505 | if (type == 'p' || type == 'q') |
fbcfacb7 ILT |
11506 | { |
11507 | addr += 2; | |
319305a7 ILT |
11508 | |
11509 | /* If we are currently assuming that this frag should be | |
11510 | extended, then, the current address is two bytes | |
11511 | higher. */ | |
11512 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11513 | addr += 2; | |
11514 | ||
fbcfacb7 ILT |
11515 | /* Ignore the low bit in the target, since it will be set |
11516 | for a text label. */ | |
11517 | if ((val & 1) != 0) | |
11518 | --val; | |
11519 | } | |
a677feeb ILT |
11520 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
11521 | addr -= 4; | |
11522 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
11523 | addr -= 2; | |
cc5703cd | 11524 | |
cc5703cd ILT |
11525 | val -= addr & ~ ((1 << op->shift) - 1); |
11526 | ||
11527 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
11528 | if (type == 'p' || type == 'q') | |
11529 | val /= 2; | |
11530 | ||
11531 | /* If any of the shifted bits are set, we must use an extended | |
11532 | opcode. If the address depends on the size of this | |
11533 | instruction, this can lead to a loop, so we arrange to always | |
559c664a ILT |
11534 | use an extended opcode. We only check this when we are in |
11535 | the main relaxation loop, when SEC is NULL. */ | |
11536 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
11537 | { | |
11538 | fragp->fr_subtype = | |
11539 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11540 | return 1; | |
11541 | } | |
11542 | ||
11543 | /* If we are about to mark a frag as extended because the value | |
11544 | is precisely maxtiny + 1, then there is a chance of an | |
11545 | infinite loop as in the following code: | |
11546 | la $4,foo | |
11547 | .skip 1020 | |
11548 | .align 2 | |
11549 | foo: | |
11550 | In this case when the la is extended, foo is 0x3fc bytes | |
11551 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
11552 | the la must be extended. To avoid this loop, we mark the | |
11553 | frag as extended if it was small, and is about to become | |
11554 | extended with a value of maxtiny + 1. */ | |
11555 | if (val == ((maxtiny + 1) << op->shift) | |
11556 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
11557 | && sec == NULL) | |
cc5703cd ILT |
11558 | { |
11559 | fragp->fr_subtype = | |
11560 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11561 | return 1; | |
11562 | } | |
11563 | } | |
41a0ed22 | 11564 | else if (symsec != absolute_section && sec != NULL) |
48401fcf | 11565 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); |
cc5703cd ILT |
11566 | |
11567 | if ((val & ((1 << op->shift) - 1)) != 0 | |
11568 | || val < (mintiny << op->shift) | |
11569 | || val > (maxtiny << op->shift)) | |
11570 | return 1; | |
11571 | else | |
11572 | return 0; | |
11573 | } | |
11574 | ||
11575 | /* Estimate the size of a frag before relaxing. Unless this is the | |
11576 | mips16, we are not really relaxing here, and the final size is | |
11577 | encoded in the subtype information. For the mips16, we have to | |
11578 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 11579 | |
0dd2d296 ILT |
11580 | /*ARGSUSED*/ |
11581 | int | |
11582 | md_estimate_size_before_relax (fragp, segtype) | |
11583 | fragS *fragp; | |
11584 | asection *segtype; | |
11585 | { | |
11586 | int change; | |
11587 | ||
cc5703cd ILT |
11588 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
11589 | { | |
11590 | if (mips16_extended_frag (fragp, segtype, 0)) | |
11591 | { | |
11592 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11593 | return 4; | |
11594 | } | |
11595 | else | |
11596 | { | |
11597 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11598 | return 2; | |
11599 | } | |
11600 | } | |
11601 | ||
d9aba805 | 11602 | if (mips_pic == NO_PIC) |
0dd2d296 | 11603 | { |
85ce5635 | 11604 | change = nopic_need_relax (fragp->fr_symbol, 0); |
0dd2d296 | 11605 | } |
d9aba805 | 11606 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 11607 | { |
46a92fde ILT |
11608 | symbolS *sym; |
11609 | asection *symsec; | |
11610 | ||
11611 | sym = fragp->fr_symbol; | |
11612 | ||
11613 | /* Handle the case of a symbol equated to another symbol. */ | |
11614 | while (sym->sy_value.X_op == O_symbol | |
11615 | && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym))) | |
11616 | { | |
11617 | symbolS *n; | |
11618 | ||
11619 | /* It's possible to get a loop here in a badly written | |
11620 | program. */ | |
11621 | n = sym->sy_value.X_add_symbol; | |
11622 | if (n == sym) | |
11623 | break; | |
11624 | sym = n; | |
11625 | } | |
11626 | ||
11627 | symsec = S_GET_SEGMENT (sym); | |
0dd2d296 ILT |
11628 | |
11629 | /* This must duplicate the test in adjust_reloc_syms. */ | |
11630 | change = (symsec != &bfd_und_section | |
11631 | && symsec != &bfd_abs_section | |
11632 | && ! bfd_is_com_section (symsec)); | |
11633 | } | |
d9aba805 ILT |
11634 | else |
11635 | abort (); | |
0dd2d296 ILT |
11636 | |
11637 | if (change) | |
11638 | { | |
11639 | /* Record the offset to the first reloc in the fr_opcode field. | |
11640 | This lets md_convert_frag and tc_gen_reloc know that the code | |
11641 | must be expanded. */ | |
11642 | fragp->fr_opcode = (fragp->fr_literal | |
11643 | + fragp->fr_fix | |
11644 | - RELAX_OLD (fragp->fr_subtype) | |
11645 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
11646 | /* FIXME: This really needs as_warn_where. */ | |
11647 | if (RELAX_WARN (fragp->fr_subtype)) | |
48401fcf | 11648 | as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\"")); |
0dd2d296 ILT |
11649 | } |
11650 | ||
11651 | if (! change) | |
11652 | return 0; | |
11653 | else | |
11654 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
11655 | } | |
11656 | ||
0d7f9025 ILT |
11657 | /* This is called to see whether a reloc against a defined symbol |
11658 | should be converted into a reloc against a section. Don't adjust | |
11659 | MIPS16 jump relocations, so we don't have to worry about the format | |
11660 | of the offset in the .o file. Don't adjust relocations against | |
6927c24d ILT |
11661 | mips16 symbols, so that the linker can find them if it needs to set |
11662 | up a stub. */ | |
0d7f9025 ILT |
11663 | |
11664 | int | |
11665 | mips_fix_adjustable (fixp) | |
11666 | fixS *fixp; | |
11667 | { | |
11668 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
11669 | return 0; | |
7e656649 RH |
11670 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
11671 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11672 | return 0; | |
0d7f9025 ILT |
11673 | if (fixp->fx_addsy == NULL) |
11674 | return 1; | |
68952421 | 11675 | #ifdef OBJ_ELF |
0d7f9025 | 11676 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
46a92fde ILT |
11677 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 |
11678 | && fixp->fx_subsy == NULL) | |
0d7f9025 ILT |
11679 | return 0; |
11680 | #endif | |
11681 | return 1; | |
11682 | } | |
11683 | ||
0dd2d296 ILT |
11684 | /* Translate internal representation of relocation info to BFD target |
11685 | format. */ | |
11686 | ||
11687 | arelent ** | |
3d3c5039 ILT |
11688 | tc_gen_reloc (section, fixp) |
11689 | asection *section; | |
11690 | fixS *fixp; | |
11691 | { | |
0dd2d296 | 11692 | static arelent *retval[4]; |
3d3c5039 | 11693 | arelent *reloc; |
a8aed9dd | 11694 | bfd_reloc_code_real_type code; |
3d3c5039 | 11695 | |
0dd2d296 ILT |
11696 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
11697 | retval[1] = NULL; | |
3d3c5039 ILT |
11698 | |
11699 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
11700 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
11701 | |
11702 | if (mips_pic == EMBEDDED_PIC | |
11703 | && SWITCH_TABLE (fixp)) | |
11704 | { | |
11705 | /* For a switch table entry we use a special reloc. The addend | |
11706 | is actually the difference between the reloc address and the | |
11707 | subtrahend. */ | |
11708 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 | 11709 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
48401fcf | 11710 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); |
1c803e52 ILT |
11711 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
11712 | } | |
ecd4ca1c ILT |
11713 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
11714 | { | |
11715 | /* We use a special addend for an internal RELLO reloc. */ | |
11716 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
11717 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
11718 | else | |
11719 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
11720 | } | |
11721 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
11722 | { | |
11723 | assert (fixp->fx_next != NULL | |
11724 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
11725 | /* We use a special addend for an internal RELHI reloc. The | |
11726 | reloc is relative to the RELLO; adjust the addend | |
11727 | accordingly. */ | |
11728 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
11729 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
11730 | + fixp->fx_next->fx_where | |
11731 | - S_GET_VALUE (fixp->fx_subsy)); | |
11732 | else | |
11733 | reloc->addend = (fixp->fx_addnumber | |
11734 | + fixp->fx_next->fx_frag->fr_address | |
11735 | + fixp->fx_next->fx_where); | |
11736 | } | |
1c803e52 | 11737 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
11738 | reloc->addend = fixp->fx_addnumber; |
11739 | else | |
5b63f465 | 11740 | { |
1dc1e798 KR |
11741 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
11742 | /* A gruesome hack which is a result of the gruesome gas reloc | |
11743 | handling. */ | |
11744 | reloc->addend = reloc->address; | |
11745 | else | |
11746 | reloc->addend = -reloc->address; | |
5b63f465 | 11747 | } |
0dd2d296 ILT |
11748 | |
11749 | /* If this is a variant frag, we may need to adjust the existing | |
11750 | reloc and generate a new one. */ | |
11751 | if (fixp->fx_frag->fr_opcode != NULL | |
11752 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
11753 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
11754 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
11755 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
11756 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
11757 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
11758 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
11759 | { |
11760 | arelent *reloc2; | |
11761 | ||
cc5703cd ILT |
11762 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
11763 | ||
0dd2d296 | 11764 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
11765 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
11766 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
11767 | the second one handle all of them. */ | |
0dd2d296 ILT |
11768 | if (fixp->fx_next != NULL |
11769 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
11770 | { | |
fb251650 ILT |
11771 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
11772 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
11773 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
11774 | && (fixp->fx_next->fx_r_type | |
11775 | == BFD_RELOC_MIPS_GOT_LO16)) | |
11776 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
11777 | && (fixp->fx_next->fx_r_type | |
11778 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
11779 | retval[0] = NULL; |
11780 | return retval; | |
11781 | } | |
11782 | ||
11783 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
11784 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
11785 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
11786 | retval[2] = NULL; | |
11787 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
11788 | reloc2->address = (reloc->address | |
11789 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
11790 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
11791 | reloc2->addend = fixp->fx_addnumber; | |
11792 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
11793 | assert (reloc2->howto != NULL); | |
11794 | ||
11795 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
11796 | { | |
11797 | arelent *reloc3; | |
11798 | ||
11799 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
11800 | retval[3] = NULL; | |
11801 | *reloc3 = *reloc2; | |
11802 | reloc3->address += 4; | |
11803 | } | |
11804 | ||
d9aba805 | 11805 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
11806 | { |
11807 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
11808 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
11809 | } | |
d9aba805 | 11810 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 11811 | { |
fb251650 | 11812 | switch (fixp->fx_r_type) |
0dd2d296 | 11813 | { |
fb251650 ILT |
11814 | default: |
11815 | abort (); | |
11816 | case BFD_RELOC_MIPS_GOT16: | |
11817 | break; | |
11818 | case BFD_RELOC_MIPS_CALL16: | |
11819 | case BFD_RELOC_MIPS_GOT_LO16: | |
11820 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 11821 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 11822 | break; |
0dd2d296 ILT |
11823 | } |
11824 | } | |
d9aba805 ILT |
11825 | else |
11826 | abort (); | |
0dd2d296 ILT |
11827 | } |
11828 | ||
7e656649 RH |
11829 | /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry |
11830 | to be used in the relocation's section offset. */ | |
11831 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11832 | { | |
11833 | reloc->address = reloc->addend; | |
11834 | reloc->addend = 0; | |
11835 | } | |
11836 | ||
a8aed9dd ILT |
11837 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
11838 | fixup_segment converted a non-PC relative reloc into a PC | |
11839 | relative reloc. In such a case, we need to convert the reloc | |
11840 | code. */ | |
11841 | code = fixp->fx_r_type; | |
11842 | if (fixp->fx_pcrel) | |
11843 | { | |
11844 | switch (code) | |
11845 | { | |
11846 | case BFD_RELOC_8: | |
11847 | code = BFD_RELOC_8_PCREL; | |
11848 | break; | |
11849 | case BFD_RELOC_16: | |
11850 | code = BFD_RELOC_16_PCREL; | |
11851 | break; | |
11852 | case BFD_RELOC_32: | |
11853 | code = BFD_RELOC_32_PCREL; | |
11854 | break; | |
bf39474f ILT |
11855 | case BFD_RELOC_64: |
11856 | code = BFD_RELOC_64_PCREL; | |
11857 | break; | |
a8aed9dd ILT |
11858 | case BFD_RELOC_8_PCREL: |
11859 | case BFD_RELOC_16_PCREL: | |
11860 | case BFD_RELOC_32_PCREL: | |
bf39474f | 11861 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 11862 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
11863 | case BFD_RELOC_PCREL_HI16_S: |
11864 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
11865 | break; |
11866 | default: | |
11867 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
48401fcf | 11868 | _("Cannot make %s relocation PC relative"), |
a8aed9dd ILT |
11869 | bfd_get_reloc_code_name (code)); |
11870 | } | |
11871 | } | |
11872 | ||
d9aba805 ILT |
11873 | /* To support a PC relative reloc when generating embedded PIC code |
11874 | for ECOFF, we use a Cygnus extension. We check for that here to | |
11875 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 11876 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 11877 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
11878 | && mips_pic != EMBEDDED_PIC) |
11879 | reloc->howto = NULL; | |
11880 | else | |
a8aed9dd | 11881 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 11882 | |
52aa70b5 JW |
11883 | if (reloc->howto == NULL) |
11884 | { | |
11885 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
48401fcf | 11886 | _("Can not represent %s relocation in this object file format"), |
a8aed9dd | 11887 | bfd_get_reloc_code_name (code)); |
0dd2d296 | 11888 | retval[0] = NULL; |
52aa70b5 | 11889 | } |
3d3c5039 | 11890 | |
0dd2d296 | 11891 | return retval; |
3d3c5039 ILT |
11892 | } |
11893 | ||
cc5703cd ILT |
11894 | /* Relax a machine dependent frag. This returns the amount by which |
11895 | the current size of the frag should change. */ | |
11896 | ||
11897 | int | |
11898 | mips_relax_frag (fragp, stretch) | |
11899 | fragS *fragp; | |
11900 | long stretch; | |
11901 | { | |
11902 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
11903 | return 0; | |
11904 | ||
11905 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
11906 | { | |
11907 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11908 | return 0; | |
11909 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11910 | return 2; | |
11911 | } | |
11912 | else | |
11913 | { | |
11914 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11915 | return 0; | |
11916 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11917 | return -2; | |
11918 | } | |
11919 | ||
11920 | return 0; | |
11921 | } | |
11922 | ||
0dd2d296 ILT |
11923 | /* Convert a machine dependent frag. */ |
11924 | ||
11925 | void | |
11926 | md_convert_frag (abfd, asec, fragp) | |
11927 | bfd *abfd; | |
11928 | segT asec; | |
11929 | fragS *fragp; | |
3d3c5039 | 11930 | { |
0dd2d296 ILT |
11931 | int old, new; |
11932 | char *fixptr; | |
3d3c5039 | 11933 | |
cc5703cd ILT |
11934 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
11935 | { | |
11936 | int type; | |
11937 | register const struct mips16_immed_operand *op; | |
11938 | boolean small, ext; | |
11939 | offsetT val; | |
11940 | bfd_byte *buf; | |
11941 | unsigned long insn; | |
11942 | boolean use_extend; | |
11943 | unsigned short extend; | |
11944 | ||
11945 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
11946 | op = mips16_immed_operands; | |
11947 | while (op->type != type) | |
11948 | ++op; | |
11949 | ||
11950 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11951 | { | |
11952 | small = false; | |
11953 | ext = true; | |
11954 | } | |
11955 | else | |
11956 | { | |
11957 | small = true; | |
11958 | ext = false; | |
11959 | } | |
11960 | ||
b637f306 | 11961 | resolve_symbol_value (fragp->fr_symbol, 1); |
cc5703cd | 11962 | val = S_GET_VALUE (fragp->fr_symbol); |
cc5703cd ILT |
11963 | if (op->pcrel) |
11964 | { | |
11965 | addressT addr; | |
11966 | ||
a677feeb ILT |
11967 | addr = fragp->fr_address + fragp->fr_fix; |
11968 | ||
11969 | /* The rules for the base address of a PC relative reloc are | |
11970 | complicated; see mips16_extended_frag. */ | |
11971 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
11972 | { |
11973 | addr += 2; | |
319305a7 ILT |
11974 | if (ext) |
11975 | addr += 2; | |
fbcfacb7 ILT |
11976 | /* Ignore the low bit in the target, since it will be |
11977 | set for a text label. */ | |
11978 | if ((val & 1) != 0) | |
11979 | --val; | |
11980 | } | |
a677feeb ILT |
11981 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
11982 | addr -= 4; | |
11983 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
11984 | addr -= 2; | |
11985 | ||
cc5703cd ILT |
11986 | addr &= ~ (addressT) ((1 << op->shift) - 1); |
11987 | val -= addr; | |
a677feeb ILT |
11988 | |
11989 | /* Make sure the section winds up with the alignment we have | |
11990 | assumed. */ | |
11991 | if (op->shift > 0) | |
11992 | record_alignment (asec, op->shift); | |
cc5703cd ILT |
11993 | } |
11994 | ||
035936da ILT |
11995 | if (ext |
11996 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
11997 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
11998 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
48401fcf | 11999 | _("extended instruction in delay slot")); |
035936da | 12000 | |
cc5703cd ILT |
12001 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); |
12002 | ||
b9129c6f ILT |
12003 | if (target_big_endian) |
12004 | insn = bfd_getb16 (buf); | |
12005 | else | |
12006 | insn = bfd_getl16 (buf); | |
cc5703cd | 12007 | |
31a2c6ff ILT |
12008 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, |
12009 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
12010 | small, ext, &insn, &use_extend, &extend); | |
cc5703cd ILT |
12011 | |
12012 | if (use_extend) | |
12013 | { | |
12014 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
12015 | fragp->fr_fix += 2; | |
12016 | buf += 2; | |
12017 | } | |
3d3c5039 | 12018 | |
cc5703cd ILT |
12019 | md_number_to_chars (buf, insn, 2); |
12020 | fragp->fr_fix += 2; | |
12021 | buf += 2; | |
12022 | } | |
12023 | else | |
12024 | { | |
12025 | if (fragp->fr_opcode == NULL) | |
12026 | return; | |
0dd2d296 | 12027 | |
cc5703cd ILT |
12028 | old = RELAX_OLD (fragp->fr_subtype); |
12029 | new = RELAX_NEW (fragp->fr_subtype); | |
12030 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 12031 | |
cc5703cd ILT |
12032 | if (new > 0) |
12033 | memcpy (fixptr - old, fixptr, new); | |
12034 | ||
12035 | fragp->fr_fix += new - old; | |
12036 | } | |
0dd2d296 | 12037 | } |
becfe05e | 12038 | |
fbcfacb7 ILT |
12039 | #ifdef OBJ_ELF |
12040 | ||
12041 | /* This function is called after the relocs have been generated. | |
12042 | We've been storing mips16 text labels as odd. Here we convert them | |
12043 | back to even for the convenience of the debugger. */ | |
12044 | ||
12045 | void | |
12046 | mips_frob_file_after_relocs () | |
12047 | { | |
12048 | asymbol **syms; | |
12049 | unsigned int count, i; | |
12050 | ||
12051 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
12052 | return; | |
12053 | ||
12054 | syms = bfd_get_outsymbols (stdoutput); | |
12055 | count = bfd_get_symcount (stdoutput); | |
12056 | for (i = 0; i < count; i++, syms++) | |
12057 | { | |
12058 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
12059 | && ((*syms)->value & 1) != 0) | |
12060 | { | |
12061 | (*syms)->value &= ~1; | |
12062 | /* If the symbol has an odd size, it was probably computed | |
12063 | incorrectly, so adjust that as well. */ | |
12064 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
12065 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
12066 | } | |
12067 | } | |
12068 | } | |
12069 | ||
12070 | #endif | |
12071 | ||
becfe05e ILT |
12072 | /* This function is called whenever a label is defined. It is used |
12073 | when handling branch delays; if a branch has a label, we assume we | |
12074 | can not move it. */ | |
12075 | ||
12076 | void | |
12077 | mips_define_label (sym) | |
12078 | symbolS *sym; | |
12079 | { | |
fbcfacb7 ILT |
12080 | struct insn_label_list *l; |
12081 | ||
12082 | if (free_insn_labels == NULL) | |
12083 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
12084 | else | |
12085 | { | |
12086 | l = free_insn_labels; | |
12087 | free_insn_labels = l->next; | |
12088 | } | |
12089 | ||
12090 | l->label = sym; | |
12091 | l->next = insn_labels; | |
12092 | insn_labels = l; | |
becfe05e | 12093 | } |
3d3c5039 | 12094 | \f |
739708fa | 12095 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 12096 | |
0dd2d296 | 12097 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
12098 | |
12099 | void | |
12100 | mips_elf_final_processing () | |
12101 | { | |
87178180 ILT |
12102 | /* Write out the register information. */ |
12103 | if (! mips_64) | |
12104 | { | |
12105 | Elf32_RegInfo s; | |
12106 | ||
12107 | s.ri_gprmask = mips_gprmask; | |
12108 | s.ri_cprmask[0] = mips_cprmask[0]; | |
12109 | s.ri_cprmask[1] = mips_cprmask[1]; | |
12110 | s.ri_cprmask[2] = mips_cprmask[2]; | |
12111 | s.ri_cprmask[3] = mips_cprmask[3]; | |
12112 | /* The gp_value field is set by the MIPS ELF backend. */ | |
12113 | ||
12114 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
12115 | ((Elf32_External_RegInfo *) | |
12116 | mips_regmask_frag)); | |
12117 | } | |
12118 | else | |
12119 | { | |
12120 | Elf64_Internal_RegInfo s; | |
12121 | ||
12122 | s.ri_gprmask = mips_gprmask; | |
12123 | s.ri_pad = 0; | |
12124 | s.ri_cprmask[0] = mips_cprmask[0]; | |
12125 | s.ri_cprmask[1] = mips_cprmask[1]; | |
12126 | s.ri_cprmask[2] = mips_cprmask[2]; | |
12127 | s.ri_cprmask[3] = mips_cprmask[3]; | |
12128 | /* The gp_value field is set by the MIPS ELF backend. */ | |
12129 | ||
12130 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
12131 | ((Elf64_External_RegInfo *) | |
12132 | mips_regmask_frag)); | |
12133 | } | |
0dd2d296 ILT |
12134 | |
12135 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
12136 | sort of BFD interface for this. */ | |
12137 | if (mips_any_noreorder) | |
12138 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 12139 | if (mips_pic != NO_PIC) |
0dd2d296 | 12140 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
02650bd0 GRK |
12141 | |
12142 | /* Set the MIPS ELF ABI flags. */ | |
12143 | if (mips_abi_string == 0) | |
12144 | ; | |
12145 | else if (strcmp (mips_abi_string,"32") == 0) | |
12146 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; | |
12147 | else if (strcmp (mips_abi_string,"o64") == 0) | |
12148 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; | |
12149 | else if (strcmp (mips_abi_string,"eabi") == 0) | |
12150 | { | |
d95b7328 | 12151 | if (mips_eabi64) |
02650bd0 | 12152 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
d95b7328 GRK |
12153 | else |
12154 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
02650bd0 | 12155 | } |
f2a663d3 ILT |
12156 | } |
12157 | ||
739708fa | 12158 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 12159 | \f |
670a50eb ILT |
12160 | typedef struct proc |
12161 | { | |
993b4e8d RU |
12162 | struct symbol *isym; |
12163 | unsigned long reg_mask; | |
12164 | unsigned long reg_offset; | |
12165 | unsigned long fpreg_mask; | |
12166 | unsigned long fpreg_offset; | |
12167 | unsigned long frame_offset; | |
12168 | unsigned long frame_reg; | |
12169 | unsigned long pc_reg; | |
670a50eb ILT |
12170 | } |
12171 | procS; | |
3d3c5039 | 12172 | |
993b4e8d RU |
12173 | static procS cur_proc; |
12174 | static procS *cur_proc_ptr; | |
3d3c5039 ILT |
12175 | static int numprocs; |
12176 | ||
12177 | static void | |
12178 | md_obj_begin () | |
12179 | { | |
3d3c5039 ILT |
12180 | } |
12181 | ||
12182 | static void | |
12183 | md_obj_end () | |
12184 | { | |
12185 | /* check for premature end, nesting errors, etc */ | |
993b4e8d | 12186 | if (cur_proc_ptr) |
48401fcf | 12187 | as_warn (_("missing `.end' at end of assembly")); |
3d3c5039 ILT |
12188 | } |
12189 | ||
3d3c5039 ILT |
12190 | static long |
12191 | get_number () | |
12192 | { | |
670a50eb ILT |
12193 | int negative = 0; |
12194 | long val = 0; | |
3d3c5039 | 12195 | |
670a50eb ILT |
12196 | if (*input_line_pointer == '-') |
12197 | { | |
12198 | ++input_line_pointer; | |
12199 | negative = 1; | |
3d3c5039 | 12200 | } |
670a50eb | 12201 | if (!isdigit (*input_line_pointer)) |
48401fcf | 12202 | as_bad (_("Expected simple number.")); |
670a50eb ILT |
12203 | if (input_line_pointer[0] == '0') |
12204 | { | |
12205 | if (input_line_pointer[1] == 'x') | |
12206 | { | |
12207 | input_line_pointer += 2; | |
12208 | while (isxdigit (*input_line_pointer)) | |
12209 | { | |
12210 | val <<= 4; | |
3a762a0b | 12211 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 12212 | } |
670a50eb ILT |
12213 | return negative ? -val : val; |
12214 | } | |
12215 | else | |
12216 | { | |
12217 | ++input_line_pointer; | |
12218 | while (isdigit (*input_line_pointer)) | |
12219 | { | |
12220 | val <<= 3; | |
12221 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 12222 | } |
670a50eb | 12223 | return negative ? -val : val; |
3d3c5039 ILT |
12224 | } |
12225 | } | |
670a50eb ILT |
12226 | if (!isdigit (*input_line_pointer)) |
12227 | { | |
48401fcf | 12228 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), |
670a50eb | 12229 | *input_line_pointer, *input_line_pointer); |
48401fcf | 12230 | as_warn (_("Invalid number")); |
670a50eb | 12231 | return -1; |
3d3c5039 | 12232 | } |
670a50eb ILT |
12233 | while (isdigit (*input_line_pointer)) |
12234 | { | |
12235 | val *= 10; | |
12236 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 12237 | } |
670a50eb | 12238 | return negative ? -val : val; |
3d3c5039 ILT |
12239 | } |
12240 | ||
12241 | /* The .file directive; just like the usual .file directive, but there | |
12242 | is an initial number which is the ECOFF file index. */ | |
12243 | ||
12244 | static void | |
12245 | s_file (x) | |
12246 | int x; | |
12247 | { | |
670a50eb | 12248 | int line; |
3d3c5039 | 12249 | |
670a50eb | 12250 | line = get_number (); |
9a7d824a | 12251 | s_app_file (0); |
3d3c5039 ILT |
12252 | } |
12253 | ||
12254 | ||
12255 | /* The .end directive. */ | |
12256 | ||
12257 | static void | |
993b4e8d | 12258 | s_mips_end (x) |
3d3c5039 ILT |
12259 | int x; |
12260 | { | |
670a50eb | 12261 | symbolS *p; |
993b4e8d | 12262 | int maybe_text; |
670a50eb ILT |
12263 | |
12264 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
12265 | { | |
12266 | p = get_symbol (); | |
12267 | demand_empty_rest_of_line (); | |
12268 | } | |
12269 | else | |
12270 | p = NULL; | |
993b4e8d RU |
12271 | |
12272 | #ifdef BFD_ASSEMBLER | |
12273 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
12274 | maybe_text = 1; | |
12275 | else | |
12276 | maybe_text = 0; | |
12277 | #else | |
12278 | if (now_seg != data_section && now_seg != bss_section) | |
12279 | maybe_text = 1; | |
12280 | else | |
12281 | maybe_text = 0; | |
12282 | #endif | |
12283 | ||
12284 | if (!maybe_text) | |
48401fcf | 12285 | as_warn (_(".end not in text section")); |
993b4e8d RU |
12286 | |
12287 | if (!cur_proc_ptr) | |
670a50eb | 12288 | { |
993b4e8d RU |
12289 | as_warn (_(".end directive without a preceding .ent directive.")); |
12290 | demand_empty_rest_of_line (); | |
670a50eb | 12291 | return; |
3d3c5039 ILT |
12292 | } |
12293 | ||
670a50eb ILT |
12294 | if (p != NULL) |
12295 | { | |
12296 | assert (S_GET_NAME (p)); | |
993b4e8d | 12297 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) |
48401fcf | 12298 | as_warn (_(".end symbol does not match .ent symbol.")); |
3d3c5039 | 12299 | } |
993b4e8d RU |
12300 | else |
12301 | as_warn (_(".end directive missing or unknown symbol")); | |
12302 | ||
12303 | #ifdef MIPS_STABS_ELF | |
12304 | { | |
12305 | segT saved_seg = now_seg; | |
12306 | subsegT saved_subseg = now_subseg; | |
12307 | fragS *saved_frag = frag_now; | |
12308 | valueT dot; | |
12309 | segT seg; | |
12310 | expressionS exp; | |
12311 | char *fragp; | |
12312 | ||
12313 | dot = frag_now_fix (); | |
12314 | ||
12315 | #ifdef md_flush_pending_output | |
12316 | md_flush_pending_output (); | |
12317 | #endif | |
12318 | ||
12319 | assert (pdr_seg); | |
12320 | subseg_set (pdr_seg, 0); | |
12321 | ||
12322 | /* Write the symbol */ | |
12323 | exp.X_op = O_symbol; | |
12324 | exp.X_add_symbol = p; | |
12325 | exp.X_add_number = 0; | |
12326 | emit_expr (&exp, 4); | |
3d3c5039 | 12327 | |
993b4e8d RU |
12328 | fragp = frag_more (7*4); |
12329 | ||
12330 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); | |
12331 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); | |
12332 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); | |
12333 | md_number_to_chars (fragp +12, (valueT) cur_proc_ptr->fpreg_offset, 4); | |
12334 | md_number_to_chars (fragp +16, (valueT) cur_proc_ptr->frame_offset, 4); | |
12335 | md_number_to_chars (fragp +20, (valueT) cur_proc_ptr->frame_reg, 4); | |
12336 | md_number_to_chars (fragp +24, (valueT) cur_proc_ptr->pc_reg, 4); | |
12337 | ||
12338 | subseg_set (saved_seg, saved_subseg); | |
12339 | } | |
12340 | #endif | |
12341 | ||
12342 | cur_proc_ptr = NULL; | |
3d3c5039 ILT |
12343 | } |
12344 | ||
12345 | /* The .aent and .ent directives. */ | |
12346 | ||
12347 | static void | |
993b4e8d | 12348 | s_mips_ent (aent) |
3d3c5039 ILT |
12349 | int aent; |
12350 | { | |
670a50eb | 12351 | int number = 0; |
670a50eb | 12352 | symbolS *symbolP; |
993b4e8d | 12353 | int maybe_text; |
670a50eb ILT |
12354 | |
12355 | symbolP = get_symbol (); | |
12356 | if (*input_line_pointer == ',') | |
12357 | input_line_pointer++; | |
dd3f1f76 | 12358 | SKIP_WHITESPACE (); |
670a50eb ILT |
12359 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
12360 | number = get_number (); | |
993b4e8d RU |
12361 | |
12362 | #ifdef BFD_ASSEMBLER | |
12363 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
12364 | maybe_text = 1; | |
12365 | else | |
12366 | maybe_text = 0; | |
12367 | #else | |
12368 | if (now_seg != data_section && now_seg != bss_section) | |
12369 | maybe_text = 1; | |
12370 | else | |
12371 | maybe_text = 0; | |
12372 | #endif | |
12373 | ||
12374 | if (!maybe_text) | |
48401fcf | 12375 | as_warn (_(".ent or .aent not in text section.")); |
670a50eb | 12376 | |
993b4e8d | 12377 | if (!aent && cur_proc_ptr) |
48401fcf | 12378 | as_warn (_("missing `.end'")); |
670a50eb ILT |
12379 | |
12380 | if (!aent) | |
12381 | { | |
993b4e8d RU |
12382 | cur_proc_ptr = &cur_proc; |
12383 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
12384 | ||
12385 | cur_proc_ptr->isym = symbolP; | |
6b34ac5a ILT |
12386 | |
12387 | symbolP->bsym->flags |= BSF_FUNCTION; | |
12388 | ||
670a50eb | 12389 | numprocs++; |
3d3c5039 | 12390 | } |
993b4e8d | 12391 | |
670a50eb | 12392 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
12393 | } |
12394 | ||
993b4e8d RU |
12395 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) |
12396 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, | |
12397 | s_mips_frame is used so that we can set the PDR information correctly. | |
12398 | We can't use the ecoff routines because they make reference to the ecoff | |
12399 | symbol table (in the mdebug section). */ | |
3d3c5039 ILT |
12400 | |
12401 | static void | |
993b4e8d RU |
12402 | s_mips_frame (ignore) |
12403 | int ignore; | |
3d3c5039 | 12404 | { |
993b4e8d | 12405 | #ifdef MIPS_STABS_ELF |
670a50eb | 12406 | |
993b4e8d RU |
12407 | long val; |
12408 | ||
12409 | if (cur_proc_ptr == (procS *) NULL) | |
12410 | { | |
12411 | as_warn (_(".frame outside of .ent")); | |
12412 | demand_empty_rest_of_line (); | |
12413 | return; | |
3d3c5039 | 12414 | } |
993b4e8d RU |
12415 | |
12416 | cur_proc_ptr->frame_reg = tc_get_register (1); | |
12417 | ||
12418 | SKIP_WHITESPACE (); | |
12419 | if (*input_line_pointer++ != ',' | |
12420 | || get_absolute_expression_and_terminator (&val) != ',') | |
12421 | { | |
12422 | as_warn (_("Bad .frame directive")); | |
12423 | --input_line_pointer; | |
12424 | demand_empty_rest_of_line (); | |
12425 | return; | |
12426 | } | |
12427 | ||
12428 | cur_proc_ptr->frame_offset = val; | |
12429 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
12430 | ||
670a50eb | 12431 | demand_empty_rest_of_line (); |
993b4e8d RU |
12432 | #else |
12433 | s_ignore (ignore); | |
12434 | #endif /* MIPS_STABS_ELF */ | |
3d3c5039 ILT |
12435 | } |
12436 | ||
993b4e8d RU |
12437 | /* The .fmask and .mask directives. If the mdebug section is present |
12438 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
12439 | embedded targets, s_mips_mask is used so that we can set the PDR | |
12440 | information correctly. We can't use the ecoff routines because they | |
12441 | make reference to the ecoff symbol table (in the mdebug section). */ | |
3d3c5039 ILT |
12442 | |
12443 | static void | |
993b4e8d | 12444 | s_mips_mask (reg_type) |
3d3c5039 ILT |
12445 | char reg_type; |
12446 | { | |
993b4e8d RU |
12447 | #ifdef MIPS_STABS_ELF |
12448 | long mask, off; | |
12449 | ||
12450 | if (cur_proc_ptr == (procS *) NULL) | |
12451 | { | |
12452 | as_warn (_(".mask/.fmask outside of .ent")); | |
12453 | demand_empty_rest_of_line (); | |
12454 | return; | |
12455 | } | |
12456 | ||
12457 | if (get_absolute_expression_and_terminator (&mask) != ',') | |
12458 | { | |
12459 | as_warn (_("Bad .mask/.fmask directive")); | |
12460 | --input_line_pointer; | |
12461 | demand_empty_rest_of_line (); | |
12462 | return; | |
12463 | } | |
670a50eb | 12464 | |
670a50eb ILT |
12465 | off = get_absolute_expression (); |
12466 | ||
670a50eb ILT |
12467 | if (reg_type == 'F') |
12468 | { | |
993b4e8d RU |
12469 | cur_proc_ptr->fpreg_mask = mask; |
12470 | cur_proc_ptr->fpreg_offset = off; | |
3d3c5039 | 12471 | } |
670a50eb ILT |
12472 | else |
12473 | { | |
993b4e8d RU |
12474 | cur_proc_ptr->reg_mask = mask; |
12475 | cur_proc_ptr->reg_offset = off; | |
670a50eb ILT |
12476 | } |
12477 | ||
993b4e8d RU |
12478 | demand_empty_rest_of_line (); |
12479 | #else | |
12480 | s_ignore (reg_type); | |
12481 | #endif /* MIPS_STABS_ELF */ | |
3d3c5039 ILT |
12482 | } |
12483 | ||
12484 | /* The .loc directive. */ | |
12485 | ||
88225433 | 12486 | #if 0 |
3d3c5039 ILT |
12487 | static void |
12488 | s_loc (x) | |
12489 | int x; | |
12490 | { | |
670a50eb ILT |
12491 | symbolS *symbolP; |
12492 | int lineno; | |
12493 | int addroff; | |
3d3c5039 | 12494 | |
670a50eb | 12495 | assert (now_seg == text_section); |
3d3c5039 | 12496 | |
670a50eb | 12497 | lineno = get_number (); |
87e48495 | 12498 | addroff = frag_now_fix (); |
3d3c5039 | 12499 | |
670a50eb ILT |
12500 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
12501 | S_SET_TYPE (symbolP, N_SLINE); | |
12502 | S_SET_OTHER (symbolP, 0); | |
12503 | S_SET_DESC (symbolP, lineno); | |
12504 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 12505 | } |
88225433 | 12506 | #endif |
993b4e8d RU |
12507 | |
12508 | ||
12509 |