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252b5132 | 1 | /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000) |
250d07de | 2 | Copyright (C) 1994-2021 Free Software Foundation, Inc. |
252b5132 RH |
3 | Written by Ian Lance Taylor, Cygnus Support. |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
10 | any later version. |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
20 | 02110-1301, USA. */ | |
252b5132 | 21 | |
252b5132 | 22 | #include "as.h" |
3882b010 | 23 | #include "safe-ctype.h" |
252b5132 | 24 | #include "subsegs.h" |
75e21f08 | 25 | #include "dw2gencfi.h" |
252b5132 RH |
26 | #include "opcode/ppc.h" |
27 | ||
28 | #ifdef OBJ_ELF | |
29 | #include "elf/ppc.h" | |
ee67d69a | 30 | #include "elf/ppc64.h" |
5d6f4f16 | 31 | #include "dwarf2dbg.h" |
252b5132 RH |
32 | #endif |
33 | ||
85645aed TG |
34 | #ifdef OBJ_XCOFF |
35 | #include "coff/xcoff.h" | |
36 | #include "libxcoff.h" | |
37 | #endif | |
38 | ||
252b5132 RH |
39 | /* This is the assembler for the PowerPC or POWER (RS/6000) chips. */ |
40 | ||
41 | /* Tell the main code what the endianness is. */ | |
42 | extern int target_big_endian; | |
43 | ||
44 | /* Whether or not, we've set target_big_endian. */ | |
45 | static int set_target_endian = 0; | |
46 | ||
47 | /* Whether to use user friendly register names. */ | |
48 | #ifndef TARGET_REG_NAMES_P | |
b34976b6 | 49 | #define TARGET_REG_NAMES_P FALSE |
252b5132 | 50 | #endif |
252b5132 | 51 | |
0baf16f2 AM |
52 | /* Macros for calculating LO, HI, HA, HIGHER, HIGHERA, HIGHEST, |
53 | HIGHESTA. */ | |
54 | ||
55 | /* #lo(value) denotes the least significant 16 bits of the indicated. */ | |
56 | #define PPC_LO(v) ((v) & 0xffff) | |
57 | ||
58 | /* #hi(value) denotes bits 16 through 31 of the indicated value. */ | |
59 | #define PPC_HI(v) (((v) >> 16) & 0xffff) | |
60 | ||
61 | /* #ha(value) denotes the high adjusted value: bits 16 through 31 of | |
62 | the indicated value, compensating for #lo() being treated as a | |
63 | signed number. */ | |
15c1449b | 64 | #define PPC_HA(v) PPC_HI ((v) + 0x8000) |
0baf16f2 AM |
65 | |
66 | /* #higher(value) denotes bits 32 through 47 of the indicated value. */ | |
2a98c3a6 | 67 | #define PPC_HIGHER(v) (((v) >> 16 >> 16) & 0xffff) |
0baf16f2 AM |
68 | |
69 | /* #highera(value) denotes bits 32 through 47 of the indicated value, | |
70 | compensating for #lo() being treated as a signed number. */ | |
15c1449b | 71 | #define PPC_HIGHERA(v) PPC_HIGHER ((v) + 0x8000) |
0baf16f2 AM |
72 | |
73 | /* #highest(value) denotes bits 48 through 63 of the indicated value. */ | |
2a98c3a6 | 74 | #define PPC_HIGHEST(v) (((v) >> 24 >> 24) & 0xffff) |
0baf16f2 AM |
75 | |
76 | /* #highesta(value) denotes bits 48 through 63 of the indicated value, | |
15c1449b AM |
77 | compensating for #lo being treated as a signed number. */ |
78 | #define PPC_HIGHESTA(v) PPC_HIGHEST ((v) + 0x8000) | |
0baf16f2 | 79 | |
f9c6b907 AM |
80 | #define SEX16(val) (((val) ^ 0x8000) - 0x8000) |
81 | ||
82 | /* For the time being on ppc64, don't report overflow on @h and @ha | |
83 | applied to constants. */ | |
84 | #define REPORT_OVERFLOW_HI 0 | |
0baf16f2 | 85 | |
b34976b6 | 86 | static bfd_boolean reg_names_p = TARGET_REG_NAMES_P; |
252b5132 | 87 | |
98027b10 AM |
88 | static void ppc_macro (char *, const struct powerpc_macro *); |
89 | static void ppc_byte (int); | |
0baf16f2 AM |
90 | |
91 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) | |
98027b10 AM |
92 | static void ppc_tc (int); |
93 | static void ppc_machine (int); | |
0baf16f2 | 94 | #endif |
252b5132 RH |
95 | |
96 | #ifdef OBJ_XCOFF | |
98027b10 AM |
97 | static void ppc_comm (int); |
98 | static void ppc_bb (int); | |
99 | static void ppc_bc (int); | |
100 | static void ppc_bf (int); | |
101 | static void ppc_biei (int); | |
102 | static void ppc_bs (int); | |
103 | static void ppc_eb (int); | |
104 | static void ppc_ec (int); | |
105 | static void ppc_ef (int); | |
106 | static void ppc_es (int); | |
107 | static void ppc_csect (int); | |
85645aed | 108 | static void ppc_dwsect (int); |
98027b10 AM |
109 | static void ppc_change_csect (symbolS *, offsetT); |
110 | static void ppc_function (int); | |
111 | static void ppc_extern (int); | |
112 | static void ppc_lglobl (int); | |
c865e45b | 113 | static void ppc_ref (int); |
98027b10 AM |
114 | static void ppc_section (int); |
115 | static void ppc_named_section (int); | |
116 | static void ppc_stabx (int); | |
117 | static void ppc_rename (int); | |
118 | static void ppc_toc (int); | |
119 | static void ppc_xcoff_cons (int); | |
120 | static void ppc_vbyte (int); | |
252b5132 RH |
121 | #endif |
122 | ||
123 | #ifdef OBJ_ELF | |
98027b10 AM |
124 | static void ppc_elf_rdata (int); |
125 | static void ppc_elf_lcomm (int); | |
6911b7dc | 126 | static void ppc_elf_localentry (int); |
ee67d69a | 127 | static void ppc_elf_abiversion (int); |
005d79fd | 128 | static void ppc_elf_gnu_attribute (int); |
252b5132 | 129 | #endif |
252b5132 RH |
130 | \f |
131 | /* Generic assembler global variables which must be defined by all | |
132 | targets. */ | |
133 | ||
134 | #ifdef OBJ_ELF | |
135 | /* This string holds the chars that always start a comment. If the | |
136 | pre-processor is disabled, these aren't very useful. The macro | |
137 | tc_comment_chars points to this. We use this, rather than the | |
138 | usual comment_chars, so that we can switch for Solaris conventions. */ | |
139 | static const char ppc_solaris_comment_chars[] = "#!"; | |
140 | static const char ppc_eabi_comment_chars[] = "#"; | |
141 | ||
142 | #ifdef TARGET_SOLARIS_COMMENT | |
143 | const char *ppc_comment_chars = ppc_solaris_comment_chars; | |
144 | #else | |
145 | const char *ppc_comment_chars = ppc_eabi_comment_chars; | |
146 | #endif | |
147 | #else | |
148 | const char comment_chars[] = "#"; | |
149 | #endif | |
150 | ||
151 | /* Characters which start a comment at the beginning of a line. */ | |
152 | const char line_comment_chars[] = "#"; | |
153 | ||
154 | /* Characters which may be used to separate multiple commands on a | |
155 | single line. */ | |
156 | const char line_separator_chars[] = ";"; | |
157 | ||
158 | /* Characters which are used to indicate an exponent in a floating | |
159 | point number. */ | |
160 | const char EXP_CHARS[] = "eE"; | |
161 | ||
162 | /* Characters which mean that a number is a floating point constant, | |
163 | as in 0d1.0. */ | |
164 | const char FLT_CHARS[] = "dD"; | |
5ce8663f | 165 | |
5e02f92e | 166 | /* Anything that can start an operand needs to be mentioned here, |
ac805826 | 167 | to stop the input scrubber eating whitespace. */ |
5e02f92e | 168 | const char ppc_symbol_chars[] = "%["; |
75e21f08 JJ |
169 | |
170 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
171 | int ppc_cie_data_alignment; | |
783de163 | 172 | |
8fbf7334 JL |
173 | /* The dwarf2 minimum instruction length. */ |
174 | int ppc_dwarf2_line_min_insn_length; | |
175 | ||
cef4f754 AM |
176 | /* More than this number of nops in an alignment op gets a branch |
177 | instead. */ | |
178 | unsigned long nop_limit = 4; | |
179 | ||
783de163 AM |
180 | /* The type of processor we are assembling for. This is one or more |
181 | of the PPC_OPCODE flags defined in opcode/ppc.h. */ | |
fa452fa6 | 182 | ppc_cpu_t ppc_cpu = 0; |
776fc418 | 183 | ppc_cpu_t sticky = 0; |
01efc3af | 184 | |
ee67d69a AM |
185 | /* Value for ELF e_flags EF_PPC64_ABI. */ |
186 | unsigned int ppc_abiversion = 0; | |
187 | ||
05f7541e | 188 | #ifdef OBJ_ELF |
01efc3af | 189 | /* Flags set on encountering toc relocs. */ |
4f2a7b51 | 190 | static enum { |
01efc3af AM |
191 | has_large_toc_reloc = 1, |
192 | has_small_toc_reloc = 2 | |
193 | } toc_reloc_types; | |
05f7541e | 194 | #endif |
bf7279d5 AM |
195 | |
196 | /* Warn on emitting data to code sections. */ | |
197 | int warn_476; | |
0f873fd5 | 198 | uint64_t last_insn; |
bf7279d5 AM |
199 | segT last_seg; |
200 | subsegT last_subseg; | |
252b5132 RH |
201 | \f |
202 | /* The target specific pseudo-ops which we support. */ | |
203 | ||
204 | const pseudo_typeS md_pseudo_table[] = | |
205 | { | |
206 | /* Pseudo-ops which must be overridden. */ | |
207 | { "byte", ppc_byte, 0 }, | |
208 | ||
209 | #ifdef OBJ_XCOFF | |
210 | /* Pseudo-ops specific to the RS/6000 XCOFF format. Some of these | |
211 | legitimately belong in the obj-*.c file. However, XCOFF is based | |
212 | on COFF, and is only implemented for the RS/6000. We just use | |
213 | obj-coff.c, and add what we need here. */ | |
214 | { "comm", ppc_comm, 0 }, | |
215 | { "lcomm", ppc_comm, 1 }, | |
216 | { "bb", ppc_bb, 0 }, | |
217 | { "bc", ppc_bc, 0 }, | |
218 | { "bf", ppc_bf, 0 }, | |
219 | { "bi", ppc_biei, 0 }, | |
220 | { "bs", ppc_bs, 0 }, | |
221 | { "csect", ppc_csect, 0 }, | |
85645aed | 222 | { "dwsect", ppc_dwsect, 0 }, |
252b5132 RH |
223 | { "data", ppc_section, 'd' }, |
224 | { "eb", ppc_eb, 0 }, | |
225 | { "ec", ppc_ec, 0 }, | |
226 | { "ef", ppc_ef, 0 }, | |
227 | { "ei", ppc_biei, 1 }, | |
228 | { "es", ppc_es, 0 }, | |
229 | { "extern", ppc_extern, 0 }, | |
230 | { "function", ppc_function, 0 }, | |
231 | { "lglobl", ppc_lglobl, 0 }, | |
c865e45b | 232 | { "ref", ppc_ref, 0 }, |
252b5132 RH |
233 | { "rename", ppc_rename, 0 }, |
234 | { "section", ppc_named_section, 0 }, | |
235 | { "stabx", ppc_stabx, 0 }, | |
236 | { "text", ppc_section, 't' }, | |
237 | { "toc", ppc_toc, 0 }, | |
238 | { "long", ppc_xcoff_cons, 2 }, | |
7f6d05e8 | 239 | { "llong", ppc_xcoff_cons, 3 }, |
252b5132 RH |
240 | { "word", ppc_xcoff_cons, 1 }, |
241 | { "short", ppc_xcoff_cons, 1 }, | |
242 | { "vbyte", ppc_vbyte, 0 }, | |
243 | #endif | |
244 | ||
245 | #ifdef OBJ_ELF | |
62ebcb5c | 246 | { "llong", cons, 8 }, |
252b5132 RH |
247 | { "rdata", ppc_elf_rdata, 0 }, |
248 | { "rodata", ppc_elf_rdata, 0 }, | |
249 | { "lcomm", ppc_elf_lcomm, 0 }, | |
6911b7dc | 250 | { "localentry", ppc_elf_localentry, 0 }, |
ee67d69a | 251 | { "abiversion", ppc_elf_abiversion, 0 }, |
005d79fd | 252 | { "gnu_attribute", ppc_elf_gnu_attribute, 0}, |
252b5132 RH |
253 | #endif |
254 | ||
0baf16f2 | 255 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
252b5132 | 256 | { "tc", ppc_tc, 0 }, |
0baf16f2 AM |
257 | { "machine", ppc_machine, 0 }, |
258 | #endif | |
252b5132 RH |
259 | |
260 | { NULL, NULL, 0 } | |
261 | }; | |
262 | ||
263 | \f | |
99a814a1 AM |
264 | /* Predefined register names if -mregnames (or default for Windows NT). |
265 | In general, there are lots of them, in an attempt to be compatible | |
266 | with a number of other Windows NT assemblers. */ | |
252b5132 RH |
267 | |
268 | /* Structure to hold information about predefined registers. */ | |
269 | struct pd_reg | |
270 | { | |
e0471c16 | 271 | const char *name; |
7e0de605 AM |
272 | unsigned short value; |
273 | unsigned short flags; | |
252b5132 RH |
274 | }; |
275 | ||
276 | /* List of registers that are pre-defined: | |
277 | ||
278 | Each general register has predefined names of the form: | |
279 | 1. r<reg_num> which has the value <reg_num>. | |
280 | 2. r.<reg_num> which has the value <reg_num>. | |
281 | ||
252b5132 RH |
282 | Each floating point register has predefined names of the form: |
283 | 1. f<reg_num> which has the value <reg_num>. | |
284 | 2. f.<reg_num> which has the value <reg_num>. | |
285 | ||
7a899fff C |
286 | Each vector unit register has predefined names of the form: |
287 | 1. v<reg_num> which has the value <reg_num>. | |
288 | 2. v.<reg_num> which has the value <reg_num>. | |
289 | ||
252b5132 RH |
290 | Each condition register has predefined names of the form: |
291 | 1. cr<reg_num> which has the value <reg_num>. | |
292 | 2. cr.<reg_num> which has the value <reg_num>. | |
293 | ||
294 | There are individual registers as well: | |
295 | sp or r.sp has the value 1 | |
296 | rtoc or r.toc has the value 2 | |
252b5132 RH |
297 | xer has the value 1 |
298 | lr has the value 8 | |
299 | ctr has the value 9 | |
252b5132 RH |
300 | dar has the value 19 |
301 | dsisr has the value 18 | |
302 | dec has the value 22 | |
303 | sdr1 has the value 25 | |
304 | srr0 has the value 26 | |
305 | srr1 has the value 27 | |
306 | ||
81d4177b | 307 | The table is sorted. Suitable for searching by a binary search. */ |
252b5132 RH |
308 | |
309 | static const struct pd_reg pre_defined_registers[] = | |
310 | { | |
aa3c112f AM |
311 | /* VSX accumulators. */ |
312 | { "a0", 0, PPC_OPERAND_ACC }, | |
313 | { "a1", 1, PPC_OPERAND_ACC }, | |
314 | { "a2", 2, PPC_OPERAND_ACC }, | |
315 | { "a3", 3, PPC_OPERAND_ACC }, | |
316 | { "a4", 4, PPC_OPERAND_ACC }, | |
317 | { "a5", 5, PPC_OPERAND_ACC }, | |
318 | { "a6", 6, PPC_OPERAND_ACC }, | |
319 | { "a7", 7, PPC_OPERAND_ACC }, | |
320 | ||
7e0de605 AM |
321 | /* Condition Registers */ |
322 | { "cr.0", 0, PPC_OPERAND_CR_REG }, | |
323 | { "cr.1", 1, PPC_OPERAND_CR_REG }, | |
324 | { "cr.2", 2, PPC_OPERAND_CR_REG }, | |
325 | { "cr.3", 3, PPC_OPERAND_CR_REG }, | |
326 | { "cr.4", 4, PPC_OPERAND_CR_REG }, | |
327 | { "cr.5", 5, PPC_OPERAND_CR_REG }, | |
328 | { "cr.6", 6, PPC_OPERAND_CR_REG }, | |
329 | { "cr.7", 7, PPC_OPERAND_CR_REG }, | |
330 | ||
331 | { "cr0", 0, PPC_OPERAND_CR_REG }, | |
332 | { "cr1", 1, PPC_OPERAND_CR_REG }, | |
333 | { "cr2", 2, PPC_OPERAND_CR_REG }, | |
334 | { "cr3", 3, PPC_OPERAND_CR_REG }, | |
335 | { "cr4", 4, PPC_OPERAND_CR_REG }, | |
336 | { "cr5", 5, PPC_OPERAND_CR_REG }, | |
337 | { "cr6", 6, PPC_OPERAND_CR_REG }, | |
338 | { "cr7", 7, PPC_OPERAND_CR_REG }, | |
339 | ||
340 | { "ctr", 9, PPC_OPERAND_SPR }, | |
341 | { "dar", 19, PPC_OPERAND_SPR }, | |
342 | { "dec", 22, PPC_OPERAND_SPR }, | |
343 | { "dsisr", 18, PPC_OPERAND_SPR }, | |
344 | ||
345 | /* Floating point registers */ | |
346 | { "f.0", 0, PPC_OPERAND_FPR }, | |
347 | { "f.1", 1, PPC_OPERAND_FPR }, | |
348 | { "f.10", 10, PPC_OPERAND_FPR }, | |
349 | { "f.11", 11, PPC_OPERAND_FPR }, | |
350 | { "f.12", 12, PPC_OPERAND_FPR }, | |
351 | { "f.13", 13, PPC_OPERAND_FPR }, | |
352 | { "f.14", 14, PPC_OPERAND_FPR }, | |
353 | { "f.15", 15, PPC_OPERAND_FPR }, | |
354 | { "f.16", 16, PPC_OPERAND_FPR }, | |
355 | { "f.17", 17, PPC_OPERAND_FPR }, | |
356 | { "f.18", 18, PPC_OPERAND_FPR }, | |
357 | { "f.19", 19, PPC_OPERAND_FPR }, | |
358 | { "f.2", 2, PPC_OPERAND_FPR }, | |
359 | { "f.20", 20, PPC_OPERAND_FPR }, | |
360 | { "f.21", 21, PPC_OPERAND_FPR }, | |
361 | { "f.22", 22, PPC_OPERAND_FPR }, | |
362 | { "f.23", 23, PPC_OPERAND_FPR }, | |
363 | { "f.24", 24, PPC_OPERAND_FPR }, | |
364 | { "f.25", 25, PPC_OPERAND_FPR }, | |
365 | { "f.26", 26, PPC_OPERAND_FPR }, | |
366 | { "f.27", 27, PPC_OPERAND_FPR }, | |
367 | { "f.28", 28, PPC_OPERAND_FPR }, | |
368 | { "f.29", 29, PPC_OPERAND_FPR }, | |
369 | { "f.3", 3, PPC_OPERAND_FPR }, | |
370 | { "f.30", 30, PPC_OPERAND_FPR }, | |
371 | { "f.31", 31, PPC_OPERAND_FPR }, | |
372 | { "f.32", 32, PPC_OPERAND_VSR }, | |
373 | { "f.33", 33, PPC_OPERAND_VSR }, | |
374 | { "f.34", 34, PPC_OPERAND_VSR }, | |
375 | { "f.35", 35, PPC_OPERAND_VSR }, | |
376 | { "f.36", 36, PPC_OPERAND_VSR }, | |
377 | { "f.37", 37, PPC_OPERAND_VSR }, | |
378 | { "f.38", 38, PPC_OPERAND_VSR }, | |
379 | { "f.39", 39, PPC_OPERAND_VSR }, | |
380 | { "f.4", 4, PPC_OPERAND_FPR }, | |
381 | { "f.40", 40, PPC_OPERAND_VSR }, | |
382 | { "f.41", 41, PPC_OPERAND_VSR }, | |
383 | { "f.42", 42, PPC_OPERAND_VSR }, | |
384 | { "f.43", 43, PPC_OPERAND_VSR }, | |
385 | { "f.44", 44, PPC_OPERAND_VSR }, | |
386 | { "f.45", 45, PPC_OPERAND_VSR }, | |
387 | { "f.46", 46, PPC_OPERAND_VSR }, | |
388 | { "f.47", 47, PPC_OPERAND_VSR }, | |
389 | { "f.48", 48, PPC_OPERAND_VSR }, | |
390 | { "f.49", 49, PPC_OPERAND_VSR }, | |
391 | { "f.5", 5, PPC_OPERAND_FPR }, | |
392 | { "f.50", 50, PPC_OPERAND_VSR }, | |
393 | { "f.51", 51, PPC_OPERAND_VSR }, | |
394 | { "f.52", 52, PPC_OPERAND_VSR }, | |
395 | { "f.53", 53, PPC_OPERAND_VSR }, | |
396 | { "f.54", 54, PPC_OPERAND_VSR }, | |
397 | { "f.55", 55, PPC_OPERAND_VSR }, | |
398 | { "f.56", 56, PPC_OPERAND_VSR }, | |
399 | { "f.57", 57, PPC_OPERAND_VSR }, | |
400 | { "f.58", 58, PPC_OPERAND_VSR }, | |
401 | { "f.59", 59, PPC_OPERAND_VSR }, | |
402 | { "f.6", 6, PPC_OPERAND_FPR }, | |
403 | { "f.60", 60, PPC_OPERAND_VSR }, | |
404 | { "f.61", 61, PPC_OPERAND_VSR }, | |
405 | { "f.62", 62, PPC_OPERAND_VSR }, | |
406 | { "f.63", 63, PPC_OPERAND_VSR }, | |
407 | { "f.7", 7, PPC_OPERAND_FPR }, | |
408 | { "f.8", 8, PPC_OPERAND_FPR }, | |
409 | { "f.9", 9, PPC_OPERAND_FPR }, | |
410 | ||
411 | { "f0", 0, PPC_OPERAND_FPR }, | |
412 | { "f1", 1, PPC_OPERAND_FPR }, | |
413 | { "f10", 10, PPC_OPERAND_FPR }, | |
414 | { "f11", 11, PPC_OPERAND_FPR }, | |
415 | { "f12", 12, PPC_OPERAND_FPR }, | |
416 | { "f13", 13, PPC_OPERAND_FPR }, | |
417 | { "f14", 14, PPC_OPERAND_FPR }, | |
418 | { "f15", 15, PPC_OPERAND_FPR }, | |
419 | { "f16", 16, PPC_OPERAND_FPR }, | |
420 | { "f17", 17, PPC_OPERAND_FPR }, | |
421 | { "f18", 18, PPC_OPERAND_FPR }, | |
422 | { "f19", 19, PPC_OPERAND_FPR }, | |
423 | { "f2", 2, PPC_OPERAND_FPR }, | |
424 | { "f20", 20, PPC_OPERAND_FPR }, | |
425 | { "f21", 21, PPC_OPERAND_FPR }, | |
426 | { "f22", 22, PPC_OPERAND_FPR }, | |
427 | { "f23", 23, PPC_OPERAND_FPR }, | |
428 | { "f24", 24, PPC_OPERAND_FPR }, | |
429 | { "f25", 25, PPC_OPERAND_FPR }, | |
430 | { "f26", 26, PPC_OPERAND_FPR }, | |
431 | { "f27", 27, PPC_OPERAND_FPR }, | |
432 | { "f28", 28, PPC_OPERAND_FPR }, | |
433 | { "f29", 29, PPC_OPERAND_FPR }, | |
434 | { "f3", 3, PPC_OPERAND_FPR }, | |
435 | { "f30", 30, PPC_OPERAND_FPR }, | |
436 | { "f31", 31, PPC_OPERAND_FPR }, | |
437 | { "f32", 32, PPC_OPERAND_VSR }, | |
438 | { "f33", 33, PPC_OPERAND_VSR }, | |
439 | { "f34", 34, PPC_OPERAND_VSR }, | |
440 | { "f35", 35, PPC_OPERAND_VSR }, | |
441 | { "f36", 36, PPC_OPERAND_VSR }, | |
442 | { "f37", 37, PPC_OPERAND_VSR }, | |
443 | { "f38", 38, PPC_OPERAND_VSR }, | |
444 | { "f39", 39, PPC_OPERAND_VSR }, | |
445 | { "f4", 4, PPC_OPERAND_FPR }, | |
446 | { "f40", 40, PPC_OPERAND_VSR }, | |
447 | { "f41", 41, PPC_OPERAND_VSR }, | |
448 | { "f42", 42, PPC_OPERAND_VSR }, | |
449 | { "f43", 43, PPC_OPERAND_VSR }, | |
450 | { "f44", 44, PPC_OPERAND_VSR }, | |
451 | { "f45", 45, PPC_OPERAND_VSR }, | |
452 | { "f46", 46, PPC_OPERAND_VSR }, | |
453 | { "f47", 47, PPC_OPERAND_VSR }, | |
454 | { "f48", 48, PPC_OPERAND_VSR }, | |
455 | { "f49", 49, PPC_OPERAND_VSR }, | |
456 | { "f5", 5, PPC_OPERAND_FPR }, | |
457 | { "f50", 50, PPC_OPERAND_VSR }, | |
458 | { "f51", 51, PPC_OPERAND_VSR }, | |
459 | { "f52", 52, PPC_OPERAND_VSR }, | |
460 | { "f53", 53, PPC_OPERAND_VSR }, | |
461 | { "f54", 54, PPC_OPERAND_VSR }, | |
462 | { "f55", 55, PPC_OPERAND_VSR }, | |
463 | { "f56", 56, PPC_OPERAND_VSR }, | |
464 | { "f57", 57, PPC_OPERAND_VSR }, | |
465 | { "f58", 58, PPC_OPERAND_VSR }, | |
466 | { "f59", 59, PPC_OPERAND_VSR }, | |
467 | { "f6", 6, PPC_OPERAND_FPR }, | |
468 | { "f60", 60, PPC_OPERAND_VSR }, | |
469 | { "f61", 61, PPC_OPERAND_VSR }, | |
470 | { "f62", 62, PPC_OPERAND_VSR }, | |
471 | { "f63", 63, PPC_OPERAND_VSR }, | |
472 | { "f7", 7, PPC_OPERAND_FPR }, | |
473 | { "f8", 8, PPC_OPERAND_FPR }, | |
474 | { "f9", 9, PPC_OPERAND_FPR }, | |
252b5132 | 475 | |
c3d65c1c | 476 | /* Quantization registers used with pair single instructions. */ |
7e0de605 AM |
477 | { "gqr.0", 0, PPC_OPERAND_GQR }, |
478 | { "gqr.1", 1, PPC_OPERAND_GQR }, | |
479 | { "gqr.2", 2, PPC_OPERAND_GQR }, | |
480 | { "gqr.3", 3, PPC_OPERAND_GQR }, | |
481 | { "gqr.4", 4, PPC_OPERAND_GQR }, | |
482 | { "gqr.5", 5, PPC_OPERAND_GQR }, | |
483 | { "gqr.6", 6, PPC_OPERAND_GQR }, | |
484 | { "gqr.7", 7, PPC_OPERAND_GQR }, | |
485 | { "gqr0", 0, PPC_OPERAND_GQR }, | |
486 | { "gqr1", 1, PPC_OPERAND_GQR }, | |
487 | { "gqr2", 2, PPC_OPERAND_GQR }, | |
488 | { "gqr3", 3, PPC_OPERAND_GQR }, | |
489 | { "gqr4", 4, PPC_OPERAND_GQR }, | |
490 | { "gqr5", 5, PPC_OPERAND_GQR }, | |
491 | { "gqr6", 6, PPC_OPERAND_GQR }, | |
492 | { "gqr7", 7, PPC_OPERAND_GQR }, | |
493 | ||
494 | { "lr", 8, PPC_OPERAND_SPR }, | |
495 | ||
496 | /* General Purpose Registers */ | |
497 | { "r.0", 0, PPC_OPERAND_GPR }, | |
498 | { "r.1", 1, PPC_OPERAND_GPR }, | |
499 | { "r.10", 10, PPC_OPERAND_GPR }, | |
500 | { "r.11", 11, PPC_OPERAND_GPR }, | |
501 | { "r.12", 12, PPC_OPERAND_GPR }, | |
502 | { "r.13", 13, PPC_OPERAND_GPR }, | |
503 | { "r.14", 14, PPC_OPERAND_GPR }, | |
504 | { "r.15", 15, PPC_OPERAND_GPR }, | |
505 | { "r.16", 16, PPC_OPERAND_GPR }, | |
506 | { "r.17", 17, PPC_OPERAND_GPR }, | |
507 | { "r.18", 18, PPC_OPERAND_GPR }, | |
508 | { "r.19", 19, PPC_OPERAND_GPR }, | |
509 | { "r.2", 2, PPC_OPERAND_GPR }, | |
510 | { "r.20", 20, PPC_OPERAND_GPR }, | |
511 | { "r.21", 21, PPC_OPERAND_GPR }, | |
512 | { "r.22", 22, PPC_OPERAND_GPR }, | |
513 | { "r.23", 23, PPC_OPERAND_GPR }, | |
514 | { "r.24", 24, PPC_OPERAND_GPR }, | |
515 | { "r.25", 25, PPC_OPERAND_GPR }, | |
516 | { "r.26", 26, PPC_OPERAND_GPR }, | |
517 | { "r.27", 27, PPC_OPERAND_GPR }, | |
518 | { "r.28", 28, PPC_OPERAND_GPR }, | |
519 | { "r.29", 29, PPC_OPERAND_GPR }, | |
520 | { "r.3", 3, PPC_OPERAND_GPR }, | |
521 | { "r.30", 30, PPC_OPERAND_GPR }, | |
522 | { "r.31", 31, PPC_OPERAND_GPR }, | |
523 | { "r.4", 4, PPC_OPERAND_GPR }, | |
524 | { "r.5", 5, PPC_OPERAND_GPR }, | |
525 | { "r.6", 6, PPC_OPERAND_GPR }, | |
526 | { "r.7", 7, PPC_OPERAND_GPR }, | |
527 | { "r.8", 8, PPC_OPERAND_GPR }, | |
528 | { "r.9", 9, PPC_OPERAND_GPR }, | |
529 | ||
530 | { "r.sp", 1, PPC_OPERAND_GPR }, | |
531 | ||
532 | { "r.toc", 2, PPC_OPERAND_GPR }, | |
533 | ||
534 | { "r0", 0, PPC_OPERAND_GPR }, | |
535 | { "r1", 1, PPC_OPERAND_GPR }, | |
536 | { "r10", 10, PPC_OPERAND_GPR }, | |
537 | { "r11", 11, PPC_OPERAND_GPR }, | |
538 | { "r12", 12, PPC_OPERAND_GPR }, | |
539 | { "r13", 13, PPC_OPERAND_GPR }, | |
540 | { "r14", 14, PPC_OPERAND_GPR }, | |
541 | { "r15", 15, PPC_OPERAND_GPR }, | |
542 | { "r16", 16, PPC_OPERAND_GPR }, | |
543 | { "r17", 17, PPC_OPERAND_GPR }, | |
544 | { "r18", 18, PPC_OPERAND_GPR }, | |
545 | { "r19", 19, PPC_OPERAND_GPR }, | |
546 | { "r2", 2, PPC_OPERAND_GPR }, | |
547 | { "r20", 20, PPC_OPERAND_GPR }, | |
548 | { "r21", 21, PPC_OPERAND_GPR }, | |
549 | { "r22", 22, PPC_OPERAND_GPR }, | |
550 | { "r23", 23, PPC_OPERAND_GPR }, | |
551 | { "r24", 24, PPC_OPERAND_GPR }, | |
552 | { "r25", 25, PPC_OPERAND_GPR }, | |
553 | { "r26", 26, PPC_OPERAND_GPR }, | |
554 | { "r27", 27, PPC_OPERAND_GPR }, | |
555 | { "r28", 28, PPC_OPERAND_GPR }, | |
556 | { "r29", 29, PPC_OPERAND_GPR }, | |
557 | { "r3", 3, PPC_OPERAND_GPR }, | |
558 | { "r30", 30, PPC_OPERAND_GPR }, | |
559 | { "r31", 31, PPC_OPERAND_GPR }, | |
560 | { "r4", 4, PPC_OPERAND_GPR }, | |
561 | { "r5", 5, PPC_OPERAND_GPR }, | |
562 | { "r6", 6, PPC_OPERAND_GPR }, | |
563 | { "r7", 7, PPC_OPERAND_GPR }, | |
564 | { "r8", 8, PPC_OPERAND_GPR }, | |
565 | { "r9", 9, PPC_OPERAND_GPR }, | |
566 | ||
567 | { "rtoc", 2, PPC_OPERAND_GPR }, | |
568 | ||
569 | { "sdr1", 25, PPC_OPERAND_SPR }, | |
570 | ||
571 | { "sp", 1, PPC_OPERAND_GPR }, | |
572 | ||
573 | { "srr0", 26, PPC_OPERAND_SPR }, | |
574 | { "srr1", 27, PPC_OPERAND_SPR }, | |
575 | ||
576 | /* Vector (Altivec/VMX) registers */ | |
577 | { "v.0", 0, PPC_OPERAND_VR }, | |
578 | { "v.1", 1, PPC_OPERAND_VR }, | |
579 | { "v.10", 10, PPC_OPERAND_VR }, | |
580 | { "v.11", 11, PPC_OPERAND_VR }, | |
581 | { "v.12", 12, PPC_OPERAND_VR }, | |
582 | { "v.13", 13, PPC_OPERAND_VR }, | |
583 | { "v.14", 14, PPC_OPERAND_VR }, | |
584 | { "v.15", 15, PPC_OPERAND_VR }, | |
585 | { "v.16", 16, PPC_OPERAND_VR }, | |
586 | { "v.17", 17, PPC_OPERAND_VR }, | |
587 | { "v.18", 18, PPC_OPERAND_VR }, | |
588 | { "v.19", 19, PPC_OPERAND_VR }, | |
589 | { "v.2", 2, PPC_OPERAND_VR }, | |
590 | { "v.20", 20, PPC_OPERAND_VR }, | |
591 | { "v.21", 21, PPC_OPERAND_VR }, | |
592 | { "v.22", 22, PPC_OPERAND_VR }, | |
593 | { "v.23", 23, PPC_OPERAND_VR }, | |
594 | { "v.24", 24, PPC_OPERAND_VR }, | |
595 | { "v.25", 25, PPC_OPERAND_VR }, | |
596 | { "v.26", 26, PPC_OPERAND_VR }, | |
597 | { "v.27", 27, PPC_OPERAND_VR }, | |
598 | { "v.28", 28, PPC_OPERAND_VR }, | |
599 | { "v.29", 29, PPC_OPERAND_VR }, | |
600 | { "v.3", 3, PPC_OPERAND_VR }, | |
601 | { "v.30", 30, PPC_OPERAND_VR }, | |
602 | { "v.31", 31, PPC_OPERAND_VR }, | |
603 | { "v.4", 4, PPC_OPERAND_VR }, | |
604 | { "v.5", 5, PPC_OPERAND_VR }, | |
605 | { "v.6", 6, PPC_OPERAND_VR }, | |
606 | { "v.7", 7, PPC_OPERAND_VR }, | |
607 | { "v.8", 8, PPC_OPERAND_VR }, | |
608 | { "v.9", 9, PPC_OPERAND_VR }, | |
609 | ||
610 | { "v0", 0, PPC_OPERAND_VR }, | |
611 | { "v1", 1, PPC_OPERAND_VR }, | |
612 | { "v10", 10, PPC_OPERAND_VR }, | |
613 | { "v11", 11, PPC_OPERAND_VR }, | |
614 | { "v12", 12, PPC_OPERAND_VR }, | |
615 | { "v13", 13, PPC_OPERAND_VR }, | |
616 | { "v14", 14, PPC_OPERAND_VR }, | |
617 | { "v15", 15, PPC_OPERAND_VR }, | |
618 | { "v16", 16, PPC_OPERAND_VR }, | |
619 | { "v17", 17, PPC_OPERAND_VR }, | |
620 | { "v18", 18, PPC_OPERAND_VR }, | |
621 | { "v19", 19, PPC_OPERAND_VR }, | |
622 | { "v2", 2, PPC_OPERAND_VR }, | |
623 | { "v20", 20, PPC_OPERAND_VR }, | |
624 | { "v21", 21, PPC_OPERAND_VR }, | |
625 | { "v22", 22, PPC_OPERAND_VR }, | |
626 | { "v23", 23, PPC_OPERAND_VR }, | |
627 | { "v24", 24, PPC_OPERAND_VR }, | |
628 | { "v25", 25, PPC_OPERAND_VR }, | |
629 | { "v26", 26, PPC_OPERAND_VR }, | |
630 | { "v27", 27, PPC_OPERAND_VR }, | |
631 | { "v28", 28, PPC_OPERAND_VR }, | |
632 | { "v29", 29, PPC_OPERAND_VR }, | |
633 | { "v3", 3, PPC_OPERAND_VR }, | |
634 | { "v30", 30, PPC_OPERAND_VR }, | |
635 | { "v31", 31, PPC_OPERAND_VR }, | |
636 | { "v4", 4, PPC_OPERAND_VR }, | |
637 | { "v5", 5, PPC_OPERAND_VR }, | |
638 | { "v6", 6, PPC_OPERAND_VR }, | |
639 | { "v7", 7, PPC_OPERAND_VR }, | |
640 | { "v8", 8, PPC_OPERAND_VR }, | |
641 | { "v9", 9, PPC_OPERAND_VR }, | |
642 | ||
643 | /* Vector Scalar (VSX) registers (ISA 2.06). */ | |
644 | { "vs.0", 0, PPC_OPERAND_VSR }, | |
645 | { "vs.1", 1, PPC_OPERAND_VSR }, | |
646 | { "vs.10", 10, PPC_OPERAND_VSR }, | |
647 | { "vs.11", 11, PPC_OPERAND_VSR }, | |
648 | { "vs.12", 12, PPC_OPERAND_VSR }, | |
649 | { "vs.13", 13, PPC_OPERAND_VSR }, | |
650 | { "vs.14", 14, PPC_OPERAND_VSR }, | |
651 | { "vs.15", 15, PPC_OPERAND_VSR }, | |
652 | { "vs.16", 16, PPC_OPERAND_VSR }, | |
653 | { "vs.17", 17, PPC_OPERAND_VSR }, | |
654 | { "vs.18", 18, PPC_OPERAND_VSR }, | |
655 | { "vs.19", 19, PPC_OPERAND_VSR }, | |
656 | { "vs.2", 2, PPC_OPERAND_VSR }, | |
657 | { "vs.20", 20, PPC_OPERAND_VSR }, | |
658 | { "vs.21", 21, PPC_OPERAND_VSR }, | |
659 | { "vs.22", 22, PPC_OPERAND_VSR }, | |
660 | { "vs.23", 23, PPC_OPERAND_VSR }, | |
661 | { "vs.24", 24, PPC_OPERAND_VSR }, | |
662 | { "vs.25", 25, PPC_OPERAND_VSR }, | |
663 | { "vs.26", 26, PPC_OPERAND_VSR }, | |
664 | { "vs.27", 27, PPC_OPERAND_VSR }, | |
665 | { "vs.28", 28, PPC_OPERAND_VSR }, | |
666 | { "vs.29", 29, PPC_OPERAND_VSR }, | |
667 | { "vs.3", 3, PPC_OPERAND_VSR }, | |
668 | { "vs.30", 30, PPC_OPERAND_VSR }, | |
669 | { "vs.31", 31, PPC_OPERAND_VSR }, | |
670 | { "vs.32", 32, PPC_OPERAND_VSR }, | |
671 | { "vs.33", 33, PPC_OPERAND_VSR }, | |
672 | { "vs.34", 34, PPC_OPERAND_VSR }, | |
673 | { "vs.35", 35, PPC_OPERAND_VSR }, | |
674 | { "vs.36", 36, PPC_OPERAND_VSR }, | |
675 | { "vs.37", 37, PPC_OPERAND_VSR }, | |
676 | { "vs.38", 38, PPC_OPERAND_VSR }, | |
677 | { "vs.39", 39, PPC_OPERAND_VSR }, | |
678 | { "vs.4", 4, PPC_OPERAND_VSR }, | |
679 | { "vs.40", 40, PPC_OPERAND_VSR }, | |
680 | { "vs.41", 41, PPC_OPERAND_VSR }, | |
681 | { "vs.42", 42, PPC_OPERAND_VSR }, | |
682 | { "vs.43", 43, PPC_OPERAND_VSR }, | |
683 | { "vs.44", 44, PPC_OPERAND_VSR }, | |
684 | { "vs.45", 45, PPC_OPERAND_VSR }, | |
685 | { "vs.46", 46, PPC_OPERAND_VSR }, | |
686 | { "vs.47", 47, PPC_OPERAND_VSR }, | |
687 | { "vs.48", 48, PPC_OPERAND_VSR }, | |
688 | { "vs.49", 49, PPC_OPERAND_VSR }, | |
689 | { "vs.5", 5, PPC_OPERAND_VSR }, | |
690 | { "vs.50", 50, PPC_OPERAND_VSR }, | |
691 | { "vs.51", 51, PPC_OPERAND_VSR }, | |
692 | { "vs.52", 52, PPC_OPERAND_VSR }, | |
693 | { "vs.53", 53, PPC_OPERAND_VSR }, | |
694 | { "vs.54", 54, PPC_OPERAND_VSR }, | |
695 | { "vs.55", 55, PPC_OPERAND_VSR }, | |
696 | { "vs.56", 56, PPC_OPERAND_VSR }, | |
697 | { "vs.57", 57, PPC_OPERAND_VSR }, | |
698 | { "vs.58", 58, PPC_OPERAND_VSR }, | |
699 | { "vs.59", 59, PPC_OPERAND_VSR }, | |
700 | { "vs.6", 6, PPC_OPERAND_VSR }, | |
701 | { "vs.60", 60, PPC_OPERAND_VSR }, | |
702 | { "vs.61", 61, PPC_OPERAND_VSR }, | |
703 | { "vs.62", 62, PPC_OPERAND_VSR }, | |
704 | { "vs.63", 63, PPC_OPERAND_VSR }, | |
705 | { "vs.7", 7, PPC_OPERAND_VSR }, | |
706 | { "vs.8", 8, PPC_OPERAND_VSR }, | |
707 | { "vs.9", 9, PPC_OPERAND_VSR }, | |
708 | ||
709 | { "vs0", 0, PPC_OPERAND_VSR }, | |
710 | { "vs1", 1, PPC_OPERAND_VSR }, | |
711 | { "vs10", 10, PPC_OPERAND_VSR }, | |
712 | { "vs11", 11, PPC_OPERAND_VSR }, | |
713 | { "vs12", 12, PPC_OPERAND_VSR }, | |
714 | { "vs13", 13, PPC_OPERAND_VSR }, | |
715 | { "vs14", 14, PPC_OPERAND_VSR }, | |
716 | { "vs15", 15, PPC_OPERAND_VSR }, | |
717 | { "vs16", 16, PPC_OPERAND_VSR }, | |
718 | { "vs17", 17, PPC_OPERAND_VSR }, | |
719 | { "vs18", 18, PPC_OPERAND_VSR }, | |
720 | { "vs19", 19, PPC_OPERAND_VSR }, | |
721 | { "vs2", 2, PPC_OPERAND_VSR }, | |
722 | { "vs20", 20, PPC_OPERAND_VSR }, | |
723 | { "vs21", 21, PPC_OPERAND_VSR }, | |
724 | { "vs22", 22, PPC_OPERAND_VSR }, | |
725 | { "vs23", 23, PPC_OPERAND_VSR }, | |
726 | { "vs24", 24, PPC_OPERAND_VSR }, | |
727 | { "vs25", 25, PPC_OPERAND_VSR }, | |
728 | { "vs26", 26, PPC_OPERAND_VSR }, | |
729 | { "vs27", 27, PPC_OPERAND_VSR }, | |
730 | { "vs28", 28, PPC_OPERAND_VSR }, | |
731 | { "vs29", 29, PPC_OPERAND_VSR }, | |
732 | { "vs3", 3, PPC_OPERAND_VSR }, | |
733 | { "vs30", 30, PPC_OPERAND_VSR }, | |
734 | { "vs31", 31, PPC_OPERAND_VSR }, | |
735 | { "vs32", 32, PPC_OPERAND_VSR }, | |
736 | { "vs33", 33, PPC_OPERAND_VSR }, | |
737 | { "vs34", 34, PPC_OPERAND_VSR }, | |
738 | { "vs35", 35, PPC_OPERAND_VSR }, | |
739 | { "vs36", 36, PPC_OPERAND_VSR }, | |
740 | { "vs37", 37, PPC_OPERAND_VSR }, | |
741 | { "vs38", 38, PPC_OPERAND_VSR }, | |
742 | { "vs39", 39, PPC_OPERAND_VSR }, | |
743 | { "vs4", 4, PPC_OPERAND_VSR }, | |
744 | { "vs40", 40, PPC_OPERAND_VSR }, | |
745 | { "vs41", 41, PPC_OPERAND_VSR }, | |
746 | { "vs42", 42, PPC_OPERAND_VSR }, | |
747 | { "vs43", 43, PPC_OPERAND_VSR }, | |
748 | { "vs44", 44, PPC_OPERAND_VSR }, | |
749 | { "vs45", 45, PPC_OPERAND_VSR }, | |
750 | { "vs46", 46, PPC_OPERAND_VSR }, | |
751 | { "vs47", 47, PPC_OPERAND_VSR }, | |
752 | { "vs48", 48, PPC_OPERAND_VSR }, | |
753 | { "vs49", 49, PPC_OPERAND_VSR }, | |
754 | { "vs5", 5, PPC_OPERAND_VSR }, | |
755 | { "vs50", 50, PPC_OPERAND_VSR }, | |
756 | { "vs51", 51, PPC_OPERAND_VSR }, | |
757 | { "vs52", 52, PPC_OPERAND_VSR }, | |
758 | { "vs53", 53, PPC_OPERAND_VSR }, | |
759 | { "vs54", 54, PPC_OPERAND_VSR }, | |
760 | { "vs55", 55, PPC_OPERAND_VSR }, | |
761 | { "vs56", 56, PPC_OPERAND_VSR }, | |
762 | { "vs57", 57, PPC_OPERAND_VSR }, | |
763 | { "vs58", 58, PPC_OPERAND_VSR }, | |
764 | { "vs59", 59, PPC_OPERAND_VSR }, | |
765 | { "vs6", 6, PPC_OPERAND_VSR }, | |
766 | { "vs60", 60, PPC_OPERAND_VSR }, | |
767 | { "vs61", 61, PPC_OPERAND_VSR }, | |
768 | { "vs62", 62, PPC_OPERAND_VSR }, | |
769 | { "vs63", 63, PPC_OPERAND_VSR }, | |
770 | { "vs7", 7, PPC_OPERAND_VSR }, | |
771 | { "vs8", 8, PPC_OPERAND_VSR }, | |
772 | { "vs9", 9, PPC_OPERAND_VSR }, | |
773 | ||
774 | { "xer", 1, PPC_OPERAND_SPR } | |
252b5132 RH |
775 | }; |
776 | ||
bc805888 | 777 | #define REG_NAME_CNT (sizeof (pre_defined_registers) / sizeof (struct pd_reg)) |
252b5132 RH |
778 | |
779 | /* Given NAME, find the register number associated with that name, return | |
780 | the integer value associated with the given name or -1 on failure. */ | |
781 | ||
7e0de605 | 782 | static const struct pd_reg * |
98027b10 | 783 | reg_name_search (const struct pd_reg *regs, int regcount, const char *name) |
252b5132 RH |
784 | { |
785 | int middle, low, high; | |
786 | int cmp; | |
787 | ||
788 | low = 0; | |
789 | high = regcount - 1; | |
790 | ||
791 | do | |
792 | { | |
793 | middle = (low + high) / 2; | |
794 | cmp = strcasecmp (name, regs[middle].name); | |
795 | if (cmp < 0) | |
796 | high = middle - 1; | |
797 | else if (cmp > 0) | |
798 | low = middle + 1; | |
799 | else | |
7e0de605 | 800 | return ®s[middle]; |
252b5132 RH |
801 | } |
802 | while (low <= high); | |
803 | ||
7e0de605 | 804 | return NULL; |
252b5132 RH |
805 | } |
806 | ||
807 | /* | |
99a814a1 | 808 | * Summary of register_name. |
252b5132 RH |
809 | * |
810 | * in: Input_line_pointer points to 1st char of operand. | |
811 | * | |
812 | * out: A expressionS. | |
813 | * The operand may have been a register: in this case, X_op == O_register, | |
814 | * X_add_number is set to the register number, and truth is returned. | |
815 | * Input_line_pointer->(next non-blank) char after operand, or is in its | |
816 | * original state. | |
817 | */ | |
818 | ||
b34976b6 | 819 | static bfd_boolean |
98027b10 | 820 | register_name (expressionS *expressionP) |
252b5132 | 821 | { |
7e0de605 | 822 | const struct pd_reg *reg; |
252b5132 RH |
823 | char *name; |
824 | char *start; | |
825 | char c; | |
826 | ||
99a814a1 | 827 | /* Find the spelling of the operand. */ |
252b5132 | 828 | start = name = input_line_pointer; |
3882b010 | 829 | if (name[0] == '%' && ISALPHA (name[1])) |
252b5132 RH |
830 | name = ++input_line_pointer; |
831 | ||
3882b010 | 832 | else if (!reg_names_p || !ISALPHA (name[0])) |
b34976b6 | 833 | return FALSE; |
252b5132 | 834 | |
d02603dc | 835 | c = get_symbol_name (&name); |
7e0de605 | 836 | reg = reg_name_search (pre_defined_registers, REG_NAME_CNT, name); |
252b5132 | 837 | |
468cced8 AM |
838 | /* Put back the delimiting char. */ |
839 | *input_line_pointer = c; | |
840 | ||
99a814a1 | 841 | /* Look to see if it's in the register table. */ |
7e0de605 | 842 | if (reg != NULL) |
252b5132 RH |
843 | { |
844 | expressionP->X_op = O_register; | |
7e0de605 AM |
845 | expressionP->X_add_number = reg->value; |
846 | expressionP->X_md = reg->flags; | |
81d4177b | 847 | |
99a814a1 | 848 | /* Make the rest nice. */ |
252b5132 RH |
849 | expressionP->X_add_symbol = NULL; |
850 | expressionP->X_op_symbol = NULL; | |
b34976b6 | 851 | return TRUE; |
252b5132 | 852 | } |
468cced8 AM |
853 | |
854 | /* Reset the line as if we had not done anything. */ | |
855 | input_line_pointer = start; | |
b34976b6 | 856 | return FALSE; |
252b5132 RH |
857 | } |
858 | \f | |
859 | /* This function is called for each symbol seen in an expression. It | |
860 | handles the special parsing which PowerPC assemblers are supposed | |
861 | to use for condition codes. */ | |
862 | ||
863 | /* Whether to do the special parsing. */ | |
b34976b6 | 864 | static bfd_boolean cr_operand; |
252b5132 RH |
865 | |
866 | /* Names to recognize in a condition code. This table is sorted. */ | |
867 | static const struct pd_reg cr_names[] = | |
868 | { | |
7e0de605 AM |
869 | { "cr0", 0, PPC_OPERAND_CR_REG }, |
870 | { "cr1", 1, PPC_OPERAND_CR_REG }, | |
871 | { "cr2", 2, PPC_OPERAND_CR_REG }, | |
872 | { "cr3", 3, PPC_OPERAND_CR_REG }, | |
873 | { "cr4", 4, PPC_OPERAND_CR_REG }, | |
874 | { "cr5", 5, PPC_OPERAND_CR_REG }, | |
875 | { "cr6", 6, PPC_OPERAND_CR_REG }, | |
876 | { "cr7", 7, PPC_OPERAND_CR_REG }, | |
877 | { "eq", 2, PPC_OPERAND_CR_BIT }, | |
878 | { "gt", 1, PPC_OPERAND_CR_BIT }, | |
879 | { "lt", 0, PPC_OPERAND_CR_BIT }, | |
880 | { "so", 3, PPC_OPERAND_CR_BIT }, | |
881 | { "un", 3, PPC_OPERAND_CR_BIT } | |
252b5132 RH |
882 | }; |
883 | ||
884 | /* Parsing function. This returns non-zero if it recognized an | |
885 | expression. */ | |
886 | ||
887 | int | |
91d6fa6a | 888 | ppc_parse_name (const char *name, expressionS *exp) |
252b5132 | 889 | { |
7e0de605 | 890 | const struct pd_reg *reg; |
252b5132 RH |
891 | |
892 | if (! cr_operand) | |
893 | return 0; | |
894 | ||
13abbae3 AM |
895 | if (*name == '%') |
896 | ++name; | |
7e0de605 | 897 | reg = reg_name_search (cr_names, sizeof cr_names / sizeof cr_names[0], |
252b5132 | 898 | name); |
7e0de605 | 899 | if (reg == NULL) |
252b5132 RH |
900 | return 0; |
901 | ||
7e0de605 AM |
902 | exp->X_op = O_register; |
903 | exp->X_add_number = reg->value; | |
904 | exp->X_md = reg->flags; | |
252b5132 RH |
905 | |
906 | return 1; | |
907 | } | |
7e0de605 AM |
908 | |
909 | /* Propagate X_md and check register expressions. This is to support | |
910 | condition codes like 4*cr5+eq. */ | |
911 | ||
912 | int | |
913 | ppc_optimize_expr (expressionS *left, operatorT op, expressionS *right) | |
914 | { | |
915 | /* Accept 4*cr<n> and cr<n>*4. */ | |
916 | if (op == O_multiply | |
917 | && ((right->X_op == O_register | |
918 | && right->X_md == PPC_OPERAND_CR_REG | |
919 | && left->X_op == O_constant | |
920 | && left->X_add_number == 4) | |
921 | || (left->X_op == O_register | |
922 | && left->X_md == PPC_OPERAND_CR_REG | |
923 | && right->X_op == O_constant | |
924 | && right->X_add_number == 4))) | |
925 | { | |
926 | left->X_op = O_register; | |
927 | left->X_md = PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT; | |
928 | left->X_add_number *= right->X_add_number; | |
929 | return 1; | |
930 | } | |
931 | ||
932 | /* Accept the above plus <cr bit>, and <cr bit> plus the above. */ | |
933 | if (right->X_op == O_register | |
934 | && left->X_op == O_register | |
935 | && op == O_add | |
936 | && ((right->X_md == PPC_OPERAND_CR_BIT | |
937 | && left->X_md == (PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT)) | |
938 | || (right->X_md == (PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT) | |
939 | && left->X_md == PPC_OPERAND_CR_BIT))) | |
940 | { | |
941 | left->X_md = PPC_OPERAND_CR_BIT; | |
942 | right->X_op = O_constant; | |
943 | return 0; | |
944 | } | |
945 | ||
946 | /* Accept reg +/- constant. */ | |
947 | if (left->X_op == O_register | |
948 | && !((op == O_add || op == O_subtract) && right->X_op == O_constant)) | |
ece5dcc1 | 949 | as_warn (_("invalid register expression")); |
7e0de605 AM |
950 | |
951 | /* Accept constant + reg. */ | |
952 | if (right->X_op == O_register) | |
953 | { | |
954 | if (op == O_add && left->X_op == O_constant) | |
955 | left->X_md = right->X_md; | |
956 | else | |
ece5dcc1 | 957 | as_warn (_("invalid register expression")); |
7e0de605 AM |
958 | } |
959 | ||
960 | return 0; | |
961 | } | |
252b5132 RH |
962 | \f |
963 | /* Local variables. */ | |
964 | ||
2b3c4602 AM |
965 | /* Whether to target xcoff64/elf64. */ |
966 | static unsigned int ppc_obj64 = BFD_DEFAULT_TARGET_SIZE == 64; | |
7f6d05e8 | 967 | |
252b5132 | 968 | /* Opcode hash table. */ |
629310ab | 969 | static htab_t ppc_hash; |
252b5132 RH |
970 | |
971 | /* Macro hash table. */ | |
629310ab | 972 | static htab_t ppc_macro_hash; |
252b5132 RH |
973 | |
974 | #ifdef OBJ_ELF | |
99a814a1 | 975 | /* What type of shared library support to use. */ |
5d6f4f16 | 976 | static enum { SHLIB_NONE, SHLIB_PIC, SHLIB_MRELOCATABLE } shlib = SHLIB_NONE; |
252b5132 | 977 | |
99a814a1 | 978 | /* Flags to set in the elf header. */ |
252b5132 RH |
979 | static flagword ppc_flags = 0; |
980 | ||
981 | /* Whether this is Solaris or not. */ | |
982 | #ifdef TARGET_SOLARIS_COMMENT | |
b34976b6 | 983 | #define SOLARIS_P TRUE |
252b5132 | 984 | #else |
b34976b6 | 985 | #define SOLARIS_P FALSE |
252b5132 RH |
986 | #endif |
987 | ||
b34976b6 | 988 | static bfd_boolean msolaris = SOLARIS_P; |
252b5132 RH |
989 | #endif |
990 | ||
991 | #ifdef OBJ_XCOFF | |
992 | ||
993 | /* The RS/6000 assembler uses the .csect pseudo-op to generate code | |
994 | using a bunch of different sections. These assembler sections, | |
995 | however, are all encompassed within the .text or .data sections of | |
996 | the final output file. We handle this by using different | |
997 | subsegments within these main segments. */ | |
998 | ||
999 | /* Next subsegment to allocate within the .text segment. */ | |
1000 | static subsegT ppc_text_subsegment = 2; | |
1001 | ||
1002 | /* Linked list of csects in the text section. */ | |
1003 | static symbolS *ppc_text_csects; | |
1004 | ||
1005 | /* Next subsegment to allocate within the .data segment. */ | |
1006 | static subsegT ppc_data_subsegment = 2; | |
1007 | ||
1008 | /* Linked list of csects in the data section. */ | |
1009 | static symbolS *ppc_data_csects; | |
1010 | ||
1011 | /* The current csect. */ | |
1012 | static symbolS *ppc_current_csect; | |
1013 | ||
1014 | /* The RS/6000 assembler uses a TOC which holds addresses of functions | |
1015 | and variables. Symbols are put in the TOC with the .tc pseudo-op. | |
1016 | A special relocation is used when accessing TOC entries. We handle | |
1017 | the TOC as a subsegment within the .data segment. We set it up if | |
1018 | we see a .toc pseudo-op, and save the csect symbol here. */ | |
1019 | static symbolS *ppc_toc_csect; | |
1020 | ||
1021 | /* The first frag in the TOC subsegment. */ | |
1022 | static fragS *ppc_toc_frag; | |
1023 | ||
1024 | /* The first frag in the first subsegment after the TOC in the .data | |
1025 | segment. NULL if there are no subsegments after the TOC. */ | |
1026 | static fragS *ppc_after_toc_frag; | |
1027 | ||
1028 | /* The current static block. */ | |
1029 | static symbolS *ppc_current_block; | |
1030 | ||
1031 | /* The COFF debugging section; set by md_begin. This is not the | |
1032 | .debug section, but is instead the secret BFD section which will | |
1033 | cause BFD to set the section number of a symbol to N_DEBUG. */ | |
1034 | static asection *ppc_coff_debug_section; | |
1035 | ||
85645aed TG |
1036 | /* Structure to set the length field of the dwarf sections. */ |
1037 | struct dw_subsection { | |
1038 | /* Subsections are simply linked. */ | |
1039 | struct dw_subsection *link; | |
1040 | ||
1041 | /* The subsection number. */ | |
1042 | subsegT subseg; | |
1043 | ||
1044 | /* Expression to compute the length of the section. */ | |
1045 | expressionS end_exp; | |
1046 | }; | |
1047 | ||
1048 | static struct dw_section { | |
1049 | /* Corresponding section. */ | |
1050 | segT sect; | |
1051 | ||
1052 | /* Simply linked list of subsections with a label. */ | |
1053 | struct dw_subsection *list_subseg; | |
1054 | ||
1055 | /* The anonymous subsection. */ | |
1056 | struct dw_subsection *anon_subseg; | |
1057 | } dw_sections[XCOFF_DWSECT_NBR_NAMES]; | |
252b5132 RH |
1058 | #endif /* OBJ_XCOFF */ |
1059 | ||
252b5132 RH |
1060 | #ifdef OBJ_ELF |
1061 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE" */ | |
6a0c61b7 EZ |
1062 | unsigned long *ppc_apuinfo_list; |
1063 | unsigned int ppc_apuinfo_num; | |
1064 | unsigned int ppc_apuinfo_num_alloc; | |
252b5132 RH |
1065 | #endif /* OBJ_ELF */ |
1066 | \f | |
1067 | #ifdef OBJ_ELF | |
15c1449b | 1068 | const char *const md_shortopts = "b:l:usm:K:VQ:"; |
252b5132 | 1069 | #else |
15c1449b | 1070 | const char *const md_shortopts = "um:"; |
252b5132 | 1071 | #endif |
cef4f754 | 1072 | #define OPTION_NOPS (OPTION_MD_BASE + 0) |
15c1449b | 1073 | const struct option md_longopts[] = { |
cef4f754 | 1074 | {"nops", required_argument, NULL, OPTION_NOPS}, |
bf7279d5 AM |
1075 | {"ppc476-workaround", no_argument, &warn_476, 1}, |
1076 | {"no-ppc476-workaround", no_argument, &warn_476, 0}, | |
252b5132 RH |
1077 | {NULL, no_argument, NULL, 0} |
1078 | }; | |
15c1449b | 1079 | const size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
1080 | |
1081 | int | |
17b9d67d | 1082 | md_parse_option (int c, const char *arg) |
252b5132 | 1083 | { |
69fe9ce5 AM |
1084 | ppc_cpu_t new_cpu; |
1085 | ||
252b5132 RH |
1086 | switch (c) |
1087 | { | |
1088 | case 'u': | |
1089 | /* -u means that any undefined symbols should be treated as | |
1090 | external, which is the default for gas anyhow. */ | |
1091 | break; | |
1092 | ||
1093 | #ifdef OBJ_ELF | |
1094 | case 'l': | |
1095 | /* Solaris as takes -le (presumably for little endian). For completeness | |
99a814a1 | 1096 | sake, recognize -be also. */ |
252b5132 RH |
1097 | if (strcmp (arg, "e") == 0) |
1098 | { | |
1099 | target_big_endian = 0; | |
1100 | set_target_endian = 1; | |
b9c361e0 | 1101 | if (ppc_cpu & PPC_OPCODE_VLE) |
d6ed37ed | 1102 | as_bad (_("the use of -mvle requires big endian.")); |
252b5132 RH |
1103 | } |
1104 | else | |
1105 | return 0; | |
1106 | ||
1107 | break; | |
1108 | ||
1109 | case 'b': | |
1110 | if (strcmp (arg, "e") == 0) | |
1111 | { | |
1112 | target_big_endian = 1; | |
1113 | set_target_endian = 1; | |
1114 | } | |
1115 | else | |
1116 | return 0; | |
1117 | ||
1118 | break; | |
1119 | ||
1120 | case 'K': | |
99a814a1 | 1121 | /* Recognize -K PIC. */ |
252b5132 RH |
1122 | if (strcmp (arg, "PIC") == 0 || strcmp (arg, "pic") == 0) |
1123 | { | |
1124 | shlib = SHLIB_PIC; | |
1125 | ppc_flags |= EF_PPC_RELOCATABLE_LIB; | |
1126 | } | |
1127 | else | |
1128 | return 0; | |
1129 | ||
1130 | break; | |
1131 | #endif | |
1132 | ||
7f6d05e8 CP |
1133 | /* a64 and a32 determine whether to use XCOFF64 or XCOFF32. */ |
1134 | case 'a': | |
1135 | if (strcmp (arg, "64") == 0) | |
2a98c3a6 AM |
1136 | { |
1137 | #ifdef BFD64 | |
1138 | ppc_obj64 = 1; | |
d6ed37ed AM |
1139 | if (ppc_cpu & PPC_OPCODE_VLE) |
1140 | as_bad (_("the use of -mvle requires -a32.")); | |
2a98c3a6 AM |
1141 | #else |
1142 | as_fatal (_("%s unsupported"), "-a64"); | |
1143 | #endif | |
1144 | } | |
7f6d05e8 | 1145 | else if (strcmp (arg, "32") == 0) |
2b3c4602 | 1146 | ppc_obj64 = 0; |
7f6d05e8 CP |
1147 | else |
1148 | return 0; | |
1149 | break; | |
81d4177b | 1150 | |
252b5132 | 1151 | case 'm': |
776fc418 | 1152 | new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, arg); |
52be03fd AM |
1153 | /* "raw" is only valid for the disassembler. */ |
1154 | if (new_cpu != 0 && (new_cpu & PPC_OPCODE_RAW) == 0) | |
b9c361e0 JL |
1155 | { |
1156 | ppc_cpu = new_cpu; | |
d6ed37ed AM |
1157 | if (strcmp (arg, "vle") == 0) |
1158 | { | |
1159 | if (set_target_endian && target_big_endian == 0) | |
1160 | as_bad (_("the use of -mvle requires big endian.")); | |
1161 | if (ppc_obj64) | |
1162 | as_bad (_("the use of -mvle requires -a32.")); | |
1163 | } | |
b9c361e0 | 1164 | } |
252b5132 | 1165 | |
83eef883 AFB |
1166 | else if (strcmp (arg, "no-vle") == 0) |
1167 | { | |
1168 | sticky &= ~PPC_OPCODE_VLE; | |
1169 | ||
1170 | new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, "booke"); | |
1171 | new_cpu &= ~PPC_OPCODE_VLE; | |
1172 | ||
1173 | ppc_cpu = new_cpu; | |
1174 | } | |
1175 | ||
252b5132 | 1176 | else if (strcmp (arg, "regnames") == 0) |
b34976b6 | 1177 | reg_names_p = TRUE; |
252b5132 RH |
1178 | |
1179 | else if (strcmp (arg, "no-regnames") == 0) | |
b34976b6 | 1180 | reg_names_p = FALSE; |
252b5132 RH |
1181 | |
1182 | #ifdef OBJ_ELF | |
99a814a1 AM |
1183 | /* -mrelocatable/-mrelocatable-lib -- warn about initializations |
1184 | that require relocation. */ | |
252b5132 RH |
1185 | else if (strcmp (arg, "relocatable") == 0) |
1186 | { | |
5d6f4f16 | 1187 | shlib = SHLIB_MRELOCATABLE; |
252b5132 RH |
1188 | ppc_flags |= EF_PPC_RELOCATABLE; |
1189 | } | |
1190 | ||
1191 | else if (strcmp (arg, "relocatable-lib") == 0) | |
1192 | { | |
5d6f4f16 | 1193 | shlib = SHLIB_MRELOCATABLE; |
252b5132 RH |
1194 | ppc_flags |= EF_PPC_RELOCATABLE_LIB; |
1195 | } | |
1196 | ||
99a814a1 | 1197 | /* -memb, set embedded bit. */ |
252b5132 RH |
1198 | else if (strcmp (arg, "emb") == 0) |
1199 | ppc_flags |= EF_PPC_EMB; | |
1200 | ||
cc643b88 | 1201 | /* -mlittle/-mbig set the endianness. */ |
99a814a1 AM |
1202 | else if (strcmp (arg, "little") == 0 |
1203 | || strcmp (arg, "little-endian") == 0) | |
252b5132 RH |
1204 | { |
1205 | target_big_endian = 0; | |
1206 | set_target_endian = 1; | |
b9c361e0 | 1207 | if (ppc_cpu & PPC_OPCODE_VLE) |
d6ed37ed | 1208 | as_bad (_("the use of -mvle requires big endian.")); |
252b5132 RH |
1209 | } |
1210 | ||
1211 | else if (strcmp (arg, "big") == 0 || strcmp (arg, "big-endian") == 0) | |
1212 | { | |
1213 | target_big_endian = 1; | |
1214 | set_target_endian = 1; | |
1215 | } | |
1216 | ||
1217 | else if (strcmp (arg, "solaris") == 0) | |
1218 | { | |
b34976b6 | 1219 | msolaris = TRUE; |
252b5132 RH |
1220 | ppc_comment_chars = ppc_solaris_comment_chars; |
1221 | } | |
1222 | ||
1223 | else if (strcmp (arg, "no-solaris") == 0) | |
1224 | { | |
b34976b6 | 1225 | msolaris = FALSE; |
252b5132 RH |
1226 | ppc_comment_chars = ppc_eabi_comment_chars; |
1227 | } | |
74081948 AF |
1228 | else if (strcmp (arg, "spe2") == 0) |
1229 | { | |
1230 | ppc_cpu |= PPC_OPCODE_SPE2; | |
1231 | } | |
252b5132 RH |
1232 | #endif |
1233 | else | |
1234 | { | |
1235 | as_bad (_("invalid switch -m%s"), arg); | |
1236 | return 0; | |
1237 | } | |
1238 | break; | |
1239 | ||
1240 | #ifdef OBJ_ELF | |
1241 | /* -V: SVR4 argument to print version ID. */ | |
1242 | case 'V': | |
1243 | print_version_id (); | |
1244 | break; | |
1245 | ||
1246 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
1247 | should be emitted or not. FIXME: Not implemented. */ | |
1248 | case 'Q': | |
1249 | break; | |
1250 | ||
1251 | /* Solaris takes -s to specify that .stabs go in a .stabs section, | |
1252 | rather than .stabs.excl, which is ignored by the linker. | |
1253 | FIXME: Not implemented. */ | |
1254 | case 's': | |
1255 | if (arg) | |
1256 | return 0; | |
1257 | ||
1258 | break; | |
1259 | #endif | |
1260 | ||
cef4f754 AM |
1261 | case OPTION_NOPS: |
1262 | { | |
1263 | char *end; | |
1264 | nop_limit = strtoul (optarg, &end, 0); | |
1265 | if (*end) | |
1266 | as_bad (_("--nops needs a numeric argument")); | |
1267 | } | |
1268 | break; | |
85645aed | 1269 | |
bf7279d5 AM |
1270 | case 0: |
1271 | break; | |
1272 | ||
252b5132 RH |
1273 | default: |
1274 | return 0; | |
1275 | } | |
1276 | ||
1277 | return 1; | |
1278 | } | |
1279 | ||
5f63875b AM |
1280 | static int |
1281 | is_ppc64_target (const bfd_target *targ, void *data ATTRIBUTE_UNUSED) | |
1282 | { | |
1283 | switch (targ->flavour) | |
1284 | { | |
1285 | #ifdef OBJ_ELF | |
1286 | case bfd_target_elf_flavour: | |
1287 | return strncmp (targ->name, "elf64-powerpc", 13) == 0; | |
1288 | #endif | |
1289 | #ifdef OBJ_XCOFF | |
1290 | case bfd_target_xcoff_flavour: | |
1291 | return (strcmp (targ->name, "aixcoff64-rs6000") == 0 | |
1292 | || strcmp (targ->name, "aix5coff64-rs6000") == 0); | |
1293 | #endif | |
1294 | default: | |
1295 | return 0; | |
1296 | } | |
1297 | } | |
1298 | ||
252b5132 | 1299 | void |
98027b10 | 1300 | md_show_usage (FILE *stream) |
252b5132 | 1301 | { |
bc805888 | 1302 | fprintf (stream, _("\ |
5f63875b AM |
1303 | PowerPC options:\n")); |
1304 | fprintf (stream, _("\ | |
1305 | -a32 generate ELF32/XCOFF32\n")); | |
1306 | if (bfd_iterate_over_targets (is_ppc64_target, NULL)) | |
1307 | fprintf (stream, _("\ | |
1308 | -a64 generate ELF64/XCOFF64\n")); | |
1309 | fprintf (stream, _("\ | |
1310 | -u ignored\n")); | |
1311 | fprintf (stream, _("\ | |
1312 | -mpwrx, -mpwr2 generate code for POWER/2 (RIOS2)\n")); | |
1313 | fprintf (stream, _("\ | |
1314 | -mpwr generate code for POWER (RIOS1)\n")); | |
1315 | fprintf (stream, _("\ | |
1316 | -m601 generate code for PowerPC 601\n")); | |
1317 | fprintf (stream, _("\ | |
418c1742 | 1318 | -mppc, -mppc32, -m603, -m604\n\ |
5f63875b AM |
1319 | generate code for PowerPC 603/604\n")); |
1320 | fprintf (stream, _("\ | |
1321 | -m403 generate code for PowerPC 403\n")); | |
1322 | fprintf (stream, _("\ | |
1323 | -m405 generate code for PowerPC 405\n")); | |
1324 | fprintf (stream, _("\ | |
1325 | -m440 generate code for PowerPC 440\n")); | |
1326 | fprintf (stream, _("\ | |
1327 | -m464 generate code for PowerPC 464\n")); | |
1328 | fprintf (stream, _("\ | |
1329 | -m476 generate code for PowerPC 476\n")); | |
1330 | fprintf (stream, _("\ | |
f5c120c5 | 1331 | -m7400, -m7410, -m7450, -m7455\n\ |
5f63875b AM |
1332 | generate code for PowerPC 7400/7410/7450/7455\n")); |
1333 | fprintf (stream, _("\ | |
fa758a70 | 1334 | -m750cl, -mgekko, -mbroadway\n\ |
5f63875b AM |
1335 | generate code for PowerPC 750cl/Gekko/Broadway\n")); |
1336 | fprintf (stream, _("\ | |
ef5a96d5 | 1337 | -m821, -m850, -m860 generate code for PowerPC 821/850/860\n")); |
df12615d | 1338 | fprintf (stream, _("\ |
5f63875b AM |
1339 | -mppc64, -m620 generate code for PowerPC 620/625/630\n")); |
1340 | fprintf (stream, _("\ | |
1341 | -mppc64bridge generate code for PowerPC 64, including bridge insns\n")); | |
1342 | fprintf (stream, _("\ | |
1343 | -mbooke generate code for 32-bit PowerPC BookE\n")); | |
1344 | fprintf (stream, _("\ | |
1345 | -ma2 generate code for A2 architecture\n")); | |
1346 | fprintf (stream, _("\ | |
1347 | -mpower4, -mpwr4 generate code for Power4 architecture\n")); | |
1348 | fprintf (stream, _("\ | |
cdc51b07 | 1349 | -mpower5, -mpwr5, -mpwr5x\n\ |
5f63875b AM |
1350 | generate code for Power5 architecture\n")); |
1351 | fprintf (stream, _("\ | |
1352 | -mpower6, -mpwr6 generate code for Power6 architecture\n")); | |
1353 | fprintf (stream, _("\ | |
1354 | -mpower7, -mpwr7 generate code for Power7 architecture\n")); | |
1355 | fprintf (stream, _("\ | |
1356 | -mpower8, -mpwr8 generate code for Power8 architecture\n")); | |
1357 | fprintf (stream, _("\ | |
1358 | -mpower9, -mpwr9 generate code for Power9 architecture\n")); | |
1359 | fprintf (stream, _("\ | |
1424c35d AM |
1360 | -mpower10, -mpwr10 generate code for Power10 architecture\n")); |
1361 | fprintf (stream, _("\ | |
5f63875b AM |
1362 | -mcell generate code for Cell Broadband Engine architecture\n")); |
1363 | fprintf (stream, _("\ | |
1364 | -mcom generate code for Power/PowerPC common instructions\n")); | |
1365 | fprintf (stream, _("\ | |
ce3d2015 | 1366 | -many generate code for any architecture (PWR/PWRX/PPC)\n")); |
6a0c61b7 | 1367 | fprintf (stream, _("\ |
5f63875b AM |
1368 | -maltivec generate code for AltiVec\n")); |
1369 | fprintf (stream, _("\ | |
1370 | -mvsx generate code for Vector-Scalar (VSX) instructions\n")); | |
1371 | fprintf (stream, _("\ | |
1372 | -me300 generate code for PowerPC e300 family\n")); | |
1373 | fprintf (stream, _("\ | |
1374 | -me500, -me500x2 generate code for Motorola e500 core complex\n")); | |
1375 | fprintf (stream, _("\ | |
1376 | -me500mc, generate code for Freescale e500mc core complex\n")); | |
1377 | fprintf (stream, _("\ | |
1378 | -me500mc64, generate code for Freescale e500mc64 core complex\n")); | |
1379 | fprintf (stream, _("\ | |
1380 | -me5500, generate code for Freescale e5500 core complex\n")); | |
1381 | fprintf (stream, _("\ | |
1382 | -me6500, generate code for Freescale e6500 core complex\n")); | |
1383 | fprintf (stream, _("\ | |
1384 | -mspe generate code for Motorola SPE instructions\n")); | |
1385 | fprintf (stream, _("\ | |
1386 | -mspe2 generate code for Freescale SPE2 instructions\n")); | |
1387 | fprintf (stream, _("\ | |
1388 | -mvle generate code for Freescale VLE instructions\n")); | |
1389 | fprintf (stream, _("\ | |
1390 | -mtitan generate code for AppliedMicro Titan core complex\n")); | |
1391 | fprintf (stream, _("\ | |
1392 | -mregnames Allow symbolic names for registers\n")); | |
1393 | fprintf (stream, _("\ | |
ce3d2015 | 1394 | -mno-regnames Do not allow symbolic names for registers\n")); |
252b5132 | 1395 | #ifdef OBJ_ELF |
bc805888 | 1396 | fprintf (stream, _("\ |
5f63875b AM |
1397 | -mrelocatable support for GCC's -mrelocatble option\n")); |
1398 | fprintf (stream, _("\ | |
1399 | -mrelocatable-lib support for GCC's -mrelocatble-lib option\n")); | |
1400 | fprintf (stream, _("\ | |
1401 | -memb set PPC_EMB bit in ELF flags\n")); | |
1402 | fprintf (stream, _("\ | |
b8b738ac | 1403 | -mlittle, -mlittle-endian, -le\n\ |
5f63875b AM |
1404 | generate code for a little endian machine\n")); |
1405 | fprintf (stream, _("\ | |
b8b738ac | 1406 | -mbig, -mbig-endian, -be\n\ |
5f63875b AM |
1407 | generate code for a big endian machine\n")); |
1408 | fprintf (stream, _("\ | |
1409 | -msolaris generate code for Solaris\n")); | |
1410 | fprintf (stream, _("\ | |
1411 | -mno-solaris do not generate code for Solaris\n")); | |
1412 | fprintf (stream, _("\ | |
1413 | -K PIC set EF_PPC_RELOCATABLE_LIB in ELF flags\n")); | |
1414 | fprintf (stream, _("\ | |
1415 | -V print assembler version number\n")); | |
1416 | fprintf (stream, _("\ | |
ce3d2015 | 1417 | -Qy, -Qn ignored\n")); |
252b5132 | 1418 | #endif |
cef4f754 | 1419 | fprintf (stream, _("\ |
5f63875b AM |
1420 | -nops=count when aligning, more than COUNT nops uses a branch\n")); |
1421 | fprintf (stream, _("\ | |
bf7279d5 | 1422 | -ppc476-workaround warn if emitting data to code sections\n")); |
252b5132 RH |
1423 | } |
1424 | \f | |
1425 | /* Set ppc_cpu if it is not already set. */ | |
1426 | ||
1427 | static void | |
98027b10 | 1428 | ppc_set_cpu (void) |
252b5132 RH |
1429 | { |
1430 | const char *default_os = TARGET_OS; | |
1431 | const char *default_cpu = TARGET_CPU; | |
1432 | ||
7102e95e | 1433 | if ((ppc_cpu & ~(ppc_cpu_t) PPC_OPCODE_ANY) == 0) |
252b5132 | 1434 | { |
2a98c3a6 | 1435 | if (ppc_obj64) |
f2ab4b42 PB |
1436 | if (target_big_endian) |
1437 | ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_64; | |
1438 | else | |
1439 | /* The minimum supported cpu for 64-bit little-endian is power8. */ | |
1440 | ppc_cpu |= ppc_parse_cpu (ppc_cpu, &sticky, "power8"); | |
2a98c3a6 AM |
1441 | else if (strncmp (default_os, "aix", 3) == 0 |
1442 | && default_os[3] >= '4' && default_os[3] <= '9') | |
bdc70b4a | 1443 | ppc_cpu |= PPC_OPCODE_COMMON; |
252b5132 | 1444 | else if (strncmp (default_os, "aix3", 4) == 0) |
bdc70b4a | 1445 | ppc_cpu |= PPC_OPCODE_POWER; |
252b5132 | 1446 | else if (strcmp (default_cpu, "rs6000") == 0) |
bdc70b4a | 1447 | ppc_cpu |= PPC_OPCODE_POWER; |
0baf16f2 | 1448 | else if (strncmp (default_cpu, "powerpc", 7) == 0) |
bdc70b4a | 1449 | ppc_cpu |= PPC_OPCODE_PPC; |
252b5132 | 1450 | else |
d6ed37ed | 1451 | as_fatal (_("unknown default cpu = %s, os = %s"), |
99a814a1 | 1452 | default_cpu, default_os); |
252b5132 RH |
1453 | } |
1454 | } | |
1455 | ||
9232bbb0 AM |
1456 | /* Figure out the BFD architecture to use. This function and ppc_mach |
1457 | are called well before md_begin, when the output file is opened. */ | |
252b5132 RH |
1458 | |
1459 | enum bfd_architecture | |
98027b10 | 1460 | ppc_arch (void) |
252b5132 RH |
1461 | { |
1462 | const char *default_cpu = TARGET_CPU; | |
1463 | ppc_set_cpu (); | |
1464 | ||
1465 | if ((ppc_cpu & PPC_OPCODE_PPC) != 0) | |
1466 | return bfd_arch_powerpc; | |
b9c361e0 JL |
1467 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) |
1468 | return bfd_arch_powerpc; | |
1469 | if ((ppc_cpu & PPC_OPCODE_POWER) != 0) | |
252b5132 | 1470 | return bfd_arch_rs6000; |
b9c361e0 | 1471 | if ((ppc_cpu & (PPC_OPCODE_COMMON | PPC_OPCODE_ANY)) != 0) |
252b5132 RH |
1472 | { |
1473 | if (strcmp (default_cpu, "rs6000") == 0) | |
1474 | return bfd_arch_rs6000; | |
0baf16f2 | 1475 | else if (strncmp (default_cpu, "powerpc", 7) == 0) |
252b5132 RH |
1476 | return bfd_arch_powerpc; |
1477 | } | |
1478 | ||
d6ed37ed | 1479 | as_fatal (_("neither Power nor PowerPC opcodes were selected.")); |
252b5132 RH |
1480 | return bfd_arch_unknown; |
1481 | } | |
1482 | ||
7f6d05e8 | 1483 | unsigned long |
98027b10 | 1484 | ppc_mach (void) |
7f6d05e8 | 1485 | { |
2a98c3a6 AM |
1486 | if (ppc_obj64) |
1487 | return bfd_mach_ppc64; | |
1488 | else if (ppc_arch () == bfd_arch_rs6000) | |
1489 | return bfd_mach_rs6k; | |
ce3d2015 AM |
1490 | else if (ppc_cpu & PPC_OPCODE_TITAN) |
1491 | return bfd_mach_ppc_titan; | |
b9c361e0 JL |
1492 | else if (ppc_cpu & PPC_OPCODE_VLE) |
1493 | return bfd_mach_ppc_vle; | |
2a98c3a6 AM |
1494 | else |
1495 | return bfd_mach_ppc; | |
7f6d05e8 CP |
1496 | } |
1497 | ||
e0471c16 | 1498 | extern const char* |
98027b10 | 1499 | ppc_target_format (void) |
7f6d05e8 CP |
1500 | { |
1501 | #ifdef OBJ_COFF | |
fe49679d | 1502 | #if TE_POWERMAC |
0baf16f2 | 1503 | return "xcoff-powermac"; |
7f6d05e8 | 1504 | #else |
eb1e0e80 | 1505 | # ifdef TE_AIX5 |
edc1d652 | 1506 | return (ppc_obj64 ? "aix5coff64-rs6000" : "aixcoff-rs6000"); |
eb1e0e80 | 1507 | # else |
edc1d652 | 1508 | return (ppc_obj64 ? "aixcoff64-rs6000" : "aixcoff-rs6000"); |
eb1e0e80 | 1509 | # endif |
7f6d05e8 | 1510 | #endif |
7f6d05e8 CP |
1511 | #endif |
1512 | #ifdef OBJ_ELF | |
edc1d652 AM |
1513 | # ifdef TE_FreeBSD |
1514 | return (ppc_obj64 ? "elf64-powerpc-freebsd" : "elf32-powerpc-freebsd"); | |
1515 | # elif defined (TE_VXWORKS) | |
9d8504b1 PB |
1516 | return "elf32-powerpc-vxworks"; |
1517 | # else | |
0baf16f2 | 1518 | return (target_big_endian |
2b3c4602 AM |
1519 | ? (ppc_obj64 ? "elf64-powerpc" : "elf32-powerpc") |
1520 | : (ppc_obj64 ? "elf64-powerpcle" : "elf32-powerpcle")); | |
9d8504b1 | 1521 | # endif |
7f6d05e8 CP |
1522 | #endif |
1523 | } | |
1524 | ||
b9c361e0 JL |
1525 | /* Validate one entry in powerpc_opcodes[] or vle_opcodes[]. |
1526 | Return TRUE if there's a problem, otherwise FALSE. */ | |
1527 | ||
1528 | static bfd_boolean | |
1529 | insn_validate (const struct powerpc_opcode *op) | |
1530 | { | |
1531 | const unsigned char *o; | |
0f873fd5 | 1532 | uint64_t omask = op->mask; |
b9c361e0 JL |
1533 | |
1534 | /* The mask had better not trim off opcode bits. */ | |
1535 | if ((op->opcode & omask) != op->opcode) | |
1536 | { | |
1537 | as_bad (_("mask trims opcode bits for %s"), op->name); | |
1538 | return TRUE; | |
1539 | } | |
1540 | ||
1541 | /* The operands must not overlap the opcode or each other. */ | |
1542 | for (o = op->operands; *o; ++o) | |
1543 | { | |
2eac3da1 | 1544 | bfd_boolean optional = FALSE; |
b9c361e0 JL |
1545 | if (*o >= num_powerpc_operands) |
1546 | { | |
1547 | as_bad (_("operand index error for %s"), op->name); | |
1548 | return TRUE; | |
1549 | } | |
1550 | else | |
1551 | { | |
71553718 | 1552 | uint64_t mask; |
b9c361e0 | 1553 | const struct powerpc_operand *operand = &powerpc_operands[*o]; |
71553718 | 1554 | if (operand->shift == (int) PPC_OPSHIFT_INV) |
b9c361e0 | 1555 | { |
71553718 AM |
1556 | const char *errmsg; |
1557 | int64_t val; | |
1558 | ||
1559 | errmsg = NULL; | |
1560 | val = -1; | |
1561 | if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
1562 | val = -val; | |
1563 | else if ((operand->flags & PPC_OPERAND_PLUS1) != 0) | |
1564 | val += 1; | |
1565 | mask = (*operand->insert) (0, val, ppc_cpu, &errmsg); | |
b9c361e0 | 1566 | } |
71553718 AM |
1567 | else if (operand->shift >= 0) |
1568 | mask = operand->bitm << operand->shift; | |
1569 | else | |
1570 | mask = operand->bitm >> -operand->shift; | |
1571 | if (omask & mask) | |
1572 | { | |
1573 | as_bad (_("operand %d overlap in %s"), | |
1574 | (int) (o - op->operands), op->name); | |
1575 | return TRUE; | |
1576 | } | |
1577 | omask |= mask; | |
2eac3da1 AM |
1578 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) |
1579 | optional = TRUE; | |
1580 | else if (optional) | |
1581 | { | |
1582 | as_bad (_("non-optional operand %d follows optional operand in %s"), | |
1583 | (int) (o - op->operands), op->name); | |
1584 | return TRUE; | |
1585 | } | |
b9c361e0 JL |
1586 | } |
1587 | } | |
1588 | return FALSE; | |
1589 | } | |
1590 | ||
69c040df | 1591 | /* Insert opcodes and macros into hash tables. Called at startup and |
1fe532cf | 1592 | for .machine pseudo. */ |
252b5132 | 1593 | |
69c040df AM |
1594 | static void |
1595 | ppc_setup_opcodes (void) | |
252b5132 | 1596 | { |
98027b10 | 1597 | const struct powerpc_opcode *op; |
252b5132 RH |
1598 | const struct powerpc_opcode *op_end; |
1599 | const struct powerpc_macro *macro; | |
1600 | const struct powerpc_macro *macro_end; | |
b84bf58a | 1601 | bfd_boolean bad_insn = FALSE; |
252b5132 | 1602 | |
69c040df | 1603 | if (ppc_hash != NULL) |
629310ab | 1604 | htab_delete (ppc_hash); |
69c040df | 1605 | if (ppc_macro_hash != NULL) |
629310ab | 1606 | htab_delete (ppc_macro_hash); |
252b5132 RH |
1607 | |
1608 | /* Insert the opcodes into a hash table. */ | |
629310ab | 1609 | ppc_hash = str_htab_create (); |
252b5132 | 1610 | |
c43a438d | 1611 | if (ENABLE_CHECKING) |
b84bf58a | 1612 | { |
c43a438d | 1613 | unsigned int i; |
b84bf58a | 1614 | |
3b8b57a9 AM |
1615 | /* An index into powerpc_operands is stored in struct fix |
1616 | fx_pcrel_adjust which is 8 bits wide. */ | |
1617 | gas_assert (num_powerpc_operands < 256); | |
1618 | ||
c43a438d AM |
1619 | /* Check operand masks. Code here and in the disassembler assumes |
1620 | all the 1's in the mask are contiguous. */ | |
1621 | for (i = 0; i < num_powerpc_operands; ++i) | |
b84bf58a | 1622 | { |
0f873fd5 PB |
1623 | uint64_t mask = powerpc_operands[i].bitm; |
1624 | uint64_t right_bit; | |
c43a438d AM |
1625 | unsigned int j; |
1626 | ||
1627 | right_bit = mask & -mask; | |
1628 | mask += right_bit; | |
1629 | right_bit = mask & -mask; | |
1630 | if (mask != right_bit) | |
1631 | { | |
1632 | as_bad (_("powerpc_operands[%d].bitm invalid"), i); | |
1633 | bad_insn = TRUE; | |
1634 | } | |
1635 | for (j = i + 1; j < num_powerpc_operands; ++j) | |
1636 | if (memcmp (&powerpc_operands[i], &powerpc_operands[j], | |
1637 | sizeof (powerpc_operands[0])) == 0) | |
1638 | { | |
1639 | as_bad (_("powerpc_operands[%d] duplicates powerpc_operands[%d]"), | |
1640 | j, i); | |
1641 | bad_insn = TRUE; | |
1642 | } | |
b84bf58a AM |
1643 | } |
1644 | } | |
1645 | ||
252b5132 RH |
1646 | op_end = powerpc_opcodes + powerpc_num_opcodes; |
1647 | for (op = powerpc_opcodes; op < op_end; op++) | |
1648 | { | |
c43a438d | 1649 | if (ENABLE_CHECKING) |
b84bf58a | 1650 | { |
2ceb7719 | 1651 | unsigned int new_opcode = PPC_OP (op[0].opcode); |
b9c361e0 JL |
1652 | |
1653 | #ifdef PRINT_OPCODE_TABLE | |
2ceb7719 PB |
1654 | printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", |
1655 | op->name, (unsigned int) (op - powerpc_opcodes), | |
1656 | new_opcode, (unsigned long long) op->opcode, | |
1657 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
b9c361e0 JL |
1658 | #endif |
1659 | ||
2ceb7719 PB |
1660 | /* The major opcodes had better be sorted. Code in the disassembler |
1661 | assumes the insns are sorted according to major opcode. */ | |
1662 | if (op != powerpc_opcodes | |
1663 | && new_opcode < PPC_OP (op[-1].opcode)) | |
1664 | { | |
1665 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
1666 | bad_insn = TRUE; | |
8dbcd839 | 1667 | } |
2ceb7719 | 1668 | |
14b57c7c AM |
1669 | if ((op->flags & PPC_OPCODE_VLE) != 0) |
1670 | { | |
1671 | as_bad (_("%s is enabled by vle flag"), op->name); | |
1672 | bad_insn = TRUE; | |
1673 | } | |
1674 | if (PPC_OP (op->opcode) != 4 | |
1675 | && PPC_OP (op->opcode) != 31 | |
1676 | && (op->deprecated & PPC_OPCODE_VLE) == 0) | |
1677 | { | |
1678 | as_bad (_("%s not disabled by vle flag"), op->name); | |
1679 | bad_insn = TRUE; | |
1680 | } | |
b9c361e0 JL |
1681 | bad_insn |= insn_validate (op); |
1682 | } | |
c43a438d | 1683 | |
b9c361e0 | 1684 | if ((ppc_cpu & op->flags) != 0 |
fe0e921f AM |
1685 | && !(ppc_cpu & op->deprecated) |
1686 | && str_hash_insert (ppc_hash, op->name, op, 0) != NULL) | |
1687 | { | |
1688 | as_bad (_("duplicate %s"), op->name); | |
1689 | bad_insn = TRUE; | |
1690 | } | |
b9c361e0 | 1691 | } |
c43a438d | 1692 | |
b9c361e0 JL |
1693 | if ((ppc_cpu & PPC_OPCODE_ANY) != 0) |
1694 | for (op = powerpc_opcodes; op < op_end; op++) | |
fe0e921f | 1695 | str_hash_insert (ppc_hash, op->name, op, 0); |
b9c361e0 | 1696 | |
dd7efa79 PB |
1697 | op_end = prefix_opcodes + prefix_num_opcodes; |
1698 | for (op = prefix_opcodes; op < op_end; op++) | |
1699 | { | |
1700 | if (ENABLE_CHECKING) | |
1701 | { | |
1702 | unsigned int new_opcode = PPC_PREFIX_SEG (op[0].opcode); | |
1703 | ||
1704 | #ifdef PRINT_OPCODE_TABLE | |
1705 | printf ("%-14s\t#%04u\tmajor op/2: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", | |
1706 | op->name, (unsigned int) (op - prefix_opcodes), | |
1707 | new_opcode, (unsigned long long) op->opcode, | |
1708 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
1709 | #endif | |
1710 | ||
1711 | /* The major opcodes had better be sorted. Code in the disassembler | |
1712 | assumes the insns are sorted according to major opcode. */ | |
1713 | if (op != prefix_opcodes | |
1714 | && new_opcode < PPC_PREFIX_SEG (op[-1].opcode)) | |
1715 | { | |
1716 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
1717 | bad_insn = TRUE; | |
1718 | } | |
1719 | bad_insn |= insn_validate (op); | |
1720 | } | |
1721 | ||
1722 | if ((ppc_cpu & op->flags) != 0 | |
fe0e921f AM |
1723 | && !(ppc_cpu & op->deprecated) |
1724 | && str_hash_insert (ppc_hash, op->name, op, 0) != NULL) | |
1725 | { | |
1726 | as_bad (_("duplicate %s"), op->name); | |
1727 | bad_insn = TRUE; | |
1728 | } | |
dd7efa79 PB |
1729 | } |
1730 | ||
1731 | if ((ppc_cpu & PPC_OPCODE_ANY) != 0) | |
1732 | for (op = prefix_opcodes; op < op_end; op++) | |
fe0e921f | 1733 | str_hash_insert (ppc_hash, op->name, op, 0); |
dd7efa79 | 1734 | |
b9c361e0 JL |
1735 | op_end = vle_opcodes + vle_num_opcodes; |
1736 | for (op = vle_opcodes; op < op_end; op++) | |
1737 | { | |
1738 | if (ENABLE_CHECKING) | |
1739 | { | |
2ceb7719 | 1740 | unsigned new_seg = VLE_OP_TO_SEG (VLE_OP (op[0].opcode, op[0].mask)); |
b9c361e0 JL |
1741 | |
1742 | #ifdef PRINT_OPCODE_TABLE | |
2ceb7719 PB |
1743 | printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", |
1744 | op->name, (unsigned int) (op - vle_opcodes), | |
1745 | (unsigned int) new_seg, (unsigned long long) op->opcode, | |
1746 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
b9c361e0 | 1747 | #endif |
2ceb7719 PB |
1748 | |
1749 | /* The major opcodes had better be sorted. Code in the disassembler | |
1750 | assumes the insns are sorted according to major opcode. */ | |
1751 | if (op != vle_opcodes | |
1752 | && new_seg < VLE_OP_TO_SEG (VLE_OP (op[-1].opcode, op[-1].mask))) | |
1753 | { | |
1754 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
1755 | bad_insn = TRUE; | |
b9c361e0 JL |
1756 | } |
1757 | ||
1758 | bad_insn |= insn_validate (op); | |
c43a438d | 1759 | } |
252b5132 | 1760 | |
bdc70b4a | 1761 | if ((ppc_cpu & op->flags) != 0 |
fe0e921f AM |
1762 | && !(ppc_cpu & op->deprecated) |
1763 | && str_hash_insert (ppc_hash, op->name, op, 0) != NULL) | |
1764 | { | |
1765 | as_bad (_("duplicate %s"), op->name); | |
1766 | bad_insn = TRUE; | |
1767 | } | |
252b5132 RH |
1768 | } |
1769 | ||
74081948 AF |
1770 | /* SPE2 instructions */ |
1771 | if ((ppc_cpu & PPC_OPCODE_SPE2) == PPC_OPCODE_SPE2) | |
1772 | { | |
1773 | op_end = spe2_opcodes + spe2_num_opcodes; | |
1774 | for (op = spe2_opcodes; op < op_end; op++) | |
1775 | { | |
1776 | if (ENABLE_CHECKING) | |
1777 | { | |
1778 | if (op != spe2_opcodes) | |
1779 | { | |
1780 | unsigned old_seg, new_seg; | |
1781 | ||
1782 | old_seg = VLE_OP (op[-1].opcode, op[-1].mask); | |
1783 | old_seg = VLE_OP_TO_SEG (old_seg); | |
1784 | new_seg = VLE_OP (op[0].opcode, op[0].mask); | |
1785 | new_seg = VLE_OP_TO_SEG (new_seg); | |
1786 | ||
1787 | /* The major opcodes had better be sorted. Code in the | |
1788 | disassembler assumes the insns are sorted according to | |
1789 | major opcode. */ | |
1790 | if (new_seg < old_seg) | |
1791 | { | |
1792 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
1793 | bad_insn = TRUE; | |
1794 | } | |
1795 | } | |
1796 | ||
1797 | bad_insn |= insn_validate (op); | |
1798 | } | |
1799 | ||
fe0e921f AM |
1800 | if ((ppc_cpu & op->flags) != 0 |
1801 | && !(ppc_cpu & op->deprecated) | |
1802 | && str_hash_insert (ppc_hash, op->name, op, 0) != NULL) | |
1803 | { | |
1804 | as_bad (_("duplicate %s"), op->name); | |
1805 | bad_insn = TRUE; | |
1806 | } | |
74081948 AF |
1807 | } |
1808 | ||
1809 | for (op = spe2_opcodes; op < op_end; op++) | |
fe0e921f | 1810 | str_hash_insert (ppc_hash, op->name, op, 0); |
74081948 AF |
1811 | } |
1812 | ||
252b5132 | 1813 | /* Insert the macros into a hash table. */ |
629310ab | 1814 | ppc_macro_hash = str_htab_create (); |
252b5132 RH |
1815 | |
1816 | macro_end = powerpc_macros + powerpc_num_macros; | |
1817 | for (macro = powerpc_macros; macro < macro_end; macro++) | |
fe0e921f AM |
1818 | if (((macro->flags & ppc_cpu) != 0 |
1819 | || (ppc_cpu & PPC_OPCODE_ANY) != 0) | |
1820 | && str_hash_insert (ppc_macro_hash, macro->name, macro, 0) != NULL) | |
1821 | { | |
1822 | as_bad (_("duplicate %s"), macro->name); | |
1823 | bad_insn = TRUE; | |
1824 | } | |
252b5132 | 1825 | |
b84bf58a | 1826 | if (bad_insn) |
252b5132 | 1827 | abort (); |
69c040df AM |
1828 | } |
1829 | ||
1830 | /* This function is called when the assembler starts up. It is called | |
1831 | after the options have been parsed and the output file has been | |
1832 | opened. */ | |
1833 | ||
1834 | void | |
98027b10 | 1835 | md_begin (void) |
69c040df AM |
1836 | { |
1837 | ppc_set_cpu (); | |
1838 | ||
1839 | ppc_cie_data_alignment = ppc_obj64 ? -8 : -4; | |
8fbf7334 | 1840 | ppc_dwarf2_line_min_insn_length = (ppc_cpu & PPC_OPCODE_VLE) ? 2 : 4; |
69c040df AM |
1841 | |
1842 | #ifdef OBJ_ELF | |
1843 | /* Set the ELF flags if desired. */ | |
1844 | if (ppc_flags && !msolaris) | |
1845 | bfd_set_private_flags (stdoutput, ppc_flags); | |
1846 | #endif | |
1847 | ||
1848 | ppc_setup_opcodes (); | |
252b5132 | 1849 | |
67c1ffbe | 1850 | /* Tell the main code what the endianness is if it is not overridden |
99a814a1 | 1851 | by the user. */ |
252b5132 RH |
1852 | if (!set_target_endian) |
1853 | { | |
1854 | set_target_endian = 1; | |
1855 | target_big_endian = PPC_BIG_ENDIAN; | |
1856 | } | |
1857 | ||
1858 | #ifdef OBJ_XCOFF | |
1859 | ppc_coff_debug_section = coff_section_from_bfd_index (stdoutput, N_DEBUG); | |
1860 | ||
1861 | /* Create dummy symbols to serve as initial csects. This forces the | |
1862 | text csects to precede the data csects. These symbols will not | |
1863 | be output. */ | |
1864 | ppc_text_csects = symbol_make ("dummy\001"); | |
809ffe0d | 1865 | symbol_get_tc (ppc_text_csects)->within = ppc_text_csects; |
252b5132 | 1866 | ppc_data_csects = symbol_make ("dummy\001"); |
809ffe0d | 1867 | symbol_get_tc (ppc_data_csects)->within = ppc_data_csects; |
252b5132 | 1868 | #endif |
252b5132 RH |
1869 | } |
1870 | ||
6a0c61b7 | 1871 | void |
98027b10 | 1872 | ppc_cleanup (void) |
6a0c61b7 | 1873 | { |
dc1d03fc | 1874 | #ifdef OBJ_ELF |
6a0c61b7 EZ |
1875 | if (ppc_apuinfo_list == NULL) |
1876 | return; | |
1877 | ||
1878 | /* Ok, so write the section info out. We have this layout: | |
1879 | ||
1880 | byte data what | |
1881 | ---- ---- ---- | |
1882 | 0 8 length of "APUinfo\0" | |
1883 | 4 (n*4) number of APU's (4 bytes each) | |
1884 | 8 2 note type 2 | |
1885 | 12 "APUinfo\0" name | |
1886 | 20 APU#1 first APU's info | |
1887 | 24 APU#2 second APU's info | |
1888 | ... ... | |
1889 | */ | |
1890 | { | |
1891 | char *p; | |
1892 | asection *seg = now_seg; | |
1893 | subsegT subseg = now_subseg; | |
1894 | asection *apuinfo_secp = (asection *) NULL; | |
49181a6a | 1895 | unsigned int i; |
6a0c61b7 EZ |
1896 | |
1897 | /* Create the .PPC.EMB.apuinfo section. */ | |
14b57c7c | 1898 | apuinfo_secp = subseg_new (APUINFO_SECTION_NAME, 0); |
fd361982 | 1899 | bfd_set_section_flags (apuinfo_secp, SEC_HAS_CONTENTS | SEC_READONLY); |
6a0c61b7 EZ |
1900 | |
1901 | p = frag_more (4); | |
1902 | md_number_to_chars (p, (valueT) 8, 4); | |
1903 | ||
1904 | p = frag_more (4); | |
e98d298c | 1905 | md_number_to_chars (p, (valueT) ppc_apuinfo_num * 4, 4); |
6a0c61b7 EZ |
1906 | |
1907 | p = frag_more (4); | |
1908 | md_number_to_chars (p, (valueT) 2, 4); | |
1909 | ||
1910 | p = frag_more (8); | |
14b57c7c | 1911 | strcpy (p, APUINFO_LABEL); |
6a0c61b7 EZ |
1912 | |
1913 | for (i = 0; i < ppc_apuinfo_num; i++) | |
1914 | { | |
b34976b6 AM |
1915 | p = frag_more (4); |
1916 | md_number_to_chars (p, (valueT) ppc_apuinfo_list[i], 4); | |
6a0c61b7 EZ |
1917 | } |
1918 | ||
1919 | frag_align (2, 0, 0); | |
1920 | ||
1921 | /* We probably can't restore the current segment, for there likely | |
1922 | isn't one yet... */ | |
1923 | if (seg && subseg) | |
1924 | subseg_set (seg, subseg); | |
1925 | } | |
dc1d03fc | 1926 | #endif |
6a0c61b7 EZ |
1927 | } |
1928 | ||
252b5132 RH |
1929 | /* Insert an operand value into an instruction. */ |
1930 | ||
0f873fd5 PB |
1931 | static uint64_t |
1932 | ppc_insert_operand (uint64_t insn, | |
a1867a27 | 1933 | const struct powerpc_operand *operand, |
0f873fd5 | 1934 | int64_t val, |
91d6fa6a | 1935 | ppc_cpu_t cpu, |
3b4dbbbf | 1936 | const char *file, |
a1867a27 | 1937 | unsigned int line) |
252b5132 | 1938 | { |
0f873fd5 | 1939 | int64_t min, max, right; |
eb42fac1 | 1940 | |
b84bf58a AM |
1941 | max = operand->bitm; |
1942 | right = max & -max; | |
1943 | min = 0; | |
1944 | ||
a47622ac | 1945 | if ((operand->flags & PPC_OPERAND_SIGNOPT) != 0) |
252b5132 | 1946 | { |
a255f00a AM |
1947 | /* Extend the allowed range for addis to [-32768, 65535]. |
1948 | Similarly for cmpli and some VLE high part insns. For 64-bit | |
1949 | it would be good to disable this for signed fields since the | |
a47622ac AM |
1950 | value is sign extended into the high 32 bits of the register. |
1951 | If the value is, say, an address, then we might care about | |
1952 | the high bits. However, gcc as of 2014-06 uses unsigned | |
1953 | values when loading the high part of 64-bit constants using | |
a255f00a AM |
1954 | lis. */ |
1955 | min = ~(max >> 1) & -right; | |
a47622ac AM |
1956 | } |
1957 | else if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
1958 | { | |
1959 | max = (max >> 1) & -right; | |
931774a9 | 1960 | min = ~max & -right; |
b84bf58a | 1961 | } |
252b5132 | 1962 | |
b84bf58a | 1963 | if ((operand->flags & PPC_OPERAND_PLUS1) != 0) |
3896c469 | 1964 | max++; |
252b5132 | 1965 | |
b84bf58a | 1966 | if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0) |
a1867a27 | 1967 | { |
0f873fd5 | 1968 | int64_t tmp = min; |
a1867a27 AM |
1969 | min = -max; |
1970 | max = -tmp; | |
1971 | } | |
b84bf58a | 1972 | |
a1867a27 AM |
1973 | if (min <= max) |
1974 | { | |
1975 | /* Some people write constants with the sign extension done by | |
1976 | hand but only up to 32 bits. This shouldn't really be valid, | |
1977 | but, to permit this code to assemble on a 64-bit host, we | |
1978 | sign extend the 32-bit value to 64 bits if so doing makes the | |
8acf1435 PB |
1979 | value valid. We only do this for operands that are 32-bits or |
1980 | smaller. */ | |
a1867a27 | 1981 | if (val > max |
8acf1435 | 1982 | && (operand->bitm & ~0xffffffffULL) == 0 |
0f873fd5 PB |
1983 | && (val - (1LL << 32)) >= min |
1984 | && (val - (1LL << 32)) <= max | |
1985 | && ((val - (1LL << 32)) & (right - 1)) == 0) | |
1986 | val = val - (1LL << 32); | |
a1867a27 AM |
1987 | |
1988 | /* Similarly, people write expressions like ~(1<<15), and expect | |
1989 | this to be OK for a 32-bit unsigned value. */ | |
1990 | else if (val < min | |
8acf1435 | 1991 | && (operand->bitm & ~0xffffffffULL) == 0 |
0f873fd5 PB |
1992 | && (val + (1LL << 32)) >= min |
1993 | && (val + (1LL << 32)) <= max | |
1994 | && ((val + (1LL << 32)) & (right - 1)) == 0) | |
1995 | val = val + (1LL << 32); | |
a1867a27 AM |
1996 | |
1997 | else if (val < min | |
1998 | || val > max | |
1999 | || (val & (right - 1)) != 0) | |
2000 | as_bad_value_out_of_range (_("operand"), val, min, max, file, line); | |
2001 | } | |
b84bf58a | 2002 | |
252b5132 RH |
2003 | if (operand->insert) |
2004 | { | |
2005 | const char *errmsg; | |
2006 | ||
2007 | errmsg = NULL; | |
0f873fd5 | 2008 | insn = (*operand->insert) (insn, val, cpu, &errmsg); |
252b5132 | 2009 | if (errmsg != (const char *) NULL) |
ee2c9aa9 | 2010 | as_bad_where (file, line, "%s", errmsg); |
252b5132 | 2011 | } |
b9c361e0 | 2012 | else if (operand->shift >= 0) |
0f873fd5 | 2013 | insn |= (val & operand->bitm) << operand->shift; |
b9c361e0 | 2014 | else |
0f873fd5 | 2015 | insn |= (val & operand->bitm) >> -operand->shift; |
252b5132 RH |
2016 | |
2017 | return insn; | |
2018 | } | |
2019 | ||
2020 | \f | |
2021 | #ifdef OBJ_ELF | |
2022 | /* Parse @got, etc. and return the desired relocation. */ | |
2023 | static bfd_reloc_code_real_type | |
98027b10 | 2024 | ppc_elf_suffix (char **str_p, expressionS *exp_p) |
252b5132 RH |
2025 | { |
2026 | struct map_bfd { | |
e0471c16 | 2027 | const char *string; |
b7d7dc63 AM |
2028 | unsigned int length : 8; |
2029 | unsigned int valid32 : 1; | |
2030 | unsigned int valid64 : 1; | |
2031 | unsigned int reloc; | |
252b5132 RH |
2032 | }; |
2033 | ||
2034 | char ident[20]; | |
2035 | char *str = *str_p; | |
2036 | char *str2; | |
2037 | int ch; | |
2038 | int len; | |
15c1449b | 2039 | const struct map_bfd *ptr; |
252b5132 | 2040 | |
b7d7dc63 AM |
2041 | #define MAP(str, reloc) { str, sizeof (str) - 1, 1, 1, reloc } |
2042 | #define MAP32(str, reloc) { str, sizeof (str) - 1, 1, 0, reloc } | |
2043 | #define MAP64(str, reloc) { str, sizeof (str) - 1, 0, 1, reloc } | |
252b5132 | 2044 | |
15c1449b | 2045 | static const struct map_bfd mapping[] = { |
b7d7dc63 AM |
2046 | MAP ("l", BFD_RELOC_LO16), |
2047 | MAP ("h", BFD_RELOC_HI16), | |
2048 | MAP ("ha", BFD_RELOC_HI16_S), | |
2049 | MAP ("brtaken", BFD_RELOC_PPC_B16_BRTAKEN), | |
2050 | MAP ("brntaken", BFD_RELOC_PPC_B16_BRNTAKEN), | |
2051 | MAP ("got", BFD_RELOC_16_GOTOFF), | |
2052 | MAP ("got@l", BFD_RELOC_LO16_GOTOFF), | |
2053 | MAP ("got@h", BFD_RELOC_HI16_GOTOFF), | |
2054 | MAP ("got@ha", BFD_RELOC_HI16_S_GOTOFF), | |
2055 | MAP ("plt@l", BFD_RELOC_LO16_PLTOFF), | |
2056 | MAP ("plt@h", BFD_RELOC_HI16_PLTOFF), | |
2057 | MAP ("plt@ha", BFD_RELOC_HI16_S_PLTOFF), | |
2058 | MAP ("copy", BFD_RELOC_PPC_COPY), | |
2059 | MAP ("globdat", BFD_RELOC_PPC_GLOB_DAT), | |
2060 | MAP ("sectoff", BFD_RELOC_16_BASEREL), | |
2061 | MAP ("sectoff@l", BFD_RELOC_LO16_BASEREL), | |
2062 | MAP ("sectoff@h", BFD_RELOC_HI16_BASEREL), | |
2063 | MAP ("sectoff@ha", BFD_RELOC_HI16_S_BASEREL), | |
2064 | MAP ("tls", BFD_RELOC_PPC_TLS), | |
2065 | MAP ("dtpmod", BFD_RELOC_PPC_DTPMOD), | |
2066 | MAP ("dtprel", BFD_RELOC_PPC_DTPREL), | |
2067 | MAP ("dtprel@l", BFD_RELOC_PPC_DTPREL16_LO), | |
2068 | MAP ("dtprel@h", BFD_RELOC_PPC_DTPREL16_HI), | |
2069 | MAP ("dtprel@ha", BFD_RELOC_PPC_DTPREL16_HA), | |
2070 | MAP ("tprel", BFD_RELOC_PPC_TPREL), | |
2071 | MAP ("tprel@l", BFD_RELOC_PPC_TPREL16_LO), | |
2072 | MAP ("tprel@h", BFD_RELOC_PPC_TPREL16_HI), | |
2073 | MAP ("tprel@ha", BFD_RELOC_PPC_TPREL16_HA), | |
2074 | MAP ("got@tlsgd", BFD_RELOC_PPC_GOT_TLSGD16), | |
2075 | MAP ("got@tlsgd@l", BFD_RELOC_PPC_GOT_TLSGD16_LO), | |
2076 | MAP ("got@tlsgd@h", BFD_RELOC_PPC_GOT_TLSGD16_HI), | |
2077 | MAP ("got@tlsgd@ha", BFD_RELOC_PPC_GOT_TLSGD16_HA), | |
2078 | MAP ("got@tlsld", BFD_RELOC_PPC_GOT_TLSLD16), | |
2079 | MAP ("got@tlsld@l", BFD_RELOC_PPC_GOT_TLSLD16_LO), | |
2080 | MAP ("got@tlsld@h", BFD_RELOC_PPC_GOT_TLSLD16_HI), | |
2081 | MAP ("got@tlsld@ha", BFD_RELOC_PPC_GOT_TLSLD16_HA), | |
2082 | MAP ("got@dtprel", BFD_RELOC_PPC_GOT_DTPREL16), | |
2083 | MAP ("got@dtprel@l", BFD_RELOC_PPC_GOT_DTPREL16_LO), | |
2084 | MAP ("got@dtprel@h", BFD_RELOC_PPC_GOT_DTPREL16_HI), | |
2085 | MAP ("got@dtprel@ha", BFD_RELOC_PPC_GOT_DTPREL16_HA), | |
2086 | MAP ("got@tprel", BFD_RELOC_PPC_GOT_TPREL16), | |
2087 | MAP ("got@tprel@l", BFD_RELOC_PPC_GOT_TPREL16_LO), | |
2088 | MAP ("got@tprel@h", BFD_RELOC_PPC_GOT_TPREL16_HI), | |
2089 | MAP ("got@tprel@ha", BFD_RELOC_PPC_GOT_TPREL16_HA), | |
2090 | MAP32 ("fixup", BFD_RELOC_CTOR), | |
2091 | MAP32 ("plt", BFD_RELOC_24_PLT_PCREL), | |
2092 | MAP32 ("pltrel24", BFD_RELOC_24_PLT_PCREL), | |
2093 | MAP32 ("local24pc", BFD_RELOC_PPC_LOCAL24PC), | |
2094 | MAP32 ("local", BFD_RELOC_PPC_LOCAL24PC), | |
2095 | MAP32 ("pltrel", BFD_RELOC_32_PLT_PCREL), | |
2096 | MAP32 ("sdarel", BFD_RELOC_GPREL16), | |
b9c361e0 JL |
2097 | MAP32 ("sdarel@l", BFD_RELOC_PPC_VLE_SDAREL_LO16A), |
2098 | MAP32 ("sdarel@h", BFD_RELOC_PPC_VLE_SDAREL_HI16A), | |
2099 | MAP32 ("sdarel@ha", BFD_RELOC_PPC_VLE_SDAREL_HA16A), | |
b7d7dc63 AM |
2100 | MAP32 ("naddr", BFD_RELOC_PPC_EMB_NADDR32), |
2101 | MAP32 ("naddr16", BFD_RELOC_PPC_EMB_NADDR16), | |
2102 | MAP32 ("naddr@l", BFD_RELOC_PPC_EMB_NADDR16_LO), | |
2103 | MAP32 ("naddr@h", BFD_RELOC_PPC_EMB_NADDR16_HI), | |
2104 | MAP32 ("naddr@ha", BFD_RELOC_PPC_EMB_NADDR16_HA), | |
2105 | MAP32 ("sdai16", BFD_RELOC_PPC_EMB_SDAI16), | |
2106 | MAP32 ("sda2rel", BFD_RELOC_PPC_EMB_SDA2REL), | |
2107 | MAP32 ("sda2i16", BFD_RELOC_PPC_EMB_SDA2I16), | |
2108 | MAP32 ("sda21", BFD_RELOC_PPC_EMB_SDA21), | |
b9c361e0 | 2109 | MAP32 ("sda21@l", BFD_RELOC_PPC_VLE_SDA21_LO), |
b7d7dc63 AM |
2110 | MAP32 ("mrkref", BFD_RELOC_PPC_EMB_MRKREF), |
2111 | MAP32 ("relsect", BFD_RELOC_PPC_EMB_RELSEC16), | |
2112 | MAP32 ("relsect@l", BFD_RELOC_PPC_EMB_RELST_LO), | |
2113 | MAP32 ("relsect@h", BFD_RELOC_PPC_EMB_RELST_HI), | |
2114 | MAP32 ("relsect@ha", BFD_RELOC_PPC_EMB_RELST_HA), | |
2115 | MAP32 ("bitfld", BFD_RELOC_PPC_EMB_BIT_FLD), | |
2116 | MAP32 ("relsda", BFD_RELOC_PPC_EMB_RELSDA), | |
2117 | MAP32 ("xgot", BFD_RELOC_PPC_TOC16), | |
f9c6b907 AM |
2118 | MAP64 ("high", BFD_RELOC_PPC64_ADDR16_HIGH), |
2119 | MAP64 ("higha", BFD_RELOC_PPC64_ADDR16_HIGHA), | |
b7d7dc63 AM |
2120 | MAP64 ("higher", BFD_RELOC_PPC64_HIGHER), |
2121 | MAP64 ("highera", BFD_RELOC_PPC64_HIGHER_S), | |
2122 | MAP64 ("highest", BFD_RELOC_PPC64_HIGHEST), | |
2123 | MAP64 ("highesta", BFD_RELOC_PPC64_HIGHEST_S), | |
2124 | MAP64 ("tocbase", BFD_RELOC_PPC64_TOC), | |
2125 | MAP64 ("toc", BFD_RELOC_PPC_TOC16), | |
2126 | MAP64 ("toc@l", BFD_RELOC_PPC64_TOC16_LO), | |
2127 | MAP64 ("toc@h", BFD_RELOC_PPC64_TOC16_HI), | |
2128 | MAP64 ("toc@ha", BFD_RELOC_PPC64_TOC16_HA), | |
f9c6b907 AM |
2129 | MAP64 ("dtprel@high", BFD_RELOC_PPC64_DTPREL16_HIGH), |
2130 | MAP64 ("dtprel@higha", BFD_RELOC_PPC64_DTPREL16_HIGHA), | |
b7d7dc63 AM |
2131 | MAP64 ("dtprel@higher", BFD_RELOC_PPC64_DTPREL16_HIGHER), |
2132 | MAP64 ("dtprel@highera", BFD_RELOC_PPC64_DTPREL16_HIGHERA), | |
2133 | MAP64 ("dtprel@highest", BFD_RELOC_PPC64_DTPREL16_HIGHEST), | |
2134 | MAP64 ("dtprel@highesta", BFD_RELOC_PPC64_DTPREL16_HIGHESTA), | |
45965137 | 2135 | MAP64 ("localentry", BFD_RELOC_PPC64_ADDR64_LOCAL), |
f9c6b907 AM |
2136 | MAP64 ("tprel@high", BFD_RELOC_PPC64_TPREL16_HIGH), |
2137 | MAP64 ("tprel@higha", BFD_RELOC_PPC64_TPREL16_HIGHA), | |
b7d7dc63 AM |
2138 | MAP64 ("tprel@higher", BFD_RELOC_PPC64_TPREL16_HIGHER), |
2139 | MAP64 ("tprel@highera", BFD_RELOC_PPC64_TPREL16_HIGHERA), | |
2140 | MAP64 ("tprel@highest", BFD_RELOC_PPC64_TPREL16_HIGHEST), | |
2141 | MAP64 ("tprel@highesta", BFD_RELOC_PPC64_TPREL16_HIGHESTA), | |
05d0e962 | 2142 | MAP64 ("notoc", BFD_RELOC_PPC64_REL24_NOTOC), |
5663e321 AM |
2143 | MAP64 ("pcrel", BFD_RELOC_PPC64_PCREL34), |
2144 | MAP64 ("got@pcrel", BFD_RELOC_PPC64_GOT_PCREL34), | |
2145 | MAP64 ("plt@pcrel", BFD_RELOC_PPC64_PLT_PCREL34), | |
c213164a | 2146 | MAP64 ("tls@pcrel", BFD_RELOC_PPC64_TLS_PCREL), |
87c69f97 AM |
2147 | MAP64 ("got@tlsgd@pcrel", BFD_RELOC_PPC64_GOT_TLSGD_PCREL34), |
2148 | MAP64 ("got@tlsld@pcrel", BFD_RELOC_PPC64_GOT_TLSLD_PCREL34), | |
2149 | MAP64 ("got@tprel@pcrel", BFD_RELOC_PPC64_GOT_TPREL_PCREL34), | |
2150 | MAP64 ("got@dtprel@pcrel", BFD_RELOC_PPC64_GOT_DTPREL_PCREL34), | |
5663e321 AM |
2151 | MAP64 ("higher34", BFD_RELOC_PPC64_ADDR16_HIGHER34), |
2152 | MAP64 ("highera34", BFD_RELOC_PPC64_ADDR16_HIGHERA34), | |
2153 | MAP64 ("highest34", BFD_RELOC_PPC64_ADDR16_HIGHEST34), | |
2154 | MAP64 ("highesta34", BFD_RELOC_PPC64_ADDR16_HIGHESTA34), | |
62ebcb5c | 2155 | { (char *) 0, 0, 0, 0, BFD_RELOC_NONE } |
252b5132 RH |
2156 | }; |
2157 | ||
2158 | if (*str++ != '@') | |
62ebcb5c | 2159 | return BFD_RELOC_NONE; |
252b5132 RH |
2160 | |
2161 | for (ch = *str, str2 = ident; | |
2162 | (str2 < ident + sizeof (ident) - 1 | |
3882b010 | 2163 | && (ISALNUM (ch) || ch == '@')); |
252b5132 RH |
2164 | ch = *++str) |
2165 | { | |
3882b010 | 2166 | *str2++ = TOLOWER (ch); |
252b5132 RH |
2167 | } |
2168 | ||
2169 | *str2 = '\0'; | |
2170 | len = str2 - ident; | |
2171 | ||
2172 | ch = ident[0]; | |
2173 | for (ptr = &mapping[0]; ptr->length > 0; ptr++) | |
2174 | if (ch == ptr->string[0] | |
2175 | && len == ptr->length | |
b7d7dc63 AM |
2176 | && memcmp (ident, ptr->string, ptr->length) == 0 |
2177 | && (ppc_obj64 ? ptr->valid64 : ptr->valid32)) | |
252b5132 | 2178 | { |
15c1449b AM |
2179 | int reloc = ptr->reloc; |
2180 | ||
727fc41e AM |
2181 | if (!ppc_obj64 && exp_p->X_add_number != 0) |
2182 | { | |
2183 | switch (reloc) | |
2184 | { | |
2185 | case BFD_RELOC_16_GOTOFF: | |
2186 | case BFD_RELOC_LO16_GOTOFF: | |
2187 | case BFD_RELOC_HI16_GOTOFF: | |
2188 | case BFD_RELOC_HI16_S_GOTOFF: | |
e47d413a AM |
2189 | as_warn (_("symbol+offset@%s means symbol@%s+offset"), |
2190 | ptr->string, ptr->string); | |
727fc41e AM |
2191 | break; |
2192 | ||
2193 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
2194 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
2195 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
2196 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
2197 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
2198 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
2199 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
2200 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
2201 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
2202 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
2203 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
2204 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
2205 | case BFD_RELOC_PPC_GOT_TPREL16: | |
2206 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
2207 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
2208 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
e47d413a | 2209 | as_bad (_("symbol+offset@%s not supported"), ptr->string); |
727fc41e AM |
2210 | break; |
2211 | } | |
2212 | } | |
5f6db75a AM |
2213 | |
2214 | /* Now check for identifier@suffix+constant. */ | |
2215 | if (*str == '-' || *str == '+') | |
252b5132 | 2216 | { |
5f6db75a AM |
2217 | char *orig_line = input_line_pointer; |
2218 | expressionS new_exp; | |
2219 | ||
2220 | input_line_pointer = str; | |
2221 | expression (&new_exp); | |
2222 | if (new_exp.X_op == O_constant) | |
252b5132 | 2223 | { |
5f6db75a AM |
2224 | exp_p->X_add_number += new_exp.X_add_number; |
2225 | str = input_line_pointer; | |
252b5132 | 2226 | } |
5f6db75a AM |
2227 | |
2228 | if (&input_line_pointer != str_p) | |
2229 | input_line_pointer = orig_line; | |
252b5132 | 2230 | } |
252b5132 | 2231 | *str_p = str; |
0baf16f2 | 2232 | |
2b3c4602 | 2233 | if (reloc == (int) BFD_RELOC_PPC64_TOC |
9f2b53d7 AM |
2234 | && exp_p->X_op == O_symbol |
2235 | && strcmp (S_GET_NAME (exp_p->X_add_symbol), ".TOC.") == 0) | |
0baf16f2 | 2236 | { |
9f2b53d7 AM |
2237 | /* Change the symbol so that the dummy .TOC. symbol can be |
2238 | omitted from the object file. */ | |
0baf16f2 AM |
2239 | exp_p->X_add_symbol = &abs_symbol; |
2240 | } | |
2241 | ||
15c1449b | 2242 | return (bfd_reloc_code_real_type) reloc; |
252b5132 RH |
2243 | } |
2244 | ||
62ebcb5c | 2245 | return BFD_RELOC_NONE; |
252b5132 RH |
2246 | } |
2247 | ||
62ebcb5c | 2248 | /* Support @got, etc. on constants emitted via .short, .int etc. */ |
99a814a1 | 2249 | |
62ebcb5c AM |
2250 | bfd_reloc_code_real_type |
2251 | ppc_elf_parse_cons (expressionS *exp, unsigned int nbytes) | |
2252 | { | |
2253 | expression (exp); | |
2254 | if (nbytes >= 2 && *input_line_pointer == '@') | |
2255 | return ppc_elf_suffix (&input_line_pointer, exp); | |
2256 | return BFD_RELOC_NONE; | |
252b5132 RH |
2257 | } |
2258 | ||
bf7279d5 AM |
2259 | /* Warn when emitting data to code sections, unless we are emitting |
2260 | a relocation that ld --ppc476-workaround uses to recognise data | |
2261 | *and* there was an unconditional branch prior to the data. */ | |
2262 | ||
2263 | void | |
2264 | ppc_elf_cons_fix_check (expressionS *exp ATTRIBUTE_UNUSED, | |
2265 | unsigned int nbytes, fixS *fix) | |
2266 | { | |
2267 | if (warn_476 | |
2268 | && (now_seg->flags & SEC_CODE) != 0 | |
2269 | && (nbytes != 4 | |
2270 | || fix == NULL | |
2271 | || !(fix->fx_r_type == BFD_RELOC_32 | |
2272 | || fix->fx_r_type == BFD_RELOC_CTOR | |
2273 | || fix->fx_r_type == BFD_RELOC_32_PCREL) | |
2274 | || !(last_seg == now_seg && last_subseg == now_subseg) | |
2275 | || !((last_insn & (0x3f << 26)) == (18u << 26) | |
2276 | || ((last_insn & (0x3f << 26)) == (16u << 26) | |
2277 | && (last_insn & (0x14 << 21)) == (0x14 << 21)) | |
2278 | || ((last_insn & (0x3f << 26)) == (19u << 26) | |
2279 | && (last_insn & (0x3ff << 1)) == (16u << 1) | |
2280 | && (last_insn & (0x14 << 21)) == (0x14 << 21))))) | |
2281 | { | |
2282 | /* Flag that we've warned. */ | |
2283 | if (fix != NULL) | |
2284 | fix->fx_tcbit = 1; | |
2285 | ||
2286 | as_warn (_("data in executable section")); | |
2287 | } | |
2288 | } | |
2289 | ||
252b5132 RH |
2290 | /* Solaris pseduo op to change to the .rodata section. */ |
2291 | static void | |
98027b10 | 2292 | ppc_elf_rdata (int xxx) |
252b5132 RH |
2293 | { |
2294 | char *save_line = input_line_pointer; | |
2295 | static char section[] = ".rodata\n"; | |
2296 | ||
99a814a1 | 2297 | /* Just pretend this is .section .rodata */ |
252b5132 RH |
2298 | input_line_pointer = section; |
2299 | obj_elf_section (xxx); | |
2300 | ||
2301 | input_line_pointer = save_line; | |
2302 | } | |
2303 | ||
99a814a1 | 2304 | /* Pseudo op to make file scope bss items. */ |
252b5132 | 2305 | static void |
98027b10 | 2306 | ppc_elf_lcomm (int xxx ATTRIBUTE_UNUSED) |
252b5132 | 2307 | { |
98027b10 AM |
2308 | char *name; |
2309 | char c; | |
2310 | char *p; | |
252b5132 | 2311 | offsetT size; |
98027b10 | 2312 | symbolS *symbolP; |
252b5132 RH |
2313 | offsetT align; |
2314 | segT old_sec; | |
2315 | int old_subsec; | |
2316 | char *pfrag; | |
2317 | int align2; | |
2318 | ||
d02603dc | 2319 | c = get_symbol_name (&name); |
252b5132 | 2320 | |
d02603dc | 2321 | /* Just after name is now '\0'. */ |
252b5132 RH |
2322 | p = input_line_pointer; |
2323 | *p = c; | |
d02603dc | 2324 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
2325 | if (*input_line_pointer != ',') |
2326 | { | |
d6ed37ed | 2327 | as_bad (_("expected comma after symbol-name: rest of line ignored.")); |
252b5132 RH |
2328 | ignore_rest_of_line (); |
2329 | return; | |
2330 | } | |
2331 | ||
2332 | input_line_pointer++; /* skip ',' */ | |
2333 | if ((size = get_absolute_expression ()) < 0) | |
2334 | { | |
2335 | as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) size); | |
2336 | ignore_rest_of_line (); | |
2337 | return; | |
2338 | } | |
2339 | ||
2340 | /* The third argument to .lcomm is the alignment. */ | |
2341 | if (*input_line_pointer != ',') | |
2342 | align = 8; | |
2343 | else | |
2344 | { | |
2345 | ++input_line_pointer; | |
2346 | align = get_absolute_expression (); | |
2347 | if (align <= 0) | |
2348 | { | |
2349 | as_warn (_("ignoring bad alignment")); | |
2350 | align = 8; | |
2351 | } | |
2352 | } | |
2353 | ||
2354 | *p = 0; | |
2355 | symbolP = symbol_find_or_make (name); | |
2356 | *p = c; | |
2357 | ||
2358 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
2359 | { | |
d6ed37ed | 2360 | as_bad (_("ignoring attempt to re-define symbol `%s'."), |
252b5132 RH |
2361 | S_GET_NAME (symbolP)); |
2362 | ignore_rest_of_line (); | |
2363 | return; | |
2364 | } | |
2365 | ||
2366 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
2367 | { | |
d6ed37ed | 2368 | as_bad (_("length of .lcomm \"%s\" is already %ld. Not changed to %ld."), |
252b5132 RH |
2369 | S_GET_NAME (symbolP), |
2370 | (long) S_GET_VALUE (symbolP), | |
2371 | (long) size); | |
2372 | ||
2373 | ignore_rest_of_line (); | |
2374 | return; | |
2375 | } | |
2376 | ||
99a814a1 | 2377 | /* Allocate_bss. */ |
252b5132 RH |
2378 | old_sec = now_seg; |
2379 | old_subsec = now_subseg; | |
2380 | if (align) | |
2381 | { | |
99a814a1 | 2382 | /* Convert to a power of 2 alignment. */ |
252b5132 RH |
2383 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2); |
2384 | if (align != 1) | |
2385 | { | |
d6ed37ed | 2386 | as_bad (_("common alignment not a power of 2")); |
252b5132 RH |
2387 | ignore_rest_of_line (); |
2388 | return; | |
2389 | } | |
2390 | } | |
2391 | else | |
2392 | align2 = 0; | |
2393 | ||
2394 | record_alignment (bss_section, align2); | |
cbe02d4f | 2395 | subseg_set (bss_section, 1); |
252b5132 RH |
2396 | if (align2) |
2397 | frag_align (align2, 0, 0); | |
2398 | if (S_GET_SEGMENT (symbolP) == bss_section) | |
49309057 ILT |
2399 | symbol_get_frag (symbolP)->fr_symbol = 0; |
2400 | symbol_set_frag (symbolP, frag_now); | |
252b5132 RH |
2401 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
2402 | (char *) 0); | |
2403 | *pfrag = 0; | |
2404 | S_SET_SIZE (symbolP, size); | |
2405 | S_SET_SEGMENT (symbolP, bss_section); | |
2406 | subseg_set (old_sec, old_subsec); | |
2407 | demand_empty_rest_of_line (); | |
2408 | } | |
2409 | ||
6911b7dc AM |
2410 | /* Pseudo op to set symbol local entry point. */ |
2411 | static void | |
2412 | ppc_elf_localentry (int ignore ATTRIBUTE_UNUSED) | |
2413 | { | |
d02603dc NC |
2414 | char *name; |
2415 | char c = get_symbol_name (&name); | |
6911b7dc AM |
2416 | char *p; |
2417 | expressionS exp; | |
2418 | symbolS *sym; | |
2419 | asymbol *bfdsym; | |
2420 | elf_symbol_type *elfsym; | |
2421 | ||
2422 | p = input_line_pointer; | |
2423 | *p = c; | |
d02603dc | 2424 | SKIP_WHITESPACE_AFTER_NAME (); |
6911b7dc AM |
2425 | if (*input_line_pointer != ',') |
2426 | { | |
2427 | *p = 0; | |
2428 | as_bad (_("expected comma after name `%s' in .localentry directive"), | |
2429 | name); | |
2430 | *p = c; | |
2431 | ignore_rest_of_line (); | |
2432 | return; | |
2433 | } | |
2434 | input_line_pointer++; | |
2435 | expression (&exp); | |
2436 | if (exp.X_op == O_absent) | |
2437 | { | |
2438 | as_bad (_("missing expression in .localentry directive")); | |
2439 | exp.X_op = O_constant; | |
2440 | exp.X_add_number = 0; | |
2441 | } | |
2442 | *p = 0; | |
2443 | sym = symbol_find_or_make (name); | |
2444 | *p = c; | |
2445 | ||
2446 | if (resolve_expression (&exp) | |
2447 | && exp.X_op == O_constant) | |
2448 | { | |
33cb30a1 | 2449 | unsigned int encoded, ok; |
6911b7dc | 2450 | |
33cb30a1 AM |
2451 | ok = 1; |
2452 | if (exp.X_add_number == 1 || exp.X_add_number == 7) | |
2453 | encoded = exp.X_add_number << STO_PPC64_LOCAL_BIT; | |
6911b7dc | 2454 | else |
33cb30a1 AM |
2455 | { |
2456 | encoded = PPC64_SET_LOCAL_ENTRY_OFFSET (exp.X_add_number); | |
2457 | if (exp.X_add_number != (offsetT) PPC64_LOCAL_ENTRY_OFFSET (encoded)) | |
2458 | { | |
2459 | as_bad (_(".localentry expression for `%s' " | |
2460 | "is not a valid power of 2"), S_GET_NAME (sym)); | |
2461 | ok = 0; | |
2462 | } | |
2463 | } | |
2464 | if (ok) | |
6911b7dc AM |
2465 | { |
2466 | bfdsym = symbol_get_bfdsym (sym); | |
c1229f84 | 2467 | elfsym = elf_symbol_from (bfdsym); |
6911b7dc AM |
2468 | gas_assert (elfsym); |
2469 | elfsym->internal_elf_sym.st_other &= ~STO_PPC64_LOCAL_MASK; | |
2470 | elfsym->internal_elf_sym.st_other |= encoded; | |
2471 | if (ppc_abiversion == 0) | |
2472 | ppc_abiversion = 2; | |
2473 | } | |
2474 | } | |
2475 | else | |
2476 | as_bad (_(".localentry expression for `%s' " | |
2477 | "does not evaluate to a constant"), S_GET_NAME (sym)); | |
2478 | ||
2479 | demand_empty_rest_of_line (); | |
2480 | } | |
2481 | ||
ee67d69a AM |
2482 | /* Pseudo op to set ABI version. */ |
2483 | static void | |
2484 | ppc_elf_abiversion (int ignore ATTRIBUTE_UNUSED) | |
2485 | { | |
2486 | expressionS exp; | |
2487 | ||
2488 | expression (&exp); | |
2489 | if (exp.X_op == O_absent) | |
2490 | { | |
2491 | as_bad (_("missing expression in .abiversion directive")); | |
2492 | exp.X_op = O_constant; | |
2493 | exp.X_add_number = 0; | |
2494 | } | |
2495 | ||
2496 | if (resolve_expression (&exp) | |
2497 | && exp.X_op == O_constant) | |
2498 | ppc_abiversion = exp.X_add_number; | |
2499 | else | |
2500 | as_bad (_(".abiversion expression does not evaluate to a constant")); | |
2501 | demand_empty_rest_of_line (); | |
2502 | } | |
2503 | ||
005d79fd AM |
2504 | /* Parse a .gnu_attribute directive. */ |
2505 | static void | |
2506 | ppc_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED) | |
2507 | { | |
2508 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_GNU); | |
2509 | ||
2510 | /* Check validity of defined powerpc tags. */ | |
2511 | if (tag == Tag_GNU_Power_ABI_FP | |
2512 | || tag == Tag_GNU_Power_ABI_Vector | |
2513 | || tag == Tag_GNU_Power_ABI_Struct_Return) | |
2514 | { | |
2515 | unsigned int val; | |
2516 | ||
2517 | val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, tag); | |
2518 | ||
2519 | if ((tag == Tag_GNU_Power_ABI_FP && val > 15) | |
2520 | || (tag == Tag_GNU_Power_ABI_Vector && val > 3) | |
2521 | || (tag == Tag_GNU_Power_ABI_Struct_Return && val > 2)) | |
2522 | as_warn (_("unknown .gnu_attribute value")); | |
2523 | } | |
2524 | } | |
2525 | ||
ee67d69a AM |
2526 | /* Set ABI version in output file. */ |
2527 | void | |
2528 | ppc_elf_end (void) | |
2529 | { | |
2530 | if (ppc_obj64 && ppc_abiversion != 0) | |
2531 | { | |
2532 | elf_elfheader (stdoutput)->e_flags &= ~EF_PPC64_ABI; | |
2533 | elf_elfheader (stdoutput)->e_flags |= ppc_abiversion & EF_PPC64_ABI; | |
2534 | } | |
22f72c48 AM |
2535 | /* Any selection of opcodes based on ppc_cpu after gas has finished |
2536 | parsing the file is invalid. md_apply_fix and ppc_handle_align | |
2537 | must select opcodes based on the machine in force at the point | |
2538 | where the fixup or alignment frag was created, not the machine in | |
2539 | force at the end of file. */ | |
2540 | ppc_cpu = 0; | |
ee67d69a AM |
2541 | } |
2542 | ||
252b5132 RH |
2543 | /* Validate any relocations emitted for -mrelocatable, possibly adding |
2544 | fixups for word relocations in writable segments, so we can adjust | |
2545 | them at runtime. */ | |
2546 | static void | |
98027b10 | 2547 | ppc_elf_validate_fix (fixS *fixp, segT seg) |
252b5132 RH |
2548 | { |
2549 | if (fixp->fx_done || fixp->fx_pcrel) | |
2550 | return; | |
2551 | ||
2552 | switch (shlib) | |
2553 | { | |
2554 | case SHLIB_NONE: | |
2555 | case SHLIB_PIC: | |
2556 | return; | |
2557 | ||
5d6f4f16 | 2558 | case SHLIB_MRELOCATABLE: |
62ebcb5c | 2559 | if (fixp->fx_r_type != BFD_RELOC_16_GOTOFF |
252b5132 RH |
2560 | && fixp->fx_r_type != BFD_RELOC_HI16_GOTOFF |
2561 | && fixp->fx_r_type != BFD_RELOC_LO16_GOTOFF | |
2562 | && fixp->fx_r_type != BFD_RELOC_HI16_S_GOTOFF | |
1cfc59d5 | 2563 | && fixp->fx_r_type != BFD_RELOC_16_BASEREL |
252b5132 RH |
2564 | && fixp->fx_r_type != BFD_RELOC_LO16_BASEREL |
2565 | && fixp->fx_r_type != BFD_RELOC_HI16_BASEREL | |
2566 | && fixp->fx_r_type != BFD_RELOC_HI16_S_BASEREL | |
e138127a | 2567 | && (seg->flags & SEC_LOAD) != 0 |
252b5132 RH |
2568 | && strcmp (segment_name (seg), ".got2") != 0 |
2569 | && strcmp (segment_name (seg), ".dtors") != 0 | |
2570 | && strcmp (segment_name (seg), ".ctors") != 0 | |
2571 | && strcmp (segment_name (seg), ".fixup") != 0 | |
252b5132 RH |
2572 | && strcmp (segment_name (seg), ".gcc_except_table") != 0 |
2573 | && strcmp (segment_name (seg), ".eh_frame") != 0 | |
2574 | && strcmp (segment_name (seg), ".ex_shared") != 0) | |
2575 | { | |
2576 | if ((seg->flags & (SEC_READONLY | SEC_CODE)) != 0 | |
2577 | || fixp->fx_r_type != BFD_RELOC_CTOR) | |
2578 | { | |
2579 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d6ed37ed | 2580 | _("relocation cannot be done when using -mrelocatable")); |
252b5132 RH |
2581 | } |
2582 | } | |
2583 | return; | |
2584 | } | |
2585 | } | |
0baf16f2 | 2586 | |
7e8d4ab4 AM |
2587 | /* Prevent elf_frob_file_before_adjust removing a weak undefined |
2588 | function descriptor sym if the corresponding code sym is used. */ | |
2589 | ||
2590 | void | |
98027b10 | 2591 | ppc_frob_file_before_adjust (void) |
0baf16f2 | 2592 | { |
7e8d4ab4 | 2593 | symbolS *symp; |
9232bbb0 | 2594 | asection *toc; |
0baf16f2 | 2595 | |
7e8d4ab4 AM |
2596 | if (!ppc_obj64) |
2597 | return; | |
2598 | ||
2599 | for (symp = symbol_rootP; symp; symp = symbol_next (symp)) | |
0baf16f2 | 2600 | { |
7e8d4ab4 AM |
2601 | const char *name; |
2602 | char *dotname; | |
2603 | symbolS *dotsym; | |
7e8d4ab4 AM |
2604 | |
2605 | name = S_GET_NAME (symp); | |
2606 | if (name[0] == '.') | |
2607 | continue; | |
2608 | ||
2609 | if (! S_IS_WEAK (symp) | |
2610 | || S_IS_DEFINED (symp)) | |
2611 | continue; | |
2612 | ||
a44e2901 | 2613 | dotname = concat (".", name, (char *) NULL); |
461b725f | 2614 | dotsym = symbol_find_noref (dotname, 1); |
7e8d4ab4 AM |
2615 | free (dotname); |
2616 | if (dotsym != NULL && (symbol_used_p (dotsym) | |
2617 | || symbol_used_in_reloc_p (dotsym))) | |
670ec21d NC |
2618 | symbol_mark_used (symp); |
2619 | ||
0baf16f2 AM |
2620 | } |
2621 | ||
9232bbb0 AM |
2622 | toc = bfd_get_section_by_name (stdoutput, ".toc"); |
2623 | if (toc != NULL | |
01efc3af | 2624 | && toc_reloc_types != has_large_toc_reloc |
fd361982 | 2625 | && bfd_section_size (toc) > 0x10000) |
9232bbb0 | 2626 | as_warn (_("TOC section size exceeds 64k")); |
a38a07e0 AM |
2627 | } |
2628 | ||
2629 | /* .TOC. used in an opd entry as .TOC.@tocbase doesn't need to be | |
2630 | emitted. Other uses of .TOC. will cause the symbol to be marked | |
2631 | with BSF_KEEP in md_apply_fix. */ | |
9232bbb0 | 2632 | |
a38a07e0 AM |
2633 | void |
2634 | ppc_elf_adjust_symtab (void) | |
2635 | { | |
2636 | if (ppc_obj64) | |
2637 | { | |
2638 | symbolS *symp; | |
2639 | symp = symbol_find (".TOC."); | |
2640 | if (symp != NULL) | |
2641 | { | |
2642 | asymbol *bsym = symbol_get_bfdsym (symp); | |
2643 | if ((bsym->flags & BSF_KEEP) == 0) | |
2644 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
a38a07e0 AM |
2645 | } |
2646 | } | |
0baf16f2 | 2647 | } |
252b5132 RH |
2648 | #endif /* OBJ_ELF */ |
2649 | \f | |
3e60bf4d | 2650 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
3b8b57a9 AM |
2651 | /* See whether a symbol is in the TOC section. */ |
2652 | ||
2653 | static int | |
2654 | ppc_is_toc_sym (symbolS *sym) | |
2655 | { | |
3e60bf4d | 2656 | #ifdef OBJ_XCOFF |
9f6e76f4 TG |
2657 | return (symbol_get_tc (sym)->symbol_class == XMC_TC |
2658 | || symbol_get_tc (sym)->symbol_class == XMC_TC0); | |
f50c47f1 | 2659 | #endif |
3e60bf4d AM |
2660 | #ifdef OBJ_ELF |
2661 | const char *sname = segment_name (S_GET_SEGMENT (sym)); | |
2662 | if (ppc_obj64) | |
2663 | return strcmp (sname, ".toc") == 0; | |
2664 | else | |
2665 | return strcmp (sname, ".got") == 0; | |
2666 | #endif | |
2667 | } | |
2668 | #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */ | |
252b5132 RH |
2669 | \f |
2670 | ||
dc1d03fc | 2671 | #ifdef OBJ_ELF |
6a0c61b7 EZ |
2672 | #define APUID(a,v) ((((a) & 0xffff) << 16) | ((v) & 0xffff)) |
2673 | static void | |
98027b10 | 2674 | ppc_apuinfo_section_add (unsigned int apu, unsigned int version) |
6a0c61b7 EZ |
2675 | { |
2676 | unsigned int i; | |
2677 | ||
2678 | /* Check we don't already exist. */ | |
2679 | for (i = 0; i < ppc_apuinfo_num; i++) | |
dc1d03fc | 2680 | if (ppc_apuinfo_list[i] == APUID (apu, version)) |
6a0c61b7 | 2681 | return; |
b34976b6 | 2682 | |
6a0c61b7 EZ |
2683 | if (ppc_apuinfo_num == ppc_apuinfo_num_alloc) |
2684 | { | |
2685 | if (ppc_apuinfo_num_alloc == 0) | |
2686 | { | |
2687 | ppc_apuinfo_num_alloc = 4; | |
325801bd | 2688 | ppc_apuinfo_list = XNEWVEC (unsigned long, ppc_apuinfo_num_alloc); |
6a0c61b7 EZ |
2689 | } |
2690 | else | |
2691 | { | |
2692 | ppc_apuinfo_num_alloc += 4; | |
325801bd TS |
2693 | ppc_apuinfo_list = XRESIZEVEC (unsigned long, ppc_apuinfo_list, |
2694 | ppc_apuinfo_num_alloc); | |
6a0c61b7 EZ |
2695 | } |
2696 | } | |
dc1d03fc | 2697 | ppc_apuinfo_list[ppc_apuinfo_num++] = APUID (apu, version); |
6a0c61b7 EZ |
2698 | } |
2699 | #undef APUID | |
dc1d03fc | 2700 | #endif |
6a0c61b7 | 2701 | \f |
dd7efa79 PB |
2702 | /* Various frobbings of labels and their addresses. */ |
2703 | ||
2704 | /* Symbols labelling the current insn. */ | |
2705 | struct insn_label_list | |
2706 | { | |
2707 | struct insn_label_list *next; | |
2708 | symbolS *label; | |
2709 | }; | |
2710 | ||
2711 | static struct insn_label_list *insn_labels; | |
2712 | static struct insn_label_list *free_insn_labels; | |
2713 | ||
2714 | static void | |
2715 | ppc_record_label (symbolS *sym) | |
2716 | { | |
2717 | struct insn_label_list *l; | |
2718 | ||
2719 | if (free_insn_labels == NULL) | |
2720 | l = XNEW (struct insn_label_list); | |
2721 | else | |
2722 | { | |
2723 | l = free_insn_labels; | |
2724 | free_insn_labels = l->next; | |
2725 | } | |
2726 | ||
2727 | l->label = sym; | |
2728 | l->next = insn_labels; | |
2729 | insn_labels = l; | |
2730 | } | |
2731 | ||
2732 | static void | |
2733 | ppc_clear_labels (void) | |
2734 | { | |
2735 | while (insn_labels != NULL) | |
2736 | { | |
2737 | struct insn_label_list *l = insn_labels; | |
2738 | insn_labels = l->next; | |
2739 | l->next = free_insn_labels; | |
2740 | free_insn_labels = l; | |
2741 | } | |
2742 | } | |
2743 | ||
2744 | void | |
2745 | ppc_start_line_hook (void) | |
2746 | { | |
2747 | ppc_clear_labels (); | |
2748 | } | |
2749 | ||
2750 | void | |
2751 | ppc_new_dot_label (symbolS *sym) | |
2752 | { | |
2753 | ppc_record_label (sym); | |
2754 | #ifdef OBJ_XCOFF | |
2755 | /* Anchor this label to the current csect for relocations. */ | |
2756 | symbol_get_tc (sym)->within = ppc_current_csect; | |
2757 | #endif | |
2758 | } | |
2759 | ||
2760 | void | |
2761 | ppc_frob_label (symbolS *sym) | |
2762 | { | |
2763 | ppc_record_label (sym); | |
2764 | ||
2765 | #ifdef OBJ_XCOFF | |
2766 | /* Set the class of a label based on where it is defined. This handles | |
2767 | symbols without suffixes. Also, move the symbol so that it follows | |
2768 | the csect symbol. */ | |
2769 | if (ppc_current_csect != (symbolS *) NULL) | |
2770 | { | |
2771 | if (symbol_get_tc (sym)->symbol_class == -1) | |
2772 | symbol_get_tc (sym)->symbol_class = symbol_get_tc (ppc_current_csect)->symbol_class; | |
2773 | ||
2774 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
2775 | symbol_append (sym, symbol_get_tc (ppc_current_csect)->within, | |
2776 | &symbol_rootP, &symbol_lastP); | |
2777 | symbol_get_tc (ppc_current_csect)->within = sym; | |
2778 | symbol_get_tc (sym)->within = ppc_current_csect; | |
2779 | } | |
2780 | #endif | |
2781 | ||
2782 | #ifdef OBJ_ELF | |
2783 | dwarf2_emit_label (sym); | |
2784 | #endif | |
2785 | } | |
6a0c61b7 | 2786 | |
252b5132 RH |
2787 | /* We need to keep a list of fixups. We can't simply generate them as |
2788 | we go, because that would require us to first create the frag, and | |
2789 | that would screw up references to ``.''. */ | |
2790 | ||
2791 | struct ppc_fixup | |
2792 | { | |
2793 | expressionS exp; | |
2794 | int opindex; | |
2795 | bfd_reloc_code_real_type reloc; | |
2796 | }; | |
2797 | ||
2798 | #define MAX_INSN_FIXUPS (5) | |
2799 | ||
0e2779e9 AM |
2800 | /* Return the field size operated on by RELOC, and whether it is |
2801 | pc-relative in PC_RELATIVE. */ | |
2802 | ||
2803 | static unsigned int | |
2804 | fixup_size (bfd_reloc_code_real_type reloc, bfd_boolean *pc_relative) | |
2805 | { | |
2806 | unsigned int size = 0; | |
2807 | bfd_boolean pcrel = FALSE; | |
2808 | ||
2809 | switch (reloc) | |
2810 | { | |
2811 | /* This switch statement must handle all BFD_RELOC values | |
2812 | possible in instruction fixups. As is, it handles all | |
2813 | BFD_RELOC values used in bfd/elf64-ppc.c, bfd/elf32-ppc.c, | |
fe49679d | 2814 | bfd/coff-rs6000.c and bfd/coff64-rs6000.c. |
0e2779e9 AM |
2815 | Overkill since data and marker relocs need not be handled |
2816 | here, but this way we can be sure a needed fixup reloc isn't | |
2817 | accidentally omitted. */ | |
2818 | case BFD_RELOC_PPC_EMB_MRKREF: | |
2819 | case BFD_RELOC_VTABLE_ENTRY: | |
2820 | case BFD_RELOC_VTABLE_INHERIT: | |
2821 | break; | |
2822 | ||
2823 | case BFD_RELOC_8: | |
2824 | size = 1; | |
2825 | break; | |
2826 | ||
2827 | case BFD_RELOC_16: | |
2828 | case BFD_RELOC_16_BASEREL: | |
2829 | case BFD_RELOC_16_GOTOFF: | |
2830 | case BFD_RELOC_GPREL16: | |
2831 | case BFD_RELOC_HI16: | |
2832 | case BFD_RELOC_HI16_BASEREL: | |
2833 | case BFD_RELOC_HI16_GOTOFF: | |
2834 | case BFD_RELOC_HI16_PLTOFF: | |
2835 | case BFD_RELOC_HI16_S: | |
2836 | case BFD_RELOC_HI16_S_BASEREL: | |
2837 | case BFD_RELOC_HI16_S_GOTOFF: | |
2838 | case BFD_RELOC_HI16_S_PLTOFF: | |
2839 | case BFD_RELOC_LO16: | |
2840 | case BFD_RELOC_LO16_BASEREL: | |
2841 | case BFD_RELOC_LO16_GOTOFF: | |
2842 | case BFD_RELOC_LO16_PLTOFF: | |
2843 | case BFD_RELOC_PPC64_ADDR16_DS: | |
2844 | case BFD_RELOC_PPC64_ADDR16_HIGH: | |
2845 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
5663e321 AM |
2846 | case BFD_RELOC_PPC64_ADDR16_HIGHER34: |
2847 | case BFD_RELOC_PPC64_ADDR16_HIGHERA34: | |
2848 | case BFD_RELOC_PPC64_ADDR16_HIGHEST34: | |
2849 | case BFD_RELOC_PPC64_ADDR16_HIGHESTA34: | |
0e2779e9 AM |
2850 | case BFD_RELOC_PPC64_ADDR16_LO_DS: |
2851 | case BFD_RELOC_PPC64_DTPREL16_DS: | |
2852 | case BFD_RELOC_PPC64_DTPREL16_HIGH: | |
2853 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
2854 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: | |
2855 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
2856 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
2857 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
2858 | case BFD_RELOC_PPC64_DTPREL16_LO_DS: | |
2859 | case BFD_RELOC_PPC64_GOT16_DS: | |
2860 | case BFD_RELOC_PPC64_GOT16_LO_DS: | |
2861 | case BFD_RELOC_PPC64_HIGHER: | |
2862 | case BFD_RELOC_PPC64_HIGHER_S: | |
2863 | case BFD_RELOC_PPC64_HIGHEST: | |
2864 | case BFD_RELOC_PPC64_HIGHEST_S: | |
2865 | case BFD_RELOC_PPC64_PLT16_LO_DS: | |
2866 | case BFD_RELOC_PPC64_PLTGOT16: | |
2867 | case BFD_RELOC_PPC64_PLTGOT16_DS: | |
2868 | case BFD_RELOC_PPC64_PLTGOT16_HA: | |
2869 | case BFD_RELOC_PPC64_PLTGOT16_HI: | |
2870 | case BFD_RELOC_PPC64_PLTGOT16_LO: | |
2871 | case BFD_RELOC_PPC64_PLTGOT16_LO_DS: | |
2872 | case BFD_RELOC_PPC64_SECTOFF_DS: | |
2873 | case BFD_RELOC_PPC64_SECTOFF_LO_DS: | |
2874 | case BFD_RELOC_PPC64_TOC16_DS: | |
2875 | case BFD_RELOC_PPC64_TOC16_HA: | |
2876 | case BFD_RELOC_PPC64_TOC16_HI: | |
2877 | case BFD_RELOC_PPC64_TOC16_LO: | |
2878 | case BFD_RELOC_PPC64_TOC16_LO_DS: | |
2879 | case BFD_RELOC_PPC64_TPREL16_DS: | |
2880 | case BFD_RELOC_PPC64_TPREL16_HIGH: | |
2881 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
2882 | case BFD_RELOC_PPC64_TPREL16_HIGHER: | |
2883 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
2884 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
2885 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
2886 | case BFD_RELOC_PPC64_TPREL16_LO_DS: | |
2887 | #ifdef OBJ_XCOFF | |
2888 | case BFD_RELOC_PPC_BA16: | |
2889 | #endif | |
2890 | case BFD_RELOC_PPC_DTPREL16: | |
2891 | case BFD_RELOC_PPC_DTPREL16_HA: | |
2892 | case BFD_RELOC_PPC_DTPREL16_HI: | |
2893 | case BFD_RELOC_PPC_DTPREL16_LO: | |
2894 | case BFD_RELOC_PPC_EMB_NADDR16: | |
2895 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
2896 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
2897 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
2898 | case BFD_RELOC_PPC_EMB_RELSDA: | |
2899 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
2900 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
2901 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
2902 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
2903 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
2904 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
2905 | case BFD_RELOC_PPC_EMB_SDAI16: | |
2906 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
2907 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
2908 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
2909 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
2910 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
2911 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
2912 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
2913 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
2914 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
2915 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
2916 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
2917 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
2918 | case BFD_RELOC_PPC_GOT_TPREL16: | |
2919 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
2920 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
2921 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
2922 | case BFD_RELOC_PPC_TOC16: | |
2923 | case BFD_RELOC_PPC_TPREL16: | |
2924 | case BFD_RELOC_PPC_TPREL16_HA: | |
2925 | case BFD_RELOC_PPC_TPREL16_HI: | |
2926 | case BFD_RELOC_PPC_TPREL16_LO: | |
2927 | size = 2; | |
2928 | break; | |
2929 | ||
2930 | case BFD_RELOC_16_PCREL: | |
2931 | case BFD_RELOC_HI16_PCREL: | |
2932 | case BFD_RELOC_HI16_S_PCREL: | |
2933 | case BFD_RELOC_LO16_PCREL: | |
2934 | case BFD_RELOC_PPC64_REL16_HIGH: | |
2935 | case BFD_RELOC_PPC64_REL16_HIGHA: | |
2936 | case BFD_RELOC_PPC64_REL16_HIGHER: | |
5663e321 | 2937 | case BFD_RELOC_PPC64_REL16_HIGHER34: |
0e2779e9 | 2938 | case BFD_RELOC_PPC64_REL16_HIGHERA: |
5663e321 | 2939 | case BFD_RELOC_PPC64_REL16_HIGHERA34: |
0e2779e9 | 2940 | case BFD_RELOC_PPC64_REL16_HIGHEST: |
5663e321 | 2941 | case BFD_RELOC_PPC64_REL16_HIGHEST34: |
0e2779e9 | 2942 | case BFD_RELOC_PPC64_REL16_HIGHESTA: |
5663e321 | 2943 | case BFD_RELOC_PPC64_REL16_HIGHESTA34: |
0e2779e9 AM |
2944 | #ifdef OBJ_XCOFF |
2945 | case BFD_RELOC_PPC_B16: | |
2946 | #endif | |
2947 | case BFD_RELOC_PPC_VLE_REL8: | |
2948 | size = 2; | |
2949 | pcrel = TRUE; | |
2950 | break; | |
2951 | ||
0e2779e9 | 2952 | case BFD_RELOC_32: |
0e2779e9 AM |
2953 | case BFD_RELOC_32_PLTOFF: |
2954 | #ifdef OBJ_XCOFF | |
2955 | case BFD_RELOC_CTOR: | |
2956 | #endif | |
2957 | case BFD_RELOC_PPC64_ENTRY: | |
2958 | case BFD_RELOC_PPC_16DX_HA: | |
2959 | #ifndef OBJ_XCOFF | |
2960 | case BFD_RELOC_PPC_BA16: | |
2961 | #endif | |
2962 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
2963 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
2964 | case BFD_RELOC_PPC_BA26: | |
2965 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
2966 | case BFD_RELOC_PPC_EMB_NADDR32: | |
2967 | case BFD_RELOC_PPC_EMB_SDA21: | |
2968 | case BFD_RELOC_PPC_TLS: | |
2969 | case BFD_RELOC_PPC_TLSGD: | |
2970 | case BFD_RELOC_PPC_TLSLD: | |
2971 | case BFD_RELOC_PPC_VLE_HA16A: | |
2972 | case BFD_RELOC_PPC_VLE_HA16D: | |
2973 | case BFD_RELOC_PPC_VLE_HI16A: | |
2974 | case BFD_RELOC_PPC_VLE_HI16D: | |
2975 | case BFD_RELOC_PPC_VLE_LO16A: | |
2976 | case BFD_RELOC_PPC_VLE_LO16D: | |
2977 | case BFD_RELOC_PPC_VLE_SDA21: | |
2978 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
2979 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
2980 | case BFD_RELOC_PPC_VLE_SDAREL_HA16D: | |
2981 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
2982 | case BFD_RELOC_PPC_VLE_SDAREL_HI16D: | |
2983 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
2984 | case BFD_RELOC_PPC_VLE_SDAREL_LO16D: | |
c213164a | 2985 | case BFD_RELOC_PPC64_TLS_PCREL: |
0e2779e9 AM |
2986 | case BFD_RELOC_RVA: |
2987 | size = 4; | |
2988 | break; | |
2989 | ||
2990 | case BFD_RELOC_24_PLT_PCREL: | |
2991 | case BFD_RELOC_32_PCREL: | |
2992 | case BFD_RELOC_32_PLT_PCREL: | |
2993 | case BFD_RELOC_PPC64_REL24_NOTOC: | |
2994 | #ifndef OBJ_XCOFF | |
2995 | case BFD_RELOC_PPC_B16: | |
2996 | #endif | |
2997 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
2998 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
2999 | case BFD_RELOC_PPC_B26: | |
3000 | case BFD_RELOC_PPC_LOCAL24PC: | |
3001 | case BFD_RELOC_PPC_REL16DX_HA: | |
3002 | case BFD_RELOC_PPC_VLE_REL15: | |
3003 | case BFD_RELOC_PPC_VLE_REL24: | |
3004 | size = 4; | |
3005 | pcrel = TRUE; | |
3006 | break; | |
3007 | ||
3008 | #ifndef OBJ_XCOFF | |
3009 | case BFD_RELOC_CTOR: | |
3010 | #endif | |
3011 | case BFD_RELOC_PPC_COPY: | |
3012 | case BFD_RELOC_PPC_DTPMOD: | |
3013 | case BFD_RELOC_PPC_DTPREL: | |
3014 | case BFD_RELOC_PPC_GLOB_DAT: | |
3015 | case BFD_RELOC_PPC_TPREL: | |
3016 | size = ppc_obj64 ? 8 : 4; | |
3017 | break; | |
3018 | ||
3019 | case BFD_RELOC_64: | |
3020 | case BFD_RELOC_64_PLTOFF: | |
3021 | case BFD_RELOC_PPC64_ADDR64_LOCAL: | |
5663e321 AM |
3022 | case BFD_RELOC_PPC64_D28: |
3023 | case BFD_RELOC_PPC64_D34: | |
3024 | case BFD_RELOC_PPC64_D34_LO: | |
3025 | case BFD_RELOC_PPC64_D34_HI30: | |
3026 | case BFD_RELOC_PPC64_D34_HA30: | |
c213164a AM |
3027 | case BFD_RELOC_PPC64_TPREL34: |
3028 | case BFD_RELOC_PPC64_DTPREL34: | |
0e2779e9 AM |
3029 | case BFD_RELOC_PPC64_TOC: |
3030 | size = 8; | |
3031 | break; | |
3032 | ||
3033 | case BFD_RELOC_64_PCREL: | |
3034 | case BFD_RELOC_64_PLT_PCREL: | |
5663e321 | 3035 | case BFD_RELOC_PPC64_GOT_PCREL34: |
87c69f97 AM |
3036 | case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34: |
3037 | case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34: | |
3038 | case BFD_RELOC_PPC64_GOT_TPREL_PCREL34: | |
3039 | case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34: | |
5663e321 AM |
3040 | case BFD_RELOC_PPC64_PCREL28: |
3041 | case BFD_RELOC_PPC64_PCREL34: | |
3042 | case BFD_RELOC_PPC64_PLT_PCREL34: | |
0e2779e9 AM |
3043 | size = 8; |
3044 | pcrel = TRUE; | |
3045 | break; | |
3046 | ||
3047 | default: | |
3048 | abort (); | |
3049 | } | |
3050 | ||
3051 | if (ENABLE_CHECKING) | |
3052 | { | |
3053 | reloc_howto_type *reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc); | |
3054 | if (reloc_howto != NULL | |
3055 | && (size != bfd_get_reloc_size (reloc_howto) | |
3056 | || pcrel != reloc_howto->pc_relative)) | |
3057 | { | |
3058 | as_bad (_("%s howto doesn't match size/pcrel in gas"), | |
3059 | reloc_howto->name); | |
3060 | abort (); | |
3061 | } | |
3062 | } | |
3063 | *pc_relative = pcrel; | |
3064 | return size; | |
3065 | } | |
3066 | ||
a894d76a | 3067 | #ifdef OBJ_ELF |
160eba93 AM |
3068 | /* If we have parsed a call to __tls_get_addr, parse an argument like |
3069 | (gd0@tlsgd). *STR is the leading parenthesis on entry. If an arg | |
3070 | is successfully parsed, *STR is updated past the trailing | |
3071 | parenthesis and trailing white space, and *TLS_FIX contains the | |
3072 | reloc and arg expression. */ | |
3073 | ||
3074 | static int | |
3075 | parse_tls_arg (char **str, const expressionS *exp, struct ppc_fixup *tls_fix) | |
3076 | { | |
3077 | const char *sym_name = S_GET_NAME (exp->X_add_symbol); | |
3078 | if (sym_name[0] == '.') | |
3079 | ++sym_name; | |
3080 | ||
3081 | tls_fix->reloc = BFD_RELOC_NONE; | |
9e7028aa AM |
3082 | if (strncasecmp (sym_name, "__tls_get_addr", 14) == 0 |
3083 | && (sym_name[14] == 0 | |
3084 | || strcasecmp (sym_name + 14, "_desc") == 0 | |
3085 | || strcasecmp (sym_name + 14, "_opt") == 0)) | |
160eba93 AM |
3086 | { |
3087 | char *hold = input_line_pointer; | |
3088 | input_line_pointer = *str + 1; | |
3089 | expression (&tls_fix->exp); | |
3090 | if (tls_fix->exp.X_op == O_symbol) | |
3091 | { | |
3092 | if (strncasecmp (input_line_pointer, "@tlsgd)", 7) == 0) | |
3093 | tls_fix->reloc = BFD_RELOC_PPC_TLSGD; | |
3094 | else if (strncasecmp (input_line_pointer, "@tlsld)", 7) == 0) | |
3095 | tls_fix->reloc = BFD_RELOC_PPC_TLSLD; | |
3096 | if (tls_fix->reloc != BFD_RELOC_NONE) | |
3097 | { | |
3098 | input_line_pointer += 7; | |
3099 | SKIP_WHITESPACE (); | |
3100 | *str = input_line_pointer; | |
3101 | } | |
3102 | } | |
3103 | input_line_pointer = hold; | |
3104 | } | |
3105 | return tls_fix->reloc != BFD_RELOC_NONE; | |
3106 | } | |
a894d76a | 3107 | #endif |
160eba93 | 3108 | |
252b5132 RH |
3109 | /* This routine is called for each instruction to be assembled. */ |
3110 | ||
3111 | void | |
98027b10 | 3112 | md_assemble (char *str) |
252b5132 RH |
3113 | { |
3114 | char *s; | |
3115 | const struct powerpc_opcode *opcode; | |
0f873fd5 | 3116 | uint64_t insn; |
252b5132 | 3117 | const unsigned char *opindex_ptr; |
252b5132 RH |
3118 | int need_paren; |
3119 | int next_opindex; | |
3120 | struct ppc_fixup fixups[MAX_INSN_FIXUPS]; | |
3121 | int fc; | |
3122 | char *f; | |
a9479dc0 | 3123 | int addr_mask; |
252b5132 | 3124 | int i; |
b9c361e0 | 3125 | unsigned int insn_length; |
252b5132 RH |
3126 | |
3127 | /* Get the opcode. */ | |
3882b010 | 3128 | for (s = str; *s != '\0' && ! ISSPACE (*s); s++) |
252b5132 RH |
3129 | ; |
3130 | if (*s != '\0') | |
3131 | *s++ = '\0'; | |
3132 | ||
3133 | /* Look up the opcode in the hash table. */ | |
629310ab | 3134 | opcode = (const struct powerpc_opcode *) str_hash_find (ppc_hash, str); |
252b5132 RH |
3135 | if (opcode == (const struct powerpc_opcode *) NULL) |
3136 | { | |
3137 | const struct powerpc_macro *macro; | |
3138 | ||
fe0e921f AM |
3139 | macro = (const struct powerpc_macro *) str_hash_find (ppc_macro_hash, |
3140 | str); | |
252b5132 | 3141 | if (macro == (const struct powerpc_macro *) NULL) |
d6ed37ed | 3142 | as_bad (_("unrecognized opcode: `%s'"), str); |
252b5132 RH |
3143 | else |
3144 | ppc_macro (s, macro); | |
3145 | ||
dd7efa79 | 3146 | ppc_clear_labels (); |
252b5132 RH |
3147 | return; |
3148 | } | |
3149 | ||
3150 | insn = opcode->opcode; | |
86c0f617 AM |
3151 | if (!target_big_endian |
3152 | && ((insn & ~(1 << 26)) == 46u << 26 | |
3153 | || (insn & ~(0xc0 << 1)) == (31u << 26 | 533 << 1))) | |
3154 | { | |
3155 | /* lmw, stmw, lswi, lswx, stswi, stswx */ | |
3156 | as_bad (_("`%s' invalid when little-endian"), str); | |
3157 | ppc_clear_labels (); | |
3158 | return; | |
3159 | } | |
252b5132 RH |
3160 | |
3161 | str = s; | |
3882b010 | 3162 | while (ISSPACE (*str)) |
252b5132 RH |
3163 | ++str; |
3164 | ||
3165 | /* PowerPC operands are just expressions. The only real issue is | |
9cf7e568 AM |
3166 | that a few operand types are optional. If an instruction has |
3167 | multiple optional operands and one is omitted, then all optional | |
3168 | operands past the first omitted one must also be omitted. */ | |
3169 | int num_optional_operands = 0; | |
3170 | int num_optional_provided = 0; | |
252b5132 RH |
3171 | |
3172 | /* Gather the operands. */ | |
3173 | need_paren = 0; | |
3174 | next_opindex = 0; | |
3175 | fc = 0; | |
3176 | for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++) | |
3177 | { | |
3178 | const struct powerpc_operand *operand; | |
3179 | const char *errmsg; | |
3180 | char *hold; | |
3181 | expressionS ex; | |
3182 | char endc; | |
3183 | ||
3184 | if (next_opindex == 0) | |
3185 | operand = &powerpc_operands[*opindex_ptr]; | |
3186 | else | |
3187 | { | |
3188 | operand = &powerpc_operands[next_opindex]; | |
3189 | next_opindex = 0; | |
3190 | } | |
252b5132 RH |
3191 | errmsg = NULL; |
3192 | ||
252b5132 | 3193 | /* If this is an optional operand, and we are skipping it, just |
9cf7e568 | 3194 | insert the default value, usually a zero. */ |
252b5132 | 3195 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 |
9cf7e568 | 3196 | && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64)) |
252b5132 | 3197 | { |
9cf7e568 AM |
3198 | if (num_optional_operands == 0) |
3199 | { | |
3200 | const unsigned char *optr; | |
3201 | int total = 0; | |
3202 | int provided = 0; | |
3203 | int omitted; | |
3204 | ||
3205 | s = str; | |
3206 | for (optr = opindex_ptr; *optr != 0; optr++) | |
3207 | { | |
3208 | const struct powerpc_operand *op; | |
3209 | op = &powerpc_operands[*optr]; | |
3210 | ||
3211 | ++total; | |
3212 | ||
3213 | if ((op->flags & PPC_OPERAND_OPTIONAL) != 0 | |
3214 | && !((op->flags & PPC_OPERAND_OPTIONAL32) != 0 | |
3215 | && ppc_obj64)) | |
3216 | ++num_optional_operands; | |
3217 | ||
3218 | if (s != NULL && *s != '\0') | |
3219 | { | |
3220 | ++provided; | |
3221 | ||
3222 | /* Look for the start of the next operand. */ | |
3223 | if ((op->flags & PPC_OPERAND_PARENS) != 0) | |
3224 | s = strpbrk (s, "(,"); | |
3225 | else | |
3226 | s = strchr (s, ','); | |
3227 | ||
3228 | if (s != NULL) | |
3229 | ++s; | |
3230 | } | |
3231 | } | |
3232 | omitted = total - provided; | |
3233 | num_optional_provided = num_optional_operands - omitted; | |
3234 | } | |
3235 | if (--num_optional_provided < 0) | |
252b5132 | 3236 | { |
9cf7e568 AM |
3237 | int64_t val = ppc_optional_operand_value (operand, insn, ppc_cpu, |
3238 | num_optional_provided); | |
3239 | if (operand->insert) | |
3240 | { | |
3241 | insn = (*operand->insert) (insn, val, ppc_cpu, &errmsg); | |
3242 | if (errmsg != (const char *) NULL) | |
3243 | as_bad ("%s", errmsg); | |
3244 | } | |
3245 | else if (operand->shift >= 0) | |
3246 | insn |= (val & operand->bitm) << operand->shift; | |
3247 | else | |
3248 | insn |= (val & operand->bitm) >> -operand->shift; | |
3249 | ||
3250 | if ((operand->flags & PPC_OPERAND_NEXT) != 0) | |
3251 | next_opindex = *opindex_ptr + 1; | |
3252 | continue; | |
252b5132 | 3253 | } |
252b5132 RH |
3254 | } |
3255 | ||
3256 | /* Gather the operand. */ | |
3257 | hold = input_line_pointer; | |
3258 | input_line_pointer = str; | |
3259 | ||
fe49679d AM |
3260 | if ((reg_names_p |
3261 | && (((operand->flags & PPC_OPERAND_CR_BIT) != 0) | |
3262 | || ((operand->flags & PPC_OPERAND_CR_REG) != 0))) | |
3263 | || !register_name (&ex)) | |
252b5132 | 3264 | { |
fe49679d | 3265 | char save_lex = lex_type['%']; |
252b5132 | 3266 | |
fe49679d AM |
3267 | if (((operand->flags & PPC_OPERAND_CR_REG) != 0) |
3268 | || (operand->flags & PPC_OPERAND_CR_BIT) != 0) | |
252b5132 | 3269 | { |
fe49679d AM |
3270 | cr_operand = TRUE; |
3271 | lex_type['%'] |= LEX_BEGIN_NAME; | |
252b5132 | 3272 | } |
fe49679d AM |
3273 | expression (&ex); |
3274 | cr_operand = FALSE; | |
3275 | lex_type['%'] = save_lex; | |
252b5132 RH |
3276 | } |
3277 | ||
3278 | str = input_line_pointer; | |
3279 | input_line_pointer = hold; | |
3280 | ||
3281 | if (ex.X_op == O_illegal) | |
3282 | as_bad (_("illegal operand")); | |
3283 | else if (ex.X_op == O_absent) | |
3284 | as_bad (_("missing operand")); | |
3285 | else if (ex.X_op == O_register) | |
3286 | { | |
7e0de605 AM |
3287 | if ((ex.X_md |
3288 | & ~operand->flags | |
3289 | & (PPC_OPERAND_GPR | PPC_OPERAND_FPR | PPC_OPERAND_VR | |
3290 | | PPC_OPERAND_VSR | PPC_OPERAND_CR_BIT | PPC_OPERAND_CR_REG | |
aa3c112f | 3291 | | PPC_OPERAND_SPR | PPC_OPERAND_GQR | PPC_OPERAND_ACC)) != 0 |
7e0de605 AM |
3292 | && !((ex.X_md & PPC_OPERAND_GPR) != 0 |
3293 | && ex.X_add_number != 0 | |
3294 | && (operand->flags & PPC_OPERAND_GPR_0) != 0)) | |
ece5dcc1 | 3295 | as_warn (_("invalid register expression")); |
4b1c0f7e | 3296 | insn = ppc_insert_operand (insn, operand, ex.X_add_number, |
783de163 | 3297 | ppc_cpu, (char *) NULL, 0); |
252b5132 RH |
3298 | } |
3299 | else if (ex.X_op == O_constant) | |
3300 | { | |
3301 | #ifdef OBJ_ELF | |
81d4177b | 3302 | /* Allow @HA, @L, @H on constants. */ |
3b8b57a9 | 3303 | bfd_reloc_code_real_type reloc; |
252b5132 RH |
3304 | char *orig_str = str; |
3305 | ||
62ebcb5c | 3306 | if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_NONE) |
252b5132 RH |
3307 | switch (reloc) |
3308 | { | |
3309 | default: | |
3310 | str = orig_str; | |
3311 | break; | |
3312 | ||
3313 | case BFD_RELOC_LO16: | |
f9c6b907 AM |
3314 | ex.X_add_number &= 0xffff; |
3315 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
0baf16f2 | 3316 | ex.X_add_number = SEX16 (ex.X_add_number); |
252b5132 RH |
3317 | break; |
3318 | ||
3319 | case BFD_RELOC_HI16: | |
f9c6b907 AM |
3320 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
3321 | { | |
3322 | /* PowerPC64 @h is tested for overflow. */ | |
3323 | ex.X_add_number = (addressT) ex.X_add_number >> 16; | |
3324 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3325 | { | |
3326 | addressT sign = (((addressT) -1 >> 16) + 1) >> 1; | |
3327 | ex.X_add_number | |
3328 | = ((addressT) ex.X_add_number ^ sign) - sign; | |
3329 | } | |
3330 | break; | |
3331 | } | |
2b0f3761 | 3332 | /* Fallthru */ |
f9c6b907 AM |
3333 | |
3334 | case BFD_RELOC_PPC64_ADDR16_HIGH: | |
3335 | ex.X_add_number = PPC_HI (ex.X_add_number); | |
3336 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3337 | ex.X_add_number = SEX16 (ex.X_add_number); | |
252b5132 RH |
3338 | break; |
3339 | ||
3340 | case BFD_RELOC_HI16_S: | |
f9c6b907 AM |
3341 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
3342 | { | |
3343 | /* PowerPC64 @ha is tested for overflow. */ | |
3344 | ex.X_add_number | |
3345 | = ((addressT) ex.X_add_number + 0x8000) >> 16; | |
3346 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3347 | { | |
3348 | addressT sign = (((addressT) -1 >> 16) + 1) >> 1; | |
3349 | ex.X_add_number | |
3350 | = ((addressT) ex.X_add_number ^ sign) - sign; | |
3351 | } | |
3352 | break; | |
3353 | } | |
2b0f3761 | 3354 | /* Fallthru */ |
f9c6b907 AM |
3355 | |
3356 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
3357 | ex.X_add_number = PPC_HA (ex.X_add_number); | |
3358 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3359 | ex.X_add_number = SEX16 (ex.X_add_number); | |
0baf16f2 AM |
3360 | break; |
3361 | ||
0baf16f2 | 3362 | case BFD_RELOC_PPC64_HIGHER: |
f9c6b907 AM |
3363 | ex.X_add_number = PPC_HIGHER (ex.X_add_number); |
3364 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3365 | ex.X_add_number = SEX16 (ex.X_add_number); | |
0baf16f2 AM |
3366 | break; |
3367 | ||
3368 | case BFD_RELOC_PPC64_HIGHER_S: | |
f9c6b907 AM |
3369 | ex.X_add_number = PPC_HIGHERA (ex.X_add_number); |
3370 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3371 | ex.X_add_number = SEX16 (ex.X_add_number); | |
252b5132 | 3372 | break; |
0baf16f2 AM |
3373 | |
3374 | case BFD_RELOC_PPC64_HIGHEST: | |
f9c6b907 AM |
3375 | ex.X_add_number = PPC_HIGHEST (ex.X_add_number); |
3376 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3377 | ex.X_add_number = SEX16 (ex.X_add_number); | |
0baf16f2 AM |
3378 | break; |
3379 | ||
3380 | case BFD_RELOC_PPC64_HIGHEST_S: | |
f9c6b907 AM |
3381 | ex.X_add_number = PPC_HIGHESTA (ex.X_add_number); |
3382 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3383 | ex.X_add_number = SEX16 (ex.X_add_number); | |
0baf16f2 | 3384 | break; |
252b5132 | 3385 | } |
0baf16f2 | 3386 | #endif /* OBJ_ELF */ |
252b5132 | 3387 | insn = ppc_insert_operand (insn, operand, ex.X_add_number, |
783de163 | 3388 | ppc_cpu, (char *) NULL, 0); |
252b5132 | 3389 | } |
727fc41e | 3390 | else |
252b5132 | 3391 | { |
62ebcb5c | 3392 | bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; |
3b8b57a9 | 3393 | #ifdef OBJ_ELF |
160eba93 AM |
3394 | /* Look for a __tls_get_addr arg using the insane old syntax. */ |
3395 | if (ex.X_op == O_symbol && *str == '(' && fc < MAX_INSN_FIXUPS | |
3396 | && parse_tls_arg (&str, &ex, &fixups[fc])) | |
cdba85ec | 3397 | { |
160eba93 AM |
3398 | fixups[fc].opindex = *opindex_ptr; |
3399 | ++fc; | |
252b5132 RH |
3400 | } |
3401 | ||
62ebcb5c | 3402 | if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_NONE) |
0baf16f2 | 3403 | { |
b9c361e0 JL |
3404 | /* If VLE-mode convert LO/HI/HA relocations. */ |
3405 | if (opcode->flags & PPC_OPCODE_VLE) | |
3406 | { | |
0f873fd5 | 3407 | uint64_t tmp_insn = insn & opcode->mask; |
3739860c | 3408 | |
08dc996f | 3409 | int use_a_reloc = (tmp_insn == E_OR2I_INSN |
b9c361e0 JL |
3410 | || tmp_insn == E_AND2I_DOT_INSN |
3411 | || tmp_insn == E_OR2IS_INSN | |
bb6bf75e | 3412 | || tmp_insn == E_LI_INSN |
b9c361e0 JL |
3413 | || tmp_insn == E_LIS_INSN |
3414 | || tmp_insn == E_AND2IS_DOT_INSN); | |
3415 | ||
3416 | ||
08dc996f | 3417 | int use_d_reloc = (tmp_insn == E_ADD2I_DOT_INSN |
b9c361e0 JL |
3418 | || tmp_insn == E_ADD2IS_INSN |
3419 | || tmp_insn == E_CMP16I_INSN | |
3420 | || tmp_insn == E_MULL2I_INSN | |
3421 | || tmp_insn == E_CMPL16I_INSN | |
3422 | || tmp_insn == E_CMPH16I_INSN | |
3423 | || tmp_insn == E_CMPHL16I_INSN); | |
3424 | ||
3425 | switch (reloc) | |
3426 | { | |
3427 | default: | |
3428 | break; | |
3429 | ||
3430 | case BFD_RELOC_PPC_EMB_SDA21: | |
3431 | reloc = BFD_RELOC_PPC_VLE_SDA21; | |
3432 | break; | |
3433 | ||
3434 | case BFD_RELOC_LO16: | |
3435 | if (use_d_reloc) | |
3436 | reloc = BFD_RELOC_PPC_VLE_LO16D; | |
3437 | else if (use_a_reloc) | |
3438 | reloc = BFD_RELOC_PPC_VLE_LO16A; | |
3439 | break; | |
3440 | ||
3441 | case BFD_RELOC_HI16: | |
3442 | if (use_d_reloc) | |
3443 | reloc = BFD_RELOC_PPC_VLE_HI16D; | |
3444 | else if (use_a_reloc) | |
3445 | reloc = BFD_RELOC_PPC_VLE_HI16A; | |
3446 | break; | |
3739860c | 3447 | |
b9c361e0 JL |
3448 | case BFD_RELOC_HI16_S: |
3449 | if (use_d_reloc) | |
3450 | reloc = BFD_RELOC_PPC_VLE_HA16D; | |
3451 | else if (use_a_reloc) | |
3452 | reloc = BFD_RELOC_PPC_VLE_HA16A; | |
3453 | break; | |
3454 | ||
3455 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
3456 | if (use_d_reloc) | |
3457 | reloc = BFD_RELOC_PPC_VLE_SDAREL_LO16D; | |
3458 | break; | |
3459 | ||
3460 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
3461 | if (use_d_reloc) | |
3462 | reloc = BFD_RELOC_PPC_VLE_SDAREL_HI16D; | |
3463 | break; | |
3464 | ||
3465 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
3466 | if (use_d_reloc) | |
3467 | reloc = BFD_RELOC_PPC_VLE_SDAREL_HA16D; | |
3468 | break; | |
3469 | } | |
3470 | } | |
bb6bf75e AM |
3471 | |
3472 | /* TLS and other tweaks. */ | |
3473 | switch (reloc) | |
3474 | { | |
3475 | default: | |
3476 | break; | |
3477 | ||
3478 | case BFD_RELOC_PPC_TLS: | |
c213164a | 3479 | case BFD_RELOC_PPC64_TLS_PCREL: |
bb6bf75e AM |
3480 | if (!_bfd_elf_ppc_at_tls_transform (opcode->opcode, 0)) |
3481 | as_bad (_("@tls may not be used with \"%s\" operands"), | |
3482 | opcode->name); | |
3483 | else if (operand->shift != 11) | |
3484 | as_bad (_("@tls may only be used in last operand")); | |
3485 | else | |
3486 | insn = ppc_insert_operand (insn, operand, | |
3487 | ppc_obj64 ? 13 : 2, | |
3488 | ppc_cpu, (char *) NULL, 0); | |
3489 | break; | |
3490 | ||
3491 | /* We'll only use the 32 (or 64) bit form of these relocations | |
c213164a | 3492 | in constants. Instructions get the 16 or 34 bit form. */ |
bb6bf75e | 3493 | case BFD_RELOC_PPC_DTPREL: |
c213164a AM |
3494 | if (operand->bitm == 0x3ffffffffULL) |
3495 | reloc = BFD_RELOC_PPC64_DTPREL34; | |
3496 | else | |
3497 | reloc = BFD_RELOC_PPC_DTPREL16; | |
bb6bf75e AM |
3498 | break; |
3499 | ||
3500 | case BFD_RELOC_PPC_TPREL: | |
c213164a AM |
3501 | if (operand->bitm == 0x3ffffffffULL) |
3502 | reloc = BFD_RELOC_PPC64_TPREL34; | |
3503 | else | |
3504 | reloc = BFD_RELOC_PPC_TPREL16; | |
bb6bf75e AM |
3505 | break; |
3506 | ||
5663e321 AM |
3507 | case BFD_RELOC_PPC64_PCREL34: |
3508 | if (operand->bitm == 0xfffffffULL) | |
3509 | { | |
3510 | reloc = BFD_RELOC_PPC64_PCREL28; | |
3511 | break; | |
3512 | } | |
3513 | /* Fall through. */ | |
3514 | case BFD_RELOC_PPC64_GOT_PCREL34: | |
3515 | case BFD_RELOC_PPC64_PLT_PCREL34: | |
87c69f97 AM |
3516 | case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34: |
3517 | case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34: | |
3518 | case BFD_RELOC_PPC64_GOT_TPREL_PCREL34: | |
3519 | case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34: | |
5663e321 | 3520 | if (operand->bitm != 0x3ffffffffULL |
bb6bf75e | 3521 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) |
5663e321 AM |
3522 | as_warn (_("%s unsupported on this instruction"), "@pcrel"); |
3523 | break; | |
3524 | ||
3525 | case BFD_RELOC_LO16: | |
3526 | if (operand->bitm == 0x3ffffffffULL | |
3527 | && (operand->flags & PPC_OPERAND_NEGATIVE) == 0) | |
3528 | reloc = BFD_RELOC_PPC64_D34_LO; | |
3529 | else if ((operand->bitm | 0xf) != 0xffff | |
3530 | || operand->shift != 0 | |
3531 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
bb6bf75e AM |
3532 | as_warn (_("%s unsupported on this instruction"), "@l"); |
3533 | break; | |
3534 | ||
3535 | case BFD_RELOC_HI16: | |
5663e321 AM |
3536 | if (operand->bitm == 0x3ffffffffULL |
3537 | && (operand->flags & PPC_OPERAND_NEGATIVE) == 0) | |
3538 | reloc = BFD_RELOC_PPC64_D34_HI30; | |
3539 | else if (operand->bitm != 0xffff | |
3540 | || operand->shift != 0 | |
3541 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
bb6bf75e AM |
3542 | as_warn (_("%s unsupported on this instruction"), "@h"); |
3543 | break; | |
3544 | ||
3545 | case BFD_RELOC_HI16_S: | |
5663e321 AM |
3546 | if (operand->bitm == 0x3ffffffffULL |
3547 | && (operand->flags & PPC_OPERAND_NEGATIVE) == 0) | |
3548 | reloc = BFD_RELOC_PPC64_D34_HA30; | |
3549 | else if (operand->bitm == 0xffff | |
3550 | && operand->shift == (int) PPC_OPSHIFT_INV | |
3551 | && opcode->opcode == (19 << 26) + (2 << 1)) | |
bb6bf75e AM |
3552 | /* addpcis. */ |
3553 | reloc = BFD_RELOC_PPC_16DX_HA; | |
3554 | else if (operand->bitm != 0xffff | |
3555 | || operand->shift != 0 | |
3556 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
3557 | as_warn (_("%s unsupported on this instruction"), "@ha"); | |
3558 | } | |
0baf16f2 | 3559 | } |
3b8b57a9 AM |
3560 | #endif /* OBJ_ELF */ |
3561 | ||
62ebcb5c | 3562 | if (reloc != BFD_RELOC_NONE) |
3b8b57a9 AM |
3563 | ; |
3564 | /* Determine a BFD reloc value based on the operand information. | |
3565 | We are only prepared to turn a few of the operands into | |
3566 | relocs. */ | |
a0593ad9 AM |
3567 | else if ((operand->flags & (PPC_OPERAND_RELATIVE |
3568 | | PPC_OPERAND_ABSOLUTE)) != 0 | |
3b8b57a9 AM |
3569 | && operand->bitm == 0x3fffffc |
3570 | && operand->shift == 0) | |
3571 | reloc = BFD_RELOC_PPC_B26; | |
a0593ad9 AM |
3572 | else if ((operand->flags & (PPC_OPERAND_RELATIVE |
3573 | | PPC_OPERAND_ABSOLUTE)) != 0 | |
3b8b57a9 AM |
3574 | && operand->bitm == 0xfffc |
3575 | && operand->shift == 0) | |
3576 | reloc = BFD_RELOC_PPC_B16; | |
3577 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3578 | && operand->bitm == 0x1fe | |
3579 | && operand->shift == -1) | |
3580 | reloc = BFD_RELOC_PPC_VLE_REL8; | |
3581 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3582 | && operand->bitm == 0xfffe | |
3583 | && operand->shift == 0) | |
3584 | reloc = BFD_RELOC_PPC_VLE_REL15; | |
3585 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3586 | && operand->bitm == 0x1fffffe | |
3587 | && operand->shift == 0) | |
3588 | reloc = BFD_RELOC_PPC_VLE_REL24; | |
a0593ad9 | 3589 | else if ((operand->flags & PPC_OPERAND_NEGATIVE) == 0 |
3b8b57a9 AM |
3590 | && (operand->bitm & 0xfff0) == 0xfff0 |
3591 | && operand->shift == 0) | |
3592 | { | |
f50c47f1 | 3593 | reloc = BFD_RELOC_16; |
3e60bf4d | 3594 | #if defined OBJ_XCOFF || defined OBJ_ELF |
f50c47f1 | 3595 | /* Note: the symbol may be not yet defined. */ |
a0593ad9 AM |
3596 | if ((operand->flags & PPC_OPERAND_PARENS) != 0 |
3597 | && ppc_is_toc_sym (ex.X_add_symbol)) | |
3e60bf4d AM |
3598 | { |
3599 | reloc = BFD_RELOC_PPC_TOC16; | |
3600 | #ifdef OBJ_ELF | |
3601 | as_warn (_("assuming %s on symbol"), | |
3602 | ppc_obj64 ? "@toc" : "@xgot"); | |
3603 | #endif | |
3604 | } | |
3b8b57a9 | 3605 | #endif |
3b8b57a9 | 3606 | } |
5663e321 AM |
3607 | else if (operand->bitm == 0x3ffffffffULL) |
3608 | reloc = BFD_RELOC_PPC64_D34; | |
3609 | else if (operand->bitm == 0xfffffffULL) | |
3610 | reloc = BFD_RELOC_PPC64_D28; | |
a0593ad9 AM |
3611 | |
3612 | /* For the absolute forms of branches, convert the PC | |
3613 | relative form back into the absolute. */ | |
3614 | if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) | |
3615 | { | |
3616 | switch (reloc) | |
3617 | { | |
3618 | case BFD_RELOC_PPC_B26: | |
3619 | reloc = BFD_RELOC_PPC_BA26; | |
3620 | break; | |
3621 | case BFD_RELOC_PPC_B16: | |
3622 | reloc = BFD_RELOC_PPC_BA16; | |
3623 | break; | |
3624 | #ifdef OBJ_ELF | |
3625 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
3626 | reloc = BFD_RELOC_PPC_BA16_BRTAKEN; | |
3627 | break; | |
3628 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
3629 | reloc = BFD_RELOC_PPC_BA16_BRNTAKEN; | |
3630 | break; | |
3631 | #endif | |
3632 | default: | |
3633 | break; | |
3634 | } | |
3635 | } | |
3636 | ||
3637 | #ifdef OBJ_ELF | |
3638 | switch (reloc) | |
3639 | { | |
3640 | case BFD_RELOC_PPC_TOC16: | |
3641 | toc_reloc_types |= has_small_toc_reloc; | |
3642 | break; | |
3643 | case BFD_RELOC_PPC64_TOC16_LO: | |
3644 | case BFD_RELOC_PPC64_TOC16_HI: | |
3645 | case BFD_RELOC_PPC64_TOC16_HA: | |
3646 | toc_reloc_types |= has_large_toc_reloc; | |
3647 | break; | |
3648 | default: | |
3649 | break; | |
3650 | } | |
3651 | ||
3652 | if (ppc_obj64 | |
3653 | && (operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0) | |
3654 | { | |
3655 | switch (reloc) | |
3656 | { | |
3657 | case BFD_RELOC_16: | |
3658 | reloc = BFD_RELOC_PPC64_ADDR16_DS; | |
3659 | break; | |
5663e321 | 3660 | |
a0593ad9 AM |
3661 | case BFD_RELOC_LO16: |
3662 | reloc = BFD_RELOC_PPC64_ADDR16_LO_DS; | |
3663 | break; | |
5663e321 | 3664 | |
a0593ad9 AM |
3665 | case BFD_RELOC_16_GOTOFF: |
3666 | reloc = BFD_RELOC_PPC64_GOT16_DS; | |
3667 | break; | |
5663e321 | 3668 | |
a0593ad9 AM |
3669 | case BFD_RELOC_LO16_GOTOFF: |
3670 | reloc = BFD_RELOC_PPC64_GOT16_LO_DS; | |
3671 | break; | |
5663e321 | 3672 | |
a0593ad9 AM |
3673 | case BFD_RELOC_LO16_PLTOFF: |
3674 | reloc = BFD_RELOC_PPC64_PLT16_LO_DS; | |
3675 | break; | |
5663e321 | 3676 | |
a0593ad9 AM |
3677 | case BFD_RELOC_16_BASEREL: |
3678 | reloc = BFD_RELOC_PPC64_SECTOFF_DS; | |
3679 | break; | |
5663e321 | 3680 | |
a0593ad9 AM |
3681 | case BFD_RELOC_LO16_BASEREL: |
3682 | reloc = BFD_RELOC_PPC64_SECTOFF_LO_DS; | |
3683 | break; | |
5663e321 | 3684 | |
a0593ad9 AM |
3685 | case BFD_RELOC_PPC_TOC16: |
3686 | reloc = BFD_RELOC_PPC64_TOC16_DS; | |
3687 | break; | |
5663e321 | 3688 | |
a0593ad9 AM |
3689 | case BFD_RELOC_PPC64_TOC16_LO: |
3690 | reloc = BFD_RELOC_PPC64_TOC16_LO_DS; | |
3691 | break; | |
5663e321 | 3692 | |
a0593ad9 AM |
3693 | case BFD_RELOC_PPC64_PLTGOT16: |
3694 | reloc = BFD_RELOC_PPC64_PLTGOT16_DS; | |
3695 | break; | |
5663e321 | 3696 | |
a0593ad9 AM |
3697 | case BFD_RELOC_PPC64_PLTGOT16_LO: |
3698 | reloc = BFD_RELOC_PPC64_PLTGOT16_LO_DS; | |
3699 | break; | |
5663e321 | 3700 | |
a0593ad9 AM |
3701 | case BFD_RELOC_PPC_DTPREL16: |
3702 | reloc = BFD_RELOC_PPC64_DTPREL16_DS; | |
3703 | break; | |
5663e321 | 3704 | |
a0593ad9 AM |
3705 | case BFD_RELOC_PPC_DTPREL16_LO: |
3706 | reloc = BFD_RELOC_PPC64_DTPREL16_LO_DS; | |
3707 | break; | |
5663e321 | 3708 | |
a0593ad9 AM |
3709 | case BFD_RELOC_PPC_TPREL16: |
3710 | reloc = BFD_RELOC_PPC64_TPREL16_DS; | |
3711 | break; | |
5663e321 | 3712 | |
a0593ad9 AM |
3713 | case BFD_RELOC_PPC_TPREL16_LO: |
3714 | reloc = BFD_RELOC_PPC64_TPREL16_LO_DS; | |
3715 | break; | |
5663e321 | 3716 | |
a0593ad9 AM |
3717 | case BFD_RELOC_PPC_GOT_DTPREL16: |
3718 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
3719 | case BFD_RELOC_PPC_GOT_TPREL16: | |
3720 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
3721 | break; | |
5663e321 | 3722 | |
a0593ad9 AM |
3723 | default: |
3724 | as_bad (_("unsupported relocation for DS offset field")); | |
3725 | break; | |
3726 | } | |
3727 | } | |
160eba93 AM |
3728 | |
3729 | /* Look for a __tls_get_addr arg after any __tls_get_addr | |
3730 | modifiers like @plt. This fixup must be emitted before | |
3731 | the usual call fixup. */ | |
3732 | if (ex.X_op == O_symbol && *str == '(' && fc < MAX_INSN_FIXUPS | |
3733 | && parse_tls_arg (&str, &ex, &fixups[fc])) | |
3734 | { | |
3735 | fixups[fc].opindex = *opindex_ptr; | |
3736 | ++fc; | |
3737 | } | |
a0593ad9 | 3738 | #endif |
0baf16f2 | 3739 | |
252b5132 RH |
3740 | /* We need to generate a fixup for this expression. */ |
3741 | if (fc >= MAX_INSN_FIXUPS) | |
3742 | as_fatal (_("too many fixups")); | |
3743 | fixups[fc].exp = ex; | |
727fc41e | 3744 | fixups[fc].opindex = *opindex_ptr; |
252b5132 RH |
3745 | fixups[fc].reloc = reloc; |
3746 | ++fc; | |
3747 | } | |
252b5132 RH |
3748 | |
3749 | if (need_paren) | |
3750 | { | |
3751 | endc = ')'; | |
3752 | need_paren = 0; | |
c3d65c1c BE |
3753 | /* If expecting more operands, then we want to see "),". */ |
3754 | if (*str == endc && opindex_ptr[1] != 0) | |
3755 | { | |
3756 | do | |
3757 | ++str; | |
3758 | while (ISSPACE (*str)); | |
3759 | endc = ','; | |
3760 | } | |
252b5132 RH |
3761 | } |
3762 | else if ((operand->flags & PPC_OPERAND_PARENS) != 0) | |
9cf7e568 | 3763 | endc = '('; |
252b5132 RH |
3764 | else |
3765 | endc = ','; | |
3766 | ||
3767 | /* The call to expression should have advanced str past any | |
3768 | whitespace. */ | |
9cf7e568 | 3769 | if (*str == endc) |
252b5132 | 3770 | { |
9cf7e568 AM |
3771 | ++str; |
3772 | if (endc == '(') | |
3773 | need_paren = 1; | |
3774 | } | |
3775 | else if (*str != '\0') | |
3776 | { | |
3777 | as_bad (_("syntax error; found `%c', expected `%c'"), *str, endc); | |
3778 | break; | |
3779 | } | |
3780 | else if (endc == ')') | |
3781 | { | |
3782 | as_bad (_("syntax error; end of line, expected `%c'"), endc); | |
252b5132 RH |
3783 | break; |
3784 | } | |
252b5132 RH |
3785 | } |
3786 | ||
3882b010 | 3787 | while (ISSPACE (*str)) |
252b5132 RH |
3788 | ++str; |
3789 | ||
3790 | if (*str != '\0') | |
3791 | as_bad (_("junk at end of line: `%s'"), str); | |
3792 | ||
dc1d03fc | 3793 | #ifdef OBJ_ELF |
b9c361e0 | 3794 | /* Do we need/want an APUinfo section? */ |
4faf939a JM |
3795 | if ((ppc_cpu & (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_VLE)) != 0 |
3796 | && !ppc_obj64) | |
6a0c61b7 EZ |
3797 | { |
3798 | /* These are all version "1". */ | |
3799 | if (opcode->flags & PPC_OPCODE_SPE) | |
b34976b6 | 3800 | ppc_apuinfo_section_add (PPC_APUINFO_SPE, 1); |
6a0c61b7 | 3801 | if (opcode->flags & PPC_OPCODE_ISEL) |
b34976b6 | 3802 | ppc_apuinfo_section_add (PPC_APUINFO_ISEL, 1); |
6a0c61b7 | 3803 | if (opcode->flags & PPC_OPCODE_EFS) |
b34976b6 | 3804 | ppc_apuinfo_section_add (PPC_APUINFO_EFS, 1); |
6a0c61b7 | 3805 | if (opcode->flags & PPC_OPCODE_BRLOCK) |
b34976b6 | 3806 | ppc_apuinfo_section_add (PPC_APUINFO_BRLOCK, 1); |
6a0c61b7 | 3807 | if (opcode->flags & PPC_OPCODE_PMR) |
b34976b6 | 3808 | ppc_apuinfo_section_add (PPC_APUINFO_PMR, 1); |
6a0c61b7 | 3809 | if (opcode->flags & PPC_OPCODE_CACHELCK) |
b34976b6 | 3810 | ppc_apuinfo_section_add (PPC_APUINFO_CACHELCK, 1); |
6a0c61b7 | 3811 | if (opcode->flags & PPC_OPCODE_RFMCI) |
b34976b6 | 3812 | ppc_apuinfo_section_add (PPC_APUINFO_RFMCI, 1); |
fbd94057 MR |
3813 | /* Only set the VLE flag if the instruction has been pulled via |
3814 | the VLE instruction set. This way the flag is guaranteed to | |
3815 | be set for VLE-only instructions or for VLE-only processors, | |
3816 | however it'll remain clear for dual-mode instructions on | |
3817 | dual-mode and, more importantly, standard-mode processors. */ | |
3818 | if ((ppc_cpu & opcode->flags) == PPC_OPCODE_VLE) | |
f7d69005 AM |
3819 | { |
3820 | ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1); | |
3821 | if (elf_section_data (now_seg) != NULL) | |
3822 | elf_section_data (now_seg)->this_hdr.sh_flags |= SHF_PPC_VLE; | |
3823 | } | |
6a0c61b7 | 3824 | } |
dc1d03fc | 3825 | #endif |
6a0c61b7 | 3826 | |
252b5132 | 3827 | /* Write out the instruction. */ |
a9479dc0 AM |
3828 | |
3829 | addr_mask = 3; | |
f7d69005 | 3830 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) |
a9479dc0 AM |
3831 | /* All instructions can start on a 2 byte boundary for VLE. */ |
3832 | addr_mask = 1; | |
3833 | ||
3834 | if (frag_now->insn_addr != addr_mask) | |
b9c361e0 | 3835 | { |
a9479dc0 AM |
3836 | /* Don't emit instructions to a frag started for data, or for a |
3837 | CPU differing in VLE mode. Data is allowed to be misaligned, | |
3838 | and it's possible to start a new frag in the middle of | |
3839 | misaligned data. */ | |
3840 | frag_wane (frag_now); | |
3841 | frag_new (0); | |
b9c361e0 | 3842 | } |
a9479dc0 AM |
3843 | |
3844 | /* Check that insns within the frag are aligned. ppc_frag_check | |
3845 | will ensure that the frag start address is aligned. */ | |
3846 | if ((frag_now_fix () & addr_mask) != 0) | |
3847 | as_bad (_("instruction address is not a multiple of %d"), addr_mask + 1); | |
3848 | ||
dd7efa79 | 3849 | /* Differentiate between two, four, and eight byte insns. */ |
a9479dc0 AM |
3850 | insn_length = 4; |
3851 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && PPC_OP_SE_VLE (insn)) | |
3852 | insn_length = 2; | |
7c1f4227 | 3853 | else if ((opcode->flags & PPC_OPCODE_POWER10) != 0 |
dd7efa79 PB |
3854 | && PPC_PREFIX_P (insn)) |
3855 | { | |
3856 | struct insn_label_list *l; | |
3857 | ||
3858 | insn_length = 8; | |
3859 | ||
3860 | /* 8-byte prefix instructions are not allowed to cross 64-byte | |
3861 | boundaries. */ | |
3862 | frag_align_code (6, 4); | |
3863 | record_alignment (now_seg, 6); | |
3864 | ||
3865 | /* Update "dot" in any expressions used by this instruction, and | |
3866 | a label attached to the instruction. By "attached" we mean | |
3867 | on the same source line as the instruction and without any | |
3868 | intervening semicolons. */ | |
3869 | dot_value = frag_now_fix (); | |
3870 | dot_frag = frag_now; | |
3871 | for (l = insn_labels; l != NULL; l = l->next) | |
3872 | { | |
3873 | symbol_set_frag (l->label, dot_frag); | |
3874 | S_SET_VALUE (l->label, dot_value); | |
3875 | } | |
3876 | } | |
3877 | ||
3878 | ppc_clear_labels (); | |
a9479dc0 | 3879 | |
b9c361e0 | 3880 | f = frag_more (insn_length); |
a9479dc0 | 3881 | frag_now->insn_addr = addr_mask; |
dd7efa79 PB |
3882 | |
3883 | /* The prefix part of an 8-byte instruction always occupies the lower | |
3884 | addressed word in a doubleword, regardless of endianness. */ | |
15a32af5 AM |
3885 | if (insn_length == 8 |
3886 | && (sizeof (insn) > sizeof (valueT) || !target_big_endian)) | |
dd7efa79 PB |
3887 | { |
3888 | md_number_to_chars (f, PPC_GET_PREFIX (insn), 4); | |
3889 | md_number_to_chars (f + 4, PPC_GET_SUFFIX (insn), 4); | |
3890 | } | |
3891 | else | |
3892 | md_number_to_chars (f, insn, insn_length); | |
3893 | ||
bf7279d5 AM |
3894 | last_insn = insn; |
3895 | last_seg = now_seg; | |
3896 | last_subseg = now_subseg; | |
252b5132 | 3897 | |
5d6f4f16 | 3898 | #ifdef OBJ_ELF |
b9c361e0 | 3899 | dwarf2_emit_insn (insn_length); |
5d6f4f16 GK |
3900 | #endif |
3901 | ||
3b8b57a9 | 3902 | /* Create any fixups. */ |
252b5132 RH |
3903 | for (i = 0; i < fc; i++) |
3904 | { | |
3b8b57a9 | 3905 | fixS *fixP; |
62ebcb5c | 3906 | if (fixups[i].reloc != BFD_RELOC_NONE) |
252b5132 | 3907 | { |
0e2779e9 AM |
3908 | bfd_boolean pcrel; |
3909 | unsigned int size = fixup_size (fixups[i].reloc, &pcrel); | |
3910 | int offset = target_big_endian ? (insn_length - size) : 0; | |
252b5132 | 3911 | |
99a814a1 AM |
3912 | fixP = fix_new_exp (frag_now, |
3913 | f - frag_now->fr_literal + offset, | |
3914 | size, | |
3915 | &fixups[i].exp, | |
0e2779e9 | 3916 | pcrel, |
252b5132 | 3917 | fixups[i].reloc); |
252b5132 RH |
3918 | } |
3919 | else | |
727fc41e AM |
3920 | { |
3921 | const struct powerpc_operand *operand; | |
3922 | ||
3923 | operand = &powerpc_operands[fixups[i].opindex]; | |
3b8b57a9 AM |
3924 | fixP = fix_new_exp (frag_now, |
3925 | f - frag_now->fr_literal, | |
3926 | insn_length, | |
3927 | &fixups[i].exp, | |
3928 | (operand->flags & PPC_OPERAND_RELATIVE) != 0, | |
62ebcb5c | 3929 | BFD_RELOC_NONE); |
727fc41e | 3930 | } |
3b8b57a9 | 3931 | fixP->fx_pcrel_adjust = fixups[i].opindex; |
252b5132 RH |
3932 | } |
3933 | } | |
3934 | ||
3935 | /* Handle a macro. Gather all the operands, transform them as | |
3936 | described by the macro, and call md_assemble recursively. All the | |
3937 | operands are separated by commas; we don't accept parentheses | |
3938 | around operands here. */ | |
3939 | ||
3940 | static void | |
98027b10 | 3941 | ppc_macro (char *str, const struct powerpc_macro *macro) |
252b5132 RH |
3942 | { |
3943 | char *operands[10]; | |
3944 | unsigned int count; | |
3945 | char *s; | |
3946 | unsigned int len; | |
3947 | const char *format; | |
db557034 | 3948 | unsigned int arg; |
252b5132 RH |
3949 | char *send; |
3950 | char *complete; | |
3951 | ||
3952 | /* Gather the users operands into the operands array. */ | |
3953 | count = 0; | |
3954 | s = str; | |
3955 | while (1) | |
3956 | { | |
3957 | if (count >= sizeof operands / sizeof operands[0]) | |
3958 | break; | |
3959 | operands[count++] = s; | |
3960 | s = strchr (s, ','); | |
3961 | if (s == (char *) NULL) | |
3962 | break; | |
3963 | *s++ = '\0'; | |
81d4177b | 3964 | } |
252b5132 RH |
3965 | |
3966 | if (count != macro->operands) | |
3967 | { | |
3968 | as_bad (_("wrong number of operands")); | |
3969 | return; | |
3970 | } | |
3971 | ||
3972 | /* Work out how large the string must be (the size is unbounded | |
3973 | because it includes user input). */ | |
3974 | len = 0; | |
3975 | format = macro->format; | |
3976 | while (*format != '\0') | |
3977 | { | |
3978 | if (*format != '%') | |
3979 | { | |
3980 | ++len; | |
3981 | ++format; | |
3982 | } | |
3983 | else | |
3984 | { | |
3985 | arg = strtol (format + 1, &send, 10); | |
db557034 | 3986 | know (send != format && arg < count); |
252b5132 RH |
3987 | len += strlen (operands[arg]); |
3988 | format = send; | |
3989 | } | |
3990 | } | |
3991 | ||
3992 | /* Put the string together. */ | |
325801bd | 3993 | complete = s = XNEWVEC (char, len + 1); |
252b5132 RH |
3994 | format = macro->format; |
3995 | while (*format != '\0') | |
3996 | { | |
3997 | if (*format != '%') | |
3998 | *s++ = *format++; | |
3999 | else | |
4000 | { | |
4001 | arg = strtol (format + 1, &send, 10); | |
4002 | strcpy (s, operands[arg]); | |
4003 | s += strlen (s); | |
4004 | format = send; | |
4005 | } | |
4006 | } | |
4007 | *s = '\0'; | |
4008 | ||
4009 | /* Assemble the constructed instruction. */ | |
4010 | md_assemble (complete); | |
e1fa0163 | 4011 | free (complete); |
81d4177b | 4012 | } |
252b5132 RH |
4013 | \f |
4014 | #ifdef OBJ_ELF | |
18ae9cc1 | 4015 | /* For ELF, add support for SHT_ORDERED. */ |
252b5132 RH |
4016 | |
4017 | int | |
98027b10 | 4018 | ppc_section_type (char *str, size_t len) |
252b5132 | 4019 | { |
9de8d8f1 RH |
4020 | if (len == 7 && strncmp (str, "ordered", 7) == 0) |
4021 | return SHT_ORDERED; | |
252b5132 | 4022 | |
9de8d8f1 | 4023 | return -1; |
252b5132 RH |
4024 | } |
4025 | ||
4026 | int | |
1239de13 | 4027 | ppc_section_flags (flagword flags, bfd_vma attr ATTRIBUTE_UNUSED, int type) |
252b5132 RH |
4028 | { |
4029 | if (type == SHT_ORDERED) | |
4030 | flags |= SEC_ALLOC | SEC_LOAD | SEC_SORT_ENTRIES; | |
4031 | ||
252b5132 RH |
4032 | return flags; |
4033 | } | |
83eef883 AFB |
4034 | |
4035 | bfd_vma | |
4036 | ppc_elf_section_letter (int letter, const char **ptrmsg) | |
4037 | { | |
4038 | if (letter == 'v') | |
4039 | return SHF_PPC_VLE; | |
4040 | ||
4041 | *ptrmsg = _("bad .section directive: want a,e,v,w,x,M,S,G,T in string"); | |
4042 | return -1; | |
4043 | } | |
252b5132 RH |
4044 | #endif /* OBJ_ELF */ |
4045 | ||
4046 | \f | |
4047 | /* Pseudo-op handling. */ | |
4048 | ||
4049 | /* The .byte pseudo-op. This is similar to the normal .byte | |
4050 | pseudo-op, but it can also take a single ASCII string. */ | |
4051 | ||
4052 | static void | |
98027b10 | 4053 | ppc_byte (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 4054 | { |
bf7279d5 AM |
4055 | int count = 0; |
4056 | ||
252b5132 RH |
4057 | if (*input_line_pointer != '\"') |
4058 | { | |
4059 | cons (1); | |
4060 | return; | |
4061 | } | |
4062 | ||
4063 | /* Gather characters. A real double quote is doubled. Unusual | |
4064 | characters are not permitted. */ | |
4065 | ++input_line_pointer; | |
4066 | while (1) | |
4067 | { | |
4068 | char c; | |
4069 | ||
4070 | c = *input_line_pointer++; | |
4071 | ||
4072 | if (c == '\"') | |
4073 | { | |
4074 | if (*input_line_pointer != '\"') | |
4075 | break; | |
4076 | ++input_line_pointer; | |
4077 | } | |
4078 | ||
4079 | FRAG_APPEND_1_CHAR (c); | |
bf7279d5 | 4080 | ++count; |
252b5132 RH |
4081 | } |
4082 | ||
bf7279d5 AM |
4083 | if (warn_476 && count != 0 && (now_seg->flags & SEC_CODE) != 0) |
4084 | as_warn (_("data in executable section")); | |
252b5132 RH |
4085 | demand_empty_rest_of_line (); |
4086 | } | |
4087 | \f | |
4088 | #ifdef OBJ_XCOFF | |
4089 | ||
4090 | /* XCOFF specific pseudo-op handling. */ | |
4091 | ||
4092 | /* This is set if we are creating a .stabx symbol, since we don't want | |
4093 | to handle symbol suffixes for such symbols. */ | |
b34976b6 | 4094 | static bfd_boolean ppc_stab_symbol; |
252b5132 RH |
4095 | |
4096 | /* The .comm and .lcomm pseudo-ops for XCOFF. XCOFF puts common | |
4097 | symbols in the .bss segment as though they were local common | |
67c1ffbe | 4098 | symbols, and uses a different smclas. The native Aix 4.3.3 assembler |
1ad63b2f | 4099 | aligns .comm and .lcomm to 4 bytes. */ |
252b5132 RH |
4100 | |
4101 | static void | |
98027b10 | 4102 | ppc_comm (int lcomm) |
252b5132 RH |
4103 | { |
4104 | asection *current_seg = now_seg; | |
4105 | subsegT current_subseg = now_subseg; | |
4106 | char *name; | |
4107 | char endc; | |
4108 | char *end_name; | |
4109 | offsetT size; | |
4110 | offsetT align; | |
4111 | symbolS *lcomm_sym = NULL; | |
4112 | symbolS *sym; | |
4113 | char *pfrag; | |
4114 | ||
d02603dc | 4115 | endc = get_symbol_name (&name); |
252b5132 | 4116 | end_name = input_line_pointer; |
d02603dc | 4117 | (void) restore_line_pointer (endc); |
252b5132 RH |
4118 | |
4119 | if (*input_line_pointer != ',') | |
4120 | { | |
4121 | as_bad (_("missing size")); | |
4122 | ignore_rest_of_line (); | |
4123 | return; | |
4124 | } | |
4125 | ++input_line_pointer; | |
4126 | ||
4127 | size = get_absolute_expression (); | |
4128 | if (size < 0) | |
4129 | { | |
4130 | as_bad (_("negative size")); | |
4131 | ignore_rest_of_line (); | |
4132 | return; | |
4133 | } | |
4134 | ||
4135 | if (! lcomm) | |
4136 | { | |
4137 | /* The third argument to .comm is the alignment. */ | |
4138 | if (*input_line_pointer != ',') | |
1ad63b2f | 4139 | align = 2; |
252b5132 RH |
4140 | else |
4141 | { | |
4142 | ++input_line_pointer; | |
4143 | align = get_absolute_expression (); | |
4144 | if (align <= 0) | |
4145 | { | |
4146 | as_warn (_("ignoring bad alignment")); | |
1ad63b2f | 4147 | align = 2; |
252b5132 RH |
4148 | } |
4149 | } | |
4150 | } | |
4151 | else | |
4152 | { | |
4153 | char *lcomm_name; | |
4154 | char lcomm_endc; | |
4155 | ||
252b5132 RH |
4156 | /* The third argument to .lcomm appears to be the real local |
4157 | common symbol to create. References to the symbol named in | |
4158 | the first argument are turned into references to the third | |
4159 | argument. */ | |
4160 | if (*input_line_pointer != ',') | |
4161 | { | |
4162 | as_bad (_("missing real symbol name")); | |
4163 | ignore_rest_of_line (); | |
4164 | return; | |
4165 | } | |
4166 | ++input_line_pointer; | |
4167 | ||
d02603dc | 4168 | lcomm_endc = get_symbol_name (&lcomm_name); |
81d4177b | 4169 | |
252b5132 RH |
4170 | lcomm_sym = symbol_find_or_make (lcomm_name); |
4171 | ||
d02603dc | 4172 | (void) restore_line_pointer (lcomm_endc); |
3c02c47f DE |
4173 | |
4174 | /* The fourth argument to .lcomm is the alignment. */ | |
4175 | if (*input_line_pointer != ',') | |
4176 | { | |
4177 | if (size <= 4) | |
4178 | align = 2; | |
4179 | else | |
4180 | align = 3; | |
4181 | } | |
4182 | else | |
4183 | { | |
4184 | ++input_line_pointer; | |
4185 | align = get_absolute_expression (); | |
4186 | if (align <= 0) | |
4187 | { | |
4188 | as_warn (_("ignoring bad alignment")); | |
4189 | align = 2; | |
4190 | } | |
4191 | } | |
252b5132 RH |
4192 | } |
4193 | ||
4194 | *end_name = '\0'; | |
4195 | sym = symbol_find_or_make (name); | |
4196 | *end_name = endc; | |
4197 | ||
4198 | if (S_IS_DEFINED (sym) | |
4199 | || S_GET_VALUE (sym) != 0) | |
4200 | { | |
4201 | as_bad (_("attempt to redefine symbol")); | |
4202 | ignore_rest_of_line (); | |
4203 | return; | |
4204 | } | |
81d4177b | 4205 | |
252b5132 | 4206 | record_alignment (bss_section, align); |
81d4177b | 4207 | |
252b5132 RH |
4208 | if (! lcomm |
4209 | || ! S_IS_DEFINED (lcomm_sym)) | |
4210 | { | |
4211 | symbolS *def_sym; | |
4212 | offsetT def_size; | |
4213 | ||
4214 | if (! lcomm) | |
4215 | { | |
4216 | def_sym = sym; | |
4217 | def_size = size; | |
4218 | S_SET_EXTERNAL (sym); | |
4219 | } | |
4220 | else | |
4221 | { | |
809ffe0d | 4222 | symbol_get_tc (lcomm_sym)->output = 1; |
252b5132 RH |
4223 | def_sym = lcomm_sym; |
4224 | def_size = 0; | |
4225 | } | |
4226 | ||
4227 | subseg_set (bss_section, 1); | |
4228 | frag_align (align, 0, 0); | |
81d4177b | 4229 | |
809ffe0d | 4230 | symbol_set_frag (def_sym, frag_now); |
252b5132 RH |
4231 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, def_sym, |
4232 | def_size, (char *) NULL); | |
4233 | *pfrag = 0; | |
4234 | S_SET_SEGMENT (def_sym, bss_section); | |
809ffe0d | 4235 | symbol_get_tc (def_sym)->align = align; |
252b5132 RH |
4236 | } |
4237 | else if (lcomm) | |
4238 | { | |
4239 | /* Align the size of lcomm_sym. */ | |
809ffe0d ILT |
4240 | symbol_get_frag (lcomm_sym)->fr_offset = |
4241 | ((symbol_get_frag (lcomm_sym)->fr_offset + (1 << align) - 1) | |
252b5132 | 4242 | &~ ((1 << align) - 1)); |
809ffe0d ILT |
4243 | if (align > symbol_get_tc (lcomm_sym)->align) |
4244 | symbol_get_tc (lcomm_sym)->align = align; | |
252b5132 RH |
4245 | } |
4246 | ||
4247 | if (lcomm) | |
4248 | { | |
4249 | /* Make sym an offset from lcomm_sym. */ | |
4250 | S_SET_SEGMENT (sym, bss_section); | |
809ffe0d ILT |
4251 | symbol_set_frag (sym, symbol_get_frag (lcomm_sym)); |
4252 | S_SET_VALUE (sym, symbol_get_frag (lcomm_sym)->fr_offset); | |
4253 | symbol_get_frag (lcomm_sym)->fr_offset += size; | |
252b5132 RH |
4254 | } |
4255 | ||
4256 | subseg_set (current_seg, current_subseg); | |
4257 | ||
4258 | demand_empty_rest_of_line (); | |
4259 | } | |
4260 | ||
4261 | /* The .csect pseudo-op. This switches us into a different | |
4262 | subsegment. The first argument is a symbol whose value is the | |
4263 | start of the .csect. In COFF, csect symbols get special aux | |
4264 | entries defined by the x_csect field of union internal_auxent. The | |
4265 | optional second argument is the alignment (the default is 2). */ | |
4266 | ||
4267 | static void | |
98027b10 | 4268 | ppc_csect (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4269 | { |
4270 | char *name; | |
4271 | char endc; | |
4272 | symbolS *sym; | |
931e13a6 | 4273 | offsetT align; |
252b5132 | 4274 | |
d02603dc | 4275 | endc = get_symbol_name (&name); |
81d4177b | 4276 | |
252b5132 RH |
4277 | sym = symbol_find_or_make (name); |
4278 | ||
d02603dc | 4279 | (void) restore_line_pointer (endc); |
252b5132 RH |
4280 | |
4281 | if (S_GET_NAME (sym)[0] == '\0') | |
4282 | { | |
4283 | /* An unnamed csect is assumed to be [PR]. */ | |
96d56e9f | 4284 | symbol_get_tc (sym)->symbol_class = XMC_PR; |
252b5132 RH |
4285 | } |
4286 | ||
931e13a6 | 4287 | align = 2; |
252b5132 RH |
4288 | if (*input_line_pointer == ',') |
4289 | { | |
4290 | ++input_line_pointer; | |
931e13a6 | 4291 | align = get_absolute_expression (); |
252b5132 RH |
4292 | } |
4293 | ||
931e13a6 AM |
4294 | ppc_change_csect (sym, align); |
4295 | ||
252b5132 RH |
4296 | demand_empty_rest_of_line (); |
4297 | } | |
4298 | ||
4299 | /* Change to a different csect. */ | |
4300 | ||
4301 | static void | |
98027b10 | 4302 | ppc_change_csect (symbolS *sym, offsetT align) |
252b5132 RH |
4303 | { |
4304 | if (S_IS_DEFINED (sym)) | |
809ffe0d | 4305 | subseg_set (S_GET_SEGMENT (sym), symbol_get_tc (sym)->subseg); |
252b5132 RH |
4306 | else |
4307 | { | |
4308 | symbolS **list_ptr; | |
4309 | int after_toc; | |
4310 | int hold_chunksize; | |
4311 | symbolS *list; | |
931e13a6 AM |
4312 | int is_code; |
4313 | segT sec; | |
252b5132 RH |
4314 | |
4315 | /* This is a new csect. We need to look at the symbol class to | |
4316 | figure out whether it should go in the text section or the | |
4317 | data section. */ | |
4318 | after_toc = 0; | |
931e13a6 | 4319 | is_code = 0; |
96d56e9f | 4320 | switch (symbol_get_tc (sym)->symbol_class) |
252b5132 RH |
4321 | { |
4322 | case XMC_PR: | |
4323 | case XMC_RO: | |
4324 | case XMC_DB: | |
4325 | case XMC_GL: | |
4326 | case XMC_XO: | |
4327 | case XMC_SV: | |
4328 | case XMC_TI: | |
4329 | case XMC_TB: | |
4330 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 4331 | symbol_get_tc (sym)->subseg = ppc_text_subsegment; |
252b5132 RH |
4332 | ++ppc_text_subsegment; |
4333 | list_ptr = &ppc_text_csects; | |
931e13a6 | 4334 | is_code = 1; |
252b5132 RH |
4335 | break; |
4336 | case XMC_RW: | |
4337 | case XMC_TC0: | |
4338 | case XMC_TC: | |
4339 | case XMC_DS: | |
4340 | case XMC_UA: | |
4341 | case XMC_BS: | |
4342 | case XMC_UC: | |
4343 | if (ppc_toc_csect != NULL | |
809ffe0d ILT |
4344 | && (symbol_get_tc (ppc_toc_csect)->subseg + 1 |
4345 | == ppc_data_subsegment)) | |
252b5132 RH |
4346 | after_toc = 1; |
4347 | S_SET_SEGMENT (sym, data_section); | |
809ffe0d | 4348 | symbol_get_tc (sym)->subseg = ppc_data_subsegment; |
252b5132 RH |
4349 | ++ppc_data_subsegment; |
4350 | list_ptr = &ppc_data_csects; | |
4351 | break; | |
4352 | default: | |
4353 | abort (); | |
4354 | } | |
4355 | ||
4356 | /* We set the obstack chunk size to a small value before | |
99a814a1 AM |
4357 | changing subsegments, so that we don't use a lot of memory |
4358 | space for what may be a small section. */ | |
252b5132 RH |
4359 | hold_chunksize = chunksize; |
4360 | chunksize = 64; | |
4361 | ||
931e13a6 AM |
4362 | sec = subseg_new (segment_name (S_GET_SEGMENT (sym)), |
4363 | symbol_get_tc (sym)->subseg); | |
252b5132 RH |
4364 | |
4365 | chunksize = hold_chunksize; | |
4366 | ||
4367 | if (after_toc) | |
4368 | ppc_after_toc_frag = frag_now; | |
4369 | ||
931e13a6 AM |
4370 | record_alignment (sec, align); |
4371 | if (is_code) | |
4372 | frag_align_code (align, 0); | |
4373 | else | |
4374 | frag_align (align, 0, 0); | |
4375 | ||
809ffe0d | 4376 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
4377 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); |
4378 | ||
931e13a6 | 4379 | symbol_get_tc (sym)->align = align; |
809ffe0d ILT |
4380 | symbol_get_tc (sym)->output = 1; |
4381 | symbol_get_tc (sym)->within = sym; | |
81d4177b | 4382 | |
252b5132 | 4383 | for (list = *list_ptr; |
809ffe0d ILT |
4384 | symbol_get_tc (list)->next != (symbolS *) NULL; |
4385 | list = symbol_get_tc (list)->next) | |
252b5132 | 4386 | ; |
809ffe0d | 4387 | symbol_get_tc (list)->next = sym; |
81d4177b | 4388 | |
252b5132 | 4389 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); |
809ffe0d ILT |
4390 | symbol_append (sym, symbol_get_tc (list)->within, &symbol_rootP, |
4391 | &symbol_lastP); | |
252b5132 RH |
4392 | } |
4393 | ||
4394 | ppc_current_csect = sym; | |
4395 | } | |
4396 | ||
85645aed TG |
4397 | static void |
4398 | ppc_change_debug_section (unsigned int idx, subsegT subseg) | |
4399 | { | |
4400 | segT sec; | |
4401 | flagword oldflags; | |
4402 | const struct xcoff_dwsect_name *dw = &xcoff_dwsect_names[idx]; | |
4403 | ||
4404 | sec = subseg_new (dw->name, subseg); | |
fd361982 | 4405 | oldflags = bfd_section_flags (sec); |
85645aed TG |
4406 | if (oldflags == SEC_NO_FLAGS) |
4407 | { | |
4408 | /* Just created section. */ | |
4409 | gas_assert (dw_sections[idx].sect == NULL); | |
4410 | ||
fd361982 AM |
4411 | bfd_set_section_flags (sec, SEC_DEBUGGING); |
4412 | bfd_set_section_alignment (sec, 0); | |
85645aed TG |
4413 | dw_sections[idx].sect = sec; |
4414 | } | |
4415 | ||
4416 | /* Not anymore in a csect. */ | |
4417 | ppc_current_csect = NULL; | |
4418 | } | |
4419 | ||
4420 | /* The .dwsect pseudo-op. Defines a DWARF section. Syntax is: | |
4421 | .dwsect flag [, opt-label ] | |
4422 | */ | |
4423 | ||
4424 | static void | |
4425 | ppc_dwsect (int ignore ATTRIBUTE_UNUSED) | |
4426 | { | |
16de26a6 | 4427 | valueT flag; |
85645aed TG |
4428 | symbolS *opt_label; |
4429 | const struct xcoff_dwsect_name *dw; | |
4430 | struct dw_subsection *subseg; | |
4431 | struct dw_section *dws; | |
4432 | int i; | |
4433 | ||
4434 | /* Find section. */ | |
4435 | flag = get_absolute_expression (); | |
4436 | dw = NULL; | |
4437 | for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++) | |
4438 | if (xcoff_dwsect_names[i].flag == flag) | |
4439 | { | |
4440 | dw = &xcoff_dwsect_names[i]; | |
4441 | break; | |
4442 | } | |
4443 | ||
4444 | /* Parse opt-label. */ | |
4445 | if (*input_line_pointer == ',') | |
4446 | { | |
d02603dc | 4447 | char *label; |
85645aed TG |
4448 | char c; |
4449 | ||
4450 | ++input_line_pointer; | |
4451 | ||
d02603dc | 4452 | c = get_symbol_name (&label); |
85645aed | 4453 | opt_label = symbol_find_or_make (label); |
d02603dc | 4454 | (void) restore_line_pointer (c); |
85645aed TG |
4455 | } |
4456 | else | |
4457 | opt_label = NULL; | |
4458 | ||
4459 | demand_empty_rest_of_line (); | |
4460 | ||
4461 | /* Return now in case of unknown subsection. */ | |
4462 | if (dw == NULL) | |
4463 | { | |
d6ed37ed | 4464 | as_bad (_("no known dwarf XCOFF section for flag 0x%08x\n"), |
85645aed TG |
4465 | (unsigned)flag); |
4466 | return; | |
4467 | } | |
4468 | ||
4469 | /* Find the subsection. */ | |
4470 | dws = &dw_sections[i]; | |
4471 | subseg = NULL; | |
4472 | if (opt_label != NULL && S_IS_DEFINED (opt_label)) | |
4473 | { | |
4474 | /* Sanity check (note that in theory S_GET_SEGMENT mustn't be null). */ | |
4475 | if (dws->sect == NULL || S_GET_SEGMENT (opt_label) != dws->sect) | |
4476 | { | |
4477 | as_bad (_("label %s was not defined in this dwarf section"), | |
4478 | S_GET_NAME (opt_label)); | |
4479 | subseg = dws->anon_subseg; | |
4480 | opt_label = NULL; | |
4481 | } | |
4482 | else | |
4483 | subseg = symbol_get_tc (opt_label)->u.dw; | |
4484 | } | |
4485 | ||
4486 | if (subseg != NULL) | |
4487 | { | |
4488 | /* Switch to the subsection. */ | |
4489 | ppc_change_debug_section (i, subseg->subseg); | |
4490 | } | |
4491 | else | |
4492 | { | |
4493 | /* Create a new dw subsection. */ | |
325801bd | 4494 | subseg = XNEW (struct dw_subsection); |
85645aed TG |
4495 | |
4496 | if (opt_label == NULL) | |
4497 | { | |
4498 | /* The anonymous one. */ | |
4499 | subseg->subseg = 0; | |
4500 | subseg->link = NULL; | |
4501 | dws->anon_subseg = subseg; | |
4502 | } | |
4503 | else | |
4504 | { | |
4505 | /* A named one. */ | |
4506 | if (dws->list_subseg != NULL) | |
4507 | subseg->subseg = dws->list_subseg->subseg + 1; | |
4508 | else | |
4509 | subseg->subseg = 1; | |
4510 | ||
4511 | subseg->link = dws->list_subseg; | |
4512 | dws->list_subseg = subseg; | |
4513 | symbol_get_tc (opt_label)->u.dw = subseg; | |
4514 | } | |
4515 | ||
4516 | ppc_change_debug_section (i, subseg->subseg); | |
4517 | ||
4518 | if (dw->def_size) | |
4519 | { | |
4520 | /* Add the length field. */ | |
4521 | expressionS *exp = &subseg->end_exp; | |
4522 | int sz; | |
4523 | ||
4524 | if (opt_label != NULL) | |
4525 | symbol_set_value_now (opt_label); | |
4526 | ||
4527 | /* Add the length field. Note that according to the AIX assembler | |
4528 | manual, the size of the length field is 4 for powerpc32 but | |
4529 | 12 for powerpc64. */ | |
4530 | if (ppc_obj64) | |
4531 | { | |
4532 | /* Write the 64bit marker. */ | |
4533 | md_number_to_chars (frag_more (4), -1, 4); | |
4534 | } | |
4535 | ||
4536 | exp->X_op = O_subtract; | |
4537 | exp->X_op_symbol = symbol_temp_new_now (); | |
4538 | exp->X_add_symbol = symbol_temp_make (); | |
4539 | ||
4540 | sz = ppc_obj64 ? 8 : 4; | |
4541 | exp->X_add_number = -sz; | |
4542 | emit_expr (exp, sz); | |
4543 | } | |
4544 | } | |
4545 | } | |
4546 | ||
252b5132 RH |
4547 | /* This function handles the .text and .data pseudo-ops. These |
4548 | pseudo-ops aren't really used by XCOFF; we implement them for the | |
4549 | convenience of people who aren't used to XCOFF. */ | |
4550 | ||
4551 | static void | |
98027b10 | 4552 | ppc_section (int type) |
252b5132 RH |
4553 | { |
4554 | const char *name; | |
4555 | symbolS *sym; | |
4556 | ||
4557 | if (type == 't') | |
4558 | name = ".text[PR]"; | |
4559 | else if (type == 'd') | |
4560 | name = ".data[RW]"; | |
4561 | else | |
4562 | abort (); | |
4563 | ||
4564 | sym = symbol_find_or_make (name); | |
4565 | ||
931e13a6 | 4566 | ppc_change_csect (sym, 2); |
252b5132 RH |
4567 | |
4568 | demand_empty_rest_of_line (); | |
4569 | } | |
4570 | ||
4571 | /* This function handles the .section pseudo-op. This is mostly to | |
4572 | give an error, since XCOFF only supports .text, .data and .bss, but | |
4573 | we do permit the user to name the text or data section. */ | |
4574 | ||
4575 | static void | |
98027b10 | 4576 | ppc_named_section (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4577 | { |
4578 | char *user_name; | |
4579 | const char *real_name; | |
4580 | char c; | |
4581 | symbolS *sym; | |
4582 | ||
d02603dc | 4583 | c = get_symbol_name (&user_name); |
252b5132 RH |
4584 | |
4585 | if (strcmp (user_name, ".text") == 0) | |
4586 | real_name = ".text[PR]"; | |
4587 | else if (strcmp (user_name, ".data") == 0) | |
4588 | real_name = ".data[RW]"; | |
4589 | else | |
4590 | { | |
d6ed37ed | 4591 | as_bad (_("the XCOFF file format does not support arbitrary sections")); |
d02603dc | 4592 | (void) restore_line_pointer (c); |
252b5132 RH |
4593 | ignore_rest_of_line (); |
4594 | return; | |
4595 | } | |
4596 | ||
d02603dc | 4597 | (void) restore_line_pointer (c); |
252b5132 RH |
4598 | |
4599 | sym = symbol_find_or_make (real_name); | |
4600 | ||
931e13a6 | 4601 | ppc_change_csect (sym, 2); |
252b5132 RH |
4602 | |
4603 | demand_empty_rest_of_line (); | |
4604 | } | |
4605 | ||
4606 | /* The .extern pseudo-op. We create an undefined symbol. */ | |
4607 | ||
4608 | static void | |
98027b10 | 4609 | ppc_extern (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4610 | { |
4611 | char *name; | |
4612 | char endc; | |
4613 | ||
d02603dc | 4614 | endc = get_symbol_name (&name); |
252b5132 RH |
4615 | |
4616 | (void) symbol_find_or_make (name); | |
4617 | ||
d02603dc | 4618 | (void) restore_line_pointer (endc); |
252b5132 RH |
4619 | |
4620 | demand_empty_rest_of_line (); | |
4621 | } | |
4622 | ||
4623 | /* The .lglobl pseudo-op. Keep the symbol in the symbol table. */ | |
4624 | ||
4625 | static void | |
98027b10 | 4626 | ppc_lglobl (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4627 | { |
4628 | char *name; | |
4629 | char endc; | |
4630 | symbolS *sym; | |
4631 | ||
d02603dc | 4632 | endc = get_symbol_name (&name); |
252b5132 RH |
4633 | |
4634 | sym = symbol_find_or_make (name); | |
4635 | ||
d02603dc | 4636 | (void) restore_line_pointer (endc); |
252b5132 | 4637 | |
809ffe0d | 4638 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
4639 | |
4640 | demand_empty_rest_of_line (); | |
4641 | } | |
4642 | ||
c865e45b RS |
4643 | /* The .ref pseudo-op. It takes a list of symbol names and inserts R_REF |
4644 | relocations at the beginning of the current csect. | |
4645 | ||
4646 | (In principle, there's no reason why the relocations _have_ to be at | |
4647 | the beginning. Anywhere in the csect would do. However, inserting | |
33eaf5de | 4648 | at the beginning is what the native assembler does, and it helps to |
c865e45b RS |
4649 | deal with cases where the .ref statements follow the section contents.) |
4650 | ||
4651 | ??? .refs don't work for empty .csects. However, the native assembler | |
4652 | doesn't report an error in this case, and neither yet do we. */ | |
4653 | ||
4654 | static void | |
4655 | ppc_ref (int ignore ATTRIBUTE_UNUSED) | |
4656 | { | |
4657 | char *name; | |
4658 | char c; | |
4659 | ||
4660 | if (ppc_current_csect == NULL) | |
4661 | { | |
4662 | as_bad (_(".ref outside .csect")); | |
4663 | ignore_rest_of_line (); | |
4664 | return; | |
4665 | } | |
4666 | ||
4667 | do | |
4668 | { | |
d02603dc | 4669 | c = get_symbol_name (&name); |
c865e45b RS |
4670 | |
4671 | fix_at_start (symbol_get_frag (ppc_current_csect), 0, | |
4672 | symbol_find_or_make (name), 0, FALSE, BFD_RELOC_NONE); | |
4673 | ||
4674 | *input_line_pointer = c; | |
d02603dc | 4675 | SKIP_WHITESPACE_AFTER_NAME (); |
c865e45b RS |
4676 | c = *input_line_pointer; |
4677 | if (c == ',') | |
4678 | { | |
4679 | input_line_pointer++; | |
4680 | SKIP_WHITESPACE (); | |
4681 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
4682 | { | |
4683 | as_bad (_("missing symbol name")); | |
4684 | ignore_rest_of_line (); | |
4685 | return; | |
4686 | } | |
4687 | } | |
4688 | } | |
4689 | while (c == ','); | |
4690 | ||
4691 | demand_empty_rest_of_line (); | |
4692 | } | |
4693 | ||
252b5132 RH |
4694 | /* The .rename pseudo-op. The RS/6000 assembler can rename symbols, |
4695 | although I don't know why it bothers. */ | |
4696 | ||
4697 | static void | |
98027b10 | 4698 | ppc_rename (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4699 | { |
4700 | char *name; | |
4701 | char endc; | |
4702 | symbolS *sym; | |
4703 | int len; | |
4704 | ||
d02603dc | 4705 | endc = get_symbol_name (&name); |
252b5132 RH |
4706 | |
4707 | sym = symbol_find_or_make (name); | |
4708 | ||
d02603dc | 4709 | (void) restore_line_pointer (endc); |
252b5132 RH |
4710 | |
4711 | if (*input_line_pointer != ',') | |
4712 | { | |
4713 | as_bad (_("missing rename string")); | |
4714 | ignore_rest_of_line (); | |
4715 | return; | |
4716 | } | |
4717 | ++input_line_pointer; | |
4718 | ||
809ffe0d | 4719 | symbol_get_tc (sym)->real_name = demand_copy_C_string (&len); |
252b5132 RH |
4720 | |
4721 | demand_empty_rest_of_line (); | |
4722 | } | |
4723 | ||
4724 | /* The .stabx pseudo-op. This is similar to a normal .stabs | |
4725 | pseudo-op, but slightly different. A sample is | |
4726 | .stabx "main:F-1",.main,142,0 | |
4727 | The first argument is the symbol name to create. The second is the | |
4728 | value, and the third is the storage class. The fourth seems to be | |
4729 | always zero, and I am assuming it is the type. */ | |
4730 | ||
4731 | static void | |
98027b10 | 4732 | ppc_stabx (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4733 | { |
4734 | char *name; | |
4735 | int len; | |
4736 | symbolS *sym; | |
4737 | expressionS exp; | |
4738 | ||
4739 | name = demand_copy_C_string (&len); | |
4740 | ||
4741 | if (*input_line_pointer != ',') | |
4742 | { | |
4743 | as_bad (_("missing value")); | |
4744 | return; | |
4745 | } | |
4746 | ++input_line_pointer; | |
4747 | ||
b34976b6 | 4748 | ppc_stab_symbol = TRUE; |
252b5132 | 4749 | sym = symbol_make (name); |
b34976b6 | 4750 | ppc_stab_symbol = FALSE; |
252b5132 | 4751 | |
809ffe0d | 4752 | symbol_get_tc (sym)->real_name = name; |
252b5132 RH |
4753 | |
4754 | (void) expression (&exp); | |
4755 | ||
4756 | switch (exp.X_op) | |
4757 | { | |
4758 | case O_illegal: | |
4759 | case O_absent: | |
4760 | case O_big: | |
4761 | as_bad (_("illegal .stabx expression; zero assumed")); | |
4762 | exp.X_add_number = 0; | |
4763 | /* Fall through. */ | |
4764 | case O_constant: | |
4765 | S_SET_VALUE (sym, (valueT) exp.X_add_number); | |
809ffe0d | 4766 | symbol_set_frag (sym, &zero_address_frag); |
252b5132 RH |
4767 | break; |
4768 | ||
4769 | case O_symbol: | |
4770 | if (S_GET_SEGMENT (exp.X_add_symbol) == undefined_section) | |
809ffe0d | 4771 | symbol_set_value_expression (sym, &exp); |
252b5132 RH |
4772 | else |
4773 | { | |
4774 | S_SET_VALUE (sym, | |
4775 | exp.X_add_number + S_GET_VALUE (exp.X_add_symbol)); | |
809ffe0d | 4776 | symbol_set_frag (sym, symbol_get_frag (exp.X_add_symbol)); |
252b5132 RH |
4777 | } |
4778 | break; | |
4779 | ||
4780 | default: | |
4781 | /* The value is some complex expression. This will probably | |
99a814a1 AM |
4782 | fail at some later point, but this is probably the right |
4783 | thing to do here. */ | |
809ffe0d | 4784 | symbol_set_value_expression (sym, &exp); |
252b5132 RH |
4785 | break; |
4786 | } | |
4787 | ||
4788 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 4789 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
4790 | |
4791 | if (*input_line_pointer != ',') | |
4792 | { | |
4793 | as_bad (_("missing class")); | |
4794 | return; | |
4795 | } | |
4796 | ++input_line_pointer; | |
4797 | ||
4798 | S_SET_STORAGE_CLASS (sym, get_absolute_expression ()); | |
4799 | ||
4800 | if (*input_line_pointer != ',') | |
4801 | { | |
4802 | as_bad (_("missing type")); | |
4803 | return; | |
4804 | } | |
4805 | ++input_line_pointer; | |
4806 | ||
4807 | S_SET_DATA_TYPE (sym, get_absolute_expression ()); | |
4808 | ||
809ffe0d | 4809 | symbol_get_tc (sym)->output = 1; |
252b5132 | 4810 | |
c734e7e3 TG |
4811 | if (S_GET_STORAGE_CLASS (sym) == C_STSYM) |
4812 | { | |
4813 | /* In this case : | |
252b5132 | 4814 | |
c734e7e3 TG |
4815 | .bs name |
4816 | .stabx "z",arrays_,133,0 | |
4817 | .es | |
99a814a1 | 4818 | |
c734e7e3 | 4819 | .comm arrays_,13768,3 |
99a814a1 | 4820 | |
c734e7e3 TG |
4821 | resolve_symbol_value will copy the exp's "within" into sym's when the |
4822 | offset is 0. Since this seems to be corner case problem, | |
4823 | only do the correction for storage class C_STSYM. A better solution | |
4824 | would be to have the tc field updated in ppc_symbol_new_hook. */ | |
99a814a1 | 4825 | |
c734e7e3 TG |
4826 | if (exp.X_op == O_symbol) |
4827 | { | |
4828 | if (ppc_current_block == NULL) | |
4829 | as_bad (_(".stabx of storage class stsym must be within .bs/.es")); | |
99a814a1 | 4830 | |
c734e7e3 TG |
4831 | symbol_get_tc (sym)->within = ppc_current_block; |
4832 | symbol_get_tc (exp.X_add_symbol)->within = ppc_current_block; | |
4833 | } | |
4834 | } | |
99a814a1 | 4835 | |
252b5132 RH |
4836 | if (exp.X_op != O_symbol |
4837 | || ! S_IS_EXTERNAL (exp.X_add_symbol) | |
4838 | || S_GET_SEGMENT (exp.X_add_symbol) != bss_section) | |
4839 | ppc_frob_label (sym); | |
4840 | else | |
4841 | { | |
4842 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
4843 | symbol_append (sym, exp.X_add_symbol, &symbol_rootP, &symbol_lastP); | |
809ffe0d ILT |
4844 | if (symbol_get_tc (ppc_current_csect)->within == exp.X_add_symbol) |
4845 | symbol_get_tc (ppc_current_csect)->within = sym; | |
252b5132 RH |
4846 | } |
4847 | ||
4848 | demand_empty_rest_of_line (); | |
4849 | } | |
4850 | ||
4851 | /* The .function pseudo-op. This takes several arguments. The first | |
4852 | argument seems to be the external name of the symbol. The second | |
67c1ffbe | 4853 | argument seems to be the label for the start of the function. gcc |
252b5132 RH |
4854 | uses the same name for both. I have no idea what the third and |
4855 | fourth arguments are meant to be. The optional fifth argument is | |
4856 | an expression for the size of the function. In COFF this symbol | |
4857 | gets an aux entry like that used for a csect. */ | |
4858 | ||
4859 | static void | |
98027b10 | 4860 | ppc_function (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4861 | { |
4862 | char *name; | |
4863 | char endc; | |
4864 | char *s; | |
4865 | symbolS *ext_sym; | |
4866 | symbolS *lab_sym; | |
4867 | ||
d02603dc | 4868 | endc = get_symbol_name (&name); |
252b5132 RH |
4869 | |
4870 | /* Ignore any [PR] suffix. */ | |
4871 | name = ppc_canonicalize_symbol_name (name); | |
4872 | s = strchr (name, '['); | |
4873 | if (s != (char *) NULL | |
4874 | && strcmp (s + 1, "PR]") == 0) | |
4875 | *s = '\0'; | |
4876 | ||
4877 | ext_sym = symbol_find_or_make (name); | |
4878 | ||
d02603dc | 4879 | (void) restore_line_pointer (endc); |
252b5132 RH |
4880 | |
4881 | if (*input_line_pointer != ',') | |
4882 | { | |
4883 | as_bad (_("missing symbol name")); | |
4884 | ignore_rest_of_line (); | |
4885 | return; | |
4886 | } | |
4887 | ++input_line_pointer; | |
4888 | ||
d02603dc | 4889 | endc = get_symbol_name (&name); |
252b5132 RH |
4890 | |
4891 | lab_sym = symbol_find_or_make (name); | |
4892 | ||
d02603dc | 4893 | (void) restore_line_pointer (endc); |
252b5132 RH |
4894 | |
4895 | if (ext_sym != lab_sym) | |
4896 | { | |
809ffe0d ILT |
4897 | expressionS exp; |
4898 | ||
4899 | exp.X_op = O_symbol; | |
4900 | exp.X_add_symbol = lab_sym; | |
4901 | exp.X_op_symbol = NULL; | |
4902 | exp.X_add_number = 0; | |
4903 | exp.X_unsigned = 0; | |
4904 | symbol_set_value_expression (ext_sym, &exp); | |
252b5132 RH |
4905 | } |
4906 | ||
96d56e9f NC |
4907 | if (symbol_get_tc (ext_sym)->symbol_class == -1) |
4908 | symbol_get_tc (ext_sym)->symbol_class = XMC_PR; | |
809ffe0d | 4909 | symbol_get_tc (ext_sym)->output = 1; |
252b5132 RH |
4910 | |
4911 | if (*input_line_pointer == ',') | |
4912 | { | |
91d6fa6a | 4913 | expressionS exp; |
252b5132 RH |
4914 | |
4915 | /* Ignore the third argument. */ | |
4916 | ++input_line_pointer; | |
91d6fa6a | 4917 | expression (& exp); |
252b5132 RH |
4918 | if (*input_line_pointer == ',') |
4919 | { | |
4920 | /* Ignore the fourth argument. */ | |
4921 | ++input_line_pointer; | |
91d6fa6a | 4922 | expression (& exp); |
252b5132 RH |
4923 | if (*input_line_pointer == ',') |
4924 | { | |
4925 | /* The fifth argument is the function size. */ | |
4926 | ++input_line_pointer; | |
e01e1cee AM |
4927 | symbol_get_tc (ext_sym)->u.size |
4928 | = symbol_new ("L0\001", absolute_section, | |
4929 | &zero_address_frag, 0); | |
85645aed | 4930 | pseudo_set (symbol_get_tc (ext_sym)->u.size); |
252b5132 RH |
4931 | } |
4932 | } | |
4933 | } | |
4934 | ||
4935 | S_SET_DATA_TYPE (ext_sym, DT_FCN << N_BTSHFT); | |
4936 | SF_SET_FUNCTION (ext_sym); | |
4937 | SF_SET_PROCESS (ext_sym); | |
4938 | coff_add_linesym (ext_sym); | |
4939 | ||
4940 | demand_empty_rest_of_line (); | |
4941 | } | |
4942 | ||
4943 | /* The .bf pseudo-op. This is just like a COFF C_FCN symbol named | |
8642cce8 TR |
4944 | ".bf". If the pseudo op .bi was seen before .bf, patch the .bi sym |
4945 | with the correct line number */ | |
5d6255fe | 4946 | |
8642cce8 | 4947 | static symbolS *saved_bi_sym = 0; |
252b5132 RH |
4948 | |
4949 | static void | |
98027b10 | 4950 | ppc_bf (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4951 | { |
4952 | symbolS *sym; | |
4953 | ||
4954 | sym = symbol_make (".bf"); | |
4955 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 4956 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
4957 | S_SET_VALUE (sym, frag_now_fix ()); |
4958 | S_SET_STORAGE_CLASS (sym, C_FCN); | |
4959 | ||
4960 | coff_line_base = get_absolute_expression (); | |
4961 | ||
4962 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
4963 | SA_SET_SYM_LNNO (sym, coff_line_base); | |
4964 | ||
8642cce8 | 4965 | /* Line number for bi. */ |
5d6255fe | 4966 | if (saved_bi_sym) |
8642cce8 TR |
4967 | { |
4968 | S_SET_VALUE (saved_bi_sym, coff_n_line_nos); | |
4969 | saved_bi_sym = 0; | |
4970 | } | |
5d6255fe | 4971 | |
8642cce8 | 4972 | |
809ffe0d | 4973 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
4974 | |
4975 | ppc_frob_label (sym); | |
4976 | ||
4977 | demand_empty_rest_of_line (); | |
4978 | } | |
4979 | ||
4980 | /* The .ef pseudo-op. This is just like a COFF C_FCN symbol named | |
4981 | ".ef", except that the line number is absolute, not relative to the | |
4982 | most recent ".bf" symbol. */ | |
4983 | ||
4984 | static void | |
98027b10 | 4985 | ppc_ef (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4986 | { |
4987 | symbolS *sym; | |
4988 | ||
4989 | sym = symbol_make (".ef"); | |
4990 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 4991 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
4992 | S_SET_VALUE (sym, frag_now_fix ()); |
4993 | S_SET_STORAGE_CLASS (sym, C_FCN); | |
4994 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
4995 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
809ffe0d | 4996 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
4997 | |
4998 | ppc_frob_label (sym); | |
4999 | ||
5000 | demand_empty_rest_of_line (); | |
5001 | } | |
5002 | ||
5003 | /* The .bi and .ei pseudo-ops. These take a string argument and | |
5004 | generates a C_BINCL or C_EINCL symbol, which goes at the start of | |
8642cce8 TR |
5005 | the symbol list. The value of .bi will be know when the next .bf |
5006 | is encountered. */ | |
252b5132 RH |
5007 | |
5008 | static void | |
98027b10 | 5009 | ppc_biei (int ei) |
252b5132 RH |
5010 | { |
5011 | static symbolS *last_biei; | |
5012 | ||
5013 | char *name; | |
5014 | int len; | |
5015 | symbolS *sym; | |
5016 | symbolS *look; | |
5017 | ||
5018 | name = demand_copy_C_string (&len); | |
5019 | ||
5020 | /* The value of these symbols is actually file offset. Here we set | |
5021 | the value to the index into the line number entries. In | |
5022 | ppc_frob_symbols we set the fix_line field, which will cause BFD | |
5023 | to do the right thing. */ | |
5024 | ||
5025 | sym = symbol_make (name); | |
5026 | /* obj-coff.c currently only handles line numbers correctly in the | |
5027 | .text section. */ | |
5028 | S_SET_SEGMENT (sym, text_section); | |
5029 | S_SET_VALUE (sym, coff_n_line_nos); | |
809ffe0d | 5030 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5031 | |
5032 | S_SET_STORAGE_CLASS (sym, ei ? C_EINCL : C_BINCL); | |
809ffe0d | 5033 | symbol_get_tc (sym)->output = 1; |
81d4177b | 5034 | |
8642cce8 | 5035 | /* Save bi. */ |
5d6255fe | 5036 | if (ei) |
8642cce8 TR |
5037 | saved_bi_sym = 0; |
5038 | else | |
5039 | saved_bi_sym = sym; | |
5040 | ||
252b5132 RH |
5041 | for (look = last_biei ? last_biei : symbol_rootP; |
5042 | (look != (symbolS *) NULL | |
5043 | && (S_GET_STORAGE_CLASS (look) == C_FILE | |
5044 | || S_GET_STORAGE_CLASS (look) == C_BINCL | |
5045 | || S_GET_STORAGE_CLASS (look) == C_EINCL)); | |
5046 | look = symbol_next (look)) | |
5047 | ; | |
5048 | if (look != (symbolS *) NULL) | |
5049 | { | |
5050 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
5051 | symbol_insert (sym, look, &symbol_rootP, &symbol_lastP); | |
5052 | last_biei = sym; | |
5053 | } | |
5054 | ||
5055 | demand_empty_rest_of_line (); | |
5056 | } | |
5057 | ||
5058 | /* The .bs pseudo-op. This generates a C_BSTAT symbol named ".bs". | |
5059 | There is one argument, which is a csect symbol. The value of the | |
5060 | .bs symbol is the index of this csect symbol. */ | |
5061 | ||
5062 | static void | |
98027b10 | 5063 | ppc_bs (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5064 | { |
5065 | char *name; | |
5066 | char endc; | |
5067 | symbolS *csect; | |
5068 | symbolS *sym; | |
5069 | ||
5070 | if (ppc_current_block != NULL) | |
5071 | as_bad (_("nested .bs blocks")); | |
5072 | ||
d02603dc | 5073 | endc = get_symbol_name (&name); |
252b5132 RH |
5074 | |
5075 | csect = symbol_find_or_make (name); | |
5076 | ||
d02603dc | 5077 | (void) restore_line_pointer (endc); |
252b5132 RH |
5078 | |
5079 | sym = symbol_make (".bs"); | |
5080 | S_SET_SEGMENT (sym, now_seg); | |
5081 | S_SET_STORAGE_CLASS (sym, C_BSTAT); | |
809ffe0d ILT |
5082 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
5083 | symbol_get_tc (sym)->output = 1; | |
252b5132 | 5084 | |
809ffe0d | 5085 | symbol_get_tc (sym)->within = csect; |
252b5132 RH |
5086 | |
5087 | ppc_frob_label (sym); | |
5088 | ||
5089 | ppc_current_block = sym; | |
5090 | ||
5091 | demand_empty_rest_of_line (); | |
5092 | } | |
5093 | ||
5094 | /* The .es pseudo-op. Generate a C_ESTART symbol named .es. */ | |
5095 | ||
5096 | static void | |
98027b10 | 5097 | ppc_es (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5098 | { |
5099 | symbolS *sym; | |
5100 | ||
5101 | if (ppc_current_block == NULL) | |
5102 | as_bad (_(".es without preceding .bs")); | |
5103 | ||
5104 | sym = symbol_make (".es"); | |
5105 | S_SET_SEGMENT (sym, now_seg); | |
5106 | S_SET_STORAGE_CLASS (sym, C_ESTAT); | |
809ffe0d ILT |
5107 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
5108 | symbol_get_tc (sym)->output = 1; | |
252b5132 RH |
5109 | |
5110 | ppc_frob_label (sym); | |
5111 | ||
5112 | ppc_current_block = NULL; | |
5113 | ||
5114 | demand_empty_rest_of_line (); | |
5115 | } | |
5116 | ||
5117 | /* The .bb pseudo-op. Generate a C_BLOCK symbol named .bb, with a | |
5118 | line number. */ | |
5119 | ||
5120 | static void | |
98027b10 | 5121 | ppc_bb (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5122 | { |
5123 | symbolS *sym; | |
5124 | ||
5125 | sym = symbol_make (".bb"); | |
5126 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5127 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5128 | S_SET_VALUE (sym, frag_now_fix ()); |
5129 | S_SET_STORAGE_CLASS (sym, C_BLOCK); | |
5130 | ||
5131 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5132 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
5133 | ||
809ffe0d | 5134 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5135 | |
5136 | SF_SET_PROCESS (sym); | |
5137 | ||
5138 | ppc_frob_label (sym); | |
5139 | ||
5140 | demand_empty_rest_of_line (); | |
5141 | } | |
5142 | ||
5143 | /* The .eb pseudo-op. Generate a C_BLOCK symbol named .eb, with a | |
5144 | line number. */ | |
5145 | ||
5146 | static void | |
98027b10 | 5147 | ppc_eb (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5148 | { |
5149 | symbolS *sym; | |
5150 | ||
5151 | sym = symbol_make (".eb"); | |
5152 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5153 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5154 | S_SET_VALUE (sym, frag_now_fix ()); |
5155 | S_SET_STORAGE_CLASS (sym, C_BLOCK); | |
5156 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5157 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
809ffe0d | 5158 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5159 | |
5160 | SF_SET_PROCESS (sym); | |
5161 | ||
5162 | ppc_frob_label (sym); | |
5163 | ||
5164 | demand_empty_rest_of_line (); | |
5165 | } | |
5166 | ||
5167 | /* The .bc pseudo-op. This just creates a C_BCOMM symbol with a | |
5168 | specified name. */ | |
5169 | ||
5170 | static void | |
98027b10 | 5171 | ppc_bc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5172 | { |
5173 | char *name; | |
5174 | int len; | |
5175 | symbolS *sym; | |
5176 | ||
5177 | name = demand_copy_C_string (&len); | |
5178 | sym = symbol_make (name); | |
5179 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5180 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5181 | S_SET_STORAGE_CLASS (sym, C_BCOMM); |
5182 | S_SET_VALUE (sym, 0); | |
809ffe0d | 5183 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5184 | |
5185 | ppc_frob_label (sym); | |
5186 | ||
5187 | demand_empty_rest_of_line (); | |
5188 | } | |
5189 | ||
5190 | /* The .ec pseudo-op. This just creates a C_ECOMM symbol. */ | |
5191 | ||
5192 | static void | |
98027b10 | 5193 | ppc_ec (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5194 | { |
5195 | symbolS *sym; | |
5196 | ||
5197 | sym = symbol_make (".ec"); | |
5198 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5199 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5200 | S_SET_STORAGE_CLASS (sym, C_ECOMM); |
5201 | S_SET_VALUE (sym, 0); | |
809ffe0d | 5202 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5203 | |
5204 | ppc_frob_label (sym); | |
5205 | ||
5206 | demand_empty_rest_of_line (); | |
5207 | } | |
5208 | ||
5209 | /* The .toc pseudo-op. Switch to the .toc subsegment. */ | |
5210 | ||
5211 | static void | |
98027b10 | 5212 | ppc_toc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5213 | { |
5214 | if (ppc_toc_csect != (symbolS *) NULL) | |
809ffe0d | 5215 | subseg_set (data_section, symbol_get_tc (ppc_toc_csect)->subseg); |
252b5132 RH |
5216 | else |
5217 | { | |
5218 | subsegT subseg; | |
5219 | symbolS *sym; | |
5220 | symbolS *list; | |
81d4177b | 5221 | |
252b5132 RH |
5222 | subseg = ppc_data_subsegment; |
5223 | ++ppc_data_subsegment; | |
5224 | ||
5225 | subseg_new (segment_name (data_section), subseg); | |
5226 | ppc_toc_frag = frag_now; | |
5227 | ||
5228 | sym = symbol_find_or_make ("TOC[TC0]"); | |
809ffe0d | 5229 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5230 | S_SET_SEGMENT (sym, data_section); |
5231 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
809ffe0d ILT |
5232 | symbol_get_tc (sym)->subseg = subseg; |
5233 | symbol_get_tc (sym)->output = 1; | |
5234 | symbol_get_tc (sym)->within = sym; | |
252b5132 RH |
5235 | |
5236 | ppc_toc_csect = sym; | |
81d4177b | 5237 | |
252b5132 | 5238 | for (list = ppc_data_csects; |
809ffe0d ILT |
5239 | symbol_get_tc (list)->next != (symbolS *) NULL; |
5240 | list = symbol_get_tc (list)->next) | |
252b5132 | 5241 | ; |
809ffe0d | 5242 | symbol_get_tc (list)->next = sym; |
252b5132 RH |
5243 | |
5244 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
809ffe0d ILT |
5245 | symbol_append (sym, symbol_get_tc (list)->within, &symbol_rootP, |
5246 | &symbol_lastP); | |
252b5132 RH |
5247 | } |
5248 | ||
5249 | ppc_current_csect = ppc_toc_csect; | |
5250 | ||
5251 | demand_empty_rest_of_line (); | |
5252 | } | |
5253 | ||
5254 | /* The AIX assembler automatically aligns the operands of a .long or | |
5255 | .short pseudo-op, and we want to be compatible. */ | |
5256 | ||
5257 | static void | |
98027b10 | 5258 | ppc_xcoff_cons (int log_size) |
252b5132 RH |
5259 | { |
5260 | frag_align (log_size, 0, 0); | |
5261 | record_alignment (now_seg, log_size); | |
5262 | cons (1 << log_size); | |
5263 | } | |
5264 | ||
5265 | static void | |
98027b10 | 5266 | ppc_vbyte (int dummy ATTRIBUTE_UNUSED) |
252b5132 RH |
5267 | { |
5268 | expressionS exp; | |
5269 | int byte_count; | |
5270 | ||
5271 | (void) expression (&exp); | |
5272 | ||
5273 | if (exp.X_op != O_constant) | |
5274 | { | |
5275 | as_bad (_("non-constant byte count")); | |
5276 | return; | |
5277 | } | |
5278 | ||
5279 | byte_count = exp.X_add_number; | |
5280 | ||
5281 | if (*input_line_pointer != ',') | |
5282 | { | |
5283 | as_bad (_("missing value")); | |
5284 | return; | |
5285 | } | |
5286 | ||
5287 | ++input_line_pointer; | |
5288 | cons (byte_count); | |
5289 | } | |
5290 | ||
85645aed TG |
5291 | void |
5292 | ppc_xcoff_end (void) | |
5293 | { | |
5294 | int i; | |
5295 | ||
5296 | for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++) | |
5297 | { | |
5298 | struct dw_section *dws = &dw_sections[i]; | |
5299 | struct dw_subsection *dwss; | |
5300 | ||
5301 | if (dws->anon_subseg) | |
5302 | { | |
5303 | dwss = dws->anon_subseg; | |
5304 | dwss->link = dws->list_subseg; | |
5305 | } | |
5306 | else | |
5307 | dwss = dws->list_subseg; | |
5308 | ||
5309 | for (; dwss != NULL; dwss = dwss->link) | |
5310 | if (dwss->end_exp.X_add_symbol != NULL) | |
5311 | { | |
5312 | subseg_set (dws->sect, dwss->subseg); | |
5313 | symbol_set_value_now (dwss->end_exp.X_add_symbol); | |
5314 | } | |
5315 | } | |
22f72c48 | 5316 | ppc_cpu = 0; |
85645aed TG |
5317 | } |
5318 | ||
252b5132 | 5319 | #endif /* OBJ_XCOFF */ |
0baf16f2 | 5320 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
252b5132 RH |
5321 | \f |
5322 | /* The .tc pseudo-op. This is used when generating either XCOFF or | |
5323 | ELF. This takes two or more arguments. | |
5324 | ||
5325 | When generating XCOFF output, the first argument is the name to | |
5326 | give to this location in the toc; this will be a symbol with class | |
0baf16f2 | 5327 | TC. The rest of the arguments are N-byte values to actually put at |
252b5132 | 5328 | this location in the TOC; often there is just one more argument, a |
1049f94e | 5329 | relocatable symbol reference. The size of the value to store |
0baf16f2 AM |
5330 | depends on target word size. A 32-bit target uses 4-byte values, a |
5331 | 64-bit target uses 8-byte values. | |
252b5132 RH |
5332 | |
5333 | When not generating XCOFF output, the arguments are the same, but | |
5334 | the first argument is simply ignored. */ | |
5335 | ||
5336 | static void | |
98027b10 | 5337 | ppc_tc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5338 | { |
5339 | #ifdef OBJ_XCOFF | |
5340 | ||
5341 | /* Define the TOC symbol name. */ | |
5342 | { | |
5343 | char *name; | |
5344 | char endc; | |
5345 | symbolS *sym; | |
5346 | ||
5347 | if (ppc_toc_csect == (symbolS *) NULL | |
5348 | || ppc_toc_csect != ppc_current_csect) | |
5349 | { | |
5350 | as_bad (_(".tc not in .toc section")); | |
5351 | ignore_rest_of_line (); | |
5352 | return; | |
5353 | } | |
5354 | ||
d02603dc | 5355 | endc = get_symbol_name (&name); |
252b5132 RH |
5356 | |
5357 | sym = symbol_find_or_make (name); | |
5358 | ||
d02603dc | 5359 | (void) restore_line_pointer (endc); |
252b5132 RH |
5360 | |
5361 | if (S_IS_DEFINED (sym)) | |
5362 | { | |
5363 | symbolS *label; | |
5364 | ||
809ffe0d | 5365 | label = symbol_get_tc (ppc_current_csect)->within; |
96d56e9f | 5366 | if (symbol_get_tc (label)->symbol_class != XMC_TC0) |
252b5132 RH |
5367 | { |
5368 | as_bad (_(".tc with no label")); | |
5369 | ignore_rest_of_line (); | |
5370 | return; | |
5371 | } | |
5372 | ||
5373 | S_SET_SEGMENT (label, S_GET_SEGMENT (sym)); | |
809ffe0d | 5374 | symbol_set_frag (label, symbol_get_frag (sym)); |
252b5132 RH |
5375 | S_SET_VALUE (label, S_GET_VALUE (sym)); |
5376 | ||
5377 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
5378 | ++input_line_pointer; | |
5379 | ||
5380 | return; | |
5381 | } | |
5382 | ||
5383 | S_SET_SEGMENT (sym, now_seg); | |
809ffe0d | 5384 | symbol_set_frag (sym, frag_now); |
252b5132 | 5385 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); |
96d56e9f | 5386 | symbol_get_tc (sym)->symbol_class = XMC_TC; |
809ffe0d | 5387 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5388 | |
5389 | ppc_frob_label (sym); | |
5390 | } | |
5391 | ||
0baf16f2 AM |
5392 | #endif /* OBJ_XCOFF */ |
5393 | #ifdef OBJ_ELF | |
9c7977b3 | 5394 | int align; |
252b5132 RH |
5395 | |
5396 | /* Skip the TOC symbol name. */ | |
5397 | while (is_part_of_name (*input_line_pointer) | |
d13d4015 | 5398 | || *input_line_pointer == ' ' |
252b5132 RH |
5399 | || *input_line_pointer == '[' |
5400 | || *input_line_pointer == ']' | |
5401 | || *input_line_pointer == '{' | |
5402 | || *input_line_pointer == '}') | |
5403 | ++input_line_pointer; | |
5404 | ||
0baf16f2 | 5405 | /* Align to a four/eight byte boundary. */ |
2b3c4602 | 5406 | align = ppc_obj64 ? 3 : 2; |
9c7977b3 AM |
5407 | frag_align (align, 0, 0); |
5408 | record_alignment (now_seg, align); | |
0baf16f2 | 5409 | #endif /* OBJ_ELF */ |
252b5132 RH |
5410 | |
5411 | if (*input_line_pointer != ',') | |
5412 | demand_empty_rest_of_line (); | |
5413 | else | |
5414 | { | |
5415 | ++input_line_pointer; | |
2b3c4602 | 5416 | cons (ppc_obj64 ? 8 : 4); |
252b5132 RH |
5417 | } |
5418 | } | |
0baf16f2 AM |
5419 | |
5420 | /* Pseudo-op .machine. */ | |
0baf16f2 AM |
5421 | |
5422 | static void | |
98027b10 | 5423 | ppc_machine (int ignore ATTRIBUTE_UNUSED) |
0baf16f2 | 5424 | { |
d02603dc | 5425 | char c; |
69c040df AM |
5426 | char *cpu_string; |
5427 | #define MAX_HISTORY 100 | |
fa452fa6 | 5428 | static ppc_cpu_t *cpu_history; |
69c040df AM |
5429 | static int curr_hist; |
5430 | ||
5431 | SKIP_WHITESPACE (); | |
5432 | ||
d02603dc NC |
5433 | c = get_symbol_name (&cpu_string); |
5434 | cpu_string = xstrdup (cpu_string); | |
5435 | (void) restore_line_pointer (c); | |
69c040df AM |
5436 | |
5437 | if (cpu_string != NULL) | |
5438 | { | |
fa452fa6 | 5439 | ppc_cpu_t old_cpu = ppc_cpu; |
69fe9ce5 | 5440 | ppc_cpu_t new_cpu; |
69c040df AM |
5441 | char *p; |
5442 | ||
5443 | for (p = cpu_string; *p != 0; p++) | |
5444 | *p = TOLOWER (*p); | |
5445 | ||
5446 | if (strcmp (cpu_string, "push") == 0) | |
5447 | { | |
5448 | if (cpu_history == NULL) | |
325801bd | 5449 | cpu_history = XNEWVEC (ppc_cpu_t, MAX_HISTORY); |
69c040df AM |
5450 | |
5451 | if (curr_hist >= MAX_HISTORY) | |
5452 | as_bad (_(".machine stack overflow")); | |
5453 | else | |
5454 | cpu_history[curr_hist++] = ppc_cpu; | |
5455 | } | |
5456 | else if (strcmp (cpu_string, "pop") == 0) | |
5457 | { | |
5458 | if (curr_hist <= 0) | |
5459 | as_bad (_(".machine stack underflow")); | |
5460 | else | |
5461 | ppc_cpu = cpu_history[--curr_hist]; | |
5462 | } | |
776fc418 | 5463 | else if ((new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, cpu_string)) != 0) |
69fe9ce5 | 5464 | ppc_cpu = new_cpu; |
69c040df AM |
5465 | else |
5466 | as_bad (_("invalid machine `%s'"), cpu_string); | |
5467 | ||
5468 | if (ppc_cpu != old_cpu) | |
5469 | ppc_setup_opcodes (); | |
5470 | } | |
5471 | ||
5472 | demand_empty_rest_of_line (); | |
0baf16f2 | 5473 | } |
0baf16f2 | 5474 | #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */ |
252b5132 | 5475 | \f |
252b5132 RH |
5476 | #ifdef OBJ_XCOFF |
5477 | ||
5478 | /* XCOFF specific symbol and file handling. */ | |
5479 | ||
5480 | /* Canonicalize the symbol name. We use the to force the suffix, if | |
5481 | any, to use square brackets, and to be in upper case. */ | |
5482 | ||
5483 | char * | |
98027b10 | 5484 | ppc_canonicalize_symbol_name (char *name) |
252b5132 RH |
5485 | { |
5486 | char *s; | |
5487 | ||
5488 | if (ppc_stab_symbol) | |
5489 | return name; | |
5490 | ||
5491 | for (s = name; *s != '\0' && *s != '{' && *s != '['; s++) | |
5492 | ; | |
5493 | if (*s != '\0') | |
5494 | { | |
5495 | char brac; | |
5496 | ||
5497 | if (*s == '[') | |
5498 | brac = ']'; | |
5499 | else | |
5500 | { | |
5501 | *s = '['; | |
5502 | brac = '}'; | |
5503 | } | |
5504 | ||
5505 | for (s++; *s != '\0' && *s != brac; s++) | |
3882b010 | 5506 | *s = TOUPPER (*s); |
252b5132 RH |
5507 | |
5508 | if (*s == '\0' || s[1] != '\0') | |
5509 | as_bad (_("bad symbol suffix")); | |
5510 | ||
5511 | *s = ']'; | |
5512 | } | |
5513 | ||
5514 | return name; | |
5515 | } | |
5516 | ||
5517 | /* Set the class of a symbol based on the suffix, if any. This is | |
5518 | called whenever a new symbol is created. */ | |
5519 | ||
5520 | void | |
98027b10 | 5521 | ppc_symbol_new_hook (symbolS *sym) |
252b5132 | 5522 | { |
809ffe0d | 5523 | struct ppc_tc_sy *tc; |
252b5132 RH |
5524 | const char *s; |
5525 | ||
809ffe0d ILT |
5526 | tc = symbol_get_tc (sym); |
5527 | tc->next = NULL; | |
5528 | tc->output = 0; | |
96d56e9f | 5529 | tc->symbol_class = -1; |
809ffe0d ILT |
5530 | tc->real_name = NULL; |
5531 | tc->subseg = 0; | |
5532 | tc->align = 0; | |
85645aed TG |
5533 | tc->u.size = NULL; |
5534 | tc->u.dw = NULL; | |
809ffe0d | 5535 | tc->within = NULL; |
252b5132 RH |
5536 | |
5537 | if (ppc_stab_symbol) | |
5538 | return; | |
5539 | ||
5540 | s = strchr (S_GET_NAME (sym), '['); | |
5541 | if (s == (const char *) NULL) | |
5542 | { | |
5543 | /* There is no suffix. */ | |
5544 | return; | |
5545 | } | |
5546 | ||
5547 | ++s; | |
5548 | ||
5549 | switch (s[0]) | |
5550 | { | |
5551 | case 'B': | |
5552 | if (strcmp (s, "BS]") == 0) | |
96d56e9f | 5553 | tc->symbol_class = XMC_BS; |
252b5132 RH |
5554 | break; |
5555 | case 'D': | |
5556 | if (strcmp (s, "DB]") == 0) | |
96d56e9f | 5557 | tc->symbol_class = XMC_DB; |
252b5132 | 5558 | else if (strcmp (s, "DS]") == 0) |
96d56e9f | 5559 | tc->symbol_class = XMC_DS; |
252b5132 RH |
5560 | break; |
5561 | case 'G': | |
5562 | if (strcmp (s, "GL]") == 0) | |
96d56e9f | 5563 | tc->symbol_class = XMC_GL; |
252b5132 RH |
5564 | break; |
5565 | case 'P': | |
5566 | if (strcmp (s, "PR]") == 0) | |
96d56e9f | 5567 | tc->symbol_class = XMC_PR; |
252b5132 RH |
5568 | break; |
5569 | case 'R': | |
5570 | if (strcmp (s, "RO]") == 0) | |
96d56e9f | 5571 | tc->symbol_class = XMC_RO; |
252b5132 | 5572 | else if (strcmp (s, "RW]") == 0) |
96d56e9f | 5573 | tc->symbol_class = XMC_RW; |
252b5132 RH |
5574 | break; |
5575 | case 'S': | |
5576 | if (strcmp (s, "SV]") == 0) | |
96d56e9f | 5577 | tc->symbol_class = XMC_SV; |
252b5132 RH |
5578 | break; |
5579 | case 'T': | |
5580 | if (strcmp (s, "TC]") == 0) | |
96d56e9f | 5581 | tc->symbol_class = XMC_TC; |
252b5132 | 5582 | else if (strcmp (s, "TI]") == 0) |
96d56e9f | 5583 | tc->symbol_class = XMC_TI; |
252b5132 | 5584 | else if (strcmp (s, "TB]") == 0) |
96d56e9f | 5585 | tc->symbol_class = XMC_TB; |
252b5132 | 5586 | else if (strcmp (s, "TC0]") == 0 || strcmp (s, "T0]") == 0) |
96d56e9f | 5587 | tc->symbol_class = XMC_TC0; |
252b5132 RH |
5588 | break; |
5589 | case 'U': | |
5590 | if (strcmp (s, "UA]") == 0) | |
96d56e9f | 5591 | tc->symbol_class = XMC_UA; |
252b5132 | 5592 | else if (strcmp (s, "UC]") == 0) |
96d56e9f | 5593 | tc->symbol_class = XMC_UC; |
252b5132 RH |
5594 | break; |
5595 | case 'X': | |
5596 | if (strcmp (s, "XO]") == 0) | |
96d56e9f | 5597 | tc->symbol_class = XMC_XO; |
252b5132 RH |
5598 | break; |
5599 | } | |
5600 | ||
96d56e9f | 5601 | if (tc->symbol_class == -1) |
d6ed37ed | 5602 | as_bad (_("unrecognized symbol suffix")); |
252b5132 RH |
5603 | } |
5604 | ||
252b5132 RH |
5605 | /* This variable is set by ppc_frob_symbol if any absolute symbols are |
5606 | seen. It tells ppc_adjust_symtab whether it needs to look through | |
5607 | the symbols. */ | |
5608 | ||
b34976b6 | 5609 | static bfd_boolean ppc_saw_abs; |
252b5132 RH |
5610 | |
5611 | /* Change the name of a symbol just before writing it out. Set the | |
5612 | real name if the .rename pseudo-op was used. Otherwise, remove any | |
5613 | class suffix. Return 1 if the symbol should not be included in the | |
5614 | symbol table. */ | |
5615 | ||
5616 | int | |
98027b10 | 5617 | ppc_frob_symbol (symbolS *sym) |
252b5132 RH |
5618 | { |
5619 | static symbolS *ppc_last_function; | |
5620 | static symbolS *set_end; | |
5621 | ||
5622 | /* Discard symbols that should not be included in the output symbol | |
5623 | table. */ | |
809ffe0d ILT |
5624 | if (! symbol_used_in_reloc_p (sym) |
5625 | && ((symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) != 0 | |
670ec21d | 5626 | || (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym)) |
809ffe0d | 5627 | && ! symbol_get_tc (sym)->output |
252b5132 RH |
5628 | && S_GET_STORAGE_CLASS (sym) != C_FILE))) |
5629 | return 1; | |
5630 | ||
a161fe53 AM |
5631 | /* This one will disappear anyway. Don't make a csect sym for it. */ |
5632 | if (sym == abs_section_sym) | |
5633 | return 1; | |
5634 | ||
809ffe0d ILT |
5635 | if (symbol_get_tc (sym)->real_name != (char *) NULL) |
5636 | S_SET_NAME (sym, symbol_get_tc (sym)->real_name); | |
252b5132 RH |
5637 | else |
5638 | { | |
5639 | const char *name; | |
5640 | const char *s; | |
5641 | ||
5642 | name = S_GET_NAME (sym); | |
5643 | s = strchr (name, '['); | |
5644 | if (s != (char *) NULL) | |
5645 | { | |
5646 | unsigned int len; | |
5647 | char *snew; | |
5648 | ||
5649 | len = s - name; | |
a44e2901 | 5650 | snew = xstrndup (name, len); |
252b5132 RH |
5651 | |
5652 | S_SET_NAME (sym, snew); | |
5653 | } | |
5654 | } | |
5655 | ||
5656 | if (set_end != (symbolS *) NULL) | |
5657 | { | |
5658 | SA_SET_SYM_ENDNDX (set_end, sym); | |
5659 | set_end = NULL; | |
5660 | } | |
5661 | ||
5662 | if (SF_GET_FUNCTION (sym)) | |
5663 | { | |
5664 | if (ppc_last_function != (symbolS *) NULL) | |
5665 | as_bad (_("two .function pseudo-ops with no intervening .ef")); | |
5666 | ppc_last_function = sym; | |
85645aed | 5667 | if (symbol_get_tc (sym)->u.size != (symbolS *) NULL) |
252b5132 | 5668 | { |
85645aed | 5669 | resolve_symbol_value (symbol_get_tc (sym)->u.size); |
809ffe0d | 5670 | SA_SET_SYM_FSIZE (sym, |
85645aed | 5671 | (long) S_GET_VALUE (symbol_get_tc (sym)->u.size)); |
252b5132 RH |
5672 | } |
5673 | } | |
5674 | else if (S_GET_STORAGE_CLASS (sym) == C_FCN | |
5675 | && strcmp (S_GET_NAME (sym), ".ef") == 0) | |
5676 | { | |
5677 | if (ppc_last_function == (symbolS *) NULL) | |
5678 | as_bad (_(".ef with no preceding .function")); | |
5679 | else | |
5680 | { | |
5681 | set_end = ppc_last_function; | |
5682 | ppc_last_function = NULL; | |
5683 | ||
5684 | /* We don't have a C_EFCN symbol, but we need to force the | |
5685 | COFF backend to believe that it has seen one. */ | |
5686 | coff_last_function = NULL; | |
5687 | } | |
5688 | } | |
5689 | ||
670ec21d | 5690 | if (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym)) |
809ffe0d | 5691 | && (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) == 0 |
252b5132 RH |
5692 | && S_GET_STORAGE_CLASS (sym) != C_FILE |
5693 | && S_GET_STORAGE_CLASS (sym) != C_FCN | |
5694 | && S_GET_STORAGE_CLASS (sym) != C_BLOCK | |
5695 | && S_GET_STORAGE_CLASS (sym) != C_BSTAT | |
5696 | && S_GET_STORAGE_CLASS (sym) != C_ESTAT | |
5697 | && S_GET_STORAGE_CLASS (sym) != C_BINCL | |
5698 | && S_GET_STORAGE_CLASS (sym) != C_EINCL | |
5699 | && S_GET_SEGMENT (sym) != ppc_coff_debug_section) | |
5700 | S_SET_STORAGE_CLASS (sym, C_HIDEXT); | |
5701 | ||
5702 | if (S_GET_STORAGE_CLASS (sym) == C_EXT | |
8602d4fe | 5703 | || S_GET_STORAGE_CLASS (sym) == C_AIX_WEAKEXT |
252b5132 RH |
5704 | || S_GET_STORAGE_CLASS (sym) == C_HIDEXT) |
5705 | { | |
5706 | int i; | |
5707 | union internal_auxent *a; | |
5708 | ||
5709 | /* Create a csect aux. */ | |
5710 | i = S_GET_NUMBER_AUXILIARY (sym); | |
5711 | S_SET_NUMBER_AUXILIARY (sym, i + 1); | |
809ffe0d | 5712 | a = &coffsymbol (symbol_get_bfdsym (sym))->native[i + 1].u.auxent; |
96d56e9f | 5713 | if (symbol_get_tc (sym)->symbol_class == XMC_TC0) |
252b5132 RH |
5714 | { |
5715 | /* This is the TOC table. */ | |
5716 | know (strcmp (S_GET_NAME (sym), "TOC") == 0); | |
5717 | a->x_csect.x_scnlen.l = 0; | |
5718 | a->x_csect.x_smtyp = (2 << 3) | XTY_SD; | |
5719 | } | |
809ffe0d | 5720 | else if (symbol_get_tc (sym)->subseg != 0) |
252b5132 RH |
5721 | { |
5722 | /* This is a csect symbol. x_scnlen is the size of the | |
5723 | csect. */ | |
809ffe0d | 5724 | if (symbol_get_tc (sym)->next == (symbolS *) NULL) |
fd361982 | 5725 | a->x_csect.x_scnlen.l = (bfd_section_size (S_GET_SEGMENT (sym)) |
252b5132 RH |
5726 | - S_GET_VALUE (sym)); |
5727 | else | |
5728 | { | |
6386f3a7 | 5729 | resolve_symbol_value (symbol_get_tc (sym)->next); |
809ffe0d | 5730 | a->x_csect.x_scnlen.l = (S_GET_VALUE (symbol_get_tc (sym)->next) |
252b5132 RH |
5731 | - S_GET_VALUE (sym)); |
5732 | } | |
809ffe0d | 5733 | a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_SD; |
252b5132 RH |
5734 | } |
5735 | else if (S_GET_SEGMENT (sym) == bss_section) | |
5736 | { | |
5737 | /* This is a common symbol. */ | |
809ffe0d ILT |
5738 | a->x_csect.x_scnlen.l = symbol_get_frag (sym)->fr_offset; |
5739 | a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_CM; | |
252b5132 | 5740 | if (S_IS_EXTERNAL (sym)) |
96d56e9f | 5741 | symbol_get_tc (sym)->symbol_class = XMC_RW; |
252b5132 | 5742 | else |
96d56e9f | 5743 | symbol_get_tc (sym)->symbol_class = XMC_BS; |
252b5132 RH |
5744 | } |
5745 | else if (S_GET_SEGMENT (sym) == absolute_section) | |
5746 | { | |
5747 | /* This is an absolute symbol. The csect will be created by | |
99a814a1 | 5748 | ppc_adjust_symtab. */ |
b34976b6 | 5749 | ppc_saw_abs = TRUE; |
252b5132 | 5750 | a->x_csect.x_smtyp = XTY_LD; |
96d56e9f NC |
5751 | if (symbol_get_tc (sym)->symbol_class == -1) |
5752 | symbol_get_tc (sym)->symbol_class = XMC_XO; | |
252b5132 RH |
5753 | } |
5754 | else if (! S_IS_DEFINED (sym)) | |
5755 | { | |
5756 | /* This is an external symbol. */ | |
5757 | a->x_csect.x_scnlen.l = 0; | |
5758 | a->x_csect.x_smtyp = XTY_ER; | |
5759 | } | |
96d56e9f | 5760 | else if (symbol_get_tc (sym)->symbol_class == XMC_TC) |
252b5132 RH |
5761 | { |
5762 | symbolS *next; | |
5763 | ||
5764 | /* This is a TOC definition. x_scnlen is the size of the | |
5765 | TOC entry. */ | |
5766 | next = symbol_next (sym); | |
96d56e9f | 5767 | while (symbol_get_tc (next)->symbol_class == XMC_TC0) |
252b5132 RH |
5768 | next = symbol_next (next); |
5769 | if (next == (symbolS *) NULL | |
96d56e9f | 5770 | || symbol_get_tc (next)->symbol_class != XMC_TC) |
252b5132 RH |
5771 | { |
5772 | if (ppc_after_toc_frag == (fragS *) NULL) | |
fd361982 | 5773 | a->x_csect.x_scnlen.l = (bfd_section_size (data_section) |
252b5132 RH |
5774 | - S_GET_VALUE (sym)); |
5775 | else | |
5776 | a->x_csect.x_scnlen.l = (ppc_after_toc_frag->fr_address | |
5777 | - S_GET_VALUE (sym)); | |
5778 | } | |
5779 | else | |
5780 | { | |
6386f3a7 | 5781 | resolve_symbol_value (next); |
252b5132 RH |
5782 | a->x_csect.x_scnlen.l = (S_GET_VALUE (next) |
5783 | - S_GET_VALUE (sym)); | |
5784 | } | |
5785 | a->x_csect.x_smtyp = (2 << 3) | XTY_SD; | |
5786 | } | |
5787 | else | |
5788 | { | |
5789 | symbolS *csect; | |
5790 | ||
5791 | /* This is a normal symbol definition. x_scnlen is the | |
5792 | symbol index of the containing csect. */ | |
5793 | if (S_GET_SEGMENT (sym) == text_section) | |
5794 | csect = ppc_text_csects; | |
5795 | else if (S_GET_SEGMENT (sym) == data_section) | |
5796 | csect = ppc_data_csects; | |
5797 | else | |
5798 | abort (); | |
5799 | ||
5800 | /* Skip the initial dummy symbol. */ | |
809ffe0d | 5801 | csect = symbol_get_tc (csect)->next; |
252b5132 RH |
5802 | |
5803 | if (csect == (symbolS *) NULL) | |
5804 | { | |
5805 | as_warn (_("warning: symbol %s has no csect"), S_GET_NAME (sym)); | |
5806 | a->x_csect.x_scnlen.l = 0; | |
5807 | } | |
5808 | else | |
5809 | { | |
809ffe0d | 5810 | while (symbol_get_tc (csect)->next != (symbolS *) NULL) |
252b5132 | 5811 | { |
6386f3a7 | 5812 | resolve_symbol_value (symbol_get_tc (csect)->next); |
809ffe0d ILT |
5813 | if (S_GET_VALUE (symbol_get_tc (csect)->next) |
5814 | > S_GET_VALUE (sym)) | |
252b5132 | 5815 | break; |
809ffe0d | 5816 | csect = symbol_get_tc (csect)->next; |
252b5132 RH |
5817 | } |
5818 | ||
809ffe0d ILT |
5819 | a->x_csect.x_scnlen.p = |
5820 | coffsymbol (symbol_get_bfdsym (csect))->native; | |
5821 | coffsymbol (symbol_get_bfdsym (sym))->native[i + 1].fix_scnlen = | |
5822 | 1; | |
252b5132 RH |
5823 | } |
5824 | a->x_csect.x_smtyp = XTY_LD; | |
5825 | } | |
81d4177b | 5826 | |
252b5132 RH |
5827 | a->x_csect.x_parmhash = 0; |
5828 | a->x_csect.x_snhash = 0; | |
96d56e9f | 5829 | if (symbol_get_tc (sym)->symbol_class == -1) |
252b5132 RH |
5830 | a->x_csect.x_smclas = XMC_PR; |
5831 | else | |
96d56e9f | 5832 | a->x_csect.x_smclas = symbol_get_tc (sym)->symbol_class; |
252b5132 RH |
5833 | a->x_csect.x_stab = 0; |
5834 | a->x_csect.x_snstab = 0; | |
5835 | ||
5836 | /* Don't let the COFF backend resort these symbols. */ | |
809ffe0d | 5837 | symbol_get_bfdsym (sym)->flags |= BSF_NOT_AT_END; |
252b5132 RH |
5838 | } |
5839 | else if (S_GET_STORAGE_CLASS (sym) == C_BSTAT) | |
5840 | { | |
5841 | /* We want the value to be the symbol index of the referenced | |
5842 | csect symbol. BFD will do that for us if we set the right | |
5843 | flags. */ | |
b782de16 AM |
5844 | asymbol *bsym = symbol_get_bfdsym (symbol_get_tc (sym)->within); |
5845 | combined_entry_type *c = coffsymbol (bsym)->native; | |
5846 | ||
5847 | S_SET_VALUE (sym, (valueT) (size_t) c); | |
809ffe0d | 5848 | coffsymbol (symbol_get_bfdsym (sym))->native->fix_value = 1; |
252b5132 RH |
5849 | } |
5850 | else if (S_GET_STORAGE_CLASS (sym) == C_STSYM) | |
5851 | { | |
5852 | symbolS *block; | |
c734e7e3 | 5853 | valueT base; |
252b5132 | 5854 | |
809ffe0d | 5855 | block = symbol_get_tc (sym)->within; |
c734e7e3 TG |
5856 | if (block) |
5857 | { | |
5858 | /* The value is the offset from the enclosing csect. */ | |
5859 | symbolS *csect; | |
5860 | ||
5861 | csect = symbol_get_tc (block)->within; | |
5862 | resolve_symbol_value (csect); | |
5863 | base = S_GET_VALUE (csect); | |
5864 | } | |
5865 | else | |
5866 | base = 0; | |
5867 | ||
5868 | S_SET_VALUE (sym, S_GET_VALUE (sym) - base); | |
252b5132 RH |
5869 | } |
5870 | else if (S_GET_STORAGE_CLASS (sym) == C_BINCL | |
5871 | || S_GET_STORAGE_CLASS (sym) == C_EINCL) | |
5872 | { | |
5873 | /* We want the value to be a file offset into the line numbers. | |
99a814a1 AM |
5874 | BFD will do that for us if we set the right flags. We have |
5875 | already set the value correctly. */ | |
809ffe0d | 5876 | coffsymbol (symbol_get_bfdsym (sym))->native->fix_line = 1; |
252b5132 RH |
5877 | } |
5878 | ||
5879 | return 0; | |
5880 | } | |
5881 | ||
5882 | /* Adjust the symbol table. This creates csect symbols for all | |
5883 | absolute symbols. */ | |
5884 | ||
5885 | void | |
98027b10 | 5886 | ppc_adjust_symtab (void) |
252b5132 RH |
5887 | { |
5888 | symbolS *sym; | |
5889 | ||
5890 | if (! ppc_saw_abs) | |
5891 | return; | |
5892 | ||
5893 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) | |
5894 | { | |
5895 | symbolS *csect; | |
5896 | int i; | |
5897 | union internal_auxent *a; | |
5898 | ||
5899 | if (S_GET_SEGMENT (sym) != absolute_section) | |
5900 | continue; | |
5901 | ||
5902 | csect = symbol_create (".abs[XO]", absolute_section, | |
e01e1cee | 5903 | &zero_address_frag, S_GET_VALUE (sym)); |
809ffe0d | 5904 | symbol_get_bfdsym (csect)->value = S_GET_VALUE (sym); |
252b5132 RH |
5905 | S_SET_STORAGE_CLASS (csect, C_HIDEXT); |
5906 | i = S_GET_NUMBER_AUXILIARY (csect); | |
5907 | S_SET_NUMBER_AUXILIARY (csect, i + 1); | |
809ffe0d | 5908 | a = &coffsymbol (symbol_get_bfdsym (csect))->native[i + 1].u.auxent; |
252b5132 RH |
5909 | a->x_csect.x_scnlen.l = 0; |
5910 | a->x_csect.x_smtyp = XTY_SD; | |
5911 | a->x_csect.x_parmhash = 0; | |
5912 | a->x_csect.x_snhash = 0; | |
5913 | a->x_csect.x_smclas = XMC_XO; | |
5914 | a->x_csect.x_stab = 0; | |
5915 | a->x_csect.x_snstab = 0; | |
5916 | ||
5917 | symbol_insert (csect, sym, &symbol_rootP, &symbol_lastP); | |
5918 | ||
5919 | i = S_GET_NUMBER_AUXILIARY (sym); | |
809ffe0d ILT |
5920 | a = &coffsymbol (symbol_get_bfdsym (sym))->native[i].u.auxent; |
5921 | a->x_csect.x_scnlen.p = coffsymbol (symbol_get_bfdsym (csect))->native; | |
5922 | coffsymbol (symbol_get_bfdsym (sym))->native[i].fix_scnlen = 1; | |
252b5132 RH |
5923 | } |
5924 | ||
b34976b6 | 5925 | ppc_saw_abs = FALSE; |
252b5132 RH |
5926 | } |
5927 | ||
5928 | /* Set the VMA for a section. This is called on all the sections in | |
5929 | turn. */ | |
5930 | ||
5931 | void | |
98027b10 | 5932 | ppc_frob_section (asection *sec) |
252b5132 | 5933 | { |
931e13a6 | 5934 | static bfd_vma vma = 0; |
252b5132 | 5935 | |
85645aed | 5936 | /* Dwarf sections start at 0. */ |
fd361982 | 5937 | if (bfd_section_flags (sec) & SEC_DEBUGGING) |
85645aed TG |
5938 | return; |
5939 | ||
931e13a6 | 5940 | vma = md_section_align (sec, vma); |
fd361982 AM |
5941 | bfd_set_section_vma (sec, vma); |
5942 | vma += bfd_section_size (sec); | |
252b5132 RH |
5943 | } |
5944 | ||
5945 | #endif /* OBJ_XCOFF */ | |
5946 | \f | |
6d4af3c2 | 5947 | const char * |
98027b10 | 5948 | md_atof (int type, char *litp, int *sizep) |
252b5132 | 5949 | { |
499ac353 | 5950 | return ieee_md_atof (type, litp, sizep, target_big_endian); |
252b5132 RH |
5951 | } |
5952 | ||
5953 | /* Write a value out to the object file, using the appropriate | |
5954 | endianness. */ | |
5955 | ||
5956 | void | |
98027b10 | 5957 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
5958 | { |
5959 | if (target_big_endian) | |
5960 | number_to_chars_bigendian (buf, val, n); | |
5961 | else | |
5962 | number_to_chars_littleendian (buf, val, n); | |
5963 | } | |
5964 | ||
5965 | /* Align a section (I don't know why this is machine dependent). */ | |
5966 | ||
5967 | valueT | |
3aeeedbb | 5968 | md_section_align (asection *seg ATTRIBUTE_UNUSED, valueT addr) |
252b5132 | 5969 | { |
3aeeedbb AM |
5970 | #ifdef OBJ_ELF |
5971 | return addr; | |
5972 | #else | |
fd361982 | 5973 | int align = bfd_section_alignment (seg); |
252b5132 | 5974 | |
8d3842cd | 5975 | return ((addr + (1 << align) - 1) & -(1 << align)); |
3aeeedbb | 5976 | #endif |
252b5132 RH |
5977 | } |
5978 | ||
5979 | /* We don't have any form of relaxing. */ | |
5980 | ||
5981 | int | |
98027b10 AM |
5982 | md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, |
5983 | asection *seg ATTRIBUTE_UNUSED) | |
252b5132 RH |
5984 | { |
5985 | abort (); | |
5986 | return 0; | |
5987 | } | |
5988 | ||
5989 | /* Convert a machine dependent frag. We never generate these. */ | |
5990 | ||
5991 | void | |
98027b10 AM |
5992 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
5993 | asection *sec ATTRIBUTE_UNUSED, | |
5994 | fragS *fragp ATTRIBUTE_UNUSED) | |
252b5132 RH |
5995 | { |
5996 | abort (); | |
5997 | } | |
5998 | ||
5999 | /* We have no need to default values of symbols. */ | |
6000 | ||
252b5132 | 6001 | symbolS * |
98027b10 | 6002 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
6003 | { |
6004 | return 0; | |
6005 | } | |
6006 | \f | |
6007 | /* Functions concerning relocs. */ | |
6008 | ||
6009 | /* The location from which a PC relative jump should be calculated, | |
6010 | given a PC relative reloc. */ | |
6011 | ||
6012 | long | |
98027b10 | 6013 | md_pcrel_from_section (fixS *fixp, segT sec ATTRIBUTE_UNUSED) |
252b5132 RH |
6014 | { |
6015 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
6016 | } | |
6017 | ||
6018 | #ifdef OBJ_XCOFF | |
6019 | ||
6020 | /* This is called to see whether a fixup should be adjusted to use a | |
6021 | section symbol. We take the opportunity to change a fixup against | |
6022 | a symbol in the TOC subsegment into a reloc against the | |
6023 | corresponding .tc symbol. */ | |
6024 | ||
6025 | int | |
98027b10 | 6026 | ppc_fix_adjustable (fixS *fix) |
252b5132 | 6027 | { |
b782de16 AM |
6028 | valueT val = resolve_symbol_value (fix->fx_addsy); |
6029 | segT symseg = S_GET_SEGMENT (fix->fx_addsy); | |
6030 | TC_SYMFIELD_TYPE *tc; | |
6031 | ||
6032 | if (symseg == absolute_section) | |
6033 | return 0; | |
252b5132 | 6034 | |
85645aed | 6035 | /* Always adjust symbols in debugging sections. */ |
fd361982 | 6036 | if (bfd_section_flags (symseg) & SEC_DEBUGGING) |
85645aed TG |
6037 | return 1; |
6038 | ||
252b5132 | 6039 | if (ppc_toc_csect != (symbolS *) NULL |
252b5132 | 6040 | && fix->fx_addsy != ppc_toc_csect |
b782de16 | 6041 | && symseg == data_section |
252b5132 RH |
6042 | && val >= ppc_toc_frag->fr_address |
6043 | && (ppc_after_toc_frag == (fragS *) NULL | |
6044 | || val < ppc_after_toc_frag->fr_address)) | |
6045 | { | |
6046 | symbolS *sy; | |
6047 | ||
6048 | for (sy = symbol_next (ppc_toc_csect); | |
6049 | sy != (symbolS *) NULL; | |
6050 | sy = symbol_next (sy)) | |
6051 | { | |
b782de16 AM |
6052 | TC_SYMFIELD_TYPE *sy_tc = symbol_get_tc (sy); |
6053 | ||
96d56e9f | 6054 | if (sy_tc->symbol_class == XMC_TC0) |
252b5132 | 6055 | continue; |
96d56e9f | 6056 | if (sy_tc->symbol_class != XMC_TC) |
252b5132 | 6057 | break; |
b782de16 | 6058 | if (val == resolve_symbol_value (sy)) |
252b5132 RH |
6059 | { |
6060 | fix->fx_addsy = sy; | |
6061 | fix->fx_addnumber = val - ppc_toc_frag->fr_address; | |
6062 | return 0; | |
6063 | } | |
6064 | } | |
6065 | ||
6066 | as_bad_where (fix->fx_file, fix->fx_line, | |
6067 | _("symbol in .toc does not match any .tc")); | |
6068 | } | |
6069 | ||
6070 | /* Possibly adjust the reloc to be against the csect. */ | |
b782de16 AM |
6071 | tc = symbol_get_tc (fix->fx_addsy); |
6072 | if (tc->subseg == 0 | |
96d56e9f NC |
6073 | && tc->symbol_class != XMC_TC0 |
6074 | && tc->symbol_class != XMC_TC | |
b782de16 | 6075 | && symseg != bss_section |
252b5132 | 6076 | /* Don't adjust if this is a reloc in the toc section. */ |
b782de16 | 6077 | && (symseg != data_section |
252b5132 RH |
6078 | || ppc_toc_csect == NULL |
6079 | || val < ppc_toc_frag->fr_address | |
6080 | || (ppc_after_toc_frag != NULL | |
6081 | && val >= ppc_after_toc_frag->fr_address))) | |
6082 | { | |
2fb4b302 | 6083 | symbolS *csect = tc->within; |
252b5132 | 6084 | |
2fb4b302 TG |
6085 | /* If the symbol was not declared by a label (eg: a section symbol), |
6086 | use the section instead of the csect. This doesn't happen in | |
6087 | normal AIX assembly code. */ | |
6088 | if (csect == NULL) | |
6089 | csect = seg_info (symseg)->sym; | |
252b5132 | 6090 | |
2fb4b302 TG |
6091 | fix->fx_offset += val - symbol_get_frag (csect)->fr_address; |
6092 | fix->fx_addsy = csect; | |
252b5132 | 6093 | |
b782de16 | 6094 | return 0; |
252b5132 RH |
6095 | } |
6096 | ||
6097 | /* Adjust a reloc against a .lcomm symbol to be against the base | |
6098 | .lcomm. */ | |
b782de16 | 6099 | if (symseg == bss_section |
252b5132 RH |
6100 | && ! S_IS_EXTERNAL (fix->fx_addsy)) |
6101 | { | |
b782de16 AM |
6102 | symbolS *sy = symbol_get_frag (fix->fx_addsy)->fr_symbol; |
6103 | ||
6104 | fix->fx_offset += val - resolve_symbol_value (sy); | |
6105 | fix->fx_addsy = sy; | |
252b5132 RH |
6106 | } |
6107 | ||
6108 | return 0; | |
6109 | } | |
6110 | ||
6111 | /* A reloc from one csect to another must be kept. The assembler | |
6112 | will, of course, keep relocs between sections, and it will keep | |
6113 | absolute relocs, but we need to force it to keep PC relative relocs | |
6114 | between two csects in the same section. */ | |
6115 | ||
6116 | int | |
98027b10 | 6117 | ppc_force_relocation (fixS *fix) |
252b5132 RH |
6118 | { |
6119 | /* At this point fix->fx_addsy should already have been converted to | |
6120 | a csect symbol. If the csect does not include the fragment, then | |
6121 | we need to force the relocation. */ | |
6122 | if (fix->fx_pcrel | |
6123 | && fix->fx_addsy != NULL | |
809ffe0d ILT |
6124 | && symbol_get_tc (fix->fx_addsy)->subseg != 0 |
6125 | && ((symbol_get_frag (fix->fx_addsy)->fr_address | |
6126 | > fix->fx_frag->fr_address) | |
6127 | || (symbol_get_tc (fix->fx_addsy)->next != NULL | |
6128 | && (symbol_get_frag (symbol_get_tc (fix->fx_addsy)->next)->fr_address | |
252b5132 RH |
6129 | <= fix->fx_frag->fr_address)))) |
6130 | return 1; | |
6131 | ||
ae6063d4 | 6132 | return generic_force_reloc (fix); |
252b5132 | 6133 | } |
252b5132 RH |
6134 | #endif /* OBJ_XCOFF */ |
6135 | ||
0baf16f2 | 6136 | #ifdef OBJ_ELF |
a161fe53 AM |
6137 | /* If this function returns non-zero, it guarantees that a relocation |
6138 | will be emitted for a fixup. */ | |
6139 | ||
6140 | int | |
98027b10 | 6141 | ppc_force_relocation (fixS *fix) |
a161fe53 AM |
6142 | { |
6143 | /* Branch prediction relocations must force a relocation, as must | |
6144 | the vtable description relocs. */ | |
6145 | switch (fix->fx_r_type) | |
6146 | { | |
6147 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
6148 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
6149 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
6150 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
c744ecf2 | 6151 | case BFD_RELOC_24_PLT_PCREL: |
a161fe53 | 6152 | case BFD_RELOC_PPC64_TOC: |
a161fe53 | 6153 | return 1; |
6911b7dc AM |
6154 | case BFD_RELOC_PPC_B26: |
6155 | case BFD_RELOC_PPC_BA26: | |
6156 | case BFD_RELOC_PPC_B16: | |
6157 | case BFD_RELOC_PPC_BA16: | |
05d0e962 | 6158 | case BFD_RELOC_PPC64_REL24_NOTOC: |
6911b7dc AM |
6159 | /* All branch fixups targeting a localentry symbol must |
6160 | force a relocation. */ | |
6161 | if (fix->fx_addsy) | |
6162 | { | |
6163 | asymbol *bfdsym = symbol_get_bfdsym (fix->fx_addsy); | |
c1229f84 | 6164 | elf_symbol_type *elfsym = elf_symbol_from (bfdsym); |
6911b7dc AM |
6165 | gas_assert (elfsym); |
6166 | if ((STO_PPC64_LOCAL_MASK & elfsym->internal_elf_sym.st_other) != 0) | |
6167 | return 1; | |
6168 | } | |
6169 | break; | |
a161fe53 AM |
6170 | default: |
6171 | break; | |
6172 | } | |
6173 | ||
cdba85ec | 6174 | if (fix->fx_r_type >= BFD_RELOC_PPC_TLS |
c213164a | 6175 | && fix->fx_r_type <= BFD_RELOC_PPC64_TLS_PCREL) |
cdba85ec AM |
6176 | return 1; |
6177 | ||
ae6063d4 | 6178 | return generic_force_reloc (fix); |
a161fe53 AM |
6179 | } |
6180 | ||
0baf16f2 | 6181 | int |
98027b10 | 6182 | ppc_fix_adjustable (fixS *fix) |
252b5132 | 6183 | { |
6911b7dc AM |
6184 | switch (fix->fx_r_type) |
6185 | { | |
6186 | /* All branch fixups targeting a localentry symbol must | |
6187 | continue using the symbol. */ | |
6188 | case BFD_RELOC_PPC_B26: | |
6189 | case BFD_RELOC_PPC_BA26: | |
6190 | case BFD_RELOC_PPC_B16: | |
6191 | case BFD_RELOC_PPC_BA16: | |
6192 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
6193 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
6194 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
6195 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
05d0e962 | 6196 | case BFD_RELOC_PPC64_REL24_NOTOC: |
6911b7dc AM |
6197 | if (fix->fx_addsy) |
6198 | { | |
6199 | asymbol *bfdsym = symbol_get_bfdsym (fix->fx_addsy); | |
c1229f84 | 6200 | elf_symbol_type *elfsym = elf_symbol_from (bfdsym); |
6911b7dc AM |
6201 | gas_assert (elfsym); |
6202 | if ((STO_PPC64_LOCAL_MASK & elfsym->internal_elf_sym.st_other) != 0) | |
6203 | return 0; | |
6204 | } | |
6205 | break; | |
6206 | default: | |
6207 | break; | |
6208 | } | |
6209 | ||
0baf16f2 AM |
6210 | return (fix->fx_r_type != BFD_RELOC_16_GOTOFF |
6211 | && fix->fx_r_type != BFD_RELOC_LO16_GOTOFF | |
6212 | && fix->fx_r_type != BFD_RELOC_HI16_GOTOFF | |
6213 | && fix->fx_r_type != BFD_RELOC_HI16_S_GOTOFF | |
cc9edbf3 AM |
6214 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_DS |
6215 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_LO_DS | |
5663e321 | 6216 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT_PCREL34 |
334d91b9 AM |
6217 | && fix->fx_r_type != BFD_RELOC_24_PLT_PCREL |
6218 | && fix->fx_r_type != BFD_RELOC_32_PLTOFF | |
6219 | && fix->fx_r_type != BFD_RELOC_32_PLT_PCREL | |
6220 | && fix->fx_r_type != BFD_RELOC_LO16_PLTOFF | |
6221 | && fix->fx_r_type != BFD_RELOC_HI16_PLTOFF | |
6222 | && fix->fx_r_type != BFD_RELOC_HI16_S_PLTOFF | |
6223 | && fix->fx_r_type != BFD_RELOC_64_PLTOFF | |
6224 | && fix->fx_r_type != BFD_RELOC_64_PLT_PCREL | |
6225 | && fix->fx_r_type != BFD_RELOC_PPC64_PLT16_LO_DS | |
5663e321 | 6226 | && fix->fx_r_type != BFD_RELOC_PPC64_PLT_PCREL34 |
334d91b9 AM |
6227 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16 |
6228 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_LO | |
6229 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_HI | |
6230 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_HA | |
6231 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_DS | |
6232 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_LO_DS | |
0baf16f2 | 6233 | && fix->fx_r_type != BFD_RELOC_GPREL16 |
334d91b9 AM |
6234 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_LO16A |
6235 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_HI16A | |
6236 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_HA16A | |
0baf16f2 AM |
6237 | && fix->fx_r_type != BFD_RELOC_VTABLE_INHERIT |
6238 | && fix->fx_r_type != BFD_RELOC_VTABLE_ENTRY | |
cdba85ec | 6239 | && !(fix->fx_r_type >= BFD_RELOC_PPC_TLS |
c213164a | 6240 | && fix->fx_r_type <= BFD_RELOC_PPC64_TLS_PCREL)); |
252b5132 | 6241 | } |
0baf16f2 | 6242 | #endif |
252b5132 | 6243 | |
b9c361e0 JL |
6244 | void |
6245 | ppc_frag_check (struct frag *fragP) | |
6246 | { | |
a9479dc0 AM |
6247 | if ((fragP->fr_address & fragP->insn_addr) != 0) |
6248 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
6249 | _("instruction address is not a multiple of %d"), | |
6250 | fragP->insn_addr + 1); | |
b9c361e0 JL |
6251 | } |
6252 | ||
22f72c48 AM |
6253 | /* rs_align_code frag handling. */ |
6254 | ||
6255 | enum ppc_nop_encoding_for_rs_align_code | |
6256 | { | |
6257 | PPC_NOP_VANILLA, | |
6258 | PPC_NOP_VLE, | |
6259 | PPC_NOP_GROUP_P6, | |
6260 | PPC_NOP_GROUP_P7 | |
6261 | }; | |
6262 | ||
6263 | unsigned int | |
6264 | ppc_nop_select (void) | |
6265 | { | |
6266 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) | |
6267 | return PPC_NOP_VLE; | |
6268 | if ((ppc_cpu & (PPC_OPCODE_POWER9 | PPC_OPCODE_E500MC)) == 0) | |
6269 | { | |
6270 | if ((ppc_cpu & PPC_OPCODE_POWER7) != 0) | |
6271 | return PPC_NOP_GROUP_P7; | |
6272 | if ((ppc_cpu & PPC_OPCODE_POWER6) != 0) | |
6273 | return PPC_NOP_GROUP_P6; | |
6274 | } | |
6275 | return PPC_NOP_VANILLA; | |
6276 | } | |
3aeeedbb AM |
6277 | |
6278 | void | |
6279 | ppc_handle_align (struct frag *fragP) | |
6280 | { | |
6281 | valueT count = (fragP->fr_next->fr_address | |
6282 | - (fragP->fr_address + fragP->fr_fix)); | |
22f72c48 AM |
6283 | char *dest = fragP->fr_literal + fragP->fr_fix; |
6284 | enum ppc_nop_encoding_for_rs_align_code nop_select = *dest & 0xff; | |
6285 | ||
6286 | /* Pad with zeros if not inserting a whole number of instructions. | |
6287 | We could pad with zeros up to an instruction boundary then follow | |
6288 | with nops but odd counts indicate data in an executable section | |
6289 | so padding with zeros is most appropriate. */ | |
6290 | if (count == 0 | |
de626965 | 6291 | || (nop_select == PPC_NOP_VLE ? (count & 1) != 0 : (count & 3) != 0)) |
22f72c48 AM |
6292 | { |
6293 | *dest = 0; | |
6294 | return; | |
6295 | } | |
3aeeedbb | 6296 | |
22f72c48 | 6297 | if (nop_select == PPC_NOP_VLE) |
b9c361e0 | 6298 | { |
b9c361e0 JL |
6299 | |
6300 | fragP->fr_var = 2; | |
6301 | md_number_to_chars (dest, 0x4400, 2); | |
6302 | } | |
22f72c48 | 6303 | else |
3aeeedbb | 6304 | { |
3aeeedbb | 6305 | fragP->fr_var = 4; |
cef4f754 AM |
6306 | |
6307 | if (count > 4 * nop_limit && count < 0x2000000) | |
6308 | { | |
6309 | struct frag *rest; | |
6310 | ||
6311 | /* Make a branch, then follow with nops. Insert another | |
6312 | frag to handle the nops. */ | |
6313 | md_number_to_chars (dest, 0x48000000 + count, 4); | |
6314 | count -= 4; | |
6315 | if (count == 0) | |
6316 | return; | |
6317 | ||
6318 | rest = xmalloc (SIZEOF_STRUCT_FRAG + 4); | |
6319 | memcpy (rest, fragP, SIZEOF_STRUCT_FRAG); | |
6320 | fragP->fr_next = rest; | |
6321 | fragP = rest; | |
6322 | rest->fr_address += rest->fr_fix + 4; | |
6323 | rest->fr_fix = 0; | |
6324 | /* If we leave the next frag as rs_align_code we'll come here | |
6325 | again, resulting in a bunch of branches rather than a | |
6326 | branch followed by nops. */ | |
6327 | rest->fr_type = rs_align; | |
6328 | dest = rest->fr_literal; | |
6329 | } | |
6330 | ||
3aeeedbb AM |
6331 | md_number_to_chars (dest, 0x60000000, 4); |
6332 | ||
22f72c48 | 6333 | if (nop_select >= PPC_NOP_GROUP_P6) |
3aeeedbb | 6334 | { |
3fea0c3b AM |
6335 | /* For power6, power7, and power8, we want the last nop to |
6336 | be a group terminating one. Do this by inserting an | |
6337 | rs_fill frag immediately after this one, with its address | |
6338 | set to the last nop location. This will automatically | |
6339 | reduce the number of nops in the current frag by one. */ | |
3aeeedbb AM |
6340 | if (count > 4) |
6341 | { | |
6342 | struct frag *group_nop = xmalloc (SIZEOF_STRUCT_FRAG + 4); | |
6343 | ||
6344 | memcpy (group_nop, fragP, SIZEOF_STRUCT_FRAG); | |
6345 | group_nop->fr_address = group_nop->fr_next->fr_address - 4; | |
6346 | group_nop->fr_fix = 0; | |
6347 | group_nop->fr_offset = 1; | |
6348 | group_nop->fr_type = rs_fill; | |
6349 | fragP->fr_next = group_nop; | |
6350 | dest = group_nop->fr_literal; | |
6351 | } | |
6352 | ||
22f72c48 | 6353 | if (nop_select == PPC_NOP_GROUP_P6) |
42240548 PB |
6354 | /* power6 group terminating nop: "ori 1,1,0". */ |
6355 | md_number_to_chars (dest, 0x60210000, 4); | |
22f72c48 AM |
6356 | else |
6357 | /* power7/power8 group terminating nop: "ori 2,2,0". */ | |
6358 | md_number_to_chars (dest, 0x60420000, 4); | |
3aeeedbb AM |
6359 | } |
6360 | } | |
6361 | } | |
6362 | ||
252b5132 | 6363 | /* Apply a fixup to the object code. This is called for all the |
3b8b57a9 | 6364 | fixups we generated by the calls to fix_new_exp, above. */ |
252b5132 | 6365 | |
94f592af | 6366 | void |
62ebcb5c | 6367 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
252b5132 | 6368 | { |
94f592af | 6369 | valueT value = * valP; |
5656a981 AM |
6370 | offsetT fieldval; |
6371 | const struct powerpc_operand *operand; | |
252b5132 RH |
6372 | |
6373 | #ifdef OBJ_ELF | |
94f592af | 6374 | if (fixP->fx_addsy != NULL) |
252b5132 | 6375 | { |
a161fe53 | 6376 | /* Hack around bfd_install_relocation brain damage. */ |
94f592af NC |
6377 | if (fixP->fx_pcrel) |
6378 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
a680de9a PB |
6379 | |
6380 | if (fixP->fx_addsy == abs_section_sym) | |
6381 | fixP->fx_done = 1; | |
252b5132 RH |
6382 | } |
6383 | else | |
94f592af | 6384 | fixP->fx_done = 1; |
252b5132 | 6385 | #else |
a161fe53 | 6386 | /* FIXME FIXME FIXME: The value we are passed in *valP includes |
7be1c489 AM |
6387 | the symbol values. If we are doing this relocation the code in |
6388 | write.c is going to call bfd_install_relocation, which is also | |
6389 | going to use the symbol value. That means that if the reloc is | |
6390 | fully resolved we want to use *valP since bfd_install_relocation is | |
6391 | not being used. | |
9f0eb232 RS |
6392 | However, if the reloc is not fully resolved we do not want to |
6393 | use *valP, and must use fx_offset instead. If the relocation | |
6394 | is PC-relative, we then need to re-apply md_pcrel_from_section | |
6395 | to this new relocation value. */ | |
94f592af NC |
6396 | if (fixP->fx_addsy == (symbolS *) NULL) |
6397 | fixP->fx_done = 1; | |
6398 | ||
252b5132 | 6399 | else |
9f0eb232 RS |
6400 | { |
6401 | value = fixP->fx_offset; | |
6402 | if (fixP->fx_pcrel) | |
6403 | value -= md_pcrel_from_section (fixP, seg); | |
6404 | } | |
a161fe53 AM |
6405 | #endif |
6406 | ||
7ba71655 AM |
6407 | /* We are only able to convert some relocs to pc-relative. */ |
6408 | if (fixP->fx_pcrel) | |
6409 | { | |
6410 | switch (fixP->fx_r_type) | |
6411 | { | |
4a969973 AM |
6412 | case BFD_RELOC_64: |
6413 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
6414 | break; | |
6415 | ||
6416 | case BFD_RELOC_32: | |
6417 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
6418 | break; | |
6419 | ||
6420 | case BFD_RELOC_16: | |
6421 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
6422 | break; | |
6423 | ||
7ba71655 AM |
6424 | case BFD_RELOC_LO16: |
6425 | fixP->fx_r_type = BFD_RELOC_LO16_PCREL; | |
6426 | break; | |
6427 | ||
6428 | case BFD_RELOC_HI16: | |
6429 | fixP->fx_r_type = BFD_RELOC_HI16_PCREL; | |
6430 | break; | |
6431 | ||
6432 | case BFD_RELOC_HI16_S: | |
6433 | fixP->fx_r_type = BFD_RELOC_HI16_S_PCREL; | |
6434 | break; | |
6435 | ||
4a969973 AM |
6436 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
6437 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGH; | |
7ba71655 AM |
6438 | break; |
6439 | ||
4a969973 AM |
6440 | case BFD_RELOC_PPC64_ADDR16_HIGHA: |
6441 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHA; | |
7ba71655 AM |
6442 | break; |
6443 | ||
4a969973 AM |
6444 | case BFD_RELOC_PPC64_HIGHER: |
6445 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHER; | |
6446 | break; | |
6447 | ||
6448 | case BFD_RELOC_PPC64_HIGHER_S: | |
6449 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHERA; | |
6450 | break; | |
6451 | ||
6452 | case BFD_RELOC_PPC64_HIGHEST: | |
6453 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHEST; | |
6454 | break; | |
6455 | ||
6456 | case BFD_RELOC_PPC64_HIGHEST_S: | |
6457 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHESTA; | |
7ba71655 AM |
6458 | break; |
6459 | ||
5663e321 AM |
6460 | case BFD_RELOC_PPC64_ADDR16_HIGHER34: |
6461 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHER34; | |
6462 | break; | |
6463 | ||
6464 | case BFD_RELOC_PPC64_ADDR16_HIGHERA34: | |
6465 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHERA34; | |
6466 | break; | |
6467 | ||
6468 | case BFD_RELOC_PPC64_ADDR16_HIGHEST34: | |
6469 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHEST34; | |
6470 | break; | |
6471 | ||
6472 | case BFD_RELOC_PPC64_ADDR16_HIGHESTA34: | |
6473 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHESTA34; | |
6474 | break; | |
6475 | ||
7ba71655 AM |
6476 | case BFD_RELOC_PPC_16DX_HA: |
6477 | fixP->fx_r_type = BFD_RELOC_PPC_REL16DX_HA; | |
6478 | break; | |
6479 | ||
5663e321 AM |
6480 | case BFD_RELOC_PPC64_D34: |
6481 | fixP->fx_r_type = BFD_RELOC_PPC64_PCREL34; | |
6482 | break; | |
6483 | ||
6484 | case BFD_RELOC_PPC64_D28: | |
6485 | fixP->fx_r_type = BFD_RELOC_PPC64_PCREL28; | |
6486 | break; | |
6487 | ||
7ba71655 AM |
6488 | default: |
6489 | break; | |
6490 | } | |
6491 | } | |
6492 | else if (!fixP->fx_done | |
6493 | && fixP->fx_r_type == BFD_RELOC_PPC_16DX_HA) | |
252b5132 | 6494 | { |
7ba71655 AM |
6495 | /* addpcis is relative to next insn address. */ |
6496 | value -= 4; | |
6497 | fixP->fx_r_type = BFD_RELOC_PPC_REL16DX_HA; | |
6498 | fixP->fx_pcrel = 1; | |
252b5132 | 6499 | } |
252b5132 | 6500 | |
5656a981 | 6501 | operand = NULL; |
3b8b57a9 | 6502 | if (fixP->fx_pcrel_adjust != 0) |
252b5132 | 6503 | { |
5656a981 | 6504 | /* This is a fixup on an instruction. */ |
3b8b57a9 | 6505 | int opindex = fixP->fx_pcrel_adjust & 0xff; |
252b5132 | 6506 | |
5656a981 | 6507 | operand = &powerpc_operands[opindex]; |
252b5132 | 6508 | #ifdef OBJ_XCOFF |
0baf16f2 AM |
6509 | /* An instruction like `lwz 9,sym(30)' when `sym' is not a TOC symbol |
6510 | does not generate a reloc. It uses the offset of `sym' within its | |
6511 | csect. Other usages, such as `.long sym', generate relocs. This | |
6512 | is the documented behaviour of non-TOC symbols. */ | |
252b5132 | 6513 | if ((operand->flags & PPC_OPERAND_PARENS) != 0 |
b84bf58a | 6514 | && (operand->bitm & 0xfff0) == 0xfff0 |
252b5132 | 6515 | && operand->shift == 0 |
2b3c4602 | 6516 | && (operand->insert == NULL || ppc_obj64) |
94f592af NC |
6517 | && fixP->fx_addsy != NULL |
6518 | && symbol_get_tc (fixP->fx_addsy)->subseg != 0 | |
96d56e9f NC |
6519 | && symbol_get_tc (fixP->fx_addsy)->symbol_class != XMC_TC |
6520 | && symbol_get_tc (fixP->fx_addsy)->symbol_class != XMC_TC0 | |
94f592af | 6521 | && S_GET_SEGMENT (fixP->fx_addsy) != bss_section) |
252b5132 | 6522 | { |
94f592af NC |
6523 | value = fixP->fx_offset; |
6524 | fixP->fx_done = 1; | |
252b5132 | 6525 | } |
ac21e7da TG |
6526 | |
6527 | /* During parsing of instructions, a TOC16 reloc is generated for | |
6528 | instructions such as 'lwz RT,SYM(RB)' if SYM is a symbol defined | |
6529 | in the toc. But at parse time, SYM may be not yet defined, so | |
6530 | check again here. */ | |
6531 | if (fixP->fx_r_type == BFD_RELOC_16 | |
6532 | && fixP->fx_addsy != NULL | |
6533 | && ppc_is_toc_sym (fixP->fx_addsy)) | |
6534 | fixP->fx_r_type = BFD_RELOC_PPC_TOC16; | |
252b5132 | 6535 | #endif |
5656a981 AM |
6536 | } |
6537 | ||
6538 | /* Calculate value to be stored in field. */ | |
6539 | fieldval = value; | |
6540 | switch (fixP->fx_r_type) | |
6541 | { | |
1ec2d25e | 6542 | #ifdef OBJ_ELF |
5656a981 AM |
6543 | case BFD_RELOC_PPC64_ADDR16_LO_DS: |
6544 | case BFD_RELOC_PPC_VLE_LO16A: | |
6545 | case BFD_RELOC_PPC_VLE_LO16D: | |
1ec2d25e | 6546 | #endif |
5656a981 AM |
6547 | case BFD_RELOC_LO16: |
6548 | case BFD_RELOC_LO16_PCREL: | |
6549 | fieldval = value & 0xffff; | |
6550 | sign_extend_16: | |
6551 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
f9c6b907 | 6552 | fieldval = SEX16 (fieldval); |
5656a981 AM |
6553 | fixP->fx_no_overflow = 1; |
6554 | break; | |
3c9d25f4 | 6555 | |
f9c6b907 AM |
6556 | case BFD_RELOC_HI16: |
6557 | case BFD_RELOC_HI16_PCREL: | |
5656a981 | 6558 | #ifdef OBJ_ELF |
f9c6b907 AM |
6559 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
6560 | { | |
6561 | fieldval = value >> 16; | |
6562 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
6563 | { | |
6564 | valueT sign = (((valueT) -1 >> 16) + 1) >> 1; | |
6565 | fieldval = ((valueT) fieldval ^ sign) - sign; | |
6566 | } | |
6567 | break; | |
6568 | } | |
2b0f3761 | 6569 | /* Fallthru */ |
f9c6b907 | 6570 | |
5656a981 AM |
6571 | case BFD_RELOC_PPC_VLE_HI16A: |
6572 | case BFD_RELOC_PPC_VLE_HI16D: | |
f9c6b907 | 6573 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
5656a981 | 6574 | #endif |
5656a981 AM |
6575 | fieldval = PPC_HI (value); |
6576 | goto sign_extend_16; | |
0baf16f2 | 6577 | |
f9c6b907 AM |
6578 | case BFD_RELOC_HI16_S: |
6579 | case BFD_RELOC_HI16_S_PCREL: | |
7ba71655 | 6580 | case BFD_RELOC_PPC_16DX_HA: |
a680de9a | 6581 | case BFD_RELOC_PPC_REL16DX_HA: |
5656a981 | 6582 | #ifdef OBJ_ELF |
f9c6b907 AM |
6583 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
6584 | { | |
6585 | fieldval = (value + 0x8000) >> 16; | |
6586 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
6587 | { | |
6588 | valueT sign = (((valueT) -1 >> 16) + 1) >> 1; | |
6589 | fieldval = ((valueT) fieldval ^ sign) - sign; | |
6590 | } | |
6591 | break; | |
6592 | } | |
2b0f3761 | 6593 | /* Fallthru */ |
f9c6b907 | 6594 | |
5656a981 AM |
6595 | case BFD_RELOC_PPC_VLE_HA16A: |
6596 | case BFD_RELOC_PPC_VLE_HA16D: | |
f9c6b907 | 6597 | case BFD_RELOC_PPC64_ADDR16_HIGHA: |
5656a981 | 6598 | #endif |
5656a981 AM |
6599 | fieldval = PPC_HA (value); |
6600 | goto sign_extend_16; | |
0baf16f2 | 6601 | |
3b8b57a9 | 6602 | #ifdef OBJ_ELF |
5656a981 AM |
6603 | case BFD_RELOC_PPC64_HIGHER: |
6604 | fieldval = PPC_HIGHER (value); | |
6605 | goto sign_extend_16; | |
252b5132 | 6606 | |
5656a981 AM |
6607 | case BFD_RELOC_PPC64_HIGHER_S: |
6608 | fieldval = PPC_HIGHERA (value); | |
6609 | goto sign_extend_16; | |
0baf16f2 | 6610 | |
5656a981 AM |
6611 | case BFD_RELOC_PPC64_HIGHEST: |
6612 | fieldval = PPC_HIGHEST (value); | |
6613 | goto sign_extend_16; | |
0baf16f2 | 6614 | |
5656a981 AM |
6615 | case BFD_RELOC_PPC64_HIGHEST_S: |
6616 | fieldval = PPC_HIGHESTA (value); | |
6617 | goto sign_extend_16; | |
6618 | #endif | |
6619 | ||
6620 | default: | |
6621 | break; | |
6622 | } | |
6623 | ||
6624 | if (operand != NULL) | |
6625 | { | |
6626 | /* Handle relocs in an insn. */ | |
5656a981 AM |
6627 | switch (fixP->fx_r_type) |
6628 | { | |
7fa9fcb6 | 6629 | #ifdef OBJ_ELF |
3b8b57a9 AM |
6630 | /* The following relocs can't be calculated by the assembler. |
6631 | Leave the field zero. */ | |
cdba85ec AM |
6632 | case BFD_RELOC_PPC_TPREL16: |
6633 | case BFD_RELOC_PPC_TPREL16_LO: | |
6634 | case BFD_RELOC_PPC_TPREL16_HI: | |
6635 | case BFD_RELOC_PPC_TPREL16_HA: | |
cdba85ec AM |
6636 | case BFD_RELOC_PPC_DTPREL16: |
6637 | case BFD_RELOC_PPC_DTPREL16_LO: | |
6638 | case BFD_RELOC_PPC_DTPREL16_HI: | |
6639 | case BFD_RELOC_PPC_DTPREL16_HA: | |
cdba85ec AM |
6640 | case BFD_RELOC_PPC_GOT_TLSGD16: |
6641 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
6642 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
6643 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
6644 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
6645 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
6646 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
6647 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
6648 | case BFD_RELOC_PPC_GOT_TPREL16: | |
6649 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
6650 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
6651 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
6652 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
6653 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
6654 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
6655 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
6656 | case BFD_RELOC_PPC64_TPREL16_DS: | |
6657 | case BFD_RELOC_PPC64_TPREL16_LO_DS: | |
f9c6b907 AM |
6658 | case BFD_RELOC_PPC64_TPREL16_HIGH: |
6659 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
cdba85ec AM |
6660 | case BFD_RELOC_PPC64_TPREL16_HIGHER: |
6661 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
6662 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
6663 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
f9c6b907 AM |
6664 | case BFD_RELOC_PPC64_DTPREL16_HIGH: |
6665 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
cdba85ec AM |
6666 | case BFD_RELOC_PPC64_DTPREL16_DS: |
6667 | case BFD_RELOC_PPC64_DTPREL16_LO_DS: | |
6668 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: | |
6669 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
6670 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
6671 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
c213164a AM |
6672 | case BFD_RELOC_PPC64_TPREL34: |
6673 | case BFD_RELOC_PPC64_DTPREL34: | |
87c69f97 AM |
6674 | case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34: |
6675 | case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34: | |
6676 | case BFD_RELOC_PPC64_GOT_TPREL_PCREL34: | |
6677 | case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34: | |
3b8b57a9 | 6678 | gas_assert (fixP->fx_addsy != NULL); |
7c1d0959 | 6679 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
3b8b57a9 | 6680 | fieldval = 0; |
cdba85ec | 6681 | break; |
3b8b57a9 AM |
6682 | |
6683 | /* These also should leave the field zero for the same | |
6684 | reason. Note that older versions of gas wrote values | |
6685 | here. If we want to go back to the old behaviour, then | |
6686 | all _LO and _LO_DS cases will need to be treated like | |
6687 | BFD_RELOC_LO16_PCREL above. Similarly for _HI etc. */ | |
6688 | case BFD_RELOC_16_GOTOFF: | |
6689 | case BFD_RELOC_LO16_GOTOFF: | |
6690 | case BFD_RELOC_HI16_GOTOFF: | |
6691 | case BFD_RELOC_HI16_S_GOTOFF: | |
6692 | case BFD_RELOC_LO16_PLTOFF: | |
6693 | case BFD_RELOC_HI16_PLTOFF: | |
6694 | case BFD_RELOC_HI16_S_PLTOFF: | |
6695 | case BFD_RELOC_GPREL16: | |
6696 | case BFD_RELOC_16_BASEREL: | |
6697 | case BFD_RELOC_LO16_BASEREL: | |
6698 | case BFD_RELOC_HI16_BASEREL: | |
6699 | case BFD_RELOC_HI16_S_BASEREL: | |
6700 | case BFD_RELOC_PPC_TOC16: | |
6701 | case BFD_RELOC_PPC64_TOC16_LO: | |
6702 | case BFD_RELOC_PPC64_TOC16_HI: | |
6703 | case BFD_RELOC_PPC64_TOC16_HA: | |
6704 | case BFD_RELOC_PPC64_PLTGOT16: | |
6705 | case BFD_RELOC_PPC64_PLTGOT16_LO: | |
6706 | case BFD_RELOC_PPC64_PLTGOT16_HI: | |
6707 | case BFD_RELOC_PPC64_PLTGOT16_HA: | |
6708 | case BFD_RELOC_PPC64_GOT16_DS: | |
6709 | case BFD_RELOC_PPC64_GOT16_LO_DS: | |
6710 | case BFD_RELOC_PPC64_PLT16_LO_DS: | |
6711 | case BFD_RELOC_PPC64_SECTOFF_DS: | |
6712 | case BFD_RELOC_PPC64_SECTOFF_LO_DS: | |
6713 | case BFD_RELOC_PPC64_TOC16_DS: | |
6714 | case BFD_RELOC_PPC64_TOC16_LO_DS: | |
6715 | case BFD_RELOC_PPC64_PLTGOT16_DS: | |
6716 | case BFD_RELOC_PPC64_PLTGOT16_LO_DS: | |
6717 | case BFD_RELOC_PPC_EMB_NADDR16: | |
6718 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
6719 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
6720 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
6721 | case BFD_RELOC_PPC_EMB_SDAI16: | |
6722 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
6723 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
252b5132 | 6724 | case BFD_RELOC_PPC_EMB_SDA21: |
3b8b57a9 AM |
6725 | case BFD_RELOC_PPC_EMB_MRKREF: |
6726 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
6727 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
6728 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
6729 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
6730 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
6731 | case BFD_RELOC_PPC_EMB_RELSDA: | |
6732 | case BFD_RELOC_PPC_VLE_SDA21: | |
6733 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
6734 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
6735 | case BFD_RELOC_PPC_VLE_SDAREL_LO16D: | |
6736 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
6737 | case BFD_RELOC_PPC_VLE_SDAREL_HI16D: | |
6738 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
6739 | case BFD_RELOC_PPC_VLE_SDAREL_HA16D: | |
5663e321 AM |
6740 | case BFD_RELOC_PPC64_GOT_PCREL34: |
6741 | case BFD_RELOC_PPC64_PLT_PCREL34: | |
3b8b57a9 | 6742 | gas_assert (fixP->fx_addsy != NULL); |
2b0f3761 | 6743 | /* Fallthru */ |
3b8b57a9 AM |
6744 | |
6745 | case BFD_RELOC_PPC_TLS: | |
6746 | case BFD_RELOC_PPC_TLSGD: | |
6747 | case BFD_RELOC_PPC_TLSLD: | |
c213164a | 6748 | case BFD_RELOC_PPC64_TLS_PCREL: |
3b8b57a9 | 6749 | fieldval = 0; |
3b8b57a9 | 6750 | break; |
7fa9fcb6 TG |
6751 | #endif |
6752 | ||
6753 | #ifdef OBJ_XCOFF | |
6754 | case BFD_RELOC_PPC_B16: | |
6755 | /* Adjust the offset to the instruction boundary. */ | |
6756 | fieldval += 2; | |
6757 | break; | |
6758 | #endif | |
252b5132 | 6759 | |
f728387b AM |
6760 | case BFD_RELOC_VTABLE_INHERIT: |
6761 | case BFD_RELOC_VTABLE_ENTRY: | |
6762 | case BFD_RELOC_PPC_DTPMOD: | |
6763 | case BFD_RELOC_PPC_TPREL: | |
6764 | case BFD_RELOC_PPC_DTPREL: | |
6765 | case BFD_RELOC_PPC_COPY: | |
6766 | case BFD_RELOC_PPC_GLOB_DAT: | |
6767 | case BFD_RELOC_32_PLT_PCREL: | |
6768 | case BFD_RELOC_PPC_EMB_NADDR32: | |
6769 | case BFD_RELOC_PPC64_TOC: | |
6770 | case BFD_RELOC_CTOR: | |
6771 | case BFD_RELOC_32: | |
6772 | case BFD_RELOC_32_PCREL: | |
6773 | case BFD_RELOC_RVA: | |
6774 | case BFD_RELOC_64: | |
6775 | case BFD_RELOC_64_PCREL: | |
6776 | case BFD_RELOC_PPC64_ADDR64_LOCAL: | |
6777 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6778 | _("%s unsupported as instruction fixup"), | |
6779 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
6780 | fixP->fx_done = 1; | |
6781 | return; | |
6782 | ||
3b8b57a9 | 6783 | default: |
252b5132 | 6784 | break; |
3b8b57a9 | 6785 | } |
252b5132 | 6786 | |
3b8b57a9 AM |
6787 | #ifdef OBJ_ELF |
6788 | /* powerpc uses RELA style relocs, so if emitting a reloc the field | |
6789 | contents can stay at zero. */ | |
6790 | #define APPLY_RELOC fixP->fx_done | |
6791 | #else | |
6792 | #define APPLY_RELOC 1 | |
6793 | #endif | |
5663e321 AM |
6794 | /* We need to call the insert function even when fieldval is |
6795 | zero if the insert function would translate that zero to a | |
6796 | bit pattern other than all zeros. */ | |
3b8b57a9 AM |
6797 | if ((fieldval != 0 && APPLY_RELOC) || operand->insert != NULL) |
6798 | { | |
5663e321 | 6799 | uint64_t insn; |
487b24d8 AM |
6800 | unsigned char *where; |
6801 | ||
3b8b57a9 AM |
6802 | /* Fetch the instruction, insert the fully resolved operand |
6803 | value, and stuff the instruction back again. */ | |
487b24d8 | 6804 | where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
3b8b57a9 | 6805 | if (target_big_endian) |
31a91399 | 6806 | { |
5663e321 | 6807 | if (fixP->fx_size < 4) |
487b24d8 | 6808 | insn = bfd_getb16 (where); |
5663e321 AM |
6809 | else |
6810 | { | |
6811 | insn = bfd_getb32 (where); | |
6812 | if (fixP->fx_size > 4) | |
6813 | insn = insn << 32 | bfd_getb32 (where + 4); | |
6814 | } | |
31a91399 NC |
6815 | } |
6816 | else | |
3b8b57a9 | 6817 | { |
5663e321 | 6818 | if (fixP->fx_size < 4) |
487b24d8 | 6819 | insn = bfd_getl16 (where); |
5663e321 AM |
6820 | else |
6821 | { | |
6822 | insn = bfd_getl32 (where); | |
6823 | if (fixP->fx_size > 4) | |
6824 | insn = insn << 32 | bfd_getl32 (where + 4); | |
6825 | } | |
3b8b57a9 AM |
6826 | } |
6827 | insn = ppc_insert_operand (insn, operand, fieldval, | |
6828 | fixP->tc_fix_data.ppc_cpu, | |
6829 | fixP->fx_file, fixP->fx_line); | |
6830 | if (target_big_endian) | |
6831 | { | |
5663e321 | 6832 | if (fixP->fx_size < 4) |
487b24d8 | 6833 | bfd_putb16 (insn, where); |
5663e321 AM |
6834 | else |
6835 | { | |
6836 | if (fixP->fx_size > 4) | |
6837 | { | |
6838 | bfd_putb32 (insn, where + 4); | |
6839 | insn >>= 32; | |
6840 | } | |
6841 | bfd_putb32 (insn, where); | |
6842 | } | |
3b8b57a9 AM |
6843 | } |
6844 | else | |
6845 | { | |
5663e321 | 6846 | if (fixP->fx_size < 4) |
487b24d8 | 6847 | bfd_putl16 (insn, where); |
5663e321 AM |
6848 | else |
6849 | { | |
6850 | if (fixP->fx_size > 4) | |
6851 | { | |
6852 | bfd_putl32 (insn, where + 4); | |
6853 | insn >>= 32; | |
6854 | } | |
6855 | bfd_putl32 (insn, where); | |
6856 | } | |
3b8b57a9 AM |
6857 | } |
6858 | } | |
6859 | ||
6860 | if (fixP->fx_done) | |
6861 | /* Nothing else to do here. */ | |
6862 | return; | |
6863 | ||
6864 | gas_assert (fixP->fx_addsy != NULL); | |
62ebcb5c | 6865 | if (fixP->fx_r_type == BFD_RELOC_NONE) |
3b8b57a9 | 6866 | { |
3b4dbbbf | 6867 | const char *sfile; |
3b8b57a9 AM |
6868 | unsigned int sline; |
6869 | ||
6870 | /* Use expr_symbol_where to see if this is an expression | |
6871 | symbol. */ | |
6872 | if (expr_symbol_where (fixP->fx_addsy, &sfile, &sline)) | |
6873 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6874 | _("unresolved expression that must be resolved")); | |
6875 | else | |
6876 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
6877 | _("unsupported relocation against %s"), | |
6878 | S_GET_NAME (fixP->fx_addsy)); | |
6879 | fixP->fx_done = 1; | |
6880 | return; | |
6881 | } | |
6882 | } | |
6883 | else | |
6884 | { | |
6885 | /* Handle relocs in data. */ | |
6886 | switch (fixP->fx_r_type) | |
6887 | { | |
252b5132 | 6888 | case BFD_RELOC_VTABLE_INHERIT: |
94f592af NC |
6889 | if (fixP->fx_addsy |
6890 | && !S_IS_DEFINED (fixP->fx_addsy) | |
6891 | && !S_IS_WEAK (fixP->fx_addsy)) | |
6892 | S_SET_WEAK (fixP->fx_addsy); | |
2b0f3761 | 6893 | /* Fallthru */ |
252b5132 RH |
6894 | |
6895 | case BFD_RELOC_VTABLE_ENTRY: | |
94f592af | 6896 | fixP->fx_done = 0; |
252b5132 RH |
6897 | break; |
6898 | ||
0baf16f2 | 6899 | #ifdef OBJ_ELF |
3b8b57a9 AM |
6900 | /* These can appear with @l etc. in data. */ |
6901 | case BFD_RELOC_LO16: | |
3b8b57a9 | 6902 | case BFD_RELOC_LO16_PCREL: |
3b8b57a9 | 6903 | case BFD_RELOC_HI16: |
3b8b57a9 | 6904 | case BFD_RELOC_HI16_PCREL: |
3b8b57a9 | 6905 | case BFD_RELOC_HI16_S: |
3b8b57a9 | 6906 | case BFD_RELOC_HI16_S_PCREL: |
3b8b57a9 | 6907 | case BFD_RELOC_PPC64_HIGHER: |
3b8b57a9 | 6908 | case BFD_RELOC_PPC64_HIGHER_S: |
3b8b57a9 | 6909 | case BFD_RELOC_PPC64_HIGHEST: |
3b8b57a9 | 6910 | case BFD_RELOC_PPC64_HIGHEST_S: |
f9c6b907 AM |
6911 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
6912 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
45965137 | 6913 | case BFD_RELOC_PPC64_ADDR64_LOCAL: |
3b8b57a9 AM |
6914 | break; |
6915 | ||
6916 | case BFD_RELOC_PPC_DTPMOD: | |
6917 | case BFD_RELOC_PPC_TPREL: | |
6918 | case BFD_RELOC_PPC_DTPREL: | |
6919 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
6920 | break; | |
6921 | ||
6922 | /* Just punt all of these to the linker. */ | |
6923 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
6924 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
6925 | case BFD_RELOC_16_GOTOFF: | |
6926 | case BFD_RELOC_LO16_GOTOFF: | |
6927 | case BFD_RELOC_HI16_GOTOFF: | |
6928 | case BFD_RELOC_HI16_S_GOTOFF: | |
6929 | case BFD_RELOC_LO16_PLTOFF: | |
6930 | case BFD_RELOC_HI16_PLTOFF: | |
6931 | case BFD_RELOC_HI16_S_PLTOFF: | |
6932 | case BFD_RELOC_PPC_COPY: | |
6933 | case BFD_RELOC_PPC_GLOB_DAT: | |
6934 | case BFD_RELOC_16_BASEREL: | |
6935 | case BFD_RELOC_LO16_BASEREL: | |
6936 | case BFD_RELOC_HI16_BASEREL: | |
6937 | case BFD_RELOC_HI16_S_BASEREL: | |
6938 | case BFD_RELOC_PPC_TLS: | |
6939 | case BFD_RELOC_PPC_DTPREL16_LO: | |
6940 | case BFD_RELOC_PPC_DTPREL16_HI: | |
6941 | case BFD_RELOC_PPC_DTPREL16_HA: | |
6942 | case BFD_RELOC_PPC_TPREL16_LO: | |
6943 | case BFD_RELOC_PPC_TPREL16_HI: | |
6944 | case BFD_RELOC_PPC_TPREL16_HA: | |
6945 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
6946 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
6947 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
6948 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
6949 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
6950 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
6951 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
6952 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
6953 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
6954 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
6955 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
6956 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
6957 | case BFD_RELOC_PPC_GOT_TPREL16: | |
6958 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
6959 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
6960 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
6961 | case BFD_RELOC_24_PLT_PCREL: | |
6962 | case BFD_RELOC_PPC_LOCAL24PC: | |
6963 | case BFD_RELOC_32_PLT_PCREL: | |
6964 | case BFD_RELOC_GPREL16: | |
6965 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
6966 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
6967 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
6968 | case BFD_RELOC_PPC_EMB_NADDR32: | |
6969 | case BFD_RELOC_PPC_EMB_NADDR16: | |
6970 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
6971 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
6972 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
6973 | case BFD_RELOC_PPC_EMB_SDAI16: | |
6974 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
6975 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
6976 | case BFD_RELOC_PPC_EMB_SDA21: | |
6977 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
6978 | case BFD_RELOC_PPC_EMB_MRKREF: | |
6979 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
6980 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
6981 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
6982 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
6983 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
6984 | case BFD_RELOC_PPC_EMB_RELSDA: | |
0baf16f2 | 6985 | case BFD_RELOC_PPC64_TOC: |
3b8b57a9 AM |
6986 | case BFD_RELOC_PPC_TOC16: |
6987 | case BFD_RELOC_PPC64_TOC16_LO: | |
6988 | case BFD_RELOC_PPC64_TOC16_HI: | |
6989 | case BFD_RELOC_PPC64_TOC16_HA: | |
f9c6b907 AM |
6990 | case BFD_RELOC_PPC64_DTPREL16_HIGH: |
6991 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
3b8b57a9 AM |
6992 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: |
6993 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
6994 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
6995 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
f9c6b907 AM |
6996 | case BFD_RELOC_PPC64_TPREL16_HIGH: |
6997 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
3b8b57a9 AM |
6998 | case BFD_RELOC_PPC64_TPREL16_HIGHER: |
6999 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
7000 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
7001 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
c213164a | 7002 | case BFD_RELOC_PPC64_TLS_PCREL: |
94f592af | 7003 | fixP->fx_done = 0; |
0baf16f2 | 7004 | break; |
0baf16f2 | 7005 | #endif |
3b8b57a9 AM |
7006 | |
7007 | #ifdef OBJ_XCOFF | |
7008 | case BFD_RELOC_NONE: | |
3b8b57a9 | 7009 | #endif |
5656a981 AM |
7010 | case BFD_RELOC_CTOR: |
7011 | case BFD_RELOC_32: | |
7012 | case BFD_RELOC_32_PCREL: | |
7013 | case BFD_RELOC_RVA: | |
7014 | case BFD_RELOC_64: | |
7015 | case BFD_RELOC_64_PCREL: | |
7016 | case BFD_RELOC_16: | |
7017 | case BFD_RELOC_16_PCREL: | |
7018 | case BFD_RELOC_8: | |
7019 | break; | |
3b8b57a9 | 7020 | |
252b5132 | 7021 | default: |
bc805888 | 7022 | fprintf (stderr, |
94f592af | 7023 | _("Gas failure, reloc value %d\n"), fixP->fx_r_type); |
99a814a1 | 7024 | fflush (stderr); |
252b5132 RH |
7025 | abort (); |
7026 | } | |
46b596ff | 7027 | |
5656a981 | 7028 | if (fixP->fx_size && APPLY_RELOC) |
46b596ff | 7029 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
5656a981 | 7030 | fieldval, fixP->fx_size); |
bf7279d5 AM |
7031 | if (warn_476 |
7032 | && (seg->flags & SEC_CODE) != 0 | |
7033 | && fixP->fx_size == 4 | |
7034 | && fixP->fx_done | |
7035 | && !fixP->fx_tcbit | |
7036 | && (fixP->fx_r_type == BFD_RELOC_32 | |
7037 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
7038 | || fixP->fx_r_type == BFD_RELOC_32_PCREL)) | |
7039 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
7040 | _("data in executable section")); | |
5656a981 AM |
7041 | } |
7042 | ||
252b5132 | 7043 | #ifdef OBJ_ELF |
3b8b57a9 | 7044 | ppc_elf_validate_fix (fixP, seg); |
94f592af | 7045 | fixP->fx_addnumber = value; |
4e6935a6 AM |
7046 | |
7047 | /* PowerPC uses RELA relocs, ie. the reloc addend is stored separately | |
7048 | from the section contents. If we are going to be emitting a reloc | |
7049 | then the section contents are immaterial, so don't warn if they | |
7050 | happen to overflow. Leave such warnings to ld. */ | |
7051 | if (!fixP->fx_done) | |
a38a07e0 AM |
7052 | { |
7053 | fixP->fx_no_overflow = 1; | |
7054 | ||
7055 | /* Arrange to emit .TOC. as a normal symbol if used in anything | |
7056 | but .TOC.@tocbase. */ | |
7057 | if (ppc_obj64 | |
7058 | && fixP->fx_r_type != BFD_RELOC_PPC64_TOC | |
7059 | && fixP->fx_addsy != NULL | |
7060 | && strcmp (S_GET_NAME (fixP->fx_addsy), ".TOC.") == 0) | |
7061 | symbol_get_bfdsym (fixP->fx_addsy)->flags |= BSF_KEEP; | |
7062 | } | |
252b5132 | 7063 | #else |
94f592af NC |
7064 | if (fixP->fx_r_type != BFD_RELOC_PPC_TOC16) |
7065 | fixP->fx_addnumber = 0; | |
252b5132 RH |
7066 | else |
7067 | { | |
8edcbfcd TG |
7068 | /* We want to use the offset within the toc, not the actual VMA |
7069 | of the symbol. */ | |
fd361982 AM |
7070 | fixP->fx_addnumber = (- bfd_section_vma (S_GET_SEGMENT (fixP->fx_addsy)) |
7071 | - S_GET_VALUE (ppc_toc_csect)); | |
ac21e7da TG |
7072 | /* Set *valP to avoid errors. */ |
7073 | *valP = value; | |
252b5132 RH |
7074 | } |
7075 | #endif | |
252b5132 RH |
7076 | } |
7077 | ||
7078 | /* Generate a reloc for a fixup. */ | |
7079 | ||
7080 | arelent * | |
98027b10 | 7081 | tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
7082 | { |
7083 | arelent *reloc; | |
7084 | ||
325801bd | 7085 | reloc = XNEW (arelent); |
252b5132 | 7086 | |
325801bd | 7087 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
49309057 | 7088 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 | 7089 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
c213164a AM |
7090 | /* BFD_RELOC_PPC64_TLS_PCREL generates R_PPC64_TLS with an odd r_offset. */ |
7091 | if (fixp->fx_r_type == BFD_RELOC_PPC64_TLS_PCREL) | |
7092 | reloc->address++; | |
252b5132 RH |
7093 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
7094 | if (reloc->howto == (reloc_howto_type *) NULL) | |
7095 | { | |
7096 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
99a814a1 AM |
7097 | _("reloc %d not supported by object file format"), |
7098 | (int) fixp->fx_r_type); | |
252b5132 RH |
7099 | return NULL; |
7100 | } | |
7101 | reloc->addend = fixp->fx_addnumber; | |
7102 | ||
7103 | return reloc; | |
7104 | } | |
75e21f08 JJ |
7105 | |
7106 | void | |
98027b10 | 7107 | ppc_cfi_frame_initial_instructions (void) |
75e21f08 JJ |
7108 | { |
7109 | cfi_add_CFA_def_cfa (1, 0); | |
7110 | } | |
7111 | ||
7112 | int | |
1df69f4f | 7113 | tc_ppc_regname_to_dw2regnum (char *regname) |
75e21f08 JJ |
7114 | { |
7115 | unsigned int regnum = -1; | |
7116 | unsigned int i; | |
7117 | const char *p; | |
7118 | char *q; | |
e0471c16 | 7119 | static struct { const char *name; int dw2regnum; } regnames[] = |
75e21f08 JJ |
7120 | { |
7121 | { "sp", 1 }, { "r.sp", 1 }, { "rtoc", 2 }, { "r.toc", 2 }, | |
7122 | { "mq", 64 }, { "lr", 65 }, { "ctr", 66 }, { "ap", 67 }, | |
80f846b6 | 7123 | { "cr", 70 }, { "xer", 76 }, { "vrsave", 109 }, { "vscr", 110 }, |
75e21f08 JJ |
7124 | { "spe_acc", 111 }, { "spefscr", 112 } |
7125 | }; | |
7126 | ||
7127 | for (i = 0; i < ARRAY_SIZE (regnames); ++i) | |
7128 | if (strcmp (regnames[i].name, regname) == 0) | |
7129 | return regnames[i].dw2regnum; | |
7130 | ||
7131 | if (regname[0] == 'r' || regname[0] == 'f' || regname[0] == 'v') | |
7132 | { | |
7133 | p = regname + 1 + (regname[1] == '.'); | |
7134 | regnum = strtoul (p, &q, 10); | |
7135 | if (p == q || *q || regnum >= 32) | |
7136 | return -1; | |
7137 | if (regname[0] == 'f') | |
b7d7dc63 | 7138 | regnum += 32; |
75e21f08 | 7139 | else if (regname[0] == 'v') |
b7d7dc63 | 7140 | regnum += 77; |
75e21f08 JJ |
7141 | } |
7142 | else if (regname[0] == 'c' && regname[1] == 'r') | |
7143 | { | |
7144 | p = regname + 2 + (regname[2] == '.'); | |
7145 | if (p[0] < '0' || p[0] > '7' || p[1]) | |
b7d7dc63 | 7146 | return -1; |
75e21f08 JJ |
7147 | regnum = p[0] - '0' + 68; |
7148 | } | |
7149 | return regnum; | |
7150 | } |