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1// movi.s Test file for AArch64 AdvSIMD modified immediate instruction MOVI
2
3 .text
4
5 .macro all_64bit_mask_movi dst
6 .irp b7, 0, 0xff00000000000000
7 .irp b6, 0, 0xff000000000000
8 .irp b5, 0, 0xff0000000000
9 .irp b4, 0, 0xff00000000
10 .irp b3, 0, 0xff000000
11 .irp b2, 0, 0xff0000
12 .irp b1, 0, 0xff00
13 .irp b0, 0, 0xff
14 movi \dst, \b7 + \b6 + \b5 + \b4 + \b3 + \b2 + \b1 + \b0
15 .endr
16 .endr
17 .endr
18 .endr
19 .endr
20 .endr
21 .endr
22 .endr
23 .endm
24
25 // MOVI <Dd>, #<imm>
26 // MOVI <Vd>.2D, #<imm>
27 all_64bit_mask_movi d31
28 all_64bit_mask_movi v15.2d
29
30
31 .macro all_8bit_imm_movi dst, from=0, to=255
32 movi \dst, \from
33 .if \to-\from
34 all_8bit_imm_movi \dst, "(\from+1)", \to
35 .endif
36 .endm
37
38 // Per byte
39 // MOVI <Vd>.<T>, #<imm8>
40 .irp T, 8b, 16b
41 all_8bit_imm_movi v15.\T, 0, 63
42 all_8bit_imm_movi v15.\T, 64, 127
43 all_8bit_imm_movi v15.\T, 128, 191
44 all_8bit_imm_movi v15.\T, 192, 255
45 .endr
46
47
48 .macro all_8bit_imm_movi_sft dst, from=0, to=255, shift_op, amount
49 movi \dst, \from, \shift_op \amount
50 .if \to-\from
51 all_8bit_imm_movi_sft \dst, "(\from+1)", \to, \shift_op, \amount
52 .endif
53 .endm
54
55 // Shift ones, per word
56 // MOVI <Vd>.<T>, #<imm8>, MSL #<amount>
57 .irp T, 2s, 4s
58 .irp amount, 8, 16
59 // Have to break into four chunks to avoid "Fatal error: macros nested
60 // too deeply".
61 all_8bit_imm_movi_sft v7.\T, 0, 63, MSL, \amount
62 all_8bit_imm_movi_sft v7.\T, 64, 127, MSL, \amount
63 all_8bit_imm_movi_sft v7.\T, 128, 191, MSL, \amount
64 all_8bit_imm_movi_sft v7.\T, 192, 255, MSL, \amount
65 .endr
66 .endr
67
68
69 // Shift zeros, per halfword
70 // MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}
71 .irp T, 4h, 8h
72 .irp amount, 0, 8
73 all_8bit_imm_movi_sft v7.\T, 0, 63, LSL, \amount
74 all_8bit_imm_movi_sft v7.\T, 64, 127, LSL, \amount
75 all_8bit_imm_movi_sft v7.\T, 128, 191, LSL, \amount
76 all_8bit_imm_movi_sft v7.\T, 192, 255, LSL, \amount
77 all_8bit_imm_movi v15.\T, 0, 63
78 all_8bit_imm_movi v15.\T, 64, 127
79 all_8bit_imm_movi v15.\T, 128, 191
80 all_8bit_imm_movi v15.\T, 192, 255
81 .endr
82 .endr
83
84
85 // Shift zeros, per word
86 // MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}
87 .irp T, 2s, 4s
88 .irp amount, 0, 8, 16, 24
89 all_8bit_imm_movi_sft v7.\T, 0, 63, LSL, \amount
90 all_8bit_imm_movi_sft v7.\T, 64, 127, LSL, \amount
91 all_8bit_imm_movi_sft v7.\T, 128, 191, LSL, \amount
92 all_8bit_imm_movi_sft v7.\T, 192, 255, LSL, \amount
93 all_8bit_imm_movi v15.\T, 0, 63
94 all_8bit_imm_movi v15.\T, 64, 127
95 all_8bit_imm_movi v15.\T, 128, 191
96 all_8bit_imm_movi v15.\T, 192, 255
97 .endr
98 .endr
99
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100 // Shift zeros, per byte
101 // MOVI <Vd>.<T>, #<imm8>, LSL #0
102 // This used to be a programmer-friendly feature (allowing LSL #0),
103 // but it is now part of the architecture specification.
104 .irp T, 8b, 16b
105 all_8bit_imm_movi_sft v7.\T, 0, 63, LSL, 0
106 all_8bit_imm_movi_sft v7.\T, 64, 127, LSL, 0
107 all_8bit_imm_movi_sft v7.\T, 128, 191, LSL, 0
108 all_8bit_imm_movi_sft v7.\T, 192, 255, LSL, 0
109 .endr
110
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111 movi v0.2d, 18446744073709551615
112 movi v0.2d, -1
113 movi v0.2d, bignum
114 movi d31, 18446744073709551615
115.set bignum, 0xffffffffffffffff
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116
117 // Allow -128 to 255 in #<imm8>
118 movi v3.8b, -128
119 movi v3.8b, -127
120 movi v3.8b, -1