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Commit | Line | Data |
---|---|---|
01a4d082 PW |
1 | #name: SME extension (LD1x instructions) |
2 | #as: -march=armv8-a+sme | |
3 | #objdump: -dr | |
4 | ||
5 | .*: file format .* | |
6 | ||
7 | Disassembly of section \.text: | |
8 | ||
9 | 0+ <.*>: | |
10 | 0: e01f0000 ld1b {za0h.b\[w12, 0\]}, p0/z, \[x0, xzr\] | |
11 | 4: e01f03e0 ld1b {za0h.b\[w12, 0\]}, p0/z, \[sp, xzr\] | |
12 | 8: e00003e0 ld1b {za0h.b\[w12, 0\]}, p0/z, \[sp, x0\] | |
13 | c: e01f7e2f ld1b {za0h.b\[w15, 15\]}, p7/z, \[x17, xzr\] | |
14 | 10: e01f7fef ld1b {za0h.b\[w15, 15\]}, p7/z, \[sp, xzr\] | |
15 | 14: e0117fef ld1b {za0h.b\[w15, 15\]}, p7/z, \[sp, x17\] | |
16 | 18: e05f0000 ld1h {za0h.h\[w12, 0\]}, p0/z, \[x0, xzr, lsl #1\] | |
17 | 1c: e05f03e0 ld1h {za0h.h\[w12, 0\]}, p0/z, \[sp, xzr, lsl #1\] | |
18 | 20: e0400000 ld1h {za0h.h\[w12, 0\]}, p0/z, \[x0, x0, lsl #1\] | |
19 | 24: e04003e0 ld1h {za0h.h\[w12, 0\]}, p0/z, \[sp, x0, lsl #1\] | |
20 | 28: e05f7e2f ld1h {za1h.h\[w15, 7\]}, p7/z, \[x17, xzr, lsl #1\] | |
21 | 2c: e05f7fef ld1h {za1h.h\[w15, 7\]}, p7/z, \[sp, xzr, lsl #1\] | |
22 | 30: e0517c0f ld1h {za1h.h\[w15, 7\]}, p7/z, \[x0, x17, lsl #1\] | |
23 | 34: e0517fef ld1h {za1h.h\[w15, 7\]}, p7/z, \[sp, x17, lsl #1\] | |
24 | 38: e09f0000 ld1w {za0h.s\[w12, 0\]}, p0/z, \[x0, xzr, lsl #2\] | |
25 | 3c: e09f03e0 ld1w {za0h.s\[w12, 0\]}, p0/z, \[sp, xzr, lsl #2\] | |
26 | 40: e0800000 ld1w {za0h.s\[w12, 0\]}, p0/z, \[x0, x0, lsl #2\] | |
27 | 44: e08003e0 ld1w {za0h.s\[w12, 0\]}, p0/z, \[sp, x0, lsl #2\] | |
28 | 48: e09f7e2f ld1w {za3h.s\[w15, 3\]}, p7/z, \[x17, xzr, lsl #2\] | |
29 | 4c: e09f7fef ld1w {za3h.s\[w15, 3\]}, p7/z, \[sp, xzr, lsl #2\] | |
30 | 50: e0917c0f ld1w {za3h.s\[w15, 3\]}, p7/z, \[x0, x17, lsl #2\] | |
31 | 54: e0917fef ld1w {za3h.s\[w15, 3\]}, p7/z, \[sp, x17, lsl #2\] | |
32 | 58: e0df0000 ld1d {za0h.d\[w12, 0\]}, p0/z, \[x0, xzr, lsl #3\] | |
33 | 5c: e0df03e0 ld1d {za0h.d\[w12, 0\]}, p0/z, \[sp, xzr, lsl #3\] | |
34 | 60: e0c00000 ld1d {za0h.d\[w12, 0\]}, p0/z, \[x0, x0, lsl #3\] | |
35 | 64: e0c003e0 ld1d {za0h.d\[w12, 0\]}, p0/z, \[sp, x0, lsl #3\] | |
36 | 68: e0df7e2f ld1d {za7h.d\[w15, 1\]}, p7/z, \[x17, xzr, lsl #3\] | |
37 | 6c: e0df7fef ld1d {za7h.d\[w15, 1\]}, p7/z, \[sp, xzr, lsl #3\] | |
38 | 70: e0d17c0f ld1d {za7h.d\[w15, 1\]}, p7/z, \[x0, x17, lsl #3\] | |
39 | 74: e0d17fef ld1d {za7h.d\[w15, 1\]}, p7/z, \[sp, x17, lsl #3\] | |
40 | 78: e1df0000 ld1q {za0h.q\[w12, 0\]}, p0/z, \[x0, xzr, lsl #4\] | |
41 | 7c: e1df03e0 ld1q {za0h.q\[w12, 0\]}, p0/z, \[sp, xzr, lsl #4\] | |
42 | 80: e1c00000 ld1q {za0h.q\[w12, 0\]}, p0/z, \[x0, x0, lsl #4\] | |
43 | 84: e1c003e0 ld1q {za0h.q\[w12, 0\]}, p0/z, \[sp, x0, lsl #4\] | |
44 | 88: e1df7e2f ld1q {za15h.q\[w15, 0\]}, p7/z, \[x17, xzr, lsl #4\] | |
45 | 8c: e1df7fef ld1q {za15h.q\[w15, 0\]}, p7/z, \[sp, xzr, lsl #4\] | |
46 | 90: e1d17c0f ld1q {za15h.q\[w15, 0\]}, p7/z, \[x0, x17, lsl #4\] | |
47 | 94: e1d17fef ld1q {za15h.q\[w15, 0\]}, p7/z, \[sp, x17, lsl #4\] | |
48 | 98: e01f8000 ld1b {za0v.b\[w12, 0\]}, p0/z, \[x0, xzr\] | |
49 | 9c: e01f83e0 ld1b {za0v.b\[w12, 0\]}, p0/z, \[sp, xzr\] | |
50 | a0: e00083e0 ld1b {za0v.b\[w12, 0\]}, p0/z, \[sp, x0\] | |
51 | a4: e01ffe2f ld1b {za0v.b\[w15, 15\]}, p7/z, \[x17, xzr\] | |
52 | a8: e01fffef ld1b {za0v.b\[w15, 15\]}, p7/z, \[sp, xzr\] | |
53 | ac: e011ffef ld1b {za0v.b\[w15, 15\]}, p7/z, \[sp, x17\] | |
54 | b0: e05f8000 ld1h {za0v.h\[w12, 0\]}, p0/z, \[x0, xzr, lsl #1\] | |
55 | b4: e05f83e0 ld1h {za0v.h\[w12, 0\]}, p0/z, \[sp, xzr, lsl #1\] | |
56 | b8: e0408000 ld1h {za0v.h\[w12, 0\]}, p0/z, \[x0, x0, lsl #1\] | |
57 | bc: e04083e0 ld1h {za0v.h\[w12, 0\]}, p0/z, \[sp, x0, lsl #1\] | |
58 | c0: e05ffe2f ld1h {za1v.h\[w15, 7\]}, p7/z, \[x17, xzr, lsl #1\] | |
59 | c4: e05fffef ld1h {za1v.h\[w15, 7\]}, p7/z, \[sp, xzr, lsl #1\] | |
60 | c8: e051fc0f ld1h {za1v.h\[w15, 7\]}, p7/z, \[x0, x17, lsl #1\] | |
61 | cc: e051ffef ld1h {za1v.h\[w15, 7\]}, p7/z, \[sp, x17, lsl #1\] | |
62 | d0: e09f8000 ld1w {za0v.s\[w12, 0\]}, p0/z, \[x0, xzr, lsl #2\] | |
63 | d4: e09f83e0 ld1w {za0v.s\[w12, 0\]}, p0/z, \[sp, xzr, lsl #2\] | |
64 | d8: e0808000 ld1w {za0v.s\[w12, 0\]}, p0/z, \[x0, x0, lsl #2\] | |
65 | dc: e08083e0 ld1w {za0v.s\[w12, 0\]}, p0/z, \[sp, x0, lsl #2\] | |
66 | e0: e09ffe2f ld1w {za3v.s\[w15, 3\]}, p7/z, \[x17, xzr, lsl #2\] | |
67 | e4: e09fffef ld1w {za3v.s\[w15, 3\]}, p7/z, \[sp, xzr, lsl #2\] | |
68 | e8: e091fc0f ld1w {za3v.s\[w15, 3\]}, p7/z, \[x0, x17, lsl #2\] | |
69 | ec: e091ffef ld1w {za3v.s\[w15, 3\]}, p7/z, \[sp, x17, lsl #2\] | |
70 | f0: e0df8000 ld1d {za0v.d\[w12, 0\]}, p0/z, \[x0, xzr, lsl #3\] | |
71 | f4: e0df83e0 ld1d {za0v.d\[w12, 0\]}, p0/z, \[sp, xzr, lsl #3\] | |
72 | f8: e0c08000 ld1d {za0v.d\[w12, 0\]}, p0/z, \[x0, x0, lsl #3\] | |
73 | fc: e0c083e0 ld1d {za0v.d\[w12, 0\]}, p0/z, \[sp, x0, lsl #3\] | |
74 | 100: e0dffe2f ld1d {za7v.d\[w15, 1\]}, p7/z, \[x17, xzr, lsl #3\] | |
75 | 104: e0dfffef ld1d {za7v.d\[w15, 1\]}, p7/z, \[sp, xzr, lsl #3\] | |
76 | 108: e0d1fc0f ld1d {za7v.d\[w15, 1\]}, p7/z, \[x0, x17, lsl #3\] | |
77 | 10c: e0d1ffef ld1d {za7v.d\[w15, 1\]}, p7/z, \[sp, x17, lsl #3\] | |
78 | 110: e1df8000 ld1q {za0v.q\[w12, 0\]}, p0/z, \[x0, xzr, lsl #4\] | |
79 | 114: e1df83e0 ld1q {za0v.q\[w12, 0\]}, p0/z, \[sp, xzr, lsl #4\] | |
80 | 118: e1c08000 ld1q {za0v.q\[w12, 0\]}, p0/z, \[x0, x0, lsl #4\] | |
81 | 11c: e1c083e0 ld1q {za0v.q\[w12, 0\]}, p0/z, \[sp, x0, lsl #4\] | |
82 | 120: e1dffe2f ld1q {za15v.q\[w15, 0\]}, p7/z, \[x17, xzr, lsl #4\] | |
83 | 124: e1dfffef ld1q {za15v.q\[w15, 0\]}, p7/z, \[sp, xzr, lsl #4\] | |
84 | 128: e1d1fc0f ld1q {za15v.q\[w15, 0\]}, p7/z, \[x0, x17, lsl #4\] | |
85 | 12c: e1d1ffef ld1q {za15v.q\[w15, 0\]}, p7/z, \[sp, x17, lsl #4\] | |
86 | 130: e1c083e0 ld1q {za0v.q\[w12, 0\]}, p0/z, \[sp, x0, lsl #4\] | |
87 | 134: e1dffe2f ld1q {za15v.q\[w15, 0\]}, p7/z, \[x17, xzr, lsl #4\] | |
88 | 138: e000ffef ld1b {za0v.b\[w15, 15\]}, p7/z, \[sp, x0\] | |
89 | 13c: e0010000 ld1b {za0h.b\[w12, 0\]}, p0/z, \[x0, x1\] | |
90 | 140: e0410000 ld1h {za0h.h\[w12, 0\]}, p0/z, \[x0, x1, lsl #1\] | |
91 | 144: e0819c0f ld1w {za3v.s\[w12, 3\]}, p7/z, \[x0, x1, lsl #2\] | |
92 | 148: e0c10000 ld1d {za0h.d\[w12, 0\]}, p0/z, \[x0, x1, lsl #3\] | |
93 | 14c: e1c18000 ld1q {za0v.q\[w12, 0\]}, p0/z, \[x0, x1, lsl #4\] |