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aarch64; Add support for vector offset ranges
[thirdparty/binutils-gdb.git] / gas / testsuite / gas / aarch64 / sme-7-illegal.s
CommitLineData
01a4d082
PW
1/* Scalable Matrix Extension (SME). */
2
3/* Load vector to ZA array. */
4ldr za[w11, 0], [x0]
5ldr za[w12, 1], [sp, x0]
6ldr za[w12, 0], [sp, #1, mul vl]
7ldr za[w13, 9], [x17, #19, mul vl]
8ldr za[w13, 21], [x17, #21, mul vl]
9ldr za[w15, 32], [x17, #15, mul vl]
10ldr za[w16, 15], [sp, #15, mul vl]
11ldr za[w12, 0], [x0, #0, mul #1]
12ldr za[w13, 0], [sp, #0, mul #2]
13ldr za[w14, 9], [x17, #9, mul #3]
14ldr za[w15, 15], [sp, #15, mul #4]
15
16/* Store vector from ZA array. */
17str za[w11, 0], [x0]
18str za[w12, 1], [sp, x0]
19str za[w12, 0], [sp, #1, mul vl]
20str za[w13, 9], [x17, #19, mul vl]
21str za[w13, 21], [x17, #21, mul vl]
22str za[w15, 32], [x17, #15, mul vl]
23str za[w16, 15], [sp, #15, mul vl]
24str za[w12, 0], [x0, #0, mul #1]
25str za[w13, 0], [sp, #0, mul #2]
26str za[w14, 9], [x17, #9, mul #3]
27str za[w15, 15], [sp, #15, mul #4]
28
29/* Operands indexes are tied. */
30ldr za[w13, 13], [x17, #23, mul vl]
31str za[w13, 13], [x17, #23, mul vl]
32ldr za[w13, 23], [x17, #13, mul vl]
33str za[w13, 23], [x17, #13, mul vl]
34ldr za[w13, 16], [x17, #16, mul vl]
35str za[w13, 16], [x17, #16, mul vl]
36ldr za[w13, -1], [x17, #1, mul vl]
37str za[w13, -1], [x17, #1, mul vl]
38ldr za[w13, 1], [x17, #-1, mul vl]
39str za[w13, 1], [x17, #-1, mul vl]
9d862382
RS
40
41ldr za.b[w12, 0], [x0]
42ldr za.h[w12, 0], [x0]
43ldr za.s[w12, 0], [x0]
44ldr za.d[w12, 0], [x0]
45ldr za.q[w12, 0], [x0]
46ldr za/z[w12, 0], [x0]
47ldr za.2b[w12, 0], [x0]
e426521e
RS
48
49ldr za0[w12, 0], [x0]
50ldr za0.b[w12, 0], [x0]
51ldr za0h[w12, 0], [x0]
52ldr za0h.h[w12, 0], [x0]
53ldr za0v[w12, 0], [x0]
54ldr za0v.s[w12, 0], [x0]
e2dc4040
RS
55
56ldr za[w12, 0, vgx2], [x0]
57ldr za[w12, 0, vgx4], [x0]
58ldr za[w12, 0, vgx8], [x0]
59
60str za[w12, 0, vgx2], [x0]
61str za[w12, 0, vgx4], [x0]
62str za[w12, 0, vgx8], [x0]
63
64ldr za.b[w12, 0, vgx2], [x0]
65str za.b[w12, 0, vgx4], [x0]
586c6281
RS
66
67ldr za[w12, 0:1], [x0]
68str za[w12, 0:2, vgx4], [x0]
69
70ldr za.b[w12, 0:1], [x0]
71str za.b[w12, 0:2, vgx4], [x0]