projects / thirdparty / binutils-gdb.git / blame
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| a06ea964 NC |
1 | /* sysreg-1.s Test file for AArch64 system registers. |
| 2 | ||
| 250d07de | 3 | Copyright (C) 2011-2021 Free Software Foundation, Inc. |
| a06ea964 NC |
4 | Contributed by ARM Ltd. |
| 5 | ||
| 6 | This file is part of GAS. | |
| 7 | ||
| 8 | GAS is free software; you can redistribute it and/or modify | |
| 9 | it under the terms of the GNU General Public License as published by | |
| 10 | the Free Software Foundation; either version 3 of the license, or | |
| 11 | (at your option) any later version. | |
| 12 | ||
| 13 | GAS is distributed in the hope that it will be useful, | |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | GNU General Public License for more details. | |
| 17 | ||
| 18 | You should have received a copy of the GNU General Public License | |
| 19 | along with this program; see the file COPYING3. If not, | |
| 20 | see <http://www.gnu.org/licenses/>. */ | |
| 21 | ||
| 22 | .macro rw_sys_reg sys_reg xreg r w | |
| 23 | .ifc \w, 1 | |
| 24 | msr \sys_reg, \xreg | |
| 25 | .endif | |
| 26 | .ifc \r, 1 | |
| 27 | mrs \xreg, \sys_reg | |
| 28 | .endif | |
| 29 | .endm | |
| 30 | ||
| 31 | .text | |
| 32 | ||
| 33 | rw_sys_reg sys_reg=id_aa64afr0_el1 xreg=x7 r=1 w=0 | |
| 34 | rw_sys_reg sys_reg=id_aa64afr1_el1 xreg=x7 r=1 w=0 | |
| 35 | rw_sys_reg sys_reg=mvfr2_el1 xreg=x7 r=1 w=0 | |
| 36 | rw_sys_reg sys_reg=dlr_el0 xreg=x7 r=1 w=1 | |
| 37 | rw_sys_reg sys_reg=dspsr_el0 xreg=x7 r=1 w=1 | |
| 38 | ||
| 39 | rw_sys_reg sys_reg=sder32_el3 xreg=x7 r=1 w=1 | |
| 40 | rw_sys_reg sys_reg=mdcr_el3 xreg=x7 r=1 w=1 | |
| 41 | ||
| 42 | rw_sys_reg sys_reg=mdccint_el1 xreg=x7 r=1 w=1 | |
| 43 | ||
| 44 | rw_sys_reg sys_reg=dbgvcr32_el2 xreg=x7 r=1 w=1 | |
| 45 | ||
| 46 | rw_sys_reg sys_reg=fpexc32_el2 xreg=x7 r=1 w=1 | |
| 47 | ||
| 48 | rw_sys_reg sys_reg=teecr32_el1 xreg=x7 r=1 w=1 | |
| 49 | rw_sys_reg sys_reg=teehbr32_el1 xreg=x7 r=1 w=1 | |
| 50 | ||
| 51 | rw_sys_reg sys_reg=cntp_tval_el0 xreg=x7 r=1 w=1 | |
| 52 | rw_sys_reg sys_reg=cntp_ctl_el0 xreg=x7 r=1 w=1 | |
| 53 | rw_sys_reg sys_reg=cntp_cval_el0 xreg=x7 r=1 w=1 | |
| 54 | rw_sys_reg sys_reg=cntps_tval_el1 xreg=x7 r=1 w=1 | |
| 55 | rw_sys_reg sys_reg=cntps_ctl_el1 xreg=x7 r=1 w=1 | |
| 56 | rw_sys_reg sys_reg=cntps_cval_el1 xreg=x7 r=1 w=1 | |
| 57 | ||
| 58 | rw_sys_reg sys_reg=pmccntr_el0 xreg=x7 r=1 w=1 | |
| 59 | ||
| 60 | rw_sys_reg sys_reg=pmevcntr0_el0 xreg=x7 r=1 w=1 | |
| 61 | rw_sys_reg sys_reg=pmevcntr1_el0 xreg=x7 r=1 w=1 | |
| 62 | rw_sys_reg sys_reg=pmevcntr2_el0 xreg=x7 r=1 w=1 | |
| 63 | rw_sys_reg sys_reg=pmevcntr3_el0 xreg=x7 r=1 w=1 | |
| 64 | rw_sys_reg sys_reg=pmevcntr4_el0 xreg=x7 r=1 w=1 | |
| 65 | rw_sys_reg sys_reg=pmevcntr5_el0 xreg=x7 r=1 w=1 | |
| 66 | rw_sys_reg sys_reg=pmevcntr6_el0 xreg=x7 r=1 w=1 | |
| 67 | rw_sys_reg sys_reg=pmevcntr7_el0 xreg=x7 r=1 w=1 | |
| 68 | rw_sys_reg sys_reg=pmevcntr8_el0 xreg=x7 r=1 w=1 | |
| 69 | rw_sys_reg sys_reg=pmevcntr9_el0 xreg=x7 r=1 w=1 | |
| 70 | rw_sys_reg sys_reg=pmevcntr10_el0 xreg=x7 r=1 w=1 | |
| 71 | rw_sys_reg sys_reg=pmevcntr11_el0 xreg=x7 r=1 w=1 | |
| 72 | rw_sys_reg sys_reg=pmevcntr12_el0 xreg=x7 r=1 w=1 | |
| 73 | rw_sys_reg sys_reg=pmevcntr13_el0 xreg=x7 r=1 w=1 | |
| 74 | rw_sys_reg sys_reg=pmevcntr14_el0 xreg=x7 r=1 w=1 | |
| 75 | rw_sys_reg sys_reg=pmevcntr15_el0 xreg=x7 r=1 w=1 | |
| 76 | rw_sys_reg sys_reg=pmevcntr16_el0 xreg=x7 r=1 w=1 | |
| 77 | rw_sys_reg sys_reg=pmevcntr17_el0 xreg=x7 r=1 w=1 | |
| 78 | rw_sys_reg sys_reg=pmevcntr18_el0 xreg=x7 r=1 w=1 | |
| 79 | rw_sys_reg sys_reg=pmevcntr19_el0 xreg=x7 r=1 w=1 | |
| 80 | rw_sys_reg sys_reg=pmevcntr20_el0 xreg=x7 r=1 w=1 | |
| 81 | rw_sys_reg sys_reg=pmevcntr21_el0 xreg=x7 r=1 w=1 | |
| 82 | rw_sys_reg sys_reg=pmevcntr22_el0 xreg=x7 r=1 w=1 | |
| 83 | rw_sys_reg sys_reg=pmevcntr23_el0 xreg=x7 r=1 w=1 | |
| 84 | rw_sys_reg sys_reg=pmevcntr24_el0 xreg=x7 r=1 w=1 | |
| 85 | rw_sys_reg sys_reg=pmevcntr25_el0 xreg=x7 r=1 w=1 | |
| 86 | rw_sys_reg sys_reg=pmevcntr26_el0 xreg=x7 r=1 w=1 | |
| 87 | rw_sys_reg sys_reg=pmevcntr27_el0 xreg=x7 r=1 w=1 | |
| 88 | rw_sys_reg sys_reg=pmevcntr28_el0 xreg=x7 r=1 w=1 | |
| 89 | rw_sys_reg sys_reg=pmevcntr29_el0 xreg=x7 r=1 w=1 | |
| 90 | rw_sys_reg sys_reg=pmevcntr30_el0 xreg=x7 r=1 w=1 | |
| 91 | rw_sys_reg sys_reg=pmevtyper0_el0 xreg=x7 r=1 w=1 | |
| 92 | rw_sys_reg sys_reg=pmevtyper1_el0 xreg=x7 r=1 w=1 | |
| 93 | rw_sys_reg sys_reg=pmevtyper2_el0 xreg=x7 r=1 w=1 | |
| 94 | rw_sys_reg sys_reg=pmevtyper3_el0 xreg=x7 r=1 w=1 | |
| 95 | rw_sys_reg sys_reg=pmevtyper4_el0 xreg=x7 r=1 w=1 | |
| 96 | rw_sys_reg sys_reg=pmevtyper5_el0 xreg=x7 r=1 w=1 | |
| 97 | rw_sys_reg sys_reg=pmevtyper6_el0 xreg=x7 r=1 w=1 | |
| 98 | rw_sys_reg sys_reg=pmevtyper7_el0 xreg=x7 r=1 w=1 | |
| 99 | rw_sys_reg sys_reg=pmevtyper8_el0 xreg=x7 r=1 w=1 | |
| 100 | rw_sys_reg sys_reg=pmevtyper9_el0 xreg=x7 r=1 w=1 | |
| 101 | rw_sys_reg sys_reg=pmevtyper10_el0 xreg=x7 r=1 w=1 | |
| 102 | rw_sys_reg sys_reg=pmevtyper11_el0 xreg=x7 r=1 w=1 | |
| 103 | rw_sys_reg sys_reg=pmevtyper12_el0 xreg=x7 r=1 w=1 | |
| 104 | rw_sys_reg sys_reg=pmevtyper13_el0 xreg=x7 r=1 w=1 | |
| 105 | rw_sys_reg sys_reg=pmevtyper14_el0 xreg=x7 r=1 w=1 | |
| 106 | rw_sys_reg sys_reg=pmevtyper15_el0 xreg=x7 r=1 w=1 | |
| 107 | rw_sys_reg sys_reg=pmevtyper16_el0 xreg=x7 r=1 w=1 | |
| 108 | rw_sys_reg sys_reg=pmevtyper17_el0 xreg=x7 r=1 w=1 | |
| 109 | rw_sys_reg sys_reg=pmevtyper18_el0 xreg=x7 r=1 w=1 | |
| 110 | rw_sys_reg sys_reg=pmevtyper19_el0 xreg=x7 r=1 w=1 | |
| 111 | rw_sys_reg sys_reg=pmevtyper20_el0 xreg=x7 r=1 w=1 | |
| 112 | rw_sys_reg sys_reg=pmevtyper21_el0 xreg=x7 r=1 w=1 | |
| 113 | rw_sys_reg sys_reg=pmevtyper22_el0 xreg=x7 r=1 w=1 | |
| 114 | rw_sys_reg sys_reg=pmevtyper23_el0 xreg=x7 r=1 w=1 | |
| 115 | rw_sys_reg sys_reg=pmevtyper24_el0 xreg=x7 r=1 w=1 | |
| 116 | rw_sys_reg sys_reg=pmevtyper25_el0 xreg=x7 r=1 w=1 | |
| 117 | rw_sys_reg sys_reg=pmevtyper26_el0 xreg=x7 r=1 w=1 | |
| 118 | rw_sys_reg sys_reg=pmevtyper27_el0 xreg=x7 r=1 w=1 | |
| 119 | rw_sys_reg sys_reg=pmevtyper28_el0 xreg=x7 r=1 w=1 | |
| 120 | rw_sys_reg sys_reg=pmevtyper29_el0 xreg=x7 r=1 w=1 | |
| 121 | rw_sys_reg sys_reg=pmevtyper30_el0 xreg=x7 r=1 w=1 | |
| 122 | rw_sys_reg sys_reg=pmccfiltr_el0 xreg=x7 r=1 w=1 | |
| 123 | ||
| 124 | rw_sys_reg sys_reg=tpidrro_el0 xreg=x7 r=1 w=1 | |
| 125 | rw_sys_reg sys_reg=tpidr_el0 xreg=x7 r=1 w=1 | |
| 126 | rw_sys_reg sys_reg=cntfrq_el0 xreg=x7 r=1 w=1 | |
| 127 | ||
| 128 | // | |
| 129 | // Macros to generate MRS and MSR with all the implementation defined | |
| 130 | // system registers in the form of S3_<op1>_<Cn>_<Cm>_<op2>. | |
| 131 | ||
| 132 | .altmacro | |
| 133 | .macro all_op2 op1, crn, crm, from=0, to=7 | |
| 134 | rw_sys_reg S3_\op1\()_C\crn\()_C\crm\()_\from x15 1 1 | |
| 135 | .if (\to-\from > 0) | |
| 136 | all_op2 \op1, \crn, \crm, %(\from+1), \to | |
| 137 | .endif | |
| 138 | .endm | |
| 139 | ||
| 140 | .macro all_crm op1, crn, from=0, to=15 | |
| 141 | all_op2 \op1, \crn, \from, 0, 7 | |
| 142 | .if (\to-\from > 0) | |
| 143 | all_crm \op1, \crn, %(\from+1), \to | |
| 144 | .endif | |
| 145 | .endm | |
| 146 | ||
| 147 | .macro all_imple_defined from=0, to=7 | |
| 148 | .irp crn, 11, 15 | |
| 149 | all_crm \from, \crn, 0, 15 | |
| 150 | .endr | |
| 151 | .if \to-\from | |
| 152 | all_imple_defined %(\from+1), \to | |
| 153 | .endif | |
| 154 | .endm | |
| 155 | ||
| 156 | all_imple_defined 0, 7 | |
| 157 | .noaltmacro | |
| 158 | ||
| 159 | rw_sys_reg sys_reg=dbgdtr_el0 xreg=x15 r=1 w=1 | |
| 160 | rw_sys_reg sys_reg=dbgdtrrx_el0 xreg=x15 r=1 w=0 | |
| b7a54b55 YZ |
161 | |
| 162 | rw_sys_reg sys_reg=rmr_el1 xreg=x15 r=1 w=1 | |
| 163 | rw_sys_reg sys_reg=rmr_el2 xreg=x15 r=1 w=1 | |
| 164 | rw_sys_reg sys_reg=rmr_el3 xreg=x15 r=1 w=1 | |
| 49eec193 YZ |
165 | |
| 166 | rw_sys_reg sys_reg=spsr_el1 xreg=x15 r=1 w=1 | |
| 167 | rw_sys_reg sys_reg=spsr_el2 xreg=x15 r=1 w=1 | |
| 168 | rw_sys_reg sys_reg=spsr_el3 xreg=x15 r=1 w=1 | |
| df7b4545 JW |
169 | |
| 170 | rw_sys_reg sys_reg=s0_0_C0_C0_0 xreg=x15 r=1 w=1 | |
| 171 | rw_sys_reg sys_reg=s1_7_C15_C15_7 xreg=x27 r=1 w=1 | |
| 172 | rw_sys_reg sys_reg=s2_4_C6_C8_0 xreg=x14 r=1 w=1 | |
| 173 | rw_sys_reg sys_reg=s1_2_C14_C4_2 xreg=x4 r=1 w=1 | |
| 174 | rw_sys_reg sys_reg=s0_1_C13_C1_3 xreg=x7 r=1 w=1 |