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Commit | Line | Data |
---|---|---|
35c228db AV |
1 | .syntax unified |
2 | .thumb | |
3 | vst20.8 {q0, q2}, [r0] | |
4 | vst20.8 {q0, q1, q2}, [r0] | |
5 | vst20.8 {q0}, [r0] | |
6 | vst20.8 {q0, q1}, [pc] | |
7 | vst20.8 {q0, q1}, [pc]! | |
8 | vst20.8 {q0, q1}, [sp]! | |
9 | vst20.8 {q3, q2}, [r0] | |
10 | vst20.64 {q0, q1}, [r0] | |
11 | vst21.8 {q0, q2}, [r0] | |
12 | vst21.8 {q0, q1, q2}, [r0] | |
13 | vst21.8 {q0}, [r0] | |
14 | vst21.8 {q0, q1}, [pc] | |
15 | vst21.8 {q0, q1}, [pc]! | |
16 | vst21.8 {q0, q1}, [sp]! | |
17 | vst21.8 {q3, q2}, [r0] | |
18 | vst21.64 {q0, q1}, [r0] | |
19 | vst40.8 {q0, q2, q3, q4}, [r0] | |
20 | vst40.8 {q0, q1, q3, q4}, [r0] | |
21 | vst40.8 {q0, q1, q2, q4}, [r0] | |
22 | vst40.8 {q3, q1, q2, q3}, [r0] | |
23 | vst40.8 {q0, q1, q2, q3, q4}, [r0] | |
24 | vst40.8 {q0, q1, q2}, [r0] | |
25 | vst40.8 {q0, q1}, [r0] | |
26 | vst40.8 {q0}, [r0] | |
27 | vst40.8 {q0, q1, q2, q3}, [pc] | |
28 | vst40.8 {q0, q1, q2, q3}, [pc]! | |
29 | vst40.8 {q0, q1, q2, q3}, [sp]! | |
30 | vst40.64 {q0, q1, q2, q3}, [r0] | |
31 | vst41.8 {q0, q2, q3, q4}, [r0] | |
32 | vst41.8 {q0, q1, q3, q4}, [r0] | |
33 | vst41.8 {q0, q1, q2, q4}, [r0] | |
34 | vst41.8 {q3, q1, q2, q3}, [r0] | |
35 | vst41.8 {q0, q1, q2, q3, q4}, [r0] | |
36 | vst41.8 {q0, q1, q2}, [r0] | |
37 | vst41.8 {q0, q1}, [r0] | |
38 | vst41.8 {q0}, [r0] | |
39 | vst41.8 {q0, q1, q2, q3}, [pc] | |
40 | vst41.8 {q0, q1, q2, q3}, [pc]! | |
41 | vst41.8 {q0, q1, q2, q3}, [sp]! | |
42 | vst41.64 {q0, q1, q2, q3}, [r0] | |
43 | vst42.8 {q0, q2, q3, q4}, [r0] | |
44 | vst42.8 {q0, q1, q3, q4}, [r0] | |
45 | vst42.8 {q0, q1, q2, q4}, [r0] | |
46 | vst42.8 {q3, q1, q2, q3}, [r0] | |
47 | vst42.8 {q0, q1, q2, q3, q4}, [r0] | |
48 | vst42.8 {q0, q1, q2}, [r0] | |
49 | vst42.8 {q0, q1}, [r0] | |
50 | vst42.8 {q0}, [r0] | |
51 | vst42.8 {q0, q1, q2, q3}, [pc] | |
52 | vst42.8 {q0, q1, q2, q3}, [pc]! | |
53 | vst42.8 {q0, q1, q2, q3}, [sp]! | |
54 | vst42.64 {q0, q1, q2, q3}, [r0] | |
55 | vst43.8 {q0, q2, q3, q4}, [r0] | |
56 | vst43.8 {q0, q1, q3, q4}, [r0] | |
57 | vst43.8 {q0, q1, q2, q4}, [r0] | |
58 | vst43.8 {q3, q1, q2, q3}, [r0] | |
59 | vst43.8 {q0, q1, q2, q3, q4}, [r0] | |
60 | vst43.8 {q0, q1, q2}, [r0] | |
61 | vst43.8 {q0, q1}, [r0] | |
62 | vst43.8 {q0}, [r0] | |
63 | vst43.8 {q0, q1, q2, q3}, [pc] | |
64 | vst43.8 {q0, q1, q2, q3}, [pc]! | |
65 | vst43.8 {q0, q1, q2, q3}, [sp]! | |
66 | vst43.64 {q0, q1, q2, q3}, [r0] | |
67 | vst1.8 {q0, q1}, [r0] | |
68 | vst2.8 {q0, q1}, [r0] | |
69 | vst3.8 {q0, q1}, [r0] | |
70 | vst4.8 {q0, q1}, [r0] | |
71 | vst23.32 {q0, q1}, [r0] | |
72 | vst44.32 {q0, q1, q2, q3}, [r0] | |
73 | vld20.8 {q0, q2}, [r0] | |
74 | vld20.8 {q0, q1, q2}, [r0] | |
75 | vld20.8 {q0}, [r0] | |
76 | vld20.8 {q0, q1}, [pc] | |
77 | vld20.8 {q0, q1}, [pc]! | |
78 | vld20.8 {q0, q1}, [sp]! | |
79 | vld20.8 {q3, q2}, [r0] | |
80 | vld20.64 {q0, q1}, [r0] | |
81 | vld21.8 {q0, q2}, [r0] | |
82 | vld21.8 {q0, q1, q2}, [r0] | |
83 | vld21.8 {q0}, [r0] | |
84 | vld21.8 {q0, q1}, [pc] | |
85 | vld21.8 {q0, q1}, [pc]! | |
86 | vld21.8 {q0, q1}, [sp]! | |
87 | vld21.8 {q3, q2}, [r0] | |
88 | vld21.64 {q0, q1}, [r0] | |
89 | vld40.8 {q0, q2, q3, q4}, [r0] | |
90 | vld40.8 {q0, q1, q3, q4}, [r0] | |
91 | vld40.8 {q0, q1, q2, q4}, [r0] | |
92 | vld40.8 {q3, q1, q2, q3}, [r0] | |
93 | vld40.8 {q0, q1, q2, q3, q4}, [r0] | |
94 | vld40.8 {q0, q1, q2}, [r0] | |
95 | vld40.8 {q0, q1}, [r0] | |
96 | vld40.8 {q0}, [r0] | |
97 | vld40.8 {q0, q1, q2, q3}, [pc] | |
98 | vld40.8 {q0, q1, q2, q3}, [pc]! | |
99 | vld40.8 {q0, q1, q2, q3}, [sp]! | |
100 | vld40.64 {q0, q1, q2, q3}, [r0] | |
101 | vld41.8 {q0, q2, q3, q4}, [r0] | |
102 | vld41.8 {q0, q1, q3, q4}, [r0] | |
103 | vld41.8 {q0, q1, q2, q4}, [r0] | |
104 | vld41.8 {q3, q1, q2, q3}, [r0] | |
105 | vld41.8 {q0, q1, q2, q3, q4}, [r0] | |
106 | vld41.8 {q0, q1, q2}, [r0] | |
107 | vld41.8 {q0, q1}, [r0] | |
108 | vld41.8 {q0}, [r0] | |
109 | vld41.8 {q0, q1, q2, q3}, [pc] | |
110 | vld41.8 {q0, q1, q2, q3}, [pc]! | |
111 | vld41.8 {q0, q1, q2, q3}, [sp]! | |
112 | vld41.64 {q0, q1, q2, q3}, [r0] | |
113 | vld42.8 {q0, q2, q3, q4}, [r0] | |
114 | vld42.8 {q0, q1, q3, q4}, [r0] | |
115 | vld42.8 {q0, q1, q2, q4}, [r0] | |
116 | vld42.8 {q3, q1, q2, q3}, [r0] | |
117 | vld42.8 {q0, q1, q2, q3, q4}, [r0] | |
118 | vld42.8 {q0, q1, q2}, [r0] | |
119 | vld42.8 {q0, q1}, [r0] | |
120 | vld42.8 {q0}, [r0] | |
121 | vld42.8 {q0, q1, q2, q3}, [pc] | |
122 | vld42.8 {q0, q1, q2, q3}, [pc]! | |
123 | vld42.8 {q0, q1, q2, q3}, [sp]! | |
124 | vld42.64 {q0, q1, q2, q3}, [r0] | |
125 | vld43.8 {q0, q2, q3, q4}, [r0] | |
126 | vld43.8 {q0, q1, q3, q4}, [r0] | |
127 | vld43.8 {q0, q1, q2, q4}, [r0] | |
128 | vld43.8 {q3, q1, q2, q3}, [r0] | |
129 | vld43.8 {q0, q1, q2, q3, q4}, [r0] | |
130 | vld43.8 {q0, q1, q2}, [r0] | |
131 | vld43.8 {q0, q1}, [r0] | |
132 | vld43.8 {q0}, [r0] | |
133 | vld43.8 {q0, q1, q2, q3}, [pc] | |
134 | vld43.8 {q0, q1, q2, q3}, [pc]! | |
135 | vld43.8 {q0, q1, q2, q3}, [sp]! | |
136 | vld43.64 {q0, q1, q2, q3}, [r0] | |
137 | vld1.8 {q0, q1}, [r0] | |
138 | vld2.8 {q0, q1}, [r0] | |
139 | vld3.8 {q0, q1}, [r0] | |
140 | vld4.8 {q0, q1}, [r0] | |
141 | vld23.32 {q0, q1}, [r0] | |
142 | vld44.32 {q0, q1, q2, q3}, [r0] | |
143 | ||
144 | .macro cond2 op | |
145 | .irp cond, eq, ne, gt, ge, lt, le | |
146 | it \cond | |
147 | \op\().32 {q0, q1}, [r0] | |
148 | .endr | |
149 | .endm | |
150 | ||
151 | ||
152 | ||
153 | .macro cond4 op | |
154 | .irp cond, eq, ne, gt, ge, lt, le | |
155 | it \cond | |
156 | \op\().32 {q0, q1, q2, q3}, [r0] | |
157 | .endr | |
158 | .endm | |
159 | ||
160 | cond2 vst20 | |
161 | cond2 vst21 | |
162 | cond4 vst40 | |
163 | cond4 vst41 | |
164 | cond4 vst42 | |
165 | cond4 vst43 | |
166 | vpste | |
167 | vst20t.32 {q0, q1}, [r0] | |
168 | vst20e.32 {q0, q1}, [r0] | |
169 | vpste | |
170 | vst21t.32 {q0, q1}, [r0] | |
171 | vst21e.32 {q0, q1}, [r0] | |
172 | vpste | |
173 | vst40t.32 {q0, q1, q2, q3}, [r0] | |
174 | vst40e.32 {q0, q1, q2, q3}, [r0] | |
175 | vpste | |
176 | vst41t.32 {q0, q1, q2, q3}, [r0] | |
177 | vst41e.32 {q0, q1, q2, q3}, [r0] | |
178 | vpste | |
179 | vst42t.32 {q0, q1, q2, q3}, [r0] | |
180 | vst42e.32 {q0, q1, q2, q3}, [r0] | |
181 | vpste | |
182 | vst43t.32 {q0, q1, q2, q3}, [r0] | |
183 | vst43e.32 {q0, q1, q2, q3}, [r0] | |
184 | ||
185 | vpst | |
186 | vst20.32 {q0, q1}, [r0] | |
187 | vpst | |
188 | vst21.32 {q0, q1}, [r0] | |
189 | vpst | |
190 | vst40.32 {q0, q1, q2, q3}, [r0] | |
191 | vpst | |
192 | vst41.32 {q0, q1, q2, q3}, [r0] | |
193 | vpst | |
194 | vst42.32 {q0, q1, q2, q3}, [r0] | |
195 | vpst | |
196 | vst43.32 {q0, q1, q2, q3}, [r0] | |
197 | ||
198 | cond2 vld20 | |
199 | cond2 vld21 | |
200 | cond4 vld40 | |
201 | cond4 vld41 | |
202 | cond4 vld42 | |
203 | cond4 vld43 | |
204 | vpste | |
205 | vld20t.32 {q0, q1}, [r0] | |
206 | vld20e.32 {q0, q1}, [r0] | |
207 | vpste | |
208 | vld21t.32 {q0, q1}, [r0] | |
209 | vld21e.32 {q0, q1}, [r0] | |
210 | vpste | |
211 | vld40t.32 {q0, q1, q2, q3}, [r0] | |
212 | vld40e.32 {q0, q1, q2, q3}, [r0] | |
213 | vpste | |
214 | vld41t.32 {q0, q1, q2, q3}, [r0] | |
215 | vld41e.32 {q0, q1, q2, q3}, [r0] | |
216 | vpste | |
217 | vld42t.32 {q0, q1, q2, q3}, [r0] | |
218 | vld42e.32 {q0, q1, q2, q3}, [r0] | |
219 | vpste | |
220 | vld43t.32 {q0, q1, q2, q3}, [r0] | |
221 | vld43e.32 {q0, q1, q2, q3}, [r0] | |
222 | ||
223 | vpst | |
224 | vld20.32 {q0, q1}, [r0] | |
225 | vpst | |
226 | vld21.32 {q0, q1}, [r0] | |
227 | vpst | |
228 | vld40.32 {q0, q1, q2, q3}, [r0] | |
229 | vpst | |
230 | vld41.32 {q0, q1, q2, q3}, [r0] | |
231 | vpst | |
232 | vld42.32 {q0, q1, q2, q3}, [r0] | |
233 | vpst | |
234 | vld43.32 {q0, q1, q2, q3}, [r0] |