projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 250d07de | 1 | /* Copyright (C) 2000-2021 Free Software Foundation, Inc. |
| ec2655a6 NC |
2 | Contributed by Alexandre Oliva <aoliva@redhat.com> |
| 3 | ||
| 4 | This file is free software; you can redistribute it and/or modify it | |
| 5 | under the terms of the GNU General Public License as published by | |
| 6 | the Free Software Foundation; either version 3 of the License, or | |
| 7 | (at your option) any later version. | |
| 8 | ||
| 9 | This program is distributed in the hope that it will be useful, but | |
| 10 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 12 | General Public License for more details. | |
| 13 | ||
| 14 | You should have received a copy of the GNU General Public License | |
| 15 | along with this program; if not, write to the Free Software | |
| 16 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, | |
| 17 | MA 02110-1301, USA. */ | |
| e1f834a3 AO |
18 | |
| 19 | /* Generator of tests for insns introduced in AM33 2.0. */ | |
| 20 | ||
| 21 | #define INSN_REPEAT 11 | |
| 22 | ||
| 23 | /* See the following file for usage and documentation. */ | |
| 24 | #include "../all/test-gen.c" | |
| 25 | ||
| 26 | /* These are the AM33 registers. */ | |
| 27 | const char *am33_regs[] = { | |
| 28 | /* These are the canonical names, i.e., those printed by the | |
| 29 | * disassembler. */ | |
| 30 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
| 31 | "a0", "a1", "a2", "a3", "d0", "d1", "d2", "d3", | |
| 32 | /* These are aliases that the assembler should also recognize. */ | |
| 33 | "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7", | |
| 34 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
| 35 | }; | |
| 36 | ||
| 37 | /* Signed constants of the given sizes. */ | |
| 38 | #define d8(shift) signed_constant( 8, shift, 1) | |
| 39 | #define d16(shift) signed_constant(16, shift, 1) | |
| 40 | #define d24(shift) signed_constant(24, shift, 1) | |
| 41 | #define d32(shift) signed_constant(32, shift, 1) | |
| 42 | #define u8(shift) unsigned_constant( 8, shift, 1) | |
| 43 | #define u24(shift) unsigned_constant(24, shift, 1) | |
| 44 | #define a16(shift) absolute_address(16, shift, 1) | |
| 45 | ||
| 46 | /* Emit an AM33 register shifted by these many words. */ | |
| 47 | #define amreg(shift) reg_r (am33_regs, shift, 15, mk_get_bits (5u)) | |
| 48 | #define spreg literal ("sp") | |
| 49 | #define fcreg literal ("fpcr") | |
| 50 | ||
| 51 | /* Emit an AM33-2 FP single-precision register, with the 4 least | |
| 52 | * significant bits shifted by shiftlow and the most significant bit | |
| 53 | * shifted by shifthigh. */ | |
| 54 | int | |
| 55 | freg (func_arg *arg, insn_data *data) | |
| 56 | #define freg(shiftlow, shifthigh) { freg, { i1: shiftlow, i2: shifthigh } } | |
| 57 | { | |
| 58 | unsigned val = get_bits (5u); | |
| 59 | ||
| 60 | data->as_in = data->dis_out = (char*)malloc (3 + ulen (val, 10)); | |
| 61 | sprintf (data->as_in, "fs%u", val); | |
| 62 | data->bits = val; | |
| 63 | data->bits = ((data->bits & 15) << arg->i1) | ((data->bits >> 4) << arg->i2); | |
| 64 | ||
| 65 | return 0; | |
| 66 | } | |
| 67 | ||
| 68 | /* Emit an AM33-2 FP single-precision register in the ``accumulator'' | |
| 69 | * range, with the 2 least significant bits shifted by shiftlow and | |
| 70 | * the most significant bit shifted by shifthigh. */ | |
| 71 | int | |
| 72 | areg (func_arg *arg, insn_data *data) | |
| 73 | #define areg(shiftlow, shifthigh) { areg, { i1: shiftlow, i2: shifthigh } } | |
| 74 | { | |
| 75 | unsigned val = get_bits (3u); | |
| 76 | ||
| 77 | data->as_in = data->dis_out = (char*)malloc (4); | |
| 78 | sprintf (data->as_in, "fs%u", val); | |
| 79 | data->bits = val; | |
| 80 | data->bits = ((data->bits & 3) << arg->i1) | ((data->bits >> 2) << arg->i2); | |
| 81 | ||
| 82 | return 0; | |
| 83 | } | |
| 84 | ||
| 85 | /* Emit an AM33-2 FP double-precision register, with the 4 least | |
| 86 | * significant bits shifted by shiftlow and the most significant bit | |
| 87 | * shifted by shifthigh. */ | |
| 88 | int | |
| 89 | dreg (func_arg *arg, insn_data *data) | |
| 90 | #define dreg(shiftlow, shifthigh) { dreg, { i1: shiftlow, i2: shifthigh } } | |
| 91 | { | |
| 92 | unsigned val = 2 * get_bits (4u); | |
| 93 | ||
| 94 | data->as_in = data->dis_out = (char*)malloc (3 + ulen (val, 10)); | |
| 95 | sprintf (data->as_in, "fd%u", val); | |
| 96 | data->bits = val; | |
| 97 | data->bits = ((data->bits & 15) << arg->i1) | ((data->bits >> 4) << arg->i2); | |
| 98 | ||
| 99 | return 0; | |
| 100 | } | |
| 101 | ||
| 102 | /* Emit a signed 8-bit PC-relative offset from the current insn to the | |
| 103 | * last emitted label. */ | |
| 104 | int | |
| 105 | d8pcoff (func_arg *arg, insn_data *data) | |
| 106 | #define d8pcoff(shift) { d8pcoff, { p1: shift } } | |
| 107 | { | |
| 108 | int diff = insn_size - arg->i1/8 - 1; | |
| 109 | int displacement = current_offset - last_label_offset; | |
| 110 | char *current_address = malloc (strlen (last_label_name) + 4 | |
| 111 | + ulen (displacement, 16) + 1); | |
| 112 | ||
| 113 | /* Make sure we're not too far from the target. */ | |
| 114 | if (displacement > 128) | |
| 115 | abort (); | |
| 116 | ||
| 117 | data->as_in = strdup (last_label_name); | |
| 118 | ||
| 119 | /* Calculate the address that will be printed by the disassembler as | |
| 120 | the target of the jump. Since it won't take relocations into | |
| 121 | account, it will be the insn's own address. */ | |
| 122 | if (current_offset == last_label_offset) | |
| 123 | strcpy (current_address, last_label_name); | |
| 124 | else | |
| 125 | sprintf (current_address, "%s\\+0x%x", last_label_name, displacement); | |
| 126 | ||
| 127 | /* Compute the complete label, including the relocation message | |
| 128 | printed as an additional message. The relocation will point us | |
| 129 | to the intended target label plus an offset equal to the offset | |
| 130 | of the displacement within the current insn. We do not account | |
| 131 | for the case in which this displacement is zero, since it doesn't | |
| 132 | come up on this platform. */ | |
| 133 | data->dis_out = malloc (8 + 2 + strlen (current_address) + 2 | |
| 134 | + 3 + ulen (current_offset + diff, 16) + 19 | |
| 135 | + strlen (last_label_name) + 4 | |
| 136 | + ulen (diff, 16) + 1); | |
| 137 | sprintf (data->dis_out, "0*%x <%s>\n" | |
| 138 | "\t\t\t%x: R_MN10300_PCREL8\t%s\\+0x%x", | |
| 139 | current_offset, current_address, | |
| 140 | current_offset + diff, last_label_name, diff); | |
| 141 | ||
| 142 | free (current_address); | |
| 143 | ||
| 144 | return 0; | |
| 145 | } | |
| 146 | ||
| 147 | /* Emit a signed 8-bit PC-relative offset from the current insn to the | |
| 148 | * current section. */ | |
| 149 | int | |
| 150 | d8pcsec (func_arg *arg, insn_data *data) | |
| 151 | #define d8pcsec(shift) { d8pcsec, { p1: shift } } | |
| 152 | { | |
| 153 | int diff = insn_size - arg->i1/8 - 1; | |
| 154 | int displacement = current_offset - last_label_offset; | |
| 155 | char *current_address = malloc (strlen (last_label_name) + 4 | |
| 156 | + ulen (displacement, 16) + 1); | |
| 157 | ||
| 158 | /* Make sure we're not too far from the target. */ | |
| 159 | if (displacement > 128) | |
| 160 | abort (); | |
| 161 | ||
| 162 | data->as_in = strdup (last_label_name); | |
| 163 | ||
| 164 | /* Calculate the address that will be printed by the disassembler as | |
| 165 | the target of the jump. Since it won't take relocations into | |
| 166 | account, it will be the insn's own address. */ | |
| 167 | ||
| 168 | if (current_offset == last_label_offset) | |
| 169 | strcpy (current_address, last_label_name); | |
| 170 | else | |
| 171 | sprintf (current_address, "%s\\+0x%x", last_label_name, displacement); | |
| 172 | ||
| 173 | ||
| 174 | /* Compute the complete label, including the relocation message | |
| 175 | printed as an additional message. The relocation will point us | |
| 176 | to the intended target label plus an offset equal to the offset | |
| 177 | of the displacement within the current insn. We do not account | |
| 178 | for the case in which this displacement is zero, since it doesn't | |
| 179 | come up on this platform. */ | |
| 180 | data->dis_out = malloc (8 + 2 + strlen (current_address) + 2 | |
| 181 | + 3 + ulen (current_offset + diff, 16) + 33); | |
| 182 | sprintf (data->dis_out, "0*%x <%s>\n" | |
| 183 | "\t\t\t%x: R_MN10300_PCREL8\tcondjmp\\+0x2", | |
| 184 | current_offset, current_address, | |
| 185 | current_offset + diff); | |
| 186 | ||
| 187 | free (current_address); | |
| 188 | ||
| 189 | return 0; | |
| 190 | } | |
| 191 | ||
| 192 | /* Convenience wrapper to define_insn. */ | |
| 193 | #define def_am_insn(insname, variant, size, word, funcs...) \ | |
| 194 | define_insn(insname ## _ ## variant, \ | |
| 195 | insn_size_bits (insname, size, \ | |
| 196 | ((unsigned long long)word) << 8*(size-2)), \ | |
| 197 | tab, \ | |
| 198 | ## funcs) | |
| 199 | #define am_insn(insname, variant) insn (insname ## _ ## variant) | |
| 200 | ||
| 201 | #define def_bit_insn(insname, word) \ | |
| 202 | def_am_insn (insname, i8a16, 5, word, \ | |
| 203 | u8(0), comma, lparen, a16 (8), rparen, tick_random); | |
| 204 | #define bit_insn(insname) insn (insname ## _ ## i8a16) | |
| 205 | ||
| 206 | /* Data cache pre-fetch insns. */ | |
| 207 | def_am_insn (dcpf, r, 3, 0xf9a6, lparen, amreg (4), rparen); | |
| 208 | def_am_insn (dcpf, sp, 3, 0xf9a7, lparen, spreg, rparen); | |
| 209 | def_am_insn (dcpf, rr, 4, 0xfba6, | |
| 210 | lparen, amreg(12), comma, amreg (8), rparen, tick_random); | |
| 211 | def_am_insn (dcpf, d8r, 4, 0xfba7, | |
| 212 | lparen, d8 (0), comma, amreg (12), rparen, tick_random); | |
| 213 | def_am_insn (dcpf, d24r, 6, 0xfda7, | |
| 214 | lparen, d24(0), comma, amreg (28), rparen, tick_random); | |
| 215 | def_am_insn (dcpf, d32r, 7, 0xfe46, | |
| 216 | lparen, d32(0), comma, amreg (36), rparen, tick_random); | |
| 217 | ||
| 218 | /* Define the group of data cache pre-fetch insns. */ | |
| 219 | func *dcpf_insns[] = { | |
| 220 | am_insn (dcpf, r), | |
| 221 | am_insn (dcpf, sp), | |
| 222 | am_insn (dcpf, rr), | |
| 223 | am_insn (dcpf, d8r), | |
| 224 | am_insn (dcpf, d24r), | |
| 225 | am_insn (dcpf, d32r), | |
| 226 | 0 | |
| 227 | }; | |
| 228 | ||
| 229 | /* Bit operations. */ | |
| 230 | def_bit_insn (bset, 0xfe80); | |
| 231 | def_bit_insn (bclr, 0xfe81); | |
| 232 | def_bit_insn (btst, 0xfe82); | |
| 233 | ||
| 234 | /* Define the group of bit insns. */ | |
| 235 | func *bit_insns[] = { | |
| 236 | bit_insn (bset), | |
| 237 | bit_insn (bclr), | |
| 238 | bit_insn (btst), | |
| 239 | 0 | |
| 240 | }; | |
| 241 | ||
| 242 | /* Define the single-precision FP move insns. */ | |
| 243 | def_am_insn (fmov, irfs, 3, 0xf920, | |
| 244 | lparen, amreg (4), rparen, comma, | |
| 245 | freg (0, 8), tick_random); | |
| 246 | def_am_insn (fmov, rpfs, 3, 0xf922, | |
| 247 | lparen, amreg (4), plus, rparen, comma, | |
| 248 | freg (0, 8), tick_random); | |
| 249 | def_am_insn (fmov, spfs, 3, 0xf924, | |
| 250 | lparen, spreg, rparen, comma, freg (0, 8)); | |
| 251 | def_am_insn (fmov, vrfs, 3, 0xf926, | |
| 252 | amreg (4), comma, freg (0, 8), tick_random); | |
| 253 | def_am_insn (fmov, fsir, 3, 0xf930, | |
| 254 | freg (4, 9), comma, lparen, amreg (0), rparen, tick_random); | |
| 255 | def_am_insn (fmov, fsrp, 3, 0xf931, | |
| 256 | freg (4, 9), comma, lparen, amreg (0), plus, rparen, tick_random); | |
| 257 | def_am_insn (fmov, fssp, 3, 0xf934, | |
| 258 | freg (4, 9), comma, lparen, spreg, rparen); | |
| 259 | def_am_insn (fmov, fsvr, 3, 0xf935, | |
| 260 | freg (4, 9), comma, amreg (0), tick_random); | |
| 261 | def_am_insn (fmov, fsfs, 3, 0xf940, | |
| 262 | freg (4, 9), comma, freg (0, 8), tick_random); | |
| 263 | def_am_insn (fmov, d8rfs, 4, 0xfb20, | |
| 264 | lparen, d8 (0), comma, amreg (12), rparen, comma, | |
| 265 | freg (8, 16)); | |
| 266 | def_am_insn (fmov, rpi8fs, 4, 0xfb22, | |
| 267 | lparen, amreg (12), plus, comma, d8 (0), rparen, comma, | |
| 268 | freg (8, 16)); | |
| 269 | def_am_insn (fmov, d8spfs, 4, 0xfb24, | |
| 270 | lparen, u8 (0), comma, spreg, rparen, comma, freg (8, 16), | |
| 271 | tick_random); | |
| 272 | def_am_insn (fmov, irrfs, 4, 0xfb27, | |
| 273 | lparen, amreg (12), comma, amreg (8), rparen, comma, | |
| 274 | freg (4, 1)); | |
| 275 | def_am_insn (fmov, fsd8r, 4, 0xfb30, | |
| 276 | freg (12, 17), comma, lparen, d8 (0), comma, amreg (8), rparen); | |
| 277 | def_am_insn (fmov, fsrpi8, 4, 0xfb31, | |
| 278 | freg (12, 17), comma, | |
| 279 | lparen, amreg (8), plus, comma, d8 (0), rparen); | |
| 280 | def_am_insn (fmov, fsd8sp, 4, 0xfb34, | |
| 281 | freg (12, 17), comma, | |
| 282 | lparen, u8 (0), comma, spreg, rparen, tick_random); | |
| 283 | def_am_insn (fmov, fsirr, 4, 0xfb37, | |
| 284 | freg (4, 1), comma, | |
| 285 | lparen, amreg (12), comma, amreg (8), rparen); | |
| 286 | def_am_insn (fmov, d24rfs, 6, 0xfd20, | |
| 287 | lparen, d24 (0), comma, amreg (28), rparen, comma, freg (24, 32)); | |
| 288 | def_am_insn (fmov, rpi24fs, 6, 0xfd22, | |
| 289 | lparen, amreg (28), plus, comma, d24 (0), rparen, comma, | |
| 290 | freg (24, 32)); | |
| 291 | def_am_insn (fmov, d24spfs, 6, 0xfd24, | |
| 292 | lparen, u24 (0), comma, spreg, rparen, comma, | |
| 293 | freg (24, 32), tick_random); | |
| 294 | def_am_insn (fmov, fsd24r, 6, 0xfd30, | |
| 295 | freg (28, 33), comma, lparen, d24 (0), comma, amreg (24), rparen); | |
| 296 | def_am_insn (fmov, fsrpi24, 6, 0xfd31, | |
| 297 | freg (28, 33), comma, | |
| 298 | lparen, amreg (24), plus, comma, d24 (0), rparen); | |
| 299 | def_am_insn (fmov, fsd24sp, 6, 0xfd34, | |
| 300 | freg (28, 33), comma, | |
| 301 | lparen, u24 (0), comma, spreg, rparen, tick_random); | |
| 302 | def_am_insn (fmov, d32rfs, 7, 0xfe20, | |
| 303 | lparen, d32 (0), comma, amreg (36), rparen, comma, freg (32, 40)); | |
| 304 | def_am_insn (fmov, rpi32fs, 7, 0xfe22, | |
| 305 | lparen, amreg (36), plus, comma, d32 (0), rparen, comma, | |
| 306 | freg (32, 40)); | |
| 307 | def_am_insn (fmov, d32spfs, 7, 0xfe24, | |
| 308 | lparen, d32 (0), comma, spreg, rparen, comma, | |
| 309 | freg (32, 40), tick_random); | |
| 310 | def_am_insn (fmov, i32fs, 7, 0xfe26, | |
| 311 | d32 (0), comma, freg (32, 40), tick_random); | |
| 312 | def_am_insn (fmov, fsd32r, 7, 0xfe30, | |
| 313 | freg (36, 41), comma, lparen, d32 (0), comma, amreg (32), rparen); | |
| 314 | def_am_insn (fmov, fsrpi32, 7, 0xfe31, | |
| 315 | freg (36, 41), comma, | |
| 316 | lparen, amreg (32), plus, comma, d32 (0), rparen); | |
| 317 | def_am_insn (fmov, fsd32sp, 7, 0xfe34, | |
| 318 | freg (36, 41), comma, | |
| 319 | lparen, d32 (0), comma, spreg, rparen, tick_random); | |
| 320 | ||
| 321 | /* Define the group of single-precision FP move insns. */ | |
| 322 | func *fmovs_insns[] = { | |
| 323 | am_insn (fmov, irfs), | |
| 324 | am_insn (fmov, rpfs), | |
| 325 | am_insn (fmov, spfs), | |
| 326 | am_insn (fmov, vrfs), | |
| 327 | am_insn (fmov, fsir), | |
| 328 | am_insn (fmov, fsrp), | |
| 329 | am_insn (fmov, fssp), | |
| 330 | am_insn (fmov, fsvr), | |
| 331 | am_insn (fmov, fsfs), | |
| 332 | am_insn (fmov, d8rfs), | |
| 333 | am_insn (fmov, rpi8fs), | |
| 334 | am_insn (fmov, d8spfs), | |
| 335 | am_insn (fmov, irrfs), | |
| 336 | am_insn (fmov, fsd8r), | |
| 337 | am_insn (fmov, fsrpi8), | |
| 338 | am_insn (fmov, fsd8sp), | |
| 339 | am_insn (fmov, fsirr), | |
| 340 | am_insn (fmov, d24rfs), | |
| 341 | am_insn (fmov, rpi24fs), | |
| 342 | am_insn (fmov, d24spfs), | |
| 343 | am_insn (fmov, fsd24r), | |
| 344 | am_insn (fmov, fsrpi24), | |
| 345 | am_insn (fmov, fsd24sp), | |
| 346 | am_insn (fmov, d32rfs), | |
| 347 | am_insn (fmov, rpi32fs), | |
| 348 | am_insn (fmov, d32spfs), | |
| 349 | am_insn (fmov, i32fs), | |
| 350 | am_insn (fmov, fsd32r), | |
| 351 | am_insn (fmov, fsrpi32), | |
| 352 | am_insn (fmov, fsd32sp), | |
| 353 | 0 | |
| 354 | }; | |
| 355 | ||
| 356 | /* Define the double-precision FP move insns. */ | |
| 357 | def_am_insn (fmov, irfd, 3, 0xf9a0, | |
| 358 | lparen, amreg (4), rparen, comma, dreg (0, 8), tick_random); | |
| 359 | def_am_insn (fmov, rpfd, 3, 0xf9a2, | |
| 360 | lparen, amreg (4), plus, rparen, comma, dreg (0, 8), tick_random); | |
| 361 | def_am_insn (fmov, spfd, 3, 0xf9a4, | |
| 362 | lparen, spreg, rparen, comma, dreg (0, 8)); | |
| 363 | def_am_insn (fmov, fdir, 3, 0xf9b0, | |
| 364 | dreg (4, 9), comma, lparen, amreg (0), rparen, tick_random); | |
| 365 | def_am_insn (fmov, fdrp, 3, 0xf9b1, | |
| 366 | dreg (4, 9), comma, lparen, amreg (0), plus, rparen, tick_random); | |
| 367 | def_am_insn (fmov, fdsp, 3, 0xf9b4, | |
| 368 | dreg (4, 9), comma, lparen, spreg, rparen); | |
| 369 | def_am_insn (fmov, fdfd, 3, 0xf9c0, | |
| 370 | dreg (4, 9), comma, dreg (0, 8), tick_random); | |
| 371 | def_am_insn (fmov, irrfd, 4, 0xfb47, | |
| 372 | lparen, amreg (12), comma, amreg (8), rparen, comma, dreg (4, 1)); | |
| 373 | def_am_insn (fmov, fdirr, 4, 0xfb57, | |
| 374 | dreg (4, 1), comma, lparen, amreg (12), comma, amreg (8), rparen); | |
| 375 | def_am_insn (fmov, d8rfd, 4, 0xfba0, | |
| 376 | lparen, d8 (0), comma, amreg (12), rparen, comma, dreg (8, 16)); | |
| 377 | def_am_insn (fmov, rpi8fd, 4, 0xfba2, | |
| 378 | lparen, amreg (12), plus, comma, d8 (0), rparen, comma, | |
| 379 | dreg (8, 16)); | |
| 380 | def_am_insn (fmov, d8spfd, 4, 0xfba4, | |
| 381 | lparen, u8 (0), comma, spreg, rparen, comma, | |
| 382 | dreg (8, 16), tick_random); | |
| 383 | def_am_insn (fmov, fdd8r, 4, 0xfbb0, | |
| 384 | dreg (12, 17), comma, lparen, d8 (0), comma, amreg (8), rparen); | |
| 385 | def_am_insn (fmov, fdrpi8, 4, 0xfbb1, | |
| 386 | dreg (12, 17), comma, | |
| 387 | lparen, amreg (8), plus, comma, d8 (0), rparen); | |
| 388 | def_am_insn (fmov, fdi8sp, 4, 0xfbb4, | |
| 389 | dreg (12, 17), comma, | |
| 390 | lparen, u8 (0), comma, spreg, rparen, tick_random); | |
| 391 | def_am_insn (fmov, d24rfd, 6, 0xfda0, | |
| 392 | lparen, d24 (0), comma, amreg (28), rparen, comma, dreg (24, 32)); | |
| 393 | def_am_insn (fmov, rpi24fd, 6, 0xfda2, | |
| 394 | lparen, amreg (28), plus, comma, d24 (0), rparen, comma, | |
| 395 | dreg (24, 32)); | |
| 396 | def_am_insn (fmov, d24spfd, 6, 0xfda4, | |
| 397 | lparen, u24 (0), comma, spreg, rparen, comma, | |
| 398 | dreg (24, 32), tick_random); | |
| 399 | def_am_insn (fmov, fdd24r, 6, 0xfdb0, | |
| 400 | dreg (28, 33), comma, | |
| 401 | lparen, d24 (0), comma, amreg (24), rparen); | |
| 402 | def_am_insn (fmov, fdrpi24, 6, 0xfdb1, | |
| 403 | dreg (28, 33), comma, | |
| 404 | lparen, amreg (24), plus, comma, d24 (0), rparen); | |
| 405 | def_am_insn (fmov, fdd24sp, 6, 0xfdb4, | |
| 406 | dreg (28, 33), comma, | |
| 407 | lparen, u24 (0), comma, spreg, rparen, tick_random); | |
| 408 | def_am_insn (fmov, d32rfd, 7, 0xfe40, | |
| 409 | lparen, d32 (0), comma, amreg (36), rparen, comma, dreg (32, 40)); | |
| 410 | def_am_insn (fmov, rpi32fd, 7, 0xfe42, | |
| 411 | lparen, amreg (36), plus, comma, d32 (0), rparen, comma, | |
| 412 | dreg (32, 40)); | |
| 413 | def_am_insn (fmov, d32spfd, 7, 0xfe44, | |
| 414 | lparen, d32 (0), comma, spreg, rparen, comma, | |
| 415 | dreg (32, 40), tick_random); | |
| 416 | def_am_insn (fmov, fdd32r, 7, 0xfe50, | |
| 417 | dreg (36, 41), comma, | |
| 418 | lparen, d32 (0), comma, amreg (32), rparen); | |
| 419 | def_am_insn (fmov, fdrpi32, 7, 0xfe51, | |
| 420 | dreg (36, 41), comma, | |
| 421 | lparen, amreg (32), plus, comma, d32 (0), rparen); | |
| 422 | def_am_insn (fmov, fdd32sp, 7, 0xfe54, | |
| 423 | dreg (36, 41), comma, | |
| 424 | lparen, d32 (0), comma, spreg, rparen, tick_random); | |
| 425 | ||
| 426 | /* Define the group of double-precision FP move insns. */ | |
| 427 | func *fmovd_insns[] = { | |
| 428 | am_insn (fmov, irfd), | |
| 429 | am_insn (fmov, rpfd), | |
| 430 | am_insn (fmov, spfd), | |
| 431 | am_insn (fmov, fdir), | |
| 432 | am_insn (fmov, fdrp), | |
| 433 | am_insn (fmov, fdsp), | |
| 434 | am_insn (fmov, fdfd), | |
| 435 | am_insn (fmov, irrfd), | |
| 436 | am_insn (fmov, fdirr), | |
| 437 | am_insn (fmov, d8rfd), | |
| 438 | am_insn (fmov, rpi8fd), | |
| 439 | am_insn (fmov, d8spfd), | |
| 440 | am_insn (fmov, fdd8r), | |
| 441 | am_insn (fmov, fdrpi8), | |
| 442 | am_insn (fmov, fdi8sp), | |
| 443 | am_insn (fmov, d24rfd), | |
| 444 | am_insn (fmov, rpi24fd), | |
| 445 | am_insn (fmov, d24spfd), | |
| 446 | am_insn (fmov, fdd24r), | |
| 447 | am_insn (fmov, fdrpi24), | |
| 448 | am_insn (fmov, fdd24sp), | |
| 449 | am_insn (fmov, d32rfd), | |
| 450 | am_insn (fmov, rpi32fd), | |
| 451 | am_insn (fmov, d32spfd), | |
| 452 | am_insn (fmov, fdd32r), | |
| 453 | am_insn (fmov, fdrpi32), | |
| 454 | am_insn (fmov, fdd32sp), | |
| 455 | 0 | |
| 456 | }; | |
| 457 | ||
| 458 | /* Define fmov FPCR insns. */ | |
| 459 | def_am_insn (fmov, vrfc, 3, 0xf9b5, | |
| 460 | amreg (4), comma, fcreg); | |
| 461 | def_am_insn (fmov, fcvr, 3, 0xf9b7, | |
| 462 | fcreg, comma, amreg (0)); | |
| 463 | def_am_insn (fmov, i32fc, 6, 0xfdb5, | |
| 464 | d32 (0), comma, fcreg); | |
| 465 | ||
| 466 | /* Define the group of FPCR move insns. */ | |
| 467 | func *fmovc_insns[] = { | |
| 468 | am_insn (fmov, vrfc), | |
| 469 | am_insn (fmov, fcvr), | |
| 470 | am_insn (fmov, i32fc), | |
| 471 | 0 | |
| 472 | }; | |
| 473 | ||
| 474 | /* Define single-precision floating-point arithmetic insns. */ | |
| 475 | def_am_insn (fabs, fs, 3, 0xf944, freg (0, 8)); | |
| 476 | def_am_insn (fabs, fsfs, 4, 0xfb44, | |
| 477 | freg (12, 3), comma, freg (4, 1), tick_random); | |
| 478 | def_am_insn (fneg, fs, 3, 0xf946, freg (0, 8)); | |
| 479 | def_am_insn (fneg, fsfs, 4, 0xfb46, | |
| 480 | freg (12, 3), comma, freg (4, 1), tick_random); | |
| 481 | def_am_insn (frsqrt, fs, 3, 0xf950, freg (0, 8)); | |
| 482 | def_am_insn (frsqrt, fsfs, 4, 0xfb50, | |
| 483 | freg (12, 3), comma, freg (4, 1), tick_random); | |
| 484 | def_am_insn (fsqrt, fs, 3, 0xf952, freg (0, 8)); | |
| 485 | def_am_insn (fsqrt, fsfs, 4, 0xfb54, | |
| 486 | freg (12, 3), comma, freg (4, 1), tick_random); | |
| 487 | def_am_insn (fcmp, fsfs, 3, 0xf954, | |
| 488 | freg (4, 9), comma, freg (0, 8), tick_random); | |
| 489 | def_am_insn (fcmp, i32fs, 7, 0xfe35, | |
| 490 | d32 (0), comma, freg (36, 41), tick_random); | |
| 491 | def_am_insn (fadd, fsfs, 3, 0xf960, | |
| 492 | freg (4, 9), comma, freg (0, 8), tick_random); | |
| 493 | def_am_insn (fadd, fsfsfs, 4, 0xfb60, | |
| 494 | freg (12, 3), comma, freg (8, 2), comma, freg (4, 1)); | |
| 495 | def_am_insn (fadd, i32fsfs, 7, 0xfe60, | |
| 496 | d32 (0), comma, freg (36, 41), comma, freg (32, 40)); | |
| 497 | def_am_insn (fsub, fsfs, 3, 0xf964, | |
| 498 | freg (4, 9), comma, freg (0, 8), tick_random); | |
| 499 | def_am_insn (fsub, fsfsfs, 4, 0xfb64, | |
| 500 | freg (12, 3), comma, freg (8, 2), comma, freg (4, 1)); | |
| 501 | def_am_insn (fsub, i32fsfs, 7, 0xfe64, | |
| 502 | d32 (0), comma, freg (36, 41), comma, freg (32, 40)); | |
| 503 | def_am_insn (fmul, fsfs, 3, 0xf970, | |
| 504 | freg (4, 9), comma, freg (0, 8), tick_random); | |
| 505 | def_am_insn (fmul, fsfsfs, 4, 0xfb70, | |
| 506 | freg (12, 3), comma, freg (8, 2), comma, freg (4, 1)); | |
| 507 | def_am_insn (fmul, i32fsfs, 7, 0xfe70, | |
| 508 | d32 (0), comma, freg (36, 41), comma, freg (32, 40)); | |
| 509 | def_am_insn (fdiv, fsfs, 3, 0xf974, | |
| 510 | freg (4, 9), comma, freg (0, 8), tick_random); | |
| 511 | def_am_insn (fdiv, fsfsfs, 4, 0xfb74, | |
| 512 | freg (12, 3), comma, freg (8, 2), comma, freg (4, 1)); | |
| 513 | def_am_insn (fdiv, i32fsfs, 7, 0xfe74, | |
| 514 | d32 (0), comma, freg (36, 41), comma, freg (32, 40)); | |
| 515 | ||
| 516 | /* Define the group of single-precision floating-point arithmetic insns. */ | |
| 517 | func *sfparith_insns[] = { | |
| 518 | am_insn (fabs, fs), | |
| 519 | am_insn (fabs, fsfs), | |
| 520 | am_insn (fneg, fs), | |
| 521 | am_insn (fneg, fsfs), | |
| 522 | am_insn (frsqrt, fs), | |
| 523 | am_insn (frsqrt, fsfs), | |
| 524 | am_insn (fsqrt, fs), | |
| 525 | am_insn (fsqrt, fsfs), | |
| 526 | am_insn (fcmp, fsfs), | |
| 527 | am_insn (fcmp, i32fs), | |
| 528 | am_insn (fadd, fsfs), | |
| 529 | am_insn (fadd, fsfsfs), | |
| 530 | am_insn (fadd, i32fsfs), | |
| 531 | am_insn (fsub, fsfs), | |
| 532 | am_insn (fsub, fsfsfs), | |
| 533 | am_insn (fsub, i32fsfs), | |
| 534 | am_insn (fmul, fsfs), | |
| 535 | am_insn (fmul, fsfsfs), | |
| 536 | am_insn (fmul, i32fsfs), | |
| 537 | am_insn (fdiv, fsfs), | |
| 538 | am_insn (fdiv, fsfsfs), | |
| 539 | am_insn (fdiv, i32fsfs), | |
| 540 | 0 | |
| 541 | }; | |
| 542 | ||
| 543 | /* Define floating-point accumulator arithmetic insns. */ | |
| 544 | def_am_insn (fmadd, , 4, 0xfb80, | |
| 545 | freg (12, 3), comma, freg (8, 2), comma, | |
| 546 | freg (4, 1), comma, areg (16, 0), tick_random); | |
| 547 | def_am_insn (fmsub, , 4, 0xfb84, | |
| 548 | freg (12, 3), comma, freg (8, 2), comma, | |
| 549 | freg (4, 1), comma, areg (16, 0), tick_random); | |
| 550 | def_am_insn (fnmadd, , 4, 0xfb90, | |
| 551 | freg (12, 3), comma, freg (8, 2), comma, | |
| 552 | freg (4, 1), comma, areg (16, 0), tick_random); | |
| 553 | def_am_insn (fnmsub, , 4, 0xfb94, | |
| 554 | freg (12, 3), comma, freg (8, 2), comma, | |
| 555 | freg (4, 1), comma, areg (16, 0), tick_random); | |
| 556 | ||
| 557 | /* Define the group of floating-point accumulator arithmetic insns. */ | |
| 558 | func *fpacc_insns[] = { | |
| 559 | am_insn (fmadd, ), | |
| 560 | am_insn (fmsub, ), | |
| 561 | am_insn (fnmadd, ), | |
| 562 | am_insn (fnmsub, ), | |
| 563 | 0 | |
| 564 | }; | |
| 565 | ||
| 566 | /* Define double-precision floating-point arithmetic insns. */ | |
| 567 | def_am_insn (fabs, fd, 3, 0xf9c4, dreg (0, 8)); | |
| 568 | def_am_insn (fabs, fdfd, 4, 0xfbc4, | |
| 569 | dreg (12, 3), comma, dreg (4, 1), tick_random); | |
| 570 | def_am_insn (fneg, fd, 3, 0xf9c6, dreg (0, 8)); | |
| 571 | def_am_insn (fneg, fdfd, 4, 0xfbc6, | |
| 572 | dreg (12, 3), comma, dreg (4, 1), tick_random); | |
| 573 | def_am_insn (frsqrt, fd, 3, 0xf9d0, dreg (0, 8)); | |
| 574 | def_am_insn (frsqrt, fdfd, 4, 0xfbd0, | |
| 575 | dreg (12, 3), comma, dreg (4, 1), tick_random); | |
| 576 | def_am_insn (fsqrt, fd, 3, 0xf9d2, dreg (0, 8)); | |
| 577 | def_am_insn (fsqrt, fdfd, 4, 0xfbd4, | |
| 578 | dreg (12, 3), comma, dreg (4, 1), tick_random); | |
| 579 | def_am_insn (fcmp, fdfd, 3, 0xf9d4, | |
| 580 | dreg (4, 9), comma, dreg (0, 8), tick_random); | |
| 581 | def_am_insn (fadd, fdfd, 3, 0xf9e0, | |
| 582 | dreg (4, 9), comma, dreg (0, 8), tick_random); | |
| 583 | def_am_insn (fadd, fdfdfd, 4, 0xfbe0, | |
| 584 | dreg (12, 3), comma, dreg (8, 2), comma, dreg (4, 1)); | |
| 585 | def_am_insn (fsub, fdfd, 3, 0xf9e4, | |
| 586 | dreg (4, 9), comma, dreg (0, 8), tick_random); | |
| 587 | def_am_insn (fsub, fdfdfd, 4, 0xfbe4, | |
| 588 | dreg (12, 3), comma, dreg (8, 2), comma, dreg (4, 1)); | |
| 589 | def_am_insn (fmul, fdfd, 3, 0xf9f0, | |
| 590 | dreg (4, 9), comma, dreg (0, 8), tick_random); | |
| 591 | def_am_insn (fmul, fdfdfd, 4, 0xfbf0, | |
| 592 | dreg (12, 3), comma, dreg (8, 2), comma, dreg (4, 1)); | |
| 593 | def_am_insn (fdiv, fdfd, 3, 0xf9f4, | |
| 594 | dreg (4, 9), comma, dreg (0, 8), tick_random); | |
| 595 | def_am_insn (fdiv, fdfdfd, 4, 0xfbf4, | |
| 596 | dreg (12, 3), comma, dreg (8, 2), comma, dreg (4, 1)); | |
| 597 | ||
| 598 | /* Define the group of double-precision floating-point arithmetic insns. */ | |
| 599 | func *dfparith_insns[] = { | |
| 600 | am_insn (fabs, fd), | |
| 601 | am_insn (fabs, fdfd), | |
| 602 | am_insn (fneg, fd), | |
| 603 | am_insn (fneg, fdfd), | |
| 604 | am_insn (frsqrt, fd), | |
| 605 | am_insn (frsqrt, fdfd), | |
| 606 | am_insn (fsqrt, fd), | |
| 607 | am_insn (fsqrt, fdfd), | |
| 608 | am_insn (fcmp, fdfd), | |
| 609 | am_insn (fadd, fdfd), | |
| 610 | am_insn (fadd, fdfdfd), | |
| 611 | am_insn (fsub, fdfd), | |
| 612 | am_insn (fsub, fdfdfd), | |
| 613 | am_insn (fmul, fdfd), | |
| 614 | am_insn (fmul, fdfdfd), | |
| 615 | am_insn (fdiv, fdfd), | |
| 616 | am_insn (fdiv, fdfdfd), | |
| 617 | 0 | |
| 618 | }; | |
| 619 | ||
| 620 | /* Define floating-point conversion insns. */ | |
| 621 | def_am_insn (ftoi, fsfs, 4, 0xfb40, | |
| 622 | freg (12, 3), comma, freg (4, 1), tick_random); | |
| 623 | def_am_insn (itof, fsfs, 4, 0xfb42, | |
| 624 | freg (12, 3), comma, freg (4, 1), tick_random); | |
| 625 | def_am_insn (ftod, fsfd, 4, 0xfb52, | |
| 626 | freg (12, 3), comma, dreg (4, 1), tick_random); | |
| 627 | def_am_insn (dtof, fdfs, 4, 0xfb56, | |
| 628 | dreg (12, 3), comma, freg (4, 1), tick_random); | |
| 629 | ||
| 630 | /* Define the group of floating-point conversion insns. */ | |
| 631 | func *fpconv_insns[] = { | |
| 632 | am_insn (ftoi, fsfs), | |
| 633 | am_insn (itof, fsfs), | |
| 634 | am_insn (ftod, fsfd), | |
| 635 | am_insn (dtof, fdfs), | |
| 636 | 0 | |
| 637 | }; | |
| 638 | ||
| 639 | /* Define conditional jump insns. */ | |
| 640 | def_am_insn (fbeq, , 3, 0xf8d0, d8pcsec (0)); | |
| 641 | def_am_insn (fbne, , 3, 0xf8d1, d8pcsec (0)); | |
| 642 | def_am_insn (fbgt, , 3, 0xf8d2, d8pcsec (0)); | |
| 643 | def_am_insn (fbge, , 3, 0xf8d3, d8pcsec (0)); | |
| 644 | def_am_insn (fblt, , 3, 0xf8d4, d8pcsec (0)); | |
| 645 | def_am_insn (fble, , 3, 0xf8d5, d8pcsec (0)); | |
| 646 | def_am_insn (fbuo, , 3, 0xf8d6, d8pcsec (0)); | |
| 647 | def_am_insn (fblg, , 3, 0xf8d7, d8pcsec (0)); | |
| 648 | def_am_insn (fbleg,, 3, 0xf8d8, d8pcsec (0)); | |
| 649 | def_am_insn (fbug, , 3, 0xf8d9, d8pcsec (0)); | |
| 650 | def_am_insn (fbuge,, 3, 0xf8da, d8pcsec (0)); | |
| 651 | def_am_insn (fbul, , 3, 0xf8db, d8pcsec (0)); | |
| 652 | def_am_insn (fbule,, 3, 0xf8dc, d8pcsec (0)); | |
| 653 | def_am_insn (fbue, , 3, 0xf8dd, d8pcsec (0)); | |
| 654 | def_am_insn (fleq, , 2, 0xf0d0, nothing); | |
| 655 | def_am_insn (flne, , 2, 0xf0d1, nothing); | |
| 656 | def_am_insn (flgt, , 2, 0xf0d2, nothing); | |
| 657 | def_am_insn (flge, , 2, 0xf0d3, nothing); | |
| 658 | def_am_insn (fllt, , 2, 0xf0d4, nothing); | |
| 659 | def_am_insn (flle, , 2, 0xf0d5, nothing); | |
| 660 | def_am_insn (fluo, , 2, 0xf0d6, nothing); | |
| 661 | def_am_insn (fllg, , 2, 0xf0d7, nothing); | |
| 662 | def_am_insn (flleg,, 2, 0xf0d8, nothing); | |
| 663 | def_am_insn (flug, , 2, 0xf0d9, nothing); | |
| 664 | def_am_insn (fluge,, 2, 0xf0da, nothing); | |
| 665 | def_am_insn (flul, , 2, 0xf0db, nothing); | |
| 666 | def_am_insn (flule,, 2, 0xf0dc, nothing); | |
| 667 | def_am_insn (flue, , 2, 0xf0dd, nothing); | |
| 668 | ||
| 669 | /* Define the group of conditional jump insns. */ | |
| 670 | func *condjmp_insns[] = { | |
| 671 | am_insn (fbeq, ), | |
| 672 | am_insn (fbne, ), | |
| 673 | am_insn (fbgt, ), | |
| 674 | am_insn (fbge, ), | |
| 675 | am_insn (fblt, ), | |
| 676 | am_insn (fble, ), | |
| 677 | am_insn (fbuo, ), | |
| 678 | am_insn (fblg, ), | |
| 679 | am_insn (fbleg, ), | |
| 680 | am_insn (fbug, ), | |
| 681 | am_insn (fbuge, ), | |
| 682 | am_insn (fbul, ), | |
| 683 | am_insn (fbule, ), | |
| 684 | am_insn (fbue, ), | |
| 685 | am_insn (fleq, ), | |
| 686 | am_insn (flne, ), | |
| 687 | am_insn (flgt, ), | |
| 688 | am_insn (flge, ), | |
| 689 | am_insn (fllt, ), | |
| 690 | am_insn (flle, ), | |
| 691 | am_insn (fluo, ), | |
| 692 | am_insn (fllg, ), | |
| 693 | am_insn (flleg, ), | |
| 694 | am_insn (flug, ), | |
| 695 | am_insn (fluge, ), | |
| 696 | am_insn (flul, ), | |
| 697 | am_insn (flule, ), | |
| 698 | am_insn (flue, ), | |
| 699 | 0 | |
| 700 | }; | |
| 701 | ||
| 702 | /* Define the set of all groups. */ | |
| 703 | group_t | |
| 704 | groups[] = { | |
| 705 | { "dcpf", dcpf_insns }, | |
| 706 | { "bit", bit_insns }, | |
| 707 | { "fmovs", fmovs_insns }, | |
| 708 | { "fmovd", fmovd_insns }, | |
| 709 | { "fmovc", fmovc_insns }, | |
| 710 | { "sfparith", sfparith_insns }, | |
| 711 | { "fpacc", fpacc_insns }, | |
| 712 | { "dfparith", dfparith_insns }, | |
| 713 | { "fpconv", fpconv_insns }, | |
| 714 | { "condjmp", condjmp_insns }, | |
| 715 | { 0 } | |
| 716 | }; | |
| 717 | ||
| 718 | int | |
| 719 | main(int argc, char *argv[]) | |
| 720 | { | |
| 721 | FILE *as_in = stdout, *dis_out = stderr; | |
| 722 | ||
| 723 | /* Check whether we're filtering insns. */ | |
| 724 | if (argc > 1) | |
| 725 | skip_list = argv + 1; | |
| 726 | ||
| 727 | /* Output assembler header. */ | |
| 728 | fputs ("\t.text\n" | |
| 729 | "\t.am33_2\n", | |
| 730 | as_in); | |
| 731 | /* Output comments for the testsuite-driver and the initial | |
| 732 | * disassembler output. */ | |
| 733 | fputs ("#objdump: -dr --prefix-address --show-raw-insn\n" | |
| 734 | "#name: AM33/2.0\n" | |
| 735 | "\n" | |
| 736 | ".*: +file format.*elf32-mn10300.*\n" | |
| 737 | "\n" | |
| 738 | "Disassembly of section .text:\n", | |
| 739 | dis_out); | |
| 740 | ||
| 741 | /* Now emit all (selected) insns. */ | |
| 742 | output_groups (groups, as_in, dis_out); | |
| 743 | ||
| 744 | exit (0); | |
| 745 | } |