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1 | /* Common target dependent code for GDB on AArch64 systems. |
2 | ||
3 | Copyright (C) 2009-2013 Free Software Foundation, Inc. | |
4 | Contributed by ARM Ltd. | |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "defs.h" | |
22 | ||
23 | #include "frame.h" | |
24 | #include "inferior.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "gdbcore.h" | |
27 | #include "gdb_string.h" | |
28 | #include "dis-asm.h" | |
29 | #include "regcache.h" | |
30 | #include "reggroups.h" | |
31 | #include "doublest.h" | |
32 | #include "value.h" | |
33 | #include "arch-utils.h" | |
34 | #include "osabi.h" | |
35 | #include "frame-unwind.h" | |
36 | #include "frame-base.h" | |
37 | #include "trad-frame.h" | |
38 | #include "objfiles.h" | |
39 | #include "dwarf2-frame.h" | |
40 | #include "gdbtypes.h" | |
41 | #include "prologue-value.h" | |
42 | #include "target-descriptions.h" | |
43 | #include "user-regs.h" | |
44 | #include "language.h" | |
45 | #include "infcall.h" | |
46 | ||
47 | #include "aarch64-tdep.h" | |
48 | ||
49 | #include "elf-bfd.h" | |
50 | #include "elf/aarch64.h" | |
51 | ||
52 | #include "gdb_assert.h" | |
53 | #include "vec.h" | |
54 | ||
55 | #include "features/aarch64.c" | |
56 | #include "features/aarch64-without-fpu.c" | |
57 | ||
58 | /* Pseudo register base numbers. */ | |
59 | #define AARCH64_Q0_REGNUM 0 | |
60 | #define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + 32) | |
61 | #define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32) | |
62 | #define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32) | |
63 | #define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32) | |
64 | ||
65 | /* The standard register names, and all the valid aliases for them. */ | |
66 | static const struct | |
67 | { | |
68 | const char *const name; | |
69 | int regnum; | |
70 | } aarch64_register_aliases[] = | |
71 | { | |
72 | /* 64-bit register names. */ | |
73 | {"fp", AARCH64_FP_REGNUM}, | |
74 | {"lr", AARCH64_LR_REGNUM}, | |
75 | {"sp", AARCH64_SP_REGNUM}, | |
76 | ||
77 | /* 32-bit register names. */ | |
78 | {"w0", AARCH64_X0_REGNUM + 0}, | |
79 | {"w1", AARCH64_X0_REGNUM + 1}, | |
80 | {"w2", AARCH64_X0_REGNUM + 2}, | |
81 | {"w3", AARCH64_X0_REGNUM + 3}, | |
82 | {"w4", AARCH64_X0_REGNUM + 4}, | |
83 | {"w5", AARCH64_X0_REGNUM + 5}, | |
84 | {"w6", AARCH64_X0_REGNUM + 6}, | |
85 | {"w7", AARCH64_X0_REGNUM + 7}, | |
86 | {"w8", AARCH64_X0_REGNUM + 8}, | |
87 | {"w9", AARCH64_X0_REGNUM + 9}, | |
88 | {"w10", AARCH64_X0_REGNUM + 10}, | |
89 | {"w11", AARCH64_X0_REGNUM + 11}, | |
90 | {"w12", AARCH64_X0_REGNUM + 12}, | |
91 | {"w13", AARCH64_X0_REGNUM + 13}, | |
92 | {"w14", AARCH64_X0_REGNUM + 14}, | |
93 | {"w15", AARCH64_X0_REGNUM + 15}, | |
94 | {"w16", AARCH64_X0_REGNUM + 16}, | |
95 | {"w17", AARCH64_X0_REGNUM + 17}, | |
96 | {"w18", AARCH64_X0_REGNUM + 18}, | |
97 | {"w19", AARCH64_X0_REGNUM + 19}, | |
98 | {"w20", AARCH64_X0_REGNUM + 20}, | |
99 | {"w21", AARCH64_X0_REGNUM + 21}, | |
100 | {"w22", AARCH64_X0_REGNUM + 22}, | |
101 | {"w23", AARCH64_X0_REGNUM + 23}, | |
102 | {"w24", AARCH64_X0_REGNUM + 24}, | |
103 | {"w25", AARCH64_X0_REGNUM + 25}, | |
104 | {"w26", AARCH64_X0_REGNUM + 26}, | |
105 | {"w27", AARCH64_X0_REGNUM + 27}, | |
106 | {"w28", AARCH64_X0_REGNUM + 28}, | |
107 | {"w29", AARCH64_X0_REGNUM + 29}, | |
108 | {"w30", AARCH64_X0_REGNUM + 30}, | |
109 | ||
110 | /* specials */ | |
111 | {"ip0", AARCH64_X0_REGNUM + 16}, | |
112 | {"ip1", AARCH64_X0_REGNUM + 17} | |
113 | }; | |
114 | ||
115 | /* The required core 'R' registers. */ | |
116 | static const char *const aarch64_r_register_names[] = | |
117 | { | |
118 | /* These registers must appear in consecutive RAW register number | |
119 | order and they must begin with AARCH64_X0_REGNUM! */ | |
120 | "x0", "x1", "x2", "x3", | |
121 | "x4", "x5", "x6", "x7", | |
122 | "x8", "x9", "x10", "x11", | |
123 | "x12", "x13", "x14", "x15", | |
124 | "x16", "x17", "x18", "x19", | |
125 | "x20", "x21", "x22", "x23", | |
126 | "x24", "x25", "x26", "x27", | |
127 | "x28", "x29", "x30", "sp", | |
128 | "pc", "cpsr" | |
129 | }; | |
130 | ||
131 | /* The FP/SIMD 'V' registers. */ | |
132 | static const char *const aarch64_v_register_names[] = | |
133 | { | |
134 | /* These registers must appear in consecutive RAW register number | |
135 | order and they must begin with AARCH64_V0_REGNUM! */ | |
136 | "v0", "v1", "v2", "v3", | |
137 | "v4", "v5", "v6", "v7", | |
138 | "v8", "v9", "v10", "v11", | |
139 | "v12", "v13", "v14", "v15", | |
140 | "v16", "v17", "v18", "v19", | |
141 | "v20", "v21", "v22", "v23", | |
142 | "v24", "v25", "v26", "v27", | |
143 | "v28", "v29", "v30", "v31", | |
144 | "fpsr", | |
145 | "fpcr" | |
146 | }; | |
147 | ||
148 | /* AArch64 prologue cache structure. */ | |
149 | struct aarch64_prologue_cache | |
150 | { | |
151 | /* The stack pointer at the time this frame was created; i.e. the | |
152 | caller's stack pointer when this function was called. It is used | |
153 | to identify this frame. */ | |
154 | CORE_ADDR prev_sp; | |
155 | ||
156 | /* The frame base for this frame is just prev_sp - frame size. | |
157 | FRAMESIZE is the distance from the frame pointer to the | |
158 | initial stack pointer. */ | |
159 | int framesize; | |
160 | ||
161 | /* The register used to hold the frame pointer for this frame. */ | |
162 | int framereg; | |
163 | ||
164 | /* Saved register offsets. */ | |
165 | struct trad_frame_saved_reg *saved_regs; | |
166 | }; | |
167 | ||
168 | /* Toggle this file's internal debugging dump. */ | |
169 | static int aarch64_debug; | |
170 | ||
171 | static void | |
172 | show_aarch64_debug (struct ui_file *file, int from_tty, | |
173 | struct cmd_list_element *c, const char *value) | |
174 | { | |
175 | fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value); | |
176 | } | |
177 | ||
178 | /* Extract a signed value from a bit field within an instruction | |
179 | encoding. | |
180 | ||
181 | INSN is the instruction opcode. | |
182 | ||
183 | WIDTH specifies the width of the bit field to extract (in bits). | |
184 | ||
185 | OFFSET specifies the least significant bit of the field where bits | |
186 | are numbered zero counting from least to most significant. */ | |
187 | ||
188 | static int32_t | |
189 | extract_signed_bitfield (uint32_t insn, unsigned width, unsigned offset) | |
190 | { | |
191 | unsigned shift_l = sizeof (int32_t) * 8 - (offset + width); | |
192 | unsigned shift_r = sizeof (int32_t) * 8 - width; | |
193 | ||
194 | return ((int32_t) insn << shift_l) >> shift_r; | |
195 | } | |
196 | ||
197 | /* Determine if specified bits within an instruction opcode matches a | |
198 | specific pattern. | |
199 | ||
200 | INSN is the instruction opcode. | |
201 | ||
202 | MASK specifies the bits within the opcode that are to be tested | |
203 | agsinst for a match with PATTERN. */ | |
204 | ||
205 | static int | |
206 | decode_masked_match (uint32_t insn, uint32_t mask, uint32_t pattern) | |
207 | { | |
208 | return (insn & mask) == pattern; | |
209 | } | |
210 | ||
211 | /* Decode an opcode if it represents an immediate ADD or SUB instruction. | |
212 | ||
213 | ADDR specifies the address of the opcode. | |
214 | INSN specifies the opcode to test. | |
215 | RD receives the 'rd' field from the decoded instruction. | |
216 | RN receives the 'rn' field from the decoded instruction. | |
217 | ||
218 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
219 | static int | |
220 | decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd, unsigned *rn, | |
221 | int32_t *imm) | |
222 | { | |
223 | if ((insn & 0x9f000000) == 0x91000000) | |
224 | { | |
225 | unsigned shift; | |
226 | unsigned op_is_sub; | |
227 | ||
228 | *rd = (insn >> 0) & 0x1f; | |
229 | *rn = (insn >> 5) & 0x1f; | |
230 | *imm = (insn >> 10) & 0xfff; | |
231 | shift = (insn >> 22) & 0x3; | |
232 | op_is_sub = (insn >> 30) & 0x1; | |
233 | ||
234 | switch (shift) | |
235 | { | |
236 | case 0: | |
237 | break; | |
238 | case 1: | |
239 | *imm <<= 12; | |
240 | break; | |
241 | default: | |
242 | /* UNDEFINED */ | |
243 | return 0; | |
244 | } | |
245 | ||
246 | if (op_is_sub) | |
247 | *imm = -*imm; | |
248 | ||
249 | if (aarch64_debug) | |
250 | fprintf_unfiltered (gdb_stdlog, | |
251 | "decode: 0x%s 0x%x add x%u, x%u, #%d\n", | |
252 | core_addr_to_string_nz (addr), insn, *rd, *rn, | |
253 | *imm); | |
254 | return 1; | |
255 | } | |
256 | return 0; | |
257 | } | |
258 | ||
259 | /* Decode an opcode if it represents an ADRP instruction. | |
260 | ||
261 | ADDR specifies the address of the opcode. | |
262 | INSN specifies the opcode to test. | |
263 | RD receives the 'rd' field from the decoded instruction. | |
264 | ||
265 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
266 | ||
267 | static int | |
268 | decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd) | |
269 | { | |
270 | if (decode_masked_match (insn, 0x9f000000, 0x90000000)) | |
271 | { | |
272 | *rd = (insn >> 0) & 0x1f; | |
273 | ||
274 | if (aarch64_debug) | |
275 | fprintf_unfiltered (gdb_stdlog, | |
276 | "decode: 0x%s 0x%x adrp x%u, #?\n", | |
277 | core_addr_to_string_nz (addr), insn, *rd); | |
278 | return 1; | |
279 | } | |
280 | return 0; | |
281 | } | |
282 | ||
283 | /* Decode an opcode if it represents an branch immediate or branch | |
284 | and link immediate instruction. | |
285 | ||
286 | ADDR specifies the address of the opcode. | |
287 | INSN specifies the opcode to test. | |
288 | LINK receives the 'link' bit from the decoded instruction. | |
289 | OFFSET receives the immediate offset from the decoded instruction. | |
290 | ||
291 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
292 | ||
293 | static int | |
294 | decode_b (CORE_ADDR addr, uint32_t insn, unsigned *link, int32_t *offset) | |
295 | { | |
296 | /* b 0001 01ii iiii iiii iiii iiii iiii iiii */ | |
297 | /* bl 1001 01ii iiii iiii iiii iiii iiii iiii */ | |
298 | if (decode_masked_match (insn, 0x7c000000, 0x14000000)) | |
299 | { | |
300 | *link = insn >> 31; | |
301 | *offset = extract_signed_bitfield (insn, 26, 0) << 2; | |
302 | ||
303 | if (aarch64_debug) | |
304 | fprintf_unfiltered (gdb_stdlog, | |
305 | "decode: 0x%s 0x%x %s 0x%s\n", | |
306 | core_addr_to_string_nz (addr), insn, | |
307 | *link ? "bl" : "b", | |
308 | core_addr_to_string_nz (addr + *offset)); | |
309 | ||
310 | return 1; | |
311 | } | |
312 | return 0; | |
313 | } | |
314 | ||
315 | /* Decode an opcode if it represents a conditional branch instruction. | |
316 | ||
317 | ADDR specifies the address of the opcode. | |
318 | INSN specifies the opcode to test. | |
319 | COND receives the branch condition field from the decoded | |
320 | instruction. | |
321 | OFFSET receives the immediate offset from the decoded instruction. | |
322 | ||
323 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
324 | ||
325 | static int | |
326 | decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond, int32_t *offset) | |
327 | { | |
328 | if (decode_masked_match (insn, 0xfe000000, 0x54000000)) | |
329 | { | |
330 | *cond = (insn >> 0) & 0xf; | |
331 | *offset = extract_signed_bitfield (insn, 19, 5) << 2; | |
332 | ||
333 | if (aarch64_debug) | |
334 | fprintf_unfiltered (gdb_stdlog, | |
335 | "decode: 0x%s 0x%x b<%u> 0x%s\n", | |
336 | core_addr_to_string_nz (addr), insn, *cond, | |
337 | core_addr_to_string_nz (addr + *offset)); | |
338 | return 1; | |
339 | } | |
340 | return 0; | |
341 | } | |
342 | ||
343 | /* Decode an opcode if it represents a branch via register instruction. | |
344 | ||
345 | ADDR specifies the address of the opcode. | |
346 | INSN specifies the opcode to test. | |
347 | LINK receives the 'link' bit from the decoded instruction. | |
348 | RN receives the 'rn' field from the decoded instruction. | |
349 | ||
350 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
351 | ||
352 | static int | |
353 | decode_br (CORE_ADDR addr, uint32_t insn, unsigned *link, unsigned *rn) | |
354 | { | |
355 | /* 8 4 0 6 2 8 4 0 */ | |
356 | /* blr 110101100011111100000000000rrrrr */ | |
357 | /* br 110101100001111100000000000rrrrr */ | |
358 | if (decode_masked_match (insn, 0xffdffc1f, 0xd61f0000)) | |
359 | { | |
360 | *link = (insn >> 21) & 1; | |
361 | *rn = (insn >> 5) & 0x1f; | |
362 | ||
363 | if (aarch64_debug) | |
364 | fprintf_unfiltered (gdb_stdlog, | |
365 | "decode: 0x%s 0x%x %s 0x%x\n", | |
366 | core_addr_to_string_nz (addr), insn, | |
367 | *link ? "blr" : "br", *rn); | |
368 | ||
369 | return 1; | |
370 | } | |
371 | return 0; | |
372 | } | |
373 | ||
374 | /* Decode an opcode if it represents a CBZ or CBNZ instruction. | |
375 | ||
376 | ADDR specifies the address of the opcode. | |
377 | INSN specifies the opcode to test. | |
378 | IS64 receives the 'sf' field from the decoded instruction. | |
379 | OP receives the 'op' field from the decoded instruction. | |
380 | RN receives the 'rn' field from the decoded instruction. | |
381 | OFFSET receives the 'imm19' field from the decoded instruction. | |
382 | ||
383 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
384 | ||
385 | static int | |
386 | decode_cb (CORE_ADDR addr, | |
387 | uint32_t insn, int *is64, unsigned *op, unsigned *rn, | |
388 | int32_t *offset) | |
389 | { | |
390 | if (decode_masked_match (insn, 0x7e000000, 0x34000000)) | |
391 | { | |
392 | /* cbz T011 010o iiii iiii iiii iiii iiir rrrr */ | |
393 | /* cbnz T011 010o iiii iiii iiii iiii iiir rrrr */ | |
394 | ||
395 | *rn = (insn >> 0) & 0x1f; | |
396 | *is64 = (insn >> 31) & 0x1; | |
397 | *op = (insn >> 24) & 0x1; | |
398 | *offset = extract_signed_bitfield (insn, 19, 5) << 2; | |
399 | ||
400 | if (aarch64_debug) | |
401 | fprintf_unfiltered (gdb_stdlog, | |
402 | "decode: 0x%s 0x%x %s 0x%s\n", | |
403 | core_addr_to_string_nz (addr), insn, | |
404 | *op ? "cbnz" : "cbz", | |
405 | core_addr_to_string_nz (addr + *offset)); | |
406 | return 1; | |
407 | } | |
408 | return 0; | |
409 | } | |
410 | ||
411 | /* Decode an opcode if it represents a ERET instruction. | |
412 | ||
413 | ADDR specifies the address of the opcode. | |
414 | INSN specifies the opcode to test. | |
415 | ||
416 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
417 | ||
418 | static int | |
419 | decode_eret (CORE_ADDR addr, uint32_t insn) | |
420 | { | |
421 | /* eret 1101 0110 1001 1111 0000 0011 1110 0000 */ | |
422 | if (insn == 0xd69f03e0) | |
423 | { | |
424 | if (aarch64_debug) | |
425 | fprintf_unfiltered (gdb_stdlog, "decode: 0x%s 0x%x eret\n", | |
426 | core_addr_to_string_nz (addr), insn); | |
427 | return 1; | |
428 | } | |
429 | return 0; | |
430 | } | |
431 | ||
432 | /* Decode an opcode if it represents a MOVZ instruction. | |
433 | ||
434 | ADDR specifies the address of the opcode. | |
435 | INSN specifies the opcode to test. | |
436 | RD receives the 'rd' field from the decoded instruction. | |
437 | ||
438 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
439 | ||
440 | static int | |
441 | decode_movz (CORE_ADDR addr, uint32_t insn, unsigned *rd) | |
442 | { | |
443 | if (decode_masked_match (insn, 0xff800000, 0x52800000)) | |
444 | { | |
445 | *rd = (insn >> 0) & 0x1f; | |
446 | ||
447 | if (aarch64_debug) | |
448 | fprintf_unfiltered (gdb_stdlog, | |
449 | "decode: 0x%s 0x%x movz x%u, #?\n", | |
450 | core_addr_to_string_nz (addr), insn, *rd); | |
451 | return 1; | |
452 | } | |
453 | return 0; | |
454 | } | |
455 | ||
456 | /* Decode an opcode if it represents a ORR (shifted register) | |
457 | instruction. | |
458 | ||
459 | ADDR specifies the address of the opcode. | |
460 | INSN specifies the opcode to test. | |
461 | RD receives the 'rd' field from the decoded instruction. | |
462 | RN receives the 'rn' field from the decoded instruction. | |
463 | RM receives the 'rm' field from the decoded instruction. | |
464 | IMM receives the 'imm6' field from the decoded instruction. | |
465 | ||
466 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
467 | ||
468 | static int | |
469 | decode_orr_shifted_register_x (CORE_ADDR addr, | |
470 | uint32_t insn, unsigned *rd, unsigned *rn, | |
471 | unsigned *rm, int32_t *imm) | |
472 | { | |
473 | if (decode_masked_match (insn, 0xff200000, 0xaa000000)) | |
474 | { | |
475 | *rd = (insn >> 0) & 0x1f; | |
476 | *rn = (insn >> 5) & 0x1f; | |
477 | *rm = (insn >> 16) & 0x1f; | |
478 | *imm = (insn >> 10) & 0x3f; | |
479 | ||
480 | if (aarch64_debug) | |
481 | fprintf_unfiltered (gdb_stdlog, | |
482 | "decode: 0x%s 0x%x orr x%u, x%u, x%u, #%u\n", | |
483 | core_addr_to_string_nz (addr), insn, *rd, | |
484 | *rn, *rm, *imm); | |
485 | return 1; | |
486 | } | |
487 | return 0; | |
488 | } | |
489 | ||
490 | /* Decode an opcode if it represents a RET instruction. | |
491 | ||
492 | ADDR specifies the address of the opcode. | |
493 | INSN specifies the opcode to test. | |
494 | RN receives the 'rn' field from the decoded instruction. | |
495 | ||
496 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
497 | ||
498 | static int | |
499 | decode_ret (CORE_ADDR addr, uint32_t insn, unsigned *rn) | |
500 | { | |
501 | if (decode_masked_match (insn, 0xfffffc1f, 0xd65f0000)) | |
502 | { | |
503 | *rn = (insn >> 5) & 0x1f; | |
504 | if (aarch64_debug) | |
505 | fprintf_unfiltered (gdb_stdlog, | |
506 | "decode: 0x%s 0x%x ret x%u\n", | |
507 | core_addr_to_string_nz (addr), insn, *rn); | |
508 | return 1; | |
509 | } | |
510 | return 0; | |
511 | } | |
512 | ||
513 | /* Decode an opcode if it represents the following instruction: | |
514 | STP rt, rt2, [rn, #imm] | |
515 | ||
516 | ADDR specifies the address of the opcode. | |
517 | INSN specifies the opcode to test. | |
518 | RT1 receives the 'rt' field from the decoded instruction. | |
519 | RT2 receives the 'rt2' field from the decoded instruction. | |
520 | RN receives the 'rn' field from the decoded instruction. | |
521 | IMM receives the 'imm' field from the decoded instruction. | |
522 | ||
523 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
524 | ||
525 | static int | |
526 | decode_stp_offset (CORE_ADDR addr, | |
527 | uint32_t insn, | |
528 | unsigned *rt1, unsigned *rt2, unsigned *rn, int32_t *imm) | |
529 | { | |
530 | if (decode_masked_match (insn, 0xffc00000, 0xa9000000)) | |
531 | { | |
532 | *rt1 = (insn >> 0) & 0x1f; | |
533 | *rn = (insn >> 5) & 0x1f; | |
534 | *rt2 = (insn >> 10) & 0x1f; | |
535 | *imm = extract_signed_bitfield (insn, 7, 15); | |
536 | *imm <<= 3; | |
537 | ||
538 | if (aarch64_debug) | |
539 | fprintf_unfiltered (gdb_stdlog, | |
540 | "decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]\n", | |
541 | core_addr_to_string_nz (addr), insn, | |
542 | *rt1, *rt2, *rn, *imm); | |
543 | return 1; | |
544 | } | |
545 | return 0; | |
546 | } | |
547 | ||
548 | /* Decode an opcode if it represents the following instruction: | |
549 | STP rt, rt2, [rn, #imm]! | |
550 | ||
551 | ADDR specifies the address of the opcode. | |
552 | INSN specifies the opcode to test. | |
553 | RT1 receives the 'rt' field from the decoded instruction. | |
554 | RT2 receives the 'rt2' field from the decoded instruction. | |
555 | RN receives the 'rn' field from the decoded instruction. | |
556 | IMM receives the 'imm' field from the decoded instruction. | |
557 | ||
558 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
559 | ||
560 | static int | |
561 | decode_stp_offset_wb (CORE_ADDR addr, | |
562 | uint32_t insn, | |
563 | unsigned *rt1, unsigned *rt2, unsigned *rn, | |
564 | int32_t *imm) | |
565 | { | |
566 | if (decode_masked_match (insn, 0xffc00000, 0xa9800000)) | |
567 | { | |
568 | *rt1 = (insn >> 0) & 0x1f; | |
569 | *rn = (insn >> 5) & 0x1f; | |
570 | *rt2 = (insn >> 10) & 0x1f; | |
571 | *imm = extract_signed_bitfield (insn, 7, 15); | |
572 | *imm <<= 3; | |
573 | ||
574 | if (aarch64_debug) | |
575 | fprintf_unfiltered (gdb_stdlog, | |
576 | "decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]!\n", | |
577 | core_addr_to_string_nz (addr), insn, | |
578 | *rt1, *rt2, *rn, *imm); | |
579 | return 1; | |
580 | } | |
581 | return 0; | |
582 | } | |
583 | ||
584 | /* Decode an opcode if it represents the following instruction: | |
585 | STUR rt, [rn, #imm] | |
586 | ||
587 | ADDR specifies the address of the opcode. | |
588 | INSN specifies the opcode to test. | |
589 | IS64 receives size field from the decoded instruction. | |
590 | RT receives the 'rt' field from the decoded instruction. | |
591 | RN receives the 'rn' field from the decoded instruction. | |
592 | IMM receives the 'imm' field from the decoded instruction. | |
593 | ||
594 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
595 | ||
596 | static int | |
597 | decode_stur (CORE_ADDR addr, uint32_t insn, int *is64, unsigned *rt, | |
598 | unsigned *rn, int32_t *imm) | |
599 | { | |
600 | if (decode_masked_match (insn, 0xbfe00c00, 0xb8000000)) | |
601 | { | |
602 | *is64 = (insn >> 30) & 1; | |
603 | *rt = (insn >> 0) & 0x1f; | |
604 | *rn = (insn >> 5) & 0x1f; | |
605 | *imm = extract_signed_bitfield (insn, 9, 12); | |
606 | ||
607 | if (aarch64_debug) | |
608 | fprintf_unfiltered (gdb_stdlog, | |
609 | "decode: 0x%s 0x%x stur %c%u, [x%u + #%d]\n", | |
610 | core_addr_to_string_nz (addr), insn, | |
611 | *is64 ? 'x' : 'w', *rt, *rn, *imm); | |
612 | return 1; | |
613 | } | |
614 | return 0; | |
615 | } | |
616 | ||
617 | /* Decode an opcode if it represents a TB or TBNZ instruction. | |
618 | ||
619 | ADDR specifies the address of the opcode. | |
620 | INSN specifies the opcode to test. | |
621 | OP receives the 'op' field from the decoded instruction. | |
622 | BIT receives the bit position field from the decoded instruction. | |
623 | RT receives 'rt' field from the decoded instruction. | |
624 | IMM receives 'imm' field from the decoded instruction. | |
625 | ||
626 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
627 | ||
628 | static int | |
629 | decode_tb (CORE_ADDR addr, | |
630 | uint32_t insn, unsigned *op, unsigned *bit, unsigned *rt, | |
631 | int32_t *imm) | |
632 | { | |
633 | if (decode_masked_match (insn, 0x7e000000, 0x36000000)) | |
634 | { | |
635 | /* tbz b011 0110 bbbb biii iiii iiii iiir rrrr */ | |
636 | /* tbnz B011 0111 bbbb biii iiii iiii iiir rrrr */ | |
637 | ||
638 | *rt = (insn >> 0) & 0x1f; | |
639 | *op = insn & (1 << 24); | |
640 | *bit = ((insn >> (31 - 4)) & 0x20) | ((insn >> 19) & 0x1f); | |
641 | *imm = extract_signed_bitfield (insn, 14, 5) << 2; | |
642 | ||
643 | if (aarch64_debug) | |
644 | fprintf_unfiltered (gdb_stdlog, | |
645 | "decode: 0x%s 0x%x %s x%u, #%u, 0x%s\n", | |
646 | core_addr_to_string_nz (addr), insn, | |
647 | *op ? "tbnz" : "tbz", *rt, *bit, | |
648 | core_addr_to_string_nz (addr + *imm)); | |
649 | return 1; | |
650 | } | |
651 | return 0; | |
652 | } | |
653 | ||
654 | /* Analyze a prologue, looking for a recognizable stack frame | |
655 | and frame pointer. Scan until we encounter a store that could | |
656 | clobber the stack frame unexpectedly, or an unknown instruction. */ | |
657 | ||
658 | static CORE_ADDR | |
659 | aarch64_analyze_prologue (struct gdbarch *gdbarch, | |
660 | CORE_ADDR start, CORE_ADDR limit, | |
661 | struct aarch64_prologue_cache *cache) | |
662 | { | |
663 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
664 | int i; | |
665 | pv_t regs[AARCH64_X_REGISTER_COUNT]; | |
666 | struct pv_area *stack; | |
667 | struct cleanup *back_to; | |
668 | ||
669 | for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
670 | regs[i] = pv_register (i, 0); | |
671 | stack = make_pv_area (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch)); | |
672 | back_to = make_cleanup_free_pv_area (stack); | |
673 | ||
674 | for (; start < limit; start += 4) | |
675 | { | |
676 | uint32_t insn; | |
677 | unsigned rd; | |
678 | unsigned rn; | |
679 | unsigned rm; | |
680 | unsigned rt; | |
681 | unsigned rt1; | |
682 | unsigned rt2; | |
683 | int op_is_sub; | |
684 | int32_t imm; | |
685 | unsigned cond; | |
686 | unsigned is64; | |
687 | unsigned is_link; | |
688 | unsigned op; | |
689 | unsigned bit; | |
690 | int32_t offset; | |
691 | ||
692 | insn = read_memory_unsigned_integer (start, 4, byte_order_for_code); | |
693 | ||
694 | if (decode_add_sub_imm (start, insn, &rd, &rn, &imm)) | |
695 | regs[rd] = pv_add_constant (regs[rn], imm); | |
696 | else if (decode_adrp (start, insn, &rd)) | |
697 | regs[rd] = pv_unknown (); | |
698 | else if (decode_b (start, insn, &is_link, &offset)) | |
699 | { | |
700 | /* Stop analysis on branch. */ | |
701 | break; | |
702 | } | |
703 | else if (decode_bcond (start, insn, &cond, &offset)) | |
704 | { | |
705 | /* Stop analysis on branch. */ | |
706 | break; | |
707 | } | |
708 | else if (decode_br (start, insn, &is_link, &rn)) | |
709 | { | |
710 | /* Stop analysis on branch. */ | |
711 | break; | |
712 | } | |
713 | else if (decode_cb (start, insn, &is64, &op, &rn, &offset)) | |
714 | { | |
715 | /* Stop analysis on branch. */ | |
716 | break; | |
717 | } | |
718 | else if (decode_eret (start, insn)) | |
719 | { | |
720 | /* Stop analysis on branch. */ | |
721 | break; | |
722 | } | |
723 | else if (decode_movz (start, insn, &rd)) | |
724 | regs[rd] = pv_unknown (); | |
725 | else | |
726 | if (decode_orr_shifted_register_x (start, insn, &rd, &rn, &rm, &imm)) | |
727 | { | |
728 | if (imm == 0 && rn == 31) | |
729 | regs[rd] = regs[rm]; | |
730 | else | |
731 | { | |
732 | if (aarch64_debug) | |
733 | fprintf_unfiltered | |
734 | (gdb_stdlog, | |
735 | "aarch64: prologue analysis gave up addr=0x%s " | |
736 | "opcode=0x%x (orr x register)\n", | |
737 | core_addr_to_string_nz (start), | |
738 | insn); | |
739 | break; | |
740 | } | |
741 | } | |
742 | else if (decode_ret (start, insn, &rn)) | |
743 | { | |
744 | /* Stop analysis on branch. */ | |
745 | break; | |
746 | } | |
747 | else if (decode_stur (start, insn, &is64, &rt, &rn, &offset)) | |
748 | { | |
749 | pv_area_store (stack, pv_add_constant (regs[rn], offset), | |
750 | is64 ? 8 : 4, regs[rt]); | |
751 | } | |
752 | else if (decode_stp_offset (start, insn, &rt1, &rt2, &rn, &imm)) | |
753 | { | |
754 | /* If recording this store would invalidate the store area | |
755 | (perhaps because rn is not known) then we should abandon | |
756 | further prologue analysis. */ | |
757 | if (pv_area_store_would_trash (stack, | |
758 | pv_add_constant (regs[rn], imm))) | |
759 | break; | |
760 | ||
761 | if (pv_area_store_would_trash (stack, | |
762 | pv_add_constant (regs[rn], imm + 8))) | |
763 | break; | |
764 | ||
765 | pv_area_store (stack, pv_add_constant (regs[rn], imm), 8, | |
766 | regs[rt1]); | |
767 | pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8, | |
768 | regs[rt2]); | |
769 | } | |
770 | else if (decode_stp_offset_wb (start, insn, &rt1, &rt2, &rn, &imm)) | |
771 | { | |
772 | /* If recording this store would invalidate the store area | |
773 | (perhaps because rn is not known) then we should abandon | |
774 | further prologue analysis. */ | |
775 | if (pv_area_store_would_trash (stack, | |
776 | pv_add_constant (regs[rn], imm)) || | |
777 | pv_area_store_would_trash (stack, | |
778 | pv_add_constant (regs[rn], imm + 8))) | |
779 | break; | |
780 | ||
781 | pv_area_store (stack, pv_add_constant (regs[rn], imm), 8, | |
782 | regs[rt1]); | |
783 | pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8, | |
784 | regs[rt2]); | |
785 | regs[rn] = pv_add_constant (regs[rn], imm); | |
786 | } | |
787 | else if (decode_tb (start, insn, &op, &bit, &rn, &offset)) | |
788 | { | |
789 | /* Stop analysis on branch. */ | |
790 | break; | |
791 | } | |
792 | else | |
793 | { | |
794 | if (aarch64_debug) | |
795 | fprintf_unfiltered (gdb_stdlog, | |
796 | "aarch64: prologue analysis gave up addr=0x%s" | |
797 | " opcode=0x%x\n", | |
798 | core_addr_to_string_nz (start), insn); | |
799 | break; | |
800 | } | |
801 | } | |
802 | ||
803 | if (cache == NULL) | |
804 | { | |
805 | do_cleanups (back_to); | |
806 | return start; | |
807 | } | |
808 | ||
809 | if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM)) | |
810 | { | |
811 | /* Frame pointer is fp. Frame size is constant. */ | |
812 | cache->framereg = AARCH64_FP_REGNUM; | |
813 | cache->framesize = -regs[AARCH64_FP_REGNUM].k; | |
814 | } | |
815 | else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM)) | |
816 | { | |
817 | /* Try the stack pointer. */ | |
818 | cache->framesize = -regs[AARCH64_SP_REGNUM].k; | |
819 | cache->framereg = AARCH64_SP_REGNUM; | |
820 | } | |
821 | else | |
822 | { | |
823 | /* We're just out of luck. We don't know where the frame is. */ | |
824 | cache->framereg = -1; | |
825 | cache->framesize = 0; | |
826 | } | |
827 | ||
828 | for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
829 | { | |
830 | CORE_ADDR offset; | |
831 | ||
832 | if (pv_area_find_reg (stack, gdbarch, i, &offset)) | |
833 | cache->saved_regs[i].addr = offset; | |
834 | } | |
835 | ||
836 | do_cleanups (back_to); | |
837 | return start; | |
838 | } | |
839 | ||
840 | /* Implement the "skip_prologue" gdbarch method. */ | |
841 | ||
842 | static CORE_ADDR | |
843 | aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
844 | { | |
845 | unsigned long inst; | |
846 | CORE_ADDR skip_pc; | |
847 | CORE_ADDR func_addr, limit_pc; | |
848 | struct symtab_and_line sal; | |
849 | ||
850 | /* See if we can determine the end of the prologue via the symbol | |
851 | table. If so, then return either PC, or the PC after the | |
852 | prologue, whichever is greater. */ | |
853 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
854 | { | |
855 | CORE_ADDR post_prologue_pc | |
856 | = skip_prologue_using_sal (gdbarch, func_addr); | |
857 | ||
858 | if (post_prologue_pc != 0) | |
859 | return max (pc, post_prologue_pc); | |
860 | } | |
861 | ||
862 | /* Can't determine prologue from the symbol table, need to examine | |
863 | instructions. */ | |
864 | ||
865 | /* Find an upper limit on the function prologue using the debug | |
866 | information. If the debug information could not be used to | |
867 | provide that bound, then use an arbitrary large number as the | |
868 | upper bound. */ | |
869 | limit_pc = skip_prologue_using_sal (gdbarch, pc); | |
870 | if (limit_pc == 0) | |
871 | limit_pc = pc + 128; /* Magic. */ | |
872 | ||
873 | /* Try disassembling prologue. */ | |
874 | return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL); | |
875 | } | |
876 | ||
877 | /* Scan the function prologue for THIS_FRAME and populate the prologue | |
878 | cache CACHE. */ | |
879 | ||
880 | static void | |
881 | aarch64_scan_prologue (struct frame_info *this_frame, | |
882 | struct aarch64_prologue_cache *cache) | |
883 | { | |
884 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); | |
885 | CORE_ADDR prologue_start; | |
886 | CORE_ADDR prologue_end; | |
887 | CORE_ADDR prev_pc = get_frame_pc (this_frame); | |
888 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
889 | ||
890 | /* Assume we do not find a frame. */ | |
891 | cache->framereg = -1; | |
892 | cache->framesize = 0; | |
893 | ||
894 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, | |
895 | &prologue_end)) | |
896 | { | |
897 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
898 | ||
899 | if (sal.line == 0) | |
900 | { | |
901 | /* No line info so use the current PC. */ | |
902 | prologue_end = prev_pc; | |
903 | } | |
904 | else if (sal.end < prologue_end) | |
905 | { | |
906 | /* The next line begins after the function end. */ | |
907 | prologue_end = sal.end; | |
908 | } | |
909 | ||
910 | prologue_end = min (prologue_end, prev_pc); | |
911 | aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); | |
912 | } | |
913 | else | |
914 | { | |
915 | CORE_ADDR frame_loc; | |
916 | LONGEST saved_fp; | |
917 | LONGEST saved_lr; | |
918 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
919 | ||
920 | frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM); | |
921 | if (frame_loc == 0) | |
922 | return; | |
923 | ||
924 | cache->framereg = AARCH64_FP_REGNUM; | |
925 | cache->framesize = 16; | |
926 | cache->saved_regs[29].addr = 0; | |
927 | cache->saved_regs[30].addr = 8; | |
928 | } | |
929 | } | |
930 | ||
931 | /* Allocate an aarch64_prologue_cache and fill it with information | |
932 | about the prologue of *THIS_FRAME. */ | |
933 | ||
934 | static struct aarch64_prologue_cache * | |
935 | aarch64_make_prologue_cache (struct frame_info *this_frame) | |
936 | { | |
937 | struct aarch64_prologue_cache *cache; | |
938 | CORE_ADDR unwound_fp; | |
939 | int reg; | |
940 | ||
941 | cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache); | |
942 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
943 | ||
944 | aarch64_scan_prologue (this_frame, cache); | |
945 | ||
946 | if (cache->framereg == -1) | |
947 | return cache; | |
948 | ||
949 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); | |
950 | if (unwound_fp == 0) | |
951 | return cache; | |
952 | ||
953 | cache->prev_sp = unwound_fp + cache->framesize; | |
954 | ||
955 | /* Calculate actual addresses of saved registers using offsets | |
956 | determined by aarch64_analyze_prologue. */ | |
957 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) | |
958 | if (trad_frame_addr_p (cache->saved_regs, reg)) | |
959 | cache->saved_regs[reg].addr += cache->prev_sp; | |
960 | ||
961 | return cache; | |
962 | } | |
963 | ||
964 | /* Our frame ID for a normal frame is the current function's starting | |
965 | PC and the caller's SP when we were called. */ | |
966 | ||
967 | static void | |
968 | aarch64_prologue_this_id (struct frame_info *this_frame, | |
969 | void **this_cache, struct frame_id *this_id) | |
970 | { | |
971 | struct aarch64_prologue_cache *cache; | |
972 | struct frame_id id; | |
973 | CORE_ADDR pc, func; | |
974 | ||
975 | if (*this_cache == NULL) | |
976 | *this_cache = aarch64_make_prologue_cache (this_frame); | |
977 | cache = *this_cache; | |
978 | ||
979 | /* This is meant to halt the backtrace at "_start". */ | |
980 | pc = get_frame_pc (this_frame); | |
981 | if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc) | |
982 | return; | |
983 | ||
984 | /* If we've hit a wall, stop. */ | |
985 | if (cache->prev_sp == 0) | |
986 | return; | |
987 | ||
988 | func = get_frame_func (this_frame); | |
989 | id = frame_id_build (cache->prev_sp, func); | |
990 | *this_id = id; | |
991 | } | |
992 | ||
993 | /* Implement the "prev_register" frame_unwind method. */ | |
994 | ||
995 | static struct value * | |
996 | aarch64_prologue_prev_register (struct frame_info *this_frame, | |
997 | void **this_cache, int prev_regnum) | |
998 | { | |
999 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1000 | struct aarch64_prologue_cache *cache; | |
1001 | ||
1002 | if (*this_cache == NULL) | |
1003 | *this_cache = aarch64_make_prologue_cache (this_frame); | |
1004 | cache = *this_cache; | |
1005 | ||
1006 | /* If we are asked to unwind the PC, then we need to return the LR | |
1007 | instead. The prologue may save PC, but it will point into this | |
1008 | frame's prologue, not the next frame's resume location. */ | |
1009 | if (prev_regnum == AARCH64_PC_REGNUM) | |
1010 | { | |
1011 | CORE_ADDR lr; | |
1012 | ||
1013 | lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM); | |
1014 | return frame_unwind_got_constant (this_frame, prev_regnum, lr); | |
1015 | } | |
1016 | ||
1017 | /* SP is generally not saved to the stack, but this frame is | |
1018 | identified by the next frame's stack pointer at the time of the | |
1019 | call. The value was already reconstructed into PREV_SP. */ | |
1020 | /* | |
1021 | +----------+ ^ | |
1022 | | saved lr | | | |
1023 | +->| saved fp |--+ | |
1024 | | | | | |
1025 | | | | <- Previous SP | |
1026 | | +----------+ | |
1027 | | | saved lr | | |
1028 | +--| saved fp |<- FP | |
1029 | | | | |
1030 | | |<- SP | |
1031 | +----------+ */ | |
1032 | if (prev_regnum == AARCH64_SP_REGNUM) | |
1033 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
1034 | cache->prev_sp); | |
1035 | ||
1036 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, | |
1037 | prev_regnum); | |
1038 | } | |
1039 | ||
1040 | /* AArch64 prologue unwinder. */ | |
1041 | struct frame_unwind aarch64_prologue_unwind = | |
1042 | { | |
1043 | NORMAL_FRAME, | |
1044 | default_frame_unwind_stop_reason, | |
1045 | aarch64_prologue_this_id, | |
1046 | aarch64_prologue_prev_register, | |
1047 | NULL, | |
1048 | default_frame_sniffer | |
1049 | }; | |
1050 | ||
1051 | /* Allocate an aarch64_prologue_cache and fill it with information | |
1052 | about the prologue of *THIS_FRAME. */ | |
1053 | ||
1054 | static struct aarch64_prologue_cache * | |
1055 | aarch64_make_stub_cache (struct frame_info *this_frame) | |
1056 | { | |
1057 | int reg; | |
1058 | struct aarch64_prologue_cache *cache; | |
1059 | CORE_ADDR unwound_fp; | |
1060 | ||
1061 | cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache); | |
1062 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
1063 | ||
1064 | cache->prev_sp | |
1065 | = get_frame_register_unsigned (this_frame, AARCH64_SP_REGNUM); | |
1066 | ||
1067 | return cache; | |
1068 | } | |
1069 | ||
1070 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
1071 | ||
1072 | static void | |
1073 | aarch64_stub_this_id (struct frame_info *this_frame, | |
1074 | void **this_cache, struct frame_id *this_id) | |
1075 | { | |
1076 | struct aarch64_prologue_cache *cache; | |
1077 | ||
1078 | if (*this_cache == NULL) | |
1079 | *this_cache = aarch64_make_stub_cache (this_frame); | |
1080 | cache = *this_cache; | |
1081 | ||
1082 | *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame)); | |
1083 | } | |
1084 | ||
1085 | /* Implement the "sniffer" frame_unwind method. */ | |
1086 | ||
1087 | static int | |
1088 | aarch64_stub_unwind_sniffer (const struct frame_unwind *self, | |
1089 | struct frame_info *this_frame, | |
1090 | void **this_prologue_cache) | |
1091 | { | |
1092 | CORE_ADDR addr_in_block; | |
1093 | gdb_byte dummy[4]; | |
1094 | ||
1095 | addr_in_block = get_frame_address_in_block (this_frame); | |
1096 | if (in_plt_section (addr_in_block, NULL) | |
1097 | /* We also use the stub winder if the target memory is unreadable | |
1098 | to avoid having the prologue unwinder trying to read it. */ | |
1099 | || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) | |
1100 | return 1; | |
1101 | ||
1102 | return 0; | |
1103 | } | |
1104 | ||
1105 | /* AArch64 stub unwinder. */ | |
1106 | struct frame_unwind aarch64_stub_unwind = | |
1107 | { | |
1108 | NORMAL_FRAME, | |
1109 | default_frame_unwind_stop_reason, | |
1110 | aarch64_stub_this_id, | |
1111 | aarch64_prologue_prev_register, | |
1112 | NULL, | |
1113 | aarch64_stub_unwind_sniffer | |
1114 | }; | |
1115 | ||
1116 | /* Return the frame base address of *THIS_FRAME. */ | |
1117 | ||
1118 | static CORE_ADDR | |
1119 | aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache) | |
1120 | { | |
1121 | struct aarch64_prologue_cache *cache; | |
1122 | ||
1123 | if (*this_cache == NULL) | |
1124 | *this_cache = aarch64_make_prologue_cache (this_frame); | |
1125 | cache = *this_cache; | |
1126 | ||
1127 | return cache->prev_sp - cache->framesize; | |
1128 | } | |
1129 | ||
1130 | /* AArch64 default frame base information. */ | |
1131 | struct frame_base aarch64_normal_base = | |
1132 | { | |
1133 | &aarch64_prologue_unwind, | |
1134 | aarch64_normal_frame_base, | |
1135 | aarch64_normal_frame_base, | |
1136 | aarch64_normal_frame_base | |
1137 | }; | |
1138 | ||
1139 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that | |
1140 | dummy frame. The frame ID's base needs to match the TOS value | |
1141 | saved by save_dummy_frame_tos () and returned from | |
1142 | aarch64_push_dummy_call, and the PC needs to match the dummy | |
1143 | frame's breakpoint. */ | |
1144 | ||
1145 | static struct frame_id | |
1146 | aarch64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1147 | { | |
1148 | return frame_id_build (get_frame_register_unsigned (this_frame, | |
1149 | AARCH64_SP_REGNUM), | |
1150 | get_frame_pc (this_frame)); | |
1151 | } | |
1152 | ||
1153 | /* Implement the "unwind_pc" gdbarch method. */ | |
1154 | ||
1155 | static CORE_ADDR | |
1156 | aarch64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1157 | { | |
1158 | CORE_ADDR pc | |
1159 | = frame_unwind_register_unsigned (this_frame, AARCH64_PC_REGNUM); | |
1160 | ||
1161 | return pc; | |
1162 | } | |
1163 | ||
1164 | /* Implement the "unwind_sp" gdbarch method. */ | |
1165 | ||
1166 | static CORE_ADDR | |
1167 | aarch64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1168 | { | |
1169 | return frame_unwind_register_unsigned (this_frame, AARCH64_SP_REGNUM); | |
1170 | } | |
1171 | ||
1172 | /* Return the value of the REGNUM register in the previous frame of | |
1173 | *THIS_FRAME. */ | |
1174 | ||
1175 | static struct value * | |
1176 | aarch64_dwarf2_prev_register (struct frame_info *this_frame, | |
1177 | void **this_cache, int regnum) | |
1178 | { | |
1179 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1180 | CORE_ADDR lr; | |
1181 | ||
1182 | switch (regnum) | |
1183 | { | |
1184 | case AARCH64_PC_REGNUM: | |
1185 | lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM); | |
1186 | return frame_unwind_got_constant (this_frame, regnum, lr); | |
1187 | ||
1188 | default: | |
1189 | internal_error (__FILE__, __LINE__, | |
1190 | _("Unexpected register %d"), regnum); | |
1191 | } | |
1192 | } | |
1193 | ||
1194 | /* Implement the "init_reg" dwarf2_frame_ops method. */ | |
1195 | ||
1196 | static void | |
1197 | aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
1198 | struct dwarf2_frame_state_reg *reg, | |
1199 | struct frame_info *this_frame) | |
1200 | { | |
1201 | switch (regnum) | |
1202 | { | |
1203 | case AARCH64_PC_REGNUM: | |
1204 | reg->how = DWARF2_FRAME_REG_FN; | |
1205 | reg->loc.fn = aarch64_dwarf2_prev_register; | |
1206 | break; | |
1207 | case AARCH64_SP_REGNUM: | |
1208 | reg->how = DWARF2_FRAME_REG_CFA; | |
1209 | break; | |
1210 | } | |
1211 | } | |
1212 | ||
1213 | /* When arguments must be pushed onto the stack, they go on in reverse | |
1214 | order. The code below implements a FILO (stack) to do this. */ | |
1215 | ||
1216 | typedef struct | |
1217 | { | |
1218 | /* Value to pass on stack. */ | |
1219 | const void *data; | |
1220 | ||
1221 | /* Size in bytes of value to pass on stack. */ | |
1222 | int len; | |
1223 | } stack_item_t; | |
1224 | ||
1225 | DEF_VEC_O (stack_item_t); | |
1226 | ||
1227 | /* Return the alignment (in bytes) of the given type. */ | |
1228 | ||
1229 | static int | |
1230 | aarch64_type_align (struct type *t) | |
1231 | { | |
1232 | int n; | |
1233 | int align; | |
1234 | int falign; | |
1235 | ||
1236 | t = check_typedef (t); | |
1237 | switch (TYPE_CODE (t)) | |
1238 | { | |
1239 | default: | |
1240 | /* Should never happen. */ | |
1241 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); | |
1242 | return 4; | |
1243 | ||
1244 | case TYPE_CODE_PTR: | |
1245 | case TYPE_CODE_ENUM: | |
1246 | case TYPE_CODE_INT: | |
1247 | case TYPE_CODE_FLT: | |
1248 | case TYPE_CODE_SET: | |
1249 | case TYPE_CODE_RANGE: | |
1250 | case TYPE_CODE_BITSTRING: | |
1251 | case TYPE_CODE_REF: | |
1252 | case TYPE_CODE_CHAR: | |
1253 | case TYPE_CODE_BOOL: | |
1254 | return TYPE_LENGTH (t); | |
1255 | ||
1256 | case TYPE_CODE_ARRAY: | |
1257 | case TYPE_CODE_COMPLEX: | |
1258 | return aarch64_type_align (TYPE_TARGET_TYPE (t)); | |
1259 | ||
1260 | case TYPE_CODE_STRUCT: | |
1261 | case TYPE_CODE_UNION: | |
1262 | align = 1; | |
1263 | for (n = 0; n < TYPE_NFIELDS (t); n++) | |
1264 | { | |
1265 | falign = aarch64_type_align (TYPE_FIELD_TYPE (t, n)); | |
1266 | if (falign > align) | |
1267 | align = falign; | |
1268 | } | |
1269 | return align; | |
1270 | } | |
1271 | } | |
1272 | ||
1273 | /* Return 1 if *TY is a homogeneous floating-point aggregate as | |
1274 | defined in the AAPCS64 ABI document; otherwise return 0. */ | |
1275 | ||
1276 | static int | |
1277 | is_hfa (struct type *ty) | |
1278 | { | |
1279 | switch (TYPE_CODE (ty)) | |
1280 | { | |
1281 | case TYPE_CODE_ARRAY: | |
1282 | { | |
1283 | struct type *target_ty = TYPE_TARGET_TYPE (ty); | |
1284 | if (TYPE_CODE (target_ty) == TYPE_CODE_FLT && TYPE_LENGTH (ty) <= 4) | |
1285 | return 1; | |
1286 | break; | |
1287 | } | |
1288 | ||
1289 | case TYPE_CODE_UNION: | |
1290 | case TYPE_CODE_STRUCT: | |
1291 | { | |
1292 | if (TYPE_NFIELDS (ty) > 0 && TYPE_NFIELDS (ty) <= 4) | |
1293 | { | |
1294 | struct type *member0_type; | |
1295 | ||
1296 | member0_type = check_typedef (TYPE_FIELD_TYPE (ty, 0)); | |
1297 | if (TYPE_CODE (member0_type) == TYPE_CODE_FLT) | |
1298 | { | |
1299 | int i; | |
1300 | ||
1301 | for (i = 0; i < TYPE_NFIELDS (ty); i++) | |
1302 | { | |
1303 | struct type *member1_type; | |
1304 | ||
1305 | member1_type = check_typedef (TYPE_FIELD_TYPE (ty, i)); | |
1306 | if (TYPE_CODE (member0_type) != TYPE_CODE (member1_type) | |
1307 | || (TYPE_LENGTH (member0_type) | |
1308 | != TYPE_LENGTH (member1_type))) | |
1309 | return 0; | |
1310 | } | |
1311 | return 1; | |
1312 | } | |
1313 | } | |
1314 | return 0; | |
1315 | } | |
1316 | ||
1317 | default: | |
1318 | break; | |
1319 | } | |
1320 | ||
1321 | return 0; | |
1322 | } | |
1323 | ||
1324 | /* AArch64 function call information structure. */ | |
1325 | struct aarch64_call_info | |
1326 | { | |
1327 | /* the current argument number. */ | |
1328 | unsigned argnum; | |
1329 | ||
1330 | /* The next general purpose register number, equivalent to NGRN as | |
1331 | described in the AArch64 Procedure Call Standard. */ | |
1332 | unsigned ngrn; | |
1333 | ||
1334 | /* The next SIMD and floating point register number, equivalent to | |
1335 | NSRN as described in the AArch64 Procedure Call Standard. */ | |
1336 | unsigned nsrn; | |
1337 | ||
1338 | /* The next stacked argument address, equivalent to NSAA as | |
1339 | described in the AArch64 Procedure Call Standard. */ | |
1340 | unsigned nsaa; | |
1341 | ||
1342 | /* Stack item vector. */ | |
1343 | VEC(stack_item_t) *si; | |
1344 | }; | |
1345 | ||
1346 | /* Pass a value in a sequence of consecutive X registers. The caller | |
1347 | is responsbile for ensuring sufficient registers are available. */ | |
1348 | ||
1349 | static void | |
1350 | pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache, | |
1351 | struct aarch64_call_info *info, struct type *type, | |
1352 | const bfd_byte *buf) | |
1353 | { | |
1354 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1355 | int len = TYPE_LENGTH (type); | |
1356 | enum type_code typecode = TYPE_CODE (type); | |
1357 | int regnum = AARCH64_X0_REGNUM + info->ngrn; | |
1358 | ||
1359 | info->argnum++; | |
1360 | ||
1361 | while (len > 0) | |
1362 | { | |
1363 | int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE; | |
1364 | CORE_ADDR regval = extract_unsigned_integer (buf, partial_len, | |
1365 | byte_order); | |
1366 | ||
1367 | ||
1368 | /* Adjust sub-word struct/union args when big-endian. */ | |
1369 | if (byte_order == BFD_ENDIAN_BIG | |
1370 | && partial_len < X_REGISTER_SIZE | |
1371 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
1372 | regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT); | |
1373 | ||
1374 | if (aarch64_debug) | |
1375 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
1376 | info->argnum, | |
1377 | gdbarch_register_name (gdbarch, regnum), | |
1378 | phex (regval, X_REGISTER_SIZE)); | |
1379 | regcache_cooked_write_unsigned (regcache, regnum, regval); | |
1380 | len -= partial_len; | |
1381 | buf += partial_len; | |
1382 | regnum++; | |
1383 | } | |
1384 | } | |
1385 | ||
1386 | /* Attempt to marshall a value in a V register. Return 1 if | |
1387 | successful, or 0 if insufficient registers are available. This | |
1388 | function, unlike the equivalent pass_in_x() function does not | |
1389 | handle arguments spread across multiple registers. */ | |
1390 | ||
1391 | static int | |
1392 | pass_in_v (struct gdbarch *gdbarch, | |
1393 | struct regcache *regcache, | |
1394 | struct aarch64_call_info *info, | |
1395 | const bfd_byte *buf) | |
1396 | { | |
1397 | if (info->nsrn < 8) | |
1398 | { | |
1399 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1400 | int regnum = AARCH64_V0_REGNUM + info->nsrn; | |
1401 | ||
1402 | info->argnum++; | |
1403 | info->nsrn++; | |
1404 | ||
1405 | regcache_cooked_write (regcache, regnum, buf); | |
1406 | if (aarch64_debug) | |
1407 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s\n", | |
1408 | info->argnum, | |
1409 | gdbarch_register_name (gdbarch, regnum)); | |
1410 | return 1; | |
1411 | } | |
1412 | info->nsrn = 8; | |
1413 | return 0; | |
1414 | } | |
1415 | ||
1416 | /* Marshall an argument onto the stack. */ | |
1417 | ||
1418 | static void | |
1419 | pass_on_stack (struct aarch64_call_info *info, struct type *type, | |
1420 | const bfd_byte *buf) | |
1421 | { | |
1422 | int len = TYPE_LENGTH (type); | |
1423 | int align; | |
1424 | stack_item_t item; | |
1425 | ||
1426 | info->argnum++; | |
1427 | ||
1428 | align = aarch64_type_align (type); | |
1429 | ||
1430 | /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the | |
1431 | Natural alignment of the argument's type. */ | |
1432 | align = align_up (align, 8); | |
1433 | ||
1434 | /* The AArch64 PCS requires at most doubleword alignment. */ | |
1435 | if (align > 16) | |
1436 | align = 16; | |
1437 | ||
1438 | if (aarch64_debug) | |
1439 | fprintf_unfiltered (gdb_stdlog, "arg %d len=%d @ sp + %d\n", | |
1440 | info->argnum, len, info->nsaa); | |
1441 | ||
1442 | item.len = len; | |
1443 | item.data = buf; | |
1444 | VEC_safe_push (stack_item_t, info->si, &item); | |
1445 | ||
1446 | info->nsaa += len; | |
1447 | if (info->nsaa & (align - 1)) | |
1448 | { | |
1449 | /* Push stack alignment padding. */ | |
1450 | int pad = align - (info->nsaa & (align - 1)); | |
1451 | ||
1452 | item.len = pad; | |
1453 | item.data = buf; | |
1454 | ||
1455 | VEC_safe_push (stack_item_t, info->si, &item); | |
1456 | info->nsaa += pad; | |
1457 | } | |
1458 | } | |
1459 | ||
1460 | /* Marshall an argument into a sequence of one or more consecutive X | |
1461 | registers or, if insufficient X registers are available then onto | |
1462 | the stack. */ | |
1463 | ||
1464 | static void | |
1465 | pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache, | |
1466 | struct aarch64_call_info *info, struct type *type, | |
1467 | const bfd_byte *buf) | |
1468 | { | |
1469 | int len = TYPE_LENGTH (type); | |
1470 | int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE; | |
1471 | ||
1472 | /* PCS C.13 - Pass in registers if we have enough spare */ | |
1473 | if (info->ngrn + nregs <= 8) | |
1474 | { | |
1475 | pass_in_x (gdbarch, regcache, info, type, buf); | |
1476 | info->ngrn += nregs; | |
1477 | } | |
1478 | else | |
1479 | { | |
1480 | info->ngrn = 8; | |
1481 | pass_on_stack (info, type, buf); | |
1482 | } | |
1483 | } | |
1484 | ||
1485 | /* Pass a value in a V register, or on the stack if insufficient are | |
1486 | available. */ | |
1487 | ||
1488 | static void | |
1489 | pass_in_v_or_stack (struct gdbarch *gdbarch, | |
1490 | struct regcache *regcache, | |
1491 | struct aarch64_call_info *info, | |
1492 | struct type *type, | |
1493 | const bfd_byte *buf) | |
1494 | { | |
1495 | if (!pass_in_v (gdbarch, regcache, info, buf)) | |
1496 | pass_on_stack (info, type, buf); | |
1497 | } | |
1498 | ||
1499 | /* Implement the "push_dummy_call" gdbarch method. */ | |
1500 | ||
1501 | static CORE_ADDR | |
1502 | aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
1503 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1504 | int nargs, | |
1505 | struct value **args, CORE_ADDR sp, int struct_return, | |
1506 | CORE_ADDR struct_addr) | |
1507 | { | |
1508 | int nstack = 0; | |
1509 | int argnum; | |
1510 | int x_argreg; | |
1511 | int v_argreg; | |
1512 | struct aarch64_call_info info; | |
1513 | struct type *func_type; | |
1514 | struct type *return_type; | |
1515 | int lang_struct_return; | |
1516 | ||
1517 | memset (&info, 0, sizeof (info)); | |
1518 | ||
1519 | /* We need to know what the type of the called function is in order | |
1520 | to determine the number of named/anonymous arguments for the | |
1521 | actual argument placement, and the return type in order to handle | |
1522 | return value correctly. | |
1523 | ||
1524 | The generic code above us views the decision of return in memory | |
1525 | or return in registers as a two stage processes. The language | |
1526 | handler is consulted first and may decide to return in memory (eg | |
1527 | class with copy constructor returned by value), this will cause | |
1528 | the generic code to allocate space AND insert an initial leading | |
1529 | argument. | |
1530 | ||
1531 | If the language code does not decide to pass in memory then the | |
1532 | target code is consulted. | |
1533 | ||
1534 | If the language code decides to pass in memory we want to move | |
1535 | the pointer inserted as the initial argument from the argument | |
1536 | list and into X8, the conventional AArch64 struct return pointer | |
1537 | register. | |
1538 | ||
1539 | This is slightly awkward, ideally the flag "lang_struct_return" | |
1540 | would be passed to the targets implementation of push_dummy_call. | |
1541 | Rather that change the target interface we call the language code | |
1542 | directly ourselves. */ | |
1543 | ||
1544 | func_type = check_typedef (value_type (function)); | |
1545 | ||
1546 | /* Dereference function pointer types. */ | |
1547 | if (TYPE_CODE (func_type) == TYPE_CODE_PTR) | |
1548 | func_type = TYPE_TARGET_TYPE (func_type); | |
1549 | ||
1550 | gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC | |
1551 | || TYPE_CODE (func_type) == TYPE_CODE_METHOD); | |
1552 | ||
1553 | /* If language_pass_by_reference () returned true we will have been | |
1554 | given an additional initial argument, a hidden pointer to the | |
1555 | return slot in memory. */ | |
1556 | return_type = TYPE_TARGET_TYPE (func_type); | |
1557 | lang_struct_return = language_pass_by_reference (return_type); | |
1558 | ||
1559 | /* Set the return address. For the AArch64, the return breakpoint | |
1560 | is always at BP_ADDR. */ | |
1561 | regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr); | |
1562 | ||
1563 | /* If we were given an initial argument for the return slot because | |
1564 | lang_struct_return was true, lose it. */ | |
1565 | if (lang_struct_return) | |
1566 | { | |
1567 | args++; | |
1568 | nargs--; | |
1569 | } | |
1570 | ||
1571 | /* The struct_return pointer occupies X8. */ | |
1572 | if (struct_return || lang_struct_return) | |
1573 | { | |
1574 | if (aarch64_debug) | |
1575 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n", | |
1576 | gdbarch_register_name | |
1577 | (gdbarch, | |
1578 | AARCH64_STRUCT_RETURN_REGNUM), | |
1579 | paddress (gdbarch, struct_addr)); | |
1580 | regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM, | |
1581 | struct_addr); | |
1582 | } | |
1583 | ||
1584 | for (argnum = 0; argnum < nargs; argnum++) | |
1585 | { | |
1586 | struct value *arg = args[argnum]; | |
1587 | struct type *arg_type; | |
1588 | int len; | |
1589 | ||
1590 | arg_type = check_typedef (value_type (arg)); | |
1591 | len = TYPE_LENGTH (arg_type); | |
1592 | ||
1593 | switch (TYPE_CODE (arg_type)) | |
1594 | { | |
1595 | case TYPE_CODE_INT: | |
1596 | case TYPE_CODE_BOOL: | |
1597 | case TYPE_CODE_CHAR: | |
1598 | case TYPE_CODE_RANGE: | |
1599 | case TYPE_CODE_ENUM: | |
1600 | if (len < 4) | |
1601 | { | |
1602 | /* Promote to 32 bit integer. */ | |
1603 | if (TYPE_UNSIGNED (arg_type)) | |
1604 | arg_type = builtin_type (gdbarch)->builtin_uint32; | |
1605 | else | |
1606 | arg_type = builtin_type (gdbarch)->builtin_int32; | |
1607 | arg = value_cast (arg_type, arg); | |
1608 | } | |
1609 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, | |
1610 | value_contents (arg)); | |
1611 | break; | |
1612 | ||
1613 | case TYPE_CODE_COMPLEX: | |
1614 | if (info.nsrn <= 6) | |
1615 | { | |
1616 | const bfd_byte *buf = value_contents (arg); | |
1617 | struct type *target_type = | |
1618 | check_typedef (TYPE_TARGET_TYPE (arg_type)); | |
1619 | ||
1620 | pass_in_v (gdbarch, regcache, &info, buf); | |
1621 | pass_in_v (gdbarch, regcache, &info, | |
1622 | buf + TYPE_LENGTH (target_type)); | |
1623 | } | |
1624 | else | |
1625 | { | |
1626 | info.nsrn = 8; | |
1627 | pass_on_stack (&info, arg_type, value_contents (arg)); | |
1628 | } | |
1629 | break; | |
1630 | case TYPE_CODE_FLT: | |
1631 | pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, | |
1632 | value_contents (arg)); | |
1633 | break; | |
1634 | ||
1635 | case TYPE_CODE_STRUCT: | |
1636 | case TYPE_CODE_ARRAY: | |
1637 | case TYPE_CODE_UNION: | |
1638 | if (is_hfa (arg_type)) | |
1639 | { | |
1640 | int elements = TYPE_NFIELDS (arg_type); | |
1641 | ||
1642 | /* Homogeneous Aggregates */ | |
1643 | if (info.nsrn + elements < 8) | |
1644 | { | |
1645 | int i; | |
1646 | ||
1647 | for (i = 0; i < elements; i++) | |
1648 | { | |
1649 | /* We know that we have sufficient registers | |
1650 | available therefore this will never fallback | |
1651 | to the stack. */ | |
1652 | struct value *field = | |
1653 | value_primitive_field (arg, 0, i, arg_type); | |
1654 | struct type *field_type = | |
1655 | check_typedef (value_type (field)); | |
1656 | ||
1657 | pass_in_v_or_stack (gdbarch, regcache, &info, field_type, | |
1658 | value_contents_writeable (field)); | |
1659 | } | |
1660 | } | |
1661 | else | |
1662 | { | |
1663 | info.nsrn = 8; | |
1664 | pass_on_stack (&info, arg_type, value_contents (arg)); | |
1665 | } | |
1666 | } | |
1667 | else if (len > 16) | |
1668 | { | |
1669 | /* PCS B.7 Aggregates larger than 16 bytes are passed by | |
1670 | invisible reference. */ | |
1671 | ||
1672 | /* Allocate aligned storage. */ | |
1673 | sp = align_down (sp - len, 16); | |
1674 | ||
1675 | /* Write the real data into the stack. */ | |
1676 | write_memory (sp, value_contents (arg), len); | |
1677 | ||
1678 | /* Construct the indirection. */ | |
1679 | arg_type = lookup_pointer_type (arg_type); | |
1680 | arg = value_from_pointer (arg_type, sp); | |
1681 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, | |
1682 | value_contents (arg)); | |
1683 | } | |
1684 | else | |
1685 | /* PCS C.15 / C.18 multiple values pass. */ | |
1686 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, | |
1687 | value_contents (arg)); | |
1688 | break; | |
1689 | ||
1690 | default: | |
1691 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, | |
1692 | value_contents (arg)); | |
1693 | break; | |
1694 | } | |
1695 | } | |
1696 | ||
1697 | /* Make sure stack retains 16 byte alignment. */ | |
1698 | if (info.nsaa & 15) | |
1699 | sp -= 16 - (info.nsaa & 15); | |
1700 | ||
1701 | while (!VEC_empty (stack_item_t, info.si)) | |
1702 | { | |
1703 | stack_item_t *si = VEC_last (stack_item_t, info.si); | |
1704 | ||
1705 | sp -= si->len; | |
1706 | write_memory (sp, si->data, si->len); | |
1707 | VEC_pop (stack_item_t, info.si); | |
1708 | } | |
1709 | ||
1710 | VEC_free (stack_item_t, info.si); | |
1711 | ||
1712 | /* Finally, update the SP register. */ | |
1713 | regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp); | |
1714 | ||
1715 | return sp; | |
1716 | } | |
1717 | ||
1718 | /* Implement the "frame_align" gdbarch method. */ | |
1719 | ||
1720 | static CORE_ADDR | |
1721 | aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
1722 | { | |
1723 | /* Align the stack to sixteen bytes. */ | |
1724 | return sp & ~(CORE_ADDR) 15; | |
1725 | } | |
1726 | ||
1727 | /* Return the type for an AdvSISD Q register. */ | |
1728 | ||
1729 | static struct type * | |
1730 | aarch64_vnq_type (struct gdbarch *gdbarch) | |
1731 | { | |
1732 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1733 | ||
1734 | if (tdep->vnq_type == NULL) | |
1735 | { | |
1736 | struct type *t; | |
1737 | struct type *elem; | |
1738 | ||
1739 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq", | |
1740 | TYPE_CODE_UNION); | |
1741 | ||
1742 | elem = builtin_type (gdbarch)->builtin_uint128; | |
1743 | append_composite_type_field (t, "u", elem); | |
1744 | ||
1745 | elem = builtin_type (gdbarch)->builtin_int128; | |
1746 | append_composite_type_field (t, "s", elem); | |
1747 | ||
1748 | tdep->vnq_type = t; | |
1749 | } | |
1750 | ||
1751 | return tdep->vnq_type; | |
1752 | } | |
1753 | ||
1754 | /* Return the type for an AdvSISD D register. */ | |
1755 | ||
1756 | static struct type * | |
1757 | aarch64_vnd_type (struct gdbarch *gdbarch) | |
1758 | { | |
1759 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1760 | ||
1761 | if (tdep->vnd_type == NULL) | |
1762 | { | |
1763 | struct type *t; | |
1764 | struct type *elem; | |
1765 | ||
1766 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd", | |
1767 | TYPE_CODE_UNION); | |
1768 | ||
1769 | elem = builtin_type (gdbarch)->builtin_double; | |
1770 | append_composite_type_field (t, "f", elem); | |
1771 | ||
1772 | elem = builtin_type (gdbarch)->builtin_uint64; | |
1773 | append_composite_type_field (t, "u", elem); | |
1774 | ||
1775 | elem = builtin_type (gdbarch)->builtin_int64; | |
1776 | append_composite_type_field (t, "s", elem); | |
1777 | ||
1778 | tdep->vnd_type = t; | |
1779 | } | |
1780 | ||
1781 | return tdep->vnd_type; | |
1782 | } | |
1783 | ||
1784 | /* Return the type for an AdvSISD S register. */ | |
1785 | ||
1786 | static struct type * | |
1787 | aarch64_vns_type (struct gdbarch *gdbarch) | |
1788 | { | |
1789 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1790 | ||
1791 | if (tdep->vns_type == NULL) | |
1792 | { | |
1793 | struct type *t; | |
1794 | struct type *elem; | |
1795 | ||
1796 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns", | |
1797 | TYPE_CODE_UNION); | |
1798 | ||
1799 | elem = builtin_type (gdbarch)->builtin_float; | |
1800 | append_composite_type_field (t, "f", elem); | |
1801 | ||
1802 | elem = builtin_type (gdbarch)->builtin_uint32; | |
1803 | append_composite_type_field (t, "u", elem); | |
1804 | ||
1805 | elem = builtin_type (gdbarch)->builtin_int32; | |
1806 | append_composite_type_field (t, "s", elem); | |
1807 | ||
1808 | tdep->vns_type = t; | |
1809 | } | |
1810 | ||
1811 | return tdep->vns_type; | |
1812 | } | |
1813 | ||
1814 | /* Return the type for an AdvSISD H register. */ | |
1815 | ||
1816 | static struct type * | |
1817 | aarch64_vnh_type (struct gdbarch *gdbarch) | |
1818 | { | |
1819 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1820 | ||
1821 | if (tdep->vnh_type == NULL) | |
1822 | { | |
1823 | struct type *t; | |
1824 | struct type *elem; | |
1825 | ||
1826 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh", | |
1827 | TYPE_CODE_UNION); | |
1828 | ||
1829 | elem = builtin_type (gdbarch)->builtin_uint16; | |
1830 | append_composite_type_field (t, "u", elem); | |
1831 | ||
1832 | elem = builtin_type (gdbarch)->builtin_int16; | |
1833 | append_composite_type_field (t, "s", elem); | |
1834 | ||
1835 | tdep->vnh_type = t; | |
1836 | } | |
1837 | ||
1838 | return tdep->vnh_type; | |
1839 | } | |
1840 | ||
1841 | /* Return the type for an AdvSISD B register. */ | |
1842 | ||
1843 | static struct type * | |
1844 | aarch64_vnb_type (struct gdbarch *gdbarch) | |
1845 | { | |
1846 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1847 | ||
1848 | if (tdep->vnb_type == NULL) | |
1849 | { | |
1850 | struct type *t; | |
1851 | struct type *elem; | |
1852 | ||
1853 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb", | |
1854 | TYPE_CODE_UNION); | |
1855 | ||
1856 | elem = builtin_type (gdbarch)->builtin_uint8; | |
1857 | append_composite_type_field (t, "u", elem); | |
1858 | ||
1859 | elem = builtin_type (gdbarch)->builtin_int8; | |
1860 | append_composite_type_field (t, "s", elem); | |
1861 | ||
1862 | tdep->vnb_type = t; | |
1863 | } | |
1864 | ||
1865 | return tdep->vnb_type; | |
1866 | } | |
1867 | ||
1868 | /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */ | |
1869 | ||
1870 | static int | |
1871 | aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) | |
1872 | { | |
1873 | if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30) | |
1874 | return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0; | |
1875 | ||
1876 | if (reg == AARCH64_DWARF_SP) | |
1877 | return AARCH64_SP_REGNUM; | |
1878 | ||
1879 | if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31) | |
1880 | return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0; | |
1881 | ||
1882 | return -1; | |
1883 | } | |
1884 | \f | |
1885 | ||
1886 | /* Implement the "print_insn" gdbarch method. */ | |
1887 | ||
1888 | static int | |
1889 | aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info) | |
1890 | { | |
1891 | info->symbols = NULL; | |
1892 | return print_insn_aarch64 (memaddr, info); | |
1893 | } | |
1894 | ||
1895 | /* AArch64 BRK software debug mode instruction. | |
1896 | Note that AArch64 code is always little-endian. | |
1897 | 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */ | |
1898 | static const char aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4}; | |
1899 | ||
1900 | /* Implement the "breakpoint_from_pc" gdbarch method. */ | |
1901 | ||
1902 | static const unsigned char * | |
1903 | aarch64_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, | |
1904 | int *lenptr) | |
1905 | { | |
1906 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1907 | ||
1908 | *lenptr = sizeof (aarch64_default_breakpoint); | |
1909 | return aarch64_default_breakpoint; | |
1910 | } | |
1911 | ||
1912 | /* Extract from an array REGS containing the (raw) register state a | |
1913 | function return value of type TYPE, and copy that, in virtual | |
1914 | format, into VALBUF. */ | |
1915 | ||
1916 | static void | |
1917 | aarch64_extract_return_value (struct type *type, struct regcache *regs, | |
1918 | gdb_byte *valbuf) | |
1919 | { | |
1920 | struct gdbarch *gdbarch = get_regcache_arch (regs); | |
1921 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1922 | ||
1923 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1924 | { | |
1925 | bfd_byte buf[V_REGISTER_SIZE]; | |
1926 | int len = TYPE_LENGTH (type); | |
1927 | ||
1928 | regcache_cooked_read (regs, AARCH64_V0_REGNUM, buf); | |
1929 | memcpy (valbuf, buf, len); | |
1930 | } | |
1931 | else if (TYPE_CODE (type) == TYPE_CODE_INT | |
1932 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
1933 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
1934 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
1935 | || TYPE_CODE (type) == TYPE_CODE_REF | |
1936 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
1937 | { | |
1938 | /* If the the type is a plain integer, then the access is | |
1939 | straight-forward. Otherwise we have to play around a bit | |
1940 | more. */ | |
1941 | int len = TYPE_LENGTH (type); | |
1942 | int regno = AARCH64_X0_REGNUM; | |
1943 | ULONGEST tmp; | |
1944 | ||
1945 | while (len > 0) | |
1946 | { | |
1947 | /* By using store_unsigned_integer we avoid having to do | |
1948 | anything special for small big-endian values. */ | |
1949 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
1950 | store_unsigned_integer (valbuf, | |
1951 | (len > X_REGISTER_SIZE | |
1952 | ? X_REGISTER_SIZE : len), byte_order, tmp); | |
1953 | len -= X_REGISTER_SIZE; | |
1954 | valbuf += X_REGISTER_SIZE; | |
1955 | } | |
1956 | } | |
1957 | else if (TYPE_CODE (type) == TYPE_CODE_COMPLEX) | |
1958 | { | |
1959 | int regno = AARCH64_V0_REGNUM; | |
1960 | bfd_byte buf[V_REGISTER_SIZE]; | |
1961 | struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type)); | |
1962 | int len = TYPE_LENGTH (target_type); | |
1963 | ||
1964 | regcache_cooked_read (regs, regno, buf); | |
1965 | memcpy (valbuf, buf, len); | |
1966 | valbuf += len; | |
1967 | regcache_cooked_read (regs, regno + 1, buf); | |
1968 | memcpy (valbuf, buf, len); | |
1969 | valbuf += len; | |
1970 | } | |
1971 | else if (is_hfa (type)) | |
1972 | { | |
1973 | int elements = TYPE_NFIELDS (type); | |
1974 | struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
1975 | int len = TYPE_LENGTH (member_type); | |
1976 | int i; | |
1977 | ||
1978 | for (i = 0; i < elements; i++) | |
1979 | { | |
1980 | int regno = AARCH64_V0_REGNUM + i; | |
1981 | bfd_byte buf[X_REGISTER_SIZE]; | |
1982 | ||
1983 | if (aarch64_debug) | |
1984 | fprintf_unfiltered (gdb_stdlog, | |
1985 | "read HFA return value element %d from %s\n", | |
1986 | i + 1, | |
1987 | gdbarch_register_name (gdbarch, regno)); | |
1988 | regcache_cooked_read (regs, regno, buf); | |
1989 | ||
1990 | memcpy (valbuf, buf, len); | |
1991 | valbuf += len; | |
1992 | } | |
1993 | } | |
1994 | else | |
1995 | { | |
1996 | /* For a structure or union the behaviour is as if the value had | |
1997 | been stored to word-aligned memory and then loaded into | |
1998 | registers with 64-bit load instruction(s). */ | |
1999 | int len = TYPE_LENGTH (type); | |
2000 | int regno = AARCH64_X0_REGNUM; | |
2001 | bfd_byte buf[X_REGISTER_SIZE]; | |
2002 | ||
2003 | while (len > 0) | |
2004 | { | |
2005 | regcache_cooked_read (regs, regno++, buf); | |
2006 | memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len); | |
2007 | len -= X_REGISTER_SIZE; | |
2008 | valbuf += X_REGISTER_SIZE; | |
2009 | } | |
2010 | } | |
2011 | } | |
2012 | ||
2013 | ||
2014 | /* Will a function return an aggregate type in memory or in a | |
2015 | register? Return 0 if an aggregate type can be returned in a | |
2016 | register, 1 if it must be returned in memory. */ | |
2017 | ||
2018 | static int | |
2019 | aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type) | |
2020 | { | |
2021 | int nRc; | |
2022 | enum type_code code; | |
2023 | ||
2024 | CHECK_TYPEDEF (type); | |
2025 | ||
2026 | /* In the AArch64 ABI, "integer" like aggregate types are returned | |
2027 | in registers. For an aggregate type to be integer like, its size | |
2028 | must be less than or equal to 4 * X_REGISTER_SIZE. */ | |
2029 | ||
2030 | if (is_hfa (type)) | |
2031 | { | |
2032 | /* PCS B.5 If the argument is a Named HFA, then the argument is | |
2033 | used unmodified. */ | |
2034 | return 0; | |
2035 | } | |
2036 | ||
2037 | if (TYPE_LENGTH (type) > 16) | |
2038 | { | |
2039 | /* PCS B.6 Aggregates larger than 16 bytes are passed by | |
2040 | invisible reference. */ | |
2041 | ||
2042 | return 1; | |
2043 | } | |
2044 | ||
2045 | return 0; | |
2046 | } | |
2047 | ||
2048 | /* Write into appropriate registers a function return value of type | |
2049 | TYPE, given in virtual format. */ | |
2050 | ||
2051 | static void | |
2052 | aarch64_store_return_value (struct type *type, struct regcache *regs, | |
2053 | const gdb_byte *valbuf) | |
2054 | { | |
2055 | struct gdbarch *gdbarch = get_regcache_arch (regs); | |
2056 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2057 | ||
2058 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2059 | { | |
2060 | bfd_byte buf[V_REGISTER_SIZE]; | |
2061 | int len = TYPE_LENGTH (type); | |
2062 | ||
2063 | memcpy (buf, valbuf, len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len); | |
2064 | regcache_cooked_write (regs, AARCH64_V0_REGNUM, buf); | |
2065 | } | |
2066 | else if (TYPE_CODE (type) == TYPE_CODE_INT | |
2067 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2068 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2069 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2070 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2071 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2072 | { | |
2073 | if (TYPE_LENGTH (type) <= X_REGISTER_SIZE) | |
2074 | { | |
2075 | /* Values of one word or less are zero/sign-extended and | |
2076 | returned in r0. */ | |
2077 | bfd_byte tmpbuf[X_REGISTER_SIZE]; | |
2078 | LONGEST val = unpack_long (type, valbuf); | |
2079 | ||
2080 | store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val); | |
2081 | regcache_cooked_write (regs, AARCH64_X0_REGNUM, tmpbuf); | |
2082 | } | |
2083 | else | |
2084 | { | |
2085 | /* Integral values greater than one word are stored in | |
2086 | consecutive registers starting with r0. This will always | |
2087 | be a multiple of the regiser size. */ | |
2088 | int len = TYPE_LENGTH (type); | |
2089 | int regno = AARCH64_X0_REGNUM; | |
2090 | ||
2091 | while (len > 0) | |
2092 | { | |
2093 | regcache_cooked_write (regs, regno++, valbuf); | |
2094 | len -= X_REGISTER_SIZE; | |
2095 | valbuf += X_REGISTER_SIZE; | |
2096 | } | |
2097 | } | |
2098 | } | |
2099 | else if (is_hfa (type)) | |
2100 | { | |
2101 | int elements = TYPE_NFIELDS (type); | |
2102 | struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2103 | int len = TYPE_LENGTH (member_type); | |
2104 | int i; | |
2105 | ||
2106 | for (i = 0; i < elements; i++) | |
2107 | { | |
2108 | int regno = AARCH64_V0_REGNUM + i; | |
2109 | bfd_byte tmpbuf[MAX_REGISTER_SIZE]; | |
2110 | ||
2111 | if (aarch64_debug) | |
2112 | fprintf_unfiltered (gdb_stdlog, | |
2113 | "write HFA return value element %d to %s\n", | |
2114 | i + 1, | |
2115 | gdbarch_register_name (gdbarch, regno)); | |
2116 | ||
2117 | memcpy (tmpbuf, valbuf, len); | |
2118 | regcache_cooked_write (regs, regno, tmpbuf); | |
2119 | valbuf += len; | |
2120 | } | |
2121 | } | |
2122 | else | |
2123 | { | |
2124 | /* For a structure or union the behaviour is as if the value had | |
2125 | been stored to word-aligned memory and then loaded into | |
2126 | registers with 64-bit load instruction(s). */ | |
2127 | int len = TYPE_LENGTH (type); | |
2128 | int regno = AARCH64_X0_REGNUM; | |
2129 | bfd_byte tmpbuf[X_REGISTER_SIZE]; | |
2130 | ||
2131 | while (len > 0) | |
2132 | { | |
2133 | memcpy (tmpbuf, valbuf, | |
2134 | len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len); | |
2135 | regcache_cooked_write (regs, regno++, tmpbuf); | |
2136 | len -= X_REGISTER_SIZE; | |
2137 | valbuf += X_REGISTER_SIZE; | |
2138 | } | |
2139 | } | |
2140 | } | |
2141 | ||
2142 | /* Implement the "return_value" gdbarch method. */ | |
2143 | ||
2144 | static enum return_value_convention | |
2145 | aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value, | |
2146 | struct type *valtype, struct regcache *regcache, | |
2147 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
2148 | { | |
2149 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2150 | ||
2151 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
2152 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
2153 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
2154 | { | |
2155 | if (aarch64_return_in_memory (gdbarch, valtype)) | |
2156 | { | |
2157 | if (aarch64_debug) | |
2158 | fprintf_unfiltered (gdb_stdlog, "return value in memory\n"); | |
2159 | return RETURN_VALUE_STRUCT_CONVENTION; | |
2160 | } | |
2161 | } | |
2162 | ||
2163 | if (writebuf) | |
2164 | aarch64_store_return_value (valtype, regcache, writebuf); | |
2165 | ||
2166 | if (readbuf) | |
2167 | aarch64_extract_return_value (valtype, regcache, readbuf); | |
2168 | ||
2169 | if (aarch64_debug) | |
2170 | fprintf_unfiltered (gdb_stdlog, "return value in registers\n"); | |
2171 | ||
2172 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2173 | } | |
2174 | ||
2175 | /* Implement the "get_longjmp_target" gdbarch method. */ | |
2176 | ||
2177 | static int | |
2178 | aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) | |
2179 | { | |
2180 | CORE_ADDR jb_addr; | |
2181 | gdb_byte buf[X_REGISTER_SIZE]; | |
2182 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
2183 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2184 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2185 | ||
2186 | jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM); | |
2187 | ||
2188 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
2189 | X_REGISTER_SIZE)) | |
2190 | return 0; | |
2191 | ||
2192 | *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order); | |
2193 | return 1; | |
2194 | } | |
2195 | \f | |
2196 | ||
2197 | /* Return the pseudo register name corresponding to register regnum. */ | |
2198 | ||
2199 | static const char * | |
2200 | aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) | |
2201 | { | |
2202 | static const char *const q_name[] = | |
2203 | { | |
2204 | "q0", "q1", "q2", "q3", | |
2205 | "q4", "q5", "q6", "q7", | |
2206 | "q8", "q9", "q10", "q11", | |
2207 | "q12", "q13", "q14", "q15", | |
2208 | "q16", "q17", "q18", "q19", | |
2209 | "q20", "q21", "q22", "q23", | |
2210 | "q24", "q25", "q26", "q27", | |
2211 | "q28", "q29", "q30", "q31", | |
2212 | }; | |
2213 | ||
2214 | static const char *const d_name[] = | |
2215 | { | |
2216 | "d0", "d1", "d2", "d3", | |
2217 | "d4", "d5", "d6", "d7", | |
2218 | "d8", "d9", "d10", "d11", | |
2219 | "d12", "d13", "d14", "d15", | |
2220 | "d16", "d17", "d18", "d19", | |
2221 | "d20", "d21", "d22", "d23", | |
2222 | "d24", "d25", "d26", "d27", | |
2223 | "d28", "d29", "d30", "d31", | |
2224 | }; | |
2225 | ||
2226 | static const char *const s_name[] = | |
2227 | { | |
2228 | "s0", "s1", "s2", "s3", | |
2229 | "s4", "s5", "s6", "s7", | |
2230 | "s8", "s9", "s10", "s11", | |
2231 | "s12", "s13", "s14", "s15", | |
2232 | "s16", "s17", "s18", "s19", | |
2233 | "s20", "s21", "s22", "s23", | |
2234 | "s24", "s25", "s26", "s27", | |
2235 | "s28", "s29", "s30", "s31", | |
2236 | }; | |
2237 | ||
2238 | static const char *const h_name[] = | |
2239 | { | |
2240 | "h0", "h1", "h2", "h3", | |
2241 | "h4", "h5", "h6", "h7", | |
2242 | "h8", "h9", "h10", "h11", | |
2243 | "h12", "h13", "h14", "h15", | |
2244 | "h16", "h17", "h18", "h19", | |
2245 | "h20", "h21", "h22", "h23", | |
2246 | "h24", "h25", "h26", "h27", | |
2247 | "h28", "h29", "h30", "h31", | |
2248 | }; | |
2249 | ||
2250 | static const char *const b_name[] = | |
2251 | { | |
2252 | "b0", "b1", "b2", "b3", | |
2253 | "b4", "b5", "b6", "b7", | |
2254 | "b8", "b9", "b10", "b11", | |
2255 | "b12", "b13", "b14", "b15", | |
2256 | "b16", "b17", "b18", "b19", | |
2257 | "b20", "b21", "b22", "b23", | |
2258 | "b24", "b25", "b26", "b27", | |
2259 | "b28", "b29", "b30", "b31", | |
2260 | }; | |
2261 | ||
2262 | regnum -= gdbarch_num_regs (gdbarch); | |
2263 | ||
2264 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2265 | return q_name[regnum - AARCH64_Q0_REGNUM]; | |
2266 | ||
2267 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2268 | return d_name[regnum - AARCH64_D0_REGNUM]; | |
2269 | ||
2270 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2271 | return s_name[regnum - AARCH64_S0_REGNUM]; | |
2272 | ||
2273 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2274 | return h_name[regnum - AARCH64_H0_REGNUM]; | |
2275 | ||
2276 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2277 | return b_name[regnum - AARCH64_B0_REGNUM]; | |
2278 | ||
2279 | internal_error (__FILE__, __LINE__, | |
2280 | _("aarch64_pseudo_register_name: bad register number %d"), | |
2281 | regnum); | |
2282 | } | |
2283 | ||
2284 | /* Implement the "pseudo_register_type" tdesc_arch_data method. */ | |
2285 | ||
2286 | static struct type * | |
2287 | aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
2288 | { | |
2289 | regnum -= gdbarch_num_regs (gdbarch); | |
2290 | ||
2291 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2292 | return aarch64_vnq_type (gdbarch); | |
2293 | ||
2294 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2295 | return aarch64_vnd_type (gdbarch); | |
2296 | ||
2297 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2298 | return aarch64_vns_type (gdbarch); | |
2299 | ||
2300 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2301 | return aarch64_vnh_type (gdbarch); | |
2302 | ||
2303 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2304 | return aarch64_vnb_type (gdbarch); | |
2305 | ||
2306 | internal_error (__FILE__, __LINE__, | |
2307 | _("aarch64_pseudo_register_type: bad register number %d"), | |
2308 | regnum); | |
2309 | } | |
2310 | ||
2311 | /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */ | |
2312 | ||
2313 | static int | |
2314 | aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2315 | struct reggroup *group) | |
2316 | { | |
2317 | regnum -= gdbarch_num_regs (gdbarch); | |
2318 | ||
2319 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2320 | return group == all_reggroup || group == vector_reggroup; | |
2321 | else if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2322 | return (group == all_reggroup || group == vector_reggroup | |
2323 | || group == float_reggroup); | |
2324 | else if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2325 | return (group == all_reggroup || group == vector_reggroup | |
2326 | || group == float_reggroup); | |
2327 | else if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2328 | return group == all_reggroup || group == vector_reggroup; | |
2329 | else if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2330 | return group == all_reggroup || group == vector_reggroup; | |
2331 | ||
2332 | return group == all_reggroup; | |
2333 | } | |
2334 | ||
2335 | /* Implement the "pseudo_register_read_value" gdbarch method. */ | |
2336 | ||
2337 | static struct value * | |
2338 | aarch64_pseudo_read_value (struct gdbarch *gdbarch, | |
2339 | struct regcache *regcache, | |
2340 | int regnum) | |
2341 | { | |
2342 | gdb_byte reg_buf[MAX_REGISTER_SIZE]; | |
2343 | struct value *result_value; | |
2344 | gdb_byte *buf; | |
2345 | ||
2346 | result_value = allocate_value (register_type (gdbarch, regnum)); | |
2347 | VALUE_LVAL (result_value) = lval_register; | |
2348 | VALUE_REGNUM (result_value) = regnum; | |
2349 | buf = value_contents_raw (result_value); | |
2350 | ||
2351 | regnum -= gdbarch_num_regs (gdbarch); | |
2352 | ||
2353 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2354 | { | |
2355 | enum register_status status; | |
2356 | unsigned v_regnum; | |
2357 | ||
2358 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM; | |
2359 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
2360 | if (status != REG_VALID) | |
2361 | mark_value_bytes_unavailable (result_value, 0, | |
2362 | TYPE_LENGTH (value_type (result_value))); | |
2363 | else | |
2364 | memcpy (buf, reg_buf, Q_REGISTER_SIZE); | |
2365 | return result_value; | |
2366 | } | |
2367 | ||
2368 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2369 | { | |
2370 | enum register_status status; | |
2371 | unsigned v_regnum; | |
2372 | ||
2373 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM; | |
2374 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
2375 | if (status != REG_VALID) | |
2376 | mark_value_bytes_unavailable (result_value, 0, | |
2377 | TYPE_LENGTH (value_type (result_value))); | |
2378 | else | |
2379 | memcpy (buf, reg_buf, D_REGISTER_SIZE); | |
2380 | return result_value; | |
2381 | } | |
2382 | ||
2383 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2384 | { | |
2385 | enum register_status status; | |
2386 | unsigned v_regnum; | |
2387 | ||
2388 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM; | |
2389 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
2390 | memcpy (buf, reg_buf, S_REGISTER_SIZE); | |
2391 | return result_value; | |
2392 | } | |
2393 | ||
2394 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2395 | { | |
2396 | enum register_status status; | |
2397 | unsigned v_regnum; | |
2398 | ||
2399 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM; | |
2400 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
2401 | if (status != REG_VALID) | |
2402 | mark_value_bytes_unavailable (result_value, 0, | |
2403 | TYPE_LENGTH (value_type (result_value))); | |
2404 | else | |
2405 | memcpy (buf, reg_buf, H_REGISTER_SIZE); | |
2406 | return result_value; | |
2407 | } | |
2408 | ||
2409 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2410 | { | |
2411 | enum register_status status; | |
2412 | unsigned v_regnum; | |
2413 | ||
2414 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM; | |
2415 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
2416 | if (status != REG_VALID) | |
2417 | mark_value_bytes_unavailable (result_value, 0, | |
2418 | TYPE_LENGTH (value_type (result_value))); | |
2419 | else | |
2420 | memcpy (buf, reg_buf, B_REGISTER_SIZE); | |
2421 | return result_value; | |
2422 | } | |
2423 | ||
2424 | gdb_assert_not_reached ("regnum out of bound"); | |
2425 | } | |
2426 | ||
2427 | /* Implement the "pseudo_register_write" gdbarch method. */ | |
2428 | ||
2429 | static void | |
2430 | aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2431 | int regnum, const gdb_byte *buf) | |
2432 | { | |
2433 | gdb_byte reg_buf[MAX_REGISTER_SIZE]; | |
2434 | ||
2435 | /* Ensure the register buffer is zero, we want gdb writes of the | |
2436 | various 'scalar' pseudo registers to behavior like architectural | |
2437 | writes, register width bytes are written the remainder are set to | |
2438 | zero. */ | |
2439 | memset (reg_buf, 0, sizeof (reg_buf)); | |
2440 | ||
2441 | regnum -= gdbarch_num_regs (gdbarch); | |
2442 | ||
2443 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2444 | { | |
2445 | /* pseudo Q registers */ | |
2446 | unsigned v_regnum; | |
2447 | ||
2448 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM; | |
2449 | memcpy (reg_buf, buf, Q_REGISTER_SIZE); | |
2450 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2451 | return; | |
2452 | } | |
2453 | ||
2454 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2455 | { | |
2456 | /* pseudo D registers */ | |
2457 | unsigned v_regnum; | |
2458 | ||
2459 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM; | |
2460 | memcpy (reg_buf, buf, D_REGISTER_SIZE); | |
2461 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2462 | return; | |
2463 | } | |
2464 | ||
2465 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2466 | { | |
2467 | unsigned v_regnum; | |
2468 | ||
2469 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM; | |
2470 | memcpy (reg_buf, buf, S_REGISTER_SIZE); | |
2471 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2472 | return; | |
2473 | } | |
2474 | ||
2475 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2476 | { | |
2477 | /* pseudo H registers */ | |
2478 | unsigned v_regnum; | |
2479 | ||
2480 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM; | |
2481 | memcpy (reg_buf, buf, H_REGISTER_SIZE); | |
2482 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2483 | return; | |
2484 | } | |
2485 | ||
2486 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2487 | { | |
2488 | /* pseudo B registers */ | |
2489 | unsigned v_regnum; | |
2490 | ||
2491 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM; | |
2492 | memcpy (reg_buf, buf, B_REGISTER_SIZE); | |
2493 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2494 | return; | |
2495 | } | |
2496 | ||
2497 | gdb_assert_not_reached ("regnum out of bound"); | |
2498 | } | |
2499 | ||
2500 | /* Implement the "write_pc" gdbarch method. */ | |
2501 | ||
2502 | static void | |
2503 | aarch64_write_pc (struct regcache *regcache, CORE_ADDR pc) | |
2504 | { | |
2505 | regcache_cooked_write_unsigned (regcache, AARCH64_PC_REGNUM, pc); | |
2506 | } | |
2507 | ||
2508 | /* Callback function for user_reg_add. */ | |
2509 | ||
2510 | static struct value * | |
2511 | value_of_aarch64_user_reg (struct frame_info *frame, const void *baton) | |
2512 | { | |
2513 | const int *reg_p = baton; | |
2514 | ||
2515 | return value_of_register (*reg_p, frame); | |
2516 | } | |
2517 | \f | |
2518 | ||
2519 | /* Initialize the current architecture based on INFO. If possible, | |
2520 | re-use an architecture from ARCHES, which is a list of | |
2521 | architectures already created during this debugging session. | |
2522 | ||
2523 | Called e.g. at program startup, when reading a core file, and when | |
2524 | reading a binary file. */ | |
2525 | ||
2526 | static struct gdbarch * | |
2527 | aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2528 | { | |
2529 | struct gdbarch_tdep *tdep; | |
2530 | struct gdbarch *gdbarch; | |
2531 | struct gdbarch_list *best_arch; | |
2532 | struct tdesc_arch_data *tdesc_data = NULL; | |
2533 | const struct target_desc *tdesc = info.target_desc; | |
2534 | int i; | |
2535 | int have_fpa_registers = 1; | |
2536 | int valid_p = 1; | |
2537 | const struct tdesc_feature *feature; | |
2538 | int num_regs = 0; | |
2539 | int num_pseudo_regs = 0; | |
2540 | ||
2541 | /* Ensure we always have a target descriptor. */ | |
2542 | if (!tdesc_has_registers (tdesc)) | |
2543 | tdesc = tdesc_aarch64; | |
2544 | ||
2545 | gdb_assert (tdesc); | |
2546 | ||
2547 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.core"); | |
2548 | ||
2549 | if (feature == NULL) | |
2550 | return NULL; | |
2551 | ||
2552 | tdesc_data = tdesc_data_alloc (); | |
2553 | ||
2554 | /* Validate the descriptor provides the mandatory core R registers | |
2555 | and allocate their numbers. */ | |
2556 | for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++) | |
2557 | valid_p &= | |
2558 | tdesc_numbered_register (feature, tdesc_data, AARCH64_X0_REGNUM + i, | |
2559 | aarch64_r_register_names[i]); | |
2560 | ||
2561 | num_regs = AARCH64_X0_REGNUM + i; | |
2562 | ||
2563 | /* Look for the V registers. */ | |
2564 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu"); | |
2565 | if (feature) | |
2566 | { | |
2567 | /* Validate the descriptor provides the mandatory V registers | |
2568 | and allocate their numbers. */ | |
2569 | for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++) | |
2570 | valid_p &= | |
2571 | tdesc_numbered_register (feature, tdesc_data, AARCH64_V0_REGNUM + i, | |
2572 | aarch64_v_register_names[i]); | |
2573 | ||
2574 | num_regs = AARCH64_V0_REGNUM + i; | |
2575 | ||
2576 | num_pseudo_regs += 32; /* add the Qn scalar register pseudos */ | |
2577 | num_pseudo_regs += 32; /* add the Dn scalar register pseudos */ | |
2578 | num_pseudo_regs += 32; /* add the Sn scalar register pseudos */ | |
2579 | num_pseudo_regs += 32; /* add the Hn scalar register pseudos */ | |
2580 | num_pseudo_regs += 32; /* add the Bn scalar register pseudos */ | |
2581 | } | |
2582 | ||
2583 | if (!valid_p) | |
2584 | { | |
2585 | tdesc_data_cleanup (tdesc_data); | |
2586 | return NULL; | |
2587 | } | |
2588 | ||
2589 | /* AArch64 code is always little-endian. */ | |
2590 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; | |
2591 | ||
2592 | /* If there is already a candidate, use it. */ | |
2593 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
2594 | best_arch != NULL; | |
2595 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
2596 | { | |
2597 | /* Found a match. */ | |
2598 | break; | |
2599 | } | |
2600 | ||
2601 | if (best_arch != NULL) | |
2602 | { | |
2603 | if (tdesc_data != NULL) | |
2604 | tdesc_data_cleanup (tdesc_data); | |
2605 | return best_arch->gdbarch; | |
2606 | } | |
2607 | ||
2608 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); | |
2609 | gdbarch = gdbarch_alloc (&info, tdep); | |
2610 | ||
2611 | /* This should be low enough for everything. */ | |
2612 | tdep->lowest_pc = 0x20; | |
2613 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ | |
2614 | tdep->jb_elt_size = 8; | |
2615 | ||
2616 | set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call); | |
2617 | set_gdbarch_frame_align (gdbarch, aarch64_frame_align); | |
2618 | ||
2619 | set_gdbarch_write_pc (gdbarch, aarch64_write_pc); | |
2620 | ||
2621 | /* Frame handling. */ | |
2622 | set_gdbarch_dummy_id (gdbarch, aarch64_dummy_id); | |
2623 | set_gdbarch_unwind_pc (gdbarch, aarch64_unwind_pc); | |
2624 | set_gdbarch_unwind_sp (gdbarch, aarch64_unwind_sp); | |
2625 | ||
2626 | /* Advance PC across function entry code. */ | |
2627 | set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue); | |
2628 | ||
2629 | /* The stack grows downward. */ | |
2630 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2631 | ||
2632 | /* Breakpoint manipulation. */ | |
2633 | set_gdbarch_breakpoint_from_pc (gdbarch, aarch64_breakpoint_from_pc); | |
2634 | set_gdbarch_cannot_step_breakpoint (gdbarch, 1); | |
2635 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
2636 | ||
2637 | /* Information about registers, etc. */ | |
2638 | set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM); | |
2639 | set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM); | |
2640 | set_gdbarch_num_regs (gdbarch, num_regs); | |
2641 | ||
2642 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs); | |
2643 | set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value); | |
2644 | set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write); | |
2645 | set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name); | |
2646 | set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type); | |
2647 | set_tdesc_pseudo_register_reggroup_p (gdbarch, | |
2648 | aarch64_pseudo_register_reggroup_p); | |
2649 | ||
2650 | /* ABI */ | |
2651 | set_gdbarch_short_bit (gdbarch, 16); | |
2652 | set_gdbarch_int_bit (gdbarch, 32); | |
2653 | set_gdbarch_float_bit (gdbarch, 32); | |
2654 | set_gdbarch_double_bit (gdbarch, 64); | |
2655 | set_gdbarch_long_double_bit (gdbarch, 128); | |
2656 | set_gdbarch_long_bit (gdbarch, 64); | |
2657 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2658 | set_gdbarch_ptr_bit (gdbarch, 64); | |
2659 | set_gdbarch_char_signed (gdbarch, 0); | |
2660 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); | |
2661 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
2662 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); | |
2663 | ||
2664 | /* Internal <-> external register number maps. */ | |
2665 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum); | |
2666 | ||
2667 | /* Returning results. */ | |
2668 | set_gdbarch_return_value (gdbarch, aarch64_return_value); | |
2669 | ||
2670 | /* Disassembly. */ | |
2671 | set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn); | |
2672 | ||
2673 | /* Virtual tables. */ | |
2674 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
2675 | ||
2676 | /* Hook in the ABI-specific overrides, if they have been registered. */ | |
2677 | info.target_desc = tdesc; | |
2678 | info.tdep_info = (void *) tdesc_data; | |
2679 | gdbarch_init_osabi (info, gdbarch); | |
2680 | ||
2681 | dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg); | |
2682 | ||
2683 | /* Add some default predicates. */ | |
2684 | frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind); | |
2685 | dwarf2_append_unwinders (gdbarch); | |
2686 | frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind); | |
2687 | ||
2688 | frame_base_set_default (gdbarch, &aarch64_normal_base); | |
2689 | ||
2690 | /* Now we have tuned the configuration, set a few final things, | |
2691 | based on what the OS ABI has told us. */ | |
2692 | ||
2693 | if (tdep->jb_pc >= 0) | |
2694 | set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target); | |
2695 | ||
2696 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); | |
2697 | ||
2698 | /* Add standard register aliases. */ | |
2699 | for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++) | |
2700 | user_reg_add (gdbarch, aarch64_register_aliases[i].name, | |
2701 | value_of_aarch64_user_reg, | |
2702 | &aarch64_register_aliases[i].regnum); | |
2703 | ||
2704 | return gdbarch; | |
2705 | } | |
2706 | ||
2707 | static void | |
2708 | aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
2709 | { | |
2710 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2711 | ||
2712 | if (tdep == NULL) | |
2713 | return; | |
2714 | ||
2715 | fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"), | |
2716 | paddress (gdbarch, tdep->lowest_pc)); | |
2717 | } | |
2718 | ||
2719 | /* Suppress warning from -Wmissing-prototypes. */ | |
2720 | extern initialize_file_ftype _initialize_aarch64_tdep; | |
2721 | ||
2722 | void | |
2723 | _initialize_aarch64_tdep (void) | |
2724 | { | |
2725 | gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init, | |
2726 | aarch64_dump_tdep); | |
2727 | ||
2728 | initialize_tdesc_aarch64 (); | |
2729 | initialize_tdesc_aarch64_without_fpu (); | |
2730 | ||
2731 | /* Debug this file's internals. */ | |
2732 | add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\ | |
2733 | Set AArch64 debugging."), _("\ | |
2734 | Show AArch64 debugging."), _("\ | |
2735 | When on, AArch64 specific debugging is enabled."), | |
2736 | NULL, | |
2737 | show_aarch64_debug, | |
2738 | &setdebuglist, &showdebuglist); | |
2739 | } |