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e53bef9f | 1 | /* Target-dependent code for AMD64. |
ce0eebec | 2 | |
213516ef | 3 | Copyright (C) 2001-2023 Free Software Foundation, Inc. |
5ae96ec1 MK |
4 | |
5 | Contributed by Jiri Smid, SuSE Labs. | |
53e95fcf JS |
6 | |
7 | This file is part of GDB. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
53e95fcf JS |
12 | (at your option) any later version. |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
53e95fcf JS |
21 | |
22 | #include "defs.h" | |
83b6e1f1 | 23 | #include "language.h" |
4de283e4 TT |
24 | #include "opcode/i386.h" |
25 | #include "dis-asm.h" | |
c4f35dd8 | 26 | #include "arch-utils.h" |
c4f35dd8 | 27 | #include "dummy-frame.h" |
4de283e4 | 28 | #include "frame.h" |
c4f35dd8 MK |
29 | #include "frame-base.h" |
30 | #include "frame-unwind.h" | |
d55e5aa6 TT |
31 | #include "inferior.h" |
32 | #include "infrun.h" | |
4de283e4 TT |
33 | #include "gdbcmd.h" |
34 | #include "gdbcore.h" | |
c4f35dd8 | 35 | #include "objfiles.h" |
53e95fcf | 36 | #include "regcache.h" |
2c261fae | 37 | #include "regset.h" |
53e95fcf | 38 | #include "symfile.h" |
4de283e4 TT |
39 | #include "disasm.h" |
40 | #include "amd64-tdep.h" | |
41 | #include "i387-tdep.h" | |
268a13a5 | 42 | #include "gdbsupport/x86-xstate.h" |
4de283e4 | 43 | #include <algorithm> |
22916b07 | 44 | #include "target-descriptions.h" |
4de283e4 TT |
45 | #include "arch/amd64.h" |
46 | #include "producer.h" | |
47 | #include "ax.h" | |
48 | #include "ax-gdb.h" | |
268a13a5 | 49 | #include "gdbsupport/byte-vector.h" |
4de283e4 | 50 | #include "osabi.h" |
1d509aa6 | 51 | #include "x86-tdep.h" |
257e02d8 | 52 | #include "amd64-ravenscar-thread.h" |
6710bf39 | 53 | |
e53bef9f MK |
54 | /* Note that the AMD64 architecture was previously known as x86-64. |
55 | The latter is (forever) engraved into the canonical system name as | |
90f90721 | 56 | returned by config.guess, and used as the name for the AMD64 port |
e53bef9f MK |
57 | of GNU/Linux. The BSD's have renamed their ports to amd64; they |
58 | don't like to shout. For GDB we prefer the amd64_-prefix over the | |
59 | x86_64_-prefix since it's so much easier to type. */ | |
60 | ||
402ecd56 | 61 | /* Register information. */ |
c4f35dd8 | 62 | |
27087b7f | 63 | static const char * const amd64_register_names[] = |
de220d0f | 64 | { |
6707b003 | 65 | "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp", |
c4f35dd8 MK |
66 | |
67 | /* %r8 is indeed register number 8. */ | |
6707b003 UW |
68 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
69 | "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs", | |
c4f35dd8 | 70 | |
af233647 | 71 | /* %st0 is register number 24. */ |
6707b003 UW |
72 | "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", |
73 | "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop", | |
c4f35dd8 | 74 | |
af233647 | 75 | /* %xmm0 is register number 40. */ |
6707b003 UW |
76 | "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", |
77 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", | |
78 | "mxcsr", | |
0e04a514 ML |
79 | }; |
80 | ||
27087b7f | 81 | static const char * const amd64_ymm_names[] = |
a055a187 L |
82 | { |
83 | "ymm0", "ymm1", "ymm2", "ymm3", | |
84 | "ymm4", "ymm5", "ymm6", "ymm7", | |
85 | "ymm8", "ymm9", "ymm10", "ymm11", | |
86 | "ymm12", "ymm13", "ymm14", "ymm15" | |
87 | }; | |
88 | ||
27087b7f | 89 | static const char * const amd64_ymm_avx512_names[] = |
01f9f808 MS |
90 | { |
91 | "ymm16", "ymm17", "ymm18", "ymm19", | |
92 | "ymm20", "ymm21", "ymm22", "ymm23", | |
93 | "ymm24", "ymm25", "ymm26", "ymm27", | |
94 | "ymm28", "ymm29", "ymm30", "ymm31" | |
95 | }; | |
96 | ||
27087b7f | 97 | static const char * const amd64_ymmh_names[] = |
a055a187 L |
98 | { |
99 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
100 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
101 | "ymm8h", "ymm9h", "ymm10h", "ymm11h", | |
102 | "ymm12h", "ymm13h", "ymm14h", "ymm15h" | |
103 | }; | |
de220d0f | 104 | |
27087b7f | 105 | static const char * const amd64_ymmh_avx512_names[] = |
01f9f808 MS |
106 | { |
107 | "ymm16h", "ymm17h", "ymm18h", "ymm19h", | |
108 | "ymm20h", "ymm21h", "ymm22h", "ymm23h", | |
109 | "ymm24h", "ymm25h", "ymm26h", "ymm27h", | |
110 | "ymm28h", "ymm29h", "ymm30h", "ymm31h" | |
111 | }; | |
112 | ||
27087b7f | 113 | static const char * const amd64_mpx_names[] = |
e43e105e WT |
114 | { |
115 | "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" | |
116 | }; | |
117 | ||
27087b7f | 118 | static const char * const amd64_k_names[] = |
01f9f808 MS |
119 | { |
120 | "k0", "k1", "k2", "k3", | |
121 | "k4", "k5", "k6", "k7" | |
122 | }; | |
123 | ||
27087b7f | 124 | static const char * const amd64_zmmh_names[] = |
01f9f808 MS |
125 | { |
126 | "zmm0h", "zmm1h", "zmm2h", "zmm3h", | |
127 | "zmm4h", "zmm5h", "zmm6h", "zmm7h", | |
128 | "zmm8h", "zmm9h", "zmm10h", "zmm11h", | |
129 | "zmm12h", "zmm13h", "zmm14h", "zmm15h", | |
130 | "zmm16h", "zmm17h", "zmm18h", "zmm19h", | |
131 | "zmm20h", "zmm21h", "zmm22h", "zmm23h", | |
132 | "zmm24h", "zmm25h", "zmm26h", "zmm27h", | |
133 | "zmm28h", "zmm29h", "zmm30h", "zmm31h" | |
134 | }; | |
135 | ||
27087b7f | 136 | static const char * const amd64_zmm_names[] = |
01f9f808 MS |
137 | { |
138 | "zmm0", "zmm1", "zmm2", "zmm3", | |
139 | "zmm4", "zmm5", "zmm6", "zmm7", | |
140 | "zmm8", "zmm9", "zmm10", "zmm11", | |
141 | "zmm12", "zmm13", "zmm14", "zmm15", | |
142 | "zmm16", "zmm17", "zmm18", "zmm19", | |
143 | "zmm20", "zmm21", "zmm22", "zmm23", | |
144 | "zmm24", "zmm25", "zmm26", "zmm27", | |
145 | "zmm28", "zmm29", "zmm30", "zmm31" | |
146 | }; | |
147 | ||
27087b7f | 148 | static const char * const amd64_xmm_avx512_names[] = { |
01f9f808 MS |
149 | "xmm16", "xmm17", "xmm18", "xmm19", |
150 | "xmm20", "xmm21", "xmm22", "xmm23", | |
151 | "xmm24", "xmm25", "xmm26", "xmm27", | |
152 | "xmm28", "xmm29", "xmm30", "xmm31" | |
153 | }; | |
154 | ||
27087b7f | 155 | static const char * const amd64_pkeys_names[] = { |
51547df6 MS |
156 | "pkru" |
157 | }; | |
158 | ||
c4f35dd8 MK |
159 | /* DWARF Register Number Mapping as defined in the System V psABI, |
160 | section 3.6. */ | |
53e95fcf | 161 | |
e53bef9f | 162 | static int amd64_dwarf_regmap[] = |
0e04a514 | 163 | { |
c4f35dd8 | 164 | /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */ |
90f90721 MK |
165 | AMD64_RAX_REGNUM, AMD64_RDX_REGNUM, |
166 | AMD64_RCX_REGNUM, AMD64_RBX_REGNUM, | |
167 | AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, | |
c4f35dd8 MK |
168 | |
169 | /* Frame Pointer Register RBP. */ | |
90f90721 | 170 | AMD64_RBP_REGNUM, |
c4f35dd8 MK |
171 | |
172 | /* Stack Pointer Register RSP. */ | |
90f90721 | 173 | AMD64_RSP_REGNUM, |
c4f35dd8 MK |
174 | |
175 | /* Extended Integer Registers 8 - 15. */ | |
5b856f36 PM |
176 | AMD64_R8_REGNUM, /* %r8 */ |
177 | AMD64_R9_REGNUM, /* %r9 */ | |
178 | AMD64_R10_REGNUM, /* %r10 */ | |
179 | AMD64_R11_REGNUM, /* %r11 */ | |
180 | AMD64_R12_REGNUM, /* %r12 */ | |
181 | AMD64_R13_REGNUM, /* %r13 */ | |
182 | AMD64_R14_REGNUM, /* %r14 */ | |
183 | AMD64_R15_REGNUM, /* %r15 */ | |
c4f35dd8 | 184 | |
59207364 | 185 | /* Return Address RA. Mapped to RIP. */ |
90f90721 | 186 | AMD64_RIP_REGNUM, |
c4f35dd8 MK |
187 | |
188 | /* SSE Registers 0 - 7. */ | |
90f90721 MK |
189 | AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, |
190 | AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, | |
191 | AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, | |
192 | AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, | |
c4f35dd8 MK |
193 | |
194 | /* Extended SSE Registers 8 - 15. */ | |
90f90721 MK |
195 | AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9, |
196 | AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11, | |
197 | AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13, | |
198 | AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15, | |
c4f35dd8 MK |
199 | |
200 | /* Floating Point Registers 0-7. */ | |
90f90721 MK |
201 | AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1, |
202 | AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, | |
203 | AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, | |
c6f4c129 | 204 | AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7, |
f7ca3fcf PM |
205 | |
206 | /* MMX Registers 0 - 7. | |
207 | We have to handle those registers specifically, as their register | |
208 | number within GDB depends on the target (or they may even not be | |
209 | available at all). */ | |
210 | -1, -1, -1, -1, -1, -1, -1, -1, | |
211 | ||
c6f4c129 JB |
212 | /* Control and Status Flags Register. */ |
213 | AMD64_EFLAGS_REGNUM, | |
214 | ||
215 | /* Selector Registers. */ | |
216 | AMD64_ES_REGNUM, | |
217 | AMD64_CS_REGNUM, | |
218 | AMD64_SS_REGNUM, | |
219 | AMD64_DS_REGNUM, | |
220 | AMD64_FS_REGNUM, | |
221 | AMD64_GS_REGNUM, | |
222 | -1, | |
223 | -1, | |
224 | ||
225 | /* Segment Base Address Registers. */ | |
226 | -1, | |
227 | -1, | |
228 | -1, | |
229 | -1, | |
230 | ||
231 | /* Special Selector Registers. */ | |
232 | -1, | |
233 | -1, | |
234 | ||
235 | /* Floating Point Control Registers. */ | |
236 | AMD64_MXCSR_REGNUM, | |
237 | AMD64_FCTRL_REGNUM, | |
238 | AMD64_FSTAT_REGNUM | |
c4f35dd8 | 239 | }; |
0e04a514 | 240 | |
e53bef9f MK |
241 | static const int amd64_dwarf_regmap_len = |
242 | (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0])); | |
0e04a514 | 243 | |
c4f35dd8 MK |
244 | /* Convert DWARF register number REG to the appropriate register |
245 | number used by GDB. */ | |
26abbdc4 | 246 | |
c4f35dd8 | 247 | static int |
d3f73121 | 248 | amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
53e95fcf | 249 | { |
08106042 | 250 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
a055a187 | 251 | int ymm0_regnum = tdep->ymm0_regnum; |
c4f35dd8 | 252 | int regnum = -1; |
53e95fcf | 253 | |
16aff9a6 | 254 | if (reg >= 0 && reg < amd64_dwarf_regmap_len) |
e53bef9f | 255 | regnum = amd64_dwarf_regmap[reg]; |
53e95fcf | 256 | |
0fde2c53 | 257 | if (ymm0_regnum >= 0 |
a055a187 L |
258 | && i386_xmm_regnum_p (gdbarch, regnum)) |
259 | regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep); | |
c4f35dd8 MK |
260 | |
261 | return regnum; | |
53e95fcf | 262 | } |
d532c08f | 263 | |
35669430 DE |
264 | /* Map architectural register numbers to gdb register numbers. */ |
265 | ||
266 | static const int amd64_arch_regmap[16] = | |
267 | { | |
268 | AMD64_RAX_REGNUM, /* %rax */ | |
269 | AMD64_RCX_REGNUM, /* %rcx */ | |
270 | AMD64_RDX_REGNUM, /* %rdx */ | |
271 | AMD64_RBX_REGNUM, /* %rbx */ | |
272 | AMD64_RSP_REGNUM, /* %rsp */ | |
273 | AMD64_RBP_REGNUM, /* %rbp */ | |
274 | AMD64_RSI_REGNUM, /* %rsi */ | |
275 | AMD64_RDI_REGNUM, /* %rdi */ | |
276 | AMD64_R8_REGNUM, /* %r8 */ | |
277 | AMD64_R9_REGNUM, /* %r9 */ | |
278 | AMD64_R10_REGNUM, /* %r10 */ | |
279 | AMD64_R11_REGNUM, /* %r11 */ | |
280 | AMD64_R12_REGNUM, /* %r12 */ | |
281 | AMD64_R13_REGNUM, /* %r13 */ | |
282 | AMD64_R14_REGNUM, /* %r14 */ | |
283 | AMD64_R15_REGNUM /* %r15 */ | |
284 | }; | |
285 | ||
286 | static const int amd64_arch_regmap_len = | |
287 | (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0])); | |
288 | ||
289 | /* Convert architectural register number REG to the appropriate register | |
290 | number used by GDB. */ | |
291 | ||
292 | static int | |
293 | amd64_arch_reg_to_regnum (int reg) | |
294 | { | |
295 | gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len); | |
296 | ||
297 | return amd64_arch_regmap[reg]; | |
298 | } | |
299 | ||
1ba53b71 L |
300 | /* Register names for byte pseudo-registers. */ |
301 | ||
27087b7f | 302 | static const char * const amd64_byte_names[] = |
1ba53b71 L |
303 | { |
304 | "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl", | |
fe01d668 L |
305 | "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l", |
306 | "ah", "bh", "ch", "dh" | |
1ba53b71 L |
307 | }; |
308 | ||
fe01d668 L |
309 | /* Number of lower byte registers. */ |
310 | #define AMD64_NUM_LOWER_BYTE_REGS 16 | |
311 | ||
1ba53b71 L |
312 | /* Register names for word pseudo-registers. */ |
313 | ||
27087b7f | 314 | static const char * const amd64_word_names[] = |
1ba53b71 | 315 | { |
9cad29ac | 316 | "ax", "bx", "cx", "dx", "si", "di", "bp", "", |
1ba53b71 L |
317 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" |
318 | }; | |
319 | ||
320 | /* Register names for dword pseudo-registers. */ | |
321 | ||
27087b7f | 322 | static const char * const amd64_dword_names[] = |
1ba53b71 L |
323 | { |
324 | "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp", | |
fff4548b MK |
325 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d", |
326 | "eip" | |
1ba53b71 L |
327 | }; |
328 | ||
329 | /* Return the name of register REGNUM. */ | |
330 | ||
331 | static const char * | |
332 | amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) | |
333 | { | |
08106042 | 334 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
1ba53b71 L |
335 | if (i386_byte_regnum_p (gdbarch, regnum)) |
336 | return amd64_byte_names[regnum - tdep->al_regnum]; | |
01f9f808 MS |
337 | else if (i386_zmm_regnum_p (gdbarch, regnum)) |
338 | return amd64_zmm_names[regnum - tdep->zmm0_regnum]; | |
a055a187 L |
339 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
340 | return amd64_ymm_names[regnum - tdep->ymm0_regnum]; | |
01f9f808 MS |
341 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
342 | return amd64_ymm_avx512_names[regnum - tdep->ymm16_regnum]; | |
1ba53b71 L |
343 | else if (i386_word_regnum_p (gdbarch, regnum)) |
344 | return amd64_word_names[regnum - tdep->ax_regnum]; | |
345 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
346 | return amd64_dword_names[regnum - tdep->eax_regnum]; | |
347 | else | |
348 | return i386_pseudo_register_name (gdbarch, regnum); | |
349 | } | |
350 | ||
3543a589 TT |
351 | static struct value * |
352 | amd64_pseudo_register_read_value (struct gdbarch *gdbarch, | |
849d0ba8 | 353 | readable_regcache *regcache, |
3543a589 | 354 | int regnum) |
1ba53b71 | 355 | { |
08106042 | 356 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
3543a589 | 357 | |
317c3ed9 | 358 | value *result_value = value::allocate (register_type (gdbarch, regnum)); |
6f9c9d71 | 359 | result_value->set_lval (lval_register); |
3543a589 | 360 | VALUE_REGNUM (result_value) = regnum; |
bbe912ba | 361 | gdb_byte *buf = result_value->contents_raw ().data (); |
1ba53b71 L |
362 | |
363 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
364 | { | |
365 | int gpnum = regnum - tdep->al_regnum; | |
366 | ||
367 | /* Extract (always little endian). */ | |
fe01d668 L |
368 | if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) |
369 | { | |
925047fe SM |
370 | gpnum -= AMD64_NUM_LOWER_BYTE_REGS; |
371 | gdb_byte raw_buf[register_size (gdbarch, gpnum)]; | |
372 | ||
fe01d668 | 373 | /* Special handling for AH, BH, CH, DH. */ |
925047fe | 374 | register_status status = regcache->raw_read (gpnum, raw_buf); |
05d1431c PA |
375 | if (status == REG_VALID) |
376 | memcpy (buf, raw_buf + 1, 1); | |
3543a589 | 377 | else |
d00664db TT |
378 | result_value->mark_bytes_unavailable (0, |
379 | result_value->type ()->length ()); | |
fe01d668 L |
380 | } |
381 | else | |
382 | { | |
925047fe SM |
383 | gdb_byte raw_buf[register_size (gdbarch, gpnum)]; |
384 | register_status status = regcache->raw_read (gpnum, raw_buf); | |
05d1431c PA |
385 | if (status == REG_VALID) |
386 | memcpy (buf, raw_buf, 1); | |
3543a589 | 387 | else |
d00664db TT |
388 | result_value->mark_bytes_unavailable (0, |
389 | result_value->type ()->length ()); | |
fe01d668 | 390 | } |
1ba53b71 L |
391 | } |
392 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
393 | { | |
394 | int gpnum = regnum - tdep->eax_regnum; | |
925047fe | 395 | gdb_byte raw_buf[register_size (gdbarch, gpnum)]; |
1ba53b71 | 396 | /* Extract (always little endian). */ |
925047fe | 397 | register_status status = regcache->raw_read (gpnum, raw_buf); |
05d1431c PA |
398 | if (status == REG_VALID) |
399 | memcpy (buf, raw_buf, 4); | |
3543a589 | 400 | else |
d00664db TT |
401 | result_value->mark_bytes_unavailable (0, |
402 | result_value->type ()->length ()); | |
1ba53b71 L |
403 | } |
404 | else | |
3543a589 TT |
405 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, |
406 | result_value); | |
407 | ||
408 | return result_value; | |
1ba53b71 L |
409 | } |
410 | ||
411 | static void | |
412 | amd64_pseudo_register_write (struct gdbarch *gdbarch, | |
413 | struct regcache *regcache, | |
414 | int regnum, const gdb_byte *buf) | |
415 | { | |
08106042 | 416 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
1ba53b71 L |
417 | |
418 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
419 | { | |
420 | int gpnum = regnum - tdep->al_regnum; | |
421 | ||
fe01d668 L |
422 | if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) |
423 | { | |
925047fe SM |
424 | gpnum -= AMD64_NUM_LOWER_BYTE_REGS; |
425 | gdb_byte raw_buf[register_size (gdbarch, gpnum)]; | |
426 | ||
fe01d668 | 427 | /* Read ... AH, BH, CH, DH. */ |
925047fe | 428 | regcache->raw_read (gpnum, raw_buf); |
fe01d668 L |
429 | /* ... Modify ... (always little endian). */ |
430 | memcpy (raw_buf + 1, buf, 1); | |
431 | /* ... Write. */ | |
925047fe | 432 | regcache->raw_write (gpnum, raw_buf); |
fe01d668 L |
433 | } |
434 | else | |
435 | { | |
925047fe SM |
436 | gdb_byte raw_buf[register_size (gdbarch, gpnum)]; |
437 | ||
fe01d668 | 438 | /* Read ... */ |
0b883586 | 439 | regcache->raw_read (gpnum, raw_buf); |
fe01d668 L |
440 | /* ... Modify ... (always little endian). */ |
441 | memcpy (raw_buf, buf, 1); | |
442 | /* ... Write. */ | |
10eaee5f | 443 | regcache->raw_write (gpnum, raw_buf); |
fe01d668 | 444 | } |
1ba53b71 L |
445 | } |
446 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
447 | { | |
448 | int gpnum = regnum - tdep->eax_regnum; | |
925047fe | 449 | gdb_byte raw_buf[register_size (gdbarch, gpnum)]; |
1ba53b71 L |
450 | |
451 | /* Read ... */ | |
0b883586 | 452 | regcache->raw_read (gpnum, raw_buf); |
1ba53b71 L |
453 | /* ... Modify ... (always little endian). */ |
454 | memcpy (raw_buf, buf, 4); | |
455 | /* ... Write. */ | |
10eaee5f | 456 | regcache->raw_write (gpnum, raw_buf); |
1ba53b71 L |
457 | } |
458 | else | |
459 | i386_pseudo_register_write (gdbarch, regcache, regnum, buf); | |
460 | } | |
461 | ||
62e5fd57 MK |
462 | /* Implement the 'ax_pseudo_register_collect' gdbarch method. */ |
463 | ||
464 | static int | |
465 | amd64_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
466 | struct agent_expr *ax, int regnum) | |
467 | { | |
08106042 | 468 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
62e5fd57 MK |
469 | |
470 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
471 | { | |
472 | int gpnum = regnum - tdep->al_regnum; | |
473 | ||
474 | if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) | |
475 | ax_reg_mask (ax, gpnum - AMD64_NUM_LOWER_BYTE_REGS); | |
476 | else | |
477 | ax_reg_mask (ax, gpnum); | |
478 | return 0; | |
479 | } | |
480 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
481 | { | |
482 | int gpnum = regnum - tdep->eax_regnum; | |
483 | ||
484 | ax_reg_mask (ax, gpnum); | |
485 | return 0; | |
486 | } | |
487 | else | |
488 | return i386_ax_pseudo_register_collect (gdbarch, ax, regnum); | |
489 | } | |
490 | ||
53e95fcf JS |
491 | \f |
492 | ||
bf4d6c1c JB |
493 | /* Register classes as defined in the psABI. */ |
494 | ||
495 | enum amd64_reg_class | |
496 | { | |
497 | AMD64_INTEGER, | |
498 | AMD64_SSE, | |
499 | AMD64_SSEUP, | |
500 | AMD64_X87, | |
501 | AMD64_X87UP, | |
502 | AMD64_COMPLEX_X87, | |
503 | AMD64_NO_CLASS, | |
504 | AMD64_MEMORY | |
505 | }; | |
506 | ||
efb1c01c MK |
507 | /* Return the union class of CLASS1 and CLASS2. See the psABI for |
508 | details. */ | |
509 | ||
510 | static enum amd64_reg_class | |
511 | amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2) | |
512 | { | |
513 | /* Rule (a): If both classes are equal, this is the resulting class. */ | |
514 | if (class1 == class2) | |
515 | return class1; | |
516 | ||
517 | /* Rule (b): If one of the classes is NO_CLASS, the resulting class | |
518 | is the other class. */ | |
519 | if (class1 == AMD64_NO_CLASS) | |
520 | return class2; | |
521 | if (class2 == AMD64_NO_CLASS) | |
522 | return class1; | |
523 | ||
524 | /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */ | |
525 | if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY) | |
526 | return AMD64_MEMORY; | |
527 | ||
528 | /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */ | |
529 | if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER) | |
530 | return AMD64_INTEGER; | |
531 | ||
532 | /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class, | |
533 | MEMORY is used as class. */ | |
534 | if (class1 == AMD64_X87 || class1 == AMD64_X87UP | |
535 | || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87 | |
536 | || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87) | |
537 | return AMD64_MEMORY; | |
538 | ||
539 | /* Rule (f): Otherwise class SSE is used. */ | |
540 | return AMD64_SSE; | |
541 | } | |
542 | ||
fe978cb0 | 543 | static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]); |
bf4d6c1c | 544 | |
4aa866af | 545 | /* Return true if TYPE is a structure or union with unaligned fields. */ |
79b1ab3d | 546 | |
4aa866af LS |
547 | static bool |
548 | amd64_has_unaligned_fields (struct type *type) | |
79b1ab3d | 549 | { |
78134374 SM |
550 | if (type->code () == TYPE_CODE_STRUCT |
551 | || type->code () == TYPE_CODE_UNION) | |
4aa866af | 552 | { |
1f704f76 | 553 | for (int i = 0; i < type->num_fields (); i++) |
4aa866af | 554 | { |
940da03e | 555 | struct type *subtype = check_typedef (type->field (i).type ()); |
4aa866af | 556 | |
a59240a4 TT |
557 | /* Ignore static fields, empty fields (for example nested |
558 | empty structures), and bitfields (these are handled by | |
559 | the caller). */ | |
c819a338 | 560 | if (type->field (i).is_static () |
4aa866af | 561 | || (TYPE_FIELD_BITSIZE (type, i) == 0 |
df86565b | 562 | && subtype->length () == 0) |
a59240a4 | 563 | || TYPE_FIELD_PACKED (type, i)) |
4aa866af LS |
564 | continue; |
565 | ||
b610c045 | 566 | int bitpos = type->field (i).loc_bitpos (); |
cd3f655c | 567 | |
4aa866af LS |
568 | if (bitpos % 8 != 0) |
569 | return true; | |
570 | ||
a12a15e7 AB |
571 | int align = type_align (subtype); |
572 | if (align == 0) | |
573 | error (_("could not determine alignment of type")); | |
574 | ||
4aa866af LS |
575 | int bytepos = bitpos / 8; |
576 | if (bytepos % align != 0) | |
577 | return true; | |
578 | ||
a59240a4 | 579 | if (amd64_has_unaligned_fields (subtype)) |
4aa866af LS |
580 | return true; |
581 | } | |
582 | } | |
79b1ab3d | 583 | |
4aa866af | 584 | return false; |
79b1ab3d MK |
585 | } |
586 | ||
d10eccaa TV |
587 | /* Classify field I of TYPE starting at BITOFFSET according to the rules for |
588 | structures and union types, and store the result in THECLASS. */ | |
589 | ||
590 | static void | |
591 | amd64_classify_aggregate_field (struct type *type, int i, | |
592 | enum amd64_reg_class theclass[2], | |
593 | unsigned int bitoffset) | |
594 | { | |
940da03e | 595 | struct type *subtype = check_typedef (type->field (i).type ()); |
d10eccaa TV |
596 | enum amd64_reg_class subclass[2]; |
597 | int bitsize = TYPE_FIELD_BITSIZE (type, i); | |
d10eccaa TV |
598 | |
599 | if (bitsize == 0) | |
df86565b | 600 | bitsize = subtype->length () * 8; |
d10eccaa TV |
601 | |
602 | /* Ignore static fields, or empty fields, for example nested | |
603 | empty structures.*/ | |
c819a338 | 604 | if (type->field (i).is_static () || bitsize == 0) |
d10eccaa TV |
605 | return; |
606 | ||
b610c045 | 607 | int bitpos = bitoffset + type->field (i).loc_bitpos (); |
cd3f655c SM |
608 | int pos = bitpos / 64; |
609 | int endpos = (bitpos + bitsize - 1) / 64; | |
610 | ||
78134374 SM |
611 | if (subtype->code () == TYPE_CODE_STRUCT |
612 | || subtype->code () == TYPE_CODE_UNION) | |
d10eccaa TV |
613 | { |
614 | /* Each field of an object is classified recursively. */ | |
615 | int j; | |
1f704f76 | 616 | for (j = 0; j < subtype->num_fields (); j++) |
d10eccaa TV |
617 | amd64_classify_aggregate_field (subtype, j, theclass, bitpos); |
618 | return; | |
619 | } | |
620 | ||
621 | gdb_assert (pos == 0 || pos == 1); | |
622 | ||
623 | amd64_classify (subtype, subclass); | |
624 | theclass[pos] = amd64_merge_classes (theclass[pos], subclass[0]); | |
625 | if (bitsize <= 64 && pos == 0 && endpos == 1) | |
626 | /* This is a bit of an odd case: We have a field that would | |
627 | normally fit in one of the two eightbytes, except that | |
628 | it is placed in a way that this field straddles them. | |
629 | This has been seen with a structure containing an array. | |
630 | ||
631 | The ABI is a bit unclear in this case, but we assume that | |
632 | this field's class (stored in subclass[0]) must also be merged | |
633 | into class[1]. In other words, our field has a piece stored | |
634 | in the second eight-byte, and thus its class applies to | |
635 | the second eight-byte as well. | |
636 | ||
637 | In the case where the field length exceeds 8 bytes, | |
638 | it should not be necessary to merge the field class | |
639 | into class[1]. As LEN > 8, subclass[1] is necessarily | |
640 | different from AMD64_NO_CLASS. If subclass[1] is equal | |
641 | to subclass[0], then the normal class[1]/subclass[1] | |
642 | merging will take care of everything. For subclass[1] | |
643 | to be different from subclass[0], I can only see the case | |
644 | where we have a SSE/SSEUP or X87/X87UP pair, which both | |
645 | use up all 16 bytes of the aggregate, and are already | |
646 | handled just fine (because each portion sits on its own | |
647 | 8-byte). */ | |
648 | theclass[1] = amd64_merge_classes (theclass[1], subclass[0]); | |
649 | if (pos == 0) | |
650 | theclass[1] = amd64_merge_classes (theclass[1], subclass[1]); | |
651 | } | |
652 | ||
efb1c01c MK |
653 | /* Classify TYPE according to the rules for aggregate (structures and |
654 | arrays) and union types, and store the result in CLASS. */ | |
c4f35dd8 MK |
655 | |
656 | static void | |
fe978cb0 | 657 | amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2]) |
53e95fcf | 658 | { |
b1718fcd AB |
659 | /* 1. If the size of an object is larger than two times eight bytes, or |
660 | it is a non-trivial C++ object, or it has unaligned fields, then it | |
661 | has class memory. | |
662 | ||
663 | It is important that the trivially_copyable check is before the | |
664 | unaligned fields check, as C++ classes with virtual base classes | |
665 | will have fields (for the virtual base classes) with non-constant | |
666 | loc_bitpos attributes, which will cause an assert to trigger within | |
667 | the unaligned field check. As classes with virtual bases are not | |
668 | trivially copyable, checking that first avoids this problem. */ | |
862ebb27 TT |
669 | if (TYPE_HAS_DYNAMIC_LENGTH (type) |
670 | || type->length () > 16 | |
b1718fcd AB |
671 | || !language_pass_by_reference (type).trivially_copyable |
672 | || amd64_has_unaligned_fields (type)) | |
53e95fcf | 673 | { |
fe978cb0 | 674 | theclass[0] = theclass[1] = AMD64_MEMORY; |
efb1c01c | 675 | return; |
53e95fcf | 676 | } |
efb1c01c MK |
677 | |
678 | /* 2. Both eightbytes get initialized to class NO_CLASS. */ | |
fe978cb0 | 679 | theclass[0] = theclass[1] = AMD64_NO_CLASS; |
efb1c01c MK |
680 | |
681 | /* 3. Each field of an object is classified recursively so that | |
dda83cd7 SM |
682 | always two fields are considered. The resulting class is |
683 | calculated according to the classes of the fields in the | |
684 | eightbyte: */ | |
efb1c01c | 685 | |
78134374 | 686 | if (type->code () == TYPE_CODE_ARRAY) |
8ffd9b1b | 687 | { |
27710edb | 688 | struct type *subtype = check_typedef (type->target_type ()); |
efb1c01c MK |
689 | |
690 | /* All fields in an array have the same type. */ | |
fe978cb0 | 691 | amd64_classify (subtype, theclass); |
df86565b | 692 | if (type->length () > 8 && theclass[1] == AMD64_NO_CLASS) |
fe978cb0 | 693 | theclass[1] = theclass[0]; |
8ffd9b1b | 694 | } |
53e95fcf JS |
695 | else |
696 | { | |
efb1c01c | 697 | int i; |
53e95fcf | 698 | |
efb1c01c | 699 | /* Structure or union. */ |
78134374 SM |
700 | gdb_assert (type->code () == TYPE_CODE_STRUCT |
701 | || type->code () == TYPE_CODE_UNION); | |
efb1c01c | 702 | |
1f704f76 | 703 | for (i = 0; i < type->num_fields (); i++) |
d10eccaa | 704 | amd64_classify_aggregate_field (type, i, theclass, 0); |
53e95fcf | 705 | } |
efb1c01c MK |
706 | |
707 | /* 4. Then a post merger cleanup is done: */ | |
708 | ||
709 | /* Rule (a): If one of the classes is MEMORY, the whole argument is | |
710 | passed in memory. */ | |
fe978cb0 PA |
711 | if (theclass[0] == AMD64_MEMORY || theclass[1] == AMD64_MEMORY) |
712 | theclass[0] = theclass[1] = AMD64_MEMORY; | |
efb1c01c | 713 | |
177b42fe | 714 | /* Rule (b): If SSEUP is not preceded by SSE, it is converted to |
efb1c01c | 715 | SSE. */ |
fe978cb0 PA |
716 | if (theclass[0] == AMD64_SSEUP) |
717 | theclass[0] = AMD64_SSE; | |
718 | if (theclass[1] == AMD64_SSEUP && theclass[0] != AMD64_SSE) | |
719 | theclass[1] = AMD64_SSE; | |
efb1c01c MK |
720 | } |
721 | ||
722 | /* Classify TYPE, and store the result in CLASS. */ | |
723 | ||
bf4d6c1c | 724 | static void |
fe978cb0 | 725 | amd64_classify (struct type *type, enum amd64_reg_class theclass[2]) |
efb1c01c | 726 | { |
78134374 | 727 | enum type_code code = type->code (); |
df86565b | 728 | int len = type->length (); |
efb1c01c | 729 | |
fe978cb0 | 730 | theclass[0] = theclass[1] = AMD64_NO_CLASS; |
efb1c01c MK |
731 | |
732 | /* Arguments of types (signed and unsigned) _Bool, char, short, int, | |
5a7225ed JB |
733 | long, long long, and pointers are in the INTEGER class. Similarly, |
734 | range types, used by languages such as Ada, are also in the INTEGER | |
735 | class. */ | |
efb1c01c | 736 | if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM |
b929c77f | 737 | || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE |
9db13498 | 738 | || code == TYPE_CODE_CHAR |
aa006118 | 739 | || code == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type)) |
efb1c01c | 740 | && (len == 1 || len == 2 || len == 4 || len == 8)) |
fe978cb0 | 741 | theclass[0] = AMD64_INTEGER; |
efb1c01c | 742 | |
0b99a660 FW |
743 | /* Arguments of types _Float16, float, double, _Decimal32, _Decimal64 and |
744 | __m64 are in class SSE. */ | |
5daa78cc | 745 | else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT) |
0b99a660 | 746 | && (len == 2 || len == 4 || len == 8)) |
efb1c01c | 747 | /* FIXME: __m64 . */ |
fe978cb0 | 748 | theclass[0] = AMD64_SSE; |
efb1c01c | 749 | |
5daa78cc TJB |
750 | /* Arguments of types __float128, _Decimal128 and __m128 are split into |
751 | two halves. The least significant ones belong to class SSE, the most | |
efb1c01c | 752 | significant one to class SSEUP. */ |
5daa78cc TJB |
753 | else if (code == TYPE_CODE_DECFLOAT && len == 16) |
754 | /* FIXME: __float128, __m128. */ | |
fe978cb0 | 755 | theclass[0] = AMD64_SSE, theclass[1] = AMD64_SSEUP; |
efb1c01c MK |
756 | |
757 | /* The 64-bit mantissa of arguments of type long double belongs to | |
758 | class X87, the 16-bit exponent plus 6 bytes of padding belongs to | |
759 | class X87UP. */ | |
760 | else if (code == TYPE_CODE_FLT && len == 16) | |
761 | /* Class X87 and X87UP. */ | |
fe978cb0 | 762 | theclass[0] = AMD64_X87, theclass[1] = AMD64_X87UP; |
efb1c01c | 763 | |
0b99a660 FW |
764 | /* Arguments of complex T - where T is one of the types _Float16, float or |
765 | double - get treated as if they are implemented as: | |
7f7930dd MK |
766 | |
767 | struct complexT { | |
768 | T real; | |
769 | T imag; | |
5f52445b YQ |
770 | }; |
771 | ||
772 | */ | |
0b99a660 | 773 | else if (code == TYPE_CODE_COMPLEX && (len == 8 || len == 4)) |
fe978cb0 | 774 | theclass[0] = AMD64_SSE; |
7f7930dd | 775 | else if (code == TYPE_CODE_COMPLEX && len == 16) |
fe978cb0 | 776 | theclass[0] = theclass[1] = AMD64_SSE; |
7f7930dd MK |
777 | |
778 | /* A variable of type complex long double is classified as type | |
779 | COMPLEX_X87. */ | |
780 | else if (code == TYPE_CODE_COMPLEX && len == 32) | |
fe978cb0 | 781 | theclass[0] = AMD64_COMPLEX_X87; |
7f7930dd | 782 | |
efb1c01c MK |
783 | /* Aggregates. */ |
784 | else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT | |
785 | || code == TYPE_CODE_UNION) | |
fe978cb0 | 786 | amd64_classify_aggregate (type, theclass); |
efb1c01c MK |
787 | } |
788 | ||
789 | static enum return_value_convention | |
6a3a010b | 790 | amd64_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 791 | struct type *type, struct regcache *regcache, |
5cb0f2d5 | 792 | struct value **read_value, const gdb_byte *writebuf) |
efb1c01c | 793 | { |
fe978cb0 | 794 | enum amd64_reg_class theclass[2]; |
df86565b | 795 | int len = type->length (); |
90f90721 MK |
796 | static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM }; |
797 | static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM }; | |
efb1c01c MK |
798 | int integer_reg = 0; |
799 | int sse_reg = 0; | |
800 | int i; | |
801 | ||
5cb0f2d5 TT |
802 | gdb_assert (!(read_value && writebuf)); |
803 | ||
efb1c01c | 804 | /* 1. Classify the return type with the classification algorithm. */ |
fe978cb0 | 805 | amd64_classify (type, theclass); |
efb1c01c MK |
806 | |
807 | /* 2. If the type has class MEMORY, then the caller provides space | |
6fa57a7d | 808 | for the return value and passes the address of this storage in |
0963b4bd | 809 | %rdi as if it were the first argument to the function. In effect, |
6fa57a7d MK |
810 | this address becomes a hidden first argument. |
811 | ||
812 | On return %rax will contain the address that has been passed in | |
813 | by the caller in %rdi. */ | |
fe978cb0 | 814 | if (theclass[0] == AMD64_MEMORY) |
6fa57a7d MK |
815 | { |
816 | /* As indicated by the comment above, the ABI guarantees that we | |
dda83cd7 SM |
817 | can always find the return value just after the function has |
818 | returned. */ | |
6fa57a7d | 819 | |
911627e7 | 820 | if (read_value != nullptr) |
6fa57a7d MK |
821 | { |
822 | ULONGEST addr; | |
823 | ||
824 | regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr); | |
911627e7 | 825 | *read_value = value_at_non_lval (type, addr); |
6fa57a7d MK |
826 | } |
827 | ||
828 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
829 | } | |
efb1c01c | 830 | |
911627e7 TT |
831 | gdb_byte *readbuf = nullptr; |
832 | if (read_value != nullptr) | |
833 | { | |
317c3ed9 | 834 | *read_value = value::allocate (type); |
bbe912ba | 835 | readbuf = (*read_value)->contents_raw ().data (); |
911627e7 TT |
836 | } |
837 | ||
7f7930dd | 838 | /* 8. If the class is COMPLEX_X87, the real part of the value is |
dda83cd7 | 839 | returned in %st0 and the imaginary part in %st1. */ |
fe978cb0 | 840 | if (theclass[0] == AMD64_COMPLEX_X87) |
7f7930dd MK |
841 | { |
842 | if (readbuf) | |
843 | { | |
0b883586 SM |
844 | regcache->raw_read (AMD64_ST0_REGNUM, readbuf); |
845 | regcache->raw_read (AMD64_ST1_REGNUM, readbuf + 16); | |
7f7930dd MK |
846 | } |
847 | ||
848 | if (writebuf) | |
849 | { | |
850 | i387_return_value (gdbarch, regcache); | |
10eaee5f SM |
851 | regcache->raw_write (AMD64_ST0_REGNUM, writebuf); |
852 | regcache->raw_write (AMD64_ST1_REGNUM, writebuf + 16); | |
7f7930dd MK |
853 | |
854 | /* Fix up the tag word such that both %st(0) and %st(1) are | |
855 | marked as valid. */ | |
856 | regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff); | |
857 | } | |
858 | ||
859 | return RETURN_VALUE_REGISTER_CONVENTION; | |
860 | } | |
861 | ||
fe978cb0 | 862 | gdb_assert (theclass[1] != AMD64_MEMORY); |
bad43aa5 | 863 | gdb_assert (len <= 16); |
efb1c01c MK |
864 | |
865 | for (i = 0; len > 0; i++, len -= 8) | |
866 | { | |
867 | int regnum = -1; | |
868 | int offset = 0; | |
869 | ||
fe978cb0 | 870 | switch (theclass[i]) |
efb1c01c MK |
871 | { |
872 | case AMD64_INTEGER: | |
873 | /* 3. If the class is INTEGER, the next available register | |
874 | of the sequence %rax, %rdx is used. */ | |
875 | regnum = integer_regnum[integer_reg++]; | |
876 | break; | |
877 | ||
878 | case AMD64_SSE: | |
879 | /* 4. If the class is SSE, the next available SSE register | |
dda83cd7 | 880 | of the sequence %xmm0, %xmm1 is used. */ |
efb1c01c MK |
881 | regnum = sse_regnum[sse_reg++]; |
882 | break; | |
883 | ||
884 | case AMD64_SSEUP: | |
885 | /* 5. If the class is SSEUP, the eightbyte is passed in the | |
886 | upper half of the last used SSE register. */ | |
887 | gdb_assert (sse_reg > 0); | |
888 | regnum = sse_regnum[sse_reg - 1]; | |
889 | offset = 8; | |
890 | break; | |
891 | ||
892 | case AMD64_X87: | |
893 | /* 6. If the class is X87, the value is returned on the X87 | |
dda83cd7 | 894 | stack in %st0 as 80-bit x87 number. */ |
90f90721 | 895 | regnum = AMD64_ST0_REGNUM; |
efb1c01c MK |
896 | if (writebuf) |
897 | i387_return_value (gdbarch, regcache); | |
898 | break; | |
899 | ||
900 | case AMD64_X87UP: | |
901 | /* 7. If the class is X87UP, the value is returned together | |
dda83cd7 | 902 | with the previous X87 value in %st0. */ |
fe978cb0 | 903 | gdb_assert (i > 0 && theclass[0] == AMD64_X87); |
90f90721 | 904 | regnum = AMD64_ST0_REGNUM; |
efb1c01c MK |
905 | offset = 8; |
906 | len = 2; | |
907 | break; | |
908 | ||
909 | case AMD64_NO_CLASS: | |
910 | continue; | |
911 | ||
912 | default: | |
913 | gdb_assert (!"Unexpected register class."); | |
914 | } | |
915 | ||
916 | gdb_assert (regnum != -1); | |
917 | ||
918 | if (readbuf) | |
502fe83e SM |
919 | regcache->raw_read_part (regnum, offset, std::min (len, 8), |
920 | readbuf + i * 8); | |
efb1c01c | 921 | if (writebuf) |
4f0420fd SM |
922 | regcache->raw_write_part (regnum, offset, std::min (len, 8), |
923 | writebuf + i * 8); | |
efb1c01c MK |
924 | } |
925 | ||
926 | return RETURN_VALUE_REGISTER_CONVENTION; | |
53e95fcf JS |
927 | } |
928 | \f | |
929 | ||
720aa428 | 930 | static CORE_ADDR |
cf84fa6b AH |
931 | amd64_push_arguments (struct regcache *regcache, int nargs, struct value **args, |
932 | CORE_ADDR sp, function_call_return_method return_method) | |
720aa428 | 933 | { |
bf4d6c1c JB |
934 | static int integer_regnum[] = |
935 | { | |
936 | AMD64_RDI_REGNUM, /* %rdi */ | |
937 | AMD64_RSI_REGNUM, /* %rsi */ | |
938 | AMD64_RDX_REGNUM, /* %rdx */ | |
939 | AMD64_RCX_REGNUM, /* %rcx */ | |
5b856f36 PM |
940 | AMD64_R8_REGNUM, /* %r8 */ |
941 | AMD64_R9_REGNUM /* %r9 */ | |
bf4d6c1c | 942 | }; |
720aa428 MK |
943 | static int sse_regnum[] = |
944 | { | |
945 | /* %xmm0 ... %xmm7 */ | |
90f90721 MK |
946 | AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, |
947 | AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, | |
948 | AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, | |
949 | AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, | |
720aa428 | 950 | }; |
224c3ddb | 951 | struct value **stack_args = XALLOCAVEC (struct value *, nargs); |
720aa428 MK |
952 | int num_stack_args = 0; |
953 | int num_elements = 0; | |
954 | int element = 0; | |
955 | int integer_reg = 0; | |
956 | int sse_reg = 0; | |
957 | int i; | |
958 | ||
6470d250 | 959 | /* Reserve a register for the "hidden" argument. */ |
cf84fa6b | 960 | if (return_method == return_method_struct) |
6470d250 MK |
961 | integer_reg++; |
962 | ||
720aa428 MK |
963 | for (i = 0; i < nargs; i++) |
964 | { | |
d0c97917 | 965 | struct type *type = args[i]->type (); |
df86565b | 966 | int len = type->length (); |
fe978cb0 | 967 | enum amd64_reg_class theclass[2]; |
720aa428 MK |
968 | int needed_integer_regs = 0; |
969 | int needed_sse_regs = 0; | |
970 | int j; | |
971 | ||
972 | /* Classify argument. */ | |
fe978cb0 | 973 | amd64_classify (type, theclass); |
720aa428 MK |
974 | |
975 | /* Calculate the number of integer and SSE registers needed for | |
dda83cd7 | 976 | this argument. */ |
720aa428 MK |
977 | for (j = 0; j < 2; j++) |
978 | { | |
fe978cb0 | 979 | if (theclass[j] == AMD64_INTEGER) |
720aa428 | 980 | needed_integer_regs++; |
fe978cb0 | 981 | else if (theclass[j] == AMD64_SSE) |
720aa428 MK |
982 | needed_sse_regs++; |
983 | } | |
984 | ||
985 | /* Check whether enough registers are available, and if the | |
dda83cd7 | 986 | argument should be passed in registers at all. */ |
bf4d6c1c | 987 | if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum) |
720aa428 MK |
988 | || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum) |
989 | || (needed_integer_regs == 0 && needed_sse_regs == 0)) | |
990 | { | |
991 | /* The argument will be passed on the stack. */ | |
992 | num_elements += ((len + 7) / 8); | |
849e9755 | 993 | stack_args[num_stack_args++] = args[i]; |
720aa428 MK |
994 | } |
995 | else | |
996 | { | |
997 | /* The argument will be passed in registers. */ | |
efaf1ae0 | 998 | const gdb_byte *valbuf = args[i]->contents ().data (); |
d8de1ef7 | 999 | gdb_byte buf[8]; |
720aa428 MK |
1000 | |
1001 | gdb_assert (len <= 16); | |
1002 | ||
1003 | for (j = 0; len > 0; j++, len -= 8) | |
1004 | { | |
1005 | int regnum = -1; | |
1006 | int offset = 0; | |
1007 | ||
fe978cb0 | 1008 | switch (theclass[j]) |
720aa428 MK |
1009 | { |
1010 | case AMD64_INTEGER: | |
bf4d6c1c | 1011 | regnum = integer_regnum[integer_reg++]; |
720aa428 MK |
1012 | break; |
1013 | ||
1014 | case AMD64_SSE: | |
1015 | regnum = sse_regnum[sse_reg++]; | |
1016 | break; | |
1017 | ||
1018 | case AMD64_SSEUP: | |
1019 | gdb_assert (sse_reg > 0); | |
1020 | regnum = sse_regnum[sse_reg - 1]; | |
1021 | offset = 8; | |
1022 | break; | |
1023 | ||
745ff14e TV |
1024 | case AMD64_NO_CLASS: |
1025 | continue; | |
1026 | ||
720aa428 MK |
1027 | default: |
1028 | gdb_assert (!"Unexpected register class."); | |
1029 | } | |
1030 | ||
1031 | gdb_assert (regnum != -1); | |
1032 | memset (buf, 0, sizeof buf); | |
325fac50 | 1033 | memcpy (buf, valbuf + j * 8, std::min (len, 8)); |
4f0420fd | 1034 | regcache->raw_write_part (regnum, offset, 8, buf); |
720aa428 MK |
1035 | } |
1036 | } | |
1037 | } | |
1038 | ||
1039 | /* Allocate space for the arguments on the stack. */ | |
1040 | sp -= num_elements * 8; | |
1041 | ||
1042 | /* The psABI says that "The end of the input argument area shall be | |
1043 | aligned on a 16 byte boundary." */ | |
1044 | sp &= ~0xf; | |
1045 | ||
1046 | /* Write out the arguments to the stack. */ | |
1047 | for (i = 0; i < num_stack_args; i++) | |
1048 | { | |
d0c97917 | 1049 | struct type *type = stack_args[i]->type (); |
efaf1ae0 | 1050 | const gdb_byte *valbuf = stack_args[i]->contents ().data (); |
df86565b | 1051 | int len = type->length (); |
849e9755 JB |
1052 | |
1053 | write_memory (sp + element * 8, valbuf, len); | |
1054 | element += ((len + 7) / 8); | |
720aa428 MK |
1055 | } |
1056 | ||
1057 | /* The psABI says that "For calls that may call functions that use | |
1058 | varargs or stdargs (prototype-less calls or calls to functions | |
1059 | containing ellipsis (...) in the declaration) %al is used as | |
1060 | hidden argument to specify the number of SSE registers used. */ | |
90f90721 | 1061 | regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg); |
720aa428 MK |
1062 | return sp; |
1063 | } | |
1064 | ||
c4f35dd8 | 1065 | static CORE_ADDR |
7d9b040b | 1066 | amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
e53bef9f MK |
1067 | struct regcache *regcache, CORE_ADDR bp_addr, |
1068 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
1069 | function_call_return_method return_method, |
1070 | CORE_ADDR struct_addr) | |
53e95fcf | 1071 | { |
e17a4113 | 1072 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d8de1ef7 | 1073 | gdb_byte buf[8]; |
c4f35dd8 | 1074 | |
4a612d6f WT |
1075 | /* BND registers can be in arbitrary values at the moment of the |
1076 | inferior call. This can cause boundary violations that are not | |
1077 | due to a real bug or even desired by the user. The best to be done | |
1078 | is set the BND registers to allow access to the whole memory, INIT | |
1079 | state, before pushing the inferior call. */ | |
1080 | i387_reset_bnd_regs (gdbarch, regcache); | |
1081 | ||
c4f35dd8 | 1082 | /* Pass arguments. */ |
cf84fa6b | 1083 | sp = amd64_push_arguments (regcache, nargs, args, sp, return_method); |
c4f35dd8 MK |
1084 | |
1085 | /* Pass "hidden" argument". */ | |
cf84fa6b | 1086 | if (return_method == return_method_struct) |
c4f35dd8 | 1087 | { |
e17a4113 | 1088 | store_unsigned_integer (buf, 8, byte_order, struct_addr); |
b66f5587 | 1089 | regcache->cooked_write (AMD64_RDI_REGNUM, buf); |
c4f35dd8 MK |
1090 | } |
1091 | ||
1092 | /* Store return address. */ | |
1093 | sp -= 8; | |
e17a4113 | 1094 | store_unsigned_integer (buf, 8, byte_order, bp_addr); |
c4f35dd8 MK |
1095 | write_memory (sp, buf, 8); |
1096 | ||
1097 | /* Finally, update the stack pointer... */ | |
e17a4113 | 1098 | store_unsigned_integer (buf, 8, byte_order, sp); |
b66f5587 | 1099 | regcache->cooked_write (AMD64_RSP_REGNUM, buf); |
c4f35dd8 MK |
1100 | |
1101 | /* ...and fake a frame pointer. */ | |
b66f5587 | 1102 | regcache->cooked_write (AMD64_RBP_REGNUM, buf); |
c4f35dd8 | 1103 | |
3e210248 | 1104 | return sp + 16; |
53e95fcf | 1105 | } |
c4f35dd8 | 1106 | \f |
35669430 DE |
1107 | /* Displaced instruction handling. */ |
1108 | ||
1109 | /* A partially decoded instruction. | |
1110 | This contains enough details for displaced stepping purposes. */ | |
1111 | ||
1112 | struct amd64_insn | |
1113 | { | |
1114 | /* The number of opcode bytes. */ | |
1115 | int opcode_len; | |
50a1fdd5 PA |
1116 | /* The offset of the REX/VEX instruction encoding prefix or -1 if |
1117 | not present. */ | |
1118 | int enc_prefix_offset; | |
35669430 DE |
1119 | /* The offset to the first opcode byte. */ |
1120 | int opcode_offset; | |
1121 | /* The offset to the modrm byte or -1 if not present. */ | |
1122 | int modrm_offset; | |
1123 | ||
1124 | /* The raw instruction. */ | |
1125 | gdb_byte *raw_insn; | |
1126 | }; | |
1127 | ||
1152d984 SM |
1128 | struct amd64_displaced_step_copy_insn_closure |
1129 | : public displaced_step_copy_insn_closure | |
35669430 | 1130 | { |
1152d984 | 1131 | amd64_displaced_step_copy_insn_closure (int insn_buf_len) |
cfba9872 SM |
1132 | : insn_buf (insn_buf_len, 0) |
1133 | {} | |
1134 | ||
35669430 | 1135 | /* For rip-relative insns, saved copy of the reg we use instead of %rip. */ |
cfba9872 | 1136 | int tmp_used = 0; |
35669430 DE |
1137 | int tmp_regno; |
1138 | ULONGEST tmp_save; | |
1139 | ||
1140 | /* Details of the instruction. */ | |
1141 | struct amd64_insn insn_details; | |
1142 | ||
cfba9872 SM |
1143 | /* The possibly modified insn. */ |
1144 | gdb::byte_vector insn_buf; | |
35669430 DE |
1145 | }; |
1146 | ||
1147 | /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with | |
1148 | ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative, | |
1149 | at which point delete these in favor of libopcodes' versions). */ | |
1150 | ||
1151 | static const unsigned char onebyte_has_modrm[256] = { | |
1152 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
1153 | /* ------------------------------- */ | |
1154 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
1155 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
1156 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
1157 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
1158 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
1159 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
1160 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
1161 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
1162 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
1163 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
1164 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
1165 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
1166 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
1167 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
1168 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
1169 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
1170 | /* ------------------------------- */ | |
1171 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
1172 | }; | |
1173 | ||
1174 | static const unsigned char twobyte_has_modrm[256] = { | |
1175 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
1176 | /* ------------------------------- */ | |
1177 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ | |
1178 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ | |
1179 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ | |
1180 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ | |
1181 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ | |
1182 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ | |
1183 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
1184 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ | |
1185 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ | |
1186 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
1187 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ | |
1188 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ | |
1189 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ | |
1190 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ | |
1191 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ | |
1192 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ | |
1193 | /* ------------------------------- */ | |
1194 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
1195 | }; | |
1196 | ||
1197 | static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp); | |
1198 | ||
1199 | static int | |
1200 | rex_prefix_p (gdb_byte pfx) | |
1201 | { | |
1202 | return REX_PREFIX_P (pfx); | |
1203 | } | |
1204 | ||
50a1fdd5 PA |
1205 | /* True if PFX is the start of the 2-byte VEX prefix. */ |
1206 | ||
1207 | static bool | |
1208 | vex2_prefix_p (gdb_byte pfx) | |
1209 | { | |
1210 | return pfx == 0xc5; | |
1211 | } | |
1212 | ||
1213 | /* True if PFX is the start of the 3-byte VEX prefix. */ | |
1214 | ||
1215 | static bool | |
1216 | vex3_prefix_p (gdb_byte pfx) | |
1217 | { | |
1218 | return pfx == 0xc4; | |
1219 | } | |
1220 | ||
35669430 DE |
1221 | /* Skip the legacy instruction prefixes in INSN. |
1222 | We assume INSN is properly sentineled so we don't have to worry | |
1223 | about falling off the end of the buffer. */ | |
1224 | ||
1225 | static gdb_byte * | |
1903f0e6 | 1226 | amd64_skip_prefixes (gdb_byte *insn) |
35669430 DE |
1227 | { |
1228 | while (1) | |
1229 | { | |
1230 | switch (*insn) | |
1231 | { | |
1232 | case DATA_PREFIX_OPCODE: | |
1233 | case ADDR_PREFIX_OPCODE: | |
1234 | case CS_PREFIX_OPCODE: | |
1235 | case DS_PREFIX_OPCODE: | |
1236 | case ES_PREFIX_OPCODE: | |
1237 | case FS_PREFIX_OPCODE: | |
1238 | case GS_PREFIX_OPCODE: | |
1239 | case SS_PREFIX_OPCODE: | |
1240 | case LOCK_PREFIX_OPCODE: | |
1241 | case REPE_PREFIX_OPCODE: | |
1242 | case REPNE_PREFIX_OPCODE: | |
1243 | ++insn; | |
1244 | continue; | |
1245 | default: | |
1246 | break; | |
1247 | } | |
1248 | break; | |
1249 | } | |
1250 | ||
1251 | return insn; | |
1252 | } | |
1253 | ||
35669430 DE |
1254 | /* Return an integer register (other than RSP) that is unused as an input |
1255 | operand in INSN. | |
1256 | In order to not require adding a rex prefix if the insn doesn't already | |
1257 | have one, the result is restricted to RAX ... RDI, sans RSP. | |
1258 | The register numbering of the result follows architecture ordering, | |
1259 | e.g. RDI = 7. */ | |
1260 | ||
1261 | static int | |
1262 | amd64_get_unused_input_int_reg (const struct amd64_insn *details) | |
1263 | { | |
1264 | /* 1 bit for each reg */ | |
1265 | int used_regs_mask = 0; | |
1266 | ||
1267 | /* There can be at most 3 int regs used as inputs in an insn, and we have | |
1268 | 7 to choose from (RAX ... RDI, sans RSP). | |
1269 | This allows us to take a conservative approach and keep things simple. | |
1270 | E.g. By avoiding RAX, we don't have to specifically watch for opcodes | |
1271 | that implicitly specify RAX. */ | |
1272 | ||
1273 | /* Avoid RAX. */ | |
1274 | used_regs_mask |= 1 << EAX_REG_NUM; | |
1275 | /* Similarily avoid RDX, implicit operand in divides. */ | |
1276 | used_regs_mask |= 1 << EDX_REG_NUM; | |
1277 | /* Avoid RSP. */ | |
1278 | used_regs_mask |= 1 << ESP_REG_NUM; | |
1279 | ||
1280 | /* If the opcode is one byte long and there's no ModRM byte, | |
1281 | assume the opcode specifies a register. */ | |
1282 | if (details->opcode_len == 1 && details->modrm_offset == -1) | |
1283 | used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7); | |
1284 | ||
1285 | /* Mark used regs in the modrm/sib bytes. */ | |
1286 | if (details->modrm_offset != -1) | |
1287 | { | |
1288 | int modrm = details->raw_insn[details->modrm_offset]; | |
1289 | int mod = MODRM_MOD_FIELD (modrm); | |
1290 | int reg = MODRM_REG_FIELD (modrm); | |
1291 | int rm = MODRM_RM_FIELD (modrm); | |
1292 | int have_sib = mod != 3 && rm == 4; | |
1293 | ||
1294 | /* Assume the reg field of the modrm byte specifies a register. */ | |
1295 | used_regs_mask |= 1 << reg; | |
1296 | ||
1297 | if (have_sib) | |
1298 | { | |
1299 | int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]); | |
d48ebb5b | 1300 | int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]); |
35669430 | 1301 | used_regs_mask |= 1 << base; |
d48ebb5b | 1302 | used_regs_mask |= 1 << idx; |
35669430 DE |
1303 | } |
1304 | else | |
1305 | { | |
1306 | used_regs_mask |= 1 << rm; | |
1307 | } | |
1308 | } | |
1309 | ||
1310 | gdb_assert (used_regs_mask < 256); | |
1311 | gdb_assert (used_regs_mask != 255); | |
1312 | ||
1313 | /* Finally, find a free reg. */ | |
1314 | { | |
1315 | int i; | |
1316 | ||
1317 | for (i = 0; i < 8; ++i) | |
1318 | { | |
1319 | if (! (used_regs_mask & (1 << i))) | |
1320 | return i; | |
1321 | } | |
1322 | ||
1323 | /* We shouldn't get here. */ | |
f34652de | 1324 | internal_error (_("unable to find free reg")); |
35669430 DE |
1325 | } |
1326 | } | |
1327 | ||
1328 | /* Extract the details of INSN that we need. */ | |
1329 | ||
1330 | static void | |
1331 | amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details) | |
1332 | { | |
1333 | gdb_byte *start = insn; | |
1334 | int need_modrm; | |
1335 | ||
1336 | details->raw_insn = insn; | |
1337 | ||
1338 | details->opcode_len = -1; | |
50a1fdd5 | 1339 | details->enc_prefix_offset = -1; |
35669430 DE |
1340 | details->opcode_offset = -1; |
1341 | details->modrm_offset = -1; | |
1342 | ||
1343 | /* Skip legacy instruction prefixes. */ | |
1903f0e6 | 1344 | insn = amd64_skip_prefixes (insn); |
35669430 | 1345 | |
50a1fdd5 | 1346 | /* Skip REX/VEX instruction encoding prefixes. */ |
35669430 DE |
1347 | if (rex_prefix_p (*insn)) |
1348 | { | |
50a1fdd5 | 1349 | details->enc_prefix_offset = insn - start; |
35669430 DE |
1350 | ++insn; |
1351 | } | |
50a1fdd5 PA |
1352 | else if (vex2_prefix_p (*insn)) |
1353 | { | |
1354 | /* Don't record the offset in this case because this prefix has | |
1355 | no REX.B equivalent. */ | |
1356 | insn += 2; | |
1357 | } | |
1358 | else if (vex3_prefix_p (*insn)) | |
1359 | { | |
1360 | details->enc_prefix_offset = insn - start; | |
1361 | insn += 3; | |
1362 | } | |
35669430 DE |
1363 | |
1364 | details->opcode_offset = insn - start; | |
1365 | ||
1366 | if (*insn == TWO_BYTE_OPCODE_ESCAPE) | |
1367 | { | |
1368 | /* Two or three-byte opcode. */ | |
1369 | ++insn; | |
1370 | need_modrm = twobyte_has_modrm[*insn]; | |
1371 | ||
1372 | /* Check for three-byte opcode. */ | |
1903f0e6 | 1373 | switch (*insn) |
35669430 | 1374 | { |
1903f0e6 DE |
1375 | case 0x24: |
1376 | case 0x25: | |
1377 | case 0x38: | |
1378 | case 0x3a: | |
1379 | case 0x7a: | |
1380 | case 0x7b: | |
35669430 DE |
1381 | ++insn; |
1382 | details->opcode_len = 3; | |
1903f0e6 DE |
1383 | break; |
1384 | default: | |
1385 | details->opcode_len = 2; | |
1386 | break; | |
35669430 | 1387 | } |
35669430 DE |
1388 | } |
1389 | else | |
1390 | { | |
1391 | /* One-byte opcode. */ | |
1392 | need_modrm = onebyte_has_modrm[*insn]; | |
1393 | details->opcode_len = 1; | |
1394 | } | |
1395 | ||
1396 | if (need_modrm) | |
1397 | { | |
1398 | ++insn; | |
1399 | details->modrm_offset = insn - start; | |
1400 | } | |
1401 | } | |
1402 | ||
1403 | /* Update %rip-relative addressing in INSN. | |
1404 | ||
1405 | %rip-relative addressing only uses a 32-bit displacement. | |
1406 | 32 bits is not enough to be guaranteed to cover the distance between where | |
1407 | the real instruction is and where its copy is. | |
1408 | Convert the insn to use base+disp addressing. | |
1409 | We set base = pc + insn_length so we can leave disp unchanged. */ | |
c4f35dd8 | 1410 | |
35669430 | 1411 | static void |
1152d984 SM |
1412 | fixup_riprel (struct gdbarch *gdbarch, |
1413 | amd64_displaced_step_copy_insn_closure *dsc, | |
35669430 DE |
1414 | CORE_ADDR from, CORE_ADDR to, struct regcache *regs) |
1415 | { | |
1416 | const struct amd64_insn *insn_details = &dsc->insn_details; | |
1417 | int modrm_offset = insn_details->modrm_offset; | |
35669430 | 1418 | CORE_ADDR rip_base; |
35669430 DE |
1419 | int insn_length; |
1420 | int arch_tmp_regno, tmp_regno; | |
1421 | ULONGEST orig_value; | |
1422 | ||
35669430 | 1423 | /* Compute the rip-relative address. */ |
cfba9872 SM |
1424 | insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf.data (), |
1425 | dsc->insn_buf.size (), from); | |
35669430 DE |
1426 | rip_base = from + insn_length; |
1427 | ||
1428 | /* We need a register to hold the address. | |
1429 | Pick one not used in the insn. | |
1430 | NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */ | |
1431 | arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details); | |
1432 | tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno); | |
1433 | ||
50a1fdd5 PA |
1434 | /* Position of the not-B bit in the 3-byte VEX prefix (in byte 1). */ |
1435 | static constexpr gdb_byte VEX3_NOT_B = 0x20; | |
1436 | ||
1437 | /* REX.B should be unset (VEX.!B set) as we were using rip-relative | |
1438 | addressing, but ensure it's unset (set for VEX) anyway, tmp_regno | |
1439 | is not r8-r15. */ | |
1440 | if (insn_details->enc_prefix_offset != -1) | |
1441 | { | |
1442 | gdb_byte *pfx = &dsc->insn_buf[insn_details->enc_prefix_offset]; | |
1443 | if (rex_prefix_p (pfx[0])) | |
1444 | pfx[0] &= ~REX_B; | |
1445 | else if (vex3_prefix_p (pfx[0])) | |
1446 | pfx[1] |= VEX3_NOT_B; | |
1447 | else | |
1448 | gdb_assert_not_reached ("unhandled prefix"); | |
1449 | } | |
35669430 DE |
1450 | |
1451 | regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value); | |
1452 | dsc->tmp_regno = tmp_regno; | |
1453 | dsc->tmp_save = orig_value; | |
1454 | dsc->tmp_used = 1; | |
1455 | ||
1456 | /* Convert the ModRM field to be base+disp. */ | |
1457 | dsc->insn_buf[modrm_offset] &= ~0xc7; | |
1458 | dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno; | |
1459 | ||
1460 | regcache_cooked_write_unsigned (regs, tmp_regno, rip_base); | |
1461 | ||
136821d9 SM |
1462 | displaced_debug_printf ("%%rip-relative addressing used."); |
1463 | displaced_debug_printf ("using temp reg %d, old value %s, new value %s", | |
1464 | dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save), | |
1465 | paddress (gdbarch, rip_base)); | |
35669430 DE |
1466 | } |
1467 | ||
1468 | static void | |
1469 | fixup_displaced_copy (struct gdbarch *gdbarch, | |
1152d984 | 1470 | amd64_displaced_step_copy_insn_closure *dsc, |
35669430 DE |
1471 | CORE_ADDR from, CORE_ADDR to, struct regcache *regs) |
1472 | { | |
1473 | const struct amd64_insn *details = &dsc->insn_details; | |
1474 | ||
1475 | if (details->modrm_offset != -1) | |
1476 | { | |
1477 | gdb_byte modrm = details->raw_insn[details->modrm_offset]; | |
1478 | ||
1479 | if ((modrm & 0xc7) == 0x05) | |
1480 | { | |
1481 | /* The insn uses rip-relative addressing. | |
1482 | Deal with it. */ | |
1483 | fixup_riprel (gdbarch, dsc, from, to, regs); | |
1484 | } | |
1485 | } | |
1486 | } | |
1487 | ||
1152d984 | 1488 | displaced_step_copy_insn_closure_up |
35669430 DE |
1489 | amd64_displaced_step_copy_insn (struct gdbarch *gdbarch, |
1490 | CORE_ADDR from, CORE_ADDR to, | |
1491 | struct regcache *regs) | |
1492 | { | |
1493 | int len = gdbarch_max_insn_length (gdbarch); | |
741e63d7 | 1494 | /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to |
35669430 DE |
1495 | continually watch for running off the end of the buffer. */ |
1496 | int fixup_sentinel_space = len; | |
1152d984 SM |
1497 | std::unique_ptr<amd64_displaced_step_copy_insn_closure> dsc |
1498 | (new amd64_displaced_step_copy_insn_closure (len + fixup_sentinel_space)); | |
35669430 DE |
1499 | gdb_byte *buf = &dsc->insn_buf[0]; |
1500 | struct amd64_insn *details = &dsc->insn_details; | |
1501 | ||
35669430 DE |
1502 | read_memory (from, buf, len); |
1503 | ||
1504 | /* Set up the sentinel space so we don't have to worry about running | |
1505 | off the end of the buffer. An excessive number of leading prefixes | |
1506 | could otherwise cause this. */ | |
1507 | memset (buf + len, 0, fixup_sentinel_space); | |
1508 | ||
1509 | amd64_get_insn_details (buf, details); | |
1510 | ||
1511 | /* GDB may get control back after the insn after the syscall. | |
1512 | Presumably this is a kernel bug. | |
1513 | If this is a syscall, make sure there's a nop afterwards. */ | |
1514 | { | |
1515 | int syscall_length; | |
1516 | ||
1517 | if (amd64_syscall_p (details, &syscall_length)) | |
1518 | buf[details->opcode_offset + syscall_length] = NOP_OPCODE; | |
1519 | } | |
1520 | ||
1521 | /* Modify the insn to cope with the address where it will be executed from. | |
1522 | In particular, handle any rip-relative addressing. */ | |
e8217e61 | 1523 | fixup_displaced_copy (gdbarch, dsc.get (), from, to, regs); |
35669430 DE |
1524 | |
1525 | write_memory (to, buf, len); | |
1526 | ||
136821d9 SM |
1527 | displaced_debug_printf ("copy %s->%s: %s", |
1528 | paddress (gdbarch, from), paddress (gdbarch, to), | |
a6e5abae | 1529 | bytes_to_string (buf, len).c_str ()); |
35669430 | 1530 | |
6d0cf446 | 1531 | /* This is a work around for a problem with g++ 4.8. */ |
1152d984 | 1532 | return displaced_step_copy_insn_closure_up (dsc.release ()); |
35669430 DE |
1533 | } |
1534 | ||
1535 | static int | |
1536 | amd64_absolute_jmp_p (const struct amd64_insn *details) | |
1537 | { | |
1538 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; | |
1539 | ||
1540 | if (insn[0] == 0xff) | |
1541 | { | |
1542 | /* jump near, absolute indirect (/4) */ | |
1543 | if ((insn[1] & 0x38) == 0x20) | |
1544 | return 1; | |
1545 | ||
1546 | /* jump far, absolute indirect (/5) */ | |
1547 | if ((insn[1] & 0x38) == 0x28) | |
1548 | return 1; | |
1549 | } | |
1550 | ||
1551 | return 0; | |
1552 | } | |
1553 | ||
c2170eef MM |
1554 | /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */ |
1555 | ||
1556 | static int | |
1557 | amd64_jmp_p (const struct amd64_insn *details) | |
1558 | { | |
1559 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; | |
1560 | ||
1561 | /* jump short, relative. */ | |
1562 | if (insn[0] == 0xeb) | |
1563 | return 1; | |
1564 | ||
1565 | /* jump near, relative. */ | |
1566 | if (insn[0] == 0xe9) | |
1567 | return 1; | |
1568 | ||
1569 | return amd64_absolute_jmp_p (details); | |
1570 | } | |
1571 | ||
35669430 DE |
1572 | static int |
1573 | amd64_absolute_call_p (const struct amd64_insn *details) | |
1574 | { | |
1575 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; | |
1576 | ||
1577 | if (insn[0] == 0xff) | |
1578 | { | |
1579 | /* Call near, absolute indirect (/2) */ | |
1580 | if ((insn[1] & 0x38) == 0x10) | |
1581 | return 1; | |
1582 | ||
1583 | /* Call far, absolute indirect (/3) */ | |
1584 | if ((insn[1] & 0x38) == 0x18) | |
1585 | return 1; | |
1586 | } | |
1587 | ||
1588 | return 0; | |
1589 | } | |
1590 | ||
1591 | static int | |
1592 | amd64_ret_p (const struct amd64_insn *details) | |
1593 | { | |
1594 | /* NOTE: gcc can emit "repz ; ret". */ | |
1595 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; | |
1596 | ||
1597 | switch (insn[0]) | |
1598 | { | |
1599 | case 0xc2: /* ret near, pop N bytes */ | |
1600 | case 0xc3: /* ret near */ | |
1601 | case 0xca: /* ret far, pop N bytes */ | |
1602 | case 0xcb: /* ret far */ | |
1603 | case 0xcf: /* iret */ | |
1604 | return 1; | |
1605 | ||
1606 | default: | |
1607 | return 0; | |
1608 | } | |
1609 | } | |
1610 | ||
1611 | static int | |
1612 | amd64_call_p (const struct amd64_insn *details) | |
1613 | { | |
1614 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; | |
1615 | ||
1616 | if (amd64_absolute_call_p (details)) | |
1617 | return 1; | |
1618 | ||
1619 | /* call near, relative */ | |
1620 | if (insn[0] == 0xe8) | |
1621 | return 1; | |
1622 | ||
1623 | return 0; | |
1624 | } | |
1625 | ||
35669430 DE |
1626 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
1627 | length in bytes. Otherwise, return zero. */ | |
1628 | ||
1629 | static int | |
1630 | amd64_syscall_p (const struct amd64_insn *details, int *lengthp) | |
1631 | { | |
1632 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; | |
1633 | ||
1634 | if (insn[0] == 0x0f && insn[1] == 0x05) | |
1635 | { | |
1636 | *lengthp = 2; | |
1637 | return 1; | |
1638 | } | |
1639 | ||
1640 | return 0; | |
1641 | } | |
1642 | ||
c2170eef MM |
1643 | /* Classify the instruction at ADDR using PRED. |
1644 | Throw an error if the memory can't be read. */ | |
1645 | ||
1646 | static int | |
1647 | amd64_classify_insn_at (struct gdbarch *gdbarch, CORE_ADDR addr, | |
1648 | int (*pred) (const struct amd64_insn *)) | |
1649 | { | |
1650 | struct amd64_insn details; | |
c2170eef | 1651 | |
83750264 | 1652 | gdb::byte_vector buf (gdbarch_max_insn_length (gdbarch)); |
c2170eef | 1653 | |
83750264 AB |
1654 | read_code (addr, buf.data (), buf.size ()); |
1655 | amd64_get_insn_details (buf.data (), &details); | |
c2170eef | 1656 | |
83750264 | 1657 | int classification = pred (&details); |
c2170eef MM |
1658 | |
1659 | return classification; | |
1660 | } | |
1661 | ||
1662 | /* The gdbarch insn_is_call method. */ | |
1663 | ||
1664 | static int | |
1665 | amd64_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1666 | { | |
1667 | return amd64_classify_insn_at (gdbarch, addr, amd64_call_p); | |
1668 | } | |
1669 | ||
1670 | /* The gdbarch insn_is_ret method. */ | |
1671 | ||
1672 | static int | |
1673 | amd64_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1674 | { | |
1675 | return amd64_classify_insn_at (gdbarch, addr, amd64_ret_p); | |
1676 | } | |
1677 | ||
1678 | /* The gdbarch insn_is_jump method. */ | |
1679 | ||
1680 | static int | |
1681 | amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1682 | { | |
1683 | return amd64_classify_insn_at (gdbarch, addr, amd64_jmp_p); | |
1684 | } | |
1685 | ||
35669430 DE |
1686 | /* Fix up the state of registers and memory after having single-stepped |
1687 | a displaced instruction. */ | |
1688 | ||
1689 | void | |
1690 | amd64_displaced_step_fixup (struct gdbarch *gdbarch, | |
1152d984 | 1691 | struct displaced_step_copy_insn_closure *dsc_, |
35669430 | 1692 | CORE_ADDR from, CORE_ADDR to, |
cf141dd8 | 1693 | struct regcache *regs, bool completed_p) |
35669430 | 1694 | { |
1152d984 SM |
1695 | amd64_displaced_step_copy_insn_closure *dsc |
1696 | = (amd64_displaced_step_copy_insn_closure *) dsc_; | |
e17a4113 | 1697 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
35669430 DE |
1698 | /* The offset we applied to the instruction's address. */ |
1699 | ULONGEST insn_offset = to - from; | |
cfba9872 | 1700 | gdb_byte *insn = dsc->insn_buf.data (); |
35669430 DE |
1701 | const struct amd64_insn *insn_details = &dsc->insn_details; |
1702 | ||
136821d9 SM |
1703 | displaced_debug_printf ("fixup (%s, %s), insn = 0x%02x 0x%02x ...", |
1704 | paddress (gdbarch, from), paddress (gdbarch, to), | |
1705 | insn[0], insn[1]); | |
35669430 DE |
1706 | |
1707 | /* If we used a tmp reg, restore it. */ | |
1708 | ||
1709 | if (dsc->tmp_used) | |
1710 | { | |
136821d9 SM |
1711 | displaced_debug_printf ("restoring reg %d to %s", |
1712 | dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save)); | |
35669430 DE |
1713 | regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save); |
1714 | } | |
1715 | ||
1716 | /* The list of issues to contend with here is taken from | |
1717 | resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28. | |
1718 | Yay for Free Software! */ | |
1719 | ||
1720 | /* Relocate the %rip back to the program's instruction stream, | |
1721 | if necessary. */ | |
1722 | ||
1723 | /* Except in the case of absolute or indirect jump or call | |
1724 | instructions, or a return instruction, the new rip is relative to | |
1725 | the displaced instruction; make it relative to the original insn. | |
1726 | Well, signal handler returns don't need relocation either, but we use the | |
1727 | value of %rip to recognize those; see below. */ | |
cf141dd8 AB |
1728 | if (!completed_p |
1729 | || (!amd64_absolute_jmp_p (insn_details) | |
1730 | && !amd64_absolute_call_p (insn_details) | |
1731 | && !amd64_ret_p (insn_details))) | |
35669430 | 1732 | { |
35669430 DE |
1733 | int insn_len; |
1734 | ||
cf141dd8 | 1735 | CORE_ADDR pc = regcache_read_pc (regs); |
35669430 DE |
1736 | |
1737 | /* A signal trampoline system call changes the %rip, resuming | |
1738 | execution of the main program after the signal handler has | |
1739 | returned. That makes them like 'return' instructions; we | |
1740 | shouldn't relocate %rip. | |
1741 | ||
1742 | But most system calls don't, and we do need to relocate %rip. | |
1743 | ||
1744 | Our heuristic for distinguishing these cases: if stepping | |
1745 | over the system call instruction left control directly after | |
1746 | the instruction, the we relocate --- control almost certainly | |
1747 | doesn't belong in the displaced copy. Otherwise, we assume | |
1748 | the instruction has put control where it belongs, and leave | |
1749 | it unrelocated. Goodness help us if there are PC-relative | |
1750 | system calls. */ | |
1751 | if (amd64_syscall_p (insn_details, &insn_len) | |
35669430 | 1752 | /* GDB can get control back after the insn after the syscall. |
cf141dd8 AB |
1753 | Presumably this is a kernel bug. Fixup ensures its a nop, we |
1754 | add one to the length for it. */ | |
1755 | && (pc < to || pc > (to + insn_len + 1))) | |
136821d9 | 1756 | displaced_debug_printf ("syscall changed %%rip; not relocating"); |
35669430 DE |
1757 | else |
1758 | { | |
cf141dd8 | 1759 | CORE_ADDR rip = pc - insn_offset; |
35669430 | 1760 | |
1903f0e6 DE |
1761 | /* If we just stepped over a breakpoint insn, we don't backup |
1762 | the pc on purpose; this is to match behaviour without | |
1763 | stepping. */ | |
35669430 | 1764 | |
cf141dd8 | 1765 | regcache_write_pc (regs, rip); |
35669430 | 1766 | |
136821d9 | 1767 | displaced_debug_printf ("relocated %%rip from %s to %s", |
cf141dd8 | 1768 | paddress (gdbarch, pc), |
136821d9 | 1769 | paddress (gdbarch, rip)); |
35669430 DE |
1770 | } |
1771 | } | |
1772 | ||
1773 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
1774 | pushed value, and should be cleared. We'll leave this for later, | |
1775 | since GDB already messes up the TF flag when stepping over a | |
1776 | pushfl. */ | |
1777 | ||
1778 | /* If the instruction was a call, the return address now atop the | |
1779 | stack is the address following the copied instruction. We need | |
1780 | to make it the address following the original instruction. */ | |
cf141dd8 | 1781 | if (completed_p && amd64_call_p (insn_details)) |
35669430 DE |
1782 | { |
1783 | ULONGEST rsp; | |
1784 | ULONGEST retaddr; | |
1785 | const ULONGEST retaddr_len = 8; | |
1786 | ||
1787 | regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp); | |
e17a4113 | 1788 | retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order); |
4dafcdeb | 1789 | retaddr = (retaddr - insn_offset) & 0xffffffffffffffffULL; |
e17a4113 | 1790 | write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr); |
35669430 | 1791 | |
136821d9 SM |
1792 | displaced_debug_printf ("relocated return addr at %s to %s", |
1793 | paddress (gdbarch, rsp), | |
1794 | paddress (gdbarch, retaddr)); | |
35669430 DE |
1795 | } |
1796 | } | |
dde08ee1 PA |
1797 | |
1798 | /* If the instruction INSN uses RIP-relative addressing, return the | |
1799 | offset into the raw INSN where the displacement to be adjusted is | |
1800 | found. Returns 0 if the instruction doesn't use RIP-relative | |
1801 | addressing. */ | |
1802 | ||
1803 | static int | |
1804 | rip_relative_offset (struct amd64_insn *insn) | |
1805 | { | |
1806 | if (insn->modrm_offset != -1) | |
1807 | { | |
1808 | gdb_byte modrm = insn->raw_insn[insn->modrm_offset]; | |
1809 | ||
1810 | if ((modrm & 0xc7) == 0x05) | |
1811 | { | |
1812 | /* The displacement is found right after the ModRM byte. */ | |
1813 | return insn->modrm_offset + 1; | |
1814 | } | |
1815 | } | |
1816 | ||
1817 | return 0; | |
1818 | } | |
1819 | ||
1820 | static void | |
1821 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
1822 | { | |
1823 | target_write_memory (*to, buf, len); | |
1824 | *to += len; | |
1825 | } | |
1826 | ||
60965737 | 1827 | static void |
dde08ee1 PA |
1828 | amd64_relocate_instruction (struct gdbarch *gdbarch, |
1829 | CORE_ADDR *to, CORE_ADDR oldloc) | |
1830 | { | |
1831 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1832 | int len = gdbarch_max_insn_length (gdbarch); | |
1833 | /* Extra space for sentinels. */ | |
1834 | int fixup_sentinel_space = len; | |
83750264 | 1835 | gdb::byte_vector buf (len + fixup_sentinel_space); |
dde08ee1 PA |
1836 | struct amd64_insn insn_details; |
1837 | int offset = 0; | |
1838 | LONGEST rel32, newrel; | |
1839 | gdb_byte *insn; | |
1840 | int insn_length; | |
1841 | ||
83750264 | 1842 | read_memory (oldloc, buf.data (), len); |
dde08ee1 PA |
1843 | |
1844 | /* Set up the sentinel space so we don't have to worry about running | |
1845 | off the end of the buffer. An excessive number of leading prefixes | |
1846 | could otherwise cause this. */ | |
83750264 | 1847 | memset (buf.data () + len, 0, fixup_sentinel_space); |
dde08ee1 | 1848 | |
83750264 | 1849 | insn = buf.data (); |
dde08ee1 PA |
1850 | amd64_get_insn_details (insn, &insn_details); |
1851 | ||
1852 | insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc); | |
1853 | ||
1854 | /* Skip legacy instruction prefixes. */ | |
1855 | insn = amd64_skip_prefixes (insn); | |
1856 | ||
1857 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
1858 | the address pushed being the location where the original call in | |
1859 | the user program would return to. */ | |
1860 | if (insn[0] == 0xe8) | |
1861 | { | |
f077e978 PA |
1862 | gdb_byte push_buf[32]; |
1863 | CORE_ADDR ret_addr; | |
1864 | int i = 0; | |
dde08ee1 PA |
1865 | |
1866 | /* Where "ret" in the original code will return to. */ | |
1867 | ret_addr = oldloc + insn_length; | |
f077e978 PA |
1868 | |
1869 | /* If pushing an address higher than or equal to 0x80000000, | |
1870 | avoid 'pushq', as that sign extends its 32-bit operand, which | |
1871 | would be incorrect. */ | |
1872 | if (ret_addr <= 0x7fffffff) | |
1873 | { | |
1874 | push_buf[0] = 0x68; /* pushq $... */ | |
1875 | store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); | |
1876 | i = 5; | |
1877 | } | |
1878 | else | |
1879 | { | |
1880 | push_buf[i++] = 0x48; /* sub $0x8,%rsp */ | |
1881 | push_buf[i++] = 0x83; | |
1882 | push_buf[i++] = 0xec; | |
1883 | push_buf[i++] = 0x08; | |
1884 | ||
1885 | push_buf[i++] = 0xc7; /* movl $imm,(%rsp) */ | |
1886 | push_buf[i++] = 0x04; | |
1887 | push_buf[i++] = 0x24; | |
1888 | store_unsigned_integer (&push_buf[i], 4, byte_order, | |
1889 | ret_addr & 0xffffffff); | |
1890 | i += 4; | |
1891 | ||
1892 | push_buf[i++] = 0xc7; /* movl $imm,4(%rsp) */ | |
1893 | push_buf[i++] = 0x44; | |
1894 | push_buf[i++] = 0x24; | |
1895 | push_buf[i++] = 0x04; | |
1896 | store_unsigned_integer (&push_buf[i], 4, byte_order, | |
1897 | ret_addr >> 32); | |
1898 | i += 4; | |
1899 | } | |
1900 | gdb_assert (i <= sizeof (push_buf)); | |
dde08ee1 | 1901 | /* Push the push. */ |
f077e978 | 1902 | append_insns (to, i, push_buf); |
dde08ee1 PA |
1903 | |
1904 | /* Convert the relative call to a relative jump. */ | |
1905 | insn[0] = 0xe9; | |
1906 | ||
1907 | /* Adjust the destination offset. */ | |
1908 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
1909 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
1910 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
1911 | ||
136821d9 SM |
1912 | displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s", |
1913 | hex_string (rel32), paddress (gdbarch, oldloc), | |
1914 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
1915 | |
1916 | /* Write the adjusted jump into its displaced location. */ | |
1917 | append_insns (to, 5, insn); | |
1918 | return; | |
1919 | } | |
1920 | ||
1921 | offset = rip_relative_offset (&insn_details); | |
1922 | if (!offset) | |
1923 | { | |
1924 | /* Adjust jumps with 32-bit relative addresses. Calls are | |
1925 | already handled above. */ | |
1926 | if (insn[0] == 0xe9) | |
1927 | offset = 1; | |
1928 | /* Adjust conditional jumps. */ | |
1929 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
1930 | offset = 2; | |
1931 | } | |
1932 | ||
1933 | if (offset) | |
1934 | { | |
1935 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
1936 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 1937 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
136821d9 SM |
1938 | displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s", |
1939 | hex_string (rel32), paddress (gdbarch, oldloc), | |
1940 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
1941 | } |
1942 | ||
1943 | /* Write the adjusted instruction into its displaced location. */ | |
83750264 | 1944 | append_insns (to, insn_length, buf.data ()); |
dde08ee1 PA |
1945 | } |
1946 | ||
35669430 | 1947 | \f |
c4f35dd8 | 1948 | /* The maximum number of saved registers. This should include %rip. */ |
90f90721 | 1949 | #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS |
c4f35dd8 | 1950 | |
e53bef9f | 1951 | struct amd64_frame_cache |
c4f35dd8 MK |
1952 | { |
1953 | /* Base address. */ | |
1954 | CORE_ADDR base; | |
8fbca658 | 1955 | int base_p; |
c4f35dd8 MK |
1956 | CORE_ADDR sp_offset; |
1957 | CORE_ADDR pc; | |
1958 | ||
1959 | /* Saved registers. */ | |
e53bef9f | 1960 | CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS]; |
c4f35dd8 | 1961 | CORE_ADDR saved_sp; |
e0c62198 | 1962 | int saved_sp_reg; |
c4f35dd8 MK |
1963 | |
1964 | /* Do we have a frame? */ | |
1965 | int frameless_p; | |
1966 | }; | |
8dda9770 | 1967 | |
d2449ee8 | 1968 | /* Initialize a frame cache. */ |
c4f35dd8 | 1969 | |
d2449ee8 DJ |
1970 | static void |
1971 | amd64_init_frame_cache (struct amd64_frame_cache *cache) | |
8dda9770 | 1972 | { |
c4f35dd8 MK |
1973 | int i; |
1974 | ||
c4f35dd8 MK |
1975 | /* Base address. */ |
1976 | cache->base = 0; | |
8fbca658 | 1977 | cache->base_p = 0; |
c4f35dd8 MK |
1978 | cache->sp_offset = -8; |
1979 | cache->pc = 0; | |
1980 | ||
1981 | /* Saved registers. We initialize these to -1 since zero is a valid | |
bba66b87 DE |
1982 | offset (that's where %rbp is supposed to be stored). |
1983 | The values start out as being offsets, and are later converted to | |
1984 | addresses (at which point -1 is interpreted as an address, still meaning | |
1985 | "invalid"). */ | |
e53bef9f | 1986 | for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) |
c4f35dd8 MK |
1987 | cache->saved_regs[i] = -1; |
1988 | cache->saved_sp = 0; | |
e0c62198 | 1989 | cache->saved_sp_reg = -1; |
c4f35dd8 MK |
1990 | |
1991 | /* Frameless until proven otherwise. */ | |
1992 | cache->frameless_p = 1; | |
d2449ee8 | 1993 | } |
c4f35dd8 | 1994 | |
d2449ee8 DJ |
1995 | /* Allocate and initialize a frame cache. */ |
1996 | ||
1997 | static struct amd64_frame_cache * | |
1998 | amd64_alloc_frame_cache (void) | |
1999 | { | |
2000 | struct amd64_frame_cache *cache; | |
2001 | ||
2002 | cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache); | |
2003 | amd64_init_frame_cache (cache); | |
c4f35dd8 | 2004 | return cache; |
8dda9770 | 2005 | } |
53e95fcf | 2006 | |
e0c62198 L |
2007 | /* GCC 4.4 and later, can put code in the prologue to realign the |
2008 | stack pointer. Check whether PC points to such code, and update | |
2009 | CACHE accordingly. Return the first instruction after the code | |
2010 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
2011 | recognize the code, return PC. */ | |
2012 | ||
2013 | static CORE_ADDR | |
2014 | amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
2015 | struct amd64_frame_cache *cache) | |
2016 | { | |
2017 | /* There are 2 code sequences to re-align stack before the frame | |
2018 | gets set up: | |
2019 | ||
2020 | 1. Use a caller-saved saved register: | |
2021 | ||
2022 | leaq 8(%rsp), %reg | |
2023 | andq $-XXX, %rsp | |
2024 | pushq -8(%reg) | |
2025 | ||
2026 | 2. Use a callee-saved saved register: | |
2027 | ||
2028 | pushq %reg | |
2029 | leaq 16(%rsp), %reg | |
2030 | andq $-XXX, %rsp | |
2031 | pushq -8(%reg) | |
2032 | ||
2033 | "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes: | |
2034 | ||
24b21115 SM |
2035 | 0x48 0x83 0xe4 0xf0 andq $-16, %rsp |
2036 | 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp | |
e0c62198 L |
2037 | */ |
2038 | ||
2039 | gdb_byte buf[18]; | |
2040 | int reg, r; | |
2041 | int offset, offset_and; | |
e0c62198 | 2042 | |
bae8a07a | 2043 | if (target_read_code (pc, buf, sizeof buf)) |
e0c62198 L |
2044 | return pc; |
2045 | ||
2046 | /* Check caller-saved saved register. The first instruction has | |
2047 | to be "leaq 8(%rsp), %reg". */ | |
2048 | if ((buf[0] & 0xfb) == 0x48 | |
2049 | && buf[1] == 0x8d | |
2050 | && buf[3] == 0x24 | |
2051 | && buf[4] == 0x8) | |
2052 | { | |
2053 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
2054 | if ((buf[2] & 0xc7) != 0x44) | |
2055 | return pc; | |
2056 | ||
2057 | /* REG has register number. */ | |
2058 | reg = (buf[2] >> 3) & 7; | |
2059 | ||
2060 | /* Check the REX.R bit. */ | |
2061 | if (buf[0] == 0x4c) | |
2062 | reg += 8; | |
2063 | ||
2064 | offset = 5; | |
2065 | } | |
2066 | else | |
2067 | { | |
2068 | /* Check callee-saved saved register. The first instruction | |
2069 | has to be "pushq %reg". */ | |
2070 | reg = 0; | |
2071 | if ((buf[0] & 0xf8) == 0x50) | |
2072 | offset = 0; | |
2073 | else if ((buf[0] & 0xf6) == 0x40 | |
2074 | && (buf[1] & 0xf8) == 0x50) | |
2075 | { | |
2076 | /* Check the REX.B bit. */ | |
2077 | if ((buf[0] & 1) != 0) | |
2078 | reg = 8; | |
2079 | ||
2080 | offset = 1; | |
2081 | } | |
2082 | else | |
2083 | return pc; | |
2084 | ||
2085 | /* Get register. */ | |
2086 | reg += buf[offset] & 0x7; | |
2087 | ||
2088 | offset++; | |
2089 | ||
2090 | /* The next instruction has to be "leaq 16(%rsp), %reg". */ | |
2091 | if ((buf[offset] & 0xfb) != 0x48 | |
2092 | || buf[offset + 1] != 0x8d | |
2093 | || buf[offset + 3] != 0x24 | |
2094 | || buf[offset + 4] != 0x10) | |
2095 | return pc; | |
2096 | ||
2097 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
2098 | if ((buf[offset + 2] & 0xc7) != 0x44) | |
2099 | return pc; | |
2100 | ||
2101 | /* REG has register number. */ | |
2102 | r = (buf[offset + 2] >> 3) & 7; | |
2103 | ||
2104 | /* Check the REX.R bit. */ | |
2105 | if (buf[offset] == 0x4c) | |
2106 | r += 8; | |
2107 | ||
2108 | /* Registers in pushq and leaq have to be the same. */ | |
2109 | if (reg != r) | |
2110 | return pc; | |
2111 | ||
2112 | offset += 5; | |
2113 | } | |
2114 | ||
2115 | /* Rigister can't be %rsp nor %rbp. */ | |
2116 | if (reg == 4 || reg == 5) | |
2117 | return pc; | |
2118 | ||
2119 | /* The next instruction has to be "andq $-XXX, %rsp". */ | |
2120 | if (buf[offset] != 0x48 | |
2121 | || buf[offset + 2] != 0xe4 | |
2122 | || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83)) | |
2123 | return pc; | |
2124 | ||
2125 | offset_and = offset; | |
2126 | offset += buf[offset + 1] == 0x81 ? 7 : 4; | |
2127 | ||
2128 | /* The next instruction has to be "pushq -8(%reg)". */ | |
2129 | r = 0; | |
2130 | if (buf[offset] == 0xff) | |
2131 | offset++; | |
2132 | else if ((buf[offset] & 0xf6) == 0x40 | |
2133 | && buf[offset + 1] == 0xff) | |
2134 | { | |
2135 | /* Check the REX.B bit. */ | |
2136 | if ((buf[offset] & 0x1) != 0) | |
2137 | r = 8; | |
2138 | offset += 2; | |
2139 | } | |
2140 | else | |
2141 | return pc; | |
2142 | ||
2143 | /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary | |
2144 | 01. */ | |
2145 | if (buf[offset + 1] != 0xf8 | |
2146 | || (buf[offset] & 0xf8) != 0x70) | |
2147 | return pc; | |
2148 | ||
2149 | /* R/M has register. */ | |
2150 | r += buf[offset] & 7; | |
2151 | ||
2152 | /* Registers in leaq and pushq have to be the same. */ | |
2153 | if (reg != r) | |
2154 | return pc; | |
2155 | ||
2156 | if (current_pc > pc + offset_and) | |
35669430 | 2157 | cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg); |
e0c62198 | 2158 | |
325fac50 | 2159 | return std::min (pc + offset + 2, current_pc); |
e0c62198 L |
2160 | } |
2161 | ||
ac142d96 L |
2162 | /* Similar to amd64_analyze_stack_align for x32. */ |
2163 | ||
2164 | static CORE_ADDR | |
2165 | amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
2166 | struct amd64_frame_cache *cache) | |
2167 | { | |
2168 | /* There are 2 code sequences to re-align stack before the frame | |
2169 | gets set up: | |
2170 | ||
2171 | 1. Use a caller-saved saved register: | |
2172 | ||
2173 | leaq 8(%rsp), %reg | |
2174 | andq $-XXX, %rsp | |
2175 | pushq -8(%reg) | |
2176 | ||
2177 | or | |
2178 | ||
2179 | [addr32] leal 8(%rsp), %reg | |
2180 | andl $-XXX, %esp | |
2181 | [addr32] pushq -8(%reg) | |
2182 | ||
2183 | 2. Use a callee-saved saved register: | |
2184 | ||
2185 | pushq %reg | |
2186 | leaq 16(%rsp), %reg | |
2187 | andq $-XXX, %rsp | |
2188 | pushq -8(%reg) | |
2189 | ||
2190 | or | |
2191 | ||
2192 | pushq %reg | |
2193 | [addr32] leal 16(%rsp), %reg | |
2194 | andl $-XXX, %esp | |
2195 | [addr32] pushq -8(%reg) | |
2196 | ||
2197 | "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes: | |
2198 | ||
24b21115 SM |
2199 | 0x48 0x83 0xe4 0xf0 andq $-16, %rsp |
2200 | 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp | |
ac142d96 L |
2201 | |
2202 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
2203 | ||
24b21115 SM |
2204 | 0x83 0xe4 0xf0 andl $-16, %esp |
2205 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
ac142d96 L |
2206 | */ |
2207 | ||
2208 | gdb_byte buf[19]; | |
2209 | int reg, r; | |
2210 | int offset, offset_and; | |
2211 | ||
2212 | if (target_read_memory (pc, buf, sizeof buf)) | |
2213 | return pc; | |
2214 | ||
2215 | /* Skip optional addr32 prefix. */ | |
2216 | offset = buf[0] == 0x67 ? 1 : 0; | |
2217 | ||
2218 | /* Check caller-saved saved register. The first instruction has | |
2219 | to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */ | |
2220 | if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40) | |
2221 | && buf[offset + 1] == 0x8d | |
2222 | && buf[offset + 3] == 0x24 | |
2223 | && buf[offset + 4] == 0x8) | |
2224 | { | |
2225 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
2226 | if ((buf[offset + 2] & 0xc7) != 0x44) | |
2227 | return pc; | |
2228 | ||
2229 | /* REG has register number. */ | |
2230 | reg = (buf[offset + 2] >> 3) & 7; | |
2231 | ||
2232 | /* Check the REX.R bit. */ | |
2233 | if ((buf[offset] & 0x4) != 0) | |
2234 | reg += 8; | |
2235 | ||
2236 | offset += 5; | |
2237 | } | |
2238 | else | |
2239 | { | |
2240 | /* Check callee-saved saved register. The first instruction | |
2241 | has to be "pushq %reg". */ | |
2242 | reg = 0; | |
2243 | if ((buf[offset] & 0xf6) == 0x40 | |
2244 | && (buf[offset + 1] & 0xf8) == 0x50) | |
2245 | { | |
2246 | /* Check the REX.B bit. */ | |
2247 | if ((buf[offset] & 1) != 0) | |
2248 | reg = 8; | |
2249 | ||
2250 | offset += 1; | |
2251 | } | |
2252 | else if ((buf[offset] & 0xf8) != 0x50) | |
2253 | return pc; | |
2254 | ||
2255 | /* Get register. */ | |
2256 | reg += buf[offset] & 0x7; | |
2257 | ||
2258 | offset++; | |
2259 | ||
2260 | /* Skip optional addr32 prefix. */ | |
2261 | if (buf[offset] == 0x67) | |
2262 | offset++; | |
2263 | ||
2264 | /* The next instruction has to be "leaq 16(%rsp), %reg" or | |
2265 | "leal 16(%rsp), %reg". */ | |
2266 | if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40) | |
2267 | || buf[offset + 1] != 0x8d | |
2268 | || buf[offset + 3] != 0x24 | |
2269 | || buf[offset + 4] != 0x10) | |
2270 | return pc; | |
2271 | ||
2272 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
2273 | if ((buf[offset + 2] & 0xc7) != 0x44) | |
2274 | return pc; | |
2275 | ||
2276 | /* REG has register number. */ | |
2277 | r = (buf[offset + 2] >> 3) & 7; | |
2278 | ||
2279 | /* Check the REX.R bit. */ | |
2280 | if ((buf[offset] & 0x4) != 0) | |
2281 | r += 8; | |
2282 | ||
2283 | /* Registers in pushq and leaq have to be the same. */ | |
2284 | if (reg != r) | |
2285 | return pc; | |
2286 | ||
2287 | offset += 5; | |
2288 | } | |
2289 | ||
2290 | /* Rigister can't be %rsp nor %rbp. */ | |
2291 | if (reg == 4 || reg == 5) | |
2292 | return pc; | |
2293 | ||
2294 | /* The next instruction may be "andq $-XXX, %rsp" or | |
2295 | "andl $-XXX, %esp". */ | |
2296 | if (buf[offset] != 0x48) | |
2297 | offset--; | |
2298 | ||
2299 | if (buf[offset + 2] != 0xe4 | |
2300 | || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83)) | |
2301 | return pc; | |
2302 | ||
2303 | offset_and = offset; | |
2304 | offset += buf[offset + 1] == 0x81 ? 7 : 4; | |
2305 | ||
2306 | /* Skip optional addr32 prefix. */ | |
2307 | if (buf[offset] == 0x67) | |
2308 | offset++; | |
2309 | ||
2310 | /* The next instruction has to be "pushq -8(%reg)". */ | |
2311 | r = 0; | |
2312 | if (buf[offset] == 0xff) | |
2313 | offset++; | |
2314 | else if ((buf[offset] & 0xf6) == 0x40 | |
2315 | && buf[offset + 1] == 0xff) | |
2316 | { | |
2317 | /* Check the REX.B bit. */ | |
2318 | if ((buf[offset] & 0x1) != 0) | |
2319 | r = 8; | |
2320 | offset += 2; | |
2321 | } | |
2322 | else | |
2323 | return pc; | |
2324 | ||
2325 | /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary | |
2326 | 01. */ | |
2327 | if (buf[offset + 1] != 0xf8 | |
2328 | || (buf[offset] & 0xf8) != 0x70) | |
2329 | return pc; | |
2330 | ||
2331 | /* R/M has register. */ | |
2332 | r += buf[offset] & 7; | |
2333 | ||
2334 | /* Registers in leaq and pushq have to be the same. */ | |
2335 | if (reg != r) | |
2336 | return pc; | |
2337 | ||
2338 | if (current_pc > pc + offset_and) | |
2339 | cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg); | |
2340 | ||
325fac50 | 2341 | return std::min (pc + offset + 2, current_pc); |
ac142d96 L |
2342 | } |
2343 | ||
c4f35dd8 MK |
2344 | /* Do a limited analysis of the prologue at PC and update CACHE |
2345 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
2346 | address where the analysis stopped. | |
2347 | ||
2348 | We will handle only functions beginning with: | |
2349 | ||
2350 | pushq %rbp 0x55 | |
50f1ae7b | 2351 | movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec) |
c4f35dd8 | 2352 | |
649e6d92 MK |
2353 | or (for the X32 ABI): |
2354 | ||
2355 | pushq %rbp 0x55 | |
2356 | movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec) | |
2357 | ||
ac4a4f1c SM |
2358 | The `endbr64` instruction can be found before these sequences, and will be |
2359 | skipped if found. | |
2360 | ||
649e6d92 MK |
2361 | Any function that doesn't start with one of these sequences will be |
2362 | assumed to have no prologue and thus no valid frame pointer in | |
2363 | %rbp. */ | |
c4f35dd8 MK |
2364 | |
2365 | static CORE_ADDR | |
e17a4113 UW |
2366 | amd64_analyze_prologue (struct gdbarch *gdbarch, |
2367 | CORE_ADDR pc, CORE_ADDR current_pc, | |
e53bef9f | 2368 | struct amd64_frame_cache *cache) |
53e95fcf | 2369 | { |
e17a4113 | 2370 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
ac4a4f1c SM |
2371 | /* The `endbr64` instruction. */ |
2372 | static const gdb_byte endbr64[4] = { 0xf3, 0x0f, 0x1e, 0xfa }; | |
50f1ae7b DE |
2373 | /* There are two variations of movq %rsp, %rbp. */ |
2374 | static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 }; | |
2375 | static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec }; | |
649e6d92 MK |
2376 | /* Ditto for movl %esp, %ebp. */ |
2377 | static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 }; | |
2378 | static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec }; | |
2379 | ||
d8de1ef7 MK |
2380 | gdb_byte buf[3]; |
2381 | gdb_byte op; | |
c4f35dd8 MK |
2382 | |
2383 | if (current_pc <= pc) | |
2384 | return current_pc; | |
2385 | ||
ac142d96 L |
2386 | if (gdbarch_ptr_bit (gdbarch) == 32) |
2387 | pc = amd64_x32_analyze_stack_align (pc, current_pc, cache); | |
2388 | else | |
2389 | pc = amd64_analyze_stack_align (pc, current_pc, cache); | |
e0c62198 | 2390 | |
bae8a07a | 2391 | op = read_code_unsigned_integer (pc, 1, byte_order); |
c4f35dd8 | 2392 | |
ac4a4f1c SM |
2393 | /* Check for the `endbr64` instruction, skip it if found. */ |
2394 | if (op == endbr64[0]) | |
2395 | { | |
2396 | read_code (pc + 1, buf, 3); | |
2397 | ||
2398 | if (memcmp (buf, &endbr64[1], 3) == 0) | |
2399 | pc += 4; | |
2400 | ||
2401 | op = read_code_unsigned_integer (pc, 1, byte_order); | |
2402 | } | |
2403 | ||
2404 | if (current_pc <= pc) | |
2405 | return current_pc; | |
2406 | ||
c4f35dd8 MK |
2407 | if (op == 0x55) /* pushq %rbp */ |
2408 | { | |
2409 | /* Take into account that we've executed the `pushq %rbp' that | |
dda83cd7 | 2410 | starts this instruction sequence. */ |
90f90721 | 2411 | cache->saved_regs[AMD64_RBP_REGNUM] = 0; |
c4f35dd8 MK |
2412 | cache->sp_offset += 8; |
2413 | ||
2414 | /* If that's all, return now. */ | |
2415 | if (current_pc <= pc + 1) | |
dda83cd7 | 2416 | return current_pc; |
c4f35dd8 | 2417 | |
bae8a07a | 2418 | read_code (pc + 1, buf, 3); |
c4f35dd8 | 2419 | |
649e6d92 MK |
2420 | /* Check for `movq %rsp, %rbp'. */ |
2421 | if (memcmp (buf, mov_rsp_rbp_1, 3) == 0 | |
2422 | || memcmp (buf, mov_rsp_rbp_2, 3) == 0) | |
2423 | { | |
2424 | /* OK, we actually have a frame. */ | |
2425 | cache->frameless_p = 0; | |
2426 | return pc + 4; | |
2427 | } | |
2428 | ||
ed908db6 | 2429 | /* For X32, also check for `movl %esp, %ebp'. */ |
649e6d92 MK |
2430 | if (gdbarch_ptr_bit (gdbarch) == 32) |
2431 | { | |
2432 | if (memcmp (buf, mov_esp_ebp_1, 2) == 0 | |
2433 | || memcmp (buf, mov_esp_ebp_2, 2) == 0) | |
2434 | { | |
2435 | /* OK, we actually have a frame. */ | |
2436 | cache->frameless_p = 0; | |
2437 | return pc + 3; | |
2438 | } | |
2439 | } | |
2440 | ||
2441 | return pc + 1; | |
c4f35dd8 MK |
2442 | } |
2443 | ||
2444 | return pc; | |
53e95fcf JS |
2445 | } |
2446 | ||
df15bd07 JK |
2447 | /* Work around false termination of prologue - GCC PR debug/48827. |
2448 | ||
2449 | START_PC is the first instruction of a function, PC is its minimal already | |
2450 | determined advanced address. Function returns PC if it has nothing to do. | |
2451 | ||
2452 | 84 c0 test %al,%al | |
2453 | 74 23 je after | |
2454 | <-- here is 0 lines advance - the false prologue end marker. | |
2455 | 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp) | |
2456 | 0f 29 4d 80 movaps %xmm1,-0x80(%rbp) | |
2457 | 0f 29 55 90 movaps %xmm2,-0x70(%rbp) | |
2458 | 0f 29 5d a0 movaps %xmm3,-0x60(%rbp) | |
2459 | 0f 29 65 b0 movaps %xmm4,-0x50(%rbp) | |
2460 | 0f 29 6d c0 movaps %xmm5,-0x40(%rbp) | |
2461 | 0f 29 75 d0 movaps %xmm6,-0x30(%rbp) | |
2462 | 0f 29 7d e0 movaps %xmm7,-0x20(%rbp) | |
2463 | after: */ | |
c4f35dd8 MK |
2464 | |
2465 | static CORE_ADDR | |
df15bd07 | 2466 | amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc) |
53e95fcf | 2467 | { |
08711b9a JK |
2468 | struct symtab_and_line start_pc_sal, next_sal; |
2469 | gdb_byte buf[4 + 8 * 7]; | |
2470 | int offset, xmmreg; | |
c4f35dd8 | 2471 | |
08711b9a JK |
2472 | if (pc == start_pc) |
2473 | return pc; | |
2474 | ||
2475 | start_pc_sal = find_pc_sect_line (start_pc, NULL, 0); | |
2476 | if (start_pc_sal.symtab == NULL | |
c6159652 SM |
2477 | || producer_is_gcc_ge_4 (start_pc_sal.symtab->compunit () |
2478 | ->producer ()) < 6 | |
08711b9a JK |
2479 | || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end) |
2480 | return pc; | |
2481 | ||
2482 | next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0); | |
2483 | if (next_sal.line != start_pc_sal.line) | |
2484 | return pc; | |
2485 | ||
2486 | /* START_PC can be from overlayed memory, ignored here. */ | |
bae8a07a | 2487 | if (target_read_code (next_sal.pc - 4, buf, sizeof (buf)) != 0) |
08711b9a JK |
2488 | return pc; |
2489 | ||
2490 | /* test %al,%al */ | |
2491 | if (buf[0] != 0x84 || buf[1] != 0xc0) | |
2492 | return pc; | |
2493 | /* je AFTER */ | |
2494 | if (buf[2] != 0x74) | |
2495 | return pc; | |
2496 | ||
2497 | offset = 4; | |
2498 | for (xmmreg = 0; xmmreg < 8; xmmreg++) | |
2499 | { | |
bede5f5f | 2500 | /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */ |
08711b9a | 2501 | if (buf[offset] != 0x0f || buf[offset + 1] != 0x29 |
dda83cd7 | 2502 | || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5)) |
08711b9a JK |
2503 | return pc; |
2504 | ||
bede5f5f JK |
2505 | /* 0b01?????? */ |
2506 | if ((buf[offset + 2] & 0xc0) == 0x40) | |
08711b9a JK |
2507 | { |
2508 | /* 8-bit displacement. */ | |
2509 | offset += 4; | |
2510 | } | |
bede5f5f JK |
2511 | /* 0b10?????? */ |
2512 | else if ((buf[offset + 2] & 0xc0) == 0x80) | |
08711b9a JK |
2513 | { |
2514 | /* 32-bit displacement. */ | |
2515 | offset += 7; | |
2516 | } | |
2517 | else | |
2518 | return pc; | |
2519 | } | |
2520 | ||
2521 | /* je AFTER */ | |
2522 | if (offset - 4 != buf[3]) | |
2523 | return pc; | |
2524 | ||
2525 | return next_sal.end; | |
53e95fcf | 2526 | } |
df15bd07 JK |
2527 | |
2528 | /* Return PC of first real instruction. */ | |
2529 | ||
2530 | static CORE_ADDR | |
2531 | amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) | |
2532 | { | |
2533 | struct amd64_frame_cache cache; | |
2534 | CORE_ADDR pc; | |
56bf0743 KB |
2535 | CORE_ADDR func_addr; |
2536 | ||
2537 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) | |
2538 | { | |
2539 | CORE_ADDR post_prologue_pc | |
2540 | = skip_prologue_using_sal (gdbarch, func_addr); | |
43f3e411 | 2541 | struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); |
56bf0743 | 2542 | |
c2fd7fae | 2543 | /* LLVM backend (Clang/Flang) always emits a line note before the |
16e311ab FW |
2544 | prologue and another one after. We trust clang and newer Intel |
2545 | compilers to emit usable line notes. */ | |
56bf0743 | 2546 | if (post_prologue_pc |
43f3e411 | 2547 | && (cust != NULL |
ab5f850e SM |
2548 | && cust->producer () != nullptr |
2549 | && (producer_is_llvm (cust->producer ()) | |
2550 | || producer_is_icc_ge_19 (cust->producer ())))) | |
287de656 | 2551 | return std::max (start_pc, post_prologue_pc); |
56bf0743 | 2552 | } |
df15bd07 JK |
2553 | |
2554 | amd64_init_frame_cache (&cache); | |
2555 | pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL, | |
2556 | &cache); | |
2557 | if (cache.frameless_p) | |
2558 | return start_pc; | |
2559 | ||
2560 | return amd64_skip_xmm_prologue (pc, start_pc); | |
2561 | } | |
c4f35dd8 | 2562 | \f |
53e95fcf | 2563 | |
c4f35dd8 MK |
2564 | /* Normal frames. */ |
2565 | ||
8fbca658 | 2566 | static void |
bd2b40ac | 2567 | amd64_frame_cache_1 (frame_info_ptr this_frame, |
8fbca658 | 2568 | struct amd64_frame_cache *cache) |
6d686a84 | 2569 | { |
e17a4113 UW |
2570 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2571 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d8de1ef7 | 2572 | gdb_byte buf[8]; |
6d686a84 | 2573 | int i; |
6d686a84 | 2574 | |
10458914 | 2575 | cache->pc = get_frame_func (this_frame); |
c4f35dd8 | 2576 | if (cache->pc != 0) |
e17a4113 UW |
2577 | amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
2578 | cache); | |
c4f35dd8 MK |
2579 | |
2580 | if (cache->frameless_p) | |
2581 | { | |
4a28816e MK |
2582 | /* We didn't find a valid frame. If we're at the start of a |
2583 | function, or somewhere half-way its prologue, the function's | |
2584 | frame probably hasn't been fully setup yet. Try to | |
2585 | reconstruct the base address for the stack frame by looking | |
2586 | at the stack pointer. For truly "frameless" functions this | |
2587 | might work too. */ | |
c4f35dd8 | 2588 | |
e0c62198 L |
2589 | if (cache->saved_sp_reg != -1) |
2590 | { | |
8fbca658 PA |
2591 | /* Stack pointer has been saved. */ |
2592 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
2593 | cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order); | |
2594 | ||
e0c62198 L |
2595 | /* We're halfway aligning the stack. */ |
2596 | cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8; | |
2597 | cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8; | |
2598 | ||
2599 | /* This will be added back below. */ | |
2600 | cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base; | |
2601 | } | |
2602 | else | |
2603 | { | |
2604 | get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); | |
e17a4113 UW |
2605 | cache->base = extract_unsigned_integer (buf, 8, byte_order) |
2606 | + cache->sp_offset; | |
e0c62198 | 2607 | } |
c4f35dd8 | 2608 | } |
35883a3f MK |
2609 | else |
2610 | { | |
10458914 | 2611 | get_frame_register (this_frame, AMD64_RBP_REGNUM, buf); |
e17a4113 | 2612 | cache->base = extract_unsigned_integer (buf, 8, byte_order); |
35883a3f | 2613 | } |
c4f35dd8 MK |
2614 | |
2615 | /* Now that we have the base address for the stack frame we can | |
2616 | calculate the value of %rsp in the calling frame. */ | |
2617 | cache->saved_sp = cache->base + 16; | |
2618 | ||
35883a3f MK |
2619 | /* For normal frames, %rip is stored at 8(%rbp). If we don't have a |
2620 | frame we find it at the same offset from the reconstructed base | |
e0c62198 L |
2621 | address. If we're halfway aligning the stack, %rip is handled |
2622 | differently (see above). */ | |
2623 | if (!cache->frameless_p || cache->saved_sp_reg == -1) | |
2624 | cache->saved_regs[AMD64_RIP_REGNUM] = 8; | |
35883a3f | 2625 | |
c4f35dd8 MK |
2626 | /* Adjust all the saved registers such that they contain addresses |
2627 | instead of offsets. */ | |
e53bef9f | 2628 | for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) |
c4f35dd8 MK |
2629 | if (cache->saved_regs[i] != -1) |
2630 | cache->saved_regs[i] += cache->base; | |
2631 | ||
8fbca658 PA |
2632 | cache->base_p = 1; |
2633 | } | |
2634 | ||
2635 | static struct amd64_frame_cache * | |
bd2b40ac | 2636 | amd64_frame_cache (frame_info_ptr this_frame, void **this_cache) |
8fbca658 | 2637 | { |
8fbca658 PA |
2638 | struct amd64_frame_cache *cache; |
2639 | ||
2640 | if (*this_cache) | |
9a3c8263 | 2641 | return (struct amd64_frame_cache *) *this_cache; |
8fbca658 PA |
2642 | |
2643 | cache = amd64_alloc_frame_cache (); | |
2644 | *this_cache = cache; | |
2645 | ||
a70b8144 | 2646 | try |
8fbca658 PA |
2647 | { |
2648 | amd64_frame_cache_1 (this_frame, cache); | |
2649 | } | |
230d2906 | 2650 | catch (const gdb_exception_error &ex) |
7556d4a4 PA |
2651 | { |
2652 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 2653 | throw; |
7556d4a4 | 2654 | } |
8fbca658 | 2655 | |
c4f35dd8 | 2656 | return cache; |
6d686a84 ML |
2657 | } |
2658 | ||
8fbca658 | 2659 | static enum unwind_stop_reason |
bd2b40ac | 2660 | amd64_frame_unwind_stop_reason (frame_info_ptr this_frame, |
8fbca658 PA |
2661 | void **this_cache) |
2662 | { | |
2663 | struct amd64_frame_cache *cache = | |
2664 | amd64_frame_cache (this_frame, this_cache); | |
2665 | ||
2666 | if (!cache->base_p) | |
2667 | return UNWIND_UNAVAILABLE; | |
2668 | ||
2669 | /* This marks the outermost frame. */ | |
2670 | if (cache->base == 0) | |
2671 | return UNWIND_OUTERMOST; | |
2672 | ||
2673 | return UNWIND_NO_REASON; | |
2674 | } | |
2675 | ||
c4f35dd8 | 2676 | static void |
bd2b40ac | 2677 | amd64_frame_this_id (frame_info_ptr this_frame, void **this_cache, |
e53bef9f | 2678 | struct frame_id *this_id) |
c4f35dd8 | 2679 | { |
e53bef9f | 2680 | struct amd64_frame_cache *cache = |
10458914 | 2681 | amd64_frame_cache (this_frame, this_cache); |
c4f35dd8 | 2682 | |
8fbca658 | 2683 | if (!cache->base_p) |
5ce0145d PA |
2684 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
2685 | else if (cache->base == 0) | |
2686 | { | |
2687 | /* This marks the outermost frame. */ | |
2688 | return; | |
2689 | } | |
2690 | else | |
2691 | (*this_id) = frame_id_build (cache->base + 16, cache->pc); | |
c4f35dd8 | 2692 | } |
e76e1718 | 2693 | |
10458914 | 2694 | static struct value * |
bd2b40ac | 2695 | amd64_frame_prev_register (frame_info_ptr this_frame, void **this_cache, |
10458914 | 2696 | int regnum) |
53e95fcf | 2697 | { |
10458914 | 2698 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e53bef9f | 2699 | struct amd64_frame_cache *cache = |
10458914 | 2700 | amd64_frame_cache (this_frame, this_cache); |
e76e1718 | 2701 | |
c4f35dd8 | 2702 | gdb_assert (regnum >= 0); |
b1ab997b | 2703 | |
2ae02b47 | 2704 | if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) |
10458914 | 2705 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
e76e1718 | 2706 | |
e53bef9f | 2707 | if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
2708 | return frame_unwind_got_memory (this_frame, regnum, |
2709 | cache->saved_regs[regnum]); | |
e76e1718 | 2710 | |
10458914 | 2711 | return frame_unwind_got_register (this_frame, regnum, regnum); |
c4f35dd8 | 2712 | } |
e76e1718 | 2713 | |
e53bef9f | 2714 | static const struct frame_unwind amd64_frame_unwind = |
c4f35dd8 | 2715 | { |
a154d838 | 2716 | "amd64 prologue", |
c4f35dd8 | 2717 | NORMAL_FRAME, |
8fbca658 | 2718 | amd64_frame_unwind_stop_reason, |
e53bef9f | 2719 | amd64_frame_this_id, |
10458914 DJ |
2720 | amd64_frame_prev_register, |
2721 | NULL, | |
2722 | default_frame_sniffer | |
c4f35dd8 | 2723 | }; |
c4f35dd8 | 2724 | \f |
6710bf39 SS |
2725 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2726 | ||
2727 | static void | |
2728 | amd64_gen_return_address (struct gdbarch *gdbarch, | |
2729 | struct agent_expr *ax, struct axs_value *value, | |
2730 | CORE_ADDR scope) | |
2731 | { | |
2732 | /* The following sequence assumes the traditional use of the base | |
2733 | register. */ | |
2734 | ax_reg (ax, AMD64_RBP_REGNUM); | |
2735 | ax_const_l (ax, 8); | |
2736 | ax_simple (ax, aop_add); | |
2737 | value->type = register_type (gdbarch, AMD64_RIP_REGNUM); | |
2738 | value->kind = axs_lvalue_memory; | |
2739 | } | |
2740 | \f | |
e76e1718 | 2741 | |
c4f35dd8 MK |
2742 | /* Signal trampolines. */ |
2743 | ||
2744 | /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and | |
2745 | 64-bit variants. This would require using identical frame caches | |
2746 | on both platforms. */ | |
2747 | ||
e53bef9f | 2748 | static struct amd64_frame_cache * |
bd2b40ac | 2749 | amd64_sigtramp_frame_cache (frame_info_ptr this_frame, void **this_cache) |
c4f35dd8 | 2750 | { |
e17a4113 | 2751 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
08106042 | 2752 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
e17a4113 | 2753 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e53bef9f | 2754 | struct amd64_frame_cache *cache; |
c4f35dd8 | 2755 | CORE_ADDR addr; |
d8de1ef7 | 2756 | gdb_byte buf[8]; |
2b5e0749 | 2757 | int i; |
c4f35dd8 MK |
2758 | |
2759 | if (*this_cache) | |
9a3c8263 | 2760 | return (struct amd64_frame_cache *) *this_cache; |
c4f35dd8 | 2761 | |
e53bef9f | 2762 | cache = amd64_alloc_frame_cache (); |
c4f35dd8 | 2763 | |
a70b8144 | 2764 | try |
8fbca658 PA |
2765 | { |
2766 | get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); | |
2767 | cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8; | |
2768 | ||
2769 | addr = tdep->sigcontext_addr (this_frame); | |
2770 | gdb_assert (tdep->sc_reg_offset); | |
2771 | gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS); | |
2772 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2773 | if (tdep->sc_reg_offset[i] != -1) | |
2774 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
c4f35dd8 | 2775 | |
8fbca658 PA |
2776 | cache->base_p = 1; |
2777 | } | |
230d2906 | 2778 | catch (const gdb_exception_error &ex) |
7556d4a4 PA |
2779 | { |
2780 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 2781 | throw; |
7556d4a4 | 2782 | } |
c4f35dd8 MK |
2783 | |
2784 | *this_cache = cache; | |
2785 | return cache; | |
53e95fcf JS |
2786 | } |
2787 | ||
8fbca658 | 2788 | static enum unwind_stop_reason |
bd2b40ac | 2789 | amd64_sigtramp_frame_unwind_stop_reason (frame_info_ptr this_frame, |
8fbca658 PA |
2790 | void **this_cache) |
2791 | { | |
2792 | struct amd64_frame_cache *cache = | |
2793 | amd64_sigtramp_frame_cache (this_frame, this_cache); | |
2794 | ||
2795 | if (!cache->base_p) | |
2796 | return UNWIND_UNAVAILABLE; | |
2797 | ||
2798 | return UNWIND_NO_REASON; | |
2799 | } | |
2800 | ||
c4f35dd8 | 2801 | static void |
bd2b40ac | 2802 | amd64_sigtramp_frame_this_id (frame_info_ptr this_frame, |
e53bef9f | 2803 | void **this_cache, struct frame_id *this_id) |
c4f35dd8 | 2804 | { |
e53bef9f | 2805 | struct amd64_frame_cache *cache = |
10458914 | 2806 | amd64_sigtramp_frame_cache (this_frame, this_cache); |
c4f35dd8 | 2807 | |
8fbca658 | 2808 | if (!cache->base_p) |
5ce0145d PA |
2809 | (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); |
2810 | else if (cache->base == 0) | |
2811 | { | |
2812 | /* This marks the outermost frame. */ | |
2813 | return; | |
2814 | } | |
2815 | else | |
2816 | (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame)); | |
c4f35dd8 MK |
2817 | } |
2818 | ||
10458914 | 2819 | static struct value * |
bd2b40ac | 2820 | amd64_sigtramp_frame_prev_register (frame_info_ptr this_frame, |
10458914 | 2821 | void **this_cache, int regnum) |
c4f35dd8 MK |
2822 | { |
2823 | /* Make sure we've initialized the cache. */ | |
10458914 | 2824 | amd64_sigtramp_frame_cache (this_frame, this_cache); |
c4f35dd8 | 2825 | |
10458914 | 2826 | return amd64_frame_prev_register (this_frame, this_cache, regnum); |
c4f35dd8 MK |
2827 | } |
2828 | ||
10458914 DJ |
2829 | static int |
2830 | amd64_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 2831 | frame_info_ptr this_frame, |
10458914 | 2832 | void **this_cache) |
c4f35dd8 | 2833 | { |
345bd07c | 2834 | gdbarch *arch = get_frame_arch (this_frame); |
08106042 | 2835 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch); |
911bc6ee MK |
2836 | |
2837 | /* We shouldn't even bother if we don't have a sigcontext_addr | |
2838 | handler. */ | |
2839 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2840 | return 0; |
911bc6ee MK |
2841 | |
2842 | if (tdep->sigtramp_p != NULL) | |
2843 | { | |
10458914 DJ |
2844 | if (tdep->sigtramp_p (this_frame)) |
2845 | return 1; | |
911bc6ee | 2846 | } |
c4f35dd8 | 2847 | |
911bc6ee | 2848 | if (tdep->sigtramp_start != 0) |
1c3545ae | 2849 | { |
10458914 | 2850 | CORE_ADDR pc = get_frame_pc (this_frame); |
1c3545ae | 2851 | |
911bc6ee MK |
2852 | gdb_assert (tdep->sigtramp_end != 0); |
2853 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2854 | return 1; |
1c3545ae | 2855 | } |
c4f35dd8 | 2856 | |
10458914 | 2857 | return 0; |
c4f35dd8 | 2858 | } |
10458914 DJ |
2859 | |
2860 | static const struct frame_unwind amd64_sigtramp_frame_unwind = | |
2861 | { | |
a154d838 | 2862 | "amd64 sigtramp", |
10458914 | 2863 | SIGTRAMP_FRAME, |
8fbca658 | 2864 | amd64_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2865 | amd64_sigtramp_frame_this_id, |
2866 | amd64_sigtramp_frame_prev_register, | |
2867 | NULL, | |
2868 | amd64_sigtramp_frame_sniffer | |
2869 | }; | |
c4f35dd8 MK |
2870 | \f |
2871 | ||
2872 | static CORE_ADDR | |
bd2b40ac | 2873 | amd64_frame_base_address (frame_info_ptr this_frame, void **this_cache) |
c4f35dd8 | 2874 | { |
e53bef9f | 2875 | struct amd64_frame_cache *cache = |
10458914 | 2876 | amd64_frame_cache (this_frame, this_cache); |
c4f35dd8 MK |
2877 | |
2878 | return cache->base; | |
2879 | } | |
2880 | ||
e53bef9f | 2881 | static const struct frame_base amd64_frame_base = |
c4f35dd8 | 2882 | { |
e53bef9f MK |
2883 | &amd64_frame_unwind, |
2884 | amd64_frame_base_address, | |
2885 | amd64_frame_base_address, | |
2886 | amd64_frame_base_address | |
c4f35dd8 MK |
2887 | }; |
2888 | ||
872761f4 MS |
2889 | /* Normal frames, but in a function epilogue. */ |
2890 | ||
c9cf6e20 MG |
2891 | /* Implement the stack_frame_destroyed_p gdbarch method. |
2892 | ||
2893 | The epilogue is defined here as the 'ret' instruction, which will | |
872761f4 MS |
2894 | follow any instruction such as 'leave' or 'pop %ebp' that destroys |
2895 | the function's stack frame. */ | |
2896 | ||
2897 | static int | |
c9cf6e20 | 2898 | amd64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
872761f4 MS |
2899 | { |
2900 | gdb_byte insn; | |
e0d00bc7 | 2901 | |
872761f4 MS |
2902 | if (target_read_memory (pc, &insn, 1)) |
2903 | return 0; /* Can't read memory at pc. */ | |
2904 | ||
2905 | if (insn != 0xc3) /* 'ret' instruction. */ | |
2906 | return 0; | |
2907 | ||
2908 | return 1; | |
2909 | } | |
2910 | ||
2911 | static int | |
5aca7eaa TV |
2912 | amd64_epilogue_frame_sniffer_1 (const struct frame_unwind *self, |
2913 | frame_info_ptr this_frame, | |
2914 | void **this_prologue_cache, bool override_p) | |
872761f4 | 2915 | { |
2f9f989c TV |
2916 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2917 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2918 | ||
2919 | if (frame_relative_level (this_frame) != 0) | |
2920 | /* We're not in the inner frame, so assume we're not in an epilogue. */ | |
872761f4 | 2921 | return 0; |
2f9f989c | 2922 | |
5aca7eaa TV |
2923 | bool unwind_valid_p |
2924 | = compunit_epilogue_unwind_valid (find_pc_compunit_symtab (pc)); | |
2925 | if (override_p) | |
2926 | { | |
2927 | if (unwind_valid_p) | |
2928 | /* Don't override the symtab unwinders, skip | |
2929 | "amd64 epilogue override". */ | |
2930 | return 0; | |
2931 | } | |
2932 | else | |
2933 | { | |
2934 | if (!unwind_valid_p) | |
2935 | /* "amd64 epilogue override" unwinder already ran, skip | |
2936 | "amd64 epilogue". */ | |
2937 | return 0; | |
2938 | } | |
2f9f989c TV |
2939 | |
2940 | /* Check whether we're in an epilogue. */ | |
2941 | return amd64_stack_frame_destroyed_p (gdbarch, pc); | |
872761f4 MS |
2942 | } |
2943 | ||
5aca7eaa TV |
2944 | static int |
2945 | amd64_epilogue_override_frame_sniffer (const struct frame_unwind *self, | |
2946 | frame_info_ptr this_frame, | |
2947 | void **this_prologue_cache) | |
2948 | { | |
2949 | return amd64_epilogue_frame_sniffer_1 (self, this_frame, this_prologue_cache, | |
2950 | true); | |
2951 | } | |
2952 | ||
2953 | static int | |
2954 | amd64_epilogue_frame_sniffer (const struct frame_unwind *self, | |
2955 | frame_info_ptr this_frame, | |
2956 | void **this_prologue_cache) | |
2957 | { | |
2958 | return amd64_epilogue_frame_sniffer_1 (self, this_frame, this_prologue_cache, | |
2959 | false); | |
2960 | } | |
2961 | ||
872761f4 | 2962 | static struct amd64_frame_cache * |
bd2b40ac | 2963 | amd64_epilogue_frame_cache (frame_info_ptr this_frame, void **this_cache) |
872761f4 MS |
2964 | { |
2965 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2966 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2967 | struct amd64_frame_cache *cache; | |
6c10c06b | 2968 | gdb_byte buf[8]; |
872761f4 MS |
2969 | |
2970 | if (*this_cache) | |
9a3c8263 | 2971 | return (struct amd64_frame_cache *) *this_cache; |
872761f4 MS |
2972 | |
2973 | cache = amd64_alloc_frame_cache (); | |
2974 | *this_cache = cache; | |
2975 | ||
a70b8144 | 2976 | try |
8fbca658 | 2977 | { |
49d7cd73 | 2978 | /* Cache base will be %rsp plus cache->sp_offset (-8). */ |
8fbca658 PA |
2979 | get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); |
2980 | cache->base = extract_unsigned_integer (buf, 8, | |
2981 | byte_order) + cache->sp_offset; | |
2982 | ||
2983 | /* Cache pc will be the frame func. */ | |
49d7cd73 | 2984 | cache->pc = get_frame_func (this_frame); |
872761f4 | 2985 | |
49d7cd73 | 2986 | /* The previous value of %rsp is cache->base plus 16. */ |
8fbca658 | 2987 | cache->saved_sp = cache->base + 16; |
872761f4 | 2988 | |
49d7cd73 | 2989 | /* The saved %rip will be at cache->base plus 8. */ |
8fbca658 | 2990 | cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8; |
872761f4 | 2991 | |
8fbca658 PA |
2992 | cache->base_p = 1; |
2993 | } | |
230d2906 | 2994 | catch (const gdb_exception_error &ex) |
7556d4a4 PA |
2995 | { |
2996 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 2997 | throw; |
7556d4a4 | 2998 | } |
872761f4 MS |
2999 | |
3000 | return cache; | |
3001 | } | |
3002 | ||
8fbca658 | 3003 | static enum unwind_stop_reason |
bd2b40ac | 3004 | amd64_epilogue_frame_unwind_stop_reason (frame_info_ptr this_frame, |
8fbca658 PA |
3005 | void **this_cache) |
3006 | { | |
3007 | struct amd64_frame_cache *cache | |
3008 | = amd64_epilogue_frame_cache (this_frame, this_cache); | |
3009 | ||
3010 | if (!cache->base_p) | |
3011 | return UNWIND_UNAVAILABLE; | |
3012 | ||
3013 | return UNWIND_NO_REASON; | |
3014 | } | |
3015 | ||
872761f4 | 3016 | static void |
bd2b40ac | 3017 | amd64_epilogue_frame_this_id (frame_info_ptr this_frame, |
872761f4 MS |
3018 | void **this_cache, |
3019 | struct frame_id *this_id) | |
3020 | { | |
3021 | struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame, | |
3022 | this_cache); | |
3023 | ||
8fbca658 | 3024 | if (!cache->base_p) |
5ce0145d PA |
3025 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
3026 | else | |
49d7cd73 | 3027 | (*this_id) = frame_id_build (cache->base + 16, cache->pc); |
872761f4 MS |
3028 | } |
3029 | ||
5aca7eaa TV |
3030 | static const struct frame_unwind amd64_epilogue_override_frame_unwind = |
3031 | { | |
3032 | "amd64 epilogue override", | |
3033 | NORMAL_FRAME, | |
3034 | amd64_epilogue_frame_unwind_stop_reason, | |
3035 | amd64_epilogue_frame_this_id, | |
3036 | amd64_frame_prev_register, | |
3037 | NULL, | |
3038 | amd64_epilogue_override_frame_sniffer | |
3039 | }; | |
3040 | ||
872761f4 MS |
3041 | static const struct frame_unwind amd64_epilogue_frame_unwind = |
3042 | { | |
a154d838 | 3043 | "amd64 epilogue", |
872761f4 | 3044 | NORMAL_FRAME, |
8fbca658 | 3045 | amd64_epilogue_frame_unwind_stop_reason, |
872761f4 MS |
3046 | amd64_epilogue_frame_this_id, |
3047 | amd64_frame_prev_register, | |
3048 | NULL, | |
3049 | amd64_epilogue_frame_sniffer | |
3050 | }; | |
3051 | ||
166f4c7b | 3052 | static struct frame_id |
bd2b40ac | 3053 | amd64_dummy_id (struct gdbarch *gdbarch, frame_info_ptr this_frame) |
166f4c7b | 3054 | { |
c4f35dd8 MK |
3055 | CORE_ADDR fp; |
3056 | ||
10458914 | 3057 | fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM); |
c4f35dd8 | 3058 | |
10458914 | 3059 | return frame_id_build (fp + 16, get_frame_pc (this_frame)); |
166f4c7b ML |
3060 | } |
3061 | ||
8b148df9 AC |
3062 | /* 16 byte align the SP per frame requirements. */ |
3063 | ||
3064 | static CORE_ADDR | |
e53bef9f | 3065 | amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
8b148df9 AC |
3066 | { |
3067 | return sp & -(CORE_ADDR)16; | |
3068 | } | |
473f17b0 MK |
3069 | \f |
3070 | ||
593adc23 MK |
3071 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN |
3072 | in the floating-point register set REGSET to register cache | |
3073 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
3074 | |
3075 | static void | |
e53bef9f MK |
3076 | amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache, |
3077 | int regnum, const void *fpregs, size_t len) | |
473f17b0 | 3078 | { |
ac7936df | 3079 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 3080 | const i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
473f17b0 | 3081 | |
1528345d | 3082 | gdb_assert (len >= tdep->sizeof_fpregset); |
90f90721 | 3083 | amd64_supply_fxsave (regcache, regnum, fpregs); |
473f17b0 | 3084 | } |
8b148df9 | 3085 | |
593adc23 MK |
3086 | /* Collect register REGNUM from the register cache REGCACHE and store |
3087 | it in the buffer specified by FPREGS and LEN as described by the | |
3088 | floating-point register set REGSET. If REGNUM is -1, do this for | |
3089 | all registers in REGSET. */ | |
3090 | ||
3091 | static void | |
3092 | amd64_collect_fpregset (const struct regset *regset, | |
3093 | const struct regcache *regcache, | |
3094 | int regnum, void *fpregs, size_t len) | |
3095 | { | |
ac7936df | 3096 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 3097 | const i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
593adc23 | 3098 | |
1528345d | 3099 | gdb_assert (len >= tdep->sizeof_fpregset); |
593adc23 MK |
3100 | amd64_collect_fxsave (regcache, regnum, fpregs); |
3101 | } | |
3102 | ||
8f0435f7 | 3103 | const struct regset amd64_fpregset = |
ecc37a5a AA |
3104 | { |
3105 | NULL, amd64_supply_fpregset, amd64_collect_fpregset | |
3106 | }; | |
c6b33596 MK |
3107 | \f |
3108 | ||
436675d3 PA |
3109 | /* Figure out where the longjmp will land. Slurp the jmp_buf out of |
3110 | %rdi. We expect its value to be a pointer to the jmp_buf structure | |
3111 | from which we extract the address that we will land at. This | |
3112 | address is copied into PC. This routine returns non-zero on | |
3113 | success. */ | |
3114 | ||
3115 | static int | |
bd2b40ac | 3116 | amd64_get_longjmp_target (frame_info_ptr frame, CORE_ADDR *pc) |
436675d3 PA |
3117 | { |
3118 | gdb_byte buf[8]; | |
3119 | CORE_ADDR jb_addr; | |
3120 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
08106042 | 3121 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
345bd07c | 3122 | int jb_pc_offset = tdep->jb_pc_offset; |
df86565b | 3123 | int len = builtin_type (gdbarch)->builtin_func_ptr->length (); |
436675d3 PA |
3124 | |
3125 | /* If JB_PC_OFFSET is -1, we have no way to find out where the | |
3126 | longjmp will land. */ | |
3127 | if (jb_pc_offset == -1) | |
3128 | return 0; | |
3129 | ||
3130 | get_frame_register (frame, AMD64_RDI_REGNUM, buf); | |
0dfff4cb UW |
3131 | jb_addr= extract_typed_address |
3132 | (buf, builtin_type (gdbarch)->builtin_data_ptr); | |
436675d3 PA |
3133 | if (target_read_memory (jb_addr + jb_pc_offset, buf, len)) |
3134 | return 0; | |
3135 | ||
0dfff4cb | 3136 | *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
436675d3 PA |
3137 | |
3138 | return 1; | |
3139 | } | |
3140 | ||
cf648174 HZ |
3141 | static const int amd64_record_regmap[] = |
3142 | { | |
3143 | AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM, | |
3144 | AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, | |
3145 | AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM, | |
3146 | AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM, | |
3147 | AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM, | |
3148 | AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM | |
3149 | }; | |
3150 | ||
1d509aa6 MM |
3151 | /* Implement the "in_indirect_branch_thunk" gdbarch function. */ |
3152 | ||
3153 | static bool | |
3154 | amd64_in_indirect_branch_thunk (struct gdbarch *gdbarch, CORE_ADDR pc) | |
3155 | { | |
3156 | return x86_in_indirect_branch_thunk (pc, amd64_register_names, | |
3157 | AMD64_RAX_REGNUM, | |
3158 | AMD64_RIP_REGNUM); | |
3159 | } | |
3160 | ||
2213a65d | 3161 | void |
c55a47e7 | 3162 | amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch, |
a04b5337 | 3163 | const target_desc *default_tdesc) |
53e95fcf | 3164 | { |
08106042 | 3165 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
90884b2b | 3166 | const struct target_desc *tdesc = info.target_desc; |
05c0465e SDJ |
3167 | static const char *const stap_integer_prefixes[] = { "$", NULL }; |
3168 | static const char *const stap_register_prefixes[] = { "%", NULL }; | |
3169 | static const char *const stap_register_indirection_prefixes[] = { "(", | |
3170 | NULL }; | |
3171 | static const char *const stap_register_indirection_suffixes[] = { ")", | |
3172 | NULL }; | |
53e95fcf | 3173 | |
473f17b0 MK |
3174 | /* AMD64 generally uses `fxsave' instead of `fsave' for saving its |
3175 | floating-point registers. */ | |
3176 | tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; | |
8f0435f7 | 3177 | tdep->fpregset = &amd64_fpregset; |
473f17b0 | 3178 | |
90884b2b | 3179 | if (! tdesc_has_registers (tdesc)) |
c55a47e7 | 3180 | tdesc = default_tdesc; |
90884b2b L |
3181 | tdep->tdesc = tdesc; |
3182 | ||
3183 | tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS; | |
3184 | tdep->register_names = amd64_register_names; | |
3185 | ||
01f9f808 MS |
3186 | if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512") != NULL) |
3187 | { | |
3188 | tdep->zmmh_register_names = amd64_zmmh_names; | |
3189 | tdep->k_register_names = amd64_k_names; | |
3190 | tdep->xmm_avx512_register_names = amd64_xmm_avx512_names; | |
3191 | tdep->ymm16h_register_names = amd64_ymmh_avx512_names; | |
3192 | ||
3193 | tdep->num_zmm_regs = 32; | |
3194 | tdep->num_xmm_avx512_regs = 16; | |
3195 | tdep->num_ymm_avx512_regs = 16; | |
3196 | ||
3197 | tdep->zmm0h_regnum = AMD64_ZMM0H_REGNUM; | |
3198 | tdep->k0_regnum = AMD64_K0_REGNUM; | |
3199 | tdep->xmm16_regnum = AMD64_XMM16_REGNUM; | |
3200 | tdep->ymm16h_regnum = AMD64_YMM16H_REGNUM; | |
3201 | } | |
3202 | ||
a055a187 L |
3203 | if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL) |
3204 | { | |
3205 | tdep->ymmh_register_names = amd64_ymmh_names; | |
3206 | tdep->num_ymm_regs = 16; | |
3207 | tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM; | |
3208 | } | |
3209 | ||
e43e105e WT |
3210 | if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL) |
3211 | { | |
3212 | tdep->mpx_register_names = amd64_mpx_names; | |
3213 | tdep->bndcfgu_regnum = AMD64_BNDCFGU_REGNUM; | |
3214 | tdep->bnd0r_regnum = AMD64_BND0R_REGNUM; | |
3215 | } | |
3216 | ||
2735833d WT |
3217 | if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments") != NULL) |
3218 | { | |
1163a4b7 | 3219 | tdep->fsbase_regnum = AMD64_FSBASE_REGNUM; |
2735833d WT |
3220 | } |
3221 | ||
51547df6 MS |
3222 | if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys") != NULL) |
3223 | { | |
3224 | tdep->pkeys_register_names = amd64_pkeys_names; | |
3225 | tdep->pkru_regnum = AMD64_PKRU_REGNUM; | |
3226 | tdep->num_pkeys_regs = 1; | |
3227 | } | |
3228 | ||
fe01d668 | 3229 | tdep->num_byte_regs = 20; |
1ba53b71 L |
3230 | tdep->num_word_regs = 16; |
3231 | tdep->num_dword_regs = 16; | |
3232 | /* Avoid wiring in the MMX registers for now. */ | |
3233 | tdep->num_mmx_regs = 0; | |
3234 | ||
3543a589 TT |
3235 | set_gdbarch_pseudo_register_read_value (gdbarch, |
3236 | amd64_pseudo_register_read_value); | |
1ba53b71 L |
3237 | set_gdbarch_pseudo_register_write (gdbarch, |
3238 | amd64_pseudo_register_write); | |
62e5fd57 MK |
3239 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
3240 | amd64_ax_pseudo_register_collect); | |
1ba53b71 L |
3241 | |
3242 | set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name); | |
3243 | ||
5716833c | 3244 | /* AMD64 has an FPU and 16 SSE registers. */ |
90f90721 | 3245 | tdep->st0_regnum = AMD64_ST0_REGNUM; |
0c1a73d6 | 3246 | tdep->num_xmm_regs = 16; |
53e95fcf | 3247 | |
0c1a73d6 | 3248 | /* This is what all the fuss is about. */ |
53e95fcf JS |
3249 | set_gdbarch_long_bit (gdbarch, 64); |
3250 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3251 | set_gdbarch_ptr_bit (gdbarch, 64); | |
3252 | ||
e53bef9f MK |
3253 | /* In contrast to the i386, on AMD64 a `long double' actually takes |
3254 | up 128 bits, even though it's still based on the i387 extended | |
3255 | floating-point format which has only 80 significant bits. */ | |
b83b026c MK |
3256 | set_gdbarch_long_double_bit (gdbarch, 128); |
3257 | ||
e53bef9f | 3258 | set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS); |
b83b026c MK |
3259 | |
3260 | /* Register numbers of various important registers. */ | |
90f90721 MK |
3261 | set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ |
3262 | set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ | |
3263 | set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */ | |
3264 | set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ | |
b83b026c | 3265 | |
e53bef9f MK |
3266 | /* The "default" register numbering scheme for AMD64 is referred to |
3267 | as the "DWARF Register Number Mapping" in the System V psABI. | |
3268 | The preferred debugging format for all known AMD64 targets is | |
3269 | actually DWARF2, and GCC doesn't seem to support DWARF (that is | |
3270 | DWARF-1), but we provide the same mapping just in case. This | |
3271 | mapping is also used for stabs, which GCC does support. */ | |
3272 | set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); | |
e53bef9f | 3273 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); |
de220d0f | 3274 | |
c4f35dd8 | 3275 | /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to |
e53bef9f | 3276 | be in use on any of the supported AMD64 targets. */ |
53e95fcf | 3277 | |
c4f35dd8 | 3278 | /* Call dummy code. */ |
e53bef9f MK |
3279 | set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call); |
3280 | set_gdbarch_frame_align (gdbarch, amd64_frame_align); | |
8b148df9 | 3281 | set_gdbarch_frame_red_zone_size (gdbarch, 128); |
53e95fcf | 3282 | |
83acabca | 3283 | set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p); |
d532c08f MK |
3284 | set_gdbarch_register_to_value (gdbarch, i387_register_to_value); |
3285 | set_gdbarch_value_to_register (gdbarch, i387_value_to_register); | |
3286 | ||
5cb0f2d5 | 3287 | set_gdbarch_return_value_as_value (gdbarch, amd64_return_value); |
53e95fcf | 3288 | |
e53bef9f | 3289 | set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue); |
53e95fcf | 3290 | |
cf648174 HZ |
3291 | tdep->record_regmap = amd64_record_regmap; |
3292 | ||
10458914 | 3293 | set_gdbarch_dummy_id (gdbarch, amd64_dummy_id); |
53e95fcf | 3294 | |
872761f4 | 3295 | /* Hook the function epilogue frame unwinder. This unwinder is |
33b5899f | 3296 | appended to the list first, so that it supersedes the other |
872761f4 | 3297 | unwinders in function epilogues. */ |
5aca7eaa TV |
3298 | frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_override_frame_unwind); |
3299 | ||
3300 | frame_unwind_append_unwinder (gdbarch, &amd64_epilogue_frame_unwind); | |
872761f4 MS |
3301 | |
3302 | /* Hook the prologue-based frame unwinders. */ | |
10458914 DJ |
3303 | frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind); |
3304 | frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind); | |
e53bef9f | 3305 | frame_base_set_default (gdbarch, &amd64_frame_base); |
c6b33596 | 3306 | |
436675d3 | 3307 | set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target); |
dde08ee1 PA |
3308 | |
3309 | set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction); | |
6710bf39 SS |
3310 | |
3311 | set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address); | |
55aa24fb SDJ |
3312 | |
3313 | /* SystemTap variables and functions. */ | |
05c0465e SDJ |
3314 | set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); |
3315 | set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); | |
3316 | set_gdbarch_stap_register_indirection_prefixes (gdbarch, | |
3317 | stap_register_indirection_prefixes); | |
3318 | set_gdbarch_stap_register_indirection_suffixes (gdbarch, | |
3319 | stap_register_indirection_suffixes); | |
55aa24fb SDJ |
3320 | set_gdbarch_stap_is_single_operand (gdbarch, |
3321 | i386_stap_is_single_operand); | |
3322 | set_gdbarch_stap_parse_special_token (gdbarch, | |
3323 | i386_stap_parse_special_token); | |
c2170eef MM |
3324 | set_gdbarch_insn_is_call (gdbarch, amd64_insn_is_call); |
3325 | set_gdbarch_insn_is_ret (gdbarch, amd64_insn_is_ret); | |
3326 | set_gdbarch_insn_is_jump (gdbarch, amd64_insn_is_jump); | |
1d509aa6 MM |
3327 | |
3328 | set_gdbarch_in_indirect_branch_thunk (gdbarch, | |
3329 | amd64_in_indirect_branch_thunk); | |
257e02d8 TT |
3330 | |
3331 | register_amd64_ravenscar_ops (gdbarch); | |
c4f35dd8 | 3332 | } |
c912f608 SM |
3333 | |
3334 | /* Initialize ARCH for x86-64, no osabi. */ | |
3335 | ||
3336 | static void | |
3337 | amd64_none_init_abi (gdbarch_info info, gdbarch *arch) | |
3338 | { | |
de52b960 PA |
3339 | amd64_init_abi (info, arch, amd64_target_description (X86_XSTATE_SSE_MASK, |
3340 | true)); | |
c912f608 | 3341 | } |
fff4548b MK |
3342 | |
3343 | static struct type * | |
3344 | amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
3345 | { | |
08106042 | 3346 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
fff4548b MK |
3347 | |
3348 | switch (regnum - tdep->eax_regnum) | |
3349 | { | |
3350 | case AMD64_RBP_REGNUM: /* %ebp */ | |
3351 | case AMD64_RSP_REGNUM: /* %esp */ | |
3352 | return builtin_type (gdbarch)->builtin_data_ptr; | |
3353 | case AMD64_RIP_REGNUM: /* %eip */ | |
3354 | return builtin_type (gdbarch)->builtin_func_ptr; | |
3355 | } | |
3356 | ||
3357 | return i386_pseudo_register_type (gdbarch, regnum); | |
3358 | } | |
3359 | ||
3360 | void | |
c55a47e7 | 3361 | amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch, |
a04b5337 | 3362 | const target_desc *default_tdesc) |
fff4548b | 3363 | { |
08106042 | 3364 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
fff4548b | 3365 | |
c55a47e7 | 3366 | amd64_init_abi (info, gdbarch, default_tdesc); |
fff4548b MK |
3367 | |
3368 | tdep->num_dword_regs = 17; | |
3369 | set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type); | |
3370 | ||
3371 | set_gdbarch_long_bit (gdbarch, 32); | |
3372 | set_gdbarch_ptr_bit (gdbarch, 32); | |
3373 | } | |
90884b2b | 3374 | |
c912f608 SM |
3375 | /* Initialize ARCH for x64-32, no osabi. */ |
3376 | ||
3377 | static void | |
3378 | amd64_x32_none_init_abi (gdbarch_info info, gdbarch *arch) | |
3379 | { | |
3380 | amd64_x32_init_abi (info, arch, | |
de52b960 | 3381 | amd64_target_description (X86_XSTATE_SSE_MASK, true)); |
c912f608 SM |
3382 | } |
3383 | ||
97de3545 JB |
3384 | /* Return the target description for a specified XSAVE feature mask. */ |
3385 | ||
3386 | const struct target_desc * | |
de52b960 | 3387 | amd64_target_description (uint64_t xcr0, bool segments) |
97de3545 | 3388 | { |
22916b07 | 3389 | static target_desc *amd64_tdescs \ |
de52b960 | 3390 | [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {}; |
22916b07 YQ |
3391 | target_desc **tdesc; |
3392 | ||
3393 | tdesc = &amd64_tdescs[(xcr0 & X86_XSTATE_AVX) ? 1 : 0] | |
3394 | [(xcr0 & X86_XSTATE_MPX) ? 1 : 0] | |
3395 | [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0] | |
de52b960 PA |
3396 | [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0] |
3397 | [segments ? 1 : 0]; | |
22916b07 YQ |
3398 | |
3399 | if (*tdesc == NULL) | |
de52b960 PA |
3400 | *tdesc = amd64_create_target_description (xcr0, false, false, |
3401 | segments); | |
22916b07 YQ |
3402 | |
3403 | return *tdesc; | |
97de3545 JB |
3404 | } |
3405 | ||
6c265988 | 3406 | void _initialize_amd64_tdep (); |
90884b2b | 3407 | void |
6c265988 | 3408 | _initialize_amd64_tdep () |
90884b2b | 3409 | { |
c912f608 | 3410 | gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x86_64, GDB_OSABI_NONE, |
24b21115 | 3411 | amd64_none_init_abi); |
c912f608 | 3412 | gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x64_32, GDB_OSABI_NONE, |
24b21115 | 3413 | amd64_x32_none_init_abi); |
90884b2b | 3414 | } |
c4f35dd8 MK |
3415 | \f |
3416 | ||
41d041d6 MK |
3417 | /* The 64-bit FXSAVE format differs from the 32-bit format in the |
3418 | sense that the instruction pointer and data pointer are simply | |
3419 | 64-bit offsets into the code segment and the data segment instead | |
3420 | of a selector offset pair. The functions below store the upper 32 | |
3421 | bits of these pointers (instead of just the 16-bits of the segment | |
3422 | selector). */ | |
3423 | ||
3424 | /* Fill register REGNUM in REGCACHE with the appropriate | |
0485f6ad MK |
3425 | floating-point or SSE register value from *FXSAVE. If REGNUM is |
3426 | -1, do this for all registers. This function masks off any of the | |
3427 | reserved bits in *FXSAVE. */ | |
c4f35dd8 MK |
3428 | |
3429 | void | |
90f90721 | 3430 | amd64_supply_fxsave (struct regcache *regcache, int regnum, |
20a6ec49 | 3431 | const void *fxsave) |
c4f35dd8 | 3432 | { |
ac7936df | 3433 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 3434 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
20a6ec49 | 3435 | |
41d041d6 | 3436 | i387_supply_fxsave (regcache, regnum, fxsave); |
c4f35dd8 | 3437 | |
233dfcf0 L |
3438 | if (fxsave |
3439 | && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) | |
c4f35dd8 | 3440 | { |
9a3c8263 | 3441 | const gdb_byte *regs = (const gdb_byte *) fxsave; |
41d041d6 | 3442 | |
20a6ec49 | 3443 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) |
73e1c03f | 3444 | regcache->raw_supply (I387_FISEG_REGNUM (tdep), regs + 12); |
20a6ec49 | 3445 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) |
73e1c03f | 3446 | regcache->raw_supply (I387_FOSEG_REGNUM (tdep), regs + 20); |
c4f35dd8 | 3447 | } |
0c1a73d6 MK |
3448 | } |
3449 | ||
a055a187 L |
3450 | /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */ |
3451 | ||
3452 | void | |
3453 | amd64_supply_xsave (struct regcache *regcache, int regnum, | |
3454 | const void *xsave) | |
3455 | { | |
ac7936df | 3456 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 3457 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
a055a187 L |
3458 | |
3459 | i387_supply_xsave (regcache, regnum, xsave); | |
3460 | ||
233dfcf0 L |
3461 | if (xsave |
3462 | && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) | |
a055a187 | 3463 | { |
9a3c8263 | 3464 | const gdb_byte *regs = (const gdb_byte *) xsave; |
8ee22052 | 3465 | ULONGEST clear_bv; |
a055a187 | 3466 | |
8ee22052 AB |
3467 | clear_bv = i387_xsave_get_clear_bv (gdbarch, xsave); |
3468 | ||
3469 | /* If the FISEG and FOSEG registers have not been initialised yet | |
3470 | (their CLEAR_BV bit is set) then their default values of zero will | |
3471 | have already been setup by I387_SUPPLY_XSAVE. */ | |
3472 | if (!(clear_bv & X86_XSTATE_X87)) | |
3473 | { | |
3474 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) | |
73e1c03f | 3475 | regcache->raw_supply (I387_FISEG_REGNUM (tdep), regs + 12); |
8ee22052 | 3476 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) |
73e1c03f | 3477 | regcache->raw_supply (I387_FOSEG_REGNUM (tdep), regs + 20); |
8ee22052 | 3478 | } |
a055a187 L |
3479 | } |
3480 | } | |
3481 | ||
3c017e40 MK |
3482 | /* Fill register REGNUM (if it is a floating-point or SSE register) in |
3483 | *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for | |
3484 | all registers. This function doesn't touch any of the reserved | |
3485 | bits in *FXSAVE. */ | |
3486 | ||
3487 | void | |
3488 | amd64_collect_fxsave (const struct regcache *regcache, int regnum, | |
3489 | void *fxsave) | |
3490 | { | |
ac7936df | 3491 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 3492 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
9a3c8263 | 3493 | gdb_byte *regs = (gdb_byte *) fxsave; |
3c017e40 MK |
3494 | |
3495 | i387_collect_fxsave (regcache, regnum, fxsave); | |
3496 | ||
233dfcf0 | 3497 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) |
f0ef85a5 | 3498 | { |
20a6ec49 | 3499 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) |
34a79281 | 3500 | regcache->raw_collect (I387_FISEG_REGNUM (tdep), regs + 12); |
20a6ec49 | 3501 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) |
34a79281 | 3502 | regcache->raw_collect (I387_FOSEG_REGNUM (tdep), regs + 20); |
f0ef85a5 | 3503 | } |
3c017e40 | 3504 | } |
a055a187 | 3505 | |
7a9dd1b2 | 3506 | /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */ |
a055a187 L |
3507 | |
3508 | void | |
3509 | amd64_collect_xsave (const struct regcache *regcache, int regnum, | |
3510 | void *xsave, int gcore) | |
3511 | { | |
ac7936df | 3512 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 3513 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
9a3c8263 | 3514 | gdb_byte *regs = (gdb_byte *) xsave; |
a055a187 L |
3515 | |
3516 | i387_collect_xsave (regcache, regnum, xsave, gcore); | |
3517 | ||
233dfcf0 | 3518 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) |
a055a187 L |
3519 | { |
3520 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) | |
34a79281 | 3521 | regcache->raw_collect (I387_FISEG_REGNUM (tdep), |
a055a187 L |
3522 | regs + 12); |
3523 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) | |
34a79281 | 3524 | regcache->raw_collect (I387_FOSEG_REGNUM (tdep), |
a055a187 L |
3525 | regs + 20); |
3526 | } | |
3527 | } |