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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
b6ba6518 | 2 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
1e698235 | 3 | 2001, 2002, 2003 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c | 21 | |
34e8f22d RE |
22 | #include <ctype.h> /* XXX for isupper () */ |
23 | ||
c906108c SS |
24 | #include "defs.h" |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "symfile.h" | |
30 | #include "gdb_string.h" | |
afd7eef0 | 31 | #include "dis-asm.h" /* For register styles. */ |
4e052eda | 32 | #include "regcache.h" |
d16aafd8 | 33 | #include "doublest.h" |
fd0407d6 | 34 | #include "value.h" |
34e8f22d | 35 | #include "arch-utils.h" |
a42dd537 | 36 | #include "solib-svr4.h" |
4be87837 | 37 | #include "osabi.h" |
34e8f22d RE |
38 | |
39 | #include "arm-tdep.h" | |
26216b98 | 40 | #include "gdb/sim-arm.h" |
34e8f22d | 41 | |
082fc60d RE |
42 | #include "elf-bfd.h" |
43 | #include "coff/internal.h" | |
97e03143 | 44 | #include "elf/arm.h" |
c906108c | 45 | |
26216b98 AC |
46 | #include "gdb_assert.h" |
47 | ||
6529d2dd AC |
48 | static int arm_debug; |
49 | ||
2a451106 KB |
50 | /* Each OS has a different mechanism for accessing the various |
51 | registers stored in the sigcontext structure. | |
52 | ||
53 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or | |
54 | function pointer) which may be used to determine the addresses | |
55 | of the various saved registers in the sigcontext structure. | |
56 | ||
57 | For the ARM target, there are three parameters to this function. | |
58 | The first is the pc value of the frame under consideration, the | |
59 | second the stack pointer of this frame, and the last is the | |
60 | register number to fetch. | |
61 | ||
62 | If the tm.h file does not define this macro, then it's assumed that | |
63 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to | |
64 | be 0. | |
65 | ||
66 | When it comes time to multi-arching this code, see the identically | |
67 | named machinery in ia64-tdep.c for an example of how it could be | |
68 | done. It should not be necessary to modify the code below where | |
69 | this macro is used. */ | |
70 | ||
3bb04bdd AC |
71 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
72 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P | |
73 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 | |
74 | #endif | |
75 | #else | |
76 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 | |
77 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 | |
2a451106 KB |
78 | #endif |
79 | ||
082fc60d RE |
80 | /* Macros for setting and testing a bit in a minimal symbol that marks |
81 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
82 | is used for this purpose. This field is already being used to store | |
83 | the symbol size, so the assumption is that the symbol size cannot | |
84 | exceed 2^31. | |
85 | ||
86 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
87 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. | |
88 | MSYMBOL_SIZE Returns the size of the minimal symbol, | |
89 | i.e. the "info" field with the "special" bit | |
90 | masked out. */ | |
91 | ||
92 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
93 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
94 | | 0x80000000) | |
95 | ||
96 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
97 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
98 | ||
99 | #define MSYMBOL_SIZE(msym) \ | |
100 | ((long) MSYMBOL_INFO (msym) & 0x7fffffff) | |
ed9a39eb | 101 | |
afd7eef0 RE |
102 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
103 | static struct cmd_list_element *setarmcmdlist = NULL; | |
104 | static struct cmd_list_element *showarmcmdlist = NULL; | |
105 | ||
fd50bc42 RE |
106 | /* The type of floating-point to use. Keep this in sync with enum |
107 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
108 | static const char *fp_model_strings[] = | |
109 | { | |
110 | "auto", | |
111 | "softfpa", | |
112 | "fpa", | |
113 | "softvfp", | |
114 | "vfp" | |
115 | }; | |
116 | ||
117 | /* A variable that can be configured by the user. */ | |
118 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
119 | static const char *current_fp_model = "auto"; | |
120 | ||
94c30b78 | 121 | /* Number of different reg name sets (options). */ |
afd7eef0 | 122 | static int num_disassembly_options; |
bc90b915 FN |
123 | |
124 | /* We have more registers than the disassembler as gdb can print the value | |
125 | of special registers as well. | |
126 | The general register names are overwritten by whatever is being used by | |
94c30b78 | 127 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
bc90b915 | 128 | |
94c30b78 | 129 | /* Initial value: Register names used in ARM's ISA documentation. */ |
bc90b915 | 130 | static char * arm_register_name_strings[] = |
da59e081 JM |
131 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
132 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
133 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
134 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
135 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
136 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 137 | "fps", "cpsr" }; /* 24 25 */ |
966fbf70 | 138 | static char **arm_register_names = arm_register_name_strings; |
ed9a39eb | 139 | |
afd7eef0 RE |
140 | /* Valid register name styles. */ |
141 | static const char **valid_disassembly_styles; | |
ed9a39eb | 142 | |
afd7eef0 RE |
143 | /* Disassembly style to use. Default to "std" register names. */ |
144 | static const char *disassembly_style; | |
94c30b78 | 145 | /* Index to that option in the opcodes table. */ |
da3c6d4a | 146 | static int current_option; |
96baa820 | 147 | |
ed9a39eb | 148 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 RE |
149 | style. */ |
150 | static void set_disassembly_style_sfunc(char *, int, | |
ed9a39eb | 151 | struct cmd_list_element *); |
afd7eef0 | 152 | static void set_disassembly_style (void); |
ed9a39eb | 153 | |
b508a996 RE |
154 | static void convert_from_extended (const struct floatformat *, const void *, |
155 | void *); | |
156 | static void convert_to_extended (const struct floatformat *, void *, | |
157 | const void *); | |
ed9a39eb JM |
158 | |
159 | /* Define other aspects of the stack frame. We keep the offsets of | |
160 | all saved registers, 'cause we need 'em a lot! We also keep the | |
161 | current size of the stack frame, and the offset of the frame | |
162 | pointer from the stack pointer (for frameless functions, and when | |
94c30b78 | 163 | we're still in the prologue of a function with a frame). */ |
ed9a39eb JM |
164 | |
165 | struct frame_extra_info | |
c3b4394c RE |
166 | { |
167 | int framesize; | |
168 | int frameoffset; | |
169 | int framereg; | |
170 | }; | |
ed9a39eb | 171 | |
bc90b915 FN |
172 | /* Addresses for calling Thumb functions have the bit 0 set. |
173 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
174 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
175 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
176 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
177 | ||
39bbf761 | 178 | static int |
ed9a39eb | 179 | arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe) |
c906108c | 180 | { |
8bedc050 | 181 | return (DEPRECATED_FRAME_SAVED_PC (thisframe) >= LOWEST_PC); |
c906108c SS |
182 | } |
183 | ||
94c30b78 | 184 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
185 | |
186 | int arm_apcs_32 = 1; | |
187 | ||
ed9a39eb JM |
188 | /* Flag set by arm_fix_call_dummy that tells whether the target |
189 | function is a Thumb function. This flag is checked by | |
190 | arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and | |
191 | its use in valops.c) to pass the function address as an additional | |
192 | parameter. */ | |
c906108c SS |
193 | |
194 | static int target_is_thumb; | |
195 | ||
ed9a39eb JM |
196 | /* Flag set by arm_fix_call_dummy that tells whether the calling |
197 | function is a Thumb function. This flag is checked by | |
198 | arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */ | |
c906108c SS |
199 | |
200 | static int caller_is_thumb; | |
201 | ||
ed9a39eb JM |
202 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
203 | function. */ | |
c906108c | 204 | |
34e8f22d | 205 | int |
2a451106 | 206 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 207 | { |
c5aa993b | 208 | struct minimal_symbol *sym; |
c906108c | 209 | |
ed9a39eb | 210 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
211 | if (IS_THUMB_ADDR (memaddr)) |
212 | return 1; | |
213 | ||
ed9a39eb | 214 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
215 | sym = lookup_minimal_symbol_by_pc (memaddr); |
216 | if (sym) | |
217 | { | |
c5aa993b | 218 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
219 | } |
220 | else | |
ed9a39eb JM |
221 | { |
222 | return 0; | |
223 | } | |
c906108c SS |
224 | } |
225 | ||
ed9a39eb JM |
226 | /* Determine if the program counter specified in MEMADDR is in a call |
227 | dummy being called from a Thumb function. */ | |
c906108c | 228 | |
34e8f22d | 229 | int |
2a451106 | 230 | arm_pc_is_thumb_dummy (CORE_ADDR memaddr) |
c906108c | 231 | { |
c5aa993b | 232 | CORE_ADDR sp = read_sp (); |
c906108c | 233 | |
dfcd3bfb JM |
234 | /* FIXME: Until we switch for the new call dummy macros, this heuristic |
235 | is the best we can do. We are trying to determine if the pc is on | |
236 | the stack, which (hopefully) will only happen in a call dummy. | |
237 | We hope the current stack pointer is not so far alway from the dummy | |
238 | frame location (true if we have not pushed large data structures or | |
239 | gone too many levels deep) and that our 1024 is not enough to consider | |
94c30b78 | 240 | code regions as part of the stack (true for most practical purposes). */ |
ae45cd16 | 241 | if (DEPRECATED_PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024)) |
c906108c SS |
242 | return caller_is_thumb; |
243 | else | |
244 | return 0; | |
245 | } | |
246 | ||
181c1381 | 247 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 248 | static CORE_ADDR |
ed9a39eb | 249 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c | 250 | { |
a3a2ee65 JT |
251 | if (arm_apcs_32) |
252 | return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc)); | |
c906108c | 253 | else |
a3a2ee65 | 254 | return (val & 0x03fffffc); |
c906108c SS |
255 | } |
256 | ||
181c1381 RE |
257 | /* When reading symbols, we need to zap the low bit of the address, |
258 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 259 | static CORE_ADDR |
181c1381 RE |
260 | arm_smash_text_address (CORE_ADDR val) |
261 | { | |
262 | return val & ~1; | |
263 | } | |
264 | ||
34e8f22d RE |
265 | /* Immediately after a function call, return the saved pc. Can't |
266 | always go through the frames for this because on some machines the | |
267 | new frame is not set up until the new function executes some | |
268 | instructions. */ | |
269 | ||
270 | static CORE_ADDR | |
ed9a39eb | 271 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c | 272 | { |
34e8f22d | 273 | return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); |
c906108c SS |
274 | } |
275 | ||
0defa245 RE |
276 | /* Determine whether the function invocation represented by FI has a |
277 | frame on the stack associated with it. If it does return zero, | |
278 | otherwise return 1. */ | |
279 | ||
148754e5 | 280 | static int |
ed9a39eb | 281 | arm_frameless_function_invocation (struct frame_info *fi) |
392a587b | 282 | { |
392a587b | 283 | CORE_ADDR func_start, after_prologue; |
96baa820 | 284 | int frameless; |
ed9a39eb | 285 | |
0defa245 RE |
286 | /* Sometimes we have functions that do a little setup (like saving the |
287 | vN registers with the stmdb instruction, but DO NOT set up a frame. | |
288 | The symbol table will report this as a prologue. However, it is | |
289 | important not to try to parse these partial frames as frames, or we | |
290 | will get really confused. | |
291 | ||
292 | So I will demand 3 instructions between the start & end of the | |
293 | prologue before I call it a real prologue, i.e. at least | |
294 | mov ip, sp, | |
295 | stmdb sp!, {} | |
296 | sub sp, ip, #4. */ | |
297 | ||
8cf71652 | 298 | func_start = (get_frame_func (fi) + FUNCTION_START_OFFSET); |
7be570e7 | 299 | after_prologue = SKIP_PROLOGUE (func_start); |
ed9a39eb | 300 | |
96baa820 | 301 | /* There are some frameless functions whose first two instructions |
ed9a39eb | 302 | follow the standard APCS form, in which case after_prologue will |
94c30b78 | 303 | be func_start + 8. */ |
ed9a39eb | 304 | |
96baa820 | 305 | frameless = (after_prologue < func_start + 12); |
392a587b JM |
306 | return frameless; |
307 | } | |
308 | ||
c906108c | 309 | /* A typical Thumb prologue looks like this: |
c5aa993b JM |
310 | push {r7, lr} |
311 | add sp, sp, #-28 | |
312 | add r7, sp, #12 | |
c906108c | 313 | Sometimes the latter instruction may be replaced by: |
da59e081 JM |
314 | mov r7, sp |
315 | ||
316 | or like this: | |
317 | push {r7, lr} | |
318 | mov r7, sp | |
319 | sub sp, #12 | |
320 | ||
321 | or, on tpcs, like this: | |
322 | sub sp,#16 | |
323 | push {r7, lr} | |
324 | (many instructions) | |
325 | mov r7, sp | |
326 | sub sp, #12 | |
327 | ||
328 | There is always one instruction of three classes: | |
329 | 1 - push | |
330 | 2 - setting of r7 | |
331 | 3 - adjusting of sp | |
332 | ||
333 | When we have found at least one of each class we are done with the prolog. | |
334 | Note that the "sub sp, #NN" before the push does not count. | |
ed9a39eb | 335 | */ |
c906108c SS |
336 | |
337 | static CORE_ADDR | |
c7885828 | 338 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
c906108c SS |
339 | { |
340 | CORE_ADDR current_pc; | |
da3c6d4a MS |
341 | /* findmask: |
342 | bit 0 - push { rlist } | |
343 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
344 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
345 | */ | |
346 | int findmask = 0; | |
347 | ||
94c30b78 MS |
348 | for (current_pc = pc; |
349 | current_pc + 2 < func_end && current_pc < pc + 40; | |
da3c6d4a | 350 | current_pc += 2) |
c906108c SS |
351 | { |
352 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
353 | ||
94c30b78 | 354 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 355 | { |
94c30b78 | 356 | findmask |= 1; /* push found */ |
da59e081 | 357 | } |
da3c6d4a MS |
358 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
359 | sub sp, #simm */ | |
da59e081 | 360 | { |
94c30b78 | 361 | if ((findmask & 1) == 0) /* before push ? */ |
da59e081 JM |
362 | continue; |
363 | else | |
94c30b78 | 364 | findmask |= 4; /* add/sub sp found */ |
da59e081 JM |
365 | } |
366 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
367 | { | |
94c30b78 | 368 | findmask |= 2; /* setting of r7 found */ |
da59e081 JM |
369 | } |
370 | else if (insn == 0x466f) /* mov r7, sp */ | |
371 | { | |
94c30b78 | 372 | findmask |= 2; /* setting of r7 found */ |
da59e081 | 373 | } |
3d74b771 FF |
374 | else if (findmask == (4+2+1)) |
375 | { | |
da3c6d4a MS |
376 | /* We have found one of each type of prologue instruction */ |
377 | break; | |
3d74b771 | 378 | } |
da59e081 | 379 | else |
94c30b78 | 380 | /* Something in the prolog that we don't care about or some |
da3c6d4a | 381 | instruction from outside the prolog scheduled here for |
94c30b78 | 382 | optimization. */ |
da3c6d4a | 383 | continue; |
c906108c SS |
384 | } |
385 | ||
386 | return current_pc; | |
387 | } | |
388 | ||
da3c6d4a MS |
389 | /* Advance the PC across any function entry prologue instructions to |
390 | reach some "real" code. | |
34e8f22d RE |
391 | |
392 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 393 | prologue: |
c906108c | 394 | |
c5aa993b JM |
395 | mov ip, sp |
396 | [stmfd sp!, {a1,a2,a3,a4}] | |
397 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
398 | [stfe f7, [sp, #-12]!] |
399 | [stfe f6, [sp, #-12]!] | |
400 | [stfe f5, [sp, #-12]!] | |
401 | [stfe f4, [sp, #-12]!] | |
402 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 403 | |
34e8f22d | 404 | static CORE_ADDR |
ed9a39eb | 405 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
406 | { |
407 | unsigned long inst; | |
408 | CORE_ADDR skip_pc; | |
b8d5e71d | 409 | CORE_ADDR func_addr, func_end = 0; |
50f6fb4b | 410 | char *func_name; |
c906108c SS |
411 | struct symtab_and_line sal; |
412 | ||
848cfffb | 413 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
ae45cd16 | 414 | if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) |
848cfffb AC |
415 | return pc; |
416 | ||
96baa820 | 417 | /* See what the symbol table says. */ |
ed9a39eb | 418 | |
50f6fb4b | 419 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 420 | { |
50f6fb4b CV |
421 | struct symbol *sym; |
422 | ||
423 | /* Found a function. */ | |
176620f1 | 424 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL); |
50f6fb4b CV |
425 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
426 | { | |
94c30b78 | 427 | /* Don't use this trick for assembly source files. */ |
50f6fb4b CV |
428 | sal = find_pc_line (func_addr, 0); |
429 | if ((sal.line != 0) && (sal.end < func_end)) | |
430 | return sal.end; | |
431 | } | |
c906108c SS |
432 | } |
433 | ||
434 | /* Check if this is Thumb code. */ | |
435 | if (arm_pc_is_thumb (pc)) | |
c7885828 | 436 | return thumb_skip_prologue (pc, func_end); |
c906108c SS |
437 | |
438 | /* Can't find the prologue end in the symbol table, try it the hard way | |
94c30b78 | 439 | by disassembling the instructions. */ |
c906108c | 440 | |
b8d5e71d MS |
441 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
442 | if (func_end == 0 || func_end > pc + 64) | |
443 | func_end = pc + 64; | |
c906108c | 444 | |
b8d5e71d | 445 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
f43845b3 | 446 | { |
f43845b3 | 447 | inst = read_memory_integer (skip_pc, 4); |
f43845b3 | 448 | |
b8d5e71d MS |
449 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
450 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
451 | continue; | |
c906108c | 452 | |
b8d5e71d MS |
453 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
454 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
455 | continue; | |
c906108c | 456 | |
b8d5e71d MS |
457 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
458 | continue; | |
c906108c | 459 | |
b8d5e71d MS |
460 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
461 | continue; | |
11d3b27d | 462 | |
b8d5e71d MS |
463 | /* Any insns after this point may float into the code, if it makes |
464 | for better instruction scheduling, so we skip them only if we | |
465 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 466 | |
b8d5e71d MS |
467 | /* We may have either one sfmfd instruction here, or several stfe |
468 | insns, depending on the version of floating point code we | |
469 | support. */ | |
470 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
471 | continue; | |
472 | ||
473 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
474 | continue; | |
475 | ||
476 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
477 | continue; | |
478 | ||
479 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
480 | continue; | |
481 | ||
482 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
483 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
484 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
485 | continue; | |
486 | ||
487 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
488 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
489 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
490 | continue; | |
491 | ||
492 | /* Un-recognized instruction; stop scanning. */ | |
493 | break; | |
f43845b3 | 494 | } |
c906108c | 495 | |
b8d5e71d | 496 | return skip_pc; /* End of prologue */ |
c906108c | 497 | } |
94c30b78 | 498 | |
c5aa993b | 499 | /* *INDENT-OFF* */ |
c906108c SS |
500 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
501 | This function decodes a Thumb function prologue to determine: | |
502 | 1) the size of the stack frame | |
503 | 2) which registers are saved on it | |
504 | 3) the offsets of saved regs | |
505 | 4) the offset from the stack pointer to the frame pointer | |
506 | This information is stored in the "extra" fields of the frame_info. | |
507 | ||
da59e081 JM |
508 | A typical Thumb function prologue would create this stack frame |
509 | (offsets relative to FP) | |
c906108c SS |
510 | old SP -> 24 stack parameters |
511 | 20 LR | |
512 | 16 R7 | |
513 | R7 -> 0 local variables (16 bytes) | |
514 | SP -> -12 additional stack space (12 bytes) | |
515 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
516 | 12 bytes. The frame register is R7. |
517 | ||
da3c6d4a MS |
518 | The comments for thumb_skip_prolog() describe the algorithm we use |
519 | to detect the end of the prolog. */ | |
c5aa993b JM |
520 | /* *INDENT-ON* */ |
521 | ||
c906108c | 522 | static void |
ed9a39eb | 523 | thumb_scan_prologue (struct frame_info *fi) |
c906108c SS |
524 | { |
525 | CORE_ADDR prologue_start; | |
526 | CORE_ADDR prologue_end; | |
527 | CORE_ADDR current_pc; | |
94c30b78 | 528 | /* Which register has been copied to register n? */ |
da3c6d4a MS |
529 | int saved_reg[16]; |
530 | /* findmask: | |
531 | bit 0 - push { rlist } | |
532 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
533 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
534 | */ | |
535 | int findmask = 0; | |
c5aa993b | 536 | int i; |
c906108c | 537 | |
848cfffb | 538 | /* Don't try to scan dummy frames. */ |
07555a72 | 539 | if (fi != NULL |
50abf9e5 | 540 | && DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0)) |
848cfffb AC |
541 | return; |
542 | ||
50abf9e5 | 543 | if (find_pc_partial_function (get_frame_pc (fi), NULL, &prologue_start, &prologue_end)) |
c906108c SS |
544 | { |
545 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
546 | ||
94c30b78 | 547 | if (sal.line == 0) /* no line info, use current PC */ |
50abf9e5 | 548 | prologue_end = get_frame_pc (fi); |
c906108c | 549 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
94c30b78 | 550 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
551 | } |
552 | else | |
da3c6d4a MS |
553 | /* We're in the boondocks: allow for |
554 | 16 pushes, an add, and "mv fp,sp". */ | |
555 | prologue_end = prologue_start + 40; | |
c906108c | 556 | |
50abf9e5 | 557 | prologue_end = min (prologue_end, get_frame_pc (fi)); |
c906108c SS |
558 | |
559 | /* Initialize the saved register map. When register H is copied to | |
560 | register L, we will put H in saved_reg[L]. */ | |
561 | for (i = 0; i < 16; i++) | |
562 | saved_reg[i] = i; | |
563 | ||
564 | /* Search the prologue looking for instructions that set up the | |
da59e081 JM |
565 | frame pointer, adjust the stack pointer, and save registers. |
566 | Do this until all basic prolog instructions are found. */ | |
c906108c | 567 | |
da50a4b7 | 568 | get_frame_extra_info (fi)->framesize = 0; |
da59e081 JM |
569 | for (current_pc = prologue_start; |
570 | (current_pc < prologue_end) && ((findmask & 7) != 7); | |
571 | current_pc += 2) | |
c906108c SS |
572 | { |
573 | unsigned short insn; | |
574 | int regno; | |
575 | int offset; | |
576 | ||
577 | insn = read_memory_unsigned_integer (current_pc, 2); | |
578 | ||
c5aa993b | 579 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c | 580 | { |
da59e081 | 581 | int mask; |
94c30b78 | 582 | findmask |= 1; /* push found */ |
c906108c SS |
583 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
584 | whether to save LR (R14). */ | |
da59e081 | 585 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
c906108c | 586 | |
b8d5e71d | 587 | /* Calculate offsets of saved R0-R7 and LR. */ |
34e8f22d | 588 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
c906108c | 589 | if (mask & (1 << regno)) |
c5aa993b | 590 | { |
da50a4b7 | 591 | get_frame_extra_info (fi)->framesize += 4; |
b2fb4676 | 592 | get_frame_saved_regs (fi)[saved_reg[regno]] = |
da50a4b7 | 593 | -(get_frame_extra_info (fi)->framesize); |
da3c6d4a MS |
594 | /* Reset saved register map. */ |
595 | saved_reg[regno] = regno; | |
c906108c SS |
596 | } |
597 | } | |
da3c6d4a MS |
598 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
599 | sub sp, #simm */ | |
c906108c | 600 | { |
b8d5e71d | 601 | if ((findmask & 1) == 0) /* before push? */ |
da59e081 JM |
602 | continue; |
603 | else | |
94c30b78 | 604 | findmask |= 4; /* add/sub sp found */ |
da59e081 | 605 | |
94c30b78 MS |
606 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
607 | if (insn & 0x80) /* is it signed? (==subtracting) */ | |
da59e081 | 608 | { |
da50a4b7 | 609 | get_frame_extra_info (fi)->frameoffset += offset; |
da59e081 JM |
610 | offset = -offset; |
611 | } | |
da50a4b7 | 612 | get_frame_extra_info (fi)->framesize -= offset; |
c906108c SS |
613 | } |
614 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
615 | { | |
94c30b78 | 616 | findmask |= 2; /* setting of r7 found */ |
da50a4b7 | 617 | get_frame_extra_info (fi)->framereg = THUMB_FP_REGNUM; |
c3b4394c | 618 | /* get scaled offset */ |
da50a4b7 | 619 | get_frame_extra_info (fi)->frameoffset = (insn & 0xff) << 2; |
c906108c | 620 | } |
da59e081 | 621 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c | 622 | { |
94c30b78 | 623 | findmask |= 2; /* setting of r7 found */ |
da50a4b7 AC |
624 | get_frame_extra_info (fi)->framereg = THUMB_FP_REGNUM; |
625 | get_frame_extra_info (fi)->frameoffset = 0; | |
34e8f22d | 626 | saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; |
c906108c SS |
627 | } |
628 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
629 | { | |
da3c6d4a | 630 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 631 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
94c30b78 | 632 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
633 | } |
634 | else | |
da3c6d4a MS |
635 | /* Something in the prolog that we don't care about or some |
636 | instruction from outside the prolog scheduled here for | |
637 | optimization. */ | |
638 | continue; | |
c906108c SS |
639 | } |
640 | } | |
641 | ||
ed9a39eb | 642 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
643 | 1) the size of the stack frame |
644 | 2) which registers are saved on it | |
645 | 3) the offsets of saved regs | |
646 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
647 | This information is stored in the "extra" fields of the frame_info. |
648 | ||
96baa820 JM |
649 | There are two basic forms for the ARM prologue. The fixed argument |
650 | function call will look like: | |
ed9a39eb JM |
651 | |
652 | mov ip, sp | |
653 | stmfd sp!, {fp, ip, lr, pc} | |
654 | sub fp, ip, #4 | |
655 | [sub sp, sp, #4] | |
96baa820 | 656 | |
c906108c | 657 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
658 | IP -> 4 (caller's stack) |
659 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
660 | -4 LR (return address in caller) | |
661 | -8 IP (copy of caller's SP) | |
662 | -12 FP (caller's FP) | |
663 | SP -> -28 Local variables | |
664 | ||
c906108c | 665 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
666 | 28 bytes. The stmfd call can also save any of the vN registers it |
667 | plans to use, which increases the frame size accordingly. | |
668 | ||
669 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
670 | because the ARM Store instructions always store PC + 8 when you read | |
671 | the PC register. | |
ed9a39eb | 672 | |
96baa820 JM |
673 | A variable argument function call will look like: |
674 | ||
ed9a39eb JM |
675 | mov ip, sp |
676 | stmfd sp!, {a1, a2, a3, a4} | |
677 | stmfd sp!, {fp, ip, lr, pc} | |
678 | sub fp, ip, #20 | |
679 | ||
96baa820 | 680 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
681 | IP -> 20 (caller's stack) |
682 | 16 A4 | |
683 | 12 A3 | |
684 | 8 A2 | |
685 | 4 A1 | |
686 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
687 | -4 LR (return address in caller) | |
688 | -8 IP (copy of caller's SP) | |
689 | -12 FP (caller's FP) | |
690 | SP -> -28 Local variables | |
96baa820 JM |
691 | |
692 | The frame size would thus be 48 bytes, and the frame offset would be | |
693 | 28 bytes. | |
694 | ||
695 | There is another potential complication, which is that the optimizer | |
696 | will try to separate the store of fp in the "stmfd" instruction from | |
697 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
698 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
699 | ||
700 | Also, note, the original version of the ARM toolchain claimed that there | |
701 | should be an | |
702 | ||
703 | instruction at the end of the prologue. I have never seen GCC produce | |
704 | this, and the ARM docs don't mention it. We still test for it below in | |
705 | case it happens... | |
ed9a39eb JM |
706 | |
707 | */ | |
c906108c SS |
708 | |
709 | static void | |
ed9a39eb | 710 | arm_scan_prologue (struct frame_info *fi) |
c906108c SS |
711 | { |
712 | int regno, sp_offset, fp_offset; | |
16a0f3e7 | 713 | LONGEST return_value; |
c906108c SS |
714 | CORE_ADDR prologue_start, prologue_end, current_pc; |
715 | ||
c906108c | 716 | /* Assume there is no frame until proven otherwise. */ |
da50a4b7 AC |
717 | get_frame_extra_info (fi)->framereg = ARM_SP_REGNUM; |
718 | get_frame_extra_info (fi)->framesize = 0; | |
719 | get_frame_extra_info (fi)->frameoffset = 0; | |
c906108c SS |
720 | |
721 | /* Check for Thumb prologue. */ | |
50abf9e5 | 722 | if (arm_pc_is_thumb (get_frame_pc (fi))) |
c906108c SS |
723 | { |
724 | thumb_scan_prologue (fi); | |
c906108c SS |
725 | return; |
726 | } | |
727 | ||
728 | /* Find the function prologue. If we can't find the function in | |
729 | the symbol table, peek in the stack frame to find the PC. */ | |
50abf9e5 | 730 | if (find_pc_partial_function (get_frame_pc (fi), NULL, &prologue_start, &prologue_end)) |
c906108c | 731 | { |
2a451106 KB |
732 | /* One way to find the end of the prologue (which works well |
733 | for unoptimized code) is to do the following: | |
734 | ||
735 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
736 | ||
737 | if (sal.line == 0) | |
50abf9e5 | 738 | prologue_end = get_frame_pc (fi); |
2a451106 KB |
739 | else if (sal.end < prologue_end) |
740 | prologue_end = sal.end; | |
741 | ||
742 | This mechanism is very accurate so long as the optimizer | |
743 | doesn't move any instructions from the function body into the | |
744 | prologue. If this happens, sal.end will be the last | |
745 | instruction in the first hunk of prologue code just before | |
746 | the first instruction that the scheduler has moved from | |
747 | the body to the prologue. | |
748 | ||
749 | In order to make sure that we scan all of the prologue | |
750 | instructions, we use a slightly less accurate mechanism which | |
751 | may scan more than necessary. To help compensate for this | |
752 | lack of accuracy, the prologue scanning loop below contains | |
753 | several clauses which'll cause the loop to terminate early if | |
754 | an implausible prologue instruction is encountered. | |
755 | ||
756 | The expression | |
757 | ||
758 | prologue_start + 64 | |
759 | ||
760 | is a suitable endpoint since it accounts for the largest | |
761 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 762 | the scheduler. */ |
2a451106 KB |
763 | |
764 | if (prologue_end > prologue_start + 64) | |
765 | { | |
94c30b78 | 766 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 767 | } |
c906108c SS |
768 | } |
769 | else | |
770 | { | |
94c30b78 MS |
771 | /* Get address of the stmfd in the prologue of the callee; |
772 | the saved PC is the address of the stmfd + 8. */ | |
1e2330ba | 773 | if (!safe_read_memory_integer (get_frame_base (fi), 4, &return_value)) |
16a0f3e7 EZ |
774 | return; |
775 | else | |
776 | { | |
777 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
94c30b78 | 778 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 779 | } |
c906108c SS |
780 | } |
781 | ||
782 | /* Now search the prologue looking for instructions that set up the | |
96baa820 | 783 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 784 | |
96baa820 JM |
785 | Be careful, however, and if it doesn't look like a prologue, |
786 | don't try to scan it. If, for instance, a frameless function | |
787 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 788 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
789 | and other operations that rely on a knowledge of the stack |
790 | traceback. | |
791 | ||
792 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 793 | if we don't see this as the first insn, we will stop. |
c906108c | 794 | |
f43845b3 MS |
795 | [Note: This doesn't seem to be true any longer, so it's now an |
796 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 797 | |
f43845b3 MS |
798 | [Note further: The "mov ip,sp" only seems to be missing in |
799 | frameless functions at optimization level "-O2" or above, | |
800 | in which case it is often (but not always) replaced by | |
b8d5e71d | 801 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 802 | |
f43845b3 MS |
803 | sp_offset = fp_offset = 0; |
804 | ||
94c30b78 MS |
805 | for (current_pc = prologue_start; |
806 | current_pc < prologue_end; | |
f43845b3 | 807 | current_pc += 4) |
96baa820 | 808 | { |
d4473757 KB |
809 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
810 | ||
94c30b78 | 811 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 MS |
812 | { |
813 | continue; | |
814 | } | |
94c30b78 | 815 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 MS |
816 | { |
817 | /* Function is frameless: extra_info defaults OK? */ | |
818 | continue; | |
819 | } | |
820 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
821 | /* stmfd sp!, {..., fp, ip, lr, pc} |
822 | or | |
823 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 824 | { |
d4473757 | 825 | int mask = insn & 0xffff; |
ed9a39eb | 826 | |
94c30b78 | 827 | /* Calculate offsets of saved registers. */ |
34e8f22d | 828 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
829 | if (mask & (1 << regno)) |
830 | { | |
831 | sp_offset -= 4; | |
b2fb4676 | 832 | get_frame_saved_regs (fi)[regno] = sp_offset; |
d4473757 KB |
833 | } |
834 | } | |
b8d5e71d MS |
835 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
836 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
837 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
838 | { | |
839 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
840 | continue; | |
841 | } | |
842 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
843 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
844 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
845 | { |
846 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
847 | continue; | |
848 | } | |
d4473757 KB |
849 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
850 | { | |
94c30b78 MS |
851 | unsigned imm = insn & 0xff; /* immediate value */ |
852 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
853 | imm = (imm >> rot) | (imm << (32 - rot)); |
854 | fp_offset = -imm; | |
da50a4b7 | 855 | get_frame_extra_info (fi)->framereg = ARM_FP_REGNUM; |
d4473757 KB |
856 | } |
857 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
858 | { | |
94c30b78 MS |
859 | unsigned imm = insn & 0xff; /* immediate value */ |
860 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
861 | imm = (imm >> rot) | (imm << (32 - rot)); |
862 | sp_offset -= imm; | |
863 | } | |
864 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
865 | { | |
866 | sp_offset -= 12; | |
34e8f22d | 867 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
b2fb4676 | 868 | get_frame_saved_regs (fi)[regno] = sp_offset; |
d4473757 KB |
869 | } |
870 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ | |
871 | { | |
872 | int n_saved_fp_regs; | |
873 | unsigned int fp_start_reg, fp_bound_reg; | |
874 | ||
94c30b78 | 875 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 876 | { |
d4473757 KB |
877 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
878 | n_saved_fp_regs = 3; | |
879 | else | |
880 | n_saved_fp_regs = 1; | |
96baa820 | 881 | } |
d4473757 | 882 | else |
96baa820 | 883 | { |
d4473757 KB |
884 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
885 | n_saved_fp_regs = 2; | |
886 | else | |
887 | n_saved_fp_regs = 4; | |
96baa820 | 888 | } |
d4473757 | 889 | |
34e8f22d | 890 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
891 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
892 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
893 | { |
894 | sp_offset -= 12; | |
b2fb4676 | 895 | get_frame_saved_regs (fi)[fp_start_reg++] = sp_offset; |
96baa820 | 896 | } |
c906108c | 897 | } |
d4473757 | 898 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 899 | break; /* Condition not true, exit early */ |
b8d5e71d | 900 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 901 | break; /* Don't scan past a block load */ |
d4473757 KB |
902 | else |
903 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 904 | so we just skip what we don't recognize. */ |
d4473757 | 905 | continue; |
c906108c SS |
906 | } |
907 | ||
94c30b78 MS |
908 | /* The frame size is just the negative of the offset (from the |
909 | original SP) of the last thing thing we pushed on the stack. | |
910 | The frame offset is [new FP] - [new SP]. */ | |
da50a4b7 AC |
911 | get_frame_extra_info (fi)->framesize = -sp_offset; |
912 | if (get_frame_extra_info (fi)->framereg == ARM_FP_REGNUM) | |
913 | get_frame_extra_info (fi)->frameoffset = fp_offset - sp_offset; | |
d4473757 | 914 | else |
da50a4b7 | 915 | get_frame_extra_info (fi)->frameoffset = 0; |
c906108c SS |
916 | } |
917 | ||
ed9a39eb JM |
918 | /* Find REGNUM on the stack. Otherwise, it's in an active register. |
919 | One thing we might want to do here is to check REGNUM against the | |
920 | clobber mask, and somehow flag it as invalid if it isn't saved on | |
921 | the stack somewhere. This would provide a graceful failure mode | |
922 | when trying to get the value of caller-saves registers for an inner | |
923 | frame. */ | |
c906108c SS |
924 | |
925 | static CORE_ADDR | |
ed9a39eb | 926 | arm_find_callers_reg (struct frame_info *fi, int regnum) |
c906108c | 927 | { |
848cfffb AC |
928 | /* NOTE: cagney/2002-05-03: This function really shouldn't be |
929 | needed. Instead the (still being written) register unwind | |
930 | function could be called directly. */ | |
11c02a10 | 931 | for (; fi; fi = get_next_frame (fi)) |
848cfffb | 932 | { |
50abf9e5 | 933 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0)) |
848cfffb | 934 | { |
1e2330ba AC |
935 | return deprecated_read_register_dummy (get_frame_pc (fi), |
936 | get_frame_base (fi), regnum); | |
848cfffb | 937 | } |
b2fb4676 | 938 | else if (get_frame_saved_regs (fi)[regnum] != 0) |
848cfffb AC |
939 | { |
940 | /* NOTE: cagney/2002-05-03: This would normally need to | |
941 | handle ARM_SP_REGNUM as a special case as, according to | |
942 | the frame.h comments, saved_regs[SP_REGNUM] contains the | |
943 | SP value not its address. It appears that the ARM isn't | |
944 | doing this though. */ | |
b2fb4676 | 945 | return read_memory_integer (get_frame_saved_regs (fi)[regnum], |
848cfffb AC |
946 | REGISTER_RAW_SIZE (regnum)); |
947 | } | |
948 | } | |
c906108c SS |
949 | return read_register (regnum); |
950 | } | |
148754e5 RE |
951 | /* Function: frame_chain Given a GDB frame, determine the address of |
952 | the calling function's frame. This will be used to create a new | |
e9582e71 | 953 | GDB frame struct, and then DEPRECATED_INIT_EXTRA_FRAME_INFO and |
a5afb99f AC |
954 | DEPRECATED_INIT_FRAME_PC will be called for the new frame. For |
955 | ARM, we save the frame size when we initialize the frame_info. */ | |
c5aa993b | 956 | |
148754e5 | 957 | static CORE_ADDR |
ed9a39eb | 958 | arm_frame_chain (struct frame_info *fi) |
c906108c | 959 | { |
848cfffb | 960 | CORE_ADDR caller_pc; |
da50a4b7 | 961 | int framereg = get_frame_extra_info (fi)->framereg; |
c906108c | 962 | |
50abf9e5 | 963 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0)) |
848cfffb | 964 | /* A generic call dummy's frame is the same as caller's. */ |
1e2330ba | 965 | return get_frame_base (fi); |
848cfffb | 966 | |
50abf9e5 | 967 | if (get_frame_pc (fi) < LOWEST_PC) |
c906108c SS |
968 | return 0; |
969 | ||
970 | /* If the caller is the startup code, we're at the end of the chain. */ | |
8bedc050 | 971 | caller_pc = DEPRECATED_FRAME_SAVED_PC (fi); |
c906108c SS |
972 | |
973 | /* If the caller is Thumb and the caller is ARM, or vice versa, | |
974 | the frame register of the caller is different from ours. | |
975 | So we must scan the prologue of the caller to determine its | |
94c30b78 | 976 | frame register number. */ |
c3b4394c RE |
977 | /* XXX Fixme, we should try to do this without creating a temporary |
978 | caller_fi. */ | |
50abf9e5 | 979 | if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (get_frame_pc (fi))) |
c906108c | 980 | { |
f6c609c4 AC |
981 | struct cleanup *old_chain = make_cleanup (null_cleanup, NULL); |
982 | struct frame_info *caller_fi = | |
983 | deprecated_frame_xmalloc_with_cleanup (SIZEOF_FRAME_SAVED_REGS, | |
984 | sizeof (struct frame_extra_info)); | |
c3b4394c RE |
985 | |
986 | /* Now, scan the prologue and obtain the frame register. */ | |
f6c609c4 AC |
987 | deprecated_update_frame_pc_hack (caller_fi, caller_pc); |
988 | arm_scan_prologue (caller_fi); | |
da50a4b7 | 989 | framereg = get_frame_extra_info (caller_fi)->framereg; |
c3b4394c RE |
990 | |
991 | /* Deallocate the storage associated with the temporary frame | |
992 | created above. */ | |
993 | do_cleanups (old_chain); | |
c906108c SS |
994 | } |
995 | ||
996 | /* If the caller used a frame register, return its value. | |
997 | Otherwise, return the caller's stack pointer. */ | |
34e8f22d | 998 | if (framereg == ARM_FP_REGNUM || framereg == THUMB_FP_REGNUM) |
c906108c SS |
999 | return arm_find_callers_reg (fi, framereg); |
1000 | else | |
da50a4b7 | 1001 | return get_frame_base (fi) + get_frame_extra_info (fi)->framesize; |
c906108c SS |
1002 | } |
1003 | ||
ed9a39eb JM |
1004 | /* This function actually figures out the frame address for a given pc |
1005 | and sp. This is tricky because we sometimes don't use an explicit | |
1006 | frame pointer, and the previous stack pointer isn't necessarily | |
1007 | recorded on the stack. The only reliable way to get this info is | |
1008 | to examine the prologue. FROMLEAF is a little confusing, it means | |
1009 | this is the next frame up the chain AFTER a frameless function. If | |
1010 | this is true, then the frame value for this frame is still in the | |
1011 | fp register. */ | |
c906108c | 1012 | |
148754e5 | 1013 | static void |
ed9a39eb | 1014 | arm_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c SS |
1015 | { |
1016 | int reg; | |
f079148d | 1017 | CORE_ADDR sp; |
c906108c | 1018 | |
b2fb4676 | 1019 | if (get_frame_saved_regs (fi) == NULL) |
c3b4394c RE |
1020 | frame_saved_regs_zalloc (fi); |
1021 | ||
a00a19e9 | 1022 | frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); |
c3b4394c | 1023 | |
da50a4b7 AC |
1024 | get_frame_extra_info (fi)->framesize = 0; |
1025 | get_frame_extra_info (fi)->frameoffset = 0; | |
1026 | get_frame_extra_info (fi)->framereg = 0; | |
c3b4394c | 1027 | |
11c02a10 | 1028 | if (get_next_frame (fi)) |
8bedc050 | 1029 | deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi))); |
c906108c | 1030 | |
b2fb4676 | 1031 | memset (get_frame_saved_regs (fi), '\000', sizeof get_frame_saved_regs (fi)); |
c906108c | 1032 | |
da3c6d4a MS |
1033 | /* Compute stack pointer for this frame. We use this value for both |
1034 | the sigtramp and call dummy cases. */ | |
11c02a10 | 1035 | if (!get_next_frame (fi)) |
f079148d | 1036 | sp = read_sp(); |
11c02a10 | 1037 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (get_next_frame (fi)), 0, 0)) |
848cfffb AC |
1038 | /* For generic dummy frames, pull the value direct from the frame. |
1039 | Having an unwind function to do this would be nice. */ | |
11c02a10 AC |
1040 | sp = deprecated_read_register_dummy (get_frame_pc (get_next_frame (fi)), |
1041 | get_frame_base (get_next_frame (fi)), | |
135c175f | 1042 | ARM_SP_REGNUM); |
f079148d | 1043 | else |
da50a4b7 AC |
1044 | sp = (get_frame_base (get_next_frame (fi)) |
1045 | - get_frame_extra_info (get_next_frame (fi))->frameoffset | |
1046 | + get_frame_extra_info (get_next_frame (fi))->framesize); | |
f079148d | 1047 | |
d7bd68ca | 1048 | /* Determine whether or not we're in a sigtramp frame. |
5a203e44 AC |
1049 | Unfortunately, it isn't sufficient to test (get_frame_type (fi) |
1050 | == SIGTRAMP_FRAME) because this value is sometimes set after | |
e9582e71 | 1051 | invoking DEPRECATED_INIT_EXTRA_FRAME_INFO. So we test *both* |
5a203e44 AC |
1052 | (get_frame_type (fi) == SIGTRAMP_FRAME) and PC_IN_SIGTRAMP to |
1053 | determine if we need to use the sigcontext addresses for the | |
1054 | saved registers. | |
2a451106 | 1055 | |
d7bd68ca AC |
1056 | Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare |
1057 | against the name of the function, the code below will have to be | |
1058 | changed to first fetch the name of the function and then pass | |
1059 | this name to PC_IN_SIGTRAMP. */ | |
2a451106 | 1060 | |
5a203e44 AC |
1061 | /* FIXME: cagney/2002-11-18: This problem will go away once |
1062 | frame.c:get_prev_frame() is modified to set the frame's type | |
1063 | before calling functions like this. */ | |
1064 | ||
3bb04bdd | 1065 | if (SIGCONTEXT_REGISTER_ADDRESS_P () |
50abf9e5 | 1066 | && ((get_frame_type (fi) == SIGTRAMP_FRAME) || PC_IN_SIGTRAMP (get_frame_pc (fi), (char *)0))) |
2a451106 | 1067 | { |
2a451106 | 1068 | for (reg = 0; reg < NUM_REGS; reg++) |
b2fb4676 | 1069 | get_frame_saved_regs (fi)[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, get_frame_pc (fi), reg); |
2a451106 | 1070 | |
94c30b78 | 1071 | /* FIXME: What about thumb mode? */ |
da50a4b7 AC |
1072 | get_frame_extra_info (fi)->framereg = ARM_SP_REGNUM; |
1073 | deprecated_update_frame_base_hack (fi, read_memory_integer (get_frame_saved_regs (fi)[get_frame_extra_info (fi)->framereg], REGISTER_RAW_SIZE (get_frame_extra_info (fi)->framereg))); | |
1074 | get_frame_extra_info (fi)->framesize = 0; | |
1075 | get_frame_extra_info (fi)->frameoffset = 0; | |
2a451106 KB |
1076 | |
1077 | } | |
1078 | else | |
c906108c SS |
1079 | { |
1080 | arm_scan_prologue (fi); | |
1081 | ||
11c02a10 | 1082 | if (!get_next_frame (fi)) |
94c30b78 | 1083 | /* This is the innermost frame? */ |
da50a4b7 | 1084 | deprecated_update_frame_base_hack (fi, read_register (get_frame_extra_info (fi)->framereg)); |
11c02a10 | 1085 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (get_next_frame (fi)), 0, 0)) |
848cfffb AC |
1086 | /* Next inner most frame is a dummy, just grab its frame. |
1087 | Dummy frames always have the same FP as their caller. */ | |
11c02a10 | 1088 | deprecated_update_frame_base_hack (fi, get_frame_base (get_next_frame (fi))); |
da50a4b7 AC |
1089 | else if (get_frame_extra_info (fi)->framereg == ARM_FP_REGNUM |
1090 | || get_frame_extra_info (fi)->framereg == THUMB_FP_REGNUM) | |
ed9a39eb JM |
1091 | { |
1092 | /* not the innermost frame */ | |
94c30b78 | 1093 | /* If we have an FP, the callee saved it. */ |
da50a4b7 AC |
1094 | if (get_frame_saved_regs (get_next_frame (fi))[get_frame_extra_info (fi)->framereg] != 0) |
1095 | deprecated_update_frame_base_hack (fi, read_memory_integer (get_frame_saved_regs (get_next_frame (fi))[get_frame_extra_info (fi)->framereg], 4)); | |
ed9a39eb JM |
1096 | else if (fromleaf) |
1097 | /* If we were called by a frameless fn. then our frame is | |
94c30b78 | 1098 | still in the frame pointer register on the board... */ |
0ba6dca9 | 1099 | deprecated_update_frame_base_hack (fi, deprecated_read_fp ()); |
ed9a39eb | 1100 | } |
c906108c | 1101 | |
ed9a39eb JM |
1102 | /* Calculate actual addresses of saved registers using offsets |
1103 | determined by arm_scan_prologue. */ | |
c906108c | 1104 | for (reg = 0; reg < NUM_REGS; reg++) |
b2fb4676 | 1105 | if (get_frame_saved_regs (fi)[reg] != 0) |
da50a4b7 AC |
1106 | get_frame_saved_regs (fi)[reg] |
1107 | += (get_frame_base (fi) | |
1108 | + get_frame_extra_info (fi)->framesize | |
1109 | - get_frame_extra_info (fi)->frameoffset); | |
c906108c SS |
1110 | } |
1111 | } | |
1112 | ||
1113 | ||
34e8f22d | 1114 | /* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM |
ed9a39eb JM |
1115 | is saved in the stack anywhere, otherwise we get it from the |
1116 | registers. | |
c906108c SS |
1117 | |
1118 | The old definition of this function was a macro: | |
c5aa993b | 1119 | #define FRAME_SAVED_PC(FRAME) \ |
ed9a39eb | 1120 | ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */ |
c906108c | 1121 | |
148754e5 | 1122 | static CORE_ADDR |
ed9a39eb | 1123 | arm_frame_saved_pc (struct frame_info *fi) |
c906108c | 1124 | { |
848cfffb | 1125 | /* If a dummy frame, pull the PC out of the frame's register buffer. */ |
50abf9e5 | 1126 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0)) |
1e2330ba AC |
1127 | return deprecated_read_register_dummy (get_frame_pc (fi), |
1128 | get_frame_base (fi), ARM_PC_REGNUM); | |
848cfffb | 1129 | |
1e2330ba AC |
1130 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), |
1131 | (get_frame_base (fi) | |
da50a4b7 | 1132 | - get_frame_extra_info (fi)->frameoffset), |
1e2330ba | 1133 | get_frame_base (fi))) |
f079148d | 1134 | { |
b2fb4676 | 1135 | return read_memory_integer (get_frame_saved_regs (fi)[ARM_PC_REGNUM], |
34e8f22d | 1136 | REGISTER_RAW_SIZE (ARM_PC_REGNUM)); |
f079148d KB |
1137 | } |
1138 | else | |
c906108c | 1139 | { |
34e8f22d | 1140 | CORE_ADDR pc = arm_find_callers_reg (fi, ARM_LR_REGNUM); |
c906108c SS |
1141 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; |
1142 | } | |
1143 | } | |
1144 | ||
c906108c SS |
1145 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. |
1146 | Examine the Program Status Register to decide which state we're in. */ | |
1147 | ||
148754e5 RE |
1148 | static CORE_ADDR |
1149 | arm_read_fp (void) | |
c906108c | 1150 | { |
34e8f22d | 1151 | if (read_register (ARM_PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */ |
c906108c SS |
1152 | return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */ |
1153 | else | |
34e8f22d | 1154 | return read_register (ARM_FP_REGNUM); /* R11 if ARM */ |
c906108c SS |
1155 | } |
1156 | ||
148754e5 RE |
1157 | /* Store into a struct frame_saved_regs the addresses of the saved |
1158 | registers of frame described by FRAME_INFO. This includes special | |
1159 | registers such as PC and FP saved in special ways in the stack | |
1160 | frame. SP is even more special: the address we return for it IS | |
1161 | the sp for the next frame. */ | |
c906108c | 1162 | |
148754e5 | 1163 | static void |
c3b4394c | 1164 | arm_frame_init_saved_regs (struct frame_info *fip) |
c906108c | 1165 | { |
c3b4394c | 1166 | |
b2fb4676 | 1167 | if (get_frame_saved_regs (fip)) |
c3b4394c RE |
1168 | return; |
1169 | ||
1170 | arm_init_extra_frame_info (0, fip); | |
c906108c SS |
1171 | } |
1172 | ||
848cfffb AC |
1173 | /* Set the return address for a generic dummy frame. ARM uses the |
1174 | entry point. */ | |
1175 | ||
1176 | static CORE_ADDR | |
1177 | arm_push_return_address (CORE_ADDR pc, CORE_ADDR sp) | |
1178 | { | |
1179 | write_register (ARM_LR_REGNUM, CALL_DUMMY_ADDRESS ()); | |
1180 | return sp; | |
1181 | } | |
1182 | ||
148754e5 RE |
1183 | /* Push an empty stack frame, to record the current PC, etc. */ |
1184 | ||
1185 | static void | |
ed9a39eb | 1186 | arm_push_dummy_frame (void) |
c906108c | 1187 | { |
34e8f22d | 1188 | CORE_ADDR old_sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1189 | CORE_ADDR sp = old_sp; |
1190 | CORE_ADDR fp, prologue_start; | |
1191 | int regnum; | |
1192 | ||
1193 | /* Push the two dummy prologue instructions in reverse order, | |
1194 | so that they'll be in the correct low-to-high order in memory. */ | |
1195 | /* sub fp, ip, #4 */ | |
1196 | sp = push_word (sp, 0xe24cb004); | |
1197 | /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ | |
1198 | prologue_start = sp = push_word (sp, 0xe92ddfff); | |
1199 | ||
ed9a39eb JM |
1200 | /* Push a pointer to the dummy prologue + 12, because when stm |
1201 | instruction stores the PC, it stores the address of the stm | |
c906108c SS |
1202 | instruction itself plus 12. */ |
1203 | fp = sp = push_word (sp, prologue_start + 12); | |
c5aa993b | 1204 | |
f079148d | 1205 | /* Push the processor status. */ |
34e8f22d | 1206 | sp = push_word (sp, read_register (ARM_PS_REGNUM)); |
f079148d KB |
1207 | |
1208 | /* Push all 16 registers starting with r15. */ | |
34e8f22d | 1209 | for (regnum = ARM_PC_REGNUM; regnum >= 0; regnum--) |
c906108c | 1210 | sp = push_word (sp, read_register (regnum)); |
c5aa993b | 1211 | |
f079148d | 1212 | /* Update fp (for both Thumb and ARM) and sp. */ |
34e8f22d | 1213 | write_register (ARM_FP_REGNUM, fp); |
c906108c | 1214 | write_register (THUMB_FP_REGNUM, fp); |
34e8f22d | 1215 | write_register (ARM_SP_REGNUM, sp); |
c906108c SS |
1216 | } |
1217 | ||
b1e29e33 | 1218 | /* DEPRECATED_CALL_DUMMY_WORDS: |
6eb69eab RE |
1219 | This sequence of words is the instructions |
1220 | ||
1221 | mov lr,pc | |
1222 | mov pc,r4 | |
1223 | illegal | |
1224 | ||
1225 | Note this is 12 bytes. */ | |
1226 | ||
34e8f22d | 1227 | static LONGEST arm_call_dummy_words[] = |
6eb69eab RE |
1228 | { |
1229 | 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe | |
1230 | }; | |
1231 | ||
3fb4b924 RE |
1232 | /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy |
1233 | breakpoint to the proper address in the call dummy, so that | |
1234 | `finish' after a stop in a call dummy works. | |
1235 | ||
d7b486e7 RE |
1236 | FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an |
1237 | optimal solution, but the call to arm_fix_call_dummy is immediately | |
04714b91 AC |
1238 | followed by a call to call_function_by_hand, which is the only |
1239 | function where call_dummy_breakpoint_offset is actually used. */ | |
3fb4b924 RE |
1240 | |
1241 | ||
1242 | static void | |
1243 | arm_set_call_dummy_breakpoint_offset (void) | |
1244 | { | |
1245 | if (caller_is_thumb) | |
b1e29e33 | 1246 | set_gdbarch_deprecated_call_dummy_breakpoint_offset (current_gdbarch, 4); |
3fb4b924 | 1247 | else |
b1e29e33 | 1248 | set_gdbarch_deprecated_call_dummy_breakpoint_offset (current_gdbarch, 8); |
3fb4b924 RE |
1249 | } |
1250 | ||
c906108c | 1251 | /* Fix up the call dummy, based on whether the processor is currently |
ed9a39eb JM |
1252 | in Thumb or ARM mode, and whether the target function is Thumb or |
1253 | ARM. There are three different situations requiring three | |
c906108c SS |
1254 | different dummies: |
1255 | ||
1256 | * ARM calling ARM: uses the call dummy in tm-arm.h, which has already | |
c5aa993b | 1257 | been copied into the dummy parameter to this function. |
c906108c | 1258 | * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the |
c5aa993b | 1259 | "mov pc,r4" instruction patched to be a "bx r4" instead. |
c906108c | 1260 | * Thumb calling anything: uses the Thumb dummy defined below, which |
c5aa993b | 1261 | works for calling both ARM and Thumb functions. |
c906108c | 1262 | |
ed9a39eb JM |
1263 | All three call dummies expect to receive the target function |
1264 | address in R4, with the low bit set if it's a Thumb function. */ | |
c906108c | 1265 | |
34e8f22d | 1266 | static void |
ed9a39eb | 1267 | arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
ea7c478f | 1268 | struct value **args, struct type *type, int gcc_p) |
c906108c SS |
1269 | { |
1270 | static short thumb_dummy[4] = | |
1271 | { | |
c5aa993b JM |
1272 | 0xf000, 0xf801, /* bl label */ |
1273 | 0xdf18, /* swi 24 */ | |
1274 | 0x4720, /* label: bx r4 */ | |
c906108c SS |
1275 | }; |
1276 | static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */ | |
1277 | ||
94c30b78 | 1278 | /* Set flag indicating whether the current PC is in a Thumb function. */ |
c5aa993b | 1279 | caller_is_thumb = arm_pc_is_thumb (read_pc ()); |
3fb4b924 | 1280 | arm_set_call_dummy_breakpoint_offset (); |
c906108c | 1281 | |
ed9a39eb JM |
1282 | /* If the target function is Thumb, set the low bit of the function |
1283 | address. And if the CPU is currently in ARM mode, patch the | |
1284 | second instruction of call dummy to use a BX instruction to | |
1285 | switch to Thumb mode. */ | |
c906108c SS |
1286 | target_is_thumb = arm_pc_is_thumb (fun); |
1287 | if (target_is_thumb) | |
1288 | { | |
1289 | fun |= 1; | |
1290 | if (!caller_is_thumb) | |
1291 | store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4); | |
1292 | } | |
1293 | ||
1294 | /* If the CPU is currently in Thumb mode, use the Thumb call dummy | |
1295 | instead of the ARM one that's already been copied. This will | |
1296 | work for both Thumb and ARM target functions. */ | |
1297 | if (caller_is_thumb) | |
1298 | { | |
1299 | int i; | |
1300 | char *p = dummy; | |
1301 | int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]); | |
1302 | ||
1303 | for (i = 0; i < len; i++) | |
1304 | { | |
1305 | store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]); | |
1306 | p += sizeof (thumb_dummy[0]); | |
1307 | } | |
1308 | } | |
1309 | ||
ed9a39eb | 1310 | /* Put the target address in r4; the call dummy will copy this to |
94c30b78 | 1311 | the PC. */ |
c906108c SS |
1312 | write_register (4, fun); |
1313 | } | |
1314 | ||
da3c6d4a MS |
1315 | /* Pop the current frame. So long as the frame info has been |
1316 | initialized properly (see arm_init_extra_frame_info), this code | |
1317 | works for dummy frames as well as regular frames. I.e, there's no | |
1318 | need to have a special case for dummy frames. */ | |
148754e5 | 1319 | static void |
ed9a39eb | 1320 | arm_pop_frame (void) |
c906108c | 1321 | { |
c906108c | 1322 | int regnum; |
8b93c638 | 1323 | struct frame_info *frame = get_current_frame (); |
da50a4b7 AC |
1324 | CORE_ADDR old_SP = (get_frame_base (frame) |
1325 | - get_frame_extra_info (frame)->frameoffset | |
1326 | + get_frame_extra_info (frame)->framesize); | |
c906108c | 1327 | |
1e2330ba AC |
1328 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
1329 | get_frame_base (frame), | |
1330 | get_frame_base (frame))) | |
848cfffb AC |
1331 | { |
1332 | generic_pop_dummy_frame (); | |
1333 | flush_cached_frames (); | |
1334 | return; | |
1335 | } | |
1336 | ||
f079148d | 1337 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
b2fb4676 | 1338 | if (get_frame_saved_regs (frame)[regnum] != 0) |
f079148d | 1339 | write_register (regnum, |
b2fb4676 | 1340 | read_memory_integer (get_frame_saved_regs (frame)[regnum], |
f079148d | 1341 | REGISTER_RAW_SIZE (regnum))); |
8b93c638 | 1342 | |
8bedc050 | 1343 | write_register (ARM_PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame)); |
34e8f22d | 1344 | write_register (ARM_SP_REGNUM, old_SP); |
c906108c SS |
1345 | |
1346 | flush_cached_frames (); | |
1347 | } | |
1348 | ||
2dd604e7 RE |
1349 | /* When arguments must be pushed onto the stack, they go on in reverse |
1350 | order. The code below implements a FILO (stack) to do this. */ | |
1351 | ||
1352 | struct stack_item | |
1353 | { | |
1354 | int len; | |
1355 | struct stack_item *prev; | |
1356 | void *data; | |
1357 | }; | |
1358 | ||
1359 | static struct stack_item * | |
1360 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
1361 | { | |
1362 | struct stack_item *si; | |
1363 | si = xmalloc (sizeof (struct stack_item)); | |
226c7fbc | 1364 | si->data = xmalloc (len); |
2dd604e7 RE |
1365 | si->len = len; |
1366 | si->prev = prev; | |
1367 | memcpy (si->data, contents, len); | |
1368 | return si; | |
1369 | } | |
1370 | ||
1371 | static struct stack_item * | |
1372 | pop_stack_item (struct stack_item *si) | |
1373 | { | |
1374 | struct stack_item *dead = si; | |
1375 | si = si->prev; | |
1376 | xfree (dead->data); | |
1377 | xfree (dead); | |
1378 | return si; | |
1379 | } | |
1380 | ||
1381 | /* We currently only support passing parameters in integer registers. This | |
1382 | conforms with GCC's default model. Several other variants exist and | |
1383 | we should probably support some of them based on the selected ABI. */ | |
1384 | ||
1385 | static CORE_ADDR | |
6a65450a AC |
1386 | arm_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
1387 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
1388 | struct value **args, CORE_ADDR sp, int struct_return, | |
1389 | CORE_ADDR struct_addr) | |
2dd604e7 RE |
1390 | { |
1391 | int argnum; | |
1392 | int argreg; | |
1393 | int nstack; | |
1394 | struct stack_item *si = NULL; | |
1395 | ||
6a65450a AC |
1396 | /* Set the return address. For the ARM, the return breakpoint is |
1397 | always at BP_ADDR. */ | |
2dd604e7 | 1398 | /* XXX Fix for Thumb. */ |
6a65450a | 1399 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
1400 | |
1401 | /* Walk through the list of args and determine how large a temporary | |
1402 | stack is required. Need to take care here as structs may be | |
1403 | passed on the stack, and we have to to push them. */ | |
1404 | nstack = 0; | |
1405 | ||
1406 | argreg = ARM_A1_REGNUM; | |
1407 | nstack = 0; | |
1408 | ||
1409 | /* Some platforms require a double-word aligned stack. Make sure sp | |
1410 | is correctly aligned before we start. We always do this even if | |
1411 | it isn't really needed -- it can never hurt things. */ | |
b1e29e33 | 1412 | sp &= ~(CORE_ADDR)(2 * DEPRECATED_REGISTER_SIZE - 1); |
2dd604e7 RE |
1413 | |
1414 | /* The struct_return pointer occupies the first parameter | |
1415 | passing register. */ | |
1416 | if (struct_return) | |
1417 | { | |
1418 | if (arm_debug) | |
1419 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n", | |
1420 | REGISTER_NAME (argreg), paddr (struct_addr)); | |
1421 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
1422 | argreg++; | |
1423 | } | |
1424 | ||
1425 | for (argnum = 0; argnum < nargs; argnum++) | |
1426 | { | |
1427 | int len; | |
1428 | struct type *arg_type; | |
1429 | struct type *target_type; | |
1430 | enum type_code typecode; | |
1431 | char *val; | |
1432 | ||
1433 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1434 | len = TYPE_LENGTH (arg_type); | |
1435 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1436 | typecode = TYPE_CODE (arg_type); | |
1437 | val = VALUE_CONTENTS (args[argnum]); | |
1438 | ||
1439 | /* If the argument is a pointer to a function, and it is a | |
1440 | Thumb function, create a LOCAL copy of the value and set | |
1441 | the THUMB bit in it. */ | |
1442 | if (TYPE_CODE_PTR == typecode | |
1443 | && target_type != NULL | |
1444 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
1445 | { | |
7c0b4a20 | 1446 | CORE_ADDR regval = extract_unsigned_integer (val, len); |
2dd604e7 RE |
1447 | if (arm_pc_is_thumb (regval)) |
1448 | { | |
1449 | val = alloca (len); | |
fbd9dcd3 | 1450 | store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval)); |
2dd604e7 RE |
1451 | } |
1452 | } | |
1453 | ||
1454 | /* Copy the argument to general registers or the stack in | |
1455 | register-sized pieces. Large arguments are split between | |
1456 | registers and stack. */ | |
1457 | while (len > 0) | |
1458 | { | |
b1e29e33 | 1459 | int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE; |
2dd604e7 RE |
1460 | |
1461 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
1462 | { | |
1463 | /* The argument is being passed in a general purpose | |
1464 | register. */ | |
7c0b4a20 | 1465 | CORE_ADDR regval = extract_unsigned_integer (val, partial_len); |
2dd604e7 RE |
1466 | if (arm_debug) |
1467 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
1468 | argnum, REGISTER_NAME (argreg), | |
b1e29e33 | 1469 | phex (regval, DEPRECATED_REGISTER_SIZE)); |
2dd604e7 RE |
1470 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
1471 | argreg++; | |
1472 | } | |
1473 | else | |
1474 | { | |
1475 | /* Push the arguments onto the stack. */ | |
1476 | if (arm_debug) | |
1477 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", | |
1478 | argnum, nstack); | |
b1e29e33 AC |
1479 | si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE); |
1480 | nstack += DEPRECATED_REGISTER_SIZE; | |
2dd604e7 RE |
1481 | } |
1482 | ||
1483 | len -= partial_len; | |
1484 | val += partial_len; | |
1485 | } | |
1486 | } | |
1487 | /* If we have an odd number of words to push, then decrement the stack | |
1488 | by one word now, so first stack argument will be dword aligned. */ | |
1489 | if (nstack & 4) | |
1490 | sp -= 4; | |
1491 | ||
1492 | while (si) | |
1493 | { | |
1494 | sp -= si->len; | |
1495 | write_memory (sp, si->data, si->len); | |
1496 | si = pop_stack_item (si); | |
1497 | } | |
1498 | ||
1499 | /* Finally, update teh SP register. */ | |
1500 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
1501 | ||
1502 | return sp; | |
1503 | } | |
1504 | ||
c906108c | 1505 | static void |
ed9a39eb | 1506 | print_fpu_flags (int flags) |
c906108c | 1507 | { |
c5aa993b JM |
1508 | if (flags & (1 << 0)) |
1509 | fputs ("IVO ", stdout); | |
1510 | if (flags & (1 << 1)) | |
1511 | fputs ("DVZ ", stdout); | |
1512 | if (flags & (1 << 2)) | |
1513 | fputs ("OFL ", stdout); | |
1514 | if (flags & (1 << 3)) | |
1515 | fputs ("UFL ", stdout); | |
1516 | if (flags & (1 << 4)) | |
1517 | fputs ("INX ", stdout); | |
1518 | putchar ('\n'); | |
c906108c SS |
1519 | } |
1520 | ||
5e74b15c RE |
1521 | /* Print interesting information about the floating point processor |
1522 | (if present) or emulator. */ | |
34e8f22d | 1523 | static void |
d855c300 | 1524 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1525 | struct frame_info *frame, const char *args) |
c906108c | 1526 | { |
34e8f22d | 1527 | register unsigned long status = read_register (ARM_FPS_REGNUM); |
c5aa993b JM |
1528 | int type; |
1529 | ||
1530 | type = (status >> 24) & 127; | |
1531 | printf ("%s FPU type %d\n", | |
ed9a39eb | 1532 | (status & (1 << 31)) ? "Hardware" : "Software", |
c5aa993b JM |
1533 | type); |
1534 | fputs ("mask: ", stdout); | |
1535 | print_fpu_flags (status >> 16); | |
1536 | fputs ("flags: ", stdout); | |
1537 | print_fpu_flags (status); | |
c906108c SS |
1538 | } |
1539 | ||
34e8f22d RE |
1540 | /* Return the GDB type object for the "standard" data type of data in |
1541 | register N. */ | |
1542 | ||
1543 | static struct type * | |
032758dc AC |
1544 | arm_register_type (int regnum) |
1545 | { | |
34e8f22d | 1546 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
032758dc | 1547 | { |
d7449b42 | 1548 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
032758dc AC |
1549 | return builtin_type_arm_ext_big; |
1550 | else | |
1551 | return builtin_type_arm_ext_littlebyte_bigword; | |
1552 | } | |
1553 | else | |
1554 | return builtin_type_int32; | |
1555 | } | |
1556 | ||
34e8f22d RE |
1557 | /* Index within `registers' of the first byte of the space for |
1558 | register N. */ | |
1559 | ||
1560 | static int | |
1561 | arm_register_byte (int regnum) | |
1562 | { | |
1563 | if (regnum < ARM_F0_REGNUM) | |
1564 | return regnum * INT_REGISTER_RAW_SIZE; | |
1565 | else if (regnum < ARM_PS_REGNUM) | |
1566 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
1567 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_RAW_SIZE); | |
1568 | else | |
1569 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
1570 | + NUM_FREGS * FP_REGISTER_RAW_SIZE | |
1571 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); | |
1572 | } | |
1573 | ||
1574 | /* Number of bytes of storage in the actual machine representation for | |
1575 | register N. All registers are 4 bytes, except fp0 - fp7, which are | |
1576 | 12 bytes in length. */ | |
1577 | ||
1578 | static int | |
1579 | arm_register_raw_size (int regnum) | |
1580 | { | |
1581 | if (regnum < ARM_F0_REGNUM) | |
1582 | return INT_REGISTER_RAW_SIZE; | |
1583 | else if (regnum < ARM_FPS_REGNUM) | |
1584 | return FP_REGISTER_RAW_SIZE; | |
1585 | else | |
1586 | return STATUS_REGISTER_SIZE; | |
1587 | } | |
1588 | ||
1589 | /* Number of bytes of storage in a program's representation | |
1590 | for register N. */ | |
1591 | static int | |
1592 | arm_register_virtual_size (int regnum) | |
1593 | { | |
1594 | if (regnum < ARM_F0_REGNUM) | |
1595 | return INT_REGISTER_VIRTUAL_SIZE; | |
1596 | else if (regnum < ARM_FPS_REGNUM) | |
1597 | return FP_REGISTER_VIRTUAL_SIZE; | |
1598 | else | |
1599 | return STATUS_REGISTER_SIZE; | |
1600 | } | |
1601 | ||
26216b98 AC |
1602 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
1603 | static int | |
1604 | arm_register_sim_regno (int regnum) | |
1605 | { | |
1606 | int reg = regnum; | |
1607 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
1608 | ||
1609 | if (reg < NUM_GREGS) | |
1610 | return SIM_ARM_R0_REGNUM + reg; | |
1611 | reg -= NUM_GREGS; | |
1612 | ||
1613 | if (reg < NUM_FREGS) | |
1614 | return SIM_ARM_FP0_REGNUM + reg; | |
1615 | reg -= NUM_FREGS; | |
1616 | ||
1617 | if (reg < NUM_SREGS) | |
1618 | return SIM_ARM_FPS_REGNUM + reg; | |
1619 | reg -= NUM_SREGS; | |
1620 | ||
1621 | internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum); | |
1622 | } | |
34e8f22d | 1623 | |
a37b3cc0 AC |
1624 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1625 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1626 | It is thought that this is is the floating-point register format on | |
1627 | little-endian systems. */ | |
c906108c | 1628 | |
ed9a39eb | 1629 | static void |
b508a996 RE |
1630 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
1631 | void *dbl) | |
c906108c | 1632 | { |
a37b3cc0 | 1633 | DOUBLEST d; |
d7449b42 | 1634 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1635 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1636 | else | |
1637 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1638 | ptr, &d); | |
b508a996 | 1639 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
1640 | } |
1641 | ||
34e8f22d | 1642 | static void |
b508a996 | 1643 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr) |
c906108c | 1644 | { |
a37b3cc0 | 1645 | DOUBLEST d; |
b508a996 | 1646 | floatformat_to_doublest (fmt, ptr, &d); |
d7449b42 | 1647 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1648 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1649 | else | |
1650 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1651 | &d, dbl); | |
c906108c | 1652 | } |
ed9a39eb | 1653 | |
c906108c | 1654 | static int |
ed9a39eb | 1655 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1656 | { |
1657 | if (cond == INST_AL || cond == INST_NV) | |
1658 | return 1; | |
1659 | ||
1660 | switch (cond) | |
1661 | { | |
1662 | case INST_EQ: | |
1663 | return ((status_reg & FLAG_Z) != 0); | |
1664 | case INST_NE: | |
1665 | return ((status_reg & FLAG_Z) == 0); | |
1666 | case INST_CS: | |
1667 | return ((status_reg & FLAG_C) != 0); | |
1668 | case INST_CC: | |
1669 | return ((status_reg & FLAG_C) == 0); | |
1670 | case INST_MI: | |
1671 | return ((status_reg & FLAG_N) != 0); | |
1672 | case INST_PL: | |
1673 | return ((status_reg & FLAG_N) == 0); | |
1674 | case INST_VS: | |
1675 | return ((status_reg & FLAG_V) != 0); | |
1676 | case INST_VC: | |
1677 | return ((status_reg & FLAG_V) == 0); | |
1678 | case INST_HI: | |
1679 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1680 | case INST_LS: | |
1681 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1682 | case INST_GE: | |
1683 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1684 | case INST_LT: | |
1685 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1686 | case INST_GT: | |
1687 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1688 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1689 | case INST_LE: |
1690 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1691 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1692 | } |
1693 | return 1; | |
1694 | } | |
1695 | ||
9512d7fd | 1696 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1697 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1698 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1699 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1700 | #define sbits(obj,st,fn) \ | |
1701 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1702 | #define BranchDest(addr,instr) \ | |
1703 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1704 | #define ARM_PC_32 1 | |
1705 | ||
1706 | static unsigned long | |
ed9a39eb JM |
1707 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1708 | unsigned long status_reg) | |
c906108c SS |
1709 | { |
1710 | unsigned long res, shift; | |
1711 | int rm = bits (inst, 0, 3); | |
1712 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1713 | |
1714 | if (bit (inst, 4)) | |
c906108c SS |
1715 | { |
1716 | int rs = bits (inst, 8, 11); | |
1717 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1718 | } | |
1719 | else | |
1720 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1721 | |
1722 | res = (rm == 15 | |
c906108c | 1723 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1724 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1725 | : read_register (rm)); |
1726 | ||
1727 | switch (shifttype) | |
1728 | { | |
c5aa993b | 1729 | case 0: /* LSL */ |
c906108c SS |
1730 | res = shift >= 32 ? 0 : res << shift; |
1731 | break; | |
c5aa993b JM |
1732 | |
1733 | case 1: /* LSR */ | |
c906108c SS |
1734 | res = shift >= 32 ? 0 : res >> shift; |
1735 | break; | |
1736 | ||
c5aa993b JM |
1737 | case 2: /* ASR */ |
1738 | if (shift >= 32) | |
1739 | shift = 31; | |
c906108c SS |
1740 | res = ((res & 0x80000000L) |
1741 | ? ~((~res) >> shift) : res >> shift); | |
1742 | break; | |
1743 | ||
c5aa993b | 1744 | case 3: /* ROR/RRX */ |
c906108c SS |
1745 | shift &= 31; |
1746 | if (shift == 0) | |
1747 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1748 | else | |
c5aa993b | 1749 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1750 | break; |
1751 | } | |
1752 | ||
1753 | return res & 0xffffffff; | |
1754 | } | |
1755 | ||
c906108c SS |
1756 | /* Return number of 1-bits in VAL. */ |
1757 | ||
1758 | static int | |
ed9a39eb | 1759 | bitcount (unsigned long val) |
c906108c SS |
1760 | { |
1761 | int nbits; | |
1762 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1763 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1764 | return nbits; |
1765 | } | |
1766 | ||
34e8f22d | 1767 | CORE_ADDR |
ed9a39eb | 1768 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1769 | { |
c5aa993b | 1770 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1771 | unsigned short inst1 = read_memory_integer (pc, 2); |
94c30b78 | 1772 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1773 | unsigned long offset; |
1774 | ||
1775 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1776 | { | |
1777 | CORE_ADDR sp; | |
1778 | ||
1779 | /* Fetch the saved PC from the stack. It's stored above | |
1780 | all of the other registers. */ | |
b1e29e33 | 1781 | offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE; |
34e8f22d | 1782 | sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1783 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); |
1784 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1785 | if (nextpc == pc) | |
1786 | error ("Infinite loop detected"); | |
1787 | } | |
1788 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1789 | { | |
34e8f22d | 1790 | unsigned long status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1791 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1792 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1793 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1794 | } | |
1795 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1796 | { | |
1797 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1798 | } | |
1799 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ | |
1800 | { | |
1801 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1802 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c SS |
1803 | nextpc = pc_val + offset; |
1804 | } | |
1805 | ||
1806 | return nextpc; | |
1807 | } | |
1808 | ||
34e8f22d | 1809 | CORE_ADDR |
ed9a39eb | 1810 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1811 | { |
1812 | unsigned long pc_val; | |
1813 | unsigned long this_instr; | |
1814 | unsigned long status; | |
1815 | CORE_ADDR nextpc; | |
1816 | ||
1817 | if (arm_pc_is_thumb (pc)) | |
1818 | return thumb_get_next_pc (pc); | |
1819 | ||
1820 | pc_val = (unsigned long) pc; | |
1821 | this_instr = read_memory_integer (pc, 4); | |
34e8f22d | 1822 | status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1823 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1824 | |
1825 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1826 | { | |
1827 | switch (bits (this_instr, 24, 27)) | |
1828 | { | |
c5aa993b | 1829 | case 0x0: |
94c30b78 | 1830 | case 0x1: /* data processing */ |
c5aa993b JM |
1831 | case 0x2: |
1832 | case 0x3: | |
c906108c SS |
1833 | { |
1834 | unsigned long operand1, operand2, result = 0; | |
1835 | unsigned long rn; | |
1836 | int c; | |
c5aa993b | 1837 | |
c906108c SS |
1838 | if (bits (this_instr, 12, 15) != 15) |
1839 | break; | |
1840 | ||
1841 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1842 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
c906108c SS |
1843 | error ("Illegal update to pc in instruction"); |
1844 | ||
1845 | /* Multiply into PC */ | |
1846 | c = (status & FLAG_C) ? 1 : 0; | |
1847 | rn = bits (this_instr, 16, 19); | |
1848 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1849 | |
c906108c SS |
1850 | if (bit (this_instr, 25)) |
1851 | { | |
1852 | unsigned long immval = bits (this_instr, 0, 7); | |
1853 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1854 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1855 | & 0xffffffff; | |
c906108c | 1856 | } |
c5aa993b | 1857 | else /* operand 2 is a shifted register */ |
c906108c | 1858 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1859 | |
c906108c SS |
1860 | switch (bits (this_instr, 21, 24)) |
1861 | { | |
c5aa993b | 1862 | case 0x0: /*and */ |
c906108c SS |
1863 | result = operand1 & operand2; |
1864 | break; | |
1865 | ||
c5aa993b | 1866 | case 0x1: /*eor */ |
c906108c SS |
1867 | result = operand1 ^ operand2; |
1868 | break; | |
1869 | ||
c5aa993b | 1870 | case 0x2: /*sub */ |
c906108c SS |
1871 | result = operand1 - operand2; |
1872 | break; | |
1873 | ||
c5aa993b | 1874 | case 0x3: /*rsb */ |
c906108c SS |
1875 | result = operand2 - operand1; |
1876 | break; | |
1877 | ||
c5aa993b | 1878 | case 0x4: /*add */ |
c906108c SS |
1879 | result = operand1 + operand2; |
1880 | break; | |
1881 | ||
c5aa993b | 1882 | case 0x5: /*adc */ |
c906108c SS |
1883 | result = operand1 + operand2 + c; |
1884 | break; | |
1885 | ||
c5aa993b | 1886 | case 0x6: /*sbc */ |
c906108c SS |
1887 | result = operand1 - operand2 + c; |
1888 | break; | |
1889 | ||
c5aa993b | 1890 | case 0x7: /*rsc */ |
c906108c SS |
1891 | result = operand2 - operand1 + c; |
1892 | break; | |
1893 | ||
c5aa993b JM |
1894 | case 0x8: |
1895 | case 0x9: | |
1896 | case 0xa: | |
1897 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1898 | result = (unsigned long) nextpc; |
1899 | break; | |
1900 | ||
c5aa993b | 1901 | case 0xc: /*orr */ |
c906108c SS |
1902 | result = operand1 | operand2; |
1903 | break; | |
1904 | ||
c5aa993b | 1905 | case 0xd: /*mov */ |
c906108c SS |
1906 | /* Always step into a function. */ |
1907 | result = operand2; | |
c5aa993b | 1908 | break; |
c906108c | 1909 | |
c5aa993b | 1910 | case 0xe: /*bic */ |
c906108c SS |
1911 | result = operand1 & ~operand2; |
1912 | break; | |
1913 | ||
c5aa993b | 1914 | case 0xf: /*mvn */ |
c906108c SS |
1915 | result = ~operand2; |
1916 | break; | |
1917 | } | |
1918 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1919 | ||
1920 | if (nextpc == pc) | |
1921 | error ("Infinite loop detected"); | |
1922 | break; | |
1923 | } | |
c5aa993b JM |
1924 | |
1925 | case 0x4: | |
1926 | case 0x5: /* data transfer */ | |
1927 | case 0x6: | |
1928 | case 0x7: | |
c906108c SS |
1929 | if (bit (this_instr, 20)) |
1930 | { | |
1931 | /* load */ | |
1932 | if (bits (this_instr, 12, 15) == 15) | |
1933 | { | |
1934 | /* rd == pc */ | |
c5aa993b | 1935 | unsigned long rn; |
c906108c | 1936 | unsigned long base; |
c5aa993b | 1937 | |
c906108c SS |
1938 | if (bit (this_instr, 22)) |
1939 | error ("Illegal update to pc in instruction"); | |
1940 | ||
1941 | /* byte write to PC */ | |
1942 | rn = bits (this_instr, 16, 19); | |
1943 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1944 | if (bit (this_instr, 24)) | |
1945 | { | |
1946 | /* pre-indexed */ | |
1947 | int c = (status & FLAG_C) ? 1 : 0; | |
1948 | unsigned long offset = | |
c5aa993b | 1949 | (bit (this_instr, 25) |
ed9a39eb | 1950 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1951 | : bits (this_instr, 0, 11)); |
c906108c SS |
1952 | |
1953 | if (bit (this_instr, 23)) | |
1954 | base += offset; | |
1955 | else | |
1956 | base -= offset; | |
1957 | } | |
c5aa993b | 1958 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1959 | 4); |
c5aa993b | 1960 | |
c906108c SS |
1961 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1962 | ||
1963 | if (nextpc == pc) | |
1964 | error ("Infinite loop detected"); | |
1965 | } | |
1966 | } | |
1967 | break; | |
c5aa993b JM |
1968 | |
1969 | case 0x8: | |
1970 | case 0x9: /* block transfer */ | |
c906108c SS |
1971 | if (bit (this_instr, 20)) |
1972 | { | |
1973 | /* LDM */ | |
1974 | if (bit (this_instr, 15)) | |
1975 | { | |
1976 | /* loading pc */ | |
1977 | int offset = 0; | |
1978 | ||
1979 | if (bit (this_instr, 23)) | |
1980 | { | |
1981 | /* up */ | |
1982 | unsigned long reglist = bits (this_instr, 0, 14); | |
1983 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1984 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1985 | offset += 4; |
1986 | } | |
1987 | else if (bit (this_instr, 24)) | |
1988 | offset = -4; | |
c5aa993b | 1989 | |
c906108c | 1990 | { |
c5aa993b JM |
1991 | unsigned long rn_val = |
1992 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
1993 | nextpc = |
1994 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1995 | + offset), |
c906108c SS |
1996 | 4); |
1997 | } | |
1998 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1999 | if (nextpc == pc) | |
2000 | error ("Infinite loop detected"); | |
2001 | } | |
2002 | } | |
2003 | break; | |
c5aa993b JM |
2004 | |
2005 | case 0xb: /* branch & link */ | |
2006 | case 0xa: /* branch */ | |
c906108c SS |
2007 | { |
2008 | nextpc = BranchDest (pc, this_instr); | |
2009 | ||
2010 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
2011 | if (nextpc == pc) | |
2012 | error ("Infinite loop detected"); | |
2013 | break; | |
2014 | } | |
c5aa993b JM |
2015 | |
2016 | case 0xc: | |
2017 | case 0xd: | |
2018 | case 0xe: /* coproc ops */ | |
2019 | case 0xf: /* SWI */ | |
c906108c SS |
2020 | break; |
2021 | ||
2022 | default: | |
97e03143 | 2023 | fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n"); |
c906108c SS |
2024 | return (pc); |
2025 | } | |
2026 | } | |
2027 | ||
2028 | return nextpc; | |
2029 | } | |
2030 | ||
9512d7fd FN |
2031 | /* single_step() is called just before we want to resume the inferior, |
2032 | if we want to single-step it but there is no hardware or kernel | |
2033 | single-step support. We find the target of the coming instruction | |
2034 | and breakpoint it. | |
2035 | ||
94c30b78 MS |
2036 | single_step() is also called just after the inferior stops. If we |
2037 | had set up a simulated single-step, we undo our damage. */ | |
9512d7fd | 2038 | |
34e8f22d RE |
2039 | static void |
2040 | arm_software_single_step (enum target_signal sig, int insert_bpt) | |
9512d7fd | 2041 | { |
b8d5e71d | 2042 | static int next_pc; /* State between setting and unsetting. */ |
9512d7fd FN |
2043 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ |
2044 | ||
2045 | if (insert_bpt) | |
2046 | { | |
34e8f22d | 2047 | next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
80fcf3f0 | 2048 | target_insert_breakpoint (next_pc, break_mem); |
9512d7fd FN |
2049 | } |
2050 | else | |
80fcf3f0 | 2051 | target_remove_breakpoint (next_pc, break_mem); |
9512d7fd | 2052 | } |
9512d7fd | 2053 | |
c906108c SS |
2054 | #include "bfd-in2.h" |
2055 | #include "libcoff.h" | |
2056 | ||
2057 | static int | |
ed9a39eb | 2058 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
2059 | { |
2060 | if (arm_pc_is_thumb (memaddr)) | |
2061 | { | |
c5aa993b JM |
2062 | static asymbol *asym; |
2063 | static combined_entry_type ce; | |
2064 | static struct coff_symbol_struct csym; | |
27cddce2 | 2065 | static struct bfd fake_bfd; |
c5aa993b | 2066 | static bfd_target fake_target; |
c906108c SS |
2067 | |
2068 | if (csym.native == NULL) | |
2069 | { | |
da3c6d4a MS |
2070 | /* Create a fake symbol vector containing a Thumb symbol. |
2071 | This is solely so that the code in print_insn_little_arm() | |
2072 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
2073 | the presence of a Thumb symbol and switch to decoding | |
2074 | Thumb instructions. */ | |
c5aa993b JM |
2075 | |
2076 | fake_target.flavour = bfd_target_coff_flavour; | |
2077 | fake_bfd.xvec = &fake_target; | |
c906108c | 2078 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
2079 | csym.native = &ce; |
2080 | csym.symbol.the_bfd = &fake_bfd; | |
2081 | csym.symbol.name = "fake"; | |
2082 | asym = (asymbol *) & csym; | |
c906108c | 2083 | } |
c5aa993b | 2084 | |
c906108c | 2085 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 2086 | info->symbols = &asym; |
c906108c SS |
2087 | } |
2088 | else | |
2089 | info->symbols = NULL; | |
c5aa993b | 2090 | |
d7449b42 | 2091 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
2092 | return print_insn_big_arm (memaddr, info); |
2093 | else | |
2094 | return print_insn_little_arm (memaddr, info); | |
2095 | } | |
2096 | ||
66e810cd RE |
2097 | /* The following define instruction sequences that will cause ARM |
2098 | cpu's to take an undefined instruction trap. These are used to | |
2099 | signal a breakpoint to GDB. | |
2100 | ||
2101 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
2102 | modes. A different instruction is required for each mode. The ARM | |
2103 | cpu's can also be big or little endian. Thus four different | |
2104 | instructions are needed to support all cases. | |
2105 | ||
2106 | Note: ARMv4 defines several new instructions that will take the | |
2107 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
2108 | not in fact add the new instructions. The new undefined | |
2109 | instructions in ARMv4 are all instructions that had no defined | |
2110 | behaviour in earlier chips. There is no guarantee that they will | |
2111 | raise an exception, but may be treated as NOP's. In practice, it | |
2112 | may only safe to rely on instructions matching: | |
2113 | ||
2114 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
2115 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
2116 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
2117 | ||
2118 | Even this may only true if the condition predicate is true. The | |
2119 | following use a condition predicate of ALWAYS so it is always TRUE. | |
2120 | ||
2121 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
2122 | and NetBSD all use a software interrupt rather than an undefined | |
2123 | instruction to force a trap. This can be handled by by the | |
2124 | abi-specific code during establishment of the gdbarch vector. */ | |
2125 | ||
2126 | ||
d7b486e7 RE |
2127 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
2128 | override these definitions. */ | |
66e810cd RE |
2129 | #ifndef ARM_LE_BREAKPOINT |
2130 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
2131 | #endif | |
2132 | #ifndef ARM_BE_BREAKPOINT | |
2133 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
2134 | #endif | |
2135 | #ifndef THUMB_LE_BREAKPOINT | |
2136 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
2137 | #endif | |
2138 | #ifndef THUMB_BE_BREAKPOINT | |
2139 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
2140 | #endif | |
2141 | ||
2142 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
2143 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
2144 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
2145 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
2146 | ||
34e8f22d RE |
2147 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
2148 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
2149 | breakpoint should be used. It returns a pointer to a string of |
2150 | bytes that encode a breakpoint instruction, stores the length of | |
2151 | the string to *lenptr, and adjusts the program counter (if | |
2152 | necessary) to point to the actual memory location where the | |
c906108c SS |
2153 | breakpoint should be inserted. */ |
2154 | ||
34e8f22d RE |
2155 | /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting |
2156 | breakpoints and storing their handles instread of what was in | |
2157 | memory. It is nice that this is the same size as a handle - | |
94c30b78 | 2158 | otherwise remote-rdp will have to change. */ |
34e8f22d | 2159 | |
ab89facf | 2160 | static const unsigned char * |
ed9a39eb | 2161 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 2162 | { |
66e810cd RE |
2163 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2164 | ||
c906108c SS |
2165 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) |
2166 | { | |
66e810cd RE |
2167 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
2168 | *lenptr = tdep->thumb_breakpoint_size; | |
2169 | return tdep->thumb_breakpoint; | |
c906108c SS |
2170 | } |
2171 | else | |
2172 | { | |
66e810cd RE |
2173 | *lenptr = tdep->arm_breakpoint_size; |
2174 | return tdep->arm_breakpoint; | |
c906108c SS |
2175 | } |
2176 | } | |
ed9a39eb JM |
2177 | |
2178 | /* Extract from an array REGBUF containing the (raw) register state a | |
2179 | function return value of type TYPE, and copy that, in virtual | |
2180 | format, into VALBUF. */ | |
2181 | ||
34e8f22d | 2182 | static void |
ed9a39eb | 2183 | arm_extract_return_value (struct type *type, |
b508a996 RE |
2184 | struct regcache *regs, |
2185 | void *dst) | |
ed9a39eb | 2186 | { |
b508a996 RE |
2187 | bfd_byte *valbuf = dst; |
2188 | ||
ed9a39eb | 2189 | if (TYPE_CODE_FLT == TYPE_CODE (type)) |
08216dd7 | 2190 | { |
fd50bc42 | 2191 | switch (arm_get_fp_model (current_gdbarch)) |
08216dd7 RE |
2192 | { |
2193 | case ARM_FLOAT_FPA: | |
b508a996 RE |
2194 | { |
2195 | /* The value is in register F0 in internal format. We need to | |
2196 | extract the raw value and then convert it to the desired | |
2197 | internal type. */ | |
2198 | bfd_byte tmpbuf[FP_REGISTER_RAW_SIZE]; | |
2199 | ||
2200 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
2201 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
2202 | valbuf); | |
2203 | } | |
08216dd7 RE |
2204 | break; |
2205 | ||
fd50bc42 | 2206 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2207 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2208 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
2209 | if (TYPE_LENGTH (type) > 4) | |
2210 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
2211 | valbuf + INT_REGISTER_RAW_SIZE); | |
08216dd7 RE |
2212 | break; |
2213 | ||
2214 | default: | |
2215 | internal_error | |
2216 | (__FILE__, __LINE__, | |
2217 | "arm_extract_return_value: Floating point model not supported"); | |
2218 | break; | |
2219 | } | |
2220 | } | |
b508a996 RE |
2221 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2222 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2223 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2224 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2225 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2226 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2227 | { | |
2228 | /* If the the type is a plain integer, then the access is | |
2229 | straight-forward. Otherwise we have to play around a bit more. */ | |
2230 | int len = TYPE_LENGTH (type); | |
2231 | int regno = ARM_A1_REGNUM; | |
2232 | ULONGEST tmp; | |
2233 | ||
2234 | while (len > 0) | |
2235 | { | |
2236 | /* By using store_unsigned_integer we avoid having to do | |
2237 | anything special for small big-endian values. */ | |
2238 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2239 | store_unsigned_integer (valbuf, | |
2240 | (len > INT_REGISTER_RAW_SIZE | |
2241 | ? INT_REGISTER_RAW_SIZE : len), | |
2242 | tmp); | |
2243 | len -= INT_REGISTER_RAW_SIZE; | |
2244 | valbuf += INT_REGISTER_RAW_SIZE; | |
2245 | } | |
2246 | } | |
ed9a39eb | 2247 | else |
b508a996 RE |
2248 | { |
2249 | /* For a structure or union the behaviour is as if the value had | |
2250 | been stored to word-aligned memory and then loaded into | |
2251 | registers with 32-bit load instruction(s). */ | |
2252 | int len = TYPE_LENGTH (type); | |
2253 | int regno = ARM_A1_REGNUM; | |
2254 | bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE]; | |
2255 | ||
2256 | while (len > 0) | |
2257 | { | |
2258 | regcache_cooked_read (regs, regno++, tmpbuf); | |
2259 | memcpy (valbuf, tmpbuf, | |
2260 | len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len); | |
2261 | len -= INT_REGISTER_RAW_SIZE; | |
2262 | valbuf += INT_REGISTER_RAW_SIZE; | |
2263 | } | |
2264 | } | |
34e8f22d RE |
2265 | } |
2266 | ||
67255d04 RE |
2267 | /* Extract from an array REGBUF containing the (raw) register state |
2268 | the address in which a function should return its structure value. */ | |
2269 | ||
2270 | static CORE_ADDR | |
95f95911 | 2271 | arm_extract_struct_value_address (struct regcache *regcache) |
67255d04 | 2272 | { |
95f95911 MS |
2273 | ULONGEST ret; |
2274 | ||
2275 | regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret); | |
2276 | return ret; | |
67255d04 RE |
2277 | } |
2278 | ||
2279 | /* Will a function return an aggregate type in memory or in a | |
2280 | register? Return 0 if an aggregate type can be returned in a | |
2281 | register, 1 if it must be returned in memory. */ | |
2282 | ||
2283 | static int | |
2284 | arm_use_struct_convention (int gcc_p, struct type *type) | |
2285 | { | |
2286 | int nRc; | |
2287 | register enum type_code code; | |
2288 | ||
2289 | /* In the ARM ABI, "integer" like aggregate types are returned in | |
2290 | registers. For an aggregate type to be integer like, its size | |
b1e29e33 AC |
2291 | must be less than or equal to DEPRECATED_REGISTER_SIZE and the |
2292 | offset of each addressable subfield must be zero. Note that bit | |
2293 | fields are not addressable, and all addressable subfields of | |
2294 | unions always start at offset zero. | |
67255d04 RE |
2295 | |
2296 | This function is based on the behaviour of GCC 2.95.1. | |
2297 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2298 | ||
2299 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2300 | parameters correctly for a function returning the following | |
2301 | structure: struct { float f;}; This should be returned in memory, | |
2302 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2303 | know of any way to detect if a function like the above has been | |
2304 | compiled with the correct calling convention. */ | |
2305 | ||
2306 | /* All aggregate types that won't fit in a register must be returned | |
2307 | in memory. */ | |
b1e29e33 | 2308 | if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE) |
67255d04 RE |
2309 | { |
2310 | return 1; | |
2311 | } | |
2312 | ||
2313 | /* The only aggregate types that can be returned in a register are | |
2314 | structs and unions. Arrays must be returned in memory. */ | |
2315 | code = TYPE_CODE (type); | |
2316 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2317 | { | |
2318 | return 1; | |
2319 | } | |
2320 | ||
2321 | /* Assume all other aggregate types can be returned in a register. | |
2322 | Run a check for structures, unions and arrays. */ | |
2323 | nRc = 0; | |
2324 | ||
2325 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2326 | { | |
2327 | int i; | |
2328 | /* Need to check if this struct/union is "integer" like. For | |
2329 | this to be true, its size must be less than or equal to | |
b1e29e33 AC |
2330 | DEPRECATED_REGISTER_SIZE and the offset of each addressable |
2331 | subfield must be zero. Note that bit fields are not | |
2332 | addressable, and unions always start at offset zero. If any | |
2333 | of the subfields is a floating point type, the struct/union | |
2334 | cannot be an integer type. */ | |
67255d04 RE |
2335 | |
2336 | /* For each field in the object, check: | |
2337 | 1) Is it FP? --> yes, nRc = 1; | |
2338 | 2) Is it addressable (bitpos != 0) and | |
2339 | not packed (bitsize == 0)? | |
2340 | --> yes, nRc = 1 | |
2341 | */ | |
2342 | ||
2343 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2344 | { | |
2345 | enum type_code field_type_code; | |
2346 | field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i)); | |
2347 | ||
2348 | /* Is it a floating point type field? */ | |
2349 | if (field_type_code == TYPE_CODE_FLT) | |
2350 | { | |
2351 | nRc = 1; | |
2352 | break; | |
2353 | } | |
2354 | ||
2355 | /* If bitpos != 0, then we have to care about it. */ | |
2356 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2357 | { | |
2358 | /* Bitfields are not addressable. If the field bitsize is | |
2359 | zero, then the field is not packed. Hence it cannot be | |
2360 | a bitfield or any other packed type. */ | |
2361 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2362 | { | |
2363 | nRc = 1; | |
2364 | break; | |
2365 | } | |
2366 | } | |
2367 | } | |
2368 | } | |
2369 | ||
2370 | return nRc; | |
2371 | } | |
2372 | ||
34e8f22d RE |
2373 | /* Write into appropriate registers a function return value of type |
2374 | TYPE, given in virtual format. */ | |
2375 | ||
2376 | static void | |
b508a996 RE |
2377 | arm_store_return_value (struct type *type, struct regcache *regs, |
2378 | const void *src) | |
34e8f22d | 2379 | { |
b508a996 RE |
2380 | const bfd_byte *valbuf = src; |
2381 | ||
34e8f22d RE |
2382 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
2383 | { | |
7bbcf283 | 2384 | char buf[ARM_MAX_REGISTER_RAW_SIZE]; |
34e8f22d | 2385 | |
fd50bc42 | 2386 | switch (arm_get_fp_model (current_gdbarch)) |
08216dd7 RE |
2387 | { |
2388 | case ARM_FLOAT_FPA: | |
2389 | ||
b508a996 RE |
2390 | convert_to_extended (floatformat_from_type (type), buf, valbuf); |
2391 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); | |
08216dd7 RE |
2392 | break; |
2393 | ||
fd50bc42 | 2394 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2395 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2396 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
2397 | if (TYPE_LENGTH (type) > 4) | |
2398 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
2399 | valbuf + INT_REGISTER_RAW_SIZE); | |
08216dd7 RE |
2400 | break; |
2401 | ||
2402 | default: | |
2403 | internal_error | |
2404 | (__FILE__, __LINE__, | |
2405 | "arm_store_return_value: Floating point model not supported"); | |
2406 | break; | |
2407 | } | |
34e8f22d | 2408 | } |
b508a996 RE |
2409 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2410 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2411 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2412 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2413 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2414 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2415 | { | |
2416 | if (TYPE_LENGTH (type) <= 4) | |
2417 | { | |
2418 | /* Values of one word or less are zero/sign-extended and | |
2419 | returned in r0. */ | |
2420 | bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE]; | |
2421 | LONGEST val = unpack_long (type, valbuf); | |
2422 | ||
2423 | store_signed_integer (tmpbuf, INT_REGISTER_RAW_SIZE, val); | |
2424 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); | |
2425 | } | |
2426 | else | |
2427 | { | |
2428 | /* Integral values greater than one word are stored in consecutive | |
2429 | registers starting with r0. This will always be a multiple of | |
2430 | the regiser size. */ | |
2431 | int len = TYPE_LENGTH (type); | |
2432 | int regno = ARM_A1_REGNUM; | |
2433 | ||
2434 | while (len > 0) | |
2435 | { | |
2436 | regcache_cooked_write (regs, regno++, valbuf); | |
2437 | len -= INT_REGISTER_RAW_SIZE; | |
2438 | valbuf += INT_REGISTER_RAW_SIZE; | |
2439 | } | |
2440 | } | |
2441 | } | |
34e8f22d | 2442 | else |
b508a996 RE |
2443 | { |
2444 | /* For a structure or union the behaviour is as if the value had | |
2445 | been stored to word-aligned memory and then loaded into | |
2446 | registers with 32-bit load instruction(s). */ | |
2447 | int len = TYPE_LENGTH (type); | |
2448 | int regno = ARM_A1_REGNUM; | |
2449 | bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE]; | |
2450 | ||
2451 | while (len > 0) | |
2452 | { | |
2453 | memcpy (tmpbuf, valbuf, | |
2454 | len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len); | |
2455 | regcache_cooked_write (regs, regno++, tmpbuf); | |
2456 | len -= INT_REGISTER_RAW_SIZE; | |
2457 | valbuf += INT_REGISTER_RAW_SIZE; | |
2458 | } | |
2459 | } | |
34e8f22d RE |
2460 | } |
2461 | ||
9df628e0 RE |
2462 | static int |
2463 | arm_get_longjmp_target (CORE_ADDR *pc) | |
2464 | { | |
2465 | CORE_ADDR jb_addr; | |
2466 | char buf[INT_REGISTER_RAW_SIZE]; | |
2467 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2468 | ||
2469 | jb_addr = read_register (ARM_A1_REGNUM); | |
2470 | ||
2471 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
2472 | INT_REGISTER_RAW_SIZE)) | |
2473 | return 0; | |
2474 | ||
7c0b4a20 | 2475 | *pc = extract_unsigned_integer (buf, INT_REGISTER_RAW_SIZE); |
9df628e0 RE |
2476 | return 1; |
2477 | } | |
2478 | ||
ed9a39eb | 2479 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
c906108c SS |
2480 | |
2481 | int | |
ed9a39eb | 2482 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2483 | { |
2484 | CORE_ADDR start_addr; | |
2485 | ||
ed9a39eb JM |
2486 | /* Find the starting address of the function containing the PC. If |
2487 | the caller didn't give us a name, look it up at the same time. */ | |
94c30b78 MS |
2488 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
2489 | &start_addr, NULL)) | |
c906108c SS |
2490 | return 0; |
2491 | ||
2492 | return strncmp (name, "_call_via_r", 11) == 0; | |
2493 | } | |
2494 | ||
ed9a39eb JM |
2495 | /* If PC is in a Thumb call or return stub, return the address of the |
2496 | target PC, which is in a register. The thunk functions are called | |
2497 | _called_via_xx, where x is the register name. The possible names | |
2498 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2499 | |
2500 | CORE_ADDR | |
ed9a39eb | 2501 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2502 | { |
c5aa993b | 2503 | char *name; |
c906108c SS |
2504 | CORE_ADDR start_addr; |
2505 | ||
2506 | /* Find the starting address and name of the function containing the PC. */ | |
2507 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2508 | return 0; | |
2509 | ||
2510 | /* Call thunks always start with "_call_via_". */ | |
2511 | if (strncmp (name, "_call_via_", 10) == 0) | |
2512 | { | |
ed9a39eb JM |
2513 | /* Use the name suffix to determine which register contains the |
2514 | target PC. */ | |
c5aa993b JM |
2515 | static char *table[15] = |
2516 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2517 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2518 | }; | |
c906108c SS |
2519 | int regno; |
2520 | ||
2521 | for (regno = 0; regno <= 14; regno++) | |
2522 | if (strcmp (&name[10], table[regno]) == 0) | |
2523 | return read_register (regno); | |
2524 | } | |
ed9a39eb | 2525 | |
c5aa993b | 2526 | return 0; /* not a stub */ |
c906108c SS |
2527 | } |
2528 | ||
afd7eef0 RE |
2529 | static void |
2530 | set_arm_command (char *args, int from_tty) | |
2531 | { | |
2532 | printf_unfiltered ("\"set arm\" must be followed by an apporpriate subcommand.\n"); | |
2533 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); | |
2534 | } | |
2535 | ||
2536 | static void | |
2537 | show_arm_command (char *args, int from_tty) | |
2538 | { | |
26304000 | 2539 | cmd_show_list (showarmcmdlist, from_tty, ""); |
afd7eef0 RE |
2540 | } |
2541 | ||
fd50bc42 RE |
2542 | enum arm_float_model |
2543 | arm_get_fp_model (struct gdbarch *gdbarch) | |
2544 | { | |
2545 | if (arm_fp_model == ARM_FLOAT_AUTO) | |
2546 | return gdbarch_tdep (gdbarch)->fp_model; | |
2547 | ||
2548 | return arm_fp_model; | |
2549 | } | |
2550 | ||
2551 | static void | |
2552 | arm_set_fp (struct gdbarch *gdbarch) | |
2553 | { | |
2554 | enum arm_float_model fp_model = arm_get_fp_model (gdbarch); | |
2555 | ||
2556 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE | |
2557 | && (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA)) | |
2558 | { | |
2559 | set_gdbarch_double_format (gdbarch, | |
2560 | &floatformat_ieee_double_littlebyte_bigword); | |
2561 | set_gdbarch_long_double_format | |
2562 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2563 | } | |
2564 | else | |
2565 | { | |
2566 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); | |
2567 | set_gdbarch_long_double_format (gdbarch, | |
2568 | &floatformat_ieee_double_little); | |
2569 | } | |
2570 | } | |
2571 | ||
2572 | static void | |
2573 | set_fp_model_sfunc (char *args, int from_tty, | |
2574 | struct cmd_list_element *c) | |
2575 | { | |
2576 | enum arm_float_model fp_model; | |
2577 | ||
2578 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
2579 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
2580 | { | |
2581 | arm_fp_model = fp_model; | |
2582 | break; | |
2583 | } | |
2584 | ||
2585 | if (fp_model == ARM_FLOAT_LAST) | |
2586 | internal_error (__FILE__, __LINE__, "Invalid fp model accepted: %s.", | |
2587 | current_fp_model); | |
2588 | ||
2589 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) | |
2590 | arm_set_fp (current_gdbarch); | |
2591 | } | |
2592 | ||
2593 | static void | |
2594 | show_fp_model (char *args, int from_tty, | |
2595 | struct cmd_list_element *c) | |
2596 | { | |
2597 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2598 | ||
2599 | if (arm_fp_model == ARM_FLOAT_AUTO | |
2600 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) | |
2601 | printf_filtered (" - the default for the current ABI is \"%s\".\n", | |
2602 | fp_model_strings[tdep->fp_model]); | |
2603 | } | |
2604 | ||
afd7eef0 RE |
2605 | /* If the user changes the register disassembly style used for info |
2606 | register and other commands, we have to also switch the style used | |
2607 | in opcodes for disassembly output. This function is run in the "set | |
2608 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
2609 | |
2610 | static void | |
afd7eef0 | 2611 | set_disassembly_style_sfunc (char *args, int from_tty, |
bc90b915 FN |
2612 | struct cmd_list_element *c) |
2613 | { | |
afd7eef0 | 2614 | set_disassembly_style (); |
bc90b915 FN |
2615 | } |
2616 | \f | |
966fbf70 | 2617 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 2618 | static const char * |
34e8f22d | 2619 | arm_register_name (int i) |
966fbf70 RE |
2620 | { |
2621 | return arm_register_names[i]; | |
2622 | } | |
2623 | ||
bc90b915 | 2624 | static void |
afd7eef0 | 2625 | set_disassembly_style (void) |
bc90b915 FN |
2626 | { |
2627 | const char *setname, *setdesc, **regnames; | |
2628 | int numregs, j; | |
2629 | ||
afd7eef0 | 2630 | /* Find the style that the user wants in the opcodes table. */ |
bc90b915 FN |
2631 | int current = 0; |
2632 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
afd7eef0 RE |
2633 | while ((disassembly_style != setname) |
2634 | && (current < num_disassembly_options)) | |
bc90b915 FN |
2635 | get_arm_regnames (++current, &setname, &setdesc, ®names); |
2636 | current_option = current; | |
2637 | ||
94c30b78 | 2638 | /* Fill our copy. */ |
bc90b915 FN |
2639 | for (j = 0; j < numregs; j++) |
2640 | arm_register_names[j] = (char *) regnames[j]; | |
2641 | ||
94c30b78 | 2642 | /* Adjust case. */ |
34e8f22d | 2643 | if (isupper (*regnames[ARM_PC_REGNUM])) |
bc90b915 | 2644 | { |
34e8f22d RE |
2645 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
2646 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; | |
bc90b915 FN |
2647 | } |
2648 | else | |
2649 | { | |
34e8f22d RE |
2650 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
2651 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; | |
bc90b915 FN |
2652 | } |
2653 | ||
94c30b78 | 2654 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2655 | set_arm_regname_option (current); |
2656 | } | |
2657 | ||
afd7eef0 RE |
2658 | /* arm_othernames implements the "othernames" command. This is deprecated |
2659 | by the "set arm disassembly" command. */ | |
bc90b915 FN |
2660 | |
2661 | static void | |
2662 | arm_othernames (char *names, int n) | |
2663 | { | |
94c30b78 | 2664 | /* Circle through the various flavors. */ |
afd7eef0 | 2665 | current_option = (current_option + 1) % num_disassembly_options; |
bc90b915 | 2666 | |
afd7eef0 RE |
2667 | disassembly_style = valid_disassembly_styles[current_option]; |
2668 | set_disassembly_style (); | |
bc90b915 FN |
2669 | } |
2670 | ||
a42dd537 KB |
2671 | /* Fetch, and possibly build, an appropriate link_map_offsets structure |
2672 | for ARM linux targets using the struct offsets defined in <link.h>. | |
2673 | Note, however, that link.h is not actually referred to in this file. | |
2674 | Instead, the relevant structs offsets were obtained from examining | |
2675 | link.h. (We can't refer to link.h from this file because the host | |
2676 | system won't necessarily have it, or if it does, the structs which | |
94c30b78 | 2677 | it defines will refer to the host system, not the target). */ |
a42dd537 KB |
2678 | |
2679 | struct link_map_offsets * | |
2680 | arm_linux_svr4_fetch_link_map_offsets (void) | |
2681 | { | |
2682 | static struct link_map_offsets lmo; | |
2683 | static struct link_map_offsets *lmp = 0; | |
2684 | ||
2685 | if (lmp == 0) | |
2686 | { | |
2687 | lmp = &lmo; | |
2688 | ||
2689 | lmo.r_debug_size = 8; /* Actual size is 20, but this is all we | |
94c30b78 | 2690 | need. */ |
a42dd537 KB |
2691 | |
2692 | lmo.r_map_offset = 4; | |
2693 | lmo.r_map_size = 4; | |
2694 | ||
2695 | lmo.link_map_size = 20; /* Actual size is 552, but this is all we | |
94c30b78 | 2696 | need. */ |
a42dd537 KB |
2697 | |
2698 | lmo.l_addr_offset = 0; | |
2699 | lmo.l_addr_size = 4; | |
2700 | ||
2701 | lmo.l_name_offset = 4; | |
2702 | lmo.l_name_size = 4; | |
2703 | ||
2704 | lmo.l_next_offset = 12; | |
2705 | lmo.l_next_size = 4; | |
2706 | ||
2707 | lmo.l_prev_offset = 16; | |
2708 | lmo.l_prev_size = 4; | |
2709 | } | |
2710 | ||
2711 | return lmp; | |
2712 | } | |
2713 | ||
082fc60d RE |
2714 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2715 | function. */ | |
2716 | ||
2717 | static int | |
2718 | coff_sym_is_thumb (int val) | |
2719 | { | |
2720 | return (val == C_THUMBEXT || | |
2721 | val == C_THUMBSTAT || | |
2722 | val == C_THUMBEXTFUNC || | |
2723 | val == C_THUMBSTATFUNC || | |
2724 | val == C_THUMBLABEL); | |
2725 | } | |
2726 | ||
2727 | /* arm_coff_make_msymbol_special() | |
2728 | arm_elf_make_msymbol_special() | |
2729 | ||
2730 | These functions test whether the COFF or ELF symbol corresponds to | |
2731 | an address in thumb code, and set a "special" bit in a minimal | |
2732 | symbol to indicate that it does. */ | |
2733 | ||
34e8f22d | 2734 | static void |
082fc60d RE |
2735 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2736 | { | |
2737 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2738 | STT_ARM_TFUNC). */ | |
2739 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2740 | == STT_LOPROC) | |
2741 | MSYMBOL_SET_SPECIAL (msym); | |
2742 | } | |
2743 | ||
34e8f22d | 2744 | static void |
082fc60d RE |
2745 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2746 | { | |
2747 | if (coff_sym_is_thumb (val)) | |
2748 | MSYMBOL_SET_SPECIAL (msym); | |
2749 | } | |
2750 | ||
97e03143 | 2751 | \f |
70f80edf JT |
2752 | static enum gdb_osabi |
2753 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 2754 | { |
70f80edf JT |
2755 | unsigned int elfosabi, eflags; |
2756 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; | |
97e03143 | 2757 | |
70f80edf | 2758 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 2759 | |
70f80edf | 2760 | switch (elfosabi) |
97e03143 | 2761 | { |
70f80edf JT |
2762 | case ELFOSABI_NONE: |
2763 | /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the | |
2764 | file are conforming to the base specification for that machine | |
2765 | (there are no OS-specific extensions). In order to determine the | |
2766 | real OS in use we must look for OS notes that have been added. */ | |
2767 | bfd_map_over_sections (abfd, | |
2768 | generic_elf_osabi_sniff_abi_tag_sections, | |
2769 | &osabi); | |
2770 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2771 | { |
70f80edf JT |
2772 | /* Existing ARM tools don't set this field, so look at the EI_FLAGS |
2773 | field for more information. */ | |
2774 | eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags); | |
2775 | switch (eflags) | |
97e03143 | 2776 | { |
70f80edf JT |
2777 | case EF_ARM_EABI_VER1: |
2778 | osabi = GDB_OSABI_ARM_EABI_V1; | |
97e03143 RE |
2779 | break; |
2780 | ||
70f80edf JT |
2781 | case EF_ARM_EABI_VER2: |
2782 | osabi = GDB_OSABI_ARM_EABI_V2; | |
97e03143 RE |
2783 | break; |
2784 | ||
70f80edf JT |
2785 | case EF_ARM_EABI_UNKNOWN: |
2786 | /* Assume GNU tools. */ | |
2787 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2788 | break; |
2789 | ||
70f80edf JT |
2790 | default: |
2791 | internal_error (__FILE__, __LINE__, | |
2792 | "arm_elf_osabi_sniffer: Unknown ARM EABI " | |
2793 | "version 0x%x", eflags); | |
97e03143 RE |
2794 | } |
2795 | } | |
70f80edf | 2796 | break; |
97e03143 | 2797 | |
70f80edf JT |
2798 | case ELFOSABI_ARM: |
2799 | /* GNU tools use this value. Check note sections in this case, | |
2800 | as well. */ | |
97e03143 | 2801 | bfd_map_over_sections (abfd, |
70f80edf JT |
2802 | generic_elf_osabi_sniff_abi_tag_sections, |
2803 | &osabi); | |
2804 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2805 | { |
70f80edf JT |
2806 | /* Assume APCS ABI. */ |
2807 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2808 | } |
2809 | break; | |
2810 | ||
97e03143 | 2811 | case ELFOSABI_FREEBSD: |
70f80edf JT |
2812 | osabi = GDB_OSABI_FREEBSD_ELF; |
2813 | break; | |
97e03143 | 2814 | |
70f80edf JT |
2815 | case ELFOSABI_NETBSD: |
2816 | osabi = GDB_OSABI_NETBSD_ELF; | |
2817 | break; | |
97e03143 | 2818 | |
70f80edf JT |
2819 | case ELFOSABI_LINUX: |
2820 | osabi = GDB_OSABI_LINUX; | |
2821 | break; | |
97e03143 RE |
2822 | } |
2823 | ||
70f80edf | 2824 | return osabi; |
97e03143 RE |
2825 | } |
2826 | ||
70f80edf | 2827 | \f |
da3c6d4a MS |
2828 | /* Initialize the current architecture based on INFO. If possible, |
2829 | re-use an architecture from ARCHES, which is a list of | |
2830 | architectures already created during this debugging session. | |
97e03143 | 2831 | |
da3c6d4a MS |
2832 | Called e.g. at program startup, when reading a core file, and when |
2833 | reading a binary file. */ | |
97e03143 | 2834 | |
39bbf761 RE |
2835 | static struct gdbarch * |
2836 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2837 | { | |
97e03143 | 2838 | struct gdbarch_tdep *tdep; |
39bbf761 RE |
2839 | struct gdbarch *gdbarch; |
2840 | ||
97e03143 | 2841 | /* Try to deterimine the ABI of the object we are loading. */ |
39bbf761 | 2842 | |
4be87837 | 2843 | if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN) |
97e03143 | 2844 | { |
4be87837 | 2845 | switch (bfd_get_flavour (info.abfd)) |
97e03143 | 2846 | { |
4be87837 DJ |
2847 | case bfd_target_aout_flavour: |
2848 | /* Assume it's an old APCS-style ABI. */ | |
2849 | info.osabi = GDB_OSABI_ARM_APCS; | |
2850 | break; | |
97e03143 | 2851 | |
4be87837 DJ |
2852 | case bfd_target_coff_flavour: |
2853 | /* Assume it's an old APCS-style ABI. */ | |
2854 | /* XXX WinCE? */ | |
2855 | info.osabi = GDB_OSABI_ARM_APCS; | |
2856 | break; | |
97e03143 | 2857 | |
4be87837 DJ |
2858 | default: |
2859 | /* Leave it as "unknown". */ | |
50ceaba5 | 2860 | break; |
97e03143 RE |
2861 | } |
2862 | } | |
2863 | ||
4be87837 DJ |
2864 | /* If there is already a candidate, use it. */ |
2865 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2866 | if (arches != NULL) | |
2867 | return arches->gdbarch; | |
97e03143 RE |
2868 | |
2869 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
2870 | gdbarch = gdbarch_alloc (&info, tdep); | |
2871 | ||
a5afb99f AC |
2872 | /* NOTE: cagney/2002-12-06: This can be deleted when this arch is |
2873 | ready to unwind the PC first (see frame.c:get_prev_frame()). */ | |
2874 | set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default); | |
2875 | ||
fd50bc42 RE |
2876 | /* We used to default to FPA for generic ARM, but almost nobody uses that |
2877 | now, and we now provide a way for the user to force the model. So | |
2878 | default to the most useful variant. */ | |
2879 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; | |
08216dd7 RE |
2880 | |
2881 | /* Breakpoints. */ | |
67255d04 RE |
2882 | switch (info.byte_order) |
2883 | { | |
2884 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
2885 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
2886 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
2887 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
2888 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
2889 | ||
67255d04 RE |
2890 | break; |
2891 | ||
2892 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
2893 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
2894 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
2895 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
2896 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
2897 | ||
67255d04 RE |
2898 | break; |
2899 | ||
2900 | default: | |
2901 | internal_error (__FILE__, __LINE__, | |
2902 | "arm_gdbarch_init: bad byte order for float format"); | |
2903 | } | |
2904 | ||
d7b486e7 RE |
2905 | /* On ARM targets char defaults to unsigned. */ |
2906 | set_gdbarch_char_signed (gdbarch, 0); | |
2907 | ||
9df628e0 | 2908 | /* This should be low enough for everything. */ |
97e03143 | 2909 | tdep->lowest_pc = 0x20; |
94c30b78 | 2910 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 2911 | |
b1e29e33 AC |
2912 | set_gdbarch_deprecated_call_dummy_words (gdbarch, arm_call_dummy_words); |
2913 | set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, 0); | |
848cfffb | 2914 | |
2dd604e7 | 2915 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
39bbf761 | 2916 | |
148754e5 | 2917 | /* Frame handling. */ |
618ce49f | 2918 | set_gdbarch_deprecated_frame_chain_valid (gdbarch, arm_frame_chain_valid); |
e9582e71 | 2919 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, arm_init_extra_frame_info); |
0ba6dca9 | 2920 | set_gdbarch_deprecated_target_read_fp (gdbarch, arm_read_fp); |
618ce49f | 2921 | set_gdbarch_deprecated_frame_chain (gdbarch, arm_frame_chain); |
148754e5 RE |
2922 | set_gdbarch_frameless_function_invocation |
2923 | (gdbarch, arm_frameless_function_invocation); | |
8bedc050 | 2924 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, arm_frame_saved_pc); |
148754e5 | 2925 | set_gdbarch_frame_args_skip (gdbarch, 0); |
f30ee0bc | 2926 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, arm_frame_init_saved_regs); |
749b82f6 | 2927 | set_gdbarch_deprecated_pop_frame (gdbarch, arm_pop_frame); |
148754e5 | 2928 | |
34e8f22d RE |
2929 | /* Address manipulation. */ |
2930 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
2931 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
2932 | ||
2933 | /* Offset from address of function to start of its code. */ | |
2934 | set_gdbarch_function_start_offset (gdbarch, 0); | |
2935 | ||
2936 | /* Advance PC across function entry code. */ | |
2937 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
2938 | ||
2939 | /* Get the PC when a frame might not be available. */ | |
6913c89a | 2940 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); |
34e8f22d RE |
2941 | |
2942 | /* The stack grows downward. */ | |
2943 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2944 | ||
2945 | /* Breakpoint manipulation. */ | |
2946 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
2947 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2948 | ||
2949 | /* Information about registers, etc. */ | |
2950 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
0ba6dca9 | 2951 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
2952 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
2953 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
2954 | set_gdbarch_register_byte (gdbarch, arm_register_byte); | |
b8b527c5 AC |
2955 | set_gdbarch_deprecated_register_bytes (gdbarch, |
2956 | (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
2957 | + NUM_FREGS * FP_REGISTER_RAW_SIZE | |
2958 | + NUM_SREGS * STATUS_REGISTER_SIZE)); | |
34e8f22d RE |
2959 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); |
2960 | set_gdbarch_register_raw_size (gdbarch, arm_register_raw_size); | |
2961 | set_gdbarch_register_virtual_size (gdbarch, arm_register_virtual_size); | |
a0ed5532 AC |
2962 | set_gdbarch_deprecated_max_register_raw_size (gdbarch, FP_REGISTER_RAW_SIZE); |
2963 | set_gdbarch_deprecated_max_register_virtual_size (gdbarch, FP_REGISTER_VIRTUAL_SIZE); | |
34e8f22d RE |
2964 | set_gdbarch_register_virtual_type (gdbarch, arm_register_type); |
2965 | ||
26216b98 AC |
2966 | /* Internal <-> external register number maps. */ |
2967 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); | |
2968 | ||
34e8f22d | 2969 | /* Integer registers are 4 bytes. */ |
b1e29e33 | 2970 | set_gdbarch_deprecated_register_size (gdbarch, 4); |
34e8f22d RE |
2971 | set_gdbarch_register_name (gdbarch, arm_register_name); |
2972 | ||
2973 | /* Returning results. */ | |
b508a996 RE |
2974 | set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value); |
2975 | set_gdbarch_store_return_value (gdbarch, arm_store_return_value); | |
67255d04 | 2976 | set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention); |
95f95911 | 2977 | set_gdbarch_extract_struct_value_address (gdbarch, |
67255d04 | 2978 | arm_extract_struct_value_address); |
34e8f22d RE |
2979 | |
2980 | /* Single stepping. */ | |
2981 | /* XXX For an RDI target we should ask the target if it can single-step. */ | |
2982 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); | |
2983 | ||
03d48a7d RE |
2984 | /* Disassembly. */ |
2985 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
2986 | ||
34e8f22d RE |
2987 | /* Minsymbol frobbing. */ |
2988 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
2989 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
2990 | arm_coff_make_msymbol_special); | |
2991 | ||
97e03143 | 2992 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 2993 | gdbarch_init_osabi (info, gdbarch); |
97e03143 RE |
2994 | |
2995 | /* Now we have tuned the configuration, set a few final things, | |
2996 | based on what the OS ABI has told us. */ | |
2997 | ||
9df628e0 RE |
2998 | if (tdep->jb_pc >= 0) |
2999 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
3000 | ||
08216dd7 RE |
3001 | /* Floating point sizes and format. */ |
3002 | switch (info.byte_order) | |
3003 | { | |
3004 | case BFD_ENDIAN_BIG: | |
3005 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
3006 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
3007 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
3008 | ||
3009 | break; | |
3010 | ||
3011 | case BFD_ENDIAN_LITTLE: | |
3012 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
fd50bc42 | 3013 | arm_set_fp (gdbarch); |
08216dd7 RE |
3014 | break; |
3015 | ||
3016 | default: | |
3017 | internal_error (__FILE__, __LINE__, | |
3018 | "arm_gdbarch_init: bad byte order for float format"); | |
3019 | } | |
3020 | ||
39bbf761 RE |
3021 | return gdbarch; |
3022 | } | |
3023 | ||
97e03143 RE |
3024 | static void |
3025 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
3026 | { | |
3027 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3028 | ||
3029 | if (tdep == NULL) | |
3030 | return; | |
3031 | ||
97e03143 RE |
3032 | fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx", |
3033 | (unsigned long) tdep->lowest_pc); | |
3034 | } | |
3035 | ||
3036 | static void | |
3037 | arm_init_abi_eabi_v1 (struct gdbarch_info info, | |
3038 | struct gdbarch *gdbarch) | |
3039 | { | |
3040 | /* Place-holder. */ | |
3041 | } | |
3042 | ||
3043 | static void | |
3044 | arm_init_abi_eabi_v2 (struct gdbarch_info info, | |
3045 | struct gdbarch *gdbarch) | |
3046 | { | |
3047 | /* Place-holder. */ | |
3048 | } | |
3049 | ||
3050 | static void | |
3051 | arm_init_abi_apcs (struct gdbarch_info info, | |
3052 | struct gdbarch *gdbarch) | |
3053 | { | |
3054 | /* Place-holder. */ | |
3055 | } | |
3056 | ||
c906108c | 3057 | void |
ed9a39eb | 3058 | _initialize_arm_tdep (void) |
c906108c | 3059 | { |
bc90b915 FN |
3060 | struct ui_file *stb; |
3061 | long length; | |
26304000 | 3062 | struct cmd_list_element *new_set, *new_show; |
53904c9e AC |
3063 | const char *setname; |
3064 | const char *setdesc; | |
3065 | const char **regnames; | |
bc90b915 FN |
3066 | int numregs, i, j; |
3067 | static char *helptext; | |
085dd6e6 | 3068 | |
39bbf761 | 3069 | if (GDB_MULTI_ARCH) |
97e03143 RE |
3070 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
3071 | ||
70f80edf JT |
3072 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
3073 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
3074 | bfd_target_elf_flavour, | |
3075 | arm_elf_osabi_sniffer); | |
3076 | ||
97e03143 | 3077 | /* Register some ABI variants for embedded systems. */ |
05816f70 | 3078 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V1, |
70f80edf | 3079 | arm_init_abi_eabi_v1); |
05816f70 | 3080 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V2, |
70f80edf | 3081 | arm_init_abi_eabi_v2); |
05816f70 | 3082 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_APCS, |
70f80edf | 3083 | arm_init_abi_apcs); |
39bbf761 | 3084 | |
94c30b78 | 3085 | /* Get the number of possible sets of register names defined in opcodes. */ |
afd7eef0 RE |
3086 | num_disassembly_options = get_arm_regname_num_options (); |
3087 | ||
3088 | /* Add root prefix command for all "set arm"/"show arm" commands. */ | |
3089 | add_prefix_cmd ("arm", no_class, set_arm_command, | |
3090 | "Various ARM-specific commands.", | |
3091 | &setarmcmdlist, "set arm ", 0, &setlist); | |
3092 | ||
3093 | add_prefix_cmd ("arm", no_class, show_arm_command, | |
3094 | "Various ARM-specific commands.", | |
3095 | &showarmcmdlist, "show arm ", 0, &showlist); | |
bc90b915 | 3096 | |
94c30b78 | 3097 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 3098 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 3099 | |
94c30b78 | 3100 | /* Begin creating the help text. */ |
bc90b915 | 3101 | stb = mem_fileopen (); |
afd7eef0 RE |
3102 | fprintf_unfiltered (stb, "Set the disassembly style.\n" |
3103 | "The valid values are:\n"); | |
ed9a39eb | 3104 | |
94c30b78 | 3105 | /* Initialize the array that will be passed to add_set_enum_cmd(). */ |
afd7eef0 RE |
3106 | valid_disassembly_styles |
3107 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); | |
3108 | for (i = 0; i < num_disassembly_options; i++) | |
bc90b915 FN |
3109 | { |
3110 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
afd7eef0 | 3111 | valid_disassembly_styles[i] = setname; |
bc90b915 FN |
3112 | fprintf_unfiltered (stb, "%s - %s\n", setname, |
3113 | setdesc); | |
94c30b78 | 3114 | /* Copy the default names (if found) and synchronize disassembler. */ |
bc90b915 FN |
3115 | if (!strcmp (setname, "std")) |
3116 | { | |
afd7eef0 | 3117 | disassembly_style = setname; |
bc90b915 FN |
3118 | current_option = i; |
3119 | for (j = 0; j < numregs; j++) | |
3120 | arm_register_names[j] = (char *) regnames[j]; | |
3121 | set_arm_regname_option (i); | |
3122 | } | |
3123 | } | |
94c30b78 | 3124 | /* Mark the end of valid options. */ |
afd7eef0 | 3125 | valid_disassembly_styles[num_disassembly_options] = NULL; |
c906108c | 3126 | |
94c30b78 | 3127 | /* Finish the creation of the help text. */ |
bc90b915 FN |
3128 | fprintf_unfiltered (stb, "The default is \"std\"."); |
3129 | helptext = ui_file_xstrdup (stb, &length); | |
3130 | ui_file_delete (stb); | |
ed9a39eb | 3131 | |
afd7eef0 | 3132 | /* Add the deprecated disassembly-flavor command. */ |
26304000 | 3133 | new_set = add_set_enum_cmd ("disassembly-flavor", no_class, |
afd7eef0 RE |
3134 | valid_disassembly_styles, |
3135 | &disassembly_style, | |
bc90b915 | 3136 | helptext, |
ed9a39eb | 3137 | &setlist); |
26304000 RE |
3138 | set_cmd_sfunc (new_set, set_disassembly_style_sfunc); |
3139 | deprecate_cmd (new_set, "set arm disassembly"); | |
3140 | deprecate_cmd (add_show_from_set (new_set, &showlist), | |
afd7eef0 RE |
3141 | "show arm disassembly"); |
3142 | ||
3143 | /* And now add the new interface. */ | |
30757f90 | 3144 | new_set = add_set_enum_cmd ("disassembler", no_class, |
26304000 RE |
3145 | valid_disassembly_styles, &disassembly_style, |
3146 | helptext, &setarmcmdlist); | |
3147 | ||
fd50bc42 | 3148 | set_cmd_sfunc (new_set, set_disassembly_style_sfunc); |
26304000 RE |
3149 | add_show_from_set (new_set, &showarmcmdlist); |
3150 | ||
3151 | add_setshow_cmd_full ("apcs32", no_class, | |
3152 | var_boolean, (char *) &arm_apcs_32, | |
3153 | "Set usage of ARM 32-bit mode.", | |
3154 | "Show usage of ARM 32-bit mode.", | |
3155 | NULL, NULL, | |
3156 | &setlist, &showlist, &new_set, &new_show); | |
3157 | deprecate_cmd (new_set, "set arm apcs32"); | |
3158 | deprecate_cmd (new_show, "show arm apcs32"); | |
3159 | ||
3160 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
3161 | "Set usage of ARM 32-bit mode. " | |
3162 | "When off, a 26-bit PC will be used.", | |
3163 | "Show usage of ARM 32-bit mode. " | |
3164 | "When off, a 26-bit PC will be used.", | |
3165 | NULL, NULL, | |
3166 | &setarmcmdlist, &showarmcmdlist); | |
c906108c | 3167 | |
fd50bc42 RE |
3168 | /* Add a command to allow the user to force the FPU model. */ |
3169 | new_set = add_set_enum_cmd | |
3170 | ("fpu", no_class, fp_model_strings, ¤t_fp_model, | |
3171 | "Set the floating point type.\n" | |
3172 | "auto - Determine the FP typefrom the OS-ABI.\n" | |
3173 | "softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n" | |
3174 | "fpa - FPA co-processor (GCC compiled).\n" | |
3175 | "softvfp - Software FP with pure-endian doubles.\n" | |
3176 | "vfp - VFP co-processor.", | |
3177 | &setarmcmdlist); | |
3178 | set_cmd_sfunc (new_set, set_fp_model_sfunc); | |
3179 | set_cmd_sfunc (add_show_from_set (new_set, &showarmcmdlist), show_fp_model); | |
3180 | ||
94c30b78 | 3181 | /* Add the deprecated "othernames" command. */ |
afd7eef0 RE |
3182 | deprecate_cmd (add_com ("othernames", class_obscure, arm_othernames, |
3183 | "Switch to the next set of register names."), | |
3184 | "set arm disassembly"); | |
c3b4394c | 3185 | |
6529d2dd | 3186 | /* Debugging flag. */ |
26304000 RE |
3187 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
3188 | "Set ARM debugging. " | |
3189 | "When on, arm-specific debugging is enabled.", | |
3190 | "Show ARM debugging. " | |
3191 | "When on, arm-specific debugging is enabled.", | |
3192 | NULL, NULL, | |
3193 | &setdebuglist, &showdebuglist); | |
c906108c | 3194 | } |