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c906108c
SS
1/* Caching code. Typically used by remote back ends for
2 caching remote memory.
3
917317f4 4 Copyright 1992-1993, 1995, 1998-1999 Free Software Foundation, Inc.
c906108c
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5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
c5aa993b
JM
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
c906108c
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22
23#include "defs.h"
24#include "dcache.h"
25#include "gdbcmd.h"
26#include "gdb_string.h"
27#include "gdbcore.h"
28
29/*
30 The data cache could lead to incorrect results because it doesn't know
31 about volatile variables, thus making it impossible to debug
32 functions which use memory mapped I/O devices.
33
34 set remotecache 0
35
36 In those cases.
37
38 In general the dcache speeds up performance, some speed improvement
39 comes from the actual caching mechanism, but the major gain is in
40 the reduction of the remote protocol overhead; instead of reading
41 or writing a large area of memory in 4 byte requests, the cache
42 bundles up the requests into 32 byte (actually LINE_SIZE) chunks.
43 Reducing the overhead to an eighth of what it was. This is very
44 obvious when displaying a large amount of data,
45
46 eg, x/200x 0
47
48 caching | no yes
49 ----------------------------
50 first time | 4 sec 2 sec improvement due to chunking
51 second time | 4 sec 0 sec improvement due to caching
52
53 The cache structure is unusual, we keep a number of cache blocks
54 (DCACHE_SIZE) and each one caches a LINE_SIZEed area of memory.
55 Within each line we remember the address of the line (always a
56 multiple of the LINE_SIZE) and a vector of bytes over the range.
57 There's another vector which contains the state of the bytes.
58
59 ENTRY_BAD means that the byte is just plain wrong, and has no
60 correspondence with anything else (as it would when the cache is
61 turned on, but nothing has been done to it.
62
63 ENTRY_DIRTY means that the byte has some data in it which should be
64 written out to the remote target one day, but contains correct
65 data. ENTRY_OK means that the data is the same in the cache as it
66 is in remote memory.
67
68
69 The ENTRY_DIRTY state is necessary because GDB likes to write large
70 lumps of memory in small bits. If the caching mechanism didn't
71 maintain the DIRTY information, then something like a two byte
72 write would mean that the entire cache line would have to be read,
73 the two bytes modified and then written out again. The alternative
74 would be to not read in the cache line in the first place, and just
75 write the two bytes directly into target memory. The trouble with
76 that is that it really nails performance, because of the remote
77 protocol overhead. This way, all those little writes are bundled
78 up into an entire cache line write in one go, without having to
79 read the cache line in the first place.
80
81
c5aa993b 82 */
c906108c
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83
84
85/* This value regulates the number of cache blocks stored.
86 Smaller values reduce the time spent searching for a cache
87 line, and reduce memory requirements, but increase the risk
88 of a line not being in memory */
89
c5aa993b 90#define DCACHE_SIZE 64
c906108c
SS
91
92/* This value regulates the size of a cache line. Smaller values
93 reduce the time taken to read a single byte, but reduce overall
94 throughput. */
95
c5aa993b 96#define LINE_SIZE_POWER (5)
c906108c
SS
97#define LINE_SIZE (1 << LINE_SIZE_POWER)
98
99/* Each cache block holds LINE_SIZE bytes of data
100 starting at a multiple-of-LINE_SIZE address. */
101
c5aa993b 102#define LINE_SIZE_MASK ((LINE_SIZE - 1))
c906108c
SS
103#define XFORM(x) ((x) & LINE_SIZE_MASK)
104#define MASK(x) ((x) & ~LINE_SIZE_MASK)
105
106
c5aa993b
JM
107#define ENTRY_BAD 0 /* data at this byte is wrong */
108#define ENTRY_DIRTY 1 /* data at this byte needs to be written back */
109#define ENTRY_OK 2 /* data at this byte is same as in memory */
c906108c
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110
111
112struct dcache_block
c5aa993b
JM
113 {
114 struct dcache_block *p; /* next in list */
115 CORE_ADDR addr; /* Address for which data is recorded. */
116 char data[LINE_SIZE]; /* bytes at given address */
117 unsigned char state[LINE_SIZE]; /* what state the data is in */
c906108c 118
c5aa993b
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119 /* whether anything in state is dirty - used to speed up the
120 dirty scan. */
121 int anydirty;
c906108c 122
c5aa993b
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123 int refs;
124 };
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SS
125
126
c5aa993b
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127struct dcache_struct
128 {
129 /* Function to actually read the target memory. */
130 memxferfunc read_memory;
c906108c 131
c5aa993b
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132 /* Function to actually write the target memory */
133 memxferfunc write_memory;
c906108c 134
c5aa993b
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135 /* free list */
136 struct dcache_block *free_head;
137 struct dcache_block *free_tail;
c906108c 138
c5aa993b
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139 /* in use list */
140 struct dcache_block *valid_head;
141 struct dcache_block *valid_tail;
c906108c 142
c5aa993b
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143 /* The cache itself. */
144 struct dcache_block *the_cache;
c906108c 145
c5aa993b
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146 /* potentially, if the cache was enabled, and then turned off, and
147 then turned on again, the stuff in it could be stale, so this is
148 used to mark it */
149 int cache_has_stuff;
150 };
c906108c 151
a14ed312 152static int dcache_poke_byte (DCACHE * dcache, CORE_ADDR addr, char *ptr);
c906108c 153
a14ed312 154static int dcache_peek_byte (DCACHE * dcache, CORE_ADDR addr, char *ptr);
c906108c 155
a14ed312 156static struct dcache_block *dcache_hit (DCACHE * dcache, CORE_ADDR addr);
c906108c 157
a14ed312 158static int dcache_write_line (DCACHE * dcache, struct dcache_block *db);
c906108c 159
a14ed312 160static struct dcache_block *dcache_alloc (DCACHE * dcache);
c906108c 161
a14ed312 162static int dcache_writeback (DCACHE * dcache);
c906108c 163
a14ed312 164static void dcache_info (char *exp, int tty);
c906108c 165
a14ed312 166void _initialize_dcache (void);
c906108c 167
917317f4 168static int dcache_enabled_p = 0;
c906108c 169
c5aa993b 170DCACHE *last_cache; /* Used by info dcache */
c906108c
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171
172
173/* Free all the data cache blocks, thus discarding all cached data. */
174
175void
fba45db2 176dcache_flush (DCACHE *dcache)
c906108c
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177{
178 int i;
179 dcache->valid_head = 0;
180 dcache->valid_tail = 0;
181
182 dcache->free_head = 0;
183 dcache->free_tail = 0;
184
185 for (i = 0; i < DCACHE_SIZE; i++)
186 {
187 struct dcache_block *db = dcache->the_cache + i;
188
189 if (!dcache->free_head)
190 dcache->free_head = db;
191 else
192 dcache->free_tail->p = db;
193 dcache->free_tail = db;
194 db->p = 0;
195 }
196
197 dcache->cache_has_stuff = 0;
198
199 return;
200}
201
202/* If addr is present in the dcache, return the address of the block
203 containing it. */
204
205static struct dcache_block *
fba45db2 206dcache_hit (DCACHE *dcache, CORE_ADDR addr)
c906108c
SS
207{
208 register struct dcache_block *db;
209
210 /* Search all cache blocks for one that is at this address. */
211 db = dcache->valid_head;
212
213 while (db)
214 {
c5aa993b 215 if (MASK (addr) == db->addr)
c906108c
SS
216 {
217 db->refs++;
218 return db;
219 }
220 db = db->p;
221 }
222
223 return NULL;
224}
225
226/* Make sure that anything in this line which needs to
227 be written is. */
228
229static int
fba45db2 230dcache_write_line (DCACHE *dcache, register struct dcache_block *db)
c906108c
SS
231{
232 int s;
233 int e;
234 s = 0;
235 if (db->anydirty)
236 {
237 for (s = 0; s < LINE_SIZE; s++)
238 {
239 if (db->state[s] == ENTRY_DIRTY)
240 {
241 int len = 0;
c5aa993b 242 for (e = s; e < LINE_SIZE; e++, len++)
c906108c
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243 if (db->state[e] != ENTRY_DIRTY)
244 break;
245 {
246 /* all bytes from s..s+len-1 need to
247 be written out */
248 int done = 0;
c5aa993b
JM
249 while (done < len)
250 {
251 int t = dcache->write_memory (db->addr + s + done,
252 db->data + s + done,
253 len - done);
254 if (t == 0)
255 return 0;
256 done += t;
257 }
c906108c
SS
258 memset (db->state + s, ENTRY_OK, len);
259 s = e;
260 }
261 }
262 }
263 db->anydirty = 0;
264 }
265 return 1;
266}
267
268
269/* Get a free cache block, put or keep it on the valid list,
270 and return its address. The caller should store into the block
271 the address and data that it describes, then remque it from the
272 free list and insert it into the valid list. This procedure
273 prevents errors from creeping in if a memory retrieval is
274 interrupted (which used to put garbage blocks in the valid
275 list...). */
276
277static struct dcache_block *
fba45db2 278dcache_alloc (DCACHE *dcache)
c906108c
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279{
280 register struct dcache_block *db;
281
917317f4 282 if (dcache_enabled_p == 0)
c906108c
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283 abort ();
284
285 /* Take something from the free list */
286 db = dcache->free_head;
287 if (db)
288 {
289 dcache->free_head = db->p;
290 }
291 else
292 {
293 /* Nothing left on free list, so grab one from the valid list */
294 db = dcache->valid_head;
295 dcache->valid_head = db->p;
296
297 dcache_write_line (dcache, db);
298 }
299
300 /* append this line to end of valid list */
301 if (!dcache->valid_head)
302 dcache->valid_head = db;
303 else
304 dcache->valid_tail->p = db;
305 dcache->valid_tail = db;
306 db->p = 0;
307
308 return db;
309}
310
311/* Using the data cache DCACHE return the contents of the byte at
312 address ADDR in the remote machine.
313
314 Returns 0 on error. */
315
316static int
fba45db2 317dcache_peek_byte (DCACHE *dcache, CORE_ADDR addr, char *ptr)
c906108c
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318{
319 register struct dcache_block *db = dcache_hit (dcache, addr);
c5aa993b 320 int ok = 1;
c906108c
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321 int done = 0;
322 if (db == 0
323 || db->state[XFORM (addr)] == ENTRY_BAD)
324 {
325 if (db)
326 {
327 dcache_write_line (dcache, db);
328 }
c5aa993b
JM
329 else
330 db = dcache_alloc (dcache);
c906108c
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331 immediate_quit++;
332 db->addr = MASK (addr);
c5aa993b 333 while (done < LINE_SIZE)
c906108c
SS
334 {
335 int try =
c5aa993b
JM
336 (*dcache->read_memory)
337 (db->addr + done,
338 db->data + done,
339 LINE_SIZE - done);
c906108c
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340 if (try == 0)
341 return 0;
342 done += try;
343 }
344 immediate_quit--;
c5aa993b 345
c906108c
SS
346 memset (db->state, ENTRY_OK, sizeof (db->data));
347 db->anydirty = 0;
348 }
349 *ptr = db->data[XFORM (addr)];
350 return ok;
351}
352
353/* Writeback any dirty lines to the remote. */
354static int
fba45db2 355dcache_writeback (DCACHE *dcache)
c906108c
SS
356{
357 struct dcache_block *db;
358
359 db = dcache->valid_head;
360
361 while (db)
362 {
363 if (!dcache_write_line (dcache, db))
364 return 0;
365 db = db->p;
366 }
367 return 1;
368}
369
370
c906108c
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371/* Write the byte at PTR into ADDR in the data cache.
372 Return zero on write error.
373 */
374
375static int
fba45db2 376dcache_poke_byte (DCACHE *dcache, CORE_ADDR addr, char *ptr)
c906108c
SS
377{
378 register struct dcache_block *db = dcache_hit (dcache, addr);
379
380 if (!db)
381 {
382 db = dcache_alloc (dcache);
383 db->addr = MASK (addr);
384 memset (db->state, ENTRY_BAD, sizeof (db->data));
385 }
386
387 db->data[XFORM (addr)] = *ptr;
388 db->state[XFORM (addr)] = ENTRY_DIRTY;
389 db->anydirty = 1;
390 return 1;
391}
392
c906108c
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393/* Initialize the data cache. */
394DCACHE *
fba45db2 395dcache_init (memxferfunc reading, memxferfunc writing)
c906108c
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396{
397 int csize = sizeof (struct dcache_block) * DCACHE_SIZE;
398 DCACHE *dcache;
399
400 dcache = (DCACHE *) xmalloc (sizeof (*dcache));
401 dcache->read_memory = reading;
402 dcache->write_memory = writing;
403
404 dcache->the_cache = (struct dcache_block *) xmalloc (csize);
405 memset (dcache->the_cache, 0, csize);
406
407 dcache_flush (dcache);
408
409 last_cache = dcache;
410 return dcache;
411}
412
413/* Read or write LEN bytes from inferior memory at MEMADDR, transferring
414 to or from debugger address MYADDR. Write to inferior if SHOULD_WRITE is
415 nonzero.
416
417 Returns length of data written or read; 0 for error.
418
419 This routine is indended to be called by remote_xfer_ functions. */
420
421int
fba45db2
KB
422dcache_xfer_memory (DCACHE *dcache, CORE_ADDR memaddr, char *myaddr, int len,
423 int should_write)
c906108c
SS
424{
425 int i;
426
917317f4 427 if (dcache_enabled_p)
c906108c 428 {
507f3c78 429 int (*xfunc) (DCACHE * dcache, CORE_ADDR addr, char *ptr);
c906108c
SS
430 xfunc = should_write ? dcache_poke_byte : dcache_peek_byte;
431
432 for (i = 0; i < len; i++)
433 {
434 if (!xfunc (dcache, memaddr + i, myaddr + i))
435 return 0;
436 }
437 dcache->cache_has_stuff = 1;
438 dcache_writeback (dcache);
439 }
c5aa993b 440 else
c906108c
SS
441 {
442 memxferfunc xfunc;
443 xfunc = should_write ? dcache->write_memory : dcache->read_memory;
444
445 if (dcache->cache_has_stuff)
446 dcache_flush (dcache);
447
448 len = xfunc (memaddr, myaddr, len);
449 }
450 return len;
451}
452
c5aa993b 453static void
fba45db2 454dcache_info (char *exp, int tty)
c906108c
SS
455{
456 struct dcache_block *p;
457
917317f4 458 if (!dcache_enabled_p)
c906108c
SS
459 {
460 printf_filtered ("Dcache not enabled\n");
461 return;
462 }
463 printf_filtered ("Dcache enabled, line width %d, depth %d\n",
464 LINE_SIZE, DCACHE_SIZE);
465
466 printf_filtered ("Cache state:\n");
467
468 for (p = last_cache->valid_head; p; p = p->p)
469 {
470 int j;
d4f3574e
SS
471 printf_filtered ("Line at %s, referenced %d times\n",
472 paddr (p->addr), p->refs);
c906108c
SS
473
474 for (j = 0; j < LINE_SIZE; j++)
475 printf_filtered ("%02x", p->data[j] & 0xFF);
476 printf_filtered ("\n");
477
478 for (j = 0; j < LINE_SIZE; j++)
479 printf_filtered (" %2x", p->state[j]);
480 printf_filtered ("\n");
481 }
482}
483
c2d11a7d
JM
484/* Turn dcache on or off. */
485void
486set_dcache_state (int what)
487{
488 dcache_enabled_p = !!what;
489}
490
c906108c 491void
fba45db2 492_initialize_dcache (void)
c906108c
SS
493{
494 add_show_from_set
495 (add_set_cmd ("remotecache", class_support, var_boolean,
917317f4 496 (char *) &dcache_enabled_p,
c906108c
SS
497 "\
498Set cache use for remote targets.\n\
499When on, use data caching for remote targets. For many remote targets\n\
500this option can offer better throughput for reading target memory.\n\
501Unfortunately, gdb does not currently know anything about volatile\n\
502registers and thus data caching will produce incorrect results with\n\
917317f4 503volatile registers are in use. By default, this option is off.",
c906108c
SS
504 &setlist),
505 &showlist);
506
507 add_info ("dcache", dcache_info,
508 "Print information on the dcache performance.");
509
510}