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9058f767
KB		 1/* Target-dependent code for the Renesas RL78 for GDB, the GNU debugger.
2
ecd75fc8 3 Copyright (C) 2011-2014 Free Software Foundation, Inc.
9058f767
KB		 4
5 Contributed by Red Hat, Inc.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22#include "defs.h"
23#include "arch-utils.h"
24#include "prologue-value.h"
25#include "target.h"
26#include "regcache.h"
27#include "opcode/rl78.h"
28#include "dis-asm.h"
29#include "gdbtypes.h"
30#include "frame.h"
31#include "frame-unwind.h"
32#include "frame-base.h"
33#include "value.h"
34#include "gdbcore.h"
35#include "dwarf2-frame.h"
c47a44f4 36#include "reggroups.h"
9058f767
KB		 37
38#include "elf/rl78.h"
39#include "elf-bfd.h"
40
41/* Register Banks. */
42
43enum
44{
45 RL78_BANK0 = 0,
46 RL78_BANK1 = 1,
47 RL78_BANK2 = 2,
48 RL78_BANK3 = 3,
49 RL78_NUMBANKS = 4,
50 RL78_REGS_PER_BANK = 8
51};
52
53/* Register Numbers. */
54
55enum
56{
57 /* All general purpose registers are 8 bits wide. */
c47a44f4
KB		 58 RL78_RAW_BANK0_R0_REGNUM = 0,
59 RL78_RAW_BANK0_R1_REGNUM,
60 RL78_RAW_BANK0_R2_REGNUM,
61 RL78_RAW_BANK0_R3_REGNUM,
62 RL78_RAW_BANK0_R4_REGNUM,
63 RL78_RAW_BANK0_R5_REGNUM,
64 RL78_RAW_BANK0_R6_REGNUM,
65 RL78_RAW_BANK0_R7_REGNUM,
66
67 RL78_RAW_BANK1_R0_REGNUM,
68 RL78_RAW_BANK1_R1_REGNUM,
69 RL78_RAW_BANK1_R2_REGNUM,
70 RL78_RAW_BANK1_R3_REGNUM,
71 RL78_RAW_BANK1_R4_REGNUM,
72 RL78_RAW_BANK1_R5_REGNUM,
73 RL78_RAW_BANK1_R6_REGNUM,
74 RL78_RAW_BANK1_R7_REGNUM,
75
76 RL78_RAW_BANK2_R0_REGNUM,
77 RL78_RAW_BANK2_R1_REGNUM,
78 RL78_RAW_BANK2_R2_REGNUM,
79 RL78_RAW_BANK2_R3_REGNUM,
80 RL78_RAW_BANK2_R4_REGNUM,
81 RL78_RAW_BANK2_R5_REGNUM,
82 RL78_RAW_BANK2_R6_REGNUM,
83 RL78_RAW_BANK2_R7_REGNUM,
84
85 RL78_RAW_BANK3_R0_REGNUM,
86 RL78_RAW_BANK3_R1_REGNUM,
87 RL78_RAW_BANK3_R2_REGNUM,
88 RL78_RAW_BANK3_R3_REGNUM,
89 RL78_RAW_BANK3_R4_REGNUM,
90 RL78_RAW_BANK3_R5_REGNUM,
91 RL78_RAW_BANK3_R6_REGNUM,
92 RL78_RAW_BANK3_R7_REGNUM,
93
94 RL78_PSW_REGNUM, /* 8 bits */
95 RL78_ES_REGNUM, /* 8 bits */
96 RL78_CS_REGNUM, /* 8 bits */
ba89f962 97 RL78_RAW_PC_REGNUM, /* 20 bits; we'll use 32 bits for it. */
c47a44f4
KB		 98
99 /* Fixed address SFRs (some of those above are SFRs too.) */
100 RL78_SPL_REGNUM, /* 8 bits; lower half of SP */
101 RL78_SPH_REGNUM, /* 8 bits; upper half of SP */
102 RL78_PMC_REGNUM, /* 8 bits */
103 RL78_MEM_REGNUM, /* 8 bits ?? */
104
105 RL78_NUM_REGS,
106
107 /* Pseudo registers. */
ba89f962
KB		 108 RL78_PC_REGNUM = RL78_NUM_REGS,
109 RL78_SP_REGNUM,
c47a44f4
KB		 110
111 RL78_X_REGNUM,
112 RL78_A_REGNUM,
113 RL78_C_REGNUM,
114 RL78_B_REGNUM,
115 RL78_E_REGNUM,
116 RL78_D_REGNUM,
117 RL78_L_REGNUM,
118 RL78_H_REGNUM,
119
120 RL78_AX_REGNUM,
121 RL78_BC_REGNUM,
122 RL78_DE_REGNUM,
123 RL78_HL_REGNUM,
124
125 RL78_BANK0_R0_REGNUM,
9058f767
KB		 126 RL78_BANK0_R1_REGNUM,
127 RL78_BANK0_R2_REGNUM,
128 RL78_BANK0_R3_REGNUM,
129 RL78_BANK0_R4_REGNUM,
130 RL78_BANK0_R5_REGNUM,
131 RL78_BANK0_R6_REGNUM,
132 RL78_BANK0_R7_REGNUM,
133
134 RL78_BANK1_R0_REGNUM,
135 RL78_BANK1_R1_REGNUM,
136 RL78_BANK1_R2_REGNUM,
137 RL78_BANK1_R3_REGNUM,
138 RL78_BANK1_R4_REGNUM,
139 RL78_BANK1_R5_REGNUM,
140 RL78_BANK1_R6_REGNUM,
141 RL78_BANK1_R7_REGNUM,
142
143 RL78_BANK2_R0_REGNUM,
144 RL78_BANK2_R1_REGNUM,
145 RL78_BANK2_R2_REGNUM,
146 RL78_BANK2_R3_REGNUM,
147 RL78_BANK2_R4_REGNUM,
148 RL78_BANK2_R5_REGNUM,
149 RL78_BANK2_R6_REGNUM,
150 RL78_BANK2_R7_REGNUM,
151
152 RL78_BANK3_R0_REGNUM,
153 RL78_BANK3_R1_REGNUM,
154 RL78_BANK3_R2_REGNUM,
155 RL78_BANK3_R3_REGNUM,
156 RL78_BANK3_R4_REGNUM,
157 RL78_BANK3_R5_REGNUM,
158 RL78_BANK3_R6_REGNUM,
159 RL78_BANK3_R7_REGNUM,
160
c47a44f4 161 RL78_BANK0_RP0_REGNUM,
9058f767
KB		 162 RL78_BANK0_RP1_REGNUM,
163 RL78_BANK0_RP2_REGNUM,
164 RL78_BANK0_RP3_REGNUM,
165
166 RL78_BANK1_RP0_REGNUM,
167 RL78_BANK1_RP1_REGNUM,
168 RL78_BANK1_RP2_REGNUM,
169 RL78_BANK1_RP3_REGNUM,
170
171 RL78_BANK2_RP0_REGNUM,
172 RL78_BANK2_RP1_REGNUM,
173 RL78_BANK2_RP2_REGNUM,
174 RL78_BANK2_RP3_REGNUM,
175
176 RL78_BANK3_RP0_REGNUM,
177 RL78_BANK3_RP1_REGNUM,
178 RL78_BANK3_RP2_REGNUM,
179 RL78_BANK3_RP3_REGNUM,
180
9058f767
KB		 181 RL78_NUM_TOTAL_REGS,
182 RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS
183};
184
185/* Architecture specific data. */
186
187struct gdbarch_tdep
188{
189 /* The ELF header flags specify the multilib used. */
190 int elf_flags;
191
192 struct type *rl78_void,
193 *rl78_uint8,
194 *rl78_int8,
195 *rl78_uint16,
196 *rl78_int16,
197 *rl78_uint32,
198 *rl78_int32,
199 *rl78_data_pointer,
200 *rl78_code_pointer;
201};
202
203/* This structure holds the results of a prologue analysis. */
204
205struct rl78_prologue
206{
207 /* The offset from the frame base to the stack pointer --- always
208 zero or negative.
209
210 Calling this a "size" is a bit misleading, but given that the
211 stack grows downwards, using offsets for everything keeps one
212 from going completely sign-crazy: you never change anything's
213 sign for an ADD instruction; always change the second operand's
214 sign for a SUB instruction; and everything takes care of
215 itself. */
216 int frame_size;
217
218 /* Non-zero if this function has initialized the frame pointer from
219 the stack pointer, zero otherwise. */
220 int has_frame_ptr;
221
222 /* If has_frame_ptr is non-zero, this is the offset from the frame
223 base to where the frame pointer points. This is always zero or
224 negative. */
225 int frame_ptr_offset;
226
227 /* The address of the first instruction at which the frame has been
228 set up and the arguments are where the debug info says they are
229 --- as best as we can tell. */
230 CORE_ADDR prologue_end;
231
232 /* reg_offset[R] is the offset from the CFA at which register R is
233 saved, or 1 if register R has not been saved. (Real values are
234 always zero or negative.) */
235 int reg_offset[RL78_NUM_TOTAL_REGS];
236};
237
238/* Implement the "register_type" gdbarch method. */
239
240static struct type *
241rl78_register_type (struct gdbarch *gdbarch, int reg_nr)
242{
243 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
244
245 if (reg_nr == RL78_PC_REGNUM)
246 return tdep->rl78_code_pointer;
ba89f962
KB		 247 else if (reg_nr == RL78_RAW_PC_REGNUM)
248 return tdep->rl78_uint32;
9058f767 249 else if (reg_nr <= RL78_MEM_REGNUM
c47a44f4
KB		 250 || (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM)
251 || (RL78_BANK0_R0_REGNUM <= reg_nr
252 && reg_nr <= RL78_BANK3_R7_REGNUM))
9058f767
KB		 253 return tdep->rl78_int8;
254 else
255 return tdep->rl78_data_pointer;
256}
257
258/* Implement the "register_name" gdbarch method. */
259
260static const char *
261rl78_register_name (struct gdbarch *gdbarch, int regnr)
262{
263 static const char *const reg_names[] =
264 {
c47a44f4
KB		 265 "", /* bank0_r0 */
266 "", /* bank0_r1 */
267 "", /* bank0_r2 */
268 "", /* bank0_r3 */
269 "", /* bank0_r4 */
270 "", /* bank0_r5 */
271 "", /* bank0_r6 */
272 "", /* bank0_r7 */
273
274 "", /* bank1_r0 */
275 "", /* bank1_r1 */
276 "", /* bank1_r2 */
277 "", /* bank1_r3 */
278 "", /* bank1_r4 */
279 "", /* bank1_r5 */
280 "", /* bank1_r6 */
281 "", /* bank1_r7 */
282
283 "", /* bank2_r0 */
284 "", /* bank2_r1 */
285 "", /* bank2_r2 */
286 "", /* bank2_r3 */
287 "", /* bank2_r4 */
288 "", /* bank2_r5 */
289 "", /* bank2_r6 */
290 "", /* bank2_r7 */
291
292 "", /* bank3_r0 */
293 "", /* bank3_r1 */
294 "", /* bank3_r2 */
295 "", /* bank3_r3 */
296 "", /* bank3_r4 */
297 "", /* bank3_r5 */
298 "", /* bank3_r6 */
299 "", /* bank3_r7 */
300
301 "psw",
302 "es",
303 "cs",
ba89f962 304 "",
c47a44f4
KB		 305
306 "", /* spl */
307 "", /* sph */
308 "pmc",
309 "mem",
310
ba89f962 311 "pc",
c47a44f4
KB		 312 "sp",
313
314 "x",
315 "a",
316 "c",
317 "b",
318 "e",
319 "d",
320 "l",
321 "h",
322
323 "ax",
324 "bc",
325 "de",
326 "hl",
327
9058f767
KB		 328 "bank0_r0",
329 "bank0_r1",
330 "bank0_r2",
331 "bank0_r3",
332 "bank0_r4",
333 "bank0_r5",
334 "bank0_r6",
335 "bank0_r7",
336
337 "bank1_r0",
338 "bank1_r1",
339 "bank1_r2",
340 "bank1_r3",
341 "bank1_r4",
342 "bank1_r5",
343 "bank1_r6",
344 "bank1_r7",
345
346 "bank2_r0",
347 "bank2_r1",
348 "bank2_r2",
349 "bank2_r3",
350 "bank2_r4",
351 "bank2_r5",
352 "bank2_r6",
353 "bank2_r7",
354
355 "bank3_r0",
356 "bank3_r1",
357 "bank3_r2",
358 "bank3_r3",
359 "bank3_r4",
360 "bank3_r5",
361 "bank3_r6",
362 "bank3_r7",
363
9058f767
KB		 364 "bank0_rp0",
365 "bank0_rp1",
366 "bank0_rp2",
367 "bank0_rp3",
368
369 "bank1_rp0",
370 "bank1_rp1",
371 "bank1_rp2",
372 "bank1_rp3",
373
374 "bank2_rp0",
375 "bank2_rp1",
376 "bank2_rp2",
377 "bank2_rp3",
378
379 "bank3_rp0",
380 "bank3_rp1",
381 "bank3_rp2",
c47a44f4
KB		 382 "bank3_rp3"
383 };
9058f767 384
c47a44f4
KB		 385 return reg_names[regnr];
386}
9058f767 387
bc3c6b36
KB		 388/* Implement the "register_name" gdbarch method for the g10 variant. */
389
390static const char *
391rl78_g10_register_name (struct gdbarch *gdbarch, int regnr)
392{
393 static const char *const reg_names[] =
394 {
395 "", /* bank0_r0 */
396 "", /* bank0_r1 */
397 "", /* bank0_r2 */
398 "", /* bank0_r3 */
399 "", /* bank0_r4 */
400 "", /* bank0_r5 */
401 "", /* bank0_r6 */
402 "", /* bank0_r7 */
403
404 "", /* bank1_r0 */
405 "", /* bank1_r1 */
406 "", /* bank1_r2 */
407 "", /* bank1_r3 */
408 "", /* bank1_r4 */
409 "", /* bank1_r5 */
410 "", /* bank1_r6 */
411 "", /* bank1_r7 */
412
413 "", /* bank2_r0 */
414 "", /* bank2_r1 */
415 "", /* bank2_r2 */
416 "", /* bank2_r3 */
417 "", /* bank2_r4 */
418 "", /* bank2_r5 */
419 "", /* bank2_r6 */
420 "", /* bank2_r7 */
421
422 "", /* bank3_r0 */
423 "", /* bank3_r1 */
424 "", /* bank3_r2 */
425 "", /* bank3_r3 */
426 "", /* bank3_r4 */
427 "", /* bank3_r5 */
428 "", /* bank3_r6 */
429 "", /* bank3_r7 */
430
431 "psw",
432 "es",
433 "cs",
434 "",
435
436 "", /* spl */
437 "", /* sph */
438 "pmc",
439 "mem",
440
441 "pc",
442 "sp",
443
444 "x",
445 "a",
446 "c",
447 "b",
448 "e",
449 "d",
450 "l",
451 "h",
452
453 "ax",
454 "bc",
455 "de",
456 "hl",
457
458 "bank0_r0",
459 "bank0_r1",
460 "bank0_r2",
461 "bank0_r3",
462 "bank0_r4",
463 "bank0_r5",
464 "bank0_r6",
465 "bank0_r7",
466
467 "",
468 "",
469 "",
470 "",
471 "",
472 "",
473 "",
474 "",
475
476 "",
477 "",
478 "",
479 "",
480 "",
481 "",
482 "",
483 "",
484
485 "",
486 "",
487 "",
488 "",
489 "",
490 "",
491 "",
492 "",
493
494 "bank0_rp0",
495 "bank0_rp1",
496 "bank0_rp2",
497 "bank0_rp3",
498
499 "",
500 "",
501 "",
502 "",
503
504 "",
505 "",
506 "",
507 "",
508
509 "",
510 "",
511 "",
512 ""
513 };
514
515 return reg_names[regnr];
516}
517
c47a44f4 518/* Implement the "register_reggroup_p" gdbarch method. */
9058f767 519
c47a44f4
KB		 520static int
521rl78_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
522 struct reggroup *group)
523{
524 if (group == all_reggroup)
525 return 1;
9058f767 526
c47a44f4
KB		 527 /* All other registers are saved and restored. */
528 if (group == save_reggroup || group == restore_reggroup)
529 {
b3ce41ea 530 if ((regnum < RL78_NUM_REGS
ba89f962
KB		 531 && regnum != RL78_SPL_REGNUM
532 && regnum != RL78_SPH_REGNUM
533 && regnum != RL78_RAW_PC_REGNUM)
534 || regnum == RL78_SP_REGNUM
535 || regnum == RL78_PC_REGNUM)
c47a44f4
KB		 536 return 1;
537 else
538 return 0;
539 }
540
541 if ((RL78_BANK0_R0_REGNUM <= regnum && regnum <= RL78_BANK3_R7_REGNUM)
542 || regnum == RL78_ES_REGNUM
543 || regnum == RL78_CS_REGNUM
544 || regnum == RL78_SPL_REGNUM
545 || regnum == RL78_SPH_REGNUM
546 || regnum == RL78_PMC_REGNUM
547 || regnum == RL78_MEM_REGNUM
ba89f962 548 || regnum == RL78_RAW_PC_REGNUM
c47a44f4
KB		 549 || (RL78_BANK0_RP0_REGNUM <= regnum && regnum <= RL78_BANK3_RP3_REGNUM))
550 return group == system_reggroup;
551
552 return group == general_reggroup;
9058f767
KB		 553}
554
555/* Strip bits to form an instruction address. (When fetching a
556 32-bit address from the stack, the high eight bits are garbage.
557 This function strips off those unused bits.) */
558
559static CORE_ADDR
560rl78_make_instruction_address (CORE_ADDR addr)
561{
562 return addr & 0xffffff;
563}
564
565/* Set / clear bits necessary to make a data address. */
566
567static CORE_ADDR
568rl78_make_data_address (CORE_ADDR addr)
569{
570 return (addr & 0xffff) | 0xf0000;
571}
572
573/* Implement the "pseudo_register_read" gdbarch method. */
574
575static enum register_status
576rl78_pseudo_register_read (struct gdbarch *gdbarch,
577 struct regcache *regcache,
578 int reg, gdb_byte *buffer)
579{
580 enum register_status status;
581
c47a44f4
KB		 582 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
583 {
584 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
585 + (reg - RL78_BANK0_R0_REGNUM);
586
587 status = regcache_raw_read (regcache, raw_regnum, buffer);
588 }
589 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
9058f767
KB		 590 {
591 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
c47a44f4 592 + RL78_RAW_BANK0_R0_REGNUM;
9058f767
KB		 593
594 status = regcache_raw_read (regcache, raw_regnum, buffer);
595 if (status == REG_VALID)
596 status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
597 }
598 else if (reg == RL78_SP_REGNUM)
599 {
600 status = regcache_raw_read (regcache, RL78_SPL_REGNUM, buffer);
601 if (status == REG_VALID)
602 status = regcache_raw_read (regcache, RL78_SPH_REGNUM, buffer + 1);
603 }
ba89f962
KB		 604 else if (reg == RL78_PC_REGNUM)
605 {
606 gdb_byte rawbuf[4];
607
608 status = regcache_raw_read (regcache, RL78_RAW_PC_REGNUM, rawbuf);
609 memcpy (buffer, rawbuf, 3);
610 }
9058f767
KB		 611 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
612 {
613 ULONGEST psw;
614
615 status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
616 if (status == REG_VALID)
617 {
618 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
619 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
c47a44f4 620 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 621 + (reg - RL78_X_REGNUM);
622 status = regcache_raw_read (regcache, raw_regnum, buffer);
623 }
624 }
625 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
626 {
627 ULONGEST psw;
628
629 status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
630 if (status == REG_VALID)
631 {
632 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
633 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
c47a44f4 634 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 635 + 2 * (reg - RL78_AX_REGNUM);
636 status = regcache_raw_read (regcache, raw_regnum, buffer);
637 if (status == REG_VALID)
638 status = regcache_raw_read (regcache, raw_regnum + 1,
639 buffer + 1);
640 }
641 }
642 else
643 gdb_assert_not_reached ("invalid pseudo register number");
644 return status;
645}
646
647/* Implement the "pseudo_register_write" gdbarch method. */
648
649static void
650rl78_pseudo_register_write (struct gdbarch *gdbarch,
651 struct regcache *regcache,
652 int reg, const gdb_byte *buffer)
653{
c47a44f4
KB		 654 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
655 {
656 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
657 + (reg - RL78_BANK0_R0_REGNUM);
658
659 regcache_raw_write (regcache, raw_regnum, buffer);
660 }
661 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
9058f767
KB		 662 {
663 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
c47a44f4 664 + RL78_RAW_BANK0_R0_REGNUM;
9058f767
KB		 665
666 regcache_raw_write (regcache, raw_regnum, buffer);
667 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
668 }
669 else if (reg == RL78_SP_REGNUM)
670 {
671 regcache_raw_write (regcache, RL78_SPL_REGNUM, buffer);
672 regcache_raw_write (regcache, RL78_SPH_REGNUM, buffer + 1);
673 }
ba89f962
KB		 674 else if (reg == RL78_PC_REGNUM)
675 {
676 gdb_byte rawbuf[4];
677
678 memcpy (rawbuf, buffer, 3);
679 rawbuf[3] = 0;
680 regcache_raw_write (regcache, RL78_RAW_PC_REGNUM, rawbuf);
681 }
9058f767
KB		 682 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
683 {
684 ULONGEST psw;
685 int bank;
686 int raw_regnum;
687
688 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
689 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
690 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
c47a44f4 691 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 692 + (reg - RL78_X_REGNUM);
693 regcache_raw_write (regcache, raw_regnum, buffer);
694 }
695 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
696 {
697 ULONGEST psw;
698 int bank, raw_regnum;
699
700 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
701 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
702 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
c47a44f4 703 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 704 + 2 * (reg - RL78_AX_REGNUM);
705 regcache_raw_write (regcache, raw_regnum, buffer);
706 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
707 }
708 else
709 gdb_assert_not_reached ("invalid pseudo register number");
710}
711
712/* Implement the "breakpoint_from_pc" gdbarch method. */
713
693be288 714static const gdb_byte *
9058f767
KB		 715rl78_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
716 int *lenptr)
717{
718 /* The documented BRK instruction is actually a two byte sequence,
719 {0x61, 0xcc}, but instructions may be as short as one byte.
720 Correspondence with Renesas revealed that the one byte sequence
721 0xff is used when a one byte breakpoint instruction is required. */
722 static gdb_byte breakpoint[] = { 0xff };
723
724 *lenptr = sizeof breakpoint;
725 return breakpoint;
726}
727
728/* Define a "handle" struct for fetching the next opcode. */
729
730struct rl78_get_opcode_byte_handle
731{
732 CORE_ADDR pc;
733};
734
735/* Fetch a byte on behalf of the opcode decoder. HANDLE contains
736 the memory address of the next byte to fetch. If successful,
737 the address in the handle is updated and the byte fetched is
738 returned as the value of the function. If not successful, -1
739 is returned. */
740
741static int
742rl78_get_opcode_byte (void *handle)
743{
744 struct rl78_get_opcode_byte_handle *opcdata = handle;
745 int status;
746 gdb_byte byte;
747
748 status = target_read_memory (opcdata->pc, &byte, 1);
749 if (status == 0)
750 {
751 opcdata->pc += 1;
752 return byte;
753 }
754 else
755 return -1;
756}
757
758/* Function for finding saved registers in a 'struct pv_area'; this
759 function is passed to pv_area_scan.
760
761 If VALUE is a saved register, ADDR says it was saved at a constant
762 offset from the frame base, and SIZE indicates that the whole
763 register was saved, record its offset. */
764
765static void
766check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size,
767 pv_t value)
768{
769 struct rl78_prologue *result = (struct rl78_prologue *) result_untyped;
770
771 if (value.kind == pvk_register
772 && value.k == 0
773 && pv_is_register (addr, RL78_SP_REGNUM)
f5656ead 774 && size == register_size (target_gdbarch (), value.reg))
9058f767
KB		 775 result->reg_offset[value.reg] = addr.k;
776}
777
778/* Analyze a prologue starting at START_PC, going no further than
779 LIMIT_PC. Fill in RESULT as appropriate. */
780
781static void
782rl78_analyze_prologue (CORE_ADDR start_pc,
783 CORE_ADDR limit_pc, struct rl78_prologue *result)
784{
785 CORE_ADDR pc, next_pc;
786 int rn;
787 pv_t reg[RL78_NUM_TOTAL_REGS];
788 struct pv_area *stack;
789 struct cleanup *back_to;
790 CORE_ADDR after_last_frame_setup_insn = start_pc;
791 int bank = 0;
792
793 memset (result, 0, sizeof (*result));
794
795 for (rn = 0; rn < RL78_NUM_TOTAL_REGS; rn++)
796 {
797 reg[rn] = pv_register (rn, 0);
798 result->reg_offset[rn] = 1;
799 }
800
f5656ead 801 stack = make_pv_area (RL78_SP_REGNUM, gdbarch_addr_bit (target_gdbarch ()));
9058f767
KB		 802 back_to = make_cleanup_free_pv_area (stack);
803
804 /* The call instruction has saved the return address on the stack. */
805 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -4);
806 pv_area_store (stack, reg[RL78_SP_REGNUM], 4, reg[RL78_PC_REGNUM]);
807
808 pc = start_pc;
809 while (pc < limit_pc)
810 {
811 int bytes_read;
812 struct rl78_get_opcode_byte_handle opcode_handle;
813 RL78_Opcode_Decoded opc;
814
815 opcode_handle.pc = pc;
816 bytes_read = rl78_decode_opcode (pc, &opc, rl78_get_opcode_byte,
817 &opcode_handle);
818 next_pc = pc + bytes_read;
819
820 if (opc.id == RLO_sel)
821 {
822 bank = opc.op[1].addend;
823 }
824 else if (opc.id == RLO_mov
825 && opc.op[0].type == RL78_Operand_PreDec
826 && opc.op[0].reg == RL78_Reg_SP
827 && opc.op[1].type == RL78_Operand_Register)
828 {
829 int rsrc = (bank * RL78_REGS_PER_BANK)
830 + 2 * (opc.op[1].reg - RL78_Reg_AX);
831
832 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
833 pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc]);
834 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
835 pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc + 1]);
836 after_last_frame_setup_insn = next_pc;
837 }
838 else if (opc.id == RLO_sub
839 && opc.op[0].type == RL78_Operand_Register
840 && opc.op[0].reg == RL78_Reg_SP
841 && opc.op[1].type == RL78_Operand_Immediate)
842 {
843 int addend = opc.op[1].addend;
844
845 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM],
846 -addend);
847 after_last_frame_setup_insn = next_pc;
848 }
849 else
850 {
851 /* Terminate the prologue scan. */
852 break;
853 }
854
855 pc = next_pc;
856 }
857
858 /* Is the frame size (offset, really) a known constant? */
859 if (pv_is_register (reg[RL78_SP_REGNUM], RL78_SP_REGNUM))
860 result->frame_size = reg[RL78_SP_REGNUM].k;
861
862 /* Record where all the registers were saved. */
863 pv_area_scan (stack, check_for_saved, (void *) result);
864
865 result->prologue_end = after_last_frame_setup_insn;
866
867 do_cleanups (back_to);
868}
869
870/* Implement the "addr_bits_remove" gdbarch method. */
871
872static CORE_ADDR
873rl78_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
874{
875 return addr & 0xffffff;
876}
877
878/* Implement the "address_to_pointer" gdbarch method. */
879
880static void
881rl78_address_to_pointer (struct gdbarch *gdbarch,
882 struct type *type, gdb_byte *buf, CORE_ADDR addr)
883{
884 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
885
886 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
887 addr & 0xffffff);
888}
889
890/* Implement the "pointer_to_address" gdbarch method. */
891
892static CORE_ADDR
893rl78_pointer_to_address (struct gdbarch *gdbarch,
894 struct type *type, const gdb_byte *buf)
895{
896 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
897 CORE_ADDR addr
898 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
899
900 /* Is it a code address? */
901 if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
902 || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD
903 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))
904 || TYPE_LENGTH (type) == 4)
905 return rl78_make_instruction_address (addr);
906 else
907 return rl78_make_data_address (addr);
908}
909
910/* Implement the "skip_prologue" gdbarch method. */
911
912static CORE_ADDR
913rl78_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
914{
e4569f1e 915 const char *name;
9058f767
KB		 916 CORE_ADDR func_addr, func_end;
917 struct rl78_prologue p;
918
919 /* Try to find the extent of the function that contains PC. */
920 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
921 return pc;
922
923 rl78_analyze_prologue (pc, func_end, &p);
924 return p.prologue_end;
925}
926
927/* Implement the "unwind_pc" gdbarch method. */
928
929static CORE_ADDR
930rl78_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame)
931{
932 return rl78_addr_bits_remove
933 (arch, frame_unwind_register_unsigned (next_frame,
934 RL78_PC_REGNUM));
935}
936
937/* Implement the "unwind_sp" gdbarch method. */
938
939static CORE_ADDR
940rl78_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame)
941{
942 return frame_unwind_register_unsigned (next_frame, RL78_SP_REGNUM);
943}
944
945/* Given a frame described by THIS_FRAME, decode the prologue of its
946 associated function if there is not cache entry as specified by
947 THIS_PROLOGUE_CACHE. Save the decoded prologue in the cache and
948 return that struct as the value of this function. */
949
950static struct rl78_prologue *
951rl78_analyze_frame_prologue (struct frame_info *this_frame,
952 void **this_prologue_cache)
953{
954 if (!*this_prologue_cache)
955 {
956 CORE_ADDR func_start, stop_addr;
957
958 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct rl78_prologue);
959
960 func_start = get_frame_func (this_frame);
961 stop_addr = get_frame_pc (this_frame);
962
963 /* If we couldn't find any function containing the PC, then
964 just initialize the prologue cache, but don't do anything. */
965 if (!func_start)
966 stop_addr = func_start;
967
968 rl78_analyze_prologue (func_start, stop_addr, *this_prologue_cache);
969 }
970
971 return *this_prologue_cache;
972}
973
974/* Given a frame and a prologue cache, return this frame's base. */
975
976static CORE_ADDR
977rl78_frame_base (struct frame_info *this_frame, void **this_prologue_cache)
978{
979 struct rl78_prologue *p
980 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
981 CORE_ADDR sp = get_frame_register_unsigned (this_frame, RL78_SP_REGNUM);
982
983 return rl78_make_data_address (sp - p->frame_size);
984}
985
986/* Implement the "frame_this_id" method for unwinding frames. */
987
988static void
989rl78_this_id (struct frame_info *this_frame,
990 void **this_prologue_cache, struct frame_id *this_id)
991{
992 *this_id = frame_id_build (rl78_frame_base (this_frame,
993 this_prologue_cache),
994 get_frame_func (this_frame));
995}
996
997/* Implement the "frame_prev_register" method for unwinding frames. */
998
999static struct value *
1000rl78_prev_register (struct frame_info *this_frame,
1001 void **this_prologue_cache, int regnum)
1002{
1003 struct rl78_prologue *p
1004 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
1005 CORE_ADDR frame_base = rl78_frame_base (this_frame, this_prologue_cache);
1006
1007 if (regnum == RL78_SP_REGNUM)
1008 return frame_unwind_got_constant (this_frame, regnum, frame_base);
1009
1010 else if (regnum == RL78_SPL_REGNUM)
1011 return frame_unwind_got_constant (this_frame, regnum,
1012 (frame_base & 0xff));
1013
1014 else if (regnum == RL78_SPH_REGNUM)
1015 return frame_unwind_got_constant (this_frame, regnum,
1016 ((frame_base >> 8) & 0xff));
1017
1018 /* If prologue analysis says we saved this register somewhere,
1019 return a description of the stack slot holding it. */
1020 else if (p->reg_offset[regnum] != 1)
1021 {
1022 struct value *rv =
1023 frame_unwind_got_memory (this_frame, regnum,
1024 frame_base + p->reg_offset[regnum]);
1025
1026 if (regnum == RL78_PC_REGNUM)
1027 {
1028 ULONGEST pc = rl78_make_instruction_address (value_as_long (rv));
1029
1030 return frame_unwind_got_constant (this_frame, regnum, pc);
1031 }
1032 return rv;
1033 }
1034
1035 /* Otherwise, presume we haven't changed the value of this
1036 register, and get it from the next frame. */
1037 else
1038 return frame_unwind_got_register (this_frame, regnum, regnum);
1039}
1040
1041static const struct frame_unwind rl78_unwind =
1042{
1043 NORMAL_FRAME,
1044 default_frame_unwind_stop_reason,
1045 rl78_this_id,
1046 rl78_prev_register,
1047 NULL,
1048 default_frame_sniffer
1049};
1050
1051/* Implement the "dwarf_reg_to_regnum" gdbarch method. */
1052
1053static int
1054rl78_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1055{
1056 if (0 <= reg && reg <= 31)
1057 {
1058 if ((reg & 1) == 0)
1059 /* Map even registers to their 16-bit counterparts. This
1060 is usually what is required from the DWARF info. */
1061 return (reg >> 1) + RL78_BANK0_RP0_REGNUM;
1062 else
1063 return reg;
1064 }
1065 else if (reg == 32)
1066 return RL78_SP_REGNUM;
1067 else if (reg == 33)
b3ce41ea
KB		 1068 return -1; /* ap */
1069 else if (reg == 34)
1070 return RL78_PSW_REGNUM;
1071 else if (reg == 35)
1072 return RL78_ES_REGNUM;
1073 else if (reg == 36)
1074 return RL78_CS_REGNUM;
1075 else if (reg == 37)
9058f767
KB		 1076 return RL78_PC_REGNUM;
1077 else
1078 internal_error (__FILE__, __LINE__,
1079 _("Undefined dwarf2 register mapping of reg %d"),
1080 reg);
1081}
1082
c47a44f4
KB		 1083/* Implement the `register_sim_regno' gdbarch method. */
1084
1085static int
1086rl78_register_sim_regno (struct gdbarch *gdbarch, int regnum)
1087{
1088 gdb_assert (regnum < RL78_NUM_REGS);
1089
1090 /* So long as regnum is in [0, RL78_NUM_REGS), it's valid. We
1091 just want to override the default here which disallows register
1092 numbers which have no names. */
1093 return regnum;
1094}
1095
9058f767
KB		 1096/* Implement the "return_value" gdbarch method. */
1097
1098static enum return_value_convention
1099rl78_return_value (struct gdbarch *gdbarch,
6a3a010b 1100 struct value *function,
9058f767
KB		 1101 struct type *valtype,
1102 struct regcache *regcache,
1103 gdb_byte *readbuf, const gdb_byte *writebuf)
1104{
1105 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1106 ULONGEST valtype_len = TYPE_LENGTH (valtype);
bc3c6b36 1107 int is_g10 = gdbarch_tdep (gdbarch)->elf_flags & E_FLAG_RL78_G10;
9058f767
KB		 1108
1109 if (valtype_len > 8)
1110 return RETURN_VALUE_STRUCT_CONVENTION;
1111
1112 if (readbuf)
1113 {
1114 ULONGEST u;
c47a44f4 1115 int argreg = RL78_RAW_BANK1_R0_REGNUM;
bc3c6b36 1116 CORE_ADDR g10_raddr = 0xffec8;
9058f767
KB		 1117 int offset = 0;
1118
1119 while (valtype_len > 0)
1120 {
bc3c6b36
KB		 1121 if (is_g10)
1122 u = read_memory_integer (g10_raddr, 1,
1123 gdbarch_byte_order (gdbarch));
1124 else
1125 regcache_cooked_read_unsigned (regcache, argreg, &u);
9058f767
KB		 1126 store_unsigned_integer (readbuf + offset, 1, byte_order, u);
1127 valtype_len -= 1;
1128 offset += 1;
1129 argreg++;
bc3c6b36 1130 g10_raddr++;
9058f767
KB		 1131 }
1132 }
1133
1134 if (writebuf)
1135 {
1136 ULONGEST u;
c47a44f4 1137 int argreg = RL78_RAW_BANK1_R0_REGNUM;
bc3c6b36 1138 CORE_ADDR g10_raddr = 0xffec8;
9058f767
KB		 1139 int offset = 0;
1140
1141 while (valtype_len > 0)
1142 {
1143 u = extract_unsigned_integer (writebuf + offset, 1, byte_order);
bc3c6b36
KB		 1144 if (is_g10) {
1145 gdb_byte b = u & 0xff;
1146 write_memory (g10_raddr, &b, 1);
1147 }
1148 else
1149 regcache_cooked_write_unsigned (regcache, argreg, u);
9058f767
KB		 1150 valtype_len -= 1;
1151 offset += 1;
1152 argreg++;
bc3c6b36 1153 g10_raddr++;
9058f767
KB		 1154 }
1155 }
1156
1157 return RETURN_VALUE_REGISTER_CONVENTION;
1158}
1159
1160
1161/* Implement the "frame_align" gdbarch method. */
1162
1163static CORE_ADDR
1164rl78_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1165{
1166 return rl78_make_data_address (align_down (sp, 2));
1167}
1168
1169
1170/* Implement the "dummy_id" gdbarch method. */
1171
1172static struct frame_id
1173rl78_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1174{
1175 return
1176 frame_id_build (rl78_make_data_address
1177 (get_frame_register_unsigned
1178 (this_frame, RL78_SP_REGNUM)),
1179 get_frame_pc (this_frame));
1180}
1181
1182
1183/* Implement the "push_dummy_call" gdbarch method. */
1184
1185static CORE_ADDR
1186rl78_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1187 struct regcache *regcache, CORE_ADDR bp_addr,
1188 int nargs, struct value **args, CORE_ADDR sp,
1189 int struct_return, CORE_ADDR struct_addr)
1190{
1191 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1192 gdb_byte buf[4];
1193 int i;
1194
1195 /* Push arguments in reverse order. */
1196 for (i = nargs - 1; i >= 0; i--)
1197 {
1198 struct type *value_type = value_enclosing_type (args[i]);
1199 int len = TYPE_LENGTH (value_type);
1200 int container_len = (len + 1) & ~1;
9058f767
KB		 1201
1202 sp -= container_len;
1203 write_memory (rl78_make_data_address (sp),
1204 value_contents_all (args[i]), len);
1205 }
1206
1207 /* Store struct value address. */
1208 if (struct_return)
1209 {
1210 store_unsigned_integer (buf, 2, byte_order, struct_addr);
1211 sp -= 2;
1212 write_memory (rl78_make_data_address (sp), buf, 2);
1213 }
1214
1215 /* Store return address. */
1216 sp -= 4;
1217 store_unsigned_integer (buf, 4, byte_order, bp_addr);
1218 write_memory (rl78_make_data_address (sp), buf, 4);
1219
1220 /* Finally, update the stack pointer... */
1221 regcache_cooked_write_unsigned (regcache, RL78_SP_REGNUM, sp);
1222
1223 /* DWARF2/GCC uses the stack address *before* the function call as a
1224 frame's CFA. */
1225 return rl78_make_data_address (sp + 4);
1226}
1227
1228/* Allocate and initialize a gdbarch object. */
1229
1230static struct gdbarch *
1231rl78_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1232{
1233 struct gdbarch *gdbarch;
1234 struct gdbarch_tdep *tdep;
1235 int elf_flags;
1236
1237 /* Extract the elf_flags if available. */
1238 if (info.abfd != NULL
1239 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1240 elf_flags = elf_elfheader (info.abfd)->e_flags;
1241 else
1242 elf_flags = 0;
1243
1244
1245 /* Try to find the architecture in the list of already defined
1246 architectures. */
1247 for (arches = gdbarch_list_lookup_by_info (arches, &info);
1248 arches != NULL;
1249 arches = gdbarch_list_lookup_by_info (arches->next, &info))
1250 {
1251 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
1252 continue;
1253
1254 return arches->gdbarch;
1255 }
1256
1257 /* None found, create a new architecture from the information
1258 provided. */
1259 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
1260 gdbarch = gdbarch_alloc (&info, tdep);
1261 tdep->elf_flags = elf_flags;
1262
1263 /* Initialize types. */
1264 tdep->rl78_void = arch_type (gdbarch, TYPE_CODE_VOID, 1, "void");
1265 tdep->rl78_uint8 = arch_integer_type (gdbarch, 8, 1, "uint8_t");
1266 tdep->rl78_int8 = arch_integer_type (gdbarch, 8, 0, "int8_t");
1267 tdep->rl78_uint16 = arch_integer_type (gdbarch, 16, 1, "uint16_t");
1268 tdep->rl78_int16 = arch_integer_type (gdbarch, 16, 0, "int16_t");
1269 tdep->rl78_uint32 = arch_integer_type (gdbarch, 32, 1, "uint32_t");
1270 tdep->rl78_int32 = arch_integer_type (gdbarch, 32, 0, "int32_t");
1271
1272 tdep->rl78_data_pointer
1273 = arch_type (gdbarch, TYPE_CODE_PTR, 16 / TARGET_CHAR_BIT,
1274 xstrdup ("rl78_data_addr_t"));
1275 TYPE_TARGET_TYPE (tdep->rl78_data_pointer) = tdep->rl78_void;
1276 TYPE_UNSIGNED (tdep->rl78_data_pointer) = 1;
1277
1278 tdep->rl78_code_pointer
1279 = arch_type (gdbarch, TYPE_CODE_PTR, 32 / TARGET_CHAR_BIT,
1280 xstrdup ("rl78_code_addr_t"));
1281 TYPE_TARGET_TYPE (tdep->rl78_code_pointer) = tdep->rl78_void;
1282 TYPE_UNSIGNED (tdep->rl78_code_pointer) = 1;
1283
1284 /* Registers. */
1285 set_gdbarch_num_regs (gdbarch, RL78_NUM_REGS);
1286 set_gdbarch_num_pseudo_regs (gdbarch, RL78_NUM_PSEUDO_REGS);
bc3c6b36
KB		 1287 if (tdep->elf_flags & E_FLAG_RL78_G10)
1288 set_gdbarch_register_name (gdbarch, rl78_g10_register_name);
1289 else
1290 set_gdbarch_register_name (gdbarch, rl78_register_name);
9058f767
KB		 1291 set_gdbarch_register_type (gdbarch, rl78_register_type);
1292 set_gdbarch_pc_regnum (gdbarch, RL78_PC_REGNUM);
1293 set_gdbarch_sp_regnum (gdbarch, RL78_SP_REGNUM);
1294 set_gdbarch_pseudo_register_read (gdbarch, rl78_pseudo_register_read);
1295 set_gdbarch_pseudo_register_write (gdbarch, rl78_pseudo_register_write);
1296 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rl78_dwarf_reg_to_regnum);
c47a44f4
KB		 1297 set_gdbarch_register_reggroup_p (gdbarch, rl78_register_reggroup_p);
1298 set_gdbarch_register_sim_regno (gdbarch, rl78_register_sim_regno);
9058f767
KB		 1299
1300 /* Data types. */
1301 set_gdbarch_char_signed (gdbarch, 0);
1302 set_gdbarch_short_bit (gdbarch, 16);
1303 set_gdbarch_int_bit (gdbarch, 16);
1304 set_gdbarch_long_bit (gdbarch, 32);
1305 set_gdbarch_long_long_bit (gdbarch, 64);
1306 set_gdbarch_ptr_bit (gdbarch, 16);
1307 set_gdbarch_addr_bit (gdbarch, 32);
b3ce41ea 1308 set_gdbarch_dwarf2_addr_size (gdbarch, 4);
9058f767
KB		 1309 set_gdbarch_float_bit (gdbarch, 32);
1310 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1311 set_gdbarch_double_bit (gdbarch, 32);
1312 set_gdbarch_long_double_bit (gdbarch, 64);
1313 set_gdbarch_double_format (gdbarch, floatformats_ieee_single);
1314 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
1315 set_gdbarch_pointer_to_address (gdbarch, rl78_pointer_to_address);
1316 set_gdbarch_address_to_pointer (gdbarch, rl78_address_to_pointer);
1317 set_gdbarch_addr_bits_remove (gdbarch, rl78_addr_bits_remove);
1318
1319 /* Breakpoints. */
1320 set_gdbarch_breakpoint_from_pc (gdbarch, rl78_breakpoint_from_pc);
1321 set_gdbarch_decr_pc_after_break (gdbarch, 1);
1322
1323 /* Disassembly. */
1324 set_gdbarch_print_insn (gdbarch, print_insn_rl78);
1325
1326 /* Frames, prologues, etc. */
1327 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1328 set_gdbarch_skip_prologue (gdbarch, rl78_skip_prologue);
1329 set_gdbarch_unwind_pc (gdbarch, rl78_unwind_pc);
1330 set_gdbarch_unwind_sp (gdbarch, rl78_unwind_sp);
1331 set_gdbarch_frame_align (gdbarch, rl78_frame_align);
b3ce41ea
KB		 1332
1333 dwarf2_append_unwinders (gdbarch);
9058f767
KB		 1334 frame_unwind_append_unwinder (gdbarch, &rl78_unwind);
1335
1336 /* Dummy frames, return values. */
1337 set_gdbarch_dummy_id (gdbarch, rl78_dummy_id);
1338 set_gdbarch_push_dummy_call (gdbarch, rl78_push_dummy_call);
1339 set_gdbarch_return_value (gdbarch, rl78_return_value);
1340
1341 /* Virtual tables. */
1342 set_gdbarch_vbit_in_delta (gdbarch, 1);
1343
1344 return gdbarch;
1345}
1346
693be288
JK		 1347/* -Wmissing-prototypes */
1348extern initialize_file_ftype _initialize_rl78_tdep;
1349
9058f767
KB		 1350/* Register the above initialization routine. */
1351
1352void
1353_initialize_rl78_tdep (void)
1354{
1355 register_gdbarch_init (bfd_arch_rl78, rl78_gdbarch_init);
1356}
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