Update copyright year range in all GDB files

[thirdparty/binutils-gdb.git] / gdb / testsuite / gdb.arch / vsx-regs.exp

# Copyright (C) 2008-2021 Free Software Foundation, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program.  If not, see <http://www.gnu.org/licenses/>.
#

#
# Test the use of VSX registers, for Powerpc.
#


if {![istarget "powerpc*"] || [skip_vsx_tests]} then {
    verbose "Skipping vsx register tests."
    return
}

standard_testfile

set compile_flags {debug nowarnings quiet}
if [get_compiler_info] {
    warning "get_compiler failed"
    return -1
}

if [test_compiler_info gcc*] {
    set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec"
} elseif [test_compiler_info xlc*] {
    set compile_flags "$compile_flags additional_flags=-qaltivec"
} else {
    warning "unknown compiler"
    return -1
}

if  { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } {
     untested "failed to compile"
     return -1
}

gdb_start
gdb_reinitialize_dir $srcdir/$subdir
gdb_load ${binfile}

# Run to `main' where we begin our tests.

if ![runto_main] then {
    fail "can't run to main"
    return 0
}

set endianness [get_endianness]

# Data sets used throughout the test

if {$endianness == "big"} {
    set vector_register1 ".uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."

    set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."

    set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."

    set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."

    set vector_register3 ".uint128 = 0x1000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."

    set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
} else {
    set vector_register1 ".uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0, 0x1., v4_float = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."

    set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."

    set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."

    set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."

    set vector_register3 ".uint128 = 0x1000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."

    set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
}

set float_register ".raw 0xdeadbeefdeadbeef."

# First run the F0~F31/VS0~VS31 tests

# 1: Set F0~F31 registers and check if it reflects on VS0~VS31.
for {set i 0} {$i < 32} {incr i 1} {
    gdb_test_no_output "set \$f$i = 1\.3"
}

for {set i 0} {$i < 32} {incr i 1} {
    gdb_test "info reg vs$i" "vs$i.*$vector_register1" "info reg vs$i (doubleword 0)"
}

# 2: Set VS0~VS31 registers and check if it reflects on F0~F31.
for {set i 0} {$i < 32} {incr i 1} {
        for {set j 0} {$j < 4} {incr j 1} {
           gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef"
        }
}

for {set i 0} {$i < 32} {incr i 1} {
    gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
}

for {set i 0} {$i < 32} {incr i 1} {
    gdb_test "info reg vs$i" "vs$i.*$vector_register2" "info reg vs$i (doubleword 1)"
}

# Now run the VR0~VR31/VS32~VS63 tests

# 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63.
for {set i 0} {$i < 32} {incr i 1} {
        for {set j 0} {$j < 4} {incr j 1} {
           gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 1"
        }
}

for {set i 32} {$i < 64} {incr i 1} {
    gdb_test "info reg vs$i" "vs$i.*$vector_register3" "info reg vs$i"
}
# 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31.
for {set i 32} {$i < 64} {incr i 1} {
        for {set j 0} {$j < 4} {incr j 1} {
           gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 1"
        }
}

for {set i 0} {$i < 32} {incr i 1} {
    gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i"
    gdb_test "info reg v$i" "v$i.*$vector_register3_vr" "info reg v$i"
}

# Create a core file.  We create the core file before the F32~F63/VR0~VR31 test
# below because then we'll have more interesting register values to verify
# later when loading the core file (i.e., different register values for different
# vector register banks).

set corefile [standard_output_file vsx-core.test]
set core_supported [gdb_gcore_cmd "$corefile" "Save a VSX-enabled corefile"]

# Now run the F32~F63/VR0~VR31 tests.

# 1: Set F32~F63 registers and check if it reflects on VR0~VR31.
for {set i 32} {$i < 64} {incr i 1} {
    gdb_test_no_output "set \$f$i = 1\.3"
}

for {set i 0} {$i < 32} {incr i 1} {
    gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (doubleword 0)"
    gdb_test "info reg v$i" "v$i.*$vector_register1_vr" "info reg v$i (doubleword 0)"
}

# 2: Set VR0~VR31 registers and check if it reflects on F32~F63.
for {set i 0} {$i < 32} {incr i 1} {
        for {set j 0} {$j < 4} {incr j 1} {
           gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 0xdeadbeef"
        }
}

for {set i 32} {$i < 64} {incr i 1} {
    gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
}

for {set i 0} {$i < 32} {incr i 1} {
    gdb_test "info reg vr$i" "vr$i.*$vector_register2_vr" "info reg vr$i (doubleword 1)"
    gdb_test "info reg v$i" "v$i.*$vector_register2_vr" "info reg v$i (doubleword 1)"
}

# Test reading the core file.

if {!$core_supported} {
  return -1
}

gdb_exit
gdb_start
gdb_reinitialize_dir $srcdir/$subdir
gdb_load ${binfile}

set core_loaded [gdb_core_cmd "$corefile" "re-load generated corefile"]
if { $core_loaded == -1 } {
    # No use proceeding from here.
    return
}

for {set i 0} {$i < 32} {incr i 1} {
    gdb_test "info reg vs$i" "vs$i.*$vector_register2" "restore vs$i from core file"
}

for {set i 32} {$i < 64} {incr i 1} {
    gdb_test "info reg vs$i" "vs$i.*$vector_register3" "restore vs$i from core file"
}