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ade64f0e
PA		 1/* Target-dependent code for the Tilera TILE-Gx processor.
2
8acc9f48 3 Copyright (C) 2012-2013 Free Software Foundation, Inc.
ade64f0e
PA		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include "defs.h"
21#include "frame.h"
22#include "frame-base.h"
23#include "frame-unwind.h"
24#include "dwarf2-frame.h"
25#include "trad-frame.h"
26#include "symtab.h"
27#include "gdbtypes.h"
28#include "gdbcmd.h"
29#include "gdbcore.h"
30#include "value.h"
31#include "dis-asm.h"
32#include "inferior.h"
33#include "gdb_string.h"
34#include "gdb_assert.h"
35#include "arch-utils.h"
36#include "floatformat.h"
37#include "regcache.h"
38#include "regset.h"
39#include "doublest.h"
40#include "osabi.h"
41#include "linux-tdep.h"
42#include "objfiles.h"
43#include "solib-svr4.h"
44#include "symtab.h"
45#include "tilegx-tdep.h"
46#include "opcode/tilegx.h"
47
48struct tilegx_frame_cache
49{
50 /* Base address. */
51 CORE_ADDR base;
52 /* Function start. */
53 CORE_ADDR start_pc;
54
55 /* Table of saved registers. */
56 struct trad_frame_saved_reg *saved_regs;
57};
58
59/* Register state values used by analyze_prologue. */
60enum reverse_state
61 {
62 REVERSE_STATE_REGISTER,
63 REVERSE_STATE_VALUE,
64 REVERSE_STATE_UNKNOWN
65 };
66
67/* Register state used by analyze_prologue(). */
68struct tilegx_reverse_regs
69{
70 LONGEST value;
71 enum reverse_state state;
72};
73
74static const struct tilegx_reverse_regs
75template_reverse_regs[TILEGX_NUM_PHYS_REGS] =
76 {
77 { TILEGX_R0_REGNUM, REVERSE_STATE_REGISTER },
78 { TILEGX_R1_REGNUM, REVERSE_STATE_REGISTER },
79 { TILEGX_R2_REGNUM, REVERSE_STATE_REGISTER },
80 { TILEGX_R3_REGNUM, REVERSE_STATE_REGISTER },
81 { TILEGX_R4_REGNUM, REVERSE_STATE_REGISTER },
82 { TILEGX_R5_REGNUM, REVERSE_STATE_REGISTER },
83 { TILEGX_R6_REGNUM, REVERSE_STATE_REGISTER },
84 { TILEGX_R7_REGNUM, REVERSE_STATE_REGISTER },
85 { TILEGX_R8_REGNUM, REVERSE_STATE_REGISTER },
86 { TILEGX_R9_REGNUM, REVERSE_STATE_REGISTER },
87 { TILEGX_R10_REGNUM, REVERSE_STATE_REGISTER },
88 { TILEGX_R11_REGNUM, REVERSE_STATE_REGISTER },
89 { TILEGX_R12_REGNUM, REVERSE_STATE_REGISTER },
90 { TILEGX_R13_REGNUM, REVERSE_STATE_REGISTER },
91 { TILEGX_R14_REGNUM, REVERSE_STATE_REGISTER },
92 { TILEGX_R15_REGNUM, REVERSE_STATE_REGISTER },
93 { TILEGX_R16_REGNUM, REVERSE_STATE_REGISTER },
94 { TILEGX_R17_REGNUM, REVERSE_STATE_REGISTER },
95 { TILEGX_R18_REGNUM, REVERSE_STATE_REGISTER },
96 { TILEGX_R19_REGNUM, REVERSE_STATE_REGISTER },
97 { TILEGX_R20_REGNUM, REVERSE_STATE_REGISTER },
98 { TILEGX_R21_REGNUM, REVERSE_STATE_REGISTER },
99 { TILEGX_R22_REGNUM, REVERSE_STATE_REGISTER },
100 { TILEGX_R23_REGNUM, REVERSE_STATE_REGISTER },
101 { TILEGX_R24_REGNUM, REVERSE_STATE_REGISTER },
102 { TILEGX_R25_REGNUM, REVERSE_STATE_REGISTER },
103 { TILEGX_R26_REGNUM, REVERSE_STATE_REGISTER },
104 { TILEGX_R27_REGNUM, REVERSE_STATE_REGISTER },
105 { TILEGX_R28_REGNUM, REVERSE_STATE_REGISTER },
106 { TILEGX_R29_REGNUM, REVERSE_STATE_REGISTER },
107 { TILEGX_R30_REGNUM, REVERSE_STATE_REGISTER },
108 { TILEGX_R31_REGNUM, REVERSE_STATE_REGISTER },
109 { TILEGX_R32_REGNUM, REVERSE_STATE_REGISTER },
110 { TILEGX_R33_REGNUM, REVERSE_STATE_REGISTER },
111 { TILEGX_R34_REGNUM, REVERSE_STATE_REGISTER },
112 { TILEGX_R35_REGNUM, REVERSE_STATE_REGISTER },
113 { TILEGX_R36_REGNUM, REVERSE_STATE_REGISTER },
114 { TILEGX_R37_REGNUM, REVERSE_STATE_REGISTER },
115 { TILEGX_R38_REGNUM, REVERSE_STATE_REGISTER },
116 { TILEGX_R39_REGNUM, REVERSE_STATE_REGISTER },
117 { TILEGX_R40_REGNUM, REVERSE_STATE_REGISTER },
118 { TILEGX_R41_REGNUM, REVERSE_STATE_REGISTER },
119 { TILEGX_R42_REGNUM, REVERSE_STATE_REGISTER },
120 { TILEGX_R43_REGNUM, REVERSE_STATE_REGISTER },
121 { TILEGX_R44_REGNUM, REVERSE_STATE_REGISTER },
122 { TILEGX_R45_REGNUM, REVERSE_STATE_REGISTER },
123 { TILEGX_R46_REGNUM, REVERSE_STATE_REGISTER },
124 { TILEGX_R47_REGNUM, REVERSE_STATE_REGISTER },
125 { TILEGX_R48_REGNUM, REVERSE_STATE_REGISTER },
126 { TILEGX_R49_REGNUM, REVERSE_STATE_REGISTER },
127 { TILEGX_R50_REGNUM, REVERSE_STATE_REGISTER },
128 { TILEGX_R51_REGNUM, REVERSE_STATE_REGISTER },
129 { TILEGX_R52_REGNUM, REVERSE_STATE_REGISTER },
130 { TILEGX_TP_REGNUM, REVERSE_STATE_REGISTER },
131 { TILEGX_SP_REGNUM, REVERSE_STATE_REGISTER },
132 { TILEGX_LR_REGNUM, REVERSE_STATE_REGISTER },
133 { 0, REVERSE_STATE_UNKNOWN },
134 { 0, REVERSE_STATE_UNKNOWN },
135 { 0, REVERSE_STATE_UNKNOWN },
136 { 0, REVERSE_STATE_UNKNOWN },
137 { 0, REVERSE_STATE_UNKNOWN },
138 { 0, REVERSE_STATE_UNKNOWN },
139 { 0, REVERSE_STATE_UNKNOWN },
140 { TILEGX_ZERO_REGNUM, REVERSE_STATE_VALUE }
141 };
142
143/* Implement the "register_name" gdbarch method. */
144
145static const char *
146tilegx_register_name (struct gdbarch *gdbarch, int regnum)
147{
148 static const char *const register_names[TILEGX_NUM_REGS] =
149 {
150 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
151 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
152 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
153 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
154 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
155 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
156 "r48", "r49", "r50", "r51", "r52", "tp", "sp", "lr",
157 "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn3", "zero",
158 "pc"
159 };
160
161 if (regnum < 0 || regnum >= TILEGX_NUM_REGS)
162 internal_error (__FILE__, __LINE__,
163 "tilegx_register_name: invalid register number %d",
164 regnum);
165
166 return register_names[regnum];
167}
168
169/* This is the implementation of gdbarch method register_type. */
170
171static struct type *
172tilegx_register_type (struct gdbarch *gdbarch, int regnum)
173{
174 if (regnum == TILEGX_PC_REGNUM)
175 return builtin_type (gdbarch)->builtin_func_ptr;
176 else
177 return builtin_type (gdbarch)->builtin_uint64;
178}
179
180/* This is the implementation of gdbarch method dwarf2_reg_to_regnum. */
181
182static int
183tilegx_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
184{
185 return num;
186}
187
188/* Makes the decision of whether a given type is a scalar type.
189 Scalar types are returned in the registers r2-r11 as they fit. */
190
191static int
192tilegx_type_is_scalar (struct type *t)
193{
194 return (TYPE_CODE(t) != TYPE_CODE_STRUCT
195 && TYPE_CODE(t) != TYPE_CODE_UNION
196 && TYPE_CODE(t) != TYPE_CODE_ARRAY);
197}
198
199/* Returns non-zero if the given struct type will be returned using
200 a special convention, rather than the normal function return method.
201 Used in the context of the "return" command, and target function
202 calls from the debugger. */
203
204static int
205tilegx_use_struct_convention (struct type *type)
206{
207 /* Only scalars which fit in R0 - R9 can be returned in registers.
208 Otherwise, they are returned via a pointer passed in R0. */
209 return (!tilegx_type_is_scalar (type)
210 && (TYPE_LENGTH (type) > (1 + TILEGX_R9_REGNUM - TILEGX_R0_REGNUM)
211 * tilegx_reg_size));
212}
213
214/* Find a function's return value in the appropriate registers (in
215 REGCACHE), and copy it into VALBUF. */
216
217static void
218tilegx_extract_return_value (struct type *type, struct regcache *regcache,
219 gdb_byte *valbuf)
220{
221 int len = TYPE_LENGTH (type);
222 int i, regnum = TILEGX_R0_REGNUM;
223
224 for (i = 0; i < len; i += tilegx_reg_size)
225 regcache_raw_read (regcache, regnum++, valbuf + i);
226}
227
228/* Copy the function return value from VALBUF into the proper
229 location for a function return.
230 Called only in the context of the "return" command. */
231
232static void
233tilegx_store_return_value (struct type *type, struct regcache *regcache,
234 const void *valbuf)
235{
236 if (TYPE_LENGTH (type) < tilegx_reg_size)
237 {
238 /* Add leading zeros to the (little-endian) value. */
239 gdb_byte buf[tilegx_reg_size] = { 0 };
240
241 memcpy (buf, valbuf, TYPE_LENGTH (type));
242 regcache_raw_write (regcache, TILEGX_R0_REGNUM, buf);
243 }
244 else
245 {
246 int len = TYPE_LENGTH (type);
247 int i, regnum = TILEGX_R0_REGNUM;
248
249 for (i = 0; i < len; i += tilegx_reg_size)
250 regcache_raw_write (regcache, regnum++, (gdb_byte *) valbuf + i);
251 }
252}
253
254/* This is the implementation of gdbarch method return_value. */
255
256static enum return_value_convention
257tilegx_return_value (struct gdbarch *gdbarch, struct value *function,
258 struct type *type, struct regcache *regcache,
259 gdb_byte *readbuf, const gdb_byte *writebuf)
260{
261 if (tilegx_use_struct_convention (type))
262 return RETURN_VALUE_STRUCT_CONVENTION;
263 if (writebuf)
264 tilegx_store_return_value (type, regcache, writebuf);
265 else if (readbuf)
266 tilegx_extract_return_value (type, regcache, readbuf);
267 return RETURN_VALUE_REGISTER_CONVENTION;
268}
269
270/* This is the implementation of gdbarch method frame_align. */
271
272static CORE_ADDR
273tilegx_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
274{
275 return addr & -8;
276}
277
278
279/* Implement the "push_dummy_call" gdbarch method. */
280
281static CORE_ADDR
282tilegx_push_dummy_call (struct gdbarch *gdbarch,
283 struct value *function,
284 struct regcache *regcache,
285 CORE_ADDR bp_addr, int nargs,
286 struct value **args,
287 CORE_ADDR sp, int struct_return,
288 CORE_ADDR struct_addr)
289{
290 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
291 CORE_ADDR stack_dest = sp;
292 int argreg = TILEGX_R0_REGNUM;
293 int i, j;
294 int typelen, slacklen, alignlen;
295 static const gdb_byte two_zero_words[8] = { 0 };
296
297 /* If struct_return is 1, then the struct return address will
298 consume one argument-passing register. */
299 if (struct_return)
300 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
301
302 /* Arguments are passed in R0 - R9, and as soon as an argument
303 will not fit completely in the remaining registers, then it,
304 and all remaining arguments, are put on the stack. */
305 for (i = 0; i < nargs && argreg <= TILEGX_R9_REGNUM; i++)
306 {
307 const gdb_byte *val;
308 typelen = TYPE_LENGTH (value_enclosing_type (args[i]));
309
310 if (typelen > (TILEGX_R9_REGNUM - argreg + 1) * tilegx_reg_size)
311 break;
312
313 /* Put argument into registers wordwise. */
314 val = value_contents (args[i]);
315 for (j = 0; j < typelen; j += tilegx_reg_size)
316 {
317 /* ISSUE: Why special handling for "typelen = 4x + 1"?
318 I don't ever see "typelen" values except 4 and 8. */
319 int n = (typelen - j == 1) ? 1 : tilegx_reg_size;
320 ULONGEST w = extract_unsigned_integer (val + j, n, byte_order);
321
322 regcache_cooked_write_unsigned (regcache, argreg++, w);
323 }
324 }
325
326 /* Align SP. */
327 stack_dest = tilegx_frame_align (gdbarch, stack_dest);
328
329 /* Loop backwards through arguments to determine stack alignment. */
330 alignlen = 0;
331
332 for (j = nargs - 1; j >= i; j--)
333 {
334 typelen = TYPE_LENGTH (value_enclosing_type (args[j]));
335 alignlen += (typelen + 3) & (~3);
336 }
337
338 if (alignlen & 0x4)
339 stack_dest -= 4;
340
341 /* Loop backwards through remaining arguments and push them on
342 the stack, word aligned. */
343 for (j = nargs - 1; j >= i; j--)
344 {
345 gdb_byte *val;
ecfb0d68
SP		 346 struct cleanup *back_to;
347 const gdb_byte *contents = value_contents (args[j]);
ade64f0e
PA		 348
349 typelen = TYPE_LENGTH (value_enclosing_type (args[j]));
350 slacklen = ((typelen + 3) & (~3)) - typelen;
ecfb0d68
SP		 351 val = xmalloc (typelen + slacklen);
352 back_to = make_cleanup (xfree, val);
353 memcpy (val, contents, typelen);
ade64f0e
PA		 354 memset (val + typelen, 0, slacklen);
355
356 /* Now write data to the stack. The stack grows downwards. */
357 stack_dest -= typelen + slacklen;
358 write_memory (stack_dest, val, typelen + slacklen);
ecfb0d68 359 do_cleanups (back_to);
ade64f0e
PA		 360 }
361
362 /* Add 2 words for linkage space to the stack. */
363 stack_dest = stack_dest - 8;
364 write_memory (stack_dest, two_zero_words, 8);
365
366 /* Update stack pointer. */
367 regcache_cooked_write_unsigned (regcache, TILEGX_SP_REGNUM, stack_dest);
368
369 /* Set the return address register to point to the entry point of
370 the program, where a breakpoint lies in wait. */
371 regcache_cooked_write_unsigned (regcache, TILEGX_LR_REGNUM, bp_addr);
372
373 return stack_dest;
374}
375
376
377/* Decode the instructions within the given address range.
378 Decide when we must have reached the end of the function prologue.
379 If a frame_info pointer is provided, fill in its saved_regs etc.
380 Returns the address of the first instruction after the prologue.
381 NOTE: This is often called with start_addr being the start of some
382 function, and end_addr being the current PC. */
383
384static CORE_ADDR
385tilegx_analyze_prologue (struct gdbarch* gdbarch,
386 CORE_ADDR start_addr, CORE_ADDR end_addr,
387 struct tilegx_frame_cache *cache,
388 struct frame_info *next_frame)
389{
390 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
391 CORE_ADDR next_addr;
392 CORE_ADDR prolog_end = end_addr;
393 ULONGEST inst, inst2;
394 LONGEST offset;
395 int regnum;
396 gdb_byte instbuf[32 * TILEGX_BUNDLE_SIZE_IN_BYTES];
397 CORE_ADDR instbuf_start;
398 unsigned int instbuf_size;
399 int status;
400 bfd_uint64_t bundle;
401 struct tilegx_decoded_instruction
402 decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
403 int num_insns;
404 struct tilegx_reverse_regs reverse_frame[TILEGX_NUM_PHYS_REGS];
405 struct tilegx_reverse_regs
406 new_reverse_frame[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
407 int dest_regs[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
408 int reverse_frame_valid, prolog_done, branch_seen;
409 LONGEST prev_sp_value;
410 int i, j;
411
412 if (start_addr >= end_addr
413 || (start_addr % TILEGX_BUNDLE_ALIGNMENT_IN_BYTES) != 0)
414 return end_addr;
415
416 /* Initialize the reverse frame. This maps the CURRENT frame's
417 registers to the outer frame's registers (the frame on the
418 stack goes the other way). */
419 memcpy (&reverse_frame, &template_reverse_regs, sizeof (reverse_frame));
420
421 prolog_done = 0;
422 branch_seen = 0;
423 prev_sp_value = 0;
424
425 /* To cut down on round-trip overhead, we fetch multiple bundles
426 at once. These variables describe the range of memory we have
427 prefetched. */
428 instbuf_start = 0;
429 instbuf_size = 0;
430
431 for (next_addr = start_addr;
432 next_addr < end_addr;
433 next_addr += TILEGX_BUNDLE_SIZE_IN_BYTES)
434 {
435 /* Retrieve the next instruction. */
436 if (next_addr - instbuf_start >= instbuf_size)
437 {
438 /* Figure out how many bytes to fetch. Don't span a page
439 boundary since that might cause an unnecessary memory
440 error. */
441 unsigned int size_on_same_page = 4096 - (next_addr & 4095);
442
443 instbuf_size = sizeof instbuf;
444
445 if (instbuf_size > size_on_same_page)
446 instbuf_size = size_on_same_page;
447 instbuf_start = next_addr;
448
449 status = safe_frame_unwind_memory (next_frame, instbuf_start,
450 instbuf, instbuf_size);
451 if (status == 0)
452 memory_error (status, next_addr);
453 }
454
455 reverse_frame_valid = 0;
456
457 bundle = extract_unsigned_integer (&instbuf[next_addr - instbuf_start],
458 8, byte_order);
459
460 num_insns = parse_insn_tilegx (bundle, next_addr, decoded);
461
462 for (i = 0; i < num_insns; i++)
463 {
464 struct tilegx_decoded_instruction *this_insn = &decoded[i];
465 int64_t *operands = (int64_t *) this_insn->operand_values;
466 const struct tilegx_opcode *opcode = this_insn->opcode;
467
468 switch (opcode->mnemonic)
469 {
470 case TILEGX_OPC_ST:
471 if (cache
472 && reverse_frame[operands[0]].state == REVERSE_STATE_VALUE
473 && reverse_frame[operands[1]].state
474 == REVERSE_STATE_REGISTER)
475 {
476 LONGEST saved_address = reverse_frame[operands[0]].value;
477 unsigned saved_register
478 = (unsigned) reverse_frame[operands[1]].value;
479
480 /* realreg >= 0 and addr != -1 indicates that the
481 value of saved_register is in memory location
482 saved_address. The value of realreg is not
483 meaningful in this case but it must be >= 0.
484 See trad-frame.h. */
485 cache->saved_regs[saved_register].realreg = saved_register;
486 cache->saved_regs[saved_register].addr = saved_address;
487 }
488 break;
489 case TILEGX_OPC_ADDI:
490 case TILEGX_OPC_ADDLI:
491 if (cache
492 && operands[0] == TILEGX_SP_REGNUM
493 && operands[1] == TILEGX_SP_REGNUM
494 && reverse_frame[operands[1]].state == REVERSE_STATE_REGISTER)
495 {
496 /* Special case. We're fixing up the stack frame. */
497 uint64_t hopefully_sp
498 = (unsigned) reverse_frame[operands[1]].value;
499 short op2_as_short = (short) operands[2];
500 signed char op2_as_char = (signed char) operands[2];
501
502 /* Fix up the sign-extension. */
503 if (opcode->mnemonic == TILEGX_OPC_ADDI)
504 op2_as_short = op2_as_char;
505 prev_sp_value = (cache->saved_regs[hopefully_sp].addr
506 - op2_as_short);
507
508 new_reverse_frame[i].state = REVERSE_STATE_VALUE;
509 new_reverse_frame[i].value
510 = cache->saved_regs[hopefully_sp].addr;
511 trad_frame_set_value (cache->saved_regs,
512 hopefully_sp, prev_sp_value);
513 }
514 else
515 {
516 short op2_as_short = (short) operands[2];
517 signed char op2_as_char = (signed char) operands[2];
518
519 /* Fix up the sign-extension. */
520 if (opcode->mnemonic == TILEGX_OPC_ADDI)
521 op2_as_short = op2_as_char;
522
523 new_reverse_frame[i] = reverse_frame[operands[1]];
524 if (new_reverse_frame[i].state == REVERSE_STATE_VALUE)
525 new_reverse_frame[i].value += op2_as_short;
526 else
527 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
528 }
529 reverse_frame_valid |= 1 << i;
530 dest_regs[i] = operands[0];
531 break;
532 case TILEGX_OPC_ADD:
533 if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE
534 && reverse_frame[operands[2]].state == REVERSE_STATE_VALUE)
535 {
536 /* We have values -- we can do this. */
537 new_reverse_frame[i] = reverse_frame[operands[2]];
538 new_reverse_frame[i].value
539 += reverse_frame[operands[i]].value;
540 }
541 else
542 {
543 /* We don't know anything about the values. Punt. */
544 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
545 }
546 reverse_frame_valid |= 1 << i;
547 dest_regs[i] = operands[0];
548 break;
549 case TILEGX_OPC_MOVE:
550 new_reverse_frame[i] = reverse_frame[operands[1]];
551 reverse_frame_valid |= 1 << i;
552 dest_regs[i] = operands[0];
553 break;
554 case TILEGX_OPC_MOVEI:
555 case TILEGX_OPC_MOVELI:
556 new_reverse_frame[i].state = REVERSE_STATE_VALUE;
557 new_reverse_frame[i].value = operands[1];
558 reverse_frame_valid |= 1 << i;
559 dest_regs[i] = operands[0];
560 break;
561 case TILEGX_OPC_ORI:
562 if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE)
563 {
564 /* We have a value in A -- we can do this. */
565 new_reverse_frame[i] = reverse_frame[operands[1]];
566 new_reverse_frame[i].value
567 = reverse_frame[operands[1]].value | operands[2];
568 }
569 else if (operands[2] == 0)
570 {
571 /* This is a move. */
572 new_reverse_frame[i] = reverse_frame[operands[1]];
573 }
574 else
575 {
576 /* We don't know anything about the values. Punt. */
577 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
578 }
579 reverse_frame_valid |= 1 << i;
580 dest_regs[i] = operands[0];
581 break;
582 case TILEGX_OPC_OR:
583 if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE
584 && reverse_frame[operands[1]].value == 0)
585 {
586 /* This is a move. */
587 new_reverse_frame[i] = reverse_frame[operands[2]];
588 }
589 else if (reverse_frame[operands[2]].state == REVERSE_STATE_VALUE
590 && reverse_frame[operands[2]].value == 0)
591 {
592 /* This is a move. */
593 new_reverse_frame[i] = reverse_frame[operands[1]];
594 }
595 else
596 {
597 /* We don't know anything about the values. Punt. */
598 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
599 }
600 reverse_frame_valid |= 1 << i;
601 dest_regs[i] = operands[0];
602 break;
603 case TILEGX_OPC_SUB:
604 if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE
605 && reverse_frame[operands[2]].state == REVERSE_STATE_VALUE)
606 {
607 /* We have values -- we can do this. */
608 new_reverse_frame[i] = reverse_frame[operands[1]];
609 new_reverse_frame[i].value
610 -= reverse_frame[operands[2]].value;
611 }
612 else
613 {
614 /* We don't know anything about the values. Punt. */
615 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
616 }
617 reverse_frame_valid |= 1 << i;
618 dest_regs[i] = operands[0];
619 break;
620
621 case TILEGX_OPC_FNOP:
622 case TILEGX_OPC_INFO:
623 case TILEGX_OPC_INFOL:
624 /* Nothing to see here, move on.
625 Note that real NOP is treated as a 'real' instruction
626 because someone must have intended that it be there.
627 It therefore terminates the prolog. */
628 break;
629
630 case TILEGX_OPC_J:
631 case TILEGX_OPC_JAL:
632
633 case TILEGX_OPC_BEQZ:
634 case TILEGX_OPC_BEQZT:
635 case TILEGX_OPC_BGEZ:
636 case TILEGX_OPC_BGEZT:
637 case TILEGX_OPC_BGTZ:
638 case TILEGX_OPC_BGTZT:
639 case TILEGX_OPC_BLBC:
640 case TILEGX_OPC_BLBCT:
641 case TILEGX_OPC_BLBS:
642 case TILEGX_OPC_BLBST:
643 case TILEGX_OPC_BLEZ:
644 case TILEGX_OPC_BLEZT:
645 case TILEGX_OPC_BLTZ:
646 case TILEGX_OPC_BLTZT:
647 case TILEGX_OPC_BNEZ:
648 case TILEGX_OPC_BNEZT:
649
650 case TILEGX_OPC_IRET:
651 case TILEGX_OPC_JALR:
652 case TILEGX_OPC_JALRP:
653 case TILEGX_OPC_JR:
654 case TILEGX_OPC_JRP:
655 case TILEGX_OPC_SWINT0:
656 case TILEGX_OPC_SWINT1:
657 case TILEGX_OPC_SWINT2:
658 case TILEGX_OPC_SWINT3:
659 /* We're really done -- this is a branch. */
660 branch_seen = 1;
661 prolog_done = 1;
662 break;
663 default:
664 /* We don't know or care what this instruction is.
665 All we know is that it isn't part of a prolog, and if
666 there's a destination register, we're trashing it. */
667 prolog_done = 1;
668 for (j = 0; j < opcode->num_operands; j++)
669 {
670 if (this_insn->operands[j]->is_dest_reg)
671 {
672 dest_regs[i] = operands[j];
673 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
674 reverse_frame_valid |= 1 << i;
675 break;
676 }
677 }
678 break;
679 }
680 }
681
682 /* Now update the reverse frames. */
683 for (i = 0; i < num_insns; i++)
684 {
685 /* ISSUE: Does this properly handle "network" registers? */
686 if ((reverse_frame_valid & (1 << i))
687 && dest_regs[i] != TILEGX_ZERO_REGNUM)
688 reverse_frame[dest_regs[i]] = new_reverse_frame[i];
689 }
690
691 if (prev_sp_value != 0)
692 {
693 /* GCC uses R52 as a frame pointer. Have we seen "move r52, sp"? */
694 if (reverse_frame[TILEGX_R52_REGNUM].state == REVERSE_STATE_REGISTER
695 && reverse_frame[TILEGX_R52_REGNUM].value == TILEGX_SP_REGNUM)
696 {
697 reverse_frame[TILEGX_R52_REGNUM].state = REVERSE_STATE_VALUE;
698 reverse_frame[TILEGX_R52_REGNUM].value = prev_sp_value;
699 }
700
701 prev_sp_value = 0;
702 }
703
704 if (prolog_done && prolog_end == end_addr)
705 {
706 /* We found non-prolog code. As such, _this_ instruction
707 is the one after the prolog. We keep processing, because
708 there may be more prolog code in there, but this is what
709 we'll return. */
710 /* ISSUE: There may not have actually been a prologue, and
711 we may have simply skipped some random instructions. */
712 prolog_end = next_addr;
713 }
714 if (branch_seen)
715 {
716 /* We saw a branch. The prolog absolutely must be over. */
717 break;
718 }
719 }
720
721 if (prolog_end == end_addr && cache)
722 {
723 /* We may have terminated the prolog early, and we're certainly
724 at THIS point right now. It's possible that the values of
725 registers we need are currently actually in other registers
726 (and haven't been written to memory yet). Go find them. */
727 for (i = 0; i < TILEGX_NUM_PHYS_REGS; i++)
728 {
729 if (reverse_frame[i].state == REVERSE_STATE_REGISTER
730 && reverse_frame[i].value != i)
731 {
732 unsigned saved_register = (unsigned) reverse_frame[i].value;
733
734 cache->saved_regs[saved_register].realreg = i;
735 cache->saved_regs[saved_register].addr = (LONGEST) -1;
736 }
737 }
738 }
739
740 return prolog_end;
741}
742
743/* This is the implementation of gdbarch method skip_prologue. */
744
745static CORE_ADDR
746tilegx_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
747{
748 struct symtab_and_line sal;
749 CORE_ADDR func_start, func_end;
750
751 /* This is the preferred method, find the end of the prologue by
752 using the debugging information. */
753 if (find_pc_partial_function (pc, NULL, &func_start, &func_end))
754 {
755 sal = find_pc_line (func_start, 0);
756
757 if (sal.end < func_end && pc <= sal.end)
758 return sal.end;
759 }
760
761 /* Otherwise, try to skip prologue the hard way. */
762 return tilegx_analyze_prologue (gdbarch,
763 pc, pc + 8 * TILEGX_BUNDLE_SIZE_IN_BYTES,
764 NULL, NULL);
765}
766
767/* This is the implementation of gdbarch method in_function_epilogue_p. */
768
769static int
770tilegx_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
771{
772 CORE_ADDR func_addr = 0, func_end = 0;
773
774 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
775 {
776 ULONGEST inst, inst2;
777 CORE_ADDR addr = func_end - TILEGX_BUNDLE_SIZE_IN_BYTES;
778
779 /* FIXME: Find the actual epilogue. */
780 /* HACK: Just assume the final bundle is the "ret" instruction". */
781 if (pc > addr)
782 return 1;
783 }
784 return 0;
785}
786
787/* This is the implementation of gdbarch method breakpoint_from_pc. */
788
789static const unsigned char *
790tilegx_breakpoint_from_pc (struct gdbarch *gdbarch,
791 CORE_ADDR *pcptr, int *lenptr)
792{
793 /* 64-bit pattern for a { bpt ; nop } bundle. */
794 static const unsigned char breakpoint[] =
795 { 0x00, 0x50, 0x48, 0x51, 0xae, 0x44, 0x6a, 0x28 };
796
797 *lenptr = sizeof (breakpoint);
798 return breakpoint;
799}
800
801/* Normal frames. */
802
803static struct tilegx_frame_cache *
804tilegx_frame_cache (struct frame_info *this_frame, void **this_cache)
805{
806 struct gdbarch *gdbarch = get_frame_arch (this_frame);
807 struct tilegx_frame_cache *cache;
808 CORE_ADDR current_pc;
809 int i;
810
811 if (*this_cache)
812 return *this_cache;
813
814 cache = FRAME_OBSTACK_ZALLOC (struct tilegx_frame_cache);
815 *this_cache = cache;
816 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
817 cache->base = 0;
818 cache->start_pc = get_frame_func (this_frame);
819 current_pc = get_frame_pc (this_frame);
820
821 cache->base = get_frame_register_unsigned (this_frame, TILEGX_SP_REGNUM);
822 trad_frame_set_value (cache->saved_regs, TILEGX_SP_REGNUM, cache->base);
823
824 cache->saved_regs[TILEGX_PC_REGNUM] = cache->saved_regs[TILEGX_LR_REGNUM];
825 if (cache->start_pc)
826 tilegx_analyze_prologue (gdbarch, cache->start_pc, current_pc,
827 cache, this_frame);
828
829 return cache;
830}
831
832/* Retrieve the value of REGNUM in FRAME. */
833
834static struct value*
835tilegx_frame_prev_register (struct frame_info *this_frame,
836 void **this_cache,
837 int regnum)
838{
839 struct tilegx_frame_cache *info =
840 tilegx_frame_cache (this_frame, this_cache);
841
842 return trad_frame_get_prev_register (this_frame, info->saved_regs,
843 regnum);
844}
845
846/* Build frame id. */
847
848static void
849tilegx_frame_this_id (struct frame_info *this_frame, void **this_cache,
850 struct frame_id *this_id)
851{
852 struct tilegx_frame_cache *info =
853 tilegx_frame_cache (this_frame, this_cache);
854
855 /* This marks the outermost frame. */
856 if (info->base == 0)
857 return;
858
859 (*this_id) = frame_id_build (info->base, info->start_pc);
860}
861
862static CORE_ADDR
863tilegx_frame_base_address (struct frame_info *this_frame, void **this_cache)
864{
865 struct tilegx_frame_cache *cache =
866 tilegx_frame_cache (this_frame, this_cache);
867
868 return cache->base;
869}
870
871static const struct frame_unwind tilegx_frame_unwind = {
872 NORMAL_FRAME,
873 default_frame_unwind_stop_reason,
874 tilegx_frame_this_id,
875 tilegx_frame_prev_register,
876 NULL, /* const struct frame_data *unwind_data */
877 default_frame_sniffer, /* frame_sniffer_ftype *sniffer */
878 NULL /* frame_prev_pc_ftype *prev_pc */
879};
880
881static const struct frame_base tilegx_frame_base = {
882 &tilegx_frame_unwind,
883 tilegx_frame_base_address,
884 tilegx_frame_base_address,
885 tilegx_frame_base_address
886};
887
888static CORE_ADDR
889tilegx_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
890{
891 return frame_unwind_register_unsigned (next_frame, TILEGX_SP_REGNUM);
892}
893
894static CORE_ADDR
895tilegx_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
896{
897 return frame_unwind_register_unsigned (next_frame, TILEGX_PC_REGNUM);
898}
899
900static struct frame_id
901tilegx_unwind_dummy_id (struct gdbarch *gdbarch,
902 struct frame_info *this_frame)
903{
904 CORE_ADDR sp;
905
906 sp = get_frame_register_unsigned (this_frame, TILEGX_SP_REGNUM);
907 return frame_id_build (sp, get_frame_pc (this_frame));
908}
909
910
911/* We cannot read/write the "special" registers. */
912
913static int
914tilegx_cannot_reference_register (struct gdbarch *gdbarch, int regno)
915{
916 if (regno >= 0 && regno < TILEGX_NUM_EASY_REGS)
917 return 0;
918 else if (regno == TILEGX_PC_REGNUM)
919 return 0;
920 else
921 return 1;
922}
923
924static struct gdbarch *
925tilegx_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
926{
927 struct gdbarch *gdbarch;
928 int arch_size = 64;
929
930 /* Handle arch_size == 32 or 64. Default to 64. */
931 if (info.abfd)
932 arch_size = bfd_get_arch_size (info.abfd);
933
934 /* Try to find a pre-existing architecture. */
935 for (arches = gdbarch_list_lookup_by_info (arches, &info);
936 arches != NULL;
937 arches = gdbarch_list_lookup_by_info (arches->next, &info))
938 {
939 /* We only have two flavors -- just make sure arch_size matches. */
940 if (gdbarch_ptr_bit (arches->gdbarch) == arch_size)
941 return (arches->gdbarch);
942 }
943
944 gdbarch = gdbarch_alloc (&info, NULL);
945
946 /* Basic register fields and methods, datatype sizes and stuff. */
947
948 /* There are 64 physical registers which can be referenced by
949 instructions (although only 56 of them can actually be
950 debugged) and 1 magic register (the PC). The other three
951 magic registers (ex1, syscall, orig_r0) which are known to
952 "ptrace" are ignored by "gdb". Note that we simply pretend
953 that there are 65 registers, and no "pseudo registers". */
954 set_gdbarch_num_regs (gdbarch, TILEGX_NUM_REGS);
955 set_gdbarch_num_pseudo_regs (gdbarch, 0);
956
957 set_gdbarch_sp_regnum (gdbarch, TILEGX_SP_REGNUM);
958 set_gdbarch_pc_regnum (gdbarch, TILEGX_PC_REGNUM);
959
960 set_gdbarch_register_name (gdbarch, tilegx_register_name);
961 set_gdbarch_register_type (gdbarch, tilegx_register_type);
962
963 set_gdbarch_char_signed (gdbarch, 0);
964 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
965 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
966 set_gdbarch_long_bit (gdbarch, arch_size);
967 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
968
969 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
970 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
971 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
972
973 set_gdbarch_ptr_bit (gdbarch, arch_size);
974 set_gdbarch_addr_bit (gdbarch, arch_size);
975
976 set_gdbarch_cannot_fetch_register (gdbarch,
977 tilegx_cannot_reference_register);
978 set_gdbarch_cannot_store_register (gdbarch,
979 tilegx_cannot_reference_register);
980
981 /* Stack grows down. */
982 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
983
984 /* Frame Info. */
985 set_gdbarch_unwind_sp (gdbarch, tilegx_unwind_sp);
986 set_gdbarch_unwind_pc (gdbarch, tilegx_unwind_pc);
987 set_gdbarch_dummy_id (gdbarch, tilegx_unwind_dummy_id);
988 set_gdbarch_frame_align (gdbarch, tilegx_frame_align);
989 frame_base_set_default (gdbarch, &tilegx_frame_base);
990
991 set_gdbarch_skip_prologue (gdbarch, tilegx_skip_prologue);
992
993 set_gdbarch_in_function_epilogue_p (gdbarch,
994 tilegx_in_function_epilogue_p);
995
996 /* Map debug registers into internal register numbers. */
997 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, tilegx_dwarf2_reg_to_regnum);
998
999 /* These values and methods are used when gdb calls a target function. */
1000 set_gdbarch_push_dummy_call (gdbarch, tilegx_push_dummy_call);
1001 set_gdbarch_breakpoint_from_pc (gdbarch, tilegx_breakpoint_from_pc);
1002 set_gdbarch_return_value (gdbarch, tilegx_return_value);
1003
1004 set_gdbarch_print_insn (gdbarch, print_insn_tilegx);
1005
1006 gdbarch_init_osabi (info, gdbarch);
1007
1008 dwarf2_append_unwinders (gdbarch);
1009 frame_unwind_append_unwinder (gdbarch, &tilegx_frame_unwind);
1010
1011 return gdbarch;
1012}
1013
1014/* Provide a prototype to silence -Wmissing-prototypes. */
1015extern initialize_file_ftype _initialize_tilegx_tdep;
1016
1017void
1018_initialize_tilegx_tdep (void)
1019{
1020 register_gdbarch_init (bfd_arch_tilegx, tilegx_gdbarch_init);
1021}
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