projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| bb368aad VM |
1 | # Machinemodel file for T4 systems |
| 2 | # | |
| fd67aa11 | 3 | # Copyright (C) 2021-2024 Free Software Foundation, Inc. |
| bb368aad VM |
4 | # |
| 5 | # This file is free software; you can redistribute it and/or modify | |
| 6 | # it under the terms of the GNU General Public License as published by | |
| 7 | # the Free Software Foundation; either version 3 of the License, or | |
| 8 | # (at your option) any later version. | |
| 9 | # | |
| 10 | # This program is distributed in the hope that it will be useful, | |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | # GNU General Public License for more details. | |
| 14 | # | |
| 15 | # You should have received a copy of the GNU General Public License | |
| 16 | # along with this program; see the file COPYING3. If not see | |
| 17 | # <http://www.gnu.org/licenses/>. | |
| 18 | ||
| 19 | indxobj_define T4_Chip (CPUID>>6) | |
| 20 | indxobj_define T4_Core (CPUID>>3) | |
| 21 | ||
| 22 | mobj_define Memory_page_size "(EA_PAGESIZE ? EA_PAGESIZE : -1)" | |
| 23 | mobj_define Memory_page "(((VADDR>255) && EA_PAGESIZE) ? VADDR & (~(EA_PAGESIZE-1)) : -1)" | |
| 24 | mobj_define Memory_64B_cacheline "((VADDR>255)?(VADDR>>6<<6):-1)" | |
| 25 | mobj_define Memory_32B_cacheline "((VADDR>255)?(VADDR>>5<<5):-1)" | |
| 26 | mobj_define Memory_address "((VADDR>255)?(VADDR):-1)" | |
| 27 | ||
| 28 | mobj_define Memory_in_home_lgrp (EA_LGRP==LWP_LGRP_HOME) | |
| 29 | mobj_define Memory_lgrp (EA_LGRP) | |
| 30 | ||
| 31 | mobj_define Physical_page "((PADDR && EA_PAGESIZE) ? PADDR & (~(EA_PAGESIZE-1)) : -1)" | |
| 32 | mobj_define Physical_64B_cacheline "(PADDR?(PADDR>>6<<6):-1)" | |
| 33 | mobj_define Physical_32B_cacheline "(PADDR?(PADDR>>5<<5):-1)" | |
| 34 | mobj_define Physical_address "(PADDR?(PADDR):-1)" | |
| 35 | ||
| 36 | ||
| 37 | #mobj_define Vpage_8K "((ea_pagesize==1<<13 && VADDR>255)?(VADDR>>13<<13):-1)" | |
| 38 | #mobj_define Vpage_64K "((ea_pagesize==1<<16 && VADDR>255)?(VADDR>>16<<16):-1)" | |
| 39 | #mobj_define Vpage_512K "((ea_pagesize==1<<19 && VADDR>255)?(VADDR>>19<<19):-1)" | |
| 40 | #mobj_define Vpage_4M "((ea_pagesize==1<<22 && VADDR>255)?(VADDR>>22<<22):-1)" | |
| 41 | #mobj_define Vpage_256M "((ea_pagesize==1<<28 && VADDR>255)?(VADDR>>28<<28):-1)" | |
| 42 | #mobj_define Vpage_2G "((ea_pagesize==1<<31 && VADDR>255)?(VADDR>>31<<31):-1)" | |
| 43 | ||
| 44 | #mobj_define Ppage_8K "((ea_pagesize==1<<13 && PADDR)?(PADDR>>13<<13):-1)" | |
| 45 | #mobj_define Ppage_64K "((ea_pagesize==1<<16 && PADDR)?(PADDR>>16<<16):-1)" | |
| 46 | #mobj_define Ppage_512K "((ea_pagesize==1<<19 && PADDR)?(PADDR>>19<<19):-1)" | |
| 47 | #mobj_define Ppage_4M "((ea_pagesize==1<<22 && PADDR)?(PADDR>>22<<22):-1)" | |
| 48 | #mobj_define Ppage_256M "((ea_pagesize==1<<28 && PADDR)?(PADDR>>28<<28):-1)" | |
| 49 | #mobj_define Ppage_2G "((ea_pagesize==1<<31 && PADDR)?(PADDR>>31<<31):-1)" | |
| 50 | ||
| 51 | # comment out *CacheTag definitions since we don't have use cases to justify their complexity | |
| 52 | # comment out other *Cache* definitions since we don't have use cases to justify their complexity | |
| 53 | # further, meminfo() tends not to give us physical addresses | |
| 54 | ||
| 55 | #mobj_define T4_L1ICacheSet "((PHYSPC>>5)&0x7F)" | |
| 56 | #mobj_define T4_L1ICacheTag "((PHYSPC>>12)&0x7FFFFFFFF)" | |
| 57 | #mobj_define T4_L1DCacheSet "(PADDR?((PADDR>>5)&0x7F):-1)" | |
| 58 | #mobj_define T4_L1DCacheTag "(PADDR?((PADDR>>12)&0x7FFFFFFFF):-1)" | |
| 59 | #mobj_define T4_L2ICacheSet "((((PHYSPC&0xFFFFFFF80FFF)|(((PHYSPC>>19)^(PHYSPC>>16)^(PHYSPC>>10)^(PHYSPC>>4)^(PHYSPC>>1)^PHYSPC)&0x7F000))>>5)&0x1FF)" | |
| 60 | #mobj_define T4_L2ICacheTag "((((PHYSPC&0xFFFFFFF80FFF)|(((PHYSPC>>19)^(PHYSPC>>16)^(PHYSPC>>10)^(PHYSPC>>4)^(PHYSPC>>1)^PHYSPC)&0x7F000))>>14)&0x1FFFFFFFF)" | |
| 61 | #mobj_define T4_L2DCacheSet "(PADDR?((((PADDR&0x800000000000)?PADDR:((PADDR&0xFFFFFFF80FFF)|(((PADDR>>19)^(PADDR>>16)^(PADDR>>10)^(PADDR>>4)^(PADDR>>1)^PADDR)&0x7F000)))>>5)&0x1FF):-1)" | |
| 62 | #mobj_define T4_L2DCacheTag "(PADDR?((((PADDR&0x800000000000)?PADDR:((PADDR&0xFFFFFFF80FFF)|(((PADDR>>19)^(PADDR>>16)^(PADDR>>10)^(PADDR>>4)^(PADDR>>1)^PADDR)&0x7F000)))>>14)&0x1FFFFFFFF):-1)" | |
| 63 | #mobj_define T4_L3DCacheSet "(PADDR?((((PADDR&0x800000000000)?((PADDR&0x800000000000)?PADDR:((PADDR&0xFFFFFFF80FFF)|(((PADDR>>19)^(PADDR>>16)^(PADDR>>10)^(PADDR>>4)^(PADDR>>1)^PADDR)&0x7F000))):((((PADDR&0x800000000000)?PADDR:((PADDR&0xFFFFFFF80FFF)|(((PADDR>>19)^(PADDR>>16)^(PADDR>>10)^(PADDR>>4)^(PADDR>>1)^PADDR)&0x7F000)))&0x7FFFFFFFFF3F)|(((((PADDR&0x800000000000)?PADDR:((PADDR&0xFFFFFFF80FFF)|(((PADDR>>19)^(PADDR>>16)^(PADDR>>10)^(PADDR>>4)^(PADDR>>1)^PADDR)&0x7F000)))>>6)^((PADDR&0x800000000000)?PADDR:((PADDR&0xFFFFFFF80FFF)|(((PADDR>>19)^(PADDR>>16)^(PADDR>>10)^(PADDR>>4)^(PADDR>>1)^PADDR)&0x7F000))))&0xC0)))>>6)&0xFFF):-1)" | |
| 64 | #mobj_define T4_L3DCacheTag "(PADDR?((((PADDR&0x800000000000)?((PADDR&0x800000000000)?PADDR:((PADDR&0xFFFFFFF80FFF)|(((PADDR>>19)^(PADDR>>16)^(PADDR>>10)^(PADDR>>4)^(PADDR>>1)^PADDR)&0x7F000))):((((PADDR&0x800000000000)?PADDR:((PADDR&0xFFFFFFF80FFF)|(((PADDR>>19)^(PADDR>>16)^(PADDR>>10)^(PADDR>>4)^(PADDR>>1)^PADDR)&0x7F000)))&0x7FFFFFFFFF3F)|(((((PADDR&0x800000000000)?PADDR:((PADDR&0xFFFFFFF80FFF)|(((PADDR>>19)^(PADDR>>16)^(PADDR>>10)^(PADDR>>4)^(PADDR>>1)^PADDR)&0x7F000)))>>6)^((PADDR&0x800000000000)?PADDR:((PADDR&0xFFFFFFF80FFF)|(((PADDR>>19)^(PADDR>>16)^(PADDR>>10)^(PADDR>>4)^(PADDR>>1)^PADDR)&0x7F000))))&0xC0)))>>18)&0x1FFFFFFF):-1)" | |
| 65 | #mobj_define T4_L3DBank "(PADDR?((((PADDR&0x800000000000)?((PADDR&0x800000000000)?PADDR:((PADDR&0xFFFFFFF80FFF)|(((PADDR>>19)^(PADDR>>16)^(PADDR>>10)^(PADDR>>4)^(PADDR>>1)^PADDR)&0x7F000))):((((PADDR&0x800000000000)?PADDR:((PADDR&0xFFFFFFF80FFF)|(((PADDR>>19)^(PADDR>>16)^(PADDR>>10)^(PADDR>>4)^(PADDR>>1)^PADDR)&0x7F000)))&0x7FFFFFFFFF3F)|(((((PADDR&0x800000000000)?PADDR:((PADDR&0xFFFFFFF80FFF)|(((PADDR>>19)^(PADDR>>16)^(PADDR>>10)^(PADDR>>4)^(PADDR>>1)^PADDR)&0x7F000)))>>6)^((PADDR&0x800000000000)?PADDR:((PADDR&0xFFFFFFF80FFF)|(((PADDR>>19)^(PADDR>>16)^(PADDR>>10)^(PADDR>>4)^(PADDR>>1)^PADDR)&0x7F000))))&0xC0)))>>6)&0x7):-1)" | |
| 66 | #mobj_define T4_2_Socket "(PADDR?((PADDR>>33)&0x1):-1)" | |
| 67 | #mobj_define T4_4_Socket "(PADDR?((PADDR>>33)&0x3):-1)" |