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arc: Put DBNZ instruction to a separate class
[thirdparty/binutils-gdb.git] / include / opcode / arc.h
CommitLineData
252b5132 1/* Opcode table for the ARC.
fd67aa11 2 Copyright (C) 1994-2024 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
252b5132 5
0d2bcfaf
NC		 6 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
7 the GNU Binutils.
252b5132 8
0d2bcfaf
NC		 9 GAS/GDB is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
e4e42b45 11 the Free Software Foundation; either version 3, or (at your option)
0d2bcfaf 12 any later version.
252b5132 13
0d2bcfaf
NC		 14 GAS/GDB is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
886a2506 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0d2bcfaf
NC		 17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
e4e42b45 20 along with GAS or GDB; see the file COPYING3. If not, write to
e172dbf8
NC		 21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132 23
886a2506
NC		 24#ifndef OPCODE_ARC_H
25#define OPCODE_ARC_H
26
6b477896
TS		 27#ifdef __cplusplus
28extern "C" {
29#endif
30
4670103e 31#ifndef MAX_INSN_ARGS
4eb6f892 32#define MAX_INSN_ARGS 16
4670103e
CZ		 33#endif
34
35#ifndef MAX_INSN_FLGS
575dcd27 36#define MAX_INSN_FLGS 4
4670103e 37#endif
886a2506
NC		 38
39/* Instruction Class. */
40typedef enum
db18dbab
GM		 41{
42 ACL,
43 ARITH,
44 AUXREG,
6ec7c1ae
CZ		 45 BBIT0,
46 BBIT1,
47 BI,
48 BIH,
db18dbab 49 BITOP,
2b848ebd 50 BITSTREAM,
db18dbab
GM		 51 BMU,
52 BRANCH,
6ec7c1ae 53 BRCC,
db18dbab 54 CONTROL,
c0852af0 55 DBNZ,
abe7c33b 56 DIVREM,
645d3342 57 DMA,
db18dbab
GM		 58 DPI,
59 DSP,
6ec7c1ae
CZ		 60 EI,
61 ENTER,
db18dbab
GM		 62 FLOAT,
63 INVALID,
6ec7c1ae 64 JLI,
db18dbab
GM		 65 JUMP,
66 KERNEL,
6ec7c1ae 67 LEAVE,
bb82aefe 68 LLOCK,
abe7c33b 69 LOAD,
db18dbab 70 LOGICAL,
6ec7c1ae 71 LOOP,
db18dbab 72 MEMORY,
c0c31e91 73 MISC,
abe7c33b
CZ		 74 MOVE,
75 MPY,
db18dbab 76 NET,
5a736821 77 PROTOCOL_DECODE,
2b848ebd 78 PMU,
6ec7c1ae
CZ		 79 POP,
80 PUSH,
bb82aefe 81 SCOND,
7179e0e6 82 SJLI,
abe7c33b 83 STORE,
6ec7c1ae 84 SUB,
7e126ba3 85 SWITCH,
c0c31e91 86 ULTRAIP,
2b848ebd 87 XY
db18dbab 88} insn_class_t;
886a2506
NC		 89
90/* Instruction Subclass. */
91typedef enum
db18dbab 92{
53a346d8
CZ		 93 NONE = 0,
94 CVT = (1U << 1),
95 BTSCN = (1U << 2),
96 CD = (1U << 3),
97 CD1 = CD,
98 CD2 = CD,
99 COND = (1U << 4),
100 DIV = (1U << 5),
101 DP = (1U << 6),
102 DPA = (1U << 7),
103 DPX = (1U << 8),
cd18a823 104 FASTMATH = (1U << 23),
53a346d8
CZ		 105 LL64 = (1U << 9),
106 MPY1E = (1U << 10),
107 MPY6E = (1U << 11),
108 MPY7E = (1U << 12),
109 MPY8E = (1U << 13),
110 MPY9E = (1U << 14),
111 NPS400 = (1U << 15),
112 QUARKSE1 = (1U << 16),
113 QUARKSE2 = (1U << 17),
114 SHFT1 = (1U << 18),
115 SHFT2 = (1U << 19),
116 SWAP = (1U << 20),
117 SP = (1U << 21),
118 SPX = (1U << 22)
db18dbab 119} insn_subclass_t;
886a2506
NC		 120
121/* Flags class. */
122typedef enum
db18dbab
GM		 123{
124 F_CLASS_NONE = 0,
1ae8ab47 125
db18dbab
GM		 126 /* At most one flag from the set of flags can appear in the
127 instruction. */
128 F_CLASS_OPTIONAL = (1 << 0),
1ae8ab47 129
db18dbab
GM		 130 /* Exactly one from from the set of flags must appear in the
131 instruction. */
132 F_CLASS_REQUIRED = (1 << 1),
f36e33da 133
db18dbab
GM		 134 /* The conditional code can be extended over the standard variants
135 via .extCondCode pseudo-op. */
136 F_CLASS_EXTEND = (1 << 2),
d9eca1df 137
db18dbab 138 /* Condition code flag. */
6ec7c1ae
CZ		 139 F_CLASS_COND = (1 << 3),
140
141 /* Write back mode. */
142 F_CLASS_WB = (1 << 4),
143
144 /* Data size. */
145 F_CLASS_ZZ = (1 << 5),
146
147 /* Implicit flag. */
148 F_CLASS_IMPLICIT = (1 << 6)
db18dbab 149} flag_class_t;
886a2506
NC		 150
151/* The opcode table is an array of struct arc_opcode. */
152struct arc_opcode
153{
154 /* The opcode name. */
c0c31e91 155 const char * name;
886a2506
NC		 156
157 /* The opcode itself. Those bits which will be filled in with
158 operands are zeroes. */
bdfe53e3 159 unsigned long long opcode;
886a2506
NC		 160
161 /* The opcode mask. This is used by the disassembler. This is a
162 mask containing ones indicating those bits which must match the
163 opcode field, and zeroes indicating those bits which need not
164 match (and are presumably filled in by operands). */
bdfe53e3 165 unsigned long long mask;
886a2506
NC		 166
167 /* One bit flags for the opcode. These are primarily used to
168 indicate specific processors and environments support the
169 instructions. The defined values are listed below. */
170 unsigned cpu;
171
172 /* The instruction class. This is used by gdb. */
c810e0b8 173 insn_class_t insn_class;
886a2506
NC		 174
175 /* The instruction subclass. */
176 insn_subclass_t subclass;
177
178 /* An array of operand codes. Each code is an index into the
179 operand table. They appear in the order which the operands must
180 appear in assembly code, and are terminated by a zero. */
181 unsigned char operands[MAX_INSN_ARGS + 1];
182
183 /* An array of flag codes. Each code is an index into the flag
184 table. They appear in the order which the flags must appear in
185 assembly code, and are terminated by a zero. */
186 unsigned char flags[MAX_INSN_FLGS + 1];
187};
252b5132 188
886a2506
NC		 189/* The table itself is sorted by major opcode number, and is otherwise
190 in the order in which the disassembler should consider
191 instructions. */
192extern const struct arc_opcode arc_opcodes[];
886a2506 193
06fe285f
GM		 194/* Return length of an instruction represented by OPCODE, in bytes. */
195extern int arc_opcode_len (const struct arc_opcode *opcode);
196
886a2506 197/* CPU Availability. */
f36e33da 198#define ARC_OPCODE_NONE 0x0000
886a2506
NC		 199#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
200#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
201#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
202#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
203
f36e33da
CZ		 204/* CPU combi. */
205#define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
8784b6df 206 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
f36e33da 207#define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
b6523c37 208#define ARC_OPCODE_ARCV1 (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700)
e5b06ef0 209#define ARC_OPCODE_ARCV2 (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
53a346d8 210#define ARC_OPCODE_ARCMPY6E (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCV2)
886a2506 211
886a2506
NC		 212/* The operands table is an array of struct arc_operand. */
213struct arc_operand
214{
215 /* The number of bits in the operand. */
216 unsigned int bits;
217
218 /* How far the operand is left shifted in the instruction. */
219 unsigned int shift;
220
221 /* The default relocation type for this operand. */
222 signed int default_reloc;
223
224 /* One bit syntax flags. */
225 unsigned int flags;
226
227 /* Insertion function. This is used by the assembler. To insert an
228 operand value into an instruction, check this field.
229
230 If it is NULL, execute
231 i |= (op & ((1 << o->bits) - 1)) << o->shift;
232 (i is the instruction which we are filling in, o is a pointer to
233 this structure, and op is the opcode value; this assumes twos
234 complement arithmetic).
235
236 If this field is not NULL, then simply call it with the
237 instruction and the operand value. It will return the new value
238 of the instruction. If the ERRMSG argument is not NULL, then if
239 the operand value is illegal, *ERRMSG will be set to a warning
240 string (the operand will be inserted in any case). If the
241 operand value is legal, *ERRMSG will be unchanged (most operands
242 can accept any value). */
bdfe53e3
AB		 243 unsigned long long (*insert) (unsigned long long instruction,
244 long long int op,
245 const char **errmsg);
886a2506
NC		 246
247 /* Extraction function. This is used by the disassembler. To
248 extract this operand type from an instruction, check this field.
249
250 If it is NULL, compute
251 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
252 if ((o->flags & ARC_OPERAND_SIGNED) != 0
253 && (op & (1 << (o->bits - 1))) != 0)
254 op -= 1 << o->bits;
255 (i is the instruction, o is a pointer to this structure, and op
256 is the result; this assumes twos complement arithmetic).
257
258 If this field is not NULL, then simply call it with the
259 instruction value. It will return the value of the operand. If
260 the INVALID argument is not NULL, *INVALID will be set to
261 TRUE if this operand type can not actually be extracted from
262 this operand (i.e., the instruction does not match). If the
263 operand is valid, *INVALID will not be changed. */
9193bc42 264 long long int (*extract) (unsigned long long instruction, bool *invalid);
886a2506 265};
0d2bcfaf 266
886a2506
NC		 267/* Elements in the table are retrieved by indexing with values from
268 the operands field of the arc_opcodes table. */
269extern const struct arc_operand arc_operands[];
270extern const unsigned arc_num_operands;
271extern const unsigned arc_Toperand;
272extern const unsigned arc_NToperand;
252b5132 273
886a2506 274/* Values defined for the flags field of a struct arc_operand. */
0d2bcfaf 275
886a2506
NC		 276/* This operand does not actually exist in the assembler input. This
277 is used to support extended mnemonics, for which two operands fields
278 are identical. The assembler should call the insert function with
279 any op value. The disassembler should call the extract function,
280 ignore the return value, and check the value placed in the invalid
281 argument. */
282#define ARC_OPERAND_FAKE 0x0001
252b5132 283
886a2506
NC		 284/* This operand names an integer register. */
285#define ARC_OPERAND_IR 0x0002
0d2bcfaf 286
886a2506
NC		 287/* This operand takes signed values. */
288#define ARC_OPERAND_SIGNED 0x0004
252b5132 289
886a2506
NC		 290/* This operand takes unsigned values. This exists primarily so that
291 a flags value of 0 can be treated as end-of-arguments. */
292#define ARC_OPERAND_UNSIGNED 0x0008
252b5132 293
886a2506
NC		 294/* This operand takes long immediate values. */
295#define ARC_OPERAND_LIMM 0x0010
252b5132 296
886a2506
NC		 297/* This operand is identical like the previous one. */
298#define ARC_OPERAND_DUPLICATE 0x0020
0d2bcfaf 299
886a2506
NC		 300/* This operand is PC relative. Used for internal relocs. */
301#define ARC_OPERAND_PCREL 0x0040
0d2bcfaf 302
886a2506
NC		 303/* This operand is truncated. The truncation is done accordingly to
304 operand alignment attribute. */
305#define ARC_OPERAND_TRUNCATE 0x0080
0d2bcfaf 306
886a2506
NC		 307/* This operand is 16bit aligned. */
308#define ARC_OPERAND_ALIGNED16 0x0100
0d2bcfaf 309
886a2506
NC		 310/* This operand is 32bit aligned. */
311#define ARC_OPERAND_ALIGNED32 0x0200
0d2bcfaf 312
886a2506
NC		 313/* This operand can be ignored by matching process if it is not
314 present. */
315#define ARC_OPERAND_IGNORE 0x0400
0d2bcfaf 316
886a2506
NC		 317/* Don't check the range when matching. */
318#define ARC_OPERAND_NCHK 0x0800
0d2bcfaf 319
886a2506
NC		 320/* Mark the braket possition. */
321#define ARC_OPERAND_BRAKET 0x1000
252b5132 322
db18dbab
GM		 323/* Address type operand for NPS400. */
324#define ARC_OPERAND_ADDRTYPE 0x2000
325
326/* Mark the colon position. */
327#define ARC_OPERAND_COLON 0x4000
328
886a2506 329/* Mask for selecting the type for typecheck purposes. */
db18dbab
GM		 330#define ARC_OPERAND_TYPECHECK_MASK \
331 (ARC_OPERAND_IR \
332 | ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED \
333 | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET \
334 | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON)
335
336/* Macro to determine if an operand is a fake operand. */
337#define ARC_OPERAND_IS_FAKE(op) \
338 ((operand->flags & ARC_OPERAND_FAKE) \
339 && !((operand->flags & ARC_OPERAND_BRAKET) \
340 || (operand->flags & ARC_OPERAND_COLON)))
252b5132 341
886a2506
NC		 342/* The flags structure. */
343struct arc_flag_operand
344{
345 /* The flag name. */
c0c31e91 346 const char * name;
0d2bcfaf 347
886a2506
NC		 348 /* The flag code. */
349 unsigned code;
252b5132 350
886a2506
NC		 351 /* The number of bits in the operand. */
352 unsigned int bits;
252b5132 353
886a2506
NC		 354 /* How far the operand is left shifted in the instruction. */
355 unsigned int shift;
252b5132 356
886a2506
NC		 357 /* Available for disassembler. */
358 unsigned char favail;
84037f8c
KD		 359};
360
886a2506
NC		 361/* The flag operands table. */
362extern const struct arc_flag_operand arc_flag_operands[];
363extern const unsigned arc_num_flag_operands;
0d2bcfaf 364
886a2506
NC		 365/* The flag's class structure. */
366struct arc_flag_class
367{
368 /* Flag class. */
c810e0b8 369 flag_class_t flag_class;
252b5132 370
886a2506
NC		 371 /* List of valid flags (codes). */
372 unsigned flags[256];
373};
252b5132 374
886a2506 375extern const struct arc_flag_class arc_flag_classes[];
252b5132 376
886a2506
NC		 377/* Structure for special cases. */
378struct arc_flag_special
379{
380 /* Name of special case instruction. */
381 const char *name;
252b5132 382
886a2506
NC		 383 /* List of flags applicable for special case instruction. */
384 unsigned flags[32];
385};
252b5132 386
886a2506
NC		 387extern const struct arc_flag_special arc_flag_special_cases[];
388extern const unsigned arc_num_flag_special;
389
390/* Relocation equivalence structure. */
391struct arc_reloc_equiv_tab
392{
393 const char * name; /* String to lookup. */
394 const char * mnemonic; /* Extra matching condition. */
24b368f8 395 unsigned flags[32]; /* Extra matching condition. */
886a2506
NC		 396 signed int oldreloc; /* Old relocation. */
397 signed int newreloc; /* New relocation. */
398};
252b5132 399
886a2506
NC		 400extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
401extern const unsigned arc_num_equiv_tab;
252b5132 402
886a2506
NC		 403/* Structure for operand operations for pseudo/alias instructions. */
404struct arc_operand_operation
405{
406 /* The index for operand from operand array. */
407 unsigned operand_idx;
252b5132 408
886a2506
NC		 409 /* Defines if it needs the operand inserted by the assembler or
410 whether this operand comes from the pseudo instruction's
411 operands. */
412 unsigned char needs_insert;
252b5132 413
886a2506
NC		 414 /* Count we have to add to the operand. Use negative number to
415 subtract from the operand. Also use this number to add to 0 if
416 the operand needs to be inserted (i.e. needs_insert == 1). */
417 int count;
252b5132 418
886a2506
NC		 419 /* Index of the operand to swap with. To be done AFTER applying
420 inc_count. */
421 unsigned swap_operand_idx;
252b5132
RH		 422};
423
886a2506
NC		 424/* Structure for pseudo/alias instructions. */
425struct arc_pseudo_insn
426{
427 /* Mnemonic for pseudo/alias insn. */
c0c31e91 428 const char * mnemonic_p;
252b5132 429
886a2506 430 /* Mnemonic for real instruction. */
c0c31e91 431 const char * mnemonic_r;
252b5132 432
886a2506 433 /* Flag that will have to be added (if any). */
c0c31e91 434 const char * flag_r;
252b5132 435
886a2506
NC		 436 /* Amount of operands. */
437 unsigned operand_cnt;
252b5132 438
886a2506
NC		 439 /* Array of operand operations. */
440 struct arc_operand_operation operand[6];
441};
252b5132 442
886a2506
NC		 443extern const struct arc_pseudo_insn arc_pseudo_insns[];
444extern const unsigned arc_num_pseudo_insn;
252b5132 445
886a2506
NC		 446/* Structure for AUXILIARY registers. */
447struct arc_aux_reg
448{
449 /* Register address. */
450 int address;
252b5132 451
f36e33da
CZ		 452 /* One bit flags for the opcode. These are primarily used to
453 indicate specific processors and environments support the
454 instructions. */
455 unsigned cpu;
456
8ddf6b2a
CZ		 457 /* AUX register subclass. */
458 insn_subclass_t subclass;
459
460 /* Register name. */
c0c31e91 461 const char * name;
886a2506
NC		 462
463 /* Size of the string. */
464 size_t length;
465};
466
467extern const struct arc_aux_reg arc_aux_regs[];
468extern const unsigned arc_num_aux_regs;
469
4670103e
CZ		 470extern const struct arc_opcode arc_relax_opcodes[];
471extern const unsigned arc_num_relax_opcodes;
472
4b0c052e
AB		 473/* Macro used for generating one class of NPS instructions. */
474#define NPS_CMEM_HIGH_VALUE 0x57f0
475
f2dd8838
CZ		 476/* Macros to help generating regular pattern instructions. */
477#define FIELDA(word) (word & 0x3F)
478#define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
479#define FIELDC(word) ((word & 0x3F) << 6)
480#define FIELDF (0x01 << 15)
481#define FIELDQ (0x1F)
482
8784b6df 483#define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
f2dd8838
CZ		 484#define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
485#define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
486
487#define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP))
488#define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62))
489#define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62))
490#define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
491#define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62))
492#define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
493#define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
494#define INSN3OP_0LL(MOP,SOP) \
495 (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
496#define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22))
497#define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
498#define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
499#define INSN3OP_0LU(MOP,SOP) \
500 (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
501#define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22))
502#define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
503#define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
504#define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
505#define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
506#define INSN3OP_C0LL(MOP,SOP) \
507 (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
508#define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
509#define INSN3OP_C0LU(MOP,SOP) \
510 (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
511
2e272202
GM		 512#define MASK_32BIT(VAL) (0xffffffff & (VAL))
513
514#define MINSN3OP_ABC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
515#define MINSN3OP_ALC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
516#define MINSN3OP_ABL (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63))))
517#define MINSN3OP_ALL (MASK_32BIT (~(FIELDF | FIELDA (63))))
518#define MINSN3OP_0BC (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
519#define MINSN3OP_0LC (MASK_32BIT (~(FIELDF | FIELDC (63))))
520#define MINSN3OP_0BL (MASK_32BIT (~(FIELDF | FIELDB (63))))
521#define MINSN3OP_0LL (MASK_32BIT (~(FIELDF)))
522#define MINSN3OP_ABU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
523#define MINSN3OP_ALU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
524#define MINSN3OP_0BU (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
525#define MINSN3OP_0LU (MASK_32BIT (~(FIELDF | FIELDC (63))))
526#define MINSN3OP_BBS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
527#define MINSN3OP_0LS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
528#define MINSN3OP_CBBC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
529#define MINSN3OP_CBBL (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63))))
530#define MINSN3OP_C0LC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
531#define MINSN3OP_C0LL (MASK_32BIT (~(FIELDF | FIELDQ)))
532#define MINSN3OP_CBBU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
533#define MINSN3OP_C0LU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
f2dd8838
CZ		 534
535#define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
536#define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
537#define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
538#define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
539#define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
540#define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
541
2e272202
GM		 542#define MINSN2OP_BC (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
543#define MINSN2OP_BL (MASK_32BIT ((~(FIELDF | FIELDB (63)))))
544#define MINSN2OP_0C (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
545#define MINSN2OP_0L (MASK_32BIT ((~(FIELDF))))
546#define MINSN2OP_BU (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
547#define MINSN2OP_0U (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
f2dd8838 548
b99747ae
CZ		 549/* Various constants used when defining an extension instruction. */
550#define ARC_SYNTAX_3OP (1 << 0)
551#define ARC_SYNTAX_2OP (1 << 1)
945e0f82
CZ		 552#define ARC_SYNTAX_1OP (1 << 2)
553#define ARC_SYNTAX_NOP (1 << 3)
554#define ARC_SYNTAX_MASK (0x0F)
555
556#define ARC_OP1_MUST_BE_IMM (1 << 0)
557#define ARC_OP1_IMM_IMPLIED (1 << 1)
b99747ae
CZ		 558
559#define ARC_SUFFIX_NONE (1 << 0)
560#define ARC_SUFFIX_COND (1 << 1)
561#define ARC_SUFFIX_FLAG (1 << 2)
562
f36e33da
CZ		 563#define ARC_REGISTER_READONLY (1 << 0)
564#define ARC_REGISTER_WRITEONLY (1 << 1)
565#define ARC_REGISTER_NOSHORT_CUT (1 << 2)
b99747ae
CZ		 566
567/* Constants needed to initialize extension instructions. */
568extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
569extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
570extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
571extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
572
573extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
574extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
575extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
576extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
577extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
578extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
579extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
580extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
581extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
582extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
583extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
584extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
585
586extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
587extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
588extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
589
590extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
591extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
592extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
593
594extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
595extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
596extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
597extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
598extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
599extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
600
601extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
602extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
603extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
604extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
605
945e0f82
CZ		 606extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
607extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
608extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
609
db18dbab
GM		 610/* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP
611 Instruction Set Reference Manual v2.4 for a description of address types. */
612
613typedef enum
614{
615 /* Addresses in memory. */
616
617 /* Buffer descriptor. */
618 ARC_NPS400_ADDRTYPE_BD,
619
620 /* Job identifier. */
621 ARC_NPS400_ADDRTYPE_JID,
622
623 /* Linked Buffer Descriptor. */
624 ARC_NPS400_ADDRTYPE_LBD,
625
626 /* Multicast Buffer Descriptor. */
627 ARC_NPS400_ADDRTYPE_MBD,
628
629 /* Summarized Address. */
630 ARC_NPS400_ADDRTYPE_SD,
631
632 /* SMEM Security Context Local Memory. */
633 ARC_NPS400_ADDRTYPE_SM,
634
635 /* Extended Address. */
636 ARC_NPS400_ADDRTYPE_XA,
637
638 /* Extended Summarized Address. */
639 ARC_NPS400_ADDRTYPE_XD,
640
641 /* CMEM offset addresses. */
642
643 /* On-demand Counter Descriptor. */
644 ARC_NPS400_ADDRTYPE_CD,
645
646 /* CMEM Buffer Descriptor. */
647 ARC_NPS400_ADDRTYPE_CBD,
648
649 /* CMEM Job Identifier. */
650 ARC_NPS400_ADDRTYPE_CJID,
651
652 /* CMEM Linked Buffer Descriptor. */
653 ARC_NPS400_ADDRTYPE_CLBD,
654
655 /* CMEM Offset. */
656 ARC_NPS400_ADDRTYPE_CM,
657
658 /* CMEM Summarized Address. */
659 ARC_NPS400_ADDRTYPE_CSD,
660
661 /* CMEM Extended Address. */
662 ARC_NPS400_ADDRTYPE_CXA,
663
664 /* CMEM Extended Summarized Address. */
665 ARC_NPS400_ADDRTYPE_CXD
666
667} arc_nps_address_type;
668
669#define ARC_NUM_ADDRTYPES 16
670
6b477896
TS		 671#ifdef __cplusplus
672}
673#endif
674
886a2506 675#endif /* OPCODE_ARC_H */
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