projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| b781e558 | 1 | /* ARM assembler/disassembler support. |
| b3adc24a | 2 | Copyright (C) 2004-2020 Free Software Foundation, Inc. |
| b781e558 RE |
3 | |
| 4 | This file is part of GDB and GAS. | |
| 5 | ||
| 6 | GDB and GAS are free software; you can redistribute it and/or | |
| 7 | modify it under the terms of the GNU General Public License as | |
| e4e42b45 | 8 | published by the Free Software Foundation; either version 3, or (at |
| b781e558 RE |
9 | your option) any later version. |
| 10 | ||
| 11 | GDB and GAS are distributed in the hope that it will be useful, but | |
| 12 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 14 | General Public License for more details. | |
| 15 | ||
| 16 | You should have received a copy of the GNU General Public License | |
| e4e42b45 NC |
17 | along with GDB or GAS; see the file COPYING3. If not, write to the |
| 18 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
| 19 | MA 02110-1301, USA. */ | |
| b781e558 RE |
20 | |
| 21 | /* The following bitmasks control CPU extensions: */ | |
| 497d849d TP |
22 | #define ARM_EXT_V1 0x00000001 /* All processors (core set). */ |
| 23 | #define ARM_EXT_V2 0x00000002 /* Multiply instructions. */ | |
| 24 | #define ARM_EXT_V2S 0x00000004 /* SWP instructions. */ | |
| 25 | #define ARM_EXT_V3 0x00000008 /* MSR MRS. */ | |
| 26 | #define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */ | |
| 27 | #define ARM_EXT_V4 0x00000020 /* Allow half word loads. */ | |
| 28 | #define ARM_EXT_V4T 0x00000040 /* Thumb. */ | |
| 29 | #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ | |
| 30 | #define ARM_EXT_V5T 0x00000100 /* Improved interworking. */ | |
| 31 | #define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */ | |
| 32 | #define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */ | |
| 33 | #define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */ | |
| 34 | #define ARM_EXT_V6 0x00001000 /* ARM V6. */ | |
| 35 | #define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ | |
| 36 | #define ARM_EXT_V8 0x00004000 /* ARMv8 w/o atomics. */ | |
| 37 | #define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */ | |
| 38 | #define ARM_EXT_DIV 0x00010000 /* Integer division. */ | |
| 62b3e311 PB |
39 | /* The 'M' in Arm V7M stands for Microcontroller. |
| 40 | On earlier architecture variants it stands for Multiply. */ | |
| 497d849d TP |
41 | #define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */ |
| 42 | #define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */ | |
| 43 | #define ARM_EXT_V7 0x00080000 /* Arm V7. */ | |
| 44 | #define ARM_EXT_V7A 0x00100000 /* Arm V7A. */ | |
| 45 | #define ARM_EXT_V7R 0x00200000 /* Arm V7R. */ | |
| 46 | #define ARM_EXT_V7M 0x00400000 /* Arm V7M. */ | |
| 47 | #define ARM_EXT_V6M 0x00800000 /* ARM V6M. */ | |
| 48 | #define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */ | |
| 49 | #define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */ | |
| 50 | #define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related), | |
| 51 | not in v7-M. */ | |
| 52 | #define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */ | |
| 53 | #define ARM_EXT_SEC 0x10000000 /* Security extensions. */ | |
| 54 | #define ARM_EXT_OS 0x20000000 /* OS Extensions. */ | |
| 55 | #define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM | |
| 56 | state. */ | |
| 57 | #define ARM_EXT_VIRT 0x80000000 /* Virtualization extensions. */ | |
| b781e558 | 58 | |
| 497d849d TP |
59 | #define ARM_EXT2_PAN 0x00000001 /* PAN extension. */ |
| 60 | #define ARM_EXT2_V8_2A 0x00000002 /* ARM V8.2A. */ | |
| 61 | #define ARM_EXT2_V8M 0x00000004 /* ARM V8M. */ | |
| 62 | #define ARM_EXT2_ATOMICS 0x00000008 /* ARMv8 atomics. */ | |
| 63 | #define ARM_EXT2_V6T2_V8M 0x00000010 /* V8M Baseline from V6T2. */ | |
| 64 | #define ARM_EXT2_FP16_INST 0x00000020 /* ARM V8.2A FP16 instructions. */ | |
| 65 | #define ARM_EXT2_V8M_MAIN 0x00000040 /* ARMv8-M Mainline. */ | |
| 66 | #define ARM_EXT2_RAS 0x00000080 /* RAS extension. */ | |
| 67 | #define ARM_EXT2_V8_3A 0x00000100 /* ARM V8.3A. */ | |
| 68 | #define ARM_EXT2_V8A 0x00000200 /* ARMv8-A. */ | |
| 69 | #define ARM_EXT2_V8_4A 0x00000400 /* ARM V8.4A. */ | |
| 70 | #define ARM_EXT2_FP16_FML 0x00000800 /* ARM V8.2A FP16-FML | |
| 71 | instructions. */ | |
| 72 | #define ARM_EXT2_V8_5A 0x00001000 /* ARM V8.5A. */ | |
| 73 | #define ARM_EXT2_SB 0x00002000 /* Speculation Barrier instruction. */ | |
| 74 | #define ARM_EXT2_PREDRES 0x00004000 /* Prediction Restriction insns. */ | |
| 031254f2 | 75 | #define ARM_EXT2_V8_1M_MAIN 0x00008000 /* ARMv8.1-M Mainline. */ |
| aab2c27d MM |
76 | #define ARM_EXT2_V8_6A 0x00010000 /* ARM V8.6A. */ |
| 77 | #define ARM_EXT2_BF16 0x00020000 /* ARMv8 bfloat16. */ | |
| 616ce08e | 78 | #define ARM_EXT2_I8MM 0x00040000 /* ARMv8.6A i8mm. */ |
| 8b301fbb | 79 | #define ARM_EXT2_CRC 0x00080000 /* ARMv8 CRC32 */ |
| ddfded2f | 80 | |
| b781e558 | 81 | /* Co-processor space extensions. */ |
| 497d849d TP |
82 | #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ |
| 83 | #define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */ | |
| 84 | #define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology | |
| 85 | coprocessor. */ | |
| 86 | #define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology | |
| 87 | coprocessor version 2. */ | |
| e74cfd16 | 88 | |
| 497d849d TP |
89 | #define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */ |
| 90 | #define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */ | |
| 91 | #define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */ | |
| 92 | #define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */ | |
| 93 | #define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */ | |
| 94 | #define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */ | |
| 95 | #define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */ | |
| 96 | #define FPU_VFP_EXT_V3xD 0x01000000 /* VFPv3 single-precision. */ | |
| 97 | #define FPU_VFP_EXT_V3 0x00800000 /* VFPv3 double-precision. */ | |
| 98 | #define FPU_NEON_EXT_V1 0x00400000 /* Neon (SIMD) insns. */ | |
| 99 | #define FPU_VFP_EXT_D32 0x00200000 /* Registers D16-D31. */ | |
| 100 | #define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */ | |
| 101 | #define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add. */ | |
| 102 | #define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add. */ | |
| 103 | #define FPU_VFP_EXT_ARMV8 0x00020000 /* Double-precision FP for ARMv8. */ | |
| 104 | #define FPU_NEON_EXT_ARMV8 0x00010000 /* Neon for ARMv8. */ | |
| 105 | #define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */ | |
| 8b301fbb | 106 | /* Unused 0x00004000 */ |
| 497d849d TP |
107 | #define FPU_VFP_EXT_ARMV8xD 0x00002000 /* Single-precision FP for ARMv8. */ |
| 108 | #define FPU_NEON_EXT_RDMA 0x00001000 /* v8.1 Adv.SIMD extensions. */ | |
| 109 | #define FPU_NEON_EXT_DOTPROD 0x00000800 /* Dot Product extension. */ | |
| a7ad558c AV |
110 | #define FPU_MVE 0x00000400 /* MVE Integer extension. */ |
| 111 | #define FPU_MVE_FP 0x00000200 /* MVE Floating Point extension. */ | |
| b781e558 RE |
112 | |
| 113 | /* Architectures are the sum of the base and extensions. The ARM ARM (rev E) | |
| 114 | defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, | |
| 115 | ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add | |
| 116 | three more to cover cores prior to ARM6. Finally, there are cores which | |
| 117 | implement further extensions in the co-processor space. */ | |
| 497d849d TP |
118 | #define ARM_AEXT_V1 ARM_EXT_V1 |
| 119 | #define ARM_AEXT_V2 (ARM_AEXT_V1 | ARM_EXT_V2) | |
| 120 | #define ARM_AEXT_V2S (ARM_AEXT_V2 | ARM_EXT_V2S) | |
| 121 | #define ARM_AEXT_V3 (ARM_AEXT_V2S | ARM_EXT_V3) | |
| 122 | #define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M) | |
| 123 | #define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4) | |
| 124 | #define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4) | |
| 125 | #define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T | ARM_EXT_OS) | |
| 126 | #define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T | ARM_EXT_OS) | |
| 127 | #define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5) | |
| 128 | #define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5) | |
| 129 | #define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T \ | |
| 130 | | ARM_EXT_OS) | |
| 131 | #define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T \ | |
| 132 | | ARM_EXT_OS) | |
| 133 | #define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP) | |
| 134 | #define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E) | |
| 135 | #define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J) | |
| 136 | #define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6) | |
| 137 | #define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K) | |
| 138 | #define ARM_AEXT_V6Z (ARM_AEXT_V6K | ARM_EXT_SEC) | |
| 139 | #define ARM_AEXT_V6KZ (ARM_AEXT_V6K | ARM_EXT_SEC) | |
| 140 | #define ARM_AEXT_V6T2 (ARM_AEXT_V6 | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM \ | |
| 141 | | ARM_EXT_THUMB_MSR \ | |
| 142 | | ARM_EXT_V6_DSP ) | |
| 143 | #define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K) | |
| 144 | #define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC) | |
| 145 | #define ARM_AEXT_V6KZT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC) | |
| 146 | #define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER) | |
| 147 | #define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A) | |
| 148 | #define ARM_AEXT_V7VE (ARM_AEXT_V7A | ARM_EXT_DIV | ARM_EXT_ADIV \ | |
| 149 | | ARM_EXT_VIRT | ARM_EXT_SEC \ | |
| 150 | | ARM_EXT_MP) | |
| 151 | #define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV) | |
| 152 | #define ARM_AEXT_NOTM (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J \ | |
| 153 | | ARM_EXT_V6_DSP \ | |
| 154 | | ARM_EXT_V6_NOTM) | |
| 155 | #define ARM_AEXT_V6M ((ARM_AEXT_V6K | ARM_EXT_V6M | ARM_EXT_BARRIER \ | |
| 156 | | ARM_EXT_THUMB_MSR) \ | |
| 157 | & ~(ARM_AEXT_NOTM | ARM_EXT_OS)) | |
| 158 | #define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS) | |
| 159 | #define ARM_AEXT_V7M ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M \ | |
| 160 | | ARM_EXT_DIV) \ | |
| 161 | & ~ARM_AEXT_NOTM) | |
| 162 | #define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M) | |
| 163 | #define ARM_AEXT_V7EM (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP) | |
| 164 | #define ARM_AEXT_V8A (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC \ | |
| 165 | | ARM_EXT_DIV | ARM_EXT_ADIV \ | |
| 166 | | ARM_EXT_VIRT | ARM_EXT_V8) | |
| ced40572 | 167 | #define ARM_AEXT2_V8AR (ARM_EXT2_V6T2_V8M | ARM_EXT2_ATOMICS) |
| 497d849d TP |
168 | #define ARM_AEXT2_V8A (ARM_AEXT2_V8AR | ARM_EXT2_V8A) |
| 169 | #define ARM_AEXT2_V8_1A (ARM_AEXT2_V8A | ARM_EXT2_PAN) | |
| 170 | #define ARM_AEXT2_V8_2A (ARM_AEXT2_V8_1A | ARM_EXT2_V8_2A | ARM_EXT2_RAS) | |
| 171 | #define ARM_AEXT2_V8_3A (ARM_AEXT2_V8_2A | ARM_EXT2_V8_3A) | |
| 172 | #define ARM_AEXT2_V8_4A (ARM_AEXT2_V8_3A | ARM_EXT2_FP16_FML \ | |
| 173 | | ARM_EXT2_V8_4A) | |
| 174 | #define ARM_AEXT2_V8_5A (ARM_AEXT2_V8_4A | ARM_EXT2_V8_5A | ARM_EXT2_SB \ | |
| 175 | | ARM_EXT2_PREDRES) | |
| aab2c27d | 176 | #define ARM_AEXT2_V8_6A (ARM_AEXT2_V8_5A | ARM_EXT2_V8_6A | ARM_EXT2_BF16) |
| 497d849d TP |
177 | #define ARM_AEXT_V8M_BASE (ARM_AEXT_V6SM | ARM_EXT_DIV) |
| 178 | #define ARM_AEXT_V8M_MAIN ARM_AEXT_V7M | |
| 179 | #define ARM_AEXT_V8M_MAIN_DSP ARM_AEXT_V7EM | |
| 180 | #define ARM_AEXT2_V8M_BASE (ARM_EXT2_V8M | ARM_EXT2_ATOMICS \ | |
| 181 | | ARM_EXT2_V6T2_V8M) | |
| 182 | #define ARM_AEXT2_V8M_MAIN (ARM_AEXT2_V8M_BASE | ARM_EXT2_V8M_MAIN) | |
| 183 | #define ARM_AEXT2_V8M_MAIN_DSP ARM_AEXT2_V8M_MAIN | |
| 184 | #define ARM_AEXT_V8R ARM_AEXT_V8A | |
| 185 | #define ARM_AEXT2_V8R ARM_AEXT2_V8AR | |
| 031254f2 AV |
186 | #define ARM_AEXT_V8_1M_MAIN ARM_AEXT_V8M_MAIN |
| 187 | #define ARM_AEXT2_V8_1M_MAIN (ARM_AEXT2_V8M_MAIN | ARM_EXT2_V8_1M_MAIN \ | |
| 188 | | ARM_EXT2_FP16_INST) | |
| b781e558 RE |
189 | |
| 190 | /* Processors with specific extensions in the co-processor space. */ | |
| 823d2571 | 191 | #define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) |
| e74cfd16 | 192 | #define ARM_ARCH_IWMMXT \ |
| 823d2571 | 193 | ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT) |
| 2d447fca | 194 | #define ARM_ARCH_IWMMXT2 \ |
| 823d2571 TG |
195 | ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT \ |
| 196 | | ARM_CEXT_IWMMXT2) | |
| e74cfd16 | 197 | |
| 497d849d TP |
198 | #define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE) |
| 199 | #define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1) | |
| 200 | #define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2) | |
| 201 | #define FPU_VFP_V3D16 (FPU_VFP_V2 | FPU_VFP_EXT_V3xD \ | |
| 202 | | FPU_VFP_EXT_V3) | |
| 203 | #define FPU_VFP_V3 (FPU_VFP_V3D16 | FPU_VFP_EXT_D32) | |
| 204 | #define FPU_VFP_V3xD (FPU_VFP_V1xD | FPU_VFP_EXT_V2 \ | |
| 205 | | FPU_VFP_EXT_V3xD) | |
| 206 | #define FPU_VFP_V4D16 (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 \ | |
| 207 | | FPU_VFP_EXT_FMA) | |
| 208 | #define FPU_VFP_V4 (FPU_VFP_V3 | FPU_VFP_EXT_FP16 \ | |
| 209 | | FPU_VFP_EXT_FMA) | |
| 210 | #define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 \ | |
| 211 | | FPU_VFP_EXT_FMA) | |
| 212 | #define FPU_VFP_V5D16 (FPU_VFP_V4D16 | FPU_VFP_EXT_ARMV8xD \ | |
| 213 | | FPU_VFP_EXT_ARMV8) | |
| a715796b | 214 | #define FPU_VFP_V5_SP_D16 (FPU_VFP_V4_SP_D16 | FPU_VFP_EXT_ARMV8xD) |
| 497d849d TP |
215 | #define FPU_VFP_ARMV8 (FPU_VFP_V4 | FPU_VFP_EXT_ARMV8 \ |
| 216 | | FPU_VFP_EXT_ARMV8xD) | |
| 217 | #define FPU_NEON_ARMV8 (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA \ | |
| 218 | | FPU_NEON_EXT_ARMV8) | |
| 34ef62f4 | 219 | #define FPU_NEON_ARMV8_1 (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA) |
| 497d849d TP |
220 | #define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8) |
| 221 | #define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 \ | |
| 222 | | FPU_VFP_EXT_V2 \ | |
| 223 | | FPU_VFP_EXT_V3xD \ | |
| 224 | | FPU_VFP_EXT_FMA \ | |
| 225 | | FPU_NEON_EXT_FMA \ | |
| 226 | | FPU_VFP_EXT_V3 \ | |
| 227 | | FPU_NEON_EXT_V1 \ | |
| 228 | | FPU_VFP_EXT_D32) | |
| 229 | #define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2) | |
| e74cfd16 | 230 | |
| 84701018 | 231 | /* Deprecated. */ |
| 497d849d | 232 | #define FPU_ARCH_VFP ARM_FEATURE_COPROC (FPU_ENDIAN_PURE) |
| b781e558 | 233 | |
| 497d849d TP |
234 | #define FPU_ARCH_FPE ARM_FEATURE_COPROC (FPU_FPA_EXT_V1) |
| 235 | #define FPU_ARCH_FPA ARM_FEATURE_COPROC (FPU_FPA) | |
| b781e558 | 236 | |
| 497d849d TP |
237 | #define FPU_ARCH_VFP_V1xD ARM_FEATURE_COPROC (FPU_VFP_V1xD) |
| 238 | #define FPU_ARCH_VFP_V1 ARM_FEATURE_COPROC (FPU_VFP_V1) | |
| 239 | #define FPU_ARCH_VFP_V2 ARM_FEATURE_COPROC (FPU_VFP_V2) | |
| 823d2571 | 240 | #define FPU_ARCH_VFP_V3D16 ARM_FEATURE_COPROC (FPU_VFP_V3D16) |
| 497d849d TP |
241 | #define FPU_ARCH_VFP_V3D16_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3D16 \ |
| 242 | | FPU_VFP_EXT_FP16) | |
| 243 | #define FPU_ARCH_VFP_V3 ARM_FEATURE_COPROC (FPU_VFP_V3) | |
| 244 | #define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3 \ | |
| 245 | | FPU_VFP_EXT_FP16) | |
| 823d2571 | 246 | #define FPU_ARCH_VFP_V3xD ARM_FEATURE_COPROC (FPU_VFP_V3xD) |
| 497d849d TP |
247 | #define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3xD \ |
| 248 | | FPU_VFP_EXT_FP16) | |
| 249 | #define FPU_ARCH_NEON_V1 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1) | |
| 250 | #define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \ | |
| 251 | ARM_FEATURE_COPROC (FPU_VFP_V3 \ | |
| 252 | | FPU_NEON_EXT_V1) | |
| 253 | #define FPU_ARCH_NEON_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3 \ | |
| 254 | | FPU_NEON_EXT_V1 \ | |
| 255 | | FPU_VFP_EXT_FP16) | |
| 256 | #define FPU_ARCH_VFP_HARD ARM_FEATURE_COPROC (FPU_VFP_HARD) | |
| 257 | #define FPU_ARCH_VFP_V4 ARM_FEATURE_COPROC (FPU_VFP_V4) | |
| 258 | #define FPU_ARCH_VFP_V4D16 ARM_FEATURE_COPROC (FPU_VFP_V4D16) | |
| 259 | #define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16) | |
| 260 | #define FPU_ARCH_VFP_V5D16 ARM_FEATURE_COPROC (FPU_VFP_V5D16) | |
| 261 | #define FPU_ARCH_VFP_V5_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16) | |
| 262 | #define FPU_ARCH_NEON_VFP_V4 ARM_FEATURE_COPROC (FPU_VFP_V4 \ | |
| 263 | | FPU_NEON_EXT_V1 \ | |
| 264 | | FPU_NEON_EXT_FMA) | |
| 265 | #define FPU_ARCH_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_VFP_ARMV8) | |
| 266 | #define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \ | |
| 267 | | FPU_VFP_ARMV8) | |
| 268 | #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \ | |
| 269 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 \ | |
| 270 | | FPU_NEON_ARMV8 \ | |
| 271 | | FPU_VFP_ARMV8) | |
| 272 | #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD \ | |
| 273 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 \ | |
| 274 | | FPU_NEON_ARMV8 \ | |
| 275 | | FPU_VFP_ARMV8 \ | |
| 276 | | FPU_NEON_EXT_DOTPROD) | |
| 497d849d | 277 | #define FPU_ARCH_NEON_VFP_ARMV8_1 \ |
| 34ef62f4 AV |
278 | ARM_FEATURE_COPROC (FPU_NEON_ARMV8_1 \ |
| 279 | | FPU_VFP_ARMV8) | |
| 497d849d TP |
280 | #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1 \ |
| 281 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 \ | |
| 34ef62f4 AV |
282 | | FPU_NEON_ARMV8_1 \ |
| 283 | | FPU_VFP_ARMV8) | |
| 284 | ||
| 497d849d TP |
285 | #define FPU_ARCH_DOTPROD_NEON_VFP_ARMV8 \ |
| 286 | ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD \ | |
| 34ef62f4 | 287 | | FPU_NEON_ARMV8_1 \ |
| 497d849d | 288 | | FPU_VFP_ARMV8) |
| d6b4b13e | 289 | |
| 34ef62f4 AV |
290 | #define FPU_ARCH_NEON_VFP_ARMV8_2_FP16 \ |
| 291 | ARM_FEATURE (0, ARM_EXT2_FP16_INST, \ | |
| 292 | FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8) | |
| 293 | ||
| 294 | #define FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML \ | |
| 295 | ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \ | |
| 296 | FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8) | |
| 297 | ||
| 298 | #define FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML \ | |
| 299 | ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \ | |
| 300 | FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8 | FPU_NEON_EXT_DOTPROD) | |
| 301 | ||
| 302 | #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4 \ | |
| 303 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 \ | |
| 304 | | FPU_NEON_ARMV8_1 \ | |
| 305 | | FPU_VFP_ARMV8 \ | |
| 306 | | FPU_NEON_EXT_DOTPROD) | |
| b781e558 | 307 | |
| 823d2571 | 308 | #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE) |
| b781e558 | 309 | |
| 823d2571 | 310 | #define FPU_ARCH_MAVERICK ARM_FEATURE_COPROC (FPU_MAVERICK) |
| e74cfd16 | 311 | |
| 497d849d TP |
312 | #define ARM_ARCH_V1 ARM_FEATURE_CORE_LOW (ARM_AEXT_V1) |
| 313 | #define ARM_ARCH_V2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V2) | |
| 314 | #define ARM_ARCH_V2S ARM_FEATURE_CORE_LOW (ARM_AEXT_V2S) | |
| 315 | #define ARM_ARCH_V3 ARM_FEATURE_CORE_LOW (ARM_AEXT_V3) | |
| 316 | #define ARM_ARCH_V3M ARM_FEATURE_CORE_LOW (ARM_AEXT_V3M) | |
| 317 | #define ARM_ARCH_V4xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4xM) | |
| 318 | #define ARM_ARCH_V4 ARM_FEATURE_CORE_LOW (ARM_AEXT_V4) | |
| 319 | #define ARM_ARCH_V4TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4TxM) | |
| 320 | #define ARM_ARCH_V4T ARM_FEATURE_CORE_LOW (ARM_AEXT_V4T) | |
| 321 | #define ARM_ARCH_V5xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5xM) | |
| 322 | #define ARM_ARCH_V5 ARM_FEATURE_CORE_LOW (ARM_AEXT_V5) | |
| 323 | #define ARM_ARCH_V5TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TxM) | |
| 324 | #define ARM_ARCH_V5T ARM_FEATURE_CORE_LOW (ARM_AEXT_V5T) | |
| 325 | #define ARM_ARCH_V5TExP ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TExP) | |
| 326 | #define ARM_ARCH_V5TE ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TE) | |
| 327 | #define ARM_ARCH_V5TEJ ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TEJ) | |
| 328 | #define ARM_ARCH_V6 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6) | |
| 329 | #define ARM_ARCH_V6K ARM_FEATURE_CORE_LOW (ARM_AEXT_V6K) | |
| 330 | #define ARM_ARCH_V6Z ARM_FEATURE_CORE_LOW (ARM_AEXT_V6Z) | |
| 331 | #define ARM_ARCH_V6KZ ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KZ) | |
| 332 | #define ARM_ARCH_V6T2 ARM_FEATURE_CORE (ARM_AEXT_V6T2, ARM_EXT2_V6T2_V8M) | |
| 333 | #define ARM_ARCH_V6KT2 ARM_FEATURE_CORE (ARM_AEXT_V6KT2, ARM_EXT2_V6T2_V8M) | |
| 334 | #define ARM_ARCH_V6ZT2 ARM_FEATURE_CORE (ARM_AEXT_V6ZT2, ARM_EXT2_V6T2_V8M) | |
| 335 | #define ARM_ARCH_V6KZT2 ARM_FEATURE_CORE (ARM_AEXT_V6KZT2, ARM_EXT2_V6T2_V8M) | |
| 336 | #define ARM_ARCH_V6M ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M) | |
| 337 | #define ARM_ARCH_V6SM ARM_FEATURE_CORE_LOW (ARM_AEXT_V6SM) | |
| 338 | #define ARM_ARCH_V7 ARM_FEATURE_CORE (ARM_AEXT_V7, ARM_EXT2_V6T2_V8M) | |
| 339 | #define ARM_ARCH_V7A ARM_FEATURE_CORE (ARM_AEXT_V7A, ARM_EXT2_V6T2_V8M) | |
| 340 | #define ARM_ARCH_V7VE ARM_FEATURE_CORE (ARM_AEXT_V7VE, ARM_EXT2_V6T2_V8M) | |
| 341 | #define ARM_ARCH_V7R ARM_FEATURE_CORE (ARM_AEXT_V7R, ARM_EXT2_V6T2_V8M) | |
| 342 | #define ARM_ARCH_V7M ARM_FEATURE_CORE (ARM_AEXT_V7M, ARM_EXT2_V6T2_V8M) | |
| 343 | #define ARM_ARCH_V7EM ARM_FEATURE_CORE (ARM_AEXT_V7EM, ARM_EXT2_V6T2_V8M) | |
| 344 | #define ARM_ARCH_V8A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_AEXT2_V8A) | |
| 8b301fbb MI |
345 | #define ARM_ARCH_V8A_CRC ARM_FEATURE (ARM_AEXT_V8A, \ |
| 346 | ARM_AEXT2_V8A | ARM_EXT2_CRC) | |
| 347 | #define ARM_ARCH_V8_1A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A \ | |
| 348 | | ARM_EXT2_CRC, FPU_NEON_EXT_RDMA) | |
| 349 | #define ARM_ARCH_V8_2A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_2A \ | |
| 350 | | ARM_EXT2_CRC, FPU_NEON_EXT_RDMA) | |
| 351 | #define ARM_ARCH_V8_3A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_3A \ | |
| 352 | | ARM_EXT2_CRC, FPU_NEON_EXT_RDMA) | |
| 353 | #define ARM_ARCH_V8_4A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_4A \ | |
| 354 | | ARM_EXT2_CRC, FPU_NEON_EXT_RDMA \ | |
| 497d849d | 355 | | FPU_NEON_EXT_DOTPROD) |
| 8b301fbb MI |
356 | #define ARM_ARCH_V8_5A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_5A \ |
| 357 | | ARM_EXT2_CRC, FPU_NEON_EXT_RDMA \ | |
| 497d849d | 358 | | FPU_NEON_EXT_DOTPROD) |
| 8b301fbb MI |
359 | #define ARM_ARCH_V8_6A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_6A \ |
| 360 | | ARM_EXT2_CRC, FPU_NEON_EXT_RDMA \ | |
| aab2c27d | 361 | | FPU_NEON_EXT_DOTPROD) |
| 497d849d TP |
362 | #define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, \ |
| 363 | ARM_AEXT2_V8M_BASE) | |
| 364 | #define ARM_ARCH_V8M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN, \ | |
| 365 | ARM_AEXT2_V8M_MAIN) | |
| 366 | #define ARM_ARCH_V8M_MAIN_DSP ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN_DSP, \ | |
| 367 | ARM_AEXT2_V8M_MAIN_DSP) | |
| 368 | #define ARM_ARCH_V8R ARM_FEATURE_CORE (ARM_AEXT_V8R, ARM_AEXT2_V8R) | |
| 031254f2 AV |
369 | #define ARM_ARCH_V8_1M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8_1M_MAIN, \ |
| 370 | ARM_AEXT2_V8_1M_MAIN) | |
| b781e558 RE |
371 | |
| 372 | /* Some useful combinations: */ | |
| 823d2571 TG |
373 | #define ARM_ARCH_NONE ARM_FEATURE_LOW (0, 0) |
| 374 | #define FPU_NONE ARM_FEATURE_LOW (0, 0) | |
| 375 | #define ARM_ANY ARM_FEATURE (-1, -1, 0) /* Any basic core. */ | |
| 2c6b98ea | 376 | #define FPU_ANY ARM_FEATURE_COPROC (-1) /* Any FPU. */ |
| 1af1dd51 | 377 | #define ARM_FEATURE_ALL ARM_FEATURE (-1, -1, -1)/* All CPU and FPU features. */ |
| 823d2571 | 378 | #define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) |
| fc289b0a TP |
379 | /* Extensions containing some Thumb-2 instructions. If any is present, Thumb |
| 380 | ISA is Thumb-2. */ | |
| ff8646ee TP |
381 | #define ARM_ARCH_THUMB2 ARM_FEATURE_CORE (ARM_EXT_V6T2 | ARM_EXT_V7 \ |
| 382 | | ARM_EXT_DIV | ARM_EXT_V8, \ | |
| 383 | ARM_EXT2_ATOMICS | ARM_EXT2_V6T2_V8M) | |
| f4c65163 | 384 | /* v7-a+sec. */ |
| ff8646ee TP |
385 | #define ARM_ARCH_V7A_SEC \ |
| 386 | ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_SEC, ARM_EXT2_V6T2_V8M) | |
| f4c65163 MGD |
387 | /* v7-a+mp+sec. */ |
| 388 | #define ARM_ARCH_V7A_MP_SEC \ | |
| ff8646ee | 389 | ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, ARM_EXT2_V6T2_V8M) |
| 3b2f0793 | 390 | /* v7-r+idiv. */ |
| ff8646ee TP |
391 | #define ARM_ARCH_V7R_IDIV \ |
| 392 | ARM_FEATURE_CORE (ARM_AEXT_V7R | ARM_EXT_ADIV, ARM_EXT2_V6T2_V8M) | |
| bca38921 | 393 | /* v8-a+fp. */ |
| 4ed7ed8d | 394 | #define ARM_ARCH_V8A_FP \ |
| ff8646ee | 395 | ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, FPU_ARCH_VFP_ARMV8) |
| bca38921 | 396 | /* v8-a+simd (implies fp). */ |
| 4ed7ed8d | 397 | #define ARM_ARCH_V8A_SIMD \ |
| ff8646ee | 398 | ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, FPU_ARCH_NEON_VFP_ARMV8) |
| bca38921 | 399 | /* v8-a+crypto (implies simd+fp). */ |
| 4ed7ed8d | 400 | #define ARM_ARCH_V8A_CRYPTOV1 \ |
| ff8646ee | 401 | ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8) |
| e74cfd16 | 402 | |
| a5932920 | 403 | /* v8.1-a+fp. */ |
| 4ed7ed8d TP |
404 | #define ARM_ARCH_V8_1A_FP \ |
| 405 | ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A, FPU_ARCH_VFP_ARMV8) | |
| a5932920 | 406 | /* v8.1-a+simd (implies fp). */ |
| 4ed7ed8d TP |
407 | #define ARM_ARCH_V8_1A_SIMD \ |
| 408 | ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A, FPU_ARCH_NEON_VFP_ARMV8_1) | |
| a5932920 | 409 | /* v8.1-a+crypto (implies simd+fp). */ |
| 4ed7ed8d TP |
410 | #define ARM_ARCH_V8_1A_CRYPTOV1 \ |
| 411 | ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1) | |
| a5932920 MW |
412 | |
| 413 | ||
| e74cfd16 | 414 | /* There are too many feature bits to fit in a single word, so use a |
| 823d2571 TG |
415 | structure. For simplicity we put all core features in array CORE |
| 416 | and everything else in the other. All the bits in element core[0] | |
| 417 | have been occupied, so new feature should use bit in element core[1] | |
| 418 | and use macro ARM_FEATURE to initialize the feature set variable. */ | |
| e74cfd16 PB |
419 | typedef struct |
| 420 | { | |
| 823d2571 | 421 | unsigned long core[2]; |
| e74cfd16 PB |
422 | unsigned long coproc; |
| 423 | } arm_feature_set; | |
| 424 | ||
| 643afb90 | 425 | /* Test whether CPU and FEAT have any features in common. */ |
| e74cfd16 | 426 | #define ARM_CPU_HAS_FEATURE(CPU,FEAT) \ |
| 823d2571 TG |
427 | (((CPU).core[0] & (FEAT).core[0]) != 0 \ |
| 428 | || ((CPU).core[1] & (FEAT).core[1]) != 0 \ | |
| 429 | || ((CPU).coproc & (FEAT).coproc) != 0) | |
| e74cfd16 | 430 | |
| d942732e TP |
431 | /* Tests whether the features of A are a subset of B. */ |
| 432 | #define ARM_FSET_CPU_SUBSET(A,B) \ | |
| 433 | (((A).core[0] & (B).core[0]) == (A).core[0] \ | |
| 434 | && ((A).core[1] & (B).core[1]) == (A).core[1] \ | |
| 435 | && ((A).coproc & (B).coproc) == (A).coproc) | |
| 436 | ||
| 59d09be6 | 437 | #define ARM_CPU_IS_ANY(CPU) \ |
| 823d2571 TG |
438 | ((CPU).core[0] == ((arm_feature_set)ARM_ANY).core[0] \ |
| 439 | && (CPU).core[1] == ((arm_feature_set)ARM_ANY).core[1]) | |
| 59d09be6 | 440 | |
| 0198d5e6 TC |
441 | #define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \ |
| 442 | do \ | |
| 443 | { \ | |
| 444 | (TARG).core[0] = (F1).core[0] | (F2).core[0]; \ | |
| 445 | (TARG).core[1] = (F1).core[1] | (F2).core[1]; \ | |
| 446 | (TARG).coproc = (F1).coproc | (F2).coproc; \ | |
| 447 | } \ | |
| 448 | while (0) | |
| 449 | ||
| 450 | #define ARM_CLEAR_FEATURE(TARG,F1,F2) \ | |
| 451 | do \ | |
| 452 | { \ | |
| 453 | (TARG).core[0] = (F1).core[0] &~ (F2).core[0]; \ | |
| 454 | (TARG).core[1] = (F1).core[1] &~ (F2).core[1]; \ | |
| 455 | (TARG).coproc = (F1).coproc &~ (F2).coproc; \ | |
| 456 | } \ | |
| 457 | while (0) | |
| e74cfd16 | 458 | |
| 823d2571 | 459 | #define ARM_FEATURE_EQUAL(T1,T2) \ |
| 0198d5e6 | 460 | ( (T1).core[0] == (T2).core[0] \ |
| 823d2571 | 461 | && (T1).core[1] == (T2).core[1] \ |
| 0198d5e6 | 462 | && (T1).coproc == (T2).coproc) |
| 823d2571 TG |
463 | |
| 464 | #define ARM_FEATURE_ZERO(T) \ | |
| 465 | ((T).core[0] == 0 && (T).core[1] == 0 && (T).coproc == 0) | |
| 466 | ||
| 467 | #define ARM_FEATURE_CORE_EQUAL(T1, T2) \ | |
| 468 | ((T1).core[0] == (T2).core[0] && (T1).core[1] == (T2).core[1]) | |
| 469 | ||
| 470 | #define ARM_FEATURE_LOW(core, coproc) {{(core), 0}, (coproc)} | |
| a5932920 | 471 | #define ARM_FEATURE_CORE(core1, core2) {{(core1), (core2)}, 0} |
| 823d2571 | 472 | #define ARM_FEATURE_CORE_LOW(core) {{(core), 0}, 0} |
| ddfded2f | 473 | #define ARM_FEATURE_CORE_HIGH(core) {{0, (core)}, 0} |
| 823d2571 TG |
474 | #define ARM_FEATURE_COPROC(coproc) {{0, 0}, (coproc)} |
| 475 | #define ARM_FEATURE(core1, core2, coproc) {{(core1), (core2)}, (coproc)} |