[thirdparty/binutils-gdb.git] / include / opcode / nios2.h

/* Nios II opcode list for GAS, the GNU assembler.
   Copyright (C) 2012-2021 Free Software Foundation, Inc.
   Contributed by Nigel Gray (ngray@altera.com).
   Contributed by Mentor Graphics, Inc.

   This file is part of the GNU opcodes library.

   GAS/GDB is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   GAS/GDB is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS or GDB; see the file COPYING3.  If not, write to
   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
   Boston, MA 02110-1301, USA.  */

#ifndef _NIOS2_H_
#define _NIOS2_H_

#include "bfd.h"

#ifdef __cplusplus
extern "C" {
#endif

/****************************************************************************
 * This file contains structures, bit masks and shift counts used
 * by the GNU toolchain to define the Nios II instruction set and
 * access various opcode fields.
 ****************************************************************************/

/* Instruction encoding formats.  */
enum iw_format_type {
  /* R1 formats.  */
  iw_i_type,
  iw_r_type,
  iw_j_type,
  iw_custom_type,

  /* 32-bit R2 formats.  */
  iw_L26_type,
  iw_F2I16_type,
  iw_F2X4I12_type,
  iw_F1X4I12_type,
  iw_F1X4L17_type,
  iw_F3X6L5_type,
  iw_F2X6L10_type,
  iw_F3X6_type,
  iw_F3X8_type,

  /* 16-bit R2 formats.  */
  iw_I10_type,
  iw_T1I7_type,
  iw_T2I4_type,
  iw_T1X1I6_type,
  iw_X1I7_type,
  iw_L5I4X1_type,
  iw_T2X1L3_type,
  iw_T2X1I3_type,
  iw_T3X1_type,
  iw_T2X3_type,
  iw_F1X1_type,
  iw_X2L5_type,
  iw_F1I5_type,
  iw_F2_type
};

/* Identify different overflow situations for error messages.  */
enum overflow_type
{
  call_target_overflow = 0,
  branch_target_overflow,
  address_offset_overflow,
  signed_immed16_overflow,
  unsigned_immed16_overflow,
  unsigned_immed5_overflow,
  signed_immed12_overflow,
  custom_opcode_overflow,
  enumeration_overflow,
  no_overflow
};

/* This structure holds information for a particular instruction. 

   The args field is a string describing the operands.  The following
   letters can appear in the args:
     c - a 5-bit control register index
     d - a 5-bit destination register index
     s - a 5-bit left source register index
     t - a 5-bit right source register index
     D - a 3-bit encoded destination register
     S - a 3-bit encoded left source register
     T - a 3-bit encoded right source register
     i - a 16-bit signed immediate
     j - a 5-bit unsigned immediate
     k - a (second) 5-bit unsigned immediate
     l - a 8-bit custom instruction constant
     m - a 26-bit unsigned immediate
     o - a 16-bit signed pc-relative offset
     u - a 16-bit unsigned immediate
     I - a 12-bit signed immediate
     M - a 6-bit unsigned immediate
     N - a 6-bit unsigned immediate with 2-bit shift
     O - a 10-bit signed pc-relative offset with 1-bit shift
     P - a 7-bit signed pc-relative offset with 1-bit shift
     U - a 7-bit unsigned immediate with 2-bit shift
     V - a 5-bit unsigned immediate with 2-bit shift
     W - a 4-bit unsigned immediate with 2-bit shift
     X - a 4-bit unsigned immediate with 1-bit shift
     Y - a 4-bit unsigned immediate
     e - an immediate coded as an enumeration for addi.n/subi.n
     f - an immediate coded as an enumeration for slli.n/srli.n
     g - an immediate coded as an enumeration for andi.n
     h - an immediate coded as an enumeration for movi.n
     R - a reglist for ldwm/stwm or push.n/pop.n
     B - a base register specifier and option list for ldwm/stwm
   Literal ',', '(', and ')' characters may also appear in the args as
   delimiters.

   Note that the args describe the semantics and assembly-language syntax
   of the operands, not their encoding into the instruction word.

   The pinfo field is INSN_MACRO for a macro.  Otherwise, it is a collection
   of bits describing the instruction, notably any relevant hazard
   information.

   When assembling, the match field contains the opcode template, which
   is modified by the arguments to produce the actual opcode
   that is emitted.  If pinfo is INSN_MACRO, then this is 0.

   If pinfo is INSN_MACRO, the mask field stores the macro identifier.
   Otherwise this is a bit mask for the relevant portions of the opcode
   when disassembling.  If the actual opcode anded with the match field
   equals the opcode field, then we have found the correct instruction.  */

struct nios2_opcode
{
  const char *name;		/* The name of the instruction.  */
  const char *args;		/* A string describing the arguments for this 
				   instruction.  */
  const char *args_test;	/* Like args, but with an extra argument for 
				   the expected opcode.  */
  unsigned long num_args;	/* The number of arguments the instruction 
				   takes.  */
  unsigned size;		/* Size in bytes of the instruction.  */
  enum iw_format_type format;	/* Instruction format.  */
  unsigned long match;		/* The basic opcode for the instruction.  */
  unsigned long mask;		/* Mask for the opcode field of the 
				   instruction.  */
  unsigned long pinfo;		/* Is this a real instruction or instruction 
				   macro?  */
  enum overflow_type overflow_msg;  /* Used to generate informative 
				       message when fixup overflows.  */
};

/* This value is used in the nios2_opcode.pinfo field to indicate that the 
   instruction is a macro or pseudo-op.  This requires special treatment by 
   the assembler, and is used by the disassembler to determine whether to 
   check for a nop.  */
#define NIOS2_INSN_MACRO	0x80000000
#define NIOS2_INSN_MACRO_MOV	0x80000001
#define NIOS2_INSN_MACRO_MOVI	0x80000002
#define NIOS2_INSN_MACRO_MOVIA	0x80000004

#define NIOS2_INSN_RELAXABLE	0x40000000
#define NIOS2_INSN_UBRANCH	0x00000010
#define NIOS2_INSN_CBRANCH	0x00000020
#define NIOS2_INSN_CALL		0x00000040

#define NIOS2_INSN_OPTARG	0x00000080

/* Register attributes.  */
#define REG_NORMAL	(1<<0)	/* Normal registers.  */
#define REG_CONTROL	(1<<1)  /* Control registers.  */
#define REG_COPROCESSOR	(1<<2)  /* For custom instructions.  */
#define REG_3BIT	(1<<3)  /* For R2 CDX instructions.  */
#define REG_LDWM	(1<<4)  /* For R2 ldwm/stwm.  */
#define REG_POP		(1<<5)  /* For R2 pop.n/push.n.  */

struct nios2_reg
{
  const char *name;
  const int index;
  unsigned long regtype;
};

/* Pull in the instruction field accessors, opcodes, and masks.  */
#include "nios2r1.h"
#include "nios2r2.h"

/* These are the data structures used to hold the instruction information.  */
extern const struct nios2_opcode nios2_r1_opcodes[];
extern const int nios2_num_r1_opcodes;
extern const struct nios2_opcode nios2_r2_opcodes[];
extern const int nios2_num_r2_opcodes;
extern struct nios2_opcode *nios2_opcodes;
extern int nios2_num_opcodes;

/* These are the data structures used to hold the register information.  */
extern const struct nios2_reg nios2_builtin_regs[];
extern struct nios2_reg *nios2_regs;
extern const int nios2_num_builtin_regs;
extern int nios2_num_regs;

/* Return the opcode descriptor for a single instruction.  */
extern const struct nios2_opcode *
nios2_find_opcode_hash (unsigned long, unsigned long);

/* Lookup tables for R2 immediate decodings.  */
extern unsigned int nios2_r2_asi_n_mappings[];
extern const int nios2_num_r2_asi_n_mappings;
extern unsigned int nios2_r2_shi_n_mappings[];
extern const int nios2_num_r2_shi_n_mappings;
extern unsigned int nios2_r2_andi_n_mappings[];
extern const int nios2_num_r2_andi_n_mappings;

/* Lookup table for 3-bit register decodings.  */
extern int nios2_r2_reg3_mappings[];
extern const int nios2_num_r2_reg3_mappings;

/* Lookup table for REG_RANGE value list decodings.  */
extern unsigned long nios2_r2_reg_range_mappings[];
extern const int nios2_num_r2_reg_range_mappings;

#ifdef __cplusplus
}
#endif

#endif /* _NIOS2_H */
Commit	Line	Data
36591ba1	1	/* Nios II opcode list for GAS, the GNU assembler.
250d07de	2	Copyright (C) 2012-2021 Free Software Foundation, Inc.
36591ba1 SL	3	Contributed by Nigel Gray (ngray@altera.com).
	4	Contributed by Mentor Graphics, Inc.
	5
a1aa5e81	6	This file is part of the GNU opcodes library.
36591ba1 SL	7
	8	GAS/GDB is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 3, or (at your option)
	11	any later version.
	12
	13	GAS/GDB is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with GAS or GDB; see the file COPYING3. If not, write to
	20	the Free Software Foundation, 51 Franklin Street - Fifth Floor,
	21	Boston, MA 02110-1301, USA. */
	22
	23	#ifndef _NIOS2_H_
	24	#define _NIOS2_H_
	25
	26	#include "bfd.h"
	27
f63c1776 PA	28	#ifdef __cplusplus
	29	extern "C" {
	30	#endif
	31
36591ba1 SL	32	/****************************************************************************
	33	* This file contains structures, bit masks and shift counts used
	34	* by the GNU toolchain to define the Nios II instruction set and
	35	* access various opcode fields.
	36	****************************************************************************/
	37
96ba4233 SL	38	/* Instruction encoding formats. */
96ba4233 SL	39	enum iw_format_type {
c8c8175b	40	/* R1 formats. */
96ba4233 SL	41	iw_i_type,
	42	iw_r_type,
	43	iw_j_type,
c8c8175b SL	44	iw_custom_type,
	45
	46	/* 32-bit R2 formats. */
	47	iw_L26_type,
	48	iw_F2I16_type,
	49	iw_F2X4I12_type,
	50	iw_F1X4I12_type,
	51	iw_F1X4L17_type,
	52	iw_F3X6L5_type,
	53	iw_F2X6L10_type,
	54	iw_F3X6_type,
	55	iw_F3X8_type,
	56
	57	/* 16-bit R2 formats. */
	58	iw_I10_type,
	59	iw_T1I7_type,
	60	iw_T2I4_type,
	61	iw_T1X1I6_type,
	62	iw_X1I7_type,
	63	iw_L5I4X1_type,
	64	iw_T2X1L3_type,
	65	iw_T2X1I3_type,
	66	iw_T3X1_type,
	67	iw_T2X3_type,
	68	iw_F1X1_type,
	69	iw_X2L5_type,
	70	iw_F1I5_type,
	71	iw_F2_type
96ba4233 SL	72	};
96ba4233 SL	73
36591ba1 SL	74	/* Identify different overflow situations for error messages. */
	75	enum overflow_type
	76	{
	77	call_target_overflow = 0,
	78	branch_target_overflow,
	79	address_offset_overflow,
	80	signed_immed16_overflow,
	81	unsigned_immed16_overflow,
	82	unsigned_immed5_overflow,
c8c8175b	83	signed_immed12_overflow,
36591ba1	84	custom_opcode_overflow,
c8c8175b	85	enumeration_overflow,
36591ba1 SL	86	no_overflow
	87	};
	88
	89	/* This structure holds information for a particular instruction.
	90
	91	The args field is a string describing the operands. The following
	92	letters can appear in the args:
531a94fd	93	c - a 5-bit control register index
36591ba1 SL	94	d - a 5-bit destination register index
	95	s - a 5-bit left source register index
	96	t - a 5-bit right source register index
c8c8175b SL	97	D - a 3-bit encoded destination register
	98	S - a 3-bit encoded left source register
	99	T - a 3-bit encoded right source register
36591ba1	100	i - a 16-bit signed immediate
36591ba1	101	j - a 5-bit unsigned immediate
c8c8175b	102	k - a (second) 5-bit unsigned immediate
531a94fd	103	l - a 8-bit custom instruction constant
36591ba1	104	m - a 26-bit unsigned immediate
c8c8175b SL	105	o - a 16-bit signed pc-relative offset
	106	u - a 16-bit unsigned immediate
	107	I - a 12-bit signed immediate
	108	M - a 6-bit unsigned immediate
	109	N - a 6-bit unsigned immediate with 2-bit shift
	110	O - a 10-bit signed pc-relative offset with 1-bit shift
	111	P - a 7-bit signed pc-relative offset with 1-bit shift
	112	U - a 7-bit unsigned immediate with 2-bit shift
	113	V - a 5-bit unsigned immediate with 2-bit shift
	114	W - a 4-bit unsigned immediate with 2-bit shift
	115	X - a 4-bit unsigned immediate with 1-bit shift
	116	Y - a 4-bit unsigned immediate
	117	e - an immediate coded as an enumeration for addi.n/subi.n
	118	f - an immediate coded as an enumeration for slli.n/srli.n
	119	g - an immediate coded as an enumeration for andi.n
	120	h - an immediate coded as an enumeration for movi.n
	121	R - a reglist for ldwm/stwm or push.n/pop.n
	122	B - a base register specifier and option list for ldwm/stwm
36591ba1 SL	123	Literal ',', '(', and ')' characters may also appear in the args as
	124	delimiters.
	125
96ba4233 SL	126	Note that the args describe the semantics and assembly-language syntax
	127	of the operands, not their encoding into the instruction word.
	128
36591ba1 SL	129	The pinfo field is INSN_MACRO for a macro. Otherwise, it is a collection
	130	of bits describing the instruction, notably any relevant hazard
	131	information.
	132
	133	When assembling, the match field contains the opcode template, which
	134	is modified by the arguments to produce the actual opcode
	135	that is emitted. If pinfo is INSN_MACRO, then this is 0.
	136
	137	If pinfo is INSN_MACRO, the mask field stores the macro identifier.
	138	Otherwise this is a bit mask for the relevant portions of the opcode
	139	when disassembling. If the actual opcode anded with the match field
	140	equals the opcode field, then we have found the correct instruction. */
	141
	142	struct nios2_opcode
	143	{
	144	const char name; / The name of the instruction. */
	145	const char args; / A string describing the arguments for this
	146	instruction. */
	147	const char args_test; / Like args, but with an extra argument for
	148	the expected opcode. */
	149	unsigned long num_args; /* The number of arguments the instruction
	150	takes. */
96ba4233 SL	151	unsigned size; /* Size in bytes of the instruction. */
96ba4233 SL	152	enum iw_format_type format; /* Instruction format. */
36591ba1 SL	153	unsigned long match; /* The basic opcode for the instruction. */
	154	unsigned long mask; /* Mask for the opcode field of the
	155	instruction. */
	156	unsigned long pinfo; /* Is this a real instruction or instruction
	157	macro? */
	158	enum overflow_type overflow_msg; /* Used to generate informative
	159	message when fixup overflows. */
	160	};
	161
	162	/* This value is used in the nios2_opcode.pinfo field to indicate that the
	163	instruction is a macro or pseudo-op. This requires special treatment by
	164	the assembler, and is used by the disassembler to determine whether to
	165	check for a nop. */
	166	#define NIOS2_INSN_MACRO 0x80000000
	167	#define NIOS2_INSN_MACRO_MOV 0x80000001
	168	#define NIOS2_INSN_MACRO_MOVI 0x80000002
	169	#define NIOS2_INSN_MACRO_MOVIA 0x80000004
	170
	171	#define NIOS2_INSN_RELAXABLE 0x40000000
	172	#define NIOS2_INSN_UBRANCH 0x00000010
	173	#define NIOS2_INSN_CBRANCH 0x00000020
	174	#define NIOS2_INSN_CALL 0x00000040
	175
d306ce58	176	#define NIOS2_INSN_OPTARG 0x00000080
96ba4233 SL	177
	178	/* Register attributes. */
	179	#define REG_NORMAL (1<<0) /* Normal registers. */
	180	#define REG_CONTROL (1<<1) /* Control registers. */
	181	#define REG_COPROCESSOR (1<<2) /* For custom instructions. */
c8c8175b SL	182	#define REG_3BIT (1<<3) /* For R2 CDX instructions. */
	183	#define REG_LDWM (1<<4) /* For R2 ldwm/stwm. */
	184	#define REG_POP (1<<5) /* For R2 pop.n/push.n. */
36591ba1	185
36591ba1 SL	186	struct nios2_reg
	187	{
	188	const char *name;
	189	const int index;
96ba4233	190	unsigned long regtype;
36591ba1 SL	191	};
36591ba1 SL	192
96ba4233 SL	193	/* Pull in the instruction field accessors, opcodes, and masks. */
96ba4233 SL	194	#include "nios2r1.h"
c8c8175b	195	#include "nios2r2.h"
36591ba1	196
96ba4233 SL	197	/* These are the data structures used to hold the instruction information. */
	198	extern const struct nios2_opcode nios2_r1_opcodes[];
	199	extern const int nios2_num_r1_opcodes;
c8c8175b SL	200	extern const struct nios2_opcode nios2_r2_opcodes[];
c8c8175b SL	201	extern const int nios2_num_r2_opcodes;
36591ba1	202	extern struct nios2_opcode *nios2_opcodes;
96ba4233	203	extern int nios2_num_opcodes;
36591ba1 SL	204
	205	/* These are the data structures used to hold the register information. */
	206	extern const struct nios2_reg nios2_builtin_regs[];
	207	extern struct nios2_reg *nios2_regs;
	208	extern const int nios2_num_builtin_regs;
	209	extern int nios2_num_regs;
	210
b4714c7c SL	211	/* Return the opcode descriptor for a single instruction. */
	212	extern const struct nios2_opcode *
	213	nios2_find_opcode_hash (unsigned long, unsigned long);
36591ba1	214
c8c8175b SL	215	/* Lookup tables for R2 immediate decodings. */
	216	extern unsigned int nios2_r2_asi_n_mappings[];
	217	extern const int nios2_num_r2_asi_n_mappings;
	218	extern unsigned int nios2_r2_shi_n_mappings[];
	219	extern const int nios2_num_r2_shi_n_mappings;
	220	extern unsigned int nios2_r2_andi_n_mappings[];
	221	extern const int nios2_num_r2_andi_n_mappings;
	222
	223	/* Lookup table for 3-bit register decodings. */
	224	extern int nios2_r2_reg3_mappings[];
	225	extern const int nios2_num_r2_reg3_mappings;
	226
	227	/* Lookup table for REG_RANGE value list decodings. */
	228	extern unsigned long nios2_r2_reg_range_mappings[];
	229	extern const int nios2_num_r2_reg_range_mappings;
	230
f63c1776 PA	231	#ifdef __cplusplus
	232	}
	233	#endif
	234
36591ba1	235	#endif /* _NIOS2_H */