[thirdparty/binutils-gdb.git] / include / opcode / sparc.h

/* Definitions for opcode table for the sparc.
   Copyright (C) 1989-2016 Free Software Foundation, Inc.

   This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   the GNU Binutils.

   GAS/GDB is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   GAS/GDB is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS or GDB; see the file COPYING3.  If not, write to
   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
   Boston, MA 02110-1301, USA.  */

#include "ansidecl.h"

/* The SPARC opcode table (and other related data) is defined in
   the opcodes library in sparc-opc.c.  If you change anything here, make
   sure you fix up that file, and vice versa.  */

 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
    instruction's name rather than the args.  This would make gas faster, pinsn
    slower, but would mess up some macros a bit.  xoxorich. */

/* List of instruction sets variations.
   These values are such that each element is either a superset of a
   preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
   returns non-zero.
   The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
   Don't change this without updating sparc-opc.c.  */

enum sparc_opcode_arch_val
{
  SPARC_OPCODE_ARCH_V6 = 0,
  SPARC_OPCODE_ARCH_V7,
  SPARC_OPCODE_ARCH_V8,
  SPARC_OPCODE_ARCH_LEON,
  SPARC_OPCODE_ARCH_SPARCLET,
  SPARC_OPCODE_ARCH_SPARCLITE,
  /* V9 variants must appear last.  */
  SPARC_OPCODE_ARCH_V9,
  SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions.  */
  SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions.  */
  SPARC_OPCODE_ARCH_BAD  /* Error return from sparc_opcode_lookup_arch.  */
};

/* The highest architecture in the table.  */
#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)

/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
   insn encoding/decoding.  */
#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))

/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9.  */
#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)

/* Table of cpu variants.  */

typedef struct sparc_opcode_arch
{
  const char *name;
  /* Mask of sparc_opcode_arch_val's supported.
     EG: For v7 this would be
     (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
     These are short's because sparc_opcode.architecture is.  */
  short supported;
} sparc_opcode_arch;

extern const struct sparc_opcode_arch sparc_opcode_archs[];

/* Given architecture name, look up it's sparc_opcode_arch_val value.  */
extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *);

/* Return the bitmask of supported architectures for ARCH.  */
#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)

/* Non-zero if ARCH1 conflicts with ARCH2.
   IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa.  */
#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
 (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
   != SPARC_OPCODE_SUPPORTED (ARCH1)) \
  && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
     != SPARC_OPCODE_SUPPORTED (ARCH2)))

/* Structure of an opcode table entry.  */

typedef struct sparc_opcode
{
  const char *name;
  unsigned long match;	/* Bits that must be set.  */
  unsigned long lose;	/* Bits that must not be set.  */
  const char *args;
  /* This was called "delayed" in versions before the flags.  */
  unsigned int flags;
  unsigned int hwcaps;
  unsigned int hwcaps2;
  short architecture;	/* Bitmask of sparc_opcode_arch_val's.  */
} sparc_opcode;

/* FIXME: Add F_ANACHRONISTIC flag for v9.  */
#define	F_DELAYED	0x00000001 /* Delayed branch.  */
#define	F_ALIAS		0x00000002 /* Alias for a "real" instruction.  */
#define	F_UNBR		0x00000004 /* Unconditional branch.  */
#define	F_CONDBR	0x00000008 /* Conditional branch.  */
#define	F_JSR		0x00000010 /* Subroutine call.  */
#define F_FLOAT		0x00000020 /* Floating point instruction (not a branch).  */
#define F_FBR		0x00000040 /* Floating point branch.  */
#define F_PREFERRED	0x00000080 /* A preferred alias.  */

#define F_PREF_ALIAS	(F_ALIAS|F_PREFERRED)

/* These must match the ELF_SPARC_HWCAP_* and ELF_SPARC_HWCAP2_*
   values precisely.  See include/elf/sparc.h.  */
#define HWCAP_MUL32	0x00000001 /* umul/umulcc/smul/smulcc insns */
#define HWCAP_DIV32	0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
#define HWCAP_FSMULD	0x00000004 /* 'fsmuld' insn */
#define HWCAP_V8PLUS	0x00000008 /* v9 insns available to 32bit */
#define HWCAP_POPC	0x00000010 /* 'popc' insn */
#define HWCAP_VIS	0x00000020 /* VIS insns */
#define HWCAP_VIS2	0x00000040 /* VIS2 insns */
#define HWCAP_ASI_BLK_INIT	\
			0x00000080 /* block init ASIs */
#define HWCAP_FMAF	0x00000100 /* fused multiply-add */
#define HWCAP_VIS3	0x00000400 /* VIS3 insns */
#define HWCAP_HPC	0x00000800 /* HPC insns */
#define HWCAP_RANDOM	0x00001000 /* 'random' insn */
#define HWCAP_TRANS	0x00002000 /* transaction insns */
#define HWCAP_FJFMAU	0x00004000 /* unfused multiply-add */
#define HWCAP_IMA	0x00008000 /* integer multiply-add */
#define HWCAP_ASI_CACHE_SPARING \
			0x00010000 /* cache sparing ASIs */
#define HWCAP_AES	0x00020000 /* AES crypto insns */
#define HWCAP_DES	0x00040000 /* DES crypto insns */
#define HWCAP_KASUMI	0x00080000 /* KASUMI crypto insns */
#define HWCAP_CAMELLIA 	0x00100000 /* CAMELLIA crypto insns */
#define HWCAP_MD5	0x00200000 /* MD5 hashing insns */
#define HWCAP_SHA1	0x00400000 /* SHA1 hashing insns */
#define HWCAP_SHA256	0x00800000 /* SHA256 hashing insns */
#define HWCAP_SHA512	0x01000000 /* SHA512 hashing insns */
#define HWCAP_MPMUL	0x02000000 /* Multiple Precision Multiply */
#define HWCAP_MONT	0x04000000 /* Montgomery Mult/Sqrt */
#define HWCAP_PAUSE	0x08000000 /* Pause insn */
#define HWCAP_CBCOND	0x10000000 /* Compare and Branch insns */
#define HWCAP_CRC32C	0x20000000 /* CRC32C insn */

#define HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */
#define HWCAP2_VIS3B     0x00000002 /* Subset of VIS3 present on sparc64 X+.  */
#define HWCAP2_ADP       0x00000004 /* Application Data Protection */
#define HWCAP2_SPARC5    0x00000008 /* The 29 new fp and sub instructions */
#define HWCAP2_MWAIT     0x00000010 /* mwait instruction and load/monitor ASIs */
#define HWCAP2_XMPMUL    0x00000020 /* XOR multiple precision multiply */
#define HWCAP2_XMONT     0x00000040 /* XOR Montgomery mult/sqr instructions */
#define HWCAP2_NSEC      \
                         0x00000080 /* pause insn with support for nsec timings */
#define HWCAP2_FJATHHPC  0x00001000 /* Fujitsu HPC instrs */
#define HWCAP2_FJDES     0x00002000 /* Fujitsu DES instrs */
#define HWCAP2_FJAES     0x00010000 /* Fujitsu AES instrs */


/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
   macro), which is 64 bits. It is handled as a special case.

   The match component is a mask saying which bits must match a particular
   opcode in order for an instruction to be an instance of that opcode.

   The args component is a string containing one character for each operand of the
   instruction.

   Kinds of operands:
	#	Number used by optimizer.	It is ignored.
	1	rs1 register.
	2	rs2 register.
	d	rd register.
	e	frs1 floating point register.
	v	frs1 floating point register (double/even).
	V	frs1 floating point register (quad/multiple of 4).
	f	frs2 floating point register.
	B	frs2 floating point register (double/even).
	R	frs2 floating point register (quad/multiple of 4).
	4	frs3 floating point register.
	5	frs3 floating point register (doube/even).
	g	frsd floating point register.
	H	frsd floating point register (double/even).
	J	frsd floating point register (quad/multiple of 4).
	}       frsd floating point register (double/even) that is == frs2
	b	crs1 coprocessor register
	c	crs2 coprocessor register
	D	crsd coprocessor register
	m	alternate space register (asr) in rd
	M	alternate space register (asr) in rs1
	h	22 high bits.
	X	5 bit unsigned immediate
	Y	6 bit unsigned immediate
	3	SIAM mode (3 bits). (v9b)
	K	MEMBAR mask (7 bits). (v9)
	j	10 bit Immediate. (v9)
	I	11 bit Immediate. (v9)
	i	13 bit Immediate.
	n	22 bit immediate.
	k	2+14 bit PC relative immediate. (v9)
	G	19 bit PC relative immediate. (v9)
	l	22 bit PC relative immediate.
	L	30 bit PC relative immediate.
	a	Annul.	The annul bit is set.
	A	Alternate address space. Stored as 8 bits.
	C	Coprocessor state register.
	F	floating point state register.
	p	Processor state register.
	N	Branch predict clear ",pn" (v9)
	T	Branch predict set ",pt" (v9)
	z	%icc. (v9)
	Z	%xcc. (v9)
	q	Floating point queue.
	r	Single register that is both rs1 and rd.
	O	Single register that is both rs2 and rd.
	Q	Coprocessor queue.
	S	Special case.
	t	Trap base register.
	w	Window invalid mask register.
	y	Y register.
	u	sparclet coprocessor registers in rd position
	U	sparclet coprocessor registers in rs1 position
	E	%ccr. (v9)
	s	%fprs. (v9)
	P	%pc.  (v9)
	W	%tick.	(v9)
	{	%mcdper. (v9b)
	o	%asi. (v9)
	6	%fcc0. (v9)
	7	%fcc1. (v9)
	8	%fcc2. (v9)
	9	%fcc3. (v9)
	!	Privileged Register in rd (v9)
	?	Privileged Register in rs1 (v9)
	*	Prefetch function constant. (v9)
	x	OPF field (v9 impdep).
	0	32/64 bit immediate for set or setx (v9) insns
	_	Ancillary state register in rd (v9a)
	/	Ancillary state register in rs1 (v9a)
	(	entire floating point state register (%efsr)
	)	5 bit immediate placed in RS3 field
	=	2+8 bit PC relative immediate. (v9)  */

#define OP2(x)		(((x) & 0x7) << 22)  /* Op2 field of format2 insns.  */
#define OP3(x)		(((x) & 0x3f) << 19) /* Op3 field of format3 insns.  */
#define OP(x)		((unsigned) ((x) & 0x3) << 30) /* Op field of all insns.  */
#define OPF(x)		(((x) & 0x1ff) << 5) /* Opf field of float insns.  */
#define OPF_LOW5(x)	OPF ((x) & 0x1f)     /* V9.  */
#define OPF_LOW4(x)	OPF ((x) & 0xf)      /* V9.  */
#define F3F(x, y, z)	(OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns.  */
#define F3F4(x, y, z)	(OP (x) | OP3 (y) | OPF_LOW4 (z))
#define F3I(x)		(((x) & 0x1) << 13)  /* Immediate field of format 3 insns.  */
#define F2(x, y)	(OP (x) | OP2(y))    /* Format 2 insns.  */
#define F3(x, y, z)	(OP (x) | OP3(y) | F3I(z)) /* Format3 insns.  */
#define F1(x)		(OP (x))
#define DISP30(x)	((x) & 0x3fffffff)
#define ASI(x)		(((x) & 0xff) << 5)  /* Asi field of format3 insns.  */
#define RS2(x)		((x) & 0x1f)         /* Rs2 field.  */
#define SIMM13(x)	((x) & 0x1fff)       /* Simm13 field.  */
#define RD(x)		(((x) & 0x1f) << 25) /* Destination register field.  */
#define RS1(x)		(((x) & 0x1f) << 14) /* Rs1 field.  */
#define RS3(x)		(((x) & 0x1f) << 9)  /* Rs3 field.  */
#define ASI_RS2(x)	(SIMM13 (x))
#define MEMBAR(x)	((x) & 0x7f)
#define SLCPOP(x)	(((x) & 0x7f) << 6)  /* Sparclet cpop.  */

#define ANNUL	(1 << 29)
#define BPRED	(1 << 19)	/* V9.  */
#define	IMMED	F3I (1)
#define RD_G0	RD (~0)
#define	RS1_G0	RS1 (~0)
#define	RS2_G0	RS2 (~0)

extern const struct sparc_opcode sparc_opcodes[];
extern const int sparc_num_opcodes;

extern int sparc_encode_asi (const char *);
extern const char *sparc_decode_asi (int);
extern int sparc_encode_membar (const char *);
extern const char *sparc_decode_membar (int);
extern int sparc_encode_prefetch (const char *);
extern const char *sparc_decode_prefetch (int);
extern int sparc_encode_sparclet_cpreg (const char *);
extern const char *sparc_decode_sparclet_cpreg (int);

/* Local Variables:
   fill-column: 131
   comment-column: 0
   End: */
Commit	Line	Data
252b5132	1	/* Definitions for opcode table for the sparc.
6f2750fe	2	Copyright (C) 1989-2016 Free Software Foundation, Inc.
252b5132	3
47b0e7ad NC	4	This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
47b0e7ad NC	5	the GNU Binutils.
252b5132	6
47b0e7ad NC	7	GAS/GDB is free software; you can redistribute it and/or modify
47b0e7ad NC	8	it under the terms of the GNU General Public License as published by
e4e42b45	9	the Free Software Foundation; either version 3, or (at your option)
47b0e7ad	10	any later version.
252b5132	11
47b0e7ad NC	12	GAS/GDB is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
252b5132	16
47b0e7ad	17	You should have received a copy of the GNU General Public License
e4e42b45	18	along with GAS or GDB; see the file COPYING3. If not, write to
47b0e7ad NC	19	the Free Software Foundation, 51 Franklin Street - Fifth Floor,
47b0e7ad NC	20	Boston, MA 02110-1301, USA. */
252b5132	21
b3f7d5fd	22	#include "ansidecl.h"
252b5132 RH	23
	24	/* The SPARC opcode table (and other related data) is defined in
	25	the opcodes library in sparc-opc.c. If you change anything here, make
	26	sure you fix up that file, and vice versa. */
	27
	28	/* FIXME-someday: perhaps the ,a's and such should be embedded in the
	29	instruction's name rather than the args. This would make gas faster, pinsn
	30	slower, but would mess up some macros a bit. xoxorich. */
	31
	32	/* List of instruction sets variations.
	33	These values are such that each element is either a superset of a
	34	preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
	35	returns non-zero.
	36	The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
	37	Don't change this without updating sparc-opc.c. */
	38
47b0e7ad NC	39	enum sparc_opcode_arch_val
47b0e7ad NC	40	{
252b5132 RH	41	SPARC_OPCODE_ARCH_V6 = 0,
	42	SPARC_OPCODE_ARCH_V7,
	43	SPARC_OPCODE_ARCH_V8,
d6787ef9	44	SPARC_OPCODE_ARCH_LEON,
252b5132 RH	45	SPARC_OPCODE_ARCH_SPARCLET,
252b5132 RH	46	SPARC_OPCODE_ARCH_SPARCLITE,
47b0e7ad	47	/* V9 variants must appear last. */
252b5132	48	SPARC_OPCODE_ARCH_V9,
47b0e7ad NC	49	SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */
	50	SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */
	51	SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */
252b5132 RH	52	};
	53
	54	/* The highest architecture in the table. */
	55	#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
	56
	57	/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
	58	insn encoding/decoding. */
	59	#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
	60
	61	/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
	62	#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
	63
	64	/* Table of cpu variants. */
	65
47b0e7ad NC	66	typedef struct sparc_opcode_arch
47b0e7ad NC	67	{
252b5132 RH	68	const char *name;
	69	/* Mask of sparc_opcode_arch_val's supported.
	70	EG: For v7 this would be
	71	(SPARC_OPCODE_ARCH_MASK (..._V6) \| SPARC_OPCODE_ARCH_MASK (..._V7)).
	72	These are short's because sparc_opcode.architecture is. */
	73	short supported;
47b0e7ad	74	} sparc_opcode_arch;
252b5132 RH	75
	76	extern const struct sparc_opcode_arch sparc_opcode_archs[];
	77
	78	/* Given architecture name, look up it's sparc_opcode_arch_val value. */
8cf3f354	79	extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *);
252b5132 RH	80
	81	/* Return the bitmask of supported architectures for ARCH. */
	82	#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
	83
	84	/* Non-zero if ARCH1 conflicts with ARCH2.
	85	IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
	86	#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
47b0e7ad NC	87	(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
	88	!= SPARC_OPCODE_SUPPORTED (ARCH1)) \
	89	&& ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
252b5132 RH	90	!= SPARC_OPCODE_SUPPORTED (ARCH2)))
	91
	92	/* Structure of an opcode table entry. */
	93
47b0e7ad NC	94	typedef struct sparc_opcode
47b0e7ad NC	95	{
252b5132	96	const char *name;
47b0e7ad NC	97	unsigned long match; /* Bits that must be set. */
47b0e7ad NC	98	unsigned long lose; /* Bits that must not be set. */
252b5132	99	const char *args;
47b0e7ad	100	/* This was called "delayed" in versions before the flags. */
9e8c70f9	101	unsigned int flags;
ec668d69	102	unsigned int hwcaps;
3d68f91c	103	unsigned int hwcaps2;
252b5132	104	short architecture; /* Bitmask of sparc_opcode_arch_val's. */
47b0e7ad NC	105	} sparc_opcode;
47b0e7ad NC	106
252b5132	107	/* FIXME: Add F_ANACHRONISTIC flag for v9. */
9e8c70f9 DM	108	#define F_DELAYED 0x00000001 /* Delayed branch. */
	109	#define F_ALIAS 0x00000002 /* Alias for a "real" instruction. */
	110	#define F_UNBR 0x00000004 /* Unconditional branch. */
	111	#define F_CONDBR 0x00000008 /* Conditional branch. */
	112	#define F_JSR 0x00000010 /* Subroutine call. */
	113	#define F_FLOAT 0x00000020 /* Floating point instruction (not a branch). */
	114	#define F_FBR 0x00000040 /* Floating point branch. */
0afd1215 DM	115	#define F_PREFERRED 0x00000080 /* A preferred alias. */
	116
	117	#define F_PREF_ALIAS (F_ALIAS\|F_PREFERRED)
ec668d69	118
3d68f91c JM	119	/* These must match the ELF_SPARC_HWCAP_* and ELF_SPARC_HWCAP2_*
3d68f91c JM	120	values precisely. See include/elf/sparc.h. */
ec668d69 DM	121	#define HWCAP_MUL32 0x00000001 /* umul/umulcc/smul/smulcc insns */
	122	#define HWCAP_DIV32 0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
	123	#define HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */
	124	#define HWCAP_V8PLUS 0x00000008 /* v9 insns available to 32bit */
	125	#define HWCAP_POPC 0x00000010 /* 'popc' insn */
	126	#define HWCAP_VIS 0x00000020 /* VIS insns */
	127	#define HWCAP_VIS2 0x00000040 /* VIS2 insns */
	128	#define HWCAP_ASI_BLK_INIT \
	129	0x00000080 /* block init ASIs */
	130	#define HWCAP_FMAF 0x00000100 /* fused multiply-add */
	131	#define HWCAP_VIS3 0x00000400 /* VIS3 insns */
	132	#define HWCAP_HPC 0x00000800 /* HPC insns */
	133	#define HWCAP_RANDOM 0x00001000 /* 'random' insn */
	134	#define HWCAP_TRANS 0x00002000 /* transaction insns */
	135	#define HWCAP_FJFMAU 0x00004000 /* unfused multiply-add */
	136	#define HWCAP_IMA 0x00008000 /* integer multiply-add */
	137	#define HWCAP_ASI_CACHE_SPARING \
	138	0x00010000 /* cache sparing ASIs */
	139	#define HWCAP_AES 0x00020000 /* AES crypto insns */
	140	#define HWCAP_DES 0x00040000 /* DES crypto insns */
	141	#define HWCAP_KASUMI 0x00080000 /* KASUMI crypto insns */
	142	#define HWCAP_CAMELLIA 0x00100000 /* CAMELLIA crypto insns */
	143	#define HWCAP_MD5 0x00200000 /* MD5 hashing insns */
	144	#define HWCAP_SHA1 0x00400000 /* SHA1 hashing insns */
	145	#define HWCAP_SHA256 0x00800000 /* SHA256 hashing insns */
	146	#define HWCAP_SHA512 0x01000000 /* SHA512 hashing insns */
	147	#define HWCAP_MPMUL 0x02000000 /* Multiple Precision Multiply */
	148	#define HWCAP_MONT 0x04000000 /* Montgomery Mult/Sqrt */
	149	#define HWCAP_PAUSE 0x08000000 /* Pause insn */
	150	#define HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */
	151	#define HWCAP_CRC32C 0x20000000 /* CRC32C insn */
252b5132	152
3d68f91c	153	#define HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */
0b6be415	154	#define HWCAP2_VIS3B 0x00000002 /* Subset of VIS3 present on sparc64 X+. */
3d68f91c JM	155	#define HWCAP2_ADP 0x00000004 /* Application Data Protection */
	156	#define HWCAP2_SPARC5 0x00000008 /* The 29 new fp and sub instructions */
	157	#define HWCAP2_MWAIT 0x00000010 /* mwait instruction and load/monitor ASIs */
	158	#define HWCAP2_XMPMUL 0x00000020 /* XOR multiple precision multiply */
	159	#define HWCAP2_XMONT 0x00000040 /* XOR Montgomery mult/sqr instructions */
	160	#define HWCAP2_NSEC \
	161	0x00000080 /* pause insn with support for nsec timings */
	162	#define HWCAP2_FJATHHPC 0x00001000 /* Fujitsu HPC instrs */
	163	#define HWCAP2_FJDES 0x00002000 /* Fujitsu DES instrs */
	164	#define HWCAP2_FJAES 0x00010000 /* Fujitsu AES instrs */
	165
	166
47b0e7ad NC	167	/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
47b0e7ad NC	168	macro), which is 64 bits. It is handled as a special case.
252b5132	169
47b0e7ad NC	170	The match component is a mask saying which bits must match a particular
47b0e7ad NC	171	opcode in order for an instruction to be an instance of that opcode.
252b5132	172
47b0e7ad NC	173	The args component is a string containing one character for each operand of the
47b0e7ad NC	174	instruction.
252b5132	175
47b0e7ad	176	Kinds of operands:
252b5132 RH	177	# Number used by optimizer. It is ignored.
	178	1 rs1 register.
	179	2 rs2 register.
	180	d rd register.
	181	e frs1 floating point register.
	182	v frs1 floating point register (double/even).
	183	V frs1 floating point register (quad/multiple of 4).
	184	f frs2 floating point register.
	185	B frs2 floating point register (double/even).
	186	R frs2 floating point register (quad/multiple of 4).
ea783ef3 DM	187	4 frs3 floating point register.
ea783ef3 DM	188	5 frs3 floating point register (doube/even).
252b5132 RH	189	g frsd floating point register.
	190	H frsd floating point register (double/even).
	191	J frsd floating point register (quad/multiple of 4).
3d68f91c	192	} frsd floating point register (double/even) that is == frs2
252b5132 RH	193	b crs1 coprocessor register
	194	c crs2 coprocessor register
	195	D crsd coprocessor register
	196	m alternate space register (asr) in rd
	197	M alternate space register (asr) in rs1
	198	h 22 high bits.
	199	X 5 bit unsigned immediate
	200	Y 6 bit unsigned immediate
19f7b010	201	3 SIAM mode (3 bits). (v9b)
252b5132 RH	202	K MEMBAR mask (7 bits). (v9)
	203	j 10 bit Immediate. (v9)
	204	I 11 bit Immediate. (v9)
	205	i 13 bit Immediate.
	206	n 22 bit immediate.
	207	k 2+14 bit PC relative immediate. (v9)
	208	G 19 bit PC relative immediate. (v9)
	209	l 22 bit PC relative immediate.
	210	L 30 bit PC relative immediate.
	211	a Annul. The annul bit is set.
	212	A Alternate address space. Stored as 8 bits.
	213	C Coprocessor state register.
	214	F floating point state register.
	215	p Processor state register.
	216	N Branch predict clear ",pn" (v9)
	217	T Branch predict set ",pt" (v9)
	218	z %icc. (v9)
	219	Z %xcc. (v9)
	220	q Floating point queue.
	221	r Single register that is both rs1 and rd.
	222	O Single register that is both rs2 and rd.
	223	Q Coprocessor queue.
	224	S Special case.
	225	t Trap base register.
	226	w Window invalid mask register.
	227	y Y register.
	228	u sparclet coprocessor registers in rd position
	229	U sparclet coprocessor registers in rs1 position
	230	E %ccr. (v9)
	231	s %fprs. (v9)
	232	P %pc. (v9)
	233	W %tick. (v9)
3d68f91c	234	{ %mcdper. (v9b)
252b5132 RH	235	o %asi. (v9)
	236	6 %fcc0. (v9)
	237	7 %fcc1. (v9)
	238	8 %fcc2. (v9)
	239	9 %fcc3. (v9)
	240	! Privileged Register in rd (v9)
	241	? Privileged Register in rs1 (v9)
	242	* Prefetch function constant. (v9)
	243	x OPF field (v9 impdep).
	244	0 32/64 bit immediate for set or setx (v9) insns
	245	_ Ancillary state register in rd (v9a)
	246	/ Ancillary state register in rs1 (v9a)
2615994e	247	( entire floating point state register (%efsr)
6cda1326	248	) 5 bit immediate placed in RS3 field
2615994e	249	= 2+8 bit PC relative immediate. (v9) */
47b0e7ad NC	250
	251	#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
	252	#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
	253	#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */
	254	#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
	255	#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
ea783ef3	256	#define OPF_LOW4(x) OPF ((x) & 0xf) /* V9. */
47b0e7ad	257	#define F3F(x, y, z) (OP (x) \| OP3 (y) \| OPF (z)) /* Format3 float insns. */
2c63854f	258	#define F3F4(x, y, z) (OP (x) \| OP3 (y) \| OPF_LOW4 (z))
47b0e7ad NC	259	#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
	260	#define F2(x, y) (OP (x) \| OP2(y)) /* Format 2 insns. */
	261	#define F3(x, y, z) (OP (x) \| OP3(y) \| F3I(z)) /* Format3 insns. */
	262	#define F1(x) (OP (x))
	263	#define DISP30(x) ((x) & 0x3fffffff)
	264	#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */
	265	#define RS2(x) ((x) & 0x1f) /* Rs2 field. */
	266	#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */
	267	#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */
	268	#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
ea783ef3	269	#define RS3(x) (((x) & 0x1f) << 9) /* Rs3 field. */
47b0e7ad NC	270	#define ASI_RS2(x) (SIMM13 (x))
	271	#define MEMBAR(x) ((x) & 0x7f)
	272	#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */
	273
	274	#define ANNUL (1 << 29)
	275	#define BPRED (1 << 19) /* V9. */
	276	#define IMMED F3I (1)
	277	#define RD_G0 RD (~0)
	278	#define RS1_G0 RS1 (~0)
	279	#define RS2_G0 RS2 (~0)
252b5132 RH	280
	281	extern const struct sparc_opcode sparc_opcodes[];
	282	extern const int sparc_num_opcodes;
	283
8cf3f354 AM	284	extern int sparc_encode_asi (const char *);
	285	extern const char *sparc_decode_asi (int);
	286	extern int sparc_encode_membar (const char *);
	287	extern const char *sparc_decode_membar (int);
	288	extern int sparc_encode_prefetch (const char *);
	289	extern const char *sparc_decode_prefetch (int);
	290	extern int sparc_encode_sparclet_cpreg (const char *);
	291	extern const char *sparc_decode_sparclet_cpreg (int);
252b5132	292
47b0e7ad NC	293	/* Local Variables:
	294	fill-column: 131
	295	comment-column: 0
	296	End: */
252b5132	297