[thirdparty/binutils-gdb.git] / include / opcode / v850.h

/* v850.h -- Header file for NEC V850 opcode table
   Copyright 1996 Free Software Foundation, Inc.
   Written by J.T. Conklin, Cygnus Support

This file is part of GDB, GAS, and the GNU binutils.

GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
1, or (at your option) any later version.

GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
the GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this file; see the file COPYING.  If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#ifndef V850_H
#define V850_H

/* The opcode table is an array of struct v850_opcode.  */

struct v850_opcode
{
  /* The opcode name.  */
  const char *name;

  /* The opcode itself.  Those bits which will be filled in with
     operands are zeroes.  */
  unsigned long opcode;

  /* The opcode mask.  This is used by the disassembler.  This is a
     mask containing ones indicating those bits which must match the
     opcode field, and zeroes indicating those bits which need not
     match (and are presumably filled in by operands).  */
  unsigned long mask;

  /* An array of operand codes.  Each code is an index into the
     operand table.  They appear in the order which the operands must
     appear in assembly code, and are terminated by a zero.  */
  unsigned char operands[8];

  /* Which (if any) operand is a memory operand.  */
  unsigned int memop;

  /* Target processor(s).  A bit field of processors which support
     this instruction.  Note a bit field is used as some instructions
     are available on multiple, different processor types, whereas
     other instructions are only available on one specific type.  */
  unsigned int processors;
};

/* Values for the processors field in the v850_opcode structure.  */
#define PROCESSOR_V850		(1 << 0)		/* Just the V850.  */
#define PROCESSOR_ALL		-1			/* Any processor.  */
/* start-sanitize-v850e */
#define PROCESSOR_V850E		(1 << 1)		/* Just the V850E. */
#define PROCESSOR_NOT_V850	(~ PROCESSOR_V850)	/* Any processor except the V850.  */
/* end-sanitize-v850e */
/* start-sanitize-v850eq */
#define PROCESSOR_V850EQ	(1 << 2)		/* Just the V850EQ. */
/* end-sanitize-v850eq */

/* The table itself is sorted by major opcode number, and is otherwise
   in the order in which the disassembler should consider
   instructions.  */
extern const struct v850_opcode v850_opcodes[];
extern const int v850_num_opcodes;

\f
/* The operands table is an array of struct v850_operand.  */

struct v850_operand
{
  /* The number of bits in the operand.  */
  /* If this value is -1 then the operand's bits are in a discontinous distribution in the instruction. */
  int bits;

  /* (bits >= 0):  How far the operand is left shifted in the instruction.  */
  /* (bits == -1): Bit mask of the bits in the operand.  */
  int shift;

  /* Insertion function.  This is used by the assembler.  To insert an
     operand value into an instruction, check this field.

     If it is NULL, execute
         i |= (op & ((1 << o->bits) - 1)) << o->shift;
     (i is the instruction which we are filling in, o is a pointer to
     this structure, and op is the opcode value; this assumes twos
     complement arithmetic).

     If this field is not NULL, then simply call it with the
     instruction and the operand value.  It will return the new value
     of the instruction.  If the ERRMSG argument is not NULL, then if
     the operand value is illegal, *ERRMSG will be set to a warning
     string (the operand will be inserted in any case).  If the
     operand value is legal, *ERRMSG will be unchanged (most operands
     can accept any value).  */
  unsigned long (* insert) PARAMS ((unsigned long instruction, long op,
				   const char ** errmsg));

  /* Extraction function.  This is used by the disassembler.  To
     extract this operand type from an instruction, check this field.

     If it is NULL, compute
         op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1);
	 if (o->flags & V850_OPERAND_SIGNED)
	     op = (op << (32 - o->bits)) >> (32 - o->bits);
     (i is the instruction, o is a pointer to this structure, and op
     is the result; this assumes twos complement arithmetic).

     If this field is not NULL, then simply call it with the
     instruction value.  It will return the value of the operand.  If
     the INVALID argument is not NULL, *INVALID will be set to
     non-zero if this operand type can not actually be extracted from
     this operand (i.e., the instruction does not match).  If the
     operand is valid, *INVALID will not be changed.  */
  unsigned long (* extract) PARAMS ((unsigned long instruction, int * invalid));

  /* One bit syntax flags.  */
  int flags;
};

/* Elements in the table are retrieved by indexing with values from
   the operands field of the v850_opcodes table.  */

extern const struct v850_operand v850_operands[];

/* Values defined for the flags field of a struct v850_operand.  */

/* This operand names a general purpose register */
#define V850_OPERAND_REG	0x01

/* This operand names a system register */
#define V850_OPERAND_SRG	0x02

/* This operand names a condition code used in the setf instruction */
#define V850_OPERAND_CC		0x04

/* This operand takes signed values */
#define V850_OPERAND_SIGNED	0x08

/* This operand is the ep register.  */
#define V850_OPERAND_EP		0x10

/* This operand is a PC displacement */
#define V850_OPERAND_DISP	0x20

/* This is a relaxable operand.   Only used for D9->D22 branch relaxing
   right now.  We may need others in the future (or maybe handle them like
   promoted operands on the mn10300?)  */
#define V850_OPERAND_RELAX	0x40

/* The register specified must not be r0 */
#define V850_NOT_R0	        0x80

/* start-sanitize-v850e */
/* push/pop type instruction, V850E specific.  */
#define V850E_PUSH_POP		0x100

/* 16 bit immediate follows instruction, V850E specific.  */
#define V850E_IMMEDIATE16	0x200

/* 32 bit immediate follows instruction, V850E specific.  */
#define V850E_IMMEDIATE32	0x400
/* end-sanitize-v850e */

#endif /* V850_H */
Commit	Line	Data
7a3c9336 C	1	/* v850.h -- Header file for NEC V850 opcode table
	2	Copyright 1996 Free Software Foundation, Inc.
	3	Written by J.T. Conklin, Cygnus Support
	4
	5	This file is part of GDB, GAS, and the GNU binutils.
	6
	7	GDB, GAS, and the GNU binutils are free software; you can redistribute
	8	them and/or modify them under the terms of the GNU General Public
	9	License as published by the Free Software Foundation; either version
	10	1, or (at your option) any later version.
	11
	12	GDB, GAS, and the GNU binutils are distributed in the hope that they
	13	will be useful, but WITHOUT ANY WARRANTY; without even the implied
	14	warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
	15	the GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this file; see the file COPYING. If not, write to the Free
	19	Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	20
	21	#ifndef V850_H
	22	#define V850_H
	23
	24	/* The opcode table is an array of struct v850_opcode. */
	25
	26	struct v850_opcode
	27	{
	28	/* The opcode name. */
	29	const char *name;
	30
	31	/* The opcode itself. Those bits which will be filled in with
	32	operands are zeroes. */
	33	unsigned long opcode;
	34
	35	/* The opcode mask. This is used by the disassembler. This is a
	36	mask containing ones indicating those bits which must match the
	37	opcode field, and zeroes indicating those bits which need not
	38	match (and are presumably filled in by operands). */
	39	unsigned long mask;
	40
	41	/* An array of operand codes. Each code is an index into the
	42	operand table. They appear in the order which the operands must
	43	appear in assembly code, and are terminated by a zero. */
	44	unsigned char operands[8];
7e3670d6 FF	45
	46	/* Which (if any) operand is a memory operand. */
	47	unsigned int memop;
92297195 NC	48
	49	/* Target processor(s). A bit field of processors which support
	50	this instruction. Note a bit field is used as some instructions
	51	are available on multiple, different processor types, whereas
	52	other instructions are only available on one specific type. */
	53	unsigned int processors;
7a3c9336 C	54	};
7a3c9336 C	55
92297195 NC	56	/* Values for the processors field in the v850_opcode structure. */
	57	#define PROCESSOR_V850 (1 << 0) /* Just the V850. */
	58	#define PROCESSOR_ALL -1 /* Any processor. */
	59	/* start-sanitize-v850e */
	60	#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */
	61	#define PROCESSOR_NOT_V850 (~ PROCESSOR_V850) /* Any processor except the V850. */
	62	/* end-sanitize-v850e */
	63	/* start-sanitize-v850eq */
	64	#define PROCESSOR_V850EQ (1 << 2) /* Just the V850EQ. */
3e906c08	65	/* end-sanitize-v850eq */
92297195	66
7a3c9336 C	67	/* The table itself is sorted by major opcode number, and is otherwise
	68	in the order in which the disassembler should consider
	69	instructions. */
	70	extern const struct v850_opcode v850_opcodes[];
	71	extern const int v850_num_opcodes;
	72
	73	\f
7e3670d6	74	/* The operands table is an array of struct v850_operand. */
7a3c9336 C	75
	76	struct v850_operand
	77	{
	78	/* The number of bits in the operand. */
b9792954	79	/* If this value is -1 then the operand's bits are in a discontinous distribution in the instruction. */
7a3c9336 C	80	int bits;
7a3c9336 C	81
b9792954 NC	82	/* (bits >= 0): How far the operand is left shifted in the instruction. */
b9792954 NC	83	/* (bits == -1): Bit mask of the bits in the operand. */
7a3c9336	84	int shift;
dd528aff	85
27021dd4 C	86	/* Insertion function. This is used by the assembler. To insert an
	87	operand value into an instruction, check this field.
	88
	89	If it is NULL, execute
	90	i \|= (op & ((1 << o->bits) - 1)) << o->shift;
	91	(i is the instruction which we are filling in, o is a pointer to
	92	this structure, and op is the opcode value; this assumes twos
	93	complement arithmetic).
	94
	95	If this field is not NULL, then simply call it with the
	96	instruction and the operand value. It will return the new value
	97	of the instruction. If the ERRMSG argument is not NULL, then if
	98	the operand value is illegal, *ERRMSG will be set to a warning
	99	string (the operand will be inserted in any case). If the
	100	operand value is legal, *ERRMSG will be unchanged (most operands
	101	can accept any value). */
b9792954 NC	102	unsigned long (* insert) PARAMS ((unsigned long instruction, long op,
b9792954 NC	103	const char ** errmsg));
27021dd4 C	104
	105	/* Extraction function. This is used by the disassembler. To
	106	extract this operand type from an instruction, check this field.
	107
	108	If it is NULL, compute
b9792954 NC	109	op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1);
	110	if (o->flags & V850_OPERAND_SIGNED)
	111	op = (op << (32 - o->bits)) >> (32 - o->bits);
27021dd4 C	112	(i is the instruction, o is a pointer to this structure, and op
	113	is the result; this assumes twos complement arithmetic).
	114
	115	If this field is not NULL, then simply call it with the
	116	instruction value. It will return the value of the operand. If
	117	the INVALID argument is not NULL, *INVALID will be set to
	118	non-zero if this operand type can not actually be extracted from
	119	this operand (i.e., the instruction does not match). If the
	120	operand is valid, INVALID will not be changed. /
b9792954	121	unsigned long (* extract) PARAMS ((unsigned long instruction, int * invalid));
27021dd4 C	122
27021dd4 C	123	/* One bit syntax flags. */
dd528aff	124	int flags;
7a3c9336 C	125	};
	126
	127	/* Elements in the table are retrieved by indexing with values from
	128	the operands field of the v850_opcodes table. */
	129
	130	extern const struct v850_operand v850_operands[];
	131
dd528aff	132	/* Values defined for the flags field of a struct v850_operand. */
dd528aff	133
27021dd4 C	134	/* This operand names a general purpose register */
27021dd4 C	135	#define V850_OPERAND_REG 0x01
dd528aff	136
27021dd4 C	137	/* This operand names a system register */
	138	#define V850_OPERAND_SRG 0x02
	139
	140	/* This operand names a condition code used in the setf instruction */
	141	#define V850_OPERAND_CC 0x04
	142
	143	/* This operand takes signed values */
	144	#define V850_OPERAND_SIGNED 0x08
7a3c9336	145
7e3670d6 FF	146	/* This operand is the ep register. */
	147	#define V850_OPERAND_EP 0x10
	148
	149	/* This operand is a PC displacement */
	150	#define V850_OPERAND_DISP 0x20
	151
	152	/* This is a relaxable operand. Only used for D9->D22 branch relaxing
	153	right now. We may need others in the future (or maybe handle them like
	154	promoted operands on the mn10300?) */
	155	#define V850_OPERAND_RELAX 0x40
	156
b9792954	157	/* The register specified must not be r0 */
1f5595a6	158	#define V850_NOT_R0 0x80
b9792954 NC	159
	160	/* start-sanitize-v850e */
	161	/* push/pop type instruction, V850E specific. */
1f5595a6	162	#define V850E_PUSH_POP 0x100
b9792954 NC	163
b9792954 NC	164	/* 16 bit immediate follows instruction, V850E specific. */
1f5595a6	165	#define V850E_IMMEDIATE16 0x200
b9792954 NC	166
b9792954 NC	167	/* 32 bit immediate follows instruction, V850E specific. */
1f5595a6	168	#define V850E_IMMEDIATE32 0x400
b9792954 NC	169	/* end-sanitize-v850e */
b9792954 NC	170
7a3c9336	171	#endif /* V850_H */