[thirdparty/binutils-gdb.git] / include / opcode / visium.h

/* Opcode table header for Visium.

   Copyright (C) 2003-2021 Free Software Foundation, Inc.

   This file is part of GDB, GAS, and GNU binutils.

   GDB, GAS and the GNU binutils are free software; you can redistribute
   them and/or modify them under the terms of the GNU General Public
   License as published by the Free Software Foundation; either version 3,
   or (at your option) any later version.

   GDB, GAS, and the GNU binutils are distributed in the hope that they
   will be useful, but WITHOUT ANY WARRANTY; without even the implied
   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
   the GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this file; see the file COPYING3.  If not, write to the Free
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

enum visium_opcode_arch_val
{
  VISIUM_OPCODE_ARCH_DEF = 0,
  VISIUM_OPCODE_ARCH_GR5,
  VISIUM_OPCODE_ARCH_GR6,
  VISIUM_OPCODE_ARCH_BAD
};

/* The highest architecture in the table.  */
#define VISIUM_OPCODE_ARCH_MAX (VISIUM_OPCODE_ARCH_BAD - 1)

/* Given an enum visium_opcode_arch_val, return the bitmask to use in
   insn encoding/decoding.  */
#define VISIUM_OPCODE_ARCH_MASK(arch) (1 << (arch))

/* Some defines to make life easy.  */
#define MASK_DEF VISIUM_OPCODE_ARCH_MASK (VISIUM_OPCODE_ARCH_DEF)
#define MASK_GR5 VISIUM_OPCODE_ARCH_MASK (VISIUM_OPCODE_ARCH_GR5)
#define MASK_GR6 VISIUM_OPCODE_ARCH_MASK (VISIUM_OPCODE_ARCH_GR6)

/* Bit masks of architectures supporting the insn.  */
#define def (MASK_DEF | MASK_GR5 | MASK_GR6)
#define gr5 (MASK_GR5 | MASK_GR6)
#define gr6 (MASK_GR6)

/* The condition code field is not used (zero) for most instructions.
   BRR and BRA make normal use of it. Floating point instructions use
   it as a sub-opcode.  */
#define CC_MASK (0xf << 27)

/* It seems a shame not to use these bits in a class 0 instruction,
   since they could be used to extend the range of the branch.  */
#define CLASS0_UNUSED_MASK (0x1f << 16)

/* For class 1 instructions the following bit is unused.  */
#define CLASS1_UNUSED_MASK (1 << 9)

/* For class 1 instructions this field gives the index for a write
   instruction, the specific operation for an EAM instruction, or
   the floating point destination register for a floating point
   instruction.  */
#define CLASS1_INDEX_MASK (0x1f << 10)

/* For class 3 instructions the following field gives the destination
   general register.  */
#define CLASS3_DEST_MASK (0x1f << 10)

/* For class 1 and class 3 instructions the following bit selects an
   EAM write/read rather than a memory write/read.  */
#define EAM_SELECT_MASK (1 << 15)

/* Floating point instructions are distinguished from general EAM
   instructions by the following bit.  */
#define FP_SELECT_MASK (1 << 3)

/* For both class 1 and class 3 the following fields give, where
   appropriate the srcA and srcB registers whether floating point
   or general.  */
#define SRCA_MASK (0x1f << 16)
#define SRCB_MASK (0x1f << 4)

/* The class 3 interrupt bit. It turns a BRA into a SYS1, and an
   RFLAG into a SYS2. This bit should not be set in the user's
   class 3 instructions. This bit is also used in class 3
   to distinguish between floating point and other EAM operations.
   (see FP_SELECT_MASK).  */
#define CLASS3_INT (1 << 3)

/* Class 3 shift instructions use this bit to indicate that the
   srcB field is a 5 bit immediate shift count rather than a
   register number.  */
#define CLASS3_SOURCEB_IMMED (1 << 9)

#define BMD 0x02630004
#define BMI 0x82230004
#define DSI 0x82800004
#define ENI 0x02a00004
#define RFI 0x82fe01d4

struct reg_entry
{
  const char *name;
  unsigned char code;
};

static const struct reg_entry gen_reg_table[] ATTRIBUTE_UNUSED =
{
  {"fp", 0x16},
  {"r0", 0x0},
  {"r1", 0x1},
  {"r10", 0xA},
  {"r11", 0xB},
  {"r12", 0xC},
  {"r13", 0xD},
  {"r14", 0xE},
  {"r15", 0xF},
  {"r16", 0x10},
  {"r17", 0x11},
  {"r18", 0x12},
  {"r19", 0x13},
  {"r2", 0x2},
  {"r20", 0x14},
  {"r21", 0x15},
  {"r22", 0x16},
  {"r23", 0x17},
  {"r24", 0x18},
  {"r25", 0x19},
  {"r26", 0x1a},
  {"r27", 0x1b},
  {"r28", 0x1c},
  {"r29", 0x1d},
  {"r3", 0x3},
  {"r30", 0x1e},
  {"r31", 0x1f},
  {"r4", 0x4},
  {"r5", 0x5},
  {"r6", 0x6},
  {"r7", 0x7},
  {"r8", 0x8},
  {"r9", 0x9},
  {"sp", 0x17},
};

static const struct reg_entry fp_reg_table[] ATTRIBUTE_UNUSED =
{
  {"f0", 0x0},
  {"f1", 0x1},
  {"f10", 0xa},
  {"f11", 0xb},
  {"f12", 0xc},
  {"f13", 0xd},
  {"f14", 0xe},
  {"f15", 0xf},
  {"f2", 0x2},
  {"f3", 0x3},
  {"f4", 0x4},
  {"f5", 0x5},
  {"f6", 0x6},
  {"f7", 0x7},
  {"f8", 0x8},
  {"f9", 0x9},
};

static const struct cc_entry
{
  const char *name;
  int code;
} cc_table [] ATTRIBUTE_UNUSED =
{
  {"cc", 6},
  {"cs", 2},
  {"eq", 1},
  {"fa", 0},
  {"ge", 9},
  {"gt", 10},
  {"hi", 11},
  {"le", 12},
  {"ls", 13},
  {"lt", 14},
  {"nc", 8},
  {"ne", 5},
  {"ns", 4},
  {"oc", 7},
  {"os", 3},
  {"tr", 15},
};

enum addressing_mode
{
  mode_d,	/* register := */
  mode_a,	/* op= register */
  mode_da,	/* register := register */
  mode_ab,	/* register * register */
  mode_dab,	/* register := register * register */
  mode_iab,	/* 5-bit immediate * register * register */
  mode_0ab,	/* zero * register * register */
  mode_da0,	/* register := register * zero */
  mode_cad,	/* condition * register * register */
  mode_das,	/* register := register * 5-bit immed/register shift count */
  mode_di,	/* register := 5-bit immediate */
  mode_ir,	/* 5-bit immediate * register */
  mode_ai,	/* register 16-bit unsigned immediate */
  mode_i,	/* 16-bit unsigned immediate */
  mode_bax,	/* register * register * 5-bit immediate */
  mode_dax,	/* register := register * 5-bit immediate */
  mode_s,	/* special mode */
  mode_sr,	/* special mode with register */
  mode_ci,	/* condition * 16-bit signed word displacement */
  mode_fdab,	/* float := float * float */
  mode_ifdab,	/* fpinst: 4-bit immediate * float * float * float */
  mode_idfab,	/* fpuread: 4-bit immediate * register * float * float */
  mode_fda,	/* float := float */
  mode_fdra,	/* float := register */
  mode_rdfab,	/* register := float * float */
  mode_rdfa,	/* register := float */
  mode_rrr,	/* 3 register sources and destinations (block move) */
};

#define class0 (0<<25)
#define class1 (1<<25)
#define class2 (2<<25)
#define class3 (3<<25)

static const struct opcode_entry
{
  const char *mnem;
  enum addressing_mode mode;
  unsigned code;
  char flags;
}
opcode_table[] ATTRIBUTE_UNUSED =
{
  { "adc.b",    mode_dab,  class3|(1<<21)|(1), def },
  { "adc.l",    mode_dab,  class3|(1<<21)|(4), def },
  { "adc.w",    mode_dab,  class3|(1<<21)|(2), def },
  { "add.b",    mode_dab,  class3|(0<<21)|(1), def },
  { "add.l",    mode_dab,  class3|(0<<21)|(4), def },
  { "add.w",    mode_dab,  class3|(0<<21)|(2), def },
  { "addi",     mode_ai,   class2, def },
  { "and.b",    mode_dab,  class3|(10<<21)|(1), def},
  { "and.l",    mode_dab,  class3|(10<<21)|(4), def },
  { "and.w",    mode_dab,  class3|(10<<21)|(2), def },
  { "asl.b",    mode_das,  class3|(7<<21)|(1), def },
  { "asl.l",    mode_das,  class3|(7<<21)|(4), def },
  { "asl.w",    mode_das,  class3|(7<<21)|(2), def },
  { "asld",     mode_a,    class1|(15<<21)|(1<<15)|(11<<10)|(4), def },
  { "asr.b",    mode_das,  class3|(5<<21)|(1), def },
  { "asr.l",    mode_das,  class3|(5<<21)|(4), def },
  { "asr.w",    mode_das,  class3|(5<<21)|(2), def },
  { "asrd",     mode_a,    class1|(15<<21)|(1<<15)|(9<<10)|(4), def },
  { "bmd",      mode_rrr,  class1|(3<<21)|(3<<16)|(4), gr6 },
  { "bmi",      mode_rrr,  class1|(1<<21)|(3<<16)|(4), gr6 },
  { "bra",      mode_cad,  class3|(12<<21)|(4), def },
  { "brr",      mode_ci,   class0, def },
  { "cmp.b",    mode_0ab,  class3|(2<<21)|(1), def },
  { "cmp.l",    mode_0ab,  class3|(2<<21)|(4), def },
  { "cmp.w",    mode_0ab,  class3|(2<<21)|(2), def },
  { "cmpc.b",   mode_0ab,  class3|(3<<21)|(1), def },
  { "cmpc.l",   mode_0ab,  class3|(3<<21)|(4), def },
  { "cmpc.w",   mode_0ab,  class3|(3<<21)|(2), def },
  { "divds",    mode_a,    class1|(15<<21)|(1<<15)|(6<<10)|(4), def },
  { "divdu",    mode_a,    class1|(15<<21)|(1<<15)|(7<<10)|(4), def },
  { "divs",     mode_a,    class1|(15<<21)|(1<<15)|(2<<10)|(4), def },
  { "divu",     mode_a,    class1|(15<<21)|(1<<15)|(3<<10)|(4), def },
  { "dsi",      mode_s,    class1|(4<<21)|(4), def },
  { "eamread",  mode_di,   class3|(15<<21)|(1<<15)|(1<<9)|(4), def },
  { "eamwrite", mode_iab,  class1|(15<<21)|(1<<15)|(4), def },
  { "eni",      mode_s,    class1|(5<<21)|(4), def },
  { "extb.b",   mode_da,   class3|(14<<21)|(1), def },
  { "extb.l",   mode_da,   class3|(14<<21)|(4), def },
  { "extb.w",   mode_da,   class3|(14<<21)|(2), def },
  { "extw.l",   mode_da,   class3|(4<<21)|(4), def },
  { "extw.w",   mode_da,   class3|(4<<21)|(2), def },
  { "fabs",     mode_fda,  class1|(7<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
  { "fadd",     mode_fdab, class1|(1<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
  { "fcmp",     mode_rdfab,class3|(10<<27)|(15<<21)|(1<<15)|(1<<9)|(1<<3)|(4), gr5 },
  { "fcmpe",    mode_rdfab,class3|(11<<27)|(15<<21)|(1<<15)|(1<<9)|(1<<3)|(4), gr5 },
  { "fdiv",     mode_fdab, class1|(4<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
  { "fload",    mode_fdra, class1|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
  { "fmove",    mode_fda,  class1|(12<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5},
  { "fmult",    mode_fdab, class1|(3<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
  { "fneg",     mode_fda,  class1|(6<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
  { "fpinst",   mode_ifdab,class1|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
  { "fpuread",  mode_idfab,class3|(15<<21)|(1<<15)|(1<<9)|(1<<3)|(4), gr5 },
  { "fsqrt",    mode_fda,  class1|(5<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
  { "fstore",   mode_rdfa, class3|(15<<21)|(1<<15)|(1<<9)|(1<<3)|(4), gr5 },
  { "fsub",     mode_fdab, class1|(2<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
  { "ftoi",     mode_fda,  class1|(8<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
  { "itof",     mode_fda,  class1|(9<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
  { "lsr.b",    mode_das,  class3|(6<<21)|(1), def },
  { "lsr.l",    mode_das,  class3|(6<<21)|(4), def },
  { "lsr.w",    mode_das,  class3|(6<<21)|(2), def },
  { "lsrd",     mode_a,    class1|(15<<21)|(1<<15)|(10<<10)|(4), def },
  { "move.b",   mode_da0,  class3|(9<<21)|(1), def },
  { "move.l",   mode_da0,  class3|(9<<21)|(4), def },
  { "move.w",   mode_da0,  class3|(9<<21)|(2), def },
  { "movil",    mode_ai,   class2|(4<<21), def },
  { "moviq",    mode_ai,   class2|(6<<21), def },
  { "moviu",    mode_ai,   class2|(5<<21), def },
  { "mults",    mode_ab,   class1|(15<<21)|(1<<15)|(0<<10)|(4), def },
  { "multu",    mode_ab,   class1|(15<<21)|(1<<15)|(1<<10)|(4), def },
  { "nop",      mode_s,    class0, def },
  { "not.b",    mode_da,   class3|(11<<21)|(1), def },
  { "not.l",    mode_da,   class3|(11<<21)|(4), def },
  { "not.w",    mode_da,   class3|(11<<21)|(2), def },
  { "or.b",     mode_dab,  class3|(9<<21)|(1), def },
  { "or.l",     mode_dab,  class3|(9<<21)|(4), def },
  { "or.w",     mode_dab,  class3|(9<<21)|(2), def },
  { "read.b",   mode_dax,  class3|(15<<21)|(1<<9)|(1), def },
  { "read.l",   mode_dax,  class3|(15<<21)|(1<<9)|(4), def },
  { "read.w",   mode_dax,  class3|(15<<21)|(1<<9)|(2), def },
  { "readmda",  mode_d,    class3|(15<<21)|(1<<15)|(1<<9)|(4), def },
  { "readmdb",  mode_d,    class3|(15<<21)|(1<<15)|(1<<9)|(1<<4)|(4), def },
  { "readmdc",  mode_d,    class3|(15<<21)|(1<<15)|(1<<9)|(2<<4)|(4), def },
  { "rfi",      mode_s,    class1|(7<<21)|(30<<16)|(29<<4)|(4), def },
  { "rflag",    mode_d,    class3|(13<<21)|(4), def },
  { "stop",     mode_ir,   class1|(0<<21)|(4), def },
  { "sub.b",    mode_dab,  class3|(2<<21)|(1), def },
  { "sub.l",    mode_dab,  class3|(2<<21)|(4), def },
  { "sub.w",    mode_dab,  class3|(2<<21)|(2), def },
  { "subc.b",   mode_dab,  class3|(3<<21)|(1), def },
  { "subc.l",   mode_dab,  class3|(3<<21)|(4), def },
  { "subc.w",   mode_dab,  class3|(3<<21)|(2), def },
  { "subi",     mode_ai,   class2|(2<<21), def },
  { "trace",    mode_ir,   class1|(13<<21), def },
  { "write.b",  mode_bax,  class1|(15<<21)|(1), def },
  { "write.l",  mode_bax,  class1|(15<<21)|(4), def },
  { "write.w",  mode_bax,  class1|(15<<21)|(2), def },
  { "writemd",  mode_ab,   class1|(15<<21)|(1<<15)|(4<<10)|(4), def },
  { "writemdc", mode_a,    class1|(15<<21)|(1<<15)|(5<<10)|(4), def },
  { "wrtl",     mode_i,    class2|(8<<21), gr6 },
  { "wrtu",     mode_i,    class2|(9<<21), gr6 },
  { "xor.b",    mode_dab,  class3|(8<<21)|(1), def },
  { "xor.l",    mode_dab,  class3|(8<<21)|(4), def },
  { "xor.w",    mode_dab,  class3|(8<<21)|(2), def },
};
Commit	Line	Data
1945cfa5 EB	1	/* Opcode table header for Visium.
1945cfa5 EB	2
250d07de	3	Copyright (C) 2003-2021 Free Software Foundation, Inc.
1945cfa5 EB	4
	5	This file is part of GDB, GAS, and GNU binutils.
	6
	7	GDB, GAS and the GNU binutils are free software; you can redistribute
	8	them and/or modify them under the terms of the GNU General Public
	9	License as published by the Free Software Foundation; either version 3,
	10	or (at your option) any later version.
	11
	12	GDB, GAS, and the GNU binutils are distributed in the hope that they
	13	will be useful, but WITHOUT ANY WARRANTY; without even the implied
	14	warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
	15	the GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this file; see the file COPYING3. If not, write to the Free
	19	Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
	20	MA 02110-1301, USA. */
	21
	22	enum visium_opcode_arch_val
	23	{
	24	VISIUM_OPCODE_ARCH_DEF = 0,
	25	VISIUM_OPCODE_ARCH_GR5,
	26	VISIUM_OPCODE_ARCH_GR6,
	27	VISIUM_OPCODE_ARCH_BAD
	28	};
	29
	30	/* The highest architecture in the table. */
	31	#define VISIUM_OPCODE_ARCH_MAX (VISIUM_OPCODE_ARCH_BAD - 1)
	32
	33	/* Given an enum visium_opcode_arch_val, return the bitmask to use in
	34	insn encoding/decoding. */
	35	#define VISIUM_OPCODE_ARCH_MASK(arch) (1 << (arch))
	36
	37	/* Some defines to make life easy. */
	38	#define MASK_DEF VISIUM_OPCODE_ARCH_MASK (VISIUM_OPCODE_ARCH_DEF)
	39	#define MASK_GR5 VISIUM_OPCODE_ARCH_MASK (VISIUM_OPCODE_ARCH_GR5)
	40	#define MASK_GR6 VISIUM_OPCODE_ARCH_MASK (VISIUM_OPCODE_ARCH_GR6)
	41
	42	/* Bit masks of architectures supporting the insn. */
	43	#define def (MASK_DEF \| MASK_GR5 \| MASK_GR6)
	44	#define gr5 (MASK_GR5 \| MASK_GR6)
	45	#define gr6 (MASK_GR6)
	46
	47	/* The condition code field is not used (zero) for most instructions.
	48	BRR and BRA make normal use of it. Floating point instructions use
	49	it as a sub-opcode. */
	50	#define CC_MASK (0xf << 27)
	51
	52	/* It seems a shame not to use these bits in a class 0 instruction,
	53	since they could be used to extend the range of the branch. */
	54	#define CLASS0_UNUSED_MASK (0x1f << 16)
	55
	56	/* For class 1 instructions the following bit is unused. */
	57	#define CLASS1_UNUSED_MASK (1 << 9)
	58
	59	/* For class 1 instructions this field gives the index for a write
	60	instruction, the specific operation for an EAM instruction, or
	61	the floating point destination register for a floating point
	62	instruction. */
	63	#define CLASS1_INDEX_MASK (0x1f << 10)
	64
	65	/* For class 3 instructions the following field gives the destination
	66	general register. */
	67	#define CLASS3_DEST_MASK (0x1f << 10)
68
69	/* For class 1 and class 3 instructions the following bit selects an
70	EAM write/read rather than a memory write/read. */
71	#define EAM_SELECT_MASK (1 << 15)
72
73	/* Floating point instructions are distinguished from general EAM
74	instructions by the following bit. */
75	#define FP_SELECT_MASK (1 << 3)
76
77	/* For both class 1 and class 3 the following fields give, where
78	appropriate the srcA and srcB registers whether floating point
79	or general. */
80	#define SRCA_MASK (0x1f << 16)
81	#define SRCB_MASK (0x1f << 4)
82
83	/* The class 3 interrupt bit. It turns a BRA into a SYS1, and an
84	RFLAG into a SYS2. This bit should not be set in the user's
85	class 3 instructions. This bit is also used in class 3
86	to distinguish between floating point and other EAM operations.
87	(see FP_SELECT_MASK). */
88	#define CLASS3_INT (1 << 3)
89
90	/* Class 3 shift instructions use this bit to indicate that the
91	srcB field is a 5 bit immediate shift count rather than a
92	register number. */
93	#define CLASS3_SOURCEB_IMMED (1 << 9)
94
95	#define BMD 0x02630004
96	#define BMI 0x82230004
97	#define DSI 0x82800004
98	#define ENI 0x02a00004
99	#define RFI 0x82fe01d4
100
101	struct reg_entry
102	{
f86f5863	103	const char *name;
1945cfa5 EB	104	unsigned char code;
	105	};
	106
609332f1	107	static const struct reg_entry gen_reg_table[] ATTRIBUTE_UNUSED =
1945cfa5 EB	108	{
	109	{"fp", 0x16},
	110	{"r0", 0x0},
	111	{"r1", 0x1},
	112	{"r10", 0xA},
	113	{"r11", 0xB},
	114	{"r12", 0xC},
	115	{"r13", 0xD},
	116	{"r14", 0xE},
	117	{"r15", 0xF},
	118	{"r16", 0x10},
	119	{"r17", 0x11},
	120	{"r18", 0x12},
	121	{"r19", 0x13},
	122	{"r2", 0x2},
	123	{"r20", 0x14},
	124	{"r21", 0x15},
	125	{"r22", 0x16},
	126	{"r23", 0x17},
	127	{"r24", 0x18},
	128	{"r25", 0x19},
	129	{"r26", 0x1a},
	130	{"r27", 0x1b},
	131	{"r28", 0x1c},
	132	{"r29", 0x1d},
	133	{"r3", 0x3},
	134	{"r30", 0x1e},
	135	{"r31", 0x1f},
	136	{"r4", 0x4},
	137	{"r5", 0x5},
	138	{"r6", 0x6},
	139	{"r7", 0x7},
	140	{"r8", 0x8},
	141	{"r9", 0x9},
	142	{"sp", 0x17},
	143	};
	144
609332f1	145	static const struct reg_entry fp_reg_table[] ATTRIBUTE_UNUSED =
1945cfa5 EB	146	{
	147	{"f0", 0x0},
	148	{"f1", 0x1},
	149	{"f10", 0xa},
	150	{"f11", 0xb},
	151	{"f12", 0xc},
	152	{"f13", 0xd},
	153	{"f14", 0xe},
	154	{"f15", 0xf},
	155	{"f2", 0x2},
	156	{"f3", 0x3},
	157	{"f4", 0x4},
	158	{"f5", 0x5},
	159	{"f6", 0x6},
	160	{"f7", 0x7},
	161	{"f8", 0x8},
	162	{"f9", 0x9},
	163	};
	164
7bdf96ef	165	static const struct cc_entry
1945cfa5	166	{
f86f5863	167	const char *name;
1945cfa5	168	int code;
609332f1	169	} cc_table [] ATTRIBUTE_UNUSED =
1945cfa5 EB	170	{
	171	{"cc", 6},
	172	{"cs", 2},
	173	{"eq", 1},
	174	{"fa", 0},
	175	{"ge", 9},
	176	{"gt", 10},
	177	{"hi", 11},
	178	{"le", 12},
	179	{"ls", 13},
	180	{"lt", 14},
	181	{"nc", 8},
	182	{"ne", 5},
	183	{"ns", 4},
	184	{"oc", 7},
	185	{"os", 3},
	186	{"tr", 15},
	187	};
	188
	189	enum addressing_mode
	190	{
	191	mode_d, /* register := */
	192	mode_a, /* op= register */
	193	mode_da, /* register := register */
	194	mode_ab, /* register * register */
	195	mode_dab, /* register := register * register */
	196	mode_iab, /* 5-bit immediate * register * register */
	197	mode_0ab, /* zero * register * register */
	198	mode_da0, /* register := register * zero */
	199	mode_cad, /* condition * register * register */
	200	mode_das, /* register := register * 5-bit immed/register shift count */
	201	mode_di, /* register := 5-bit immediate */
	202	mode_ir, /* 5-bit immediate * register */
	203	mode_ai, /* register 16-bit unsigned immediate */
	204	mode_i, /* 16-bit unsigned immediate */
	205	mode_bax, /* register * register * 5-bit immediate */
	206	mode_dax, /* register := register * 5-bit immediate */
	207	mode_s, /* special mode */
	208	mode_sr, /* special mode with register */
	209	mode_ci, /* condition * 16-bit signed word displacement */
	210	mode_fdab, /* float := float * float */
	211	mode_ifdab, /* fpinst: 4-bit immediate * float * float * float */
	212	mode_idfab, /* fpuread: 4-bit immediate * register * float * float */
	213	mode_fda, /* float := float */
	214	mode_fdra, /* float := register */
	215	mode_rdfab, /* register := float * float */
	216	mode_rdfa, /* register := float */
	217	mode_rrr, /* 3 register sources and destinations (block move) */
	218	};
	219
	220	#define class0 (0<<25)
	221	#define class1 (1<<25)
	222	#define class2 (2<<25)
	223	#define class3 (3<<25)
	224
	225	static const struct opcode_entry
	226	{
f86f5863	227	const char *mnem;
1945cfa5 EB	228	enum addressing_mode mode;
	229	unsigned code;
	230	char flags;
	231	}
609332f1	232	opcode_table[] ATTRIBUTE_UNUSED =
1945cfa5 EB	233	{
	234	{ "adc.b", mode_dab, class3\|(1<<21)\|(1), def },
	235	{ "adc.l", mode_dab, class3\|(1<<21)\|(4), def },
	236	{ "adc.w", mode_dab, class3\|(1<<21)\|(2), def },
	237	{ "add.b", mode_dab, class3\|(0<<21)\|(1), def },
	238	{ "add.l", mode_dab, class3\|(0<<21)\|(4), def },
	239	{ "add.w", mode_dab, class3\|(0<<21)\|(2), def },
	240	{ "addi", mode_ai, class2, def },
	241	{ "and.b", mode_dab, class3\|(10<<21)\|(1), def},
	242	{ "and.l", mode_dab, class3\|(10<<21)\|(4), def },
	243	{ "and.w", mode_dab, class3\|(10<<21)\|(2), def },
	244	{ "asl.b", mode_das, class3\|(7<<21)\|(1), def },
	245	{ "asl.l", mode_das, class3\|(7<<21)\|(4), def },
	246	{ "asl.w", mode_das, class3\|(7<<21)\|(2), def },
	247	{ "asld", mode_a, class1\|(15<<21)\|(1<<15)\|(11<<10)\|(4), def },
	248	{ "asr.b", mode_das, class3\|(5<<21)\|(1), def },
	249	{ "asr.l", mode_das, class3\|(5<<21)\|(4), def },
	250	{ "asr.w", mode_das, class3\|(5<<21)\|(2), def },
	251	{ "asrd", mode_a, class1\|(15<<21)\|(1<<15)\|(9<<10)\|(4), def },
	252	{ "bmd", mode_rrr, class1\|(3<<21)\|(3<<16)\|(4), gr6 },
	253	{ "bmi", mode_rrr, class1\|(1<<21)\|(3<<16)\|(4), gr6 },
	254	{ "bra", mode_cad, class3\|(12<<21)\|(4), def },
	255	{ "brr", mode_ci, class0, def },
	256	{ "cmp.b", mode_0ab, class3\|(2<<21)\|(1), def },
	257	{ "cmp.l", mode_0ab, class3\|(2<<21)\|(4), def },
	258	{ "cmp.w", mode_0ab, class3\|(2<<21)\|(2), def },
	259	{ "cmpc.b", mode_0ab, class3\|(3<<21)\|(1), def },
	260	{ "cmpc.l", mode_0ab, class3\|(3<<21)\|(4), def },
	261	{ "cmpc.w", mode_0ab, class3\|(3<<21)\|(2), def },
	262	{ "divds", mode_a, class1\|(15<<21)\|(1<<15)\|(6<<10)\|(4), def },
	263	{ "divdu", mode_a, class1\|(15<<21)\|(1<<15)\|(7<<10)\|(4), def },
	264	{ "divs", mode_a, class1\|(15<<21)\|(1<<15)\|(2<<10)\|(4), def },
	265	{ "divu", mode_a, class1\|(15<<21)\|(1<<15)\|(3<<10)\|(4), def },
	266	{ "dsi", mode_s, class1\|(4<<21)\|(4), def },
	267	{ "eamread", mode_di, class3\|(15<<21)\|(1<<15)\|(1<<9)\|(4), def },
	268	{ "eamwrite", mode_iab, class1\|(15<<21)\|(1<<15)\|(4), def },
	269	{ "eni", mode_s, class1\|(5<<21)\|(4), def },
	270	{ "extb.b", mode_da, class3\|(14<<21)\|(1), def },
	271	{ "extb.l", mode_da, class3\|(14<<21)\|(4), def },
	272	{ "extb.w", mode_da, class3\|(14<<21)\|(2), def },
	273	{ "extw.l", mode_da, class3\|(4<<21)\|(4), def },
	274	{ "extw.w", mode_da, class3\|(4<<21)\|(2), def },
	275	{ "fabs", mode_fda, class1\|(7<<27)\|(15<<21)\|(1<<15)\|(1<<3)\|(4), gr5 },
	276	{ "fadd", mode_fdab, class1\|(1<<27)\|(15<<21)\|(1<<15)\|(1<<3)\|(4), gr5 },
	277	{ "fcmp", mode_rdfab,class3\|(10<<27)\|(15<<21)\|(1<<15)\|(1<<9)\|(1<<3)\|(4), gr5 },
	278	{ "fcmpe", mode_rdfab,class3\|(11<<27)\|(15<<21)\|(1<<15)\|(1<<9)\|(1<<3)\|(4), gr5 },
	279	{ "fdiv", mode_fdab, class1\|(4<<27)\|(15<<21)\|(1<<15)\|(1<<3)\|(4), gr5 },
	280	{ "fload", mode_fdra, class1\|(15<<21)\|(1<<15)\|(1<<3)\|(4), gr5 },
	281	{ "fmove", mode_fda, class1\|(12<<27)\|(15<<21)\|(1<<15)\|(1<<3)\|(4), gr5},
	282	{ "fmult", mode_fdab, class1\|(3<<27)\|(15<<21)\|(1<<15)\|(1<<3)\|(4), gr5 },
	283	{ "fneg", mode_fda, class1\|(6<<27)\|(15<<21)\|(1<<15)\|(1<<3)\|(4), gr5 },
	284	{ "fpinst", mode_ifdab,class1\|(15<<21)\|(1<<15)\|(1<<3)\|(4), gr5 },
	285	{ "fpuread", mode_idfab,class3\|(15<<21)\|(1<<15)\|(1<<9)\|(1<<3)\|(4), gr5 },
	286	{ "fsqrt", mode_fda, class1\|(5<<27)\|(15<<21)\|(1<<15)\|(1<<3)\|(4), gr5 },
	287	{ "fstore", mode_rdfa, class3\|(15<<21)\|(1<<15)\|(1<<9)\|(1<<3)\|(4), gr5 },
	288	{ "fsub", mode_fdab, class1\|(2<<27)\|(15<<21)\|(1<<15)\|(1<<3)\|(4), gr5 },
	289	{ "ftoi", mode_fda, class1\|(8<<27)\|(15<<21)\|(1<<15)\|(1<<3)\|(4), gr5 },
	290	{ "itof", mode_fda, class1\|(9<<27)\|(15<<21)\|(1<<15)\|(1<<3)\|(4), gr5 },
	291	{ "lsr.b", mode_das, class3\|(6<<21)\|(1), def },
	292	{ "lsr.l", mode_das, class3\|(6<<21)\|(4), def },
	293	{ "lsr.w", mode_das, class3\|(6<<21)\|(2), def },
	294	{ "lsrd", mode_a, class1\|(15<<21)\|(1<<15)\|(10<<10)\|(4), def },
	295	{ "move.b", mode_da0, class3\|(9<<21)\|(1), def },
	296	{ "move.l", mode_da0, class3\|(9<<21)\|(4), def },
297	{ "move.w", mode_da0, class3\|(9<<21)\|(2), def },
298	{ "movil", mode_ai, class2\|(4<<21), def },
299	{ "moviq", mode_ai, class2\|(6<<21), def },
300	{ "moviu", mode_ai, class2\|(5<<21), def },
301	{ "mults", mode_ab, class1\|(15<<21)\|(1<<15)\|(0<<10)\|(4), def },
302	{ "multu", mode_ab, class1\|(15<<21)\|(1<<15)\|(1<<10)\|(4), def },
303	{ "nop", mode_s, class0, def },
304	{ "not.b", mode_da, class3\|(11<<21)\|(1), def },
305	{ "not.l", mode_da, class3\|(11<<21)\|(4), def },
306	{ "not.w", mode_da, class3\|(11<<21)\|(2), def },
307	{ "or.b", mode_dab, class3\|(9<<21)\|(1), def },
308	{ "or.l", mode_dab, class3\|(9<<21)\|(4), def },
309	{ "or.w", mode_dab, class3\|(9<<21)\|(2), def },
310	{ "read.b", mode_dax, class3\|(15<<21)\|(1<<9)\|(1), def },
311	{ "read.l", mode_dax, class3\|(15<<21)\|(1<<9)\|(4), def },
312	{ "read.w", mode_dax, class3\|(15<<21)\|(1<<9)\|(2), def },
313	{ "readmda", mode_d, class3\|(15<<21)\|(1<<15)\|(1<<9)\|(4), def },
314	{ "readmdb", mode_d, class3\|(15<<21)\|(1<<15)\|(1<<9)\|(1<<4)\|(4), def },
315	{ "readmdc", mode_d, class3\|(15<<21)\|(1<<15)\|(1<<9)\|(2<<4)\|(4), def },
316	{ "rfi", mode_s, class1\|(7<<21)\|(30<<16)\|(29<<4)\|(4), def },
317	{ "rflag", mode_d, class3\|(13<<21)\|(4), def },
318	{ "stop", mode_ir, class1\|(0<<21)\|(4), def },
319	{ "sub.b", mode_dab, class3\|(2<<21)\|(1), def },
320	{ "sub.l", mode_dab, class3\|(2<<21)\|(4), def },
321	{ "sub.w", mode_dab, class3\|(2<<21)\|(2), def },
322	{ "subc.b", mode_dab, class3\|(3<<21)\|(1), def },
323	{ "subc.l", mode_dab, class3\|(3<<21)\|(4), def },
324	{ "subc.w", mode_dab, class3\|(3<<21)\|(2), def },
325	{ "subi", mode_ai, class2\|(2<<21), def },
326	{ "trace", mode_ir, class1\|(13<<21), def },
327	{ "write.b", mode_bax, class1\|(15<<21)\|(1), def },
328	{ "write.l", mode_bax, class1\|(15<<21)\|(4), def },
329	{ "write.w", mode_bax, class1\|(15<<21)\|(2), def },
330	{ "writemd", mode_ab, class1\|(15<<21)\|(1<<15)\|(4<<10)\|(4), def },
331	{ "writemdc", mode_a, class1\|(15<<21)\|(1<<15)\|(5<<10)\|(4), def },
332	{ "wrtl", mode_i, class2\|(8<<21), gr6 },
333	{ "wrtu", mode_i, class2\|(9<<21), gr6 },
334	{ "xor.b", mode_dab, class3\|(8<<21)\|(1), def },
335	{ "xor.l", mode_dab, class3\|(8<<21)\|(4), def },
336	{ "xor.w", mode_dab, class3\|(8<<21)\|(2), def },
337	};
609332f1	338