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Fix tests after rebase of 36b6002396d onto 8504495ada4
[thirdparty/binutils-gdb.git] / ld / testsuite / ld-aarch64 / morello-ifunc1-a.d
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36b60023
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1# Checking that when linking as standard, the BL and the GOT access both use
2# the PLT. This link does not do anything special to maintain pointer equality
3# since there is no access which directly uses the address.
4#
5# Things this testcase checks:
6# 1) Fragment of IRELATIVE relocation is PCC_START with bounds and
7# permissions of PCC.
8# 2) GOT access uses IRELATIVE relocation in the PLTGOT when no direct access
9# to address is used.
10# 3) BL to an IFUNC branches to a PLT stub which uses the a PLTGOT slot
11# initialised by an IRELATIVE relocation against our resolver.
12#source: morello-ifunc1.s
13#as: -march=morello+c64
14#ld: -pie
15#objdump: -DR --section-headers
16
17.*: file format .*
18
19Sections:
20Idx Name Size VMA LMA File off Algn
21#record: PCC_START
22 0 \.[^ ]+ +[0-9a-f]+ ([0-9a-f]+) [0-9a-f]+ [0-9a-f]+ 2\*\*.
23 CONTENTS, ALLOC, LOAD, READONLY, DATA
36b60023 24#...
816fc4e7 25 *[0-9]+ \.got\.plt *[0-9a-f]+ [0-9a-f]+ .*
36b60023 26 CONTENTS, ALLOC, LOAD, DATA
816fc4e7
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27#record: PCC_END
28 *[0-9]+ \.[^ ]* +[0-9a-f]* ([0-9a-f]+) .*
36b60023
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29#...
30Disassembly of section \.plt:
31
32[0-9a-f]+ <\.plt>:
33#...
34.*nop
35.*nop
36.*nop
37# Note that for a none-linux-gnu target we don't emit a symbol specific to the
38# PLT stub for an IFUNC, but for a none-elf target we do. That means we can't
39# generally check the offset in the symbols name matches the `foo` address
40# below.
41#?
42#?[0-9a-f]+ <\*ABS\*\+0x[0-9a-f]+@plt>:
43#record: PLTADDR PLTGOT_PAGE
44 *([0-9a-f]+): .* adrp c16, ([0-9a-f]+) .*
45#record: PLTGOT_DEC_OFF
46 *[0-9a-f]+: .* ldr c17, \[c16, #([0-9]+)\]
47 *[0-9a-f]+: .* add c16, c16, #0x.*
48 *[0-9a-f]+: .* br c17
49
50Disassembly of section \.text:
51
52[0-9a-f]+ <foo_1>:
53#...
54
55[0-9a-f]+ <foo_2>:
56#...
57
58#record: FOO_ADDR
59([0-9a-f]+) <foo>:
60 *[0-9a-f]+: .* mov x1, #0x2a // #42
61 *[0-9a-f]+: .* tst x0, x1
62 *[0-9a-f]+: .* b\.ne .* <foo\+0x18> // b\.any
63 *[0-9a-f]+: .* adrp c0, .*
64 *[0-9a-f]+: .* add c0, c0, .*
65 *[0-9a-f]+: .* ret c30
66 *[0-9a-f]+: .* adrp c0, .*
67 *[0-9a-f]+: .* add c0, .*
68 *[0-9a-f]+: .* b .* <foo\+0x14>
69
70[0-9a-f]+ <_start>:
71#check: PLTLOC string tolower $PLTADDR
72#check: PLTGOTPAGE string tolower $PLTGOT_PAGE
73#check: PLTGOT_DECOFF string tolower $PLTGOT_DEC_OFF
74 *[0-9a-f]+: .* bl PLTLOC .*
75 *[0-9a-f]+: .* adrp c0, PLTGOTPAGE .*
76 *[0-9a-f]+: .* ldr c0, \[c0, #PLTGOT_DECOFF\]
77 *[0-9a-f]+: .* ret c30
78#...
79Disassembly of section \.got\.plt:
80
81#check: GOTLOC aarch64_page_plus_decimal_offset $PLTGOT_PAGE $PLTGOT_DEC_OFF
82#check: FRAGBASE format %08x 0x$PCC_START
816fc4e7 83#check: FRAGSIZE format %08x [expr "0x$PCC_END - 0x$PCC_START"]
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84#check: FOO_OFFSET format %x [expr "0x$FOO_ADDR + 1 - 0x$PCC_START"]
85[0-9a-f]+ <.*>:
86 \.\.\.
87 *GOTLOC: FRAGBASE .*
88 GOTLOC: R_MORELLO_IRELATIVE \*ABS\*\+0xFOO_OFFSET
89 *[0-9a-f]+: 00000000 .*
90 *[0-9a-f]+: FRAGSIZE .*
91 *[0-9a-f]+: 04000000 .*
92#...
93Disassembly of section \.data:
94
95[0-9a-f]+ <.*>:
96 *[0-9a-f]+: FRAGBASE .*
97 [0-9a-f]+: R_MORELLO_IRELATIVE \*ABS\*\+0xFOO_OFFSET
98 *[0-9a-f]+: 00000000 .*
99 *[0-9a-f]+: FRAGSIZE .*
100 *[0-9a-f]+: 04000000 .*
101#pass