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MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
38bf472a
MR		 12017-06-28 Maciej W. Rozycki <macro@imgtec.com>
2 Matthew Fortune <matthew.fortune@imgtec.com>
3 Andrew Bennett <andrew.bennett@imgtec.com>
4
5 * mips-formats.h (INT_BIAS): New macro.
6 (INT_ADJ): Redefine in INT_BIAS terms.
7 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
8 (mips_print_save_restore): New function.
9 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
10 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
11 call.
12 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
13 (print_mips16_insn_arg): Call `mips_print_save_restore' for
14 OP_SAVE_RESTORE_LIST handling, factored out from here.
15 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
16 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
17 (mips_builtin_opcodes): Add "restore" and "save" entries.
18 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
19 (IAMR2): New macro.
20 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
21
9bdfdbf9
AW		 222017-06-23 Andrew Waterman <andrew@sifive.com>
23
24 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
25 alias; do not mark SLTI instruction as an alias.
26
2234eee6
L		 272017-06-21 H.J. Lu <hongjiu.lu@intel.com>
28
29 * i386-dis.c (RM_0FAE_REG_5): Removed.
30 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
31 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
32 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
33 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
34 PREFIX_MOD_3_0F01_REG_5_RM_0.
35 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
36 PREFIX_MOD_3_0FAE_REG_5.
37 (mod_table): Update MOD_0FAE_REG_5.
38 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
39 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
40 * i386-tbl.h: Regenerated.
41
c2f76402
L		 422017-06-21 H.J. Lu <hongjiu.lu@intel.com>
43
44 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
45 * i386-opc.tbl: Likewise.
46 * i386-tbl.h: Regenerated.
47
9fef80d6
L		 482017-06-21 H.J. Lu <hongjiu.lu@intel.com>
49
50 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
51 and "jmp{&|}".
52 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
53 prefix.
54
0f6d864d
NC		 552017-06-19 Nick Clifton <nickc@redhat.com>
56
57 PR binutils/21614
58 * score-dis.c (score_opcodes): Add sentinel.
59
e197589b
AM		 602017-06-16 Alan Modra <amodra@gmail.com>
61
62 * rx-decode.c: Regenerate.
63
0d96e4df
L		 642017-06-15 H.J. Lu <hongjiu.lu@intel.com>
65
66 PR binutils/21594
67 * i386-dis.c (OP_E_register): Check valid bnd register.
68 (OP_G): Likewise.
69
cd3ea7c6
NC		 702017-06-15 Nick Clifton <nickc@redhat.com>
71
72 PR binutils/21595
73 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
74 range value.
75
63323b5b
NC		 762017-06-15 Nick Clifton <nickc@redhat.com>
77
78 PR binutils/21588
79 * rl78-decode.opc (OP_BUF_LEN): Define.
80 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
81 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
82 array.
83 * rl78-decode.c: Regenerate.
84
08c7881b
NC		 852017-06-15 Nick Clifton <nickc@redhat.com>
86
87 PR binutils/21586
88 * bfin-dis.c (gregs): Clip index to prevent overflow.
89 (regs): Likewise.
90 (regs_lo): Likewise.
91 (regs_hi): Likewise.
92
e64519d1
NC		 932017-06-14 Nick Clifton <nickc@redhat.com>
94
95 PR binutils/21576
96 * score7-dis.c (score_opcodes): Add sentinel.
97
6394c606
YQ		 982017-06-14 Yao Qi <yao.qi@linaro.org>
99
100 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
101 * arm-dis.c: Likewise.
102 * ia64-dis.c: Likewise.
103 * mips-dis.c: Likewise.
104 * spu-dis.c: Likewise.
105 * disassemble.h (print_insn_aarch64): New declaration, moved from
106 include/dis-asm.h.
107 (print_insn_big_arm, print_insn_big_mips): Likewise.
108 (print_insn_i386, print_insn_ia64): Likewise.
109 (print_insn_little_arm, print_insn_little_mips): Likewise.
110
db5fa770
NC		 1112017-06-14 Nick Clifton <nickc@redhat.com>
112
113 PR binutils/21587
114 * rx-decode.opc: Include libiberty.h
115 (GET_SCALE): New macro - validates access to SCALE array.
116 (GET_PSCALE): New macro - validates access to PSCALE array.
117 (DIs, SIs, S2Is, rx_disp): Use new macros.
118 * rx-decode.c: Regenerate.
119
05c966f3
AV		 1202017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
121
122 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
123
10045478
AK		 1242017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
125
126 * arc-dis.c (enforced_isa_mask): Declare.
127 (cpu_types): Likewise.
128 (parse_cpu_option): New function.
129 (parse_disassembler_options): Use it.
130 (print_insn_arc): Use enforced_isa_mask.
131 (print_arc_disassembler_options): Document new options.
132
88c1242d
YQ		 1332017-05-24 Yao Qi <yao.qi@linaro.org>
134
135 * alpha-dis.c: Include disassemble.h, don't include
136 dis-asm.h.
137 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
138 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
139 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
140 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
141 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
142 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
143 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
144 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
145 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
146 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
147 * moxie-dis.c, msp430-dis.c, mt-dis.c:
148 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
149 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
150 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
151 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
152 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
153 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
154 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
155 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
156 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
157 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
158 * z80-dis.c, z8k-dis.c: Likewise.
159 * disassemble.h: New file.
160
ab20fa4a
YQ		 1612017-05-24 Yao Qi <yao.qi@linaro.org>
162
163 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
164 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
165
003ca0fd
YQ		 1662017-05-24 Yao Qi <yao.qi@linaro.org>
167
168 * disassemble.c (disassembler): Add arguments a, big and mach.
169 Use them.
170
04ef582a
L		 1712017-05-22 H.J. Lu <hongjiu.lu@intel.com>
172
173 * i386-dis.c (NOTRACK_Fixup): New.
174 (NOTRACK): Likewise.
175 (NOTRACK_PREFIX): Likewise.
176 (last_active_prefix): Likewise.
177 (reg_table): Use NOTRACK on indirect call and jmp.
178 (ckprefix): Set last_active_prefix.
179 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
180 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
181 * i386-opc.h (NoTrackPrefixOk): New.
182 (i386_opcode_modifier): Add notrackprefixok.
183 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
184 Add notrack.
185 * i386-tbl.h: Regenerated.
186
64517994
JM		 1872017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
188
189 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
190 (X_IMM2): Define.
191 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
192 bfd_mach_sparc_v9m8.
193 (print_insn_sparc): Handle new operand types.
194 * sparc-opc.c (MASK_M8): Define.
195 (v6): Add MASK_M8.
196 (v6notlet): Likewise.
197 (v7): Likewise.
198 (v8): Likewise.
199 (v9): Likewise.
200 (v9a): Likewise.
201 (v9b): Likewise.
202 (v9c): Likewise.
203 (v9d): Likewise.
204 (v9e): Likewise.
205 (v9v): Likewise.
206 (v9m): Likewise.
207 (v9andleon): Likewise.
208 (m8): Define.
209 (HWS_VM8): Define.
210 (HWS2_VM8): Likewise.
211 (sparc_opcode_archs): Add entry for "m8".
212 (sparc_opcodes): Add OSA2017 and M8 instructions
213 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
214 fpx{ll,ra,rl}64x,
215 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
216 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
217 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
218 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
219 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
220 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
221 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
222 ASI_CORE_SELECT_COMMIT_NHT.
223
535b785f
AM		 2242017-05-18 Alan Modra <amodra@gmail.com>
225
226 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
227 * aarch64-dis.c: Likewise.
228 * aarch64-gen.c: Likewise.
229 * aarch64-opc.c: Likewise.
230
25499ac7
MR		 2312017-05-15 Maciej W. Rozycki <macro@imgtec.com>
232 Matthew Fortune <matthew.fortune@imgtec.com>
233
234 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
235 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
236 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
237 (print_insn_arg) <OP_REG28>: Add handler.
238 (validate_insn_args) <OP_REG28>: Handle.
239 (print_mips16_insn_arg): Handle MIPS16 instructions that require
240 32-bit encoding and 9-bit immediates.
241 (print_insn_mips16): Handle MIPS16 instructions that require
242 32-bit encoding and MFC0/MTC0 operand decoding.
243 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
244 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
245 (RD_C0, WR_C0, E2, E2MT): New macros.
246 (mips16_opcodes): Add entries for MIPS16e2 instructions:
247 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
248 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
249 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
250 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
251 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
252 instructions, "swl", "swr", "sync" and its "sync_acquire",
253 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
254 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
255 regular/extended entries for original MIPS16 ISA revision
256 instructions whose extended forms are subdecoded in the MIPS16e2
257 ISA revision: "li", "sll" and "srl".
258
fdfb4752
MR		 2592017-05-15 Maciej W. Rozycki <macro@imgtec.com>
260
261 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
262 reference in CP0 move operand decoding.
263
a4f89915
MR		 2642017-05-12 Maciej W. Rozycki <macro@imgtec.com>
265
266 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
267 type to hexadecimal.
268 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
269
99e2d67a
MR		 2702017-05-11 Maciej W. Rozycki <macro@imgtec.com>
271
272 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
273 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
274 "sync_rmb" and "sync_wmb" as aliases.
275 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
276 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
277
53a346d8
CZ		 2782017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
279
280 * arc-dis.c (parse_option): Update quarkse_em option..
281 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
282 QUARKSE1.
283 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
284
f91d48de
KC		 2852017-05-03 Kito Cheng <kito.cheng@gmail.com>
286
287 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
288
43e379d7
MC		 2892017-05-01 Michael Clark <michaeljclark@mac.com>
290
291 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
292 register.
293
a4ddc54e
MR		 2942017-05-02 Maciej W. Rozycki <macro@imgtec.com>
295
296 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
297 and branches and not synthetic data instructions.
298
fe50e98c
BE		 2992017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
300
301 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
302
126124cc
CZ		 3032017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
304
305 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
306 * arc-opc.c (insert_r13el): New function.
307 (R13_EL): Define.
308 * arc-tbl.h: Add new enter/leave variants.
309
be6a24d8
CZ		 3102017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
311
312 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
313
0348fd79
MR		 3142017-04-25 Maciej W. Rozycki <macro@imgtec.com>
315
316 * mips-dis.c (print_mips_disassembler_options): Add
317 `no-aliases'.
318
6e3d1f07
MR		 3192017-04-25 Maciej W. Rozycki <macro@imgtec.com>
320
321 * mips16-opc.c (AL): New macro.
322 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
323 of "ld" and "lw" as aliases.
324
957f6b39
TC		 3252017-04-24 Tamar Christina <tamar.christina@arm.com>
326
327 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
328 arguments.
329
a8cc8a54
AM		 3302017-04-22 Alexander Fedotov <alfedotov@gmail.com>
331 Alan Modra <amodra@gmail.com>
332
333 * ppc-opc.c (ELEV): Define.
334 (vle_opcodes): Add se_rfgi and e_sc.
335 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
336 for E200Z4.
337
3ab87b68
JM		 3382017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
339
340 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
341
792f174f
NC		 3422017-04-21 Nick Clifton <nickc@redhat.com>
343
344 PR binutils/21380
345 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
346 LD3R and LD4R.
347
42742084
AM		 3482017-04-13 Alan Modra <amodra@gmail.com>
349
350 * epiphany-desc.c: Regenerate.
351 * fr30-desc.c: Regenerate.
352 * frv-desc.c: Regenerate.
353 * ip2k-desc.c: Regenerate.
354 * iq2000-desc.c: Regenerate.
355 * lm32-desc.c: Regenerate.
356 * m32c-desc.c: Regenerate.
357 * m32r-desc.c: Regenerate.
358 * mep-desc.c: Regenerate.
359 * mt-desc.c: Regenerate.
360 * or1k-desc.c: Regenerate.
361 * xc16x-desc.c: Regenerate.
362 * xstormy16-desc.c: Regenerate.
363
9a85b496
AM		 3642017-04-11 Alan Modra <amodra@gmail.com>
365
ef85eab0 366 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 367 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
368 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 369 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
370 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 371 (PPCVSX2): Define as PPC_OPCODE_POWER8.
372 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 373 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 374 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 375
62adc510
AM		 3762017-04-10 Alan Modra <amodra@gmail.com>
377
378 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
379 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
380 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
381 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
382
aa808707
PC		 3832017-04-09 Pip Cet <pipcet@gmail.com>
384
385 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
386 appropriate floating-point precision directly.
387
ac8f0f72
AM		 3882017-04-07 Alan Modra <amodra@gmail.com>
389
390 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
391 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
392 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
393 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
394 vector instructions with E6500 not PPCVEC2.
395
62ecb94c
PC		 3962017-04-06 Pip Cet <pipcet@gmail.com>
397
398 * Makefile.am: Add wasm32-dis.c.
399 * configure.ac: Add wasm32-dis.c to wasm32 target.
400 * disassemble.c: Add wasm32 disassembler code.
401 * wasm32-dis.c: New file.
402 * Makefile.in: Regenerate.
403 * configure: Regenerate.
404 * po/POTFILES.in: Regenerate.
405 * po/opcodes.pot: Regenerate.
406
f995bbe8
PA		 4072017-04-05 Pedro Alves <palves@redhat.com>
408
409 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
410 * arm-dis.c (parse_arm_disassembler_options): Constify.
411 * ppc-dis.c (powerpc_init_dialect): Constify local.
412 * vax-dis.c (parse_disassembler_options): Constify.
413
b5292032
PD		 4142017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
415
416 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
417 RISCV_GP_SYMBOL.
418
f96bd6c2
PC		 4192017-03-30 Pip Cet <pipcet@gmail.com>
420
421 * configure.ac: Add (empty) bfd_wasm32_arch target.
422 * configure: Regenerate
423 * po/opcodes.pot: Regenerate.
424
f7c514a3
JM		 4252017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
426
427 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
428 OSA2015.
429 * opcodes/sparc-opc.c (asi_table): New ASIs.
430
52be03fd
AM		 4312017-03-29 Alan Modra <amodra@gmail.com>
432
433 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
434 "raw" option.
435 (lookup_powerpc): Don't special case -1 dialect. Handle
436 PPC_OPCODE_RAW.
437 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
438 lookup_powerpc call, pass it on second.
439
9b753937
AM		 4402017-03-27 Alan Modra <amodra@gmail.com>
441
442 PR 21303
443 * ppc-dis.c (struct ppc_mopt): Comment.
444 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
445
c0c31e91
RZ		 4462017-03-27 Rinat Zelig <rinat@mellanox.com>
447
448 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
449 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
450 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
451 (insert_nps_misc_imm_offset): New function.
452 (extract_nps_misc imm_offset): New function.
453 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
454 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
455
2253c8f0
AK		 4562017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
457
458 * s390-mkopc.c (main): Remove vx2 check.
459 * s390-opc.txt: Remove vx2 instruction flags.
460
645d3342
RZ		 4612017-03-21 Rinat Zelig <rinat@mellanox.com>
462
463 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
464 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
465 (insert_nps_imm_offset): New function.
466 (extract_nps_imm_offset): New function.
467 (insert_nps_imm_entry): New function.
468 (extract_nps_imm_entry): New function.
469
4b94dd2d
AM		 4702017-03-17 Alan Modra <amodra@gmail.com>
471
472 PR 21248
473 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
474 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
475 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
476
b416fe87
KC		 4772017-03-14 Kito Cheng <kito.cheng@gmail.com>
478
479 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
480 <c.andi>: Likewise.
481 <c.addiw> Likewise.
482
03b039a5
KC		 4832017-03-14 Kito Cheng <kito.cheng@gmail.com>
484
485 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
486
2c232b83
AW		 4872017-03-13 Andrew Waterman <andrew@sifive.com>
488
489 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
490 <srl> Likewise.
491 <srai> Likewise.
492 <sra> Likewise.
493
86fa6981
L		 4942017-03-09 H.J. Lu <hongjiu.lu@intel.com>
495
496 * i386-gen.c (opcode_modifiers): Replace S with Load.
497 * i386-opc.h (S): Removed.
498 (Load): New.
499 (i386_opcode_modifier): Replace s with load.
500 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
501 and {evex}. Replace S with Load.
502 * i386-tbl.h: Regenerated.
503
c1fe188b
L		 5042017-03-09 H.J. Lu <hongjiu.lu@intel.com>
505
506 * i386-opc.tbl: Use CpuCET on rdsspq.
507 * i386-tbl.h: Regenerated.
508
4b8b687e
PB		 5092017-03-08 Peter Bergner <bergner@vnet.ibm.com>
510
511 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
512 <vsx>: Do not use PPC_OPCODE_VSX3;
513
1437d063
PB		 5142017-03-08 Peter Bergner <bergner@vnet.ibm.com>
515
516 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
517
603555e5
L		 5182017-03-06 H.J. Lu <hongjiu.lu@intel.com>
519
520 * i386-dis.c (REG_0F1E_MOD_3): New enum.
521 (MOD_0F1E_PREFIX_1): Likewise.
522 (MOD_0F38F5_PREFIX_2): Likewise.
523 (MOD_0F38F6_PREFIX_0): Likewise.
524 (RM_0F1E_MOD_3_REG_7): Likewise.
525 (PREFIX_MOD_0_0F01_REG_5): Likewise.
526 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
527 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
528 (PREFIX_0F1E): Likewise.
529 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
530 (PREFIX_0F38F5): Likewise.
531 (dis386_twobyte): Use PREFIX_0F1E.
532 (reg_table): Add REG_0F1E_MOD_3.
533 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
534 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
535 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
536 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
537 (three_byte_table): Use PREFIX_0F38F5.
538 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
539 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
540 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
541 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
542 PREFIX_MOD_3_0F01_REG_5_RM_2.
543 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
544 (cpu_flags): Add CpuCET.
545 * i386-opc.h (CpuCET): New enum.
546 (CpuUnused): Commented out.
547 (i386_cpu_flags): Add cpucet.
548 * i386-opc.tbl: Add Intel CET instructions.
549 * i386-init.h: Regenerated.
550 * i386-tbl.h: Likewise.
551
73f07bff
AM		 5522017-03-06 Alan Modra <amodra@gmail.com>
553
554 PR 21124
555 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
556 (extract_raq, extract_ras, extract_rbx): New functions.
557 (powerpc_operands): Use opposite corresponding insert function.
558 (Q_MASK): Define.
559 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
560 register restriction.
561
65b48a81
PB		 5622017-02-28 Peter Bergner <bergner@vnet.ibm.com>
563
564 * disassemble.c Include "safe-ctype.h".
565 (disassemble_init_for_target): Handle s390 init.
566 (remove_whitespace_and_extra_commas): New function.
567 (disassembler_options_cmp): Likewise.
568 * arm-dis.c: Include "libiberty.h".
569 (NUM_ELEM): Delete.
570 (regnames): Use long disassembler style names.
571 Add force-thumb and no-force-thumb options.
572 (NUM_ARM_REGNAMES): Rename from this...
573 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
574 (get_arm_regname_num_options): Delete.
575 (set_arm_regname_option): Likewise.
576 (get_arm_regnames): Likewise.
577 (parse_disassembler_options): Likewise.
578 (parse_arm_disassembler_option): Rename from this...
579 (parse_arm_disassembler_options): ...to this. Make static.
580 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
581 (print_insn): Use parse_arm_disassembler_options.
582 (disassembler_options_arm): New function.
583 (print_arm_disassembler_options): Handle updated regnames.
584 * ppc-dis.c: Include "libiberty.h".
585 (ppc_opts): Add "32" and "64" entries.
586 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
587 (powerpc_init_dialect): Add break to switch statement.
588 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
589 (disassembler_options_powerpc): New function.
590 (print_ppc_disassembler_options): Use ARRAY_SIZE.
591 Remove printing of "32" and "64".
592 * s390-dis.c: Include "libiberty.h".
593 (init_flag): Remove unneeded variable.
594 (struct s390_options_t): New structure type.
595 (options): New structure.
596 (init_disasm): Rename from this...
597 (disassemble_init_s390): ...to this. Add initializations for
598 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
599 (print_insn_s390): Delete call to init_disasm.
600 (disassembler_options_s390): New function.
601 (print_s390_disassembler_options): Print using information from
602 struct 'options'.
603 * po/opcodes.pot: Regenerate.
604
15c7c1d8
JB		 6052017-02-28 Jan Beulich <jbeulich@suse.com>
606
607 * i386-dis.c (PCMPESTR_Fixup): New.
608 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
609 (prefix_table): Use PCMPESTR_Fixup.
610 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
611 PCMPESTR_Fixup.
612 (vex_w_table): Delete VPCMPESTR{I,M} entries.
613 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
614 Split 64-bit and non-64-bit variants.
615 * opcodes/i386-tbl.h: Re-generate.
616
582e12bf
RS		 6172017-02-24 Richard Sandiford <richard.sandiford@arm.com>
618
619 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
620 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
621 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
622 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
623 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
624 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
625 (OP_SVE_V_HSD): New macros.
626 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
627 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
628 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
629 (aarch64_opcode_table): Add new SVE instructions.
630 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
631 for rotation operands. Add new SVE operands.
632 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
633 (ins_sve_quad_index): Likewise.
634 (ins_imm_rotate): Split into...
635 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
636 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
637 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
638 functions.
639 (aarch64_ins_sve_addr_ri_s4): New function.
640 (aarch64_ins_sve_quad_index): Likewise.
641 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
642 * aarch64-asm-2.c: Regenerate.
643 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
644 (ext_sve_quad_index): Likewise.
645 (ext_imm_rotate): Split into...
646 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
647 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
648 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
649 functions.
650 (aarch64_ext_sve_addr_ri_s4): New function.
651 (aarch64_ext_sve_quad_index): Likewise.
652 (aarch64_ext_sve_index): Allow quad indices.
653 (do_misc_decoding): Likewise.
654 * aarch64-dis-2.c: Regenerate.
655 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
656 aarch64_field_kinds.
657 (OPD_F_OD_MASK): Widen by one bit.
658 (OPD_F_NO_ZR): Bump accordingly.
659 (get_operand_field_width): New function.
660 * aarch64-opc.c (fields): Add new SVE fields.
661 (operand_general_constraint_met_p): Handle new SVE operands.
662 (aarch64_print_operand): Likewise.
663 * aarch64-opc-2.c: Regenerate.
664
f482d304
RS		 6652017-02-24 Richard Sandiford <richard.sandiford@arm.com>
666
667 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
668 (aarch64_feature_compnum): ...this.
669 (SIMD_V8_3): Replace with...
670 (COMPNUM): ...this.
671 (CNUM_INSN): New macro.
672 (aarch64_opcode_table): Use it for the complex number instructions.
673
7db2c588
JB		 6742017-02-24 Jan Beulich <jbeulich@suse.com>
675
676 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
677
1e9d41d4
SL		 6782017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
679
680 Add support for associating SPARC ASIs with an architecture level.
681 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
682 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
683 decoding of SPARC ASIs.
684
53c4d625
JB		 6852017-02-23 Jan Beulich <jbeulich@suse.com>
686
687 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
688 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
689
11648de5
JB		 6902017-02-21 Jan Beulich <jbeulich@suse.com>
691
692 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
693 1 (instead of to itself). Correct typo.
694
f98d33be
AW		 6952017-02-14 Andrew Waterman <andrew@sifive.com>
696
697 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
698 pseudoinstructions.
699
773fb663
RS		 7002017-02-15 Richard Sandiford <richard.sandiford@arm.com>
701
702 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
703 (aarch64_sys_reg_supported_p): Handle them.
704
cc07cda6
CZ		 7052017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
706
707 * arc-opc.c (UIMM6_20R): Define.
708 (SIMM12_20): Use above.
709 (SIMM12_20R): Define.
710 (SIMM3_5_S): Use above.
711 (UIMM7_A32_11R_S): Define.
712 (UIMM7_9_S): Use above.
713 (UIMM3_13R_S): Define.
714 (SIMM11_A32_7_S): Use above.
715 (SIMM9_8R): Define.
716 (UIMM10_A32_8_S): Use above.
717 (UIMM8_8R_S): Define.
718 (W6): Use above.
719 (arc_relax_opcodes): Use all above defines.
720
66a5a740
VG		 7212017-02-15 Vineet Gupta <vgupta@synopsys.com>
722
723 * arc-regs.h: Distinguish some of the registers different on
724 ARC700 and HS38 cpus.
725
7e0de605
AM		 7262017-02-14 Alan Modra <amodra@gmail.com>
727
728 PR 21118
729 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
730 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
731
54064fdb
AM		 7322017-02-11 Stafford Horne <shorne@gmail.com>
733 Alan Modra <amodra@gmail.com>
734
735 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
736 Use insn_bytes_value and insn_int_value directly instead. Don't
737 free allocated memory until function exit.
738
dce75bf9
NP		 7392017-02-10 Nicholas Piggin <npiggin@gmail.com>
740
741 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
742
1b7e3d2f
NC		 7432017-02-03 Nick Clifton <nickc@redhat.com>
744
745 PR 21096
746 * aarch64-opc.c (print_register_list): Ensure that the register
747 list index will fir into the tb buffer.
748 (print_register_offset_address): Likewise.
749 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
750
8ec5cf65
AD		 7512017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
752
753 PR 21056
754 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
755 instructions when the previous fetch packet ends with a 32-bit
756 instruction.
757
a1aa5e81
DD		 7582017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
759
760 * pru-opc.c: Remove vague reference to a future GDB port.
761
add3afb2
NC		 7622017-01-20 Nick Clifton <nickc@redhat.com>
763
764 * po/ga.po: Updated Irish translation.
765
c13a63b0
SN		 7662017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
767
768 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
769
9608051a
YQ		 7702017-01-13 Yao Qi <yao.qi@linaro.org>
771
772 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
773 if FETCH_DATA returns 0.
774 (m68k_scan_mask): Likewise.
775 (print_insn_m68k): Update code to handle -1 return value.
776
f622ea96
YQ		 7772017-01-13 Yao Qi <yao.qi@linaro.org>
778
779 * m68k-dis.c (enum print_insn_arg_error): New.
780 (NEXTBYTE): Replace -3 with
781 PRINT_INSN_ARG_MEMORY_ERROR.
782 (NEXTULONG): Likewise.
783 (NEXTSINGLE): Likewise.
784 (NEXTDOUBLE): Likewise.
785 (NEXTDOUBLE): Likewise.
786 (NEXTPACKED): Likewise.
787 (FETCH_ARG): Likewise.
788 (FETCH_DATA): Update comments.
789 (print_insn_arg): Update comments. Replace magic numbers with
790 enum.
791 (match_insn_m68k): Likewise.
792
620214f7
IT		 7932017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
794
795 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
796 * i386-dis-evex.h (evex_table): Updated.
797 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
798 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
799 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
800 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
801 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
802 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
803 * i386-init.h: Regenerate.
804 * i386-tbl.h: Ditto.
805
d95014a2
YQ		 8062017-01-12 Yao Qi <yao.qi@linaro.org>
807
808 * msp430-dis.c (msp430_singleoperand): Return -1 if
809 msp430dis_opcode_signed returns false.
810 (msp430_doubleoperand): Likewise.
811 (msp430_branchinstr): Return -1 if
812 msp430dis_opcode_unsigned returns false.
813 (msp430x_calla_instr): Likewise.
814 (print_insn_msp430): Likewise.
815
0ae60c3e
NC		 8162017-01-05 Nick Clifton <nickc@redhat.com>
817
818 PR 20946
819 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
820 could not be matched.
821 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
822 NULL.
823
d74d4880
SN		 8242017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
825
826 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
827 (aarch64_opcode_table): Use RCPC_INSN.
828
cc917fd9
KC		 8292017-01-03 Kito Cheng <kito.cheng@gmail.com>
830
831 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
832 extension.
833 * riscv-opcodes/all-opcodes: Likewise.
834
b52d3cfc
DP		 8352017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
836
837 * riscv-dis.c (print_insn_args): Add fall through comment.
838
f90c58d5
NC		 8392017-01-03 Nick Clifton <nickc@redhat.com>
840
841 * po/sr.po: New Serbian translation.
842 * configure.ac (ALL_LINGUAS): Add sr.
843 * configure: Regenerate.
844
f47b0d4a
AM		 8452017-01-02 Alan Modra <amodra@gmail.com>
846
847 * epiphany-desc.h: Regenerate.
848 * epiphany-opc.h: Regenerate.
849 * fr30-desc.h: Regenerate.
850 * fr30-opc.h: Regenerate.
851 * frv-desc.h: Regenerate.
852 * frv-opc.h: Regenerate.
853 * ip2k-desc.h: Regenerate.
854 * ip2k-opc.h: Regenerate.
855 * iq2000-desc.h: Regenerate.
856 * iq2000-opc.h: Regenerate.
857 * lm32-desc.h: Regenerate.
858 * lm32-opc.h: Regenerate.
859 * m32c-desc.h: Regenerate.
860 * m32c-opc.h: Regenerate.
861 * m32r-desc.h: Regenerate.
862 * m32r-opc.h: Regenerate.
863 * mep-desc.h: Regenerate.
864 * mep-opc.h: Regenerate.
865 * mt-desc.h: Regenerate.
866 * mt-opc.h: Regenerate.
867 * or1k-desc.h: Regenerate.
868 * or1k-opc.h: Regenerate.
869 * xc16x-desc.h: Regenerate.
870 * xc16x-opc.h: Regenerate.
871 * xstormy16-desc.h: Regenerate.
872 * xstormy16-opc.h: Regenerate.
873
2571583a
AM		 8742017-01-02 Alan Modra <amodra@gmail.com>
875
876 Update year range in copyright notice of all files.
877
5c1ad6b5 878For older changes see ChangeLog-2016
3499769a 879\f
5c1ad6b5 880Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 881
882Copying and distribution of this file, with or without modification,
883are permitted in any medium without royalty provided the copyright
884notice and this notice are preserved.
885
886Local Variables:
887mode: change-log
888left-margin: 8
889fill-column: 74
890version-control: never
891End:
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