[thirdparty/binutils-gdb.git] / opcodes / ChangeLog

2020-01-17  Christian Biesinger  <cbiesinger@google.com>

	* opintl.h: Fix spelling error (seperate).

2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Add {vex} pseudo prefix.
	* i386-tbl.h: Regenerated.

2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
	(neon_opcodes): Likewise.
	(select_arm_features): Make sure we enable MVE bits when selecting
	armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
	any architecture.

2020-01-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl: Drop stale comment from XOP section.

2020-01-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
	(extractps): Add VexWIG to SSE2AVX forms.
	* i386-tbl.h: Re-generate.

2020-01-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
	Size64 from and use VexW1 on SSE2AVX forms.
	(vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
	VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
	* i386-tbl.h: Re-generate.

2020-01-15  Alan Modra  <amodra@gmail.com>

	* tic4x-dis.c (tic4x_version): Make unsigned long.
	(optab, optab_special, registernames): New file scope vars.
	(tic4x_print_register): Set up registernames rather than
	malloc'd registertable.
	(tic4x_disassemble): Delete optable and optable_special.  Use
	optab and optab_special instead.  Throw away old optab,
	optab_special and registernames when info->mach changes.

2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25377
	* z80-dis.c (suffix): Use .db instruction to generate double
	prefix.

2020-01-14  Alan Modra  <amodra@gmail.com>

	* z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
	values to unsigned before shifting.

2020-01-13  Thomas Troeger  <tstroege@gmx.de>

	* arm-dis.c (print_insn_arm): Fill in insn info fields for control
	flow instructions.
	(print_insn_thumb16, print_insn_thumb32): Likewise.
	(print_insn): Initialize the insn info.
	* i386-dis.c (print_insn): Initialize the insn info fields, and
	detect jumps.

2012-01-13  Claudiu Zissulescu <claziss@gmail.com>

	* arc-opc.c (C_NE): Make it required.

2012-01-13  Claudiu Zissulescu <claziss@gmail.com>

        * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
	reserved register name.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
	(print_insn_ns32k): Adjust ioffset for 'f' index_offset.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
	result of wasm_read_leb128 in a uint64_t and check that bits
	are not lost when copying to other locals.  Use uint32_t for
	most locals.  Use PRId64 when printing int64_t.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* score-dis.c: Formatting.
	* score7-dis.c: Formatting.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* score-dis.c (print_insn_score48): Use unsigned variables for
	unsigned values.  Don't left shift negative values.
	(print_insn_score32): Likewise.
	* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* tic4x-dis.c (tic4x_print_register): Remove dead code.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* fr30-ibld.c: Regenerate.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* xgate-dis.c (print_insn): Don't left shift signed value.
	(ripBits): Formatting, use 1u.

2020-01-10  Alan Modra  <amodra@gmail.com>

	* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
	* tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.

2020-01-10  Alan Modra  <amodra@gmail.com>

	* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
	and XRREG value earlier to avoid a shift with negative exponent.
	* m10200-dis.c (disassemble): Similarly.

2020-01-09  Nick Clifton  <nickc@redhat.com>

	PR 25224
	* z80-dis.c (ld_ii_ii): Use correct cast.

2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25224
	* z80-dis.c (ld_ii_ii): Use character constant when checking
	opcode byte value.

2020-01-09  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (SEP_Fixup): New.
	(SEP): Define.
	(dis386_twobyte): Use it for sysenter/sysexit.
	(enum x86_64_isa): Change amd64 enumerator to value 1.
	(OP_J): Compare isa64 against intel64 instead of amd64.
	* i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
	forms.
	* i386-tbl.h: Re-generate.

2020-01-08  Alan Modra  <amodra@gmail.com>

	* z8k-dis.c: Include libiberty.h
	(instr_data_s): Make max_fetched unsigned.
	(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
	Don't exceed byte_info bounds.
	(output_instr): Make num_bytes unsigned.
	(unpack_instr): Likewise for nibl_count and loop.
	* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
	idx unsigned.
	* z8k-opc.h: Regenerate.

2020-01-07  Shahab Vahedi  <shahab@synopsys.com>

	* arc-tbl.h (llock): Use 'LLOCK' as class.
	(llockd): Likewise.
	(scond): Use 'SCOND' as class.
	(scondd): Likewise.
	(llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
	(scondd): Likewise.

2020-01-06  Alan Modra  <amodra@gmail.com>

	* m32c-ibld.c: Regenerate.

2020-01-06  Alan Modra  <amodra@gmail.com>

	PR 25344
	* z80-dis.c (suffix): Don't use a local struct buffer copy.
	Peek at next byte to prevent recursion on repeated prefix bytes.
	Ensure uninitialised "mybuf" is not accessed.
	(print_insn_z80): Don't zero n_fetch and n_used here,..
	(print_insn_z80_buf): ..do it here instead.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* m32r-ibld.c: Regenerate.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* crx-dis.c (match_opcode): Avoid shift left of signed value.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* d30v-dis.c (print_insn): Avoid signed overflow in left shift.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Use
	SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
	forms of SUDOT and USDOT.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
	uzip{1,2}.
	* opcodes/aarch64-dis-2.c: Re-generate.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
	FMMLA encoding.
	* opcodes/aarch64-dis-2.c: Re-generate.

2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>

	* z80-dis.c: Add support for eZ80 and Z80 instructions.

2020-01-01  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2019
\f
Copyright (C) 2020 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
07f1f3aa CB	1	2020-01-17 Christian Biesinger <cbiesinger@google.com>
	2
	3	* opintl.h: Fix spelling error (seperate).
	4
42e04b36 L	5	2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
	6
	7	* i386-opc.tbl: Add {vex} pseudo prefix.
	8	* i386-tbl.h: Regenerated.
	9
2da2eaf4 AV	10	2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
	11
	12	PR 25376
	13	* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
	14	(neon_opcodes): Likewise.
	15	(select_arm_features): Make sure we enable MVE bits when selecting
	16	armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
	17	any architecture.
	18
d0849eed JB	19	2020-01-16 Jan Beulich <jbeulich@suse.com>
	20
	21	* i386-opc.tbl: Drop stale comment from XOP section.
	22
9cf70a44 JB	23	2020-01-16 Jan Beulich <jbeulich@suse.com>
	24
	25	* i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
	26	(extractps): Add VexWIG to SSE2AVX forms.
	27	* i386-tbl.h: Re-generate.
	28
4814632e JB	29	2020-01-16 Jan Beulich <jbeulich@suse.com>
	30
	31	* i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
	32	Size64 from and use VexW1 on SSE2AVX forms.
	33	(vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
	34	VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
	35	* i386-tbl.h: Re-generate.
	36
aad09917 AM	37	2020-01-15 Alan Modra <amodra@gmail.com>
	38
	39	* tic4x-dis.c (tic4x_version): Make unsigned long.
	40	(optab, optab_special, registernames): New file scope vars.
	41	(tic4x_print_register): Set up registernames rather than
	42	malloc'd registertable.
	43	(tic4x_disassemble): Delete optable and optable_special. Use
	44	optab and optab_special instead. Throw away old optab,
	45	optab_special and registernames when info->mach changes.
	46
7a6bf3be SB	47	2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
	48
	49	PR 25377
	50	* z80-dis.c (suffix): Use .db instruction to generate double
	51	prefix.
	52
ca1eaac0 AM	53	2020-01-14 Alan Modra <amodra@gmail.com>
	54
	55	* z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
	56	values to unsigned before shifting.
	57
1d67fe3b TT	58	2020-01-13 Thomas Troeger <tstroege@gmx.de>
	59
	60	* arm-dis.c (print_insn_arm): Fill in insn info fields for control
	61	flow instructions.
	62	(print_insn_thumb16, print_insn_thumb32): Likewise.
	63	(print_insn): Initialize the insn info.
	64	* i386-dis.c (print_insn): Initialize the insn info fields, and
	65	detect jumps.
	66
5e4f7e05 CZ	67	2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
	68
	69	* arc-opc.c (C_NE): Make it required.
	70
b9fe6b8a CZ	71	2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
	72
	73	* opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
	74	reserved register name.
	75
90dee485 AM	76	2020-01-13 Alan Modra <amodra@gmail.com>
	77
	78	* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
	79	(print_insn_ns32k): Adjust ioffset for 'f' index_offset.
	80
febda64f AM	81	2020-01-13 Alan Modra <amodra@gmail.com>
	82
	83	* wasm32-dis.c (print_insn_wasm32): Localise variables. Store
	84	result of wasm_read_leb128 in a uint64_t and check that bits
	85	are not lost when copying to other locals. Use uint32_t for
	86	most locals. Use PRId64 when printing int64_t.
	87
df08b588 AM	88	2020-01-13 Alan Modra <amodra@gmail.com>
	89
	90	* score-dis.c: Formatting.
	91	* score7-dis.c: Formatting.
	92
b2c759ce AM	93	2020-01-13 Alan Modra <amodra@gmail.com>
	94
	95	* score-dis.c (print_insn_score48): Use unsigned variables for
	96	unsigned values. Don't left shift negative values.
	97	(print_insn_score32): Likewise.
	98	* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
	99
5496abe1 AM	100	2020-01-13 Alan Modra <amodra@gmail.com>
	101
	102	* tic4x-dis.c (tic4x_print_register): Remove dead code.
	103
202e762b AM	104	2020-01-13 Alan Modra <amodra@gmail.com>
	105
	106	* fr30-ibld.c: Regenerate.
	107
7ef412cf AM	108	2020-01-13 Alan Modra <amodra@gmail.com>
	109
	110	* xgate-dis.c (print_insn): Don't left shift signed value.
	111	(ripBits): Formatting, use 1u.
	112
7f578b95 AM	113	2020-01-10 Alan Modra <amodra@gmail.com>
	114
	115	* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
	116	* tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
	117
441af85b AM	118	2020-01-10 Alan Modra <amodra@gmail.com>
	119
	120	* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
	121	and XRREG value earlier to avoid a shift with negative exponent.
	122	* m10200-dis.c (disassemble): Similarly.
	123
bce58db4 NC	124	2020-01-09 Nick Clifton <nickc@redhat.com>
	125
	126	PR 25224
	127	* z80-dis.c (ld_ii_ii): Use correct cast.
	128
40c75bc8 SB	129	2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
	130
	131	PR 25224
	132	* z80-dis.c (ld_ii_ii): Use character constant when checking
	133	opcode byte value.
	134
d835a58b JB	135	2020-01-09 Jan Beulich <jbeulich@suse.com>
	136
	137	* i386-dis.c (SEP_Fixup): New.
	138	(SEP): Define.
	139	(dis386_twobyte): Use it for sysenter/sysexit.
	140	(enum x86_64_isa): Change amd64 enumerator to value 1.
	141	(OP_J): Compare isa64 against intel64 instead of amd64.
	142	* i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
	143	forms.
	144	* i386-tbl.h: Re-generate.
	145
030a2e78 AM	146	2020-01-08 Alan Modra <amodra@gmail.com>
	147
	148	* z8k-dis.c: Include libiberty.h
	149	(instr_data_s): Make max_fetched unsigned.
	150	(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
	151	Don't exceed byte_info bounds.
	152	(output_instr): Make num_bytes unsigned.
	153	(unpack_instr): Likewise for nibl_count and loop.
	154	* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
	155	idx unsigned.
	156	* z8k-opc.h: Regenerate.
	157
bb82aefe SV	158	2020-01-07 Shahab Vahedi <shahab@synopsys.com>
	159
	160	* arc-tbl.h (llock): Use 'LLOCK' as class.
	161	(llockd): Likewise.
	162	(scond): Use 'SCOND' as class.
	163	(scondd): Likewise.
	164	(llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
	165	(scondd): Likewise.
	166
cc6aa1a6 AM	167	2020-01-06 Alan Modra <amodra@gmail.com>
	168
	169	* m32c-ibld.c: Regenerate.
	170
660e62b1 AM	171	2020-01-06 Alan Modra <amodra@gmail.com>
	172
	173	PR 25344
	174	* z80-dis.c (suffix): Don't use a local struct buffer copy.
	175	Peek at next byte to prevent recursion on repeated prefix bytes.
	176	Ensure uninitialised "mybuf" is not accessed.
	177	(print_insn_z80): Don't zero n_fetch and n_used here,..
	178	(print_insn_z80_buf): ..do it here instead.
	179
c9ae58fe AM	180	2020-01-04 Alan Modra <amodra@gmail.com>
	181
	182	* m32r-ibld.c: Regenerate.
	183
5f57d4ec AM	184	2020-01-04 Alan Modra <amodra@gmail.com>
	185
	186	* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
	187
2c5c1196 AM	188	2020-01-04 Alan Modra <amodra@gmail.com>
	189
	190	* crx-dis.c (match_opcode): Avoid shift left of signed value.
	191
2e98c6c5 AM	192	2020-01-04 Alan Modra <amodra@gmail.com>
	193
	194	* d30v-dis.c (print_insn): Avoid signed overflow in left shift.
	195
567dfba2 JB	196	2020-01-03 Jan Beulich <jbeulich@suse.com>
567dfba2 JB	197
5437a02a JB	198	* aarch64-tbl.h (aarch64_opcode_table): Use
	199	SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
	200
	201	2020-01-03 Jan Beulich <jbeulich@suse.com>
	202
	203	* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2 JB	204	forms of SUDOT and USDOT.
567dfba2 JB	205
8c45011a JB	206	2020-01-03 Jan Beulich <jbeulich@suse.com>
8c45011a JB	207
5437a02a	208	* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a JB	209	uzip{1,2}.
	210	* opcodes/aarch64-dis-2.c: Re-generate.
	211
f4950f76 JB	212	2020-01-03 Jan Beulich <jbeulich@suse.com>
f4950f76 JB	213
5437a02a	214	* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76 JB	215	FMMLA encoding.
	216	* opcodes/aarch64-dis-2.c: Re-generate.
	217
6655dba2 SB	218	2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
	219
	220	* z80-dis.c: Add support for eZ80 and Z80 instructions.
	221
b14ce8bf AM	222	2020-01-01 Alan Modra <amodra@gmail.com>
	223
	224	Update year range in copyright notice of all files.
	225
0b114740	226	For older changes see ChangeLog-2019
3499769a	227	\f
0b114740	228	Copyright (C) 2020 Free Software Foundation, Inc.
3499769a AM	229
	230	Copying and distribution of this file, with or without modification,
	231	are permitted in any medium without royalty provided the copyright
	232	notice and this notice are preserved.
	233
	234	Local Variables:
	235	mode: change-log
	236	left-margin: 8
	237	fill-column: 74
	238	version-control: never
	239	End: