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Updated Serbian and Russian translations for various sub-directories
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
79ddc884
NC		 12020-08-12 Nick Clifton <nickc@redhat.com>
2
3 * po/sr.po: Updated Serbian translation.
4
08770ec2
AM		 52020-08-11 Alan Modra <amodra@gmail.com>
6
7 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
8
f7cb161e
PW		 92020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
10
11 * aarch64-opc.c (aarch64_print_operand):
12 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
13 (aarch64_sys_reg_supported_p): Function removed.
14 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
15 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
16 into this function.
17
3eb65174
AM		 182020-08-10 Alan Modra <amodra@gmail.com>
19
20 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
21 instructions.
22
8b2742a1
AM		 232020-08-10 Alan Modra <amodra@gmail.com>
24
25 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
26 Enable icbt for power5, miso for power8.
27
5fbec329
AM		 282020-08-10 Alan Modra <amodra@gmail.com>
29
30 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
31 mtvsrd, and similarly for mfvsrd.
32
563a3225
CG		 332020-08-04 Christian Groessler <chris@groessler.org>
34 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
35
36 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
37 opcodes (special "out" to absolute address).
38 * z8k-opc.h: Regenerate.
39
41eb8e88
L		 402020-07-30 H.J. Lu <hongjiu.lu@intel.com>
41
42 PR gas/26305
43 * i386-opc.h (Prefix_Disp8): New.
44 (Prefix_Disp16): Likewise.
45 (Prefix_Disp32): Likewise.
46 (Prefix_Load): Likewise.
47 (Prefix_Store): Likewise.
48 (Prefix_VEX): Likewise.
49 (Prefix_VEX3): Likewise.
50 (Prefix_EVEX): Likewise.
51 (Prefix_REX): Likewise.
52 (Prefix_NoOptimize): Likewise.
53 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
54 * i386-tbl.h: Regenerated.
55
98116973
AA		 562020-07-29 Andreas Arnez <arnez@linux.ibm.com>
57
58 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
59 default case with abort() instead of printing an error message and
60 continuing, to avoid a maybe-uninitialized warning.
61
2dddfa20
NC		 622020-07-24 Nick Clifton <nickc@redhat.com>
63
64 * po/de.po: Updated German translation.
65
bf4ba07c
JB		 662020-07-21 Jan Beulich <jbeulich@suse.com>
67
68 * i386-dis.c (OP_E_memory): Revert previous change.
69
04c662e2
L		 702020-07-15 H.J. Lu <hongjiu.lu@intel.com>
71
72 PR gas/26237
73 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
74 without base nor index registers.
75
f0e8d0ba
JB		 762020-07-15 Jan Beulich <jbeulich@suse.com>
77
78 * i386-dis.c (putop): Move 'V' and 'W' handling.
79
c3f5525f
JB		 802020-07-15 Jan Beulich <jbeulich@suse.com>
81
82 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
83 construct for push/pop of register.
84 (putop): Honor cond when handling 'P'. Drop handling of plain
85 'V'.
86
36938cab
JB		 872020-07-15 Jan Beulich <jbeulich@suse.com>
88
89 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
90 description. Drop '&' description. Use P for push of immediate,
91 pushf/popf, enter, and leave. Use %LP for lret/retf.
92 (dis386_twobyte): Use P for push/pop of fs/gs.
93 (reg_table): Use P for push/pop. Use @ for near call/jmp.
94 (x86_64_table): Use P for far call/jmp.
95 (putop): Drop handling of 'U' and '&'. Move and adjust handling
96 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
97 labels.
98 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
99 and dqw_mode (unconditional).
100
8e58ef80
L		 1012020-07-14 H.J. Lu <hongjiu.lu@intel.com>
102
103 PR gas/26237
104 * i386-dis.c (OP_E_memory): Without base nor index registers,
105 32-bit displacement to 64 bits.
106
570b0ed6
CZ		 1072020-07-14 Claudiu Zissulescu <claziss@gmail.com>
108
109 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
110 faulty double register pair is detected.
111
bfbd9438
JB		 1122020-07-14 Jan Beulich <jbeulich@suse.com>
113
114 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
115
78467458
JB		 1162020-07-14 Jan Beulich <jbeulich@suse.com>
117
118 * i386-dis.c (OP_R, Rm): Delete.
119 (MOD_0F24, MOD_0F26): Rename to ...
120 (X86_64_0F24, X86_64_0F26): ... respectively.
121 (dis386): Update 'L' and 'Z' comments.
122 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
123 table references.
124 (mod_table): Move opcode 0F24 and 0F26 entries ...
125 (x86_64_table): ... here.
126 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
127 'Z' case block.
128
464d2b65
JB		 1292020-07-14 Jan Beulich <jbeulich@suse.com>
130
131 * i386-dis.c (Rd, Rdq, MaskR): Delete.
132 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
133 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
134 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
135 MOD_EVEX_0F387C): New enumerators.
136 (reg_table): Use Edq for rdssp.
137 (prefix_table): Use Edq for incssp.
138 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
139 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
140 ktest*, and kshift*. Use Edq / MaskE for kmov*.
141 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
142 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
143 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
144 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
145 0F3828_P_1 and 0F3838_P_1.
146 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
147 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
148
035e7389
JB		 1492020-07-14 Jan Beulich <jbeulich@suse.com>
150
151 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
152 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
153 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
154 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
155 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
156 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
157 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
158 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
159 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
160 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
161 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
162 (reg_table, prefix_table, three_byte_table, vex_table,
163 vex_len_table, mod_table, rm_table): Replace / remove respective
164 entries.
165 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
166 of PREFIX_DATA in used_prefixes.
167
bb5b3501
JB		 1682020-07-14 Jan Beulich <jbeulich@suse.com>
169
170 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
171 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
172 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
173 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
174 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
175 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
176 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
177 VEX_W_0F3A33_L_0): Delete.
178 (dis386): Adjust "BW" description.
179 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
180 0F3A31, 0F3A32, and 0F3A33.
181 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
182 entries.
183 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
184 entries.
185
7531c613
JB		 1862020-07-14 Jan Beulich <jbeulich@suse.com>
187
188 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
189 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
190 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
191 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
192 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
193 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
194 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
195 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
196 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
197 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
198 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
199 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
200 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
201 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
202 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
203 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
204 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
205 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
206 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
207 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
208 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
209 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
210 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
211 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
212 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
213 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
214 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
215 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
216 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
217 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
218 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
219 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
220 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
221 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
222 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
223 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
224 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
225 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
226 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
227 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
228 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
229 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
230 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
231 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
232 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
233 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
234 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
235 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
236 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
237 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
238 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
239 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
240 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
241 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
242 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
243 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
244 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
245 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
246 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
247 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
248 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
249 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
250 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
251 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
252 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
253 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
254 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
255 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
256 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
257 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
258 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
259 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
260 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
261 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
262 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
263 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
264 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
265 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
266 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
267 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
268 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
269 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
270 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
271 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
272 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
273 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
274 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
275 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
276 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
277 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
278 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
279 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
280 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
281 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
282 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
283 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
284 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
285 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
286 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
287 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
288 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
289 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
290 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
291 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
292 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
293 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
294 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
295 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
296 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
297 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
298 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
299 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
300 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
301 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
302 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
303 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
304 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
305 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
306 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
307 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
308 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
309 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
310 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
311 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
312 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
313 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
314 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
315 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
316 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
317 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
318 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
319 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
320 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
321 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
322 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
323 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
324 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
325 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
326 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
327 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
328 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
329 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
330 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
331 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
332 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
333 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
334 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
335 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
336 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
337 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
338 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
339 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
340 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
341 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
342 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
343 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
344 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
345 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
346 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
347 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
348 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
349 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
350 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
351 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
352 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
353 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
354 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
355 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
356 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
357 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
358 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
359 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
360 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
361 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
362 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
363 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
364 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
365 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
366 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
367 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
368 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
369 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
370 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
371 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
372 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
373 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
374 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
375 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
376 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
377 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
378 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
379 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
380 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
381 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
382 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
383 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
384 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
385 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
386 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
387 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
388 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
389 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
390 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
391 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
392 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
393 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
394 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
395 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
396 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
397 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
398 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
399 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
400 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
401 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
402 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
403 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
404 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
405 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
406 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
407 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
408 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
409 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
410 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
411 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
412 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
413 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
414 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
415 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
416 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
417 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
418 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
419 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
420 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
421 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
422 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
423 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
424 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
425 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
426 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
427 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
428 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
429 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
430 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
431 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
432 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
433 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
434 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
435 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
436 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
437 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
438 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
439 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
440 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
441 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
442 EVEX_W_0F3A72_P_2): Rename to ...
443 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
444 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
445 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
446 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
447 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
448 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
449 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
450 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
451 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
452 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
453 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
454 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
455 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
456 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
457 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
458 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
459 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
460 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
461 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
462 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
463 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
464 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
465 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
466 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
467 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
468 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
469 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
470 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
471 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
472 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
473 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
474 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
475 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
476 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
477 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
478 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
479 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
480 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
481 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
482 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
483 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
484 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
485 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
486 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
487 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
488 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
489 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
490 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
491 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
492 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
493 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
494 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
495 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
496 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
497 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
498 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
499 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
500 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
501 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
502 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
503 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
504 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
505 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
506 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
507 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
508 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
509 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
510 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
511 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
512 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
513 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
514 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
515 respectively.
516 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
517 vex_w_table, mod_table): Replace / remove respective entries.
518 (print_insn): Move up dp->prefix_requirement handling. Handle
519 PREFIX_DATA.
520 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
521 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
522 Replace / remove respective entries.
523
17d3c7ec
JB		 5242020-07-14 Jan Beulich <jbeulich@suse.com>
525
526 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
527 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
528 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
529 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
530 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
531 the latter two.
532 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
533 0F2C, 0F2D, 0F2E, and 0F2F.
534 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
535 0F2F table entries.
536
41f5efc6
JB		 5372020-07-14 Jan Beulich <jbeulich@suse.com>
538
539 * i386-dis.c (OP_VexR, VexScalarR): New.
540 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
541 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
542 need_vex_reg): Delete.
543 (prefix_table): Replace VexScalar by VexScalarR and
544 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
545 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
546 (vex_len_table): Replace EXqVexScalarS by EXqS.
547 (get_valid_dis386): Don't set need_vex_reg.
548 (print_insn): Don't initialize need_vex_reg.
549 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
550 q_scalar_swap_mode cases.
551 (OP_EX): Don't check for d_scalar_swap_mode and
552 q_scalar_swap_mode.
553 (OP_VEX): Done check need_vex_reg.
554 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
555 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
556 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
557
89e65d17
JB		 5582020-07-14 Jan Beulich <jbeulich@suse.com>
559
560 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
561 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
562 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
563 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
564 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
565 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
566 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
567 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
568 (vex_table): Replace Vex128 by Vex.
569 (vex_len_table): Likewise. Adjust referenced enum names.
570 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
571 referenced enum names.
572 (OP_VEX): Drop vex128_mode and vex256_mode cases.
573 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
574
492a76aa
JB		 5752020-07-14 Jan Beulich <jbeulich@suse.com>
576
577 * i386-dis.c (dis386): "LW" description now applies to "DQ".
578 (putop): Handle "DQ". Don't handle "LW" anymore.
579 (prefix_table, mod_table): Replace %LW by %DQ.
580 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
581
059edf8b
JB		 5822020-07-14 Jan Beulich <jbeulich@suse.com>
583
584 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
585 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
586 d_scalar_swap_mode case handling. Move shift adjsutment into
587 the case its applicable to.
588
4726e9a4
JB		 5892020-07-14 Jan Beulich <jbeulich@suse.com>
590
591 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
592 (EXbScalar, EXwScalar): Fold to ...
593 (EXbwUnit): ... this.
594 (b_scalar_mode, w_scalar_mode): Fold to ...
595 (bw_unit_mode): ... this.
596 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
597 w_scalar_mode handling by bw_unit_mode one.
598 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
599 ...
600 * i386-dis-evex-prefix.h: ... here.
601
b24d668c
JB		 6022020-07-14 Jan Beulich <jbeulich@suse.com>
603
604 * i386-dis.c (PCMPESTR_Fixup): Delete.
605 (dis386): Adjust "LQ" description.
606 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
607 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
608 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
609 vpcmpestrm, and vpcmpestri.
610 (putop): Honor "cond" when handling LQ.
611 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
612 vcvtsi2ss and vcvtusi2ss.
613 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
614 vcvtsi2sd and vcvtusi2sd.
615
c4de7606
JB		 6162020-07-14 Jan Beulich <jbeulich@suse.com>
617
618 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
619 (simd_cmp_op): Add const.
620 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
621 (CMP_Fixup): Handle VEX case.
622 (prefix_table): Replace VCMP by CMP.
623 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
624
9ab00b61
JB		 6252020-07-14 Jan Beulich <jbeulich@suse.com>
626
627 * i386-dis.c (MOVBE_Fixup): Delete.
628 (Mv): Define.
629 (prefix_table): Use Mv for movbe entries.
630
2875b28a
JB		 6312020-07-14 Jan Beulich <jbeulich@suse.com>
632
633 * i386-dis.c (CRC32_Fixup): Delete.
634 (prefix_table): Use Eb/Ev for crc32 entries.
635
e184e611
JB		 6362020-07-14 Jan Beulich <jbeulich@suse.com>
637
638 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
639 Conditionalize invocations of "USED_REX (0)".
640
e8b5d5f9
JB		 6412020-07-14 Jan Beulich <jbeulich@suse.com>
642
643 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
644 CH, DH, BH, AX, DX): Delete.
645 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
646 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
647 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
648
260cd341
LC		 6492020-07-10 Lili Cui <lili.cui@intel.com>
650
651 * i386-dis.c (TMM): New.
652 (EXtmm): Likewise.
653 (VexTmm): Likewise.
654 (MVexSIBMEM): Likewise.
655 (tmm_mode): Likewise.
656 (vex_sibmem_mode): Likewise.
657 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
658 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
659 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
660 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
661 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
662 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
663 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
664 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
665 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
666 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
667 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
668 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
669 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
670 (PREFIX_VEX_0F3849_X86_64): Likewise.
671 (PREFIX_VEX_0F384B_X86_64): Likewise.
672 (PREFIX_VEX_0F385C_X86_64): Likewise.
673 (PREFIX_VEX_0F385E_X86_64): Likewise.
674 (X86_64_VEX_0F3849): Likewise.
675 (X86_64_VEX_0F384B): Likewise.
676 (X86_64_VEX_0F385C): Likewise.
677 (X86_64_VEX_0F385E): Likewise.
678 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
679 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
680 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
681 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
682 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
683 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
684 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
685 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
686 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
687 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
688 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
689 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
690 (VEX_W_0F3849_X86_64_P_0): Likewise.
691 (VEX_W_0F3849_X86_64_P_2): Likewise.
692 (VEX_W_0F3849_X86_64_P_3): Likewise.
693 (VEX_W_0F384B_X86_64_P_1): Likewise.
694 (VEX_W_0F384B_X86_64_P_2): Likewise.
695 (VEX_W_0F384B_X86_64_P_3): Likewise.
696 (VEX_W_0F385C_X86_64_P_1): Likewise.
697 (VEX_W_0F385E_X86_64_P_0): Likewise.
698 (VEX_W_0F385E_X86_64_P_1): Likewise.
699 (VEX_W_0F385E_X86_64_P_2): Likewise.
700 (VEX_W_0F385E_X86_64_P_3): Likewise.
701 (names_tmm): Likewise.
702 (att_names_tmm): Likewise.
703 (intel_operand_size): Handle void_mode.
704 (OP_XMM): Handle tmm_mode.
705 (OP_EX): Likewise.
706 (OP_VEX): Likewise.
707 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
708 CpuAMX_BF16 and CpuAMX_TILE.
709 (operand_type_shorthands): Add RegTMM.
710 (operand_type_init): Likewise.
711 (operand_types): Add Tmmword.
712 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
713 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
714 * i386-opc.h (CpuAMX_INT8): New.
715 (CpuAMX_BF16): Likewise.
716 (CpuAMX_TILE): Likewise.
717 (SIBMEM): Likewise.
718 (Tmmword): Likewise.
719 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
720 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
721 (i386_operand_type): Add tmmword.
722 * i386-opc.tbl: Add AMX instructions.
723 * i386-reg.tbl: Add AMX registers.
724 * i386-init.h: Regenerated.
725 * i386-tbl.h: Likewise.
726
467bbef0
JB		 7272020-07-08 Jan Beulich <jbeulich@suse.com>
728
729 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
730 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
731 Rename to ...
732 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
733 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
734 respectively.
735 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
736 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
737 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
738 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
739 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
740 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
741 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
742 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
743 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
744 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
745 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
746 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
747 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
748 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
749 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
750 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
751 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
752 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
753 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
754 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
755 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
756 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
757 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
758 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
759 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
760 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
761 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
762 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
763 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
764 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
765 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
766 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
767 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
768 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
769 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
770 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
771 (reg_table): Re-order XOP entries. Adjust their operands.
772 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
773 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
774 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
775 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
776 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
777 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
778 entries by references ...
779 (vex_len_table): ... to resepctive new entries here. For several
780 new and existing entries reference ...
781 (vex_w_table): ... new entries here.
782 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
783
6384fd9e
JB		 7842020-07-08 Jan Beulich <jbeulich@suse.com>
785
786 * i386-dis.c (XMVexScalarI4): Define.
787 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
788 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
789 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
790 (vex_len_table): Move scalar FMA4 entries ...
791 (prefix_table): ... here.
792 (OP_REG_VexI4): Handle scalar_mode.
793 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
794 * i386-tbl.h: Re-generate.
795
e6123d0c
JB		 7962020-07-08 Jan Beulich <jbeulich@suse.com>
797
798 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
799 Vex_2src_2): Delete.
800 (OP_VexW, VexW): New.
801 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
802 for shifts and rotates by register.
803
93abb146
JB		 8042020-07-08 Jan Beulich <jbeulich@suse.com>
805
806 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
807 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
808 OP_EX_VexReg): Delete.
809 (OP_VexI4, VexI4): New.
810 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
811 (prefix_table): ... here.
812 (print_insn): Drop setting of vex_w_done.
813
b13b1bc0
JB		 8142020-07-08 Jan Beulich <jbeulich@suse.com>
815
816 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
817 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
818 (xop_table): Replace operands of 4-operand insns.
819 (OP_REG_VexI4): Move VEX.W based operand swaping here.
820
f337259f
CZ		 8212020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
822
823 * arc-opc.c (insert_rbd): New function.
824 (RBD): Define.
825 (RBDdup): Likewise.
826 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
827 instructions.
828
931452b6
JB		 8292020-07-07 Jan Beulich <jbeulich@suse.com>
830
831 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
832 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
833 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
834 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
835 Delete.
836 (putop): Handle "BW".
837 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
838 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
839 and 0F3A3F ...
840 * i386-dis-evex-prefix.h: ... here.
841
b5b098c2
JB		 8422020-07-06 Jan Beulich <jbeulich@suse.com>
843
844 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
845 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
846 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
847 VEX_W_0FXOP_09_83): New enumerators.
848 (xop_table): Reference the above.
849 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
850 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
851 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
852 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
853
21a3faeb
JB		 8542020-07-06 Jan Beulich <jbeulich@suse.com>
855
856 * i386-dis.c (EVEX_W_0F3838_P_1,
857 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
858 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
859 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
860 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
861 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
862 (putop): Centralize management of last[]. Delete SAVE_LAST.
863 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
864 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
865 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
866 * i386-dis-evex-prefix.h: here.
867
bc152a17
JB		 8682020-07-06 Jan Beulich <jbeulich@suse.com>
869
870 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
871 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
872 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
873 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
874 enumerators.
875 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
876 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
877 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
878 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
879 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
880 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
881 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
882 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
883 these, respectively.
884 * i386-dis-evex-len.h: Adjust comments.
885 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
886 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
887 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
888 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
889 MOD_EVEX_0F385B_P_2_W_1 table entries.
890 * i386-dis-evex-w.h: Reference mod_table[] for
891 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
892 EVEX_W_0F385B_P_2.
893
c82a99a0
JB		 8942020-07-06 Jan Beulich <jbeulich@suse.com>
895
896 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
897 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
898 EXymm.
899 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
900 Likewise. Mark 256-bit entries invalid.
901
fedfb81e
JB		 9022020-07-06 Jan Beulich <jbeulich@suse.com>
903
904 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
905 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
906 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
907 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
908 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
909 PREFIX_EVEX_0F382B): Delete.
910 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
911 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
912 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
913 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
914 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
915 to ...
916 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
917 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
918 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
919 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
920 respectively.
921 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
922 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
923 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
924 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
925 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
926 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
927 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
928 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
929 PREFIX_EVEX_0F382B): Remove table entries.
930 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
931 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
932 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
933
3a57774c
JB		 9342020-07-06 Jan Beulich <jbeulich@suse.com>
935
936 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
937 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
938 enumerators.
939 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
940 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
941 EVEX_LEN_0F3A01_P_2_W_1 table entries.
942 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
943 entries.
944
e74d9fa9
JB		 9452020-07-06 Jan Beulich <jbeulich@suse.com>
946
947 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
948 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
949 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
950 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
951 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
952 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
953 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
954 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
955 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
956 entries.
957
6431c801
JB		 9582020-07-06 Jan Beulich <jbeulich@suse.com>
959
960 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
961 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
962 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
963 respectively.
964 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
965 entries.
966 * i386-dis-evex.h (evex_table): Reference VEX table entry for
967 opcode 0F3A1D.
968 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
969 entry.
970 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
971
6df22cf6
JB		 9722020-07-06 Jan Beulich <jbeulich@suse.com>
973
974 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
975 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
976 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
977 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
978 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
979 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
980 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
981 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
982 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
983 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
984 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
985 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
986 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
987 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
988 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
989 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
990 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
991 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
992 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
993 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
994 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
995 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
996 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
997 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
998 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
999 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1000 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1001 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1002 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1003 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1004 (prefix_table): Add EXxEVexR to FMA table entries.
1005 (OP_Rounding): Move abort() invocation.
1006 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1007 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1008 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1009 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1010 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1011 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1012 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1013 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1014 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1015 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1016 0F3ACE, 0F3ACF.
1017 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1018 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1019 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1020 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1021 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1022 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1023 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1024 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1025 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1026 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1027 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1028 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1029 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1030 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1031 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1032 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1033 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1034 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1035 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1036 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1037 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1038 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1039 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1040 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1041 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1042 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1043 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1044 Delete table entries.
1045 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1046 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1047 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1048 Likewise.
1049
39e0f456
JB		 10502020-07-06 Jan Beulich <jbeulich@suse.com>
1051
1052 * i386-dis.c (EXqScalarS): Delete.
1053 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1054 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1055
5b872f7d
JB		 10562020-07-06 Jan Beulich <jbeulich@suse.com>
1057
1058 * i386-dis.c (safe-ctype.h): Include.
1059 (EXdScalar, EXqScalar): Delete.
1060 (d_scalar_mode, q_scalar_mode): Delete.
1061 (prefix_table, vex_len_table): Use EXxmm_md in place of
1062 EXdScalar and EXxmm_mq in place of EXqScalar.
1063 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1064 d_scalar_mode and q_scalar_mode.
1065 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1066 (vmovsd): Use EXxmm_mq.
1067
ddc73fa9
NC		 10682020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1069
1070 PR 26204
1071 * arc-dis.c: Fix spelling mistake.
1072 * po/opcodes.pot: Regenerate.
1073
17550be7
NC		 10742020-07-06 Nick Clifton <nickc@redhat.com>
1075
1076 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1077 * po/uk.po: Updated Ukranian translation.
1078
b19d852d
NC		 10792020-07-04 Nick Clifton <nickc@redhat.com>
1080
1081 * configure: Regenerate.
1082 * po/opcodes.pot: Regenerate.
1083
b115b9fd
NC		 10842020-07-04 Nick Clifton <nickc@redhat.com>
1085
1086 Binutils 2.35 branch created.
1087
c2ecccb3
L		 10882020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1089
1090 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1091 * i386-opc.h (VexSwapSources): New.
1092 (i386_opcode_modifier): Add vexswapsources.
1093 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1094 with two source operands swapped.
1095 * i386-tbl.h: Regenerated.
1096
08ccfccf
NC		 10972020-06-30 Nelson Chu <nelson.chu@sifive.com>
1098
1099 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1100 unprivileged CSR can also be initialized.
1101
279edac5
AM		 11022020-06-29 Alan Modra <amodra@gmail.com>
1103
1104 * arm-dis.c: Use C style comments.
1105 * cr16-opc.c: Likewise.
1106 * ft32-dis.c: Likewise.
1107 * moxie-opc.c: Likewise.
1108 * tic54x-dis.c: Likewise.
1109 * s12z-opc.c: Remove useless comment.
1110 * xgate-dis.c: Likewise.
1111
e978ad62
L		 11122020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1113
1114 * i386-opc.tbl: Add a blank line.
1115
63112cd6
L		 11162020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1117
1118 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1119 (VecSIB128): Renamed to ...
1120 (VECSIB128): This.
1121 (VecSIB256): Renamed to ...
1122 (VECSIB256): This.
1123 (VecSIB512): Renamed to ...
1124 (VECSIB512): This.
1125 (VecSIB): Renamed to ...
1126 (SIB): This.
1127 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 1128 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 1129 (VecSIB256): Likewise.
1130 (VecSIB512): Likewise.
79b32e73 1131 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 1132 and VecSIB512, respectively.
1133
d1c36125
JB		 11342020-06-26 Jan Beulich <jbeulich@suse.com>
1135
1136 * i386-dis.c: Adjust description of I macro.
1137 (x86_64_table): Drop use of I.
1138 (float_mem): Replace use of I.
1139 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1140
2a1bb84c
JB		 11412020-06-26 Jan Beulich <jbeulich@suse.com>
1142
1143 * i386-dis.c: (print_insn): Avoid straight assignment to
1144 priv.orig_sizeflag when processing -M sub-options.
1145
8f570d62
JB		 11462020-06-25 Jan Beulich <jbeulich@suse.com>
1147
1148 * i386-dis.c: Adjust description of J macro.
1149 (dis386, x86_64_table, mod_table): Replace J.
1150 (putop): Remove handling of J.
1151
464dc4af
JB		 11522020-06-25 Jan Beulich <jbeulich@suse.com>
1153
1154 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1155
589958d6
JB		 11562020-06-25 Jan Beulich <jbeulich@suse.com>
1157
1158 * i386-dis.c: Adjust description of "LQ" macro.
1159 (dis386_twobyte): Use LQ for sysret.
1160 (putop): Adjust handling of LQ.
1161
39ff0b81
NC		 11622020-06-22 Nelson Chu <nelson.chu@sifive.com>
1163
1164 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1165 * riscv-dis.c: Include elfxx-riscv.h.
1166
d27c357a
JB		 11672020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1168
1169 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1170
6fde587f
CL		 11712020-06-17 Lili Cui <lili.cui@intel.com>
1172
1173 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1174
efe30057
L		 11752020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1176
1177 PR gas/26115
1178 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1179 * i386-opc.tbl: Likewise.
1180 * i386-tbl.h: Regenerated.
1181
d8af286f
NC		 11822020-06-12 Nelson Chu <nelson.chu@sifive.com>
1183
1184 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1185
14962256
AC		 11862020-06-11 Alex Coplan <alex.coplan@arm.com>
1187
1188 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1189 (SR_CORE): Likewise.
1190 (SR_FEAT): Likewise.
1191 (SR_RNG): Likewise.
1192 (SR_V8_1): Likewise.
1193 (SR_V8_2): Likewise.
1194 (SR_V8_3): Likewise.
1195 (SR_V8_4): Likewise.
1196 (SR_PAN): Likewise.
1197 (SR_RAS): Likewise.
1198 (SR_SSBS): Likewise.
1199 (SR_SVE): Likewise.
1200 (SR_ID_PFR2): Likewise.
1201 (SR_PROFILE): Likewise.
1202 (SR_MEMTAG): Likewise.
1203 (SR_SCXTNUM): Likewise.
1204 (aarch64_sys_regs): Refactor to store feature information in the table.
1205 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1206 that now describe their own features.
1207 (aarch64_pstatefield_supported_p): Likewise.
1208
f9630fa6
L		 12092020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1210
1211 * i386-dis.c (prefix_table): Fix a typo in comments.
1212
73239888
JB		 12132020-06-09 Jan Beulich <jbeulich@suse.com>
1214
1215 * i386-dis.c (rex_ignored): Delete.
1216 (ckprefix): Drop rex_ignored initialization.
1217 (get_valid_dis386): Drop setting of rex_ignored.
1218 (print_insn): Drop checking of rex_ignored. Don't record data
1219 size prefix as used with VEX-and-alike encodings.
1220
18897deb
JB		 12212020-06-09 Jan Beulich <jbeulich@suse.com>
1222
1223 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1224 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1225 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1226 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1227 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1228 VEX_0F12, and VEX_0F16.
1229 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1230 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1231 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1232 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1233 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1234 MOD_VEX_0F16_PREFIX_2 entries.
1235
97e6786a
JB		 12362020-06-09 Jan Beulich <jbeulich@suse.com>
1237
1238 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1239 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1240 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1241 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1242 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1243 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1244 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1245 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1246 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1247 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1248 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1249 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1250 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1251 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1252 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1253 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1254 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1255 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1256 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1257 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1258 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1259 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1260 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1261 EVEX_W_0FC6_P_2): Delete.
1262 (print_insn): Add EVEX.W vs embedded prefix consistency check
1263 to prefix validation.
1264 * i386-dis-evex.h (evex_table): Don't further descend for
1265 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1266 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1267 and 0F2B.
1268 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1269 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1270 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1271 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1272 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1273 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1274 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1275 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1276 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1277 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1278 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1279 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1280 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1281 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1282 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1283 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1284 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1285 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1286 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1287 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1288 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1289 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1290 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1291 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1292 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1293 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1294 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1295
bf926894
JB		 12962020-06-09 Jan Beulich <jbeulich@suse.com>
1297
1298 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1299 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1300 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1301 vmovmskpX.
1302 (print_insn): Drop pointless check against bad_opcode. Split
1303 prefix validation into legacy and VEX-and-alike parts.
1304 (putop): Re-work 'X' macro handling.
1305
a5aaedb9
JB		 13062020-06-09 Jan Beulich <jbeulich@suse.com>
1307
1308 * i386-dis.c (MOD_0F51): Rename to ...
1309 (MOD_0F50): ... this.
1310
26417f19
AC		 13112020-06-08 Alex Coplan <alex.coplan@arm.com>
1312
1313 * arm-dis.c (arm_opcodes): Add dfb.
1314 (thumb32_opcodes): Add dfb.
1315
8a6fb3f9
JB		 13162020-06-08 Jan Beulich <jbeulich@suse.com>
1317
1318 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1319
1424c35d
AM		 13202020-06-06 Alan Modra <amodra@gmail.com>
1321
1322 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1323
d3d1cc7b
AM		 13242020-06-05 Alan Modra <amodra@gmail.com>
1325
1326 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1327 size is large enough.
1328
d8740be1
JM		 13292020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1330
1331 * disassemble.c (disassemble_init_for_target): Set endian_code for
1332 bpf targets.
1333 * bpf-desc.c: Regenerate.
1334 * bpf-opc.c: Likewise.
1335 * bpf-dis.c: Likewise.
1336
e9bffec9
JM		 13372020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1338
1339 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1340 (cgen_put_insn_value): Likewise.
1341 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1342 * cgen-dis.in (print_insn): Likewise.
1343 * cgen-ibld.in (insert_1): Likewise.
1344 (insert_1): Likewise.
1345 (insert_insn_normal): Likewise.
1346 (extract_1): Likewise.
1347 * bpf-dis.c: Regenerate.
1348 * bpf-ibld.c: Likewise.
1349 * bpf-ibld.c: Likewise.
1350 * cgen-dis.in: Likewise.
1351 * cgen-ibld.in: Likewise.
1352 * cgen-opc.c: Likewise.
1353 * epiphany-dis.c: Likewise.
1354 * epiphany-ibld.c: Likewise.
1355 * fr30-dis.c: Likewise.
1356 * fr30-ibld.c: Likewise.
1357 * frv-dis.c: Likewise.
1358 * frv-ibld.c: Likewise.
1359 * ip2k-dis.c: Likewise.
1360 * ip2k-ibld.c: Likewise.
1361 * iq2000-dis.c: Likewise.
1362 * iq2000-ibld.c: Likewise.
1363 * lm32-dis.c: Likewise.
1364 * lm32-ibld.c: Likewise.
1365 * m32c-dis.c: Likewise.
1366 * m32c-ibld.c: Likewise.
1367 * m32r-dis.c: Likewise.
1368 * m32r-ibld.c: Likewise.
1369 * mep-dis.c: Likewise.
1370 * mep-ibld.c: Likewise.
1371 * mt-dis.c: Likewise.
1372 * mt-ibld.c: Likewise.
1373 * or1k-dis.c: Likewise.
1374 * or1k-ibld.c: Likewise.
1375 * xc16x-dis.c: Likewise.
1376 * xc16x-ibld.c: Likewise.
1377 * xstormy16-dis.c: Likewise.
1378 * xstormy16-ibld.c: Likewise.
1379
b3db6d07
JM		 13802020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1381
1382 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1383 (print_insn_): Handle instruction endian.
1384 * bpf-dis.c: Regenerate.
1385 * bpf-desc.c: Regenerate.
1386 * epiphany-dis.c: Likewise.
1387 * epiphany-desc.c: Likewise.
1388 * fr30-dis.c: Likewise.
1389 * fr30-desc.c: Likewise.
1390 * frv-dis.c: Likewise.
1391 * frv-desc.c: Likewise.
1392 * ip2k-dis.c: Likewise.
1393 * ip2k-desc.c: Likewise.
1394 * iq2000-dis.c: Likewise.
1395 * iq2000-desc.c: Likewise.
1396 * lm32-dis.c: Likewise.
1397 * lm32-desc.c: Likewise.
1398 * m32c-dis.c: Likewise.
1399 * m32c-desc.c: Likewise.
1400 * m32r-dis.c: Likewise.
1401 * m32r-desc.c: Likewise.
1402 * mep-dis.c: Likewise.
1403 * mep-desc.c: Likewise.
1404 * mt-dis.c: Likewise.
1405 * mt-desc.c: Likewise.
1406 * or1k-dis.c: Likewise.
1407 * or1k-desc.c: Likewise.
1408 * xc16x-dis.c: Likewise.
1409 * xc16x-desc.c: Likewise.
1410 * xstormy16-dis.c: Likewise.
1411 * xstormy16-desc.c: Likewise.
1412
4ee4189f
NC		 14132020-06-03 Nick Clifton <nickc@redhat.com>
1414
1415 * po/sr.po: Updated Serbian translation.
1416
44730156
NC		 14172020-06-03 Nelson Chu <nelson.chu@sifive.com>
1418
1419 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1420 (riscv_get_priv_spec_class): Likewise.
1421
3c3d0376
AM		 14222020-06-01 Alan Modra <amodra@gmail.com>
1423
1424 * bpf-desc.c: Regenerate.
1425
78c1c354
JM		 14262020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1427 David Faust <david.faust@oracle.com>
1428
1429 * bpf-desc.c: Regenerate.
1430 * bpf-opc.h: Likewise.
1431 * bpf-opc.c: Likewise.
1432 * bpf-dis.c: Likewise.
1433
efcf5fb5
AM		 14342020-05-28 Alan Modra <amodra@gmail.com>
1435
1436 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1437 values.
1438
ab382d64
AM		 14392020-05-28 Alan Modra <amodra@gmail.com>
1440
1441 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1442 immediates.
1443 (print_insn_ns32k): Revert last change.
1444
151f5de4
NC		 14452020-05-28 Nick Clifton <nickc@redhat.com>
1446
1447 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1448 static.
1449
25e1eca8
SL		 14502020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1451
1452 Fix extraction of signed constants in nios2 disassembler (again).
1453
1454 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1455 extractions of signed fields.
1456
57b17940
SSF		 14572020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1458
1459 * s390-opc.txt: Relocate vector load/store instructions with
1460 additional alignment parameter and change architecture level
1461 constraint from z14 to z13.
1462
d96bf37b
AM		 14632020-05-21 Alan Modra <amodra@gmail.com>
1464
1465 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1466 * sparc-dis.c: Likewise.
1467 * tic4x-dis.c: Likewise.
1468 * xtensa-dis.c: Likewise.
1469 * bpf-desc.c: Regenerate.
1470 * epiphany-desc.c: Regenerate.
1471 * fr30-desc.c: Regenerate.
1472 * frv-desc.c: Regenerate.
1473 * ip2k-desc.c: Regenerate.
1474 * iq2000-desc.c: Regenerate.
1475 * lm32-desc.c: Regenerate.
1476 * m32c-desc.c: Regenerate.
1477 * m32r-desc.c: Regenerate.
1478 * mep-asm.c: Regenerate.
1479 * mep-desc.c: Regenerate.
1480 * mt-desc.c: Regenerate.
1481 * or1k-desc.c: Regenerate.
1482 * xc16x-desc.c: Regenerate.
1483 * xstormy16-desc.c: Regenerate.
1484
8f595e9b
NC		 14852020-05-20 Nelson Chu <nelson.chu@sifive.com>
1486
1487 * riscv-opc.c (riscv_ext_version_table): The table used to store
1488 all information about the supported spec and the corresponding ISA
1489 versions. Currently, only Zicsr is supported to verify the
1490 correctness of Z sub extension settings. Others will be supported
1491 in the future patches.
1492 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1493 classes and the corresponding strings.
1494 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1495 spec class by giving a ISA spec string.
1496 * riscv-opc.c (struct priv_spec_t): New structure.
1497 (struct priv_spec_t priv_specs): List for all supported privilege spec
1498 classes and the corresponding strings.
1499 (riscv_get_priv_spec_class): New function. Get the corresponding
1500 privilege spec class by giving a spec string.
1501 (riscv_get_priv_spec_name): New function. Get the corresponding
1502 privilege spec string by giving a CSR version class.
1503 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1504 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1505 according to the chosen version. Build a hash table riscv_csr_hash to
1506 store the valid CSR for the chosen pirv verison. Dump the direct
1507 CSR address rather than it's name if it is invalid.
1508 (parse_riscv_dis_option_without_args): New function. Parse the options
1509 without arguments.
1510 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1511 parse the options without arguments first, and then handle the options
1512 with arguments. Add the new option -Mpriv-spec, which has argument.
1513 * riscv-dis.c (print_riscv_disassembler_options): Add description
1514 about the new OBJDUMP option.
1515
3d205eb4
PB		 15162020-05-19 Peter Bergner <bergner@linux.ibm.com>
1517
1518 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1519 WC values on POWER10 sync, dcbf and wait instructions.
1520 (insert_pl, extract_pl): New functions.
1521 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1522 (LS3): New , 3-bit L for sync.
1523 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1524 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1525 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1526 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1527 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1528 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1529 <wait>: Enable PL operand on POWER10.
1530 <dcbf>: Enable L3OPT operand on POWER10.
1531 <sync>: Enable SC2 operand on POWER10.
1532
a501eb44
SH		 15332020-05-19 Stafford Horne <shorne@gmail.com>
1534
1535 PR 25184
1536 * or1k-asm.c: Regenerate.
1537 * or1k-desc.c: Regenerate.
1538 * or1k-desc.h: Regenerate.
1539 * or1k-dis.c: Regenerate.
1540 * or1k-ibld.c: Regenerate.
1541 * or1k-opc.c: Regenerate.
1542 * or1k-opc.h: Regenerate.
1543 * or1k-opinst.c: Regenerate.
1544
3b646889
AM		 15452020-05-11 Alan Modra <amodra@gmail.com>
1546
1547 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1548 xsmaxcqp, xsmincqp.
1549
9cc4ce88
AM		 15502020-05-11 Alan Modra <amodra@gmail.com>
1551
1552 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1553 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1554
5d57bc3f
AM		 15552020-05-11 Alan Modra <amodra@gmail.com>
1556
1557 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1558
66ef5847
AM		 15592020-05-11 Alan Modra <amodra@gmail.com>
1560
1561 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1562 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1563
4f3e9537
PB		 15642020-05-11 Peter Bergner <bergner@linux.ibm.com>
1565
1566 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1567 mnemonics.
1568
ec40e91c
AM		 15692020-05-11 Alan Modra <amodra@gmail.com>
1570
1571 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1572 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1573 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1574 (prefix_opcodes): Add xxeval.
1575
d7e97a76
AM		 15762020-05-11 Alan Modra <amodra@gmail.com>
1577
1578 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1579 xxgenpcvwm, xxgenpcvdm.
1580
fdefed7c
AM		 15812020-05-11 Alan Modra <amodra@gmail.com>
1582
1583 * ppc-opc.c (MP, VXVAM_MASK): Define.
1584 (VXVAPS_MASK): Use VXVA_MASK.
1585 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1586 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1587 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1588 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1589
aa3c112f
AM		 15902020-05-11 Alan Modra <amodra@gmail.com>
1591 Peter Bergner <bergner@linux.ibm.com>
1592
1593 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1594 New functions.
1595 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1596 YMSK2, XA6a, XA6ap, XB6a entries.
1597 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1598 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1599 (PPCVSX4): Define.
1600 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1601 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1602 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1603 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1604 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1605 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1606 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1607 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1608 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1609 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1610 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1611 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1612 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1613 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1614
6edbfd3b
AM		 16152020-05-11 Alan Modra <amodra@gmail.com>
1616
1617 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1618 (insert_xts, extract_xts): New functions.
1619 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1620 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1621 (VXRC_MASK, VXSH_MASK): Define.
1622 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1623 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1624 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1625 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1626 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1627 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1628 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1629
c7d7aea2
AM		 16302020-05-11 Alan Modra <amodra@gmail.com>
1631
1632 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1633 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1634 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1635 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1636 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1637
94ba9882
AM		 16382020-05-11 Alan Modra <amodra@gmail.com>
1639
1640 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1641 (XTP, DQXP, DQXP_MASK): Define.
1642 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1643 (prefix_opcodes): Add plxvp and pstxvp.
1644
f4791f1a
AM		 16452020-05-11 Alan Modra <amodra@gmail.com>
1646
1647 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1648 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1649 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1650
3ff0a5ba
PB		 16512020-05-11 Peter Bergner <bergner@linux.ibm.com>
1652
1653 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1654
afef4fe9
PB		 16552020-05-11 Peter Bergner <bergner@linux.ibm.com>
1656
1657 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1658 (L1OPT): Define.
1659 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1660
1224c05d
PB		 16612020-05-11 Peter Bergner <bergner@linux.ibm.com>
1662
1663 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1664
6bbb0c05
AM		 16652020-05-11 Alan Modra <amodra@gmail.com>
1666
1667 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1668
7c1f4227
AM		 16692020-05-11 Alan Modra <amodra@gmail.com>
1670
1671 * ppc-dis.c (ppc_opts): Add "power10" entry.
1672 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1673 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1674
73199c2b
NC		 16752020-05-11 Nick Clifton <nickc@redhat.com>
1676
1677 * po/fr.po: Updated French translation.
1678
09c1e68a
AC		 16792020-04-30 Alex Coplan <alex.coplan@arm.com>
1680
1681 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1682 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1683 (operand_general_constraint_met_p): validate
1684 AARCH64_OPND_UNDEFINED.
1685 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1686 for FLD_imm16_2.
1687 * aarch64-asm-2.c: Regenerated.
1688 * aarch64-dis-2.c: Regenerated.
1689 * aarch64-opc-2.c: Regenerated.
1690
9654d51a
NC		 16912020-04-29 Nick Clifton <nickc@redhat.com>
1692
1693 PR 22699
1694 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1695 and SETRC insns.
1696
c2e71e57
NC		 16972020-04-29 Nick Clifton <nickc@redhat.com>
1698
1699 * po/sv.po: Updated Swedish translation.
1700
5c936ef5
NC		 17012020-04-29 Nick Clifton <nickc@redhat.com>
1702
1703 PR 22699
1704 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1705 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1706 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1707 IMM0_8U case.
1708
bb2a1453
AS		 17092020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1710
1711 PR 25848
1712 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1713 cmpi only on m68020up and cpu32.
1714
c2e5c986
SD		 17152020-04-20 Sudakshina Das <sudi.das@arm.com>
1716
1717 * aarch64-asm.c (aarch64_ins_none): New.
1718 * aarch64-asm.h (ins_none): New declaration.
1719 * aarch64-dis.c (aarch64_ext_none): New.
1720 * aarch64-dis.h (ext_none): New declaration.
1721 * aarch64-opc.c (aarch64_print_operand): Update case for
1722 AARCH64_OPND_BARRIER_PSB.
1723 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1724 (AARCH64_OPERANDS): Update inserter/extracter for
1725 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1726 * aarch64-asm-2.c: Regenerated.
1727 * aarch64-dis-2.c: Regenerated.
1728 * aarch64-opc-2.c: Regenerated.
1729
8a6e1d1d
SD		 17302020-04-20 Sudakshina Das <sudi.das@arm.com>
1731
1732 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1733 (aarch64_feature_ras, RAS): Likewise.
1734 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1735 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1736 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1737 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1738 * aarch64-asm-2.c: Regenerated.
1739 * aarch64-dis-2.c: Regenerated.
1740 * aarch64-opc-2.c: Regenerated.
1741
e409955d
FS		 17422020-04-17 Fredrik Strupe <fredrik@strupe.net>
1743
1744 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1745 (print_insn_neon): Support disassembly of conditional
1746 instructions.
1747
c54a9b56
DF		 17482020-02-16 David Faust <david.faust@oracle.com>
1749
1750 * bpf-desc.c: Regenerate.
1751 * bpf-desc.h: Likewise.
1752 * bpf-opc.c: Regenerate.
1753 * bpf-opc.h: Likewise.
1754
bb651e8b
CL		 17552020-04-07 Lili Cui <lili.cui@intel.com>
1756
1757 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1758 (prefix_table): New instructions (see prefixes above).
1759 (rm_table): Likewise
1760 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1761 CPU_ANY_TSXLDTRK_FLAGS.
1762 (cpu_flags): Add CpuTSXLDTRK.
1763 * i386-opc.h (enum): Add CpuTSXLDTRK.
1764 (i386_cpu_flags): Add cputsxldtrk.
1765 * i386-opc.tbl: Add XSUSPLDTRK insns.
1766 * i386-init.h: Regenerate.
1767 * i386-tbl.h: Likewise.
1768
4b27d27c
L		 17692020-04-02 Lili Cui <lili.cui@intel.com>
1770
1771 * i386-dis.c (prefix_table): New instructions serialize.
1772 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1773 CPU_ANY_SERIALIZE_FLAGS.
1774 (cpu_flags): Add CpuSERIALIZE.
1775 * i386-opc.h (enum): Add CpuSERIALIZE.
1776 (i386_cpu_flags): Add cpuserialize.
1777 * i386-opc.tbl: Add SERIALIZE insns.
1778 * i386-init.h: Regenerate.
1779 * i386-tbl.h: Likewise.
1780
832a5807
AM		 17812020-03-26 Alan Modra <amodra@gmail.com>
1782
1783 * disassemble.h (opcodes_assert): Declare.
1784 (OPCODES_ASSERT): Define.
1785 * disassemble.c: Don't include assert.h. Include opintl.h.
1786 (opcodes_assert): New function.
1787 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1788 (bfd_h8_disassemble): Reduce size of data array. Correctly
1789 calculate maxlen. Omit insn decoding when insn length exceeds
1790 maxlen. Exit from nibble loop when looking for E, before
1791 accessing next data byte. Move processing of E outside loop.
1792 Replace tests of maxlen in loop with assertions.
1793
4c4addbe
AM		 17942020-03-26 Alan Modra <amodra@gmail.com>
1795
1796 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1797
a18cd0ca
AM		 17982020-03-25 Alan Modra <amodra@gmail.com>
1799
1800 * z80-dis.c (suffix): Init mybuf.
1801
57cb32b3
AM		 18022020-03-22 Alan Modra <amodra@gmail.com>
1803
1804 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1805 successflly read from section.
1806
beea5cc1
AM		 18072020-03-22 Alan Modra <amodra@gmail.com>
1808
1809 * arc-dis.c (find_format): Use ISO C string concatenation rather
1810 than line continuation within a string. Don't access needs_limm
1811 before testing opcode != NULL.
1812
03704c77
AM		 18132020-03-22 Alan Modra <amodra@gmail.com>
1814
1815 * ns32k-dis.c (print_insn_arg): Update comment.
1816 (print_insn_ns32k): Reduce size of index_offset array, and
1817 initialize, passing -1 to print_insn_arg for args that are not
1818 an index. Don't exit arg loop early. Abort on bad arg number.
1819
d1023b5d
AM		 18202020-03-22 Alan Modra <amodra@gmail.com>
1821
1822 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1823 * s12z-opc.c: Formatting.
1824 (operands_f): Return an int.
1825 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1826 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1827 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1828 (exg_sex_discrim): Likewise.
1829 (create_immediate_operand, create_bitfield_operand),
1830 (create_register_operand_with_size, create_register_all_operand),
1831 (create_register_all16_operand, create_simple_memory_operand),
1832 (create_memory_operand, create_memory_auto_operand): Don't
1833 segfault on malloc failure.
1834 (z_ext24_decode): Return an int status, negative on fail, zero
1835 on success.
1836 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1837 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1838 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1839 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1840 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1841 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1842 (loop_primitive_decode, shift_decode, psh_pul_decode),
1843 (bit_field_decode): Similarly.
1844 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1845 to return value, update callers.
1846 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1847 Don't segfault on NULL operand.
1848 (decode_operation): Return OP_INVALID on first fail.
1849 (decode_s12z): Check all reads, returning -1 on fail.
1850
340f3ac8
AM		 18512020-03-20 Alan Modra <amodra@gmail.com>
1852
1853 * metag-dis.c (print_insn_metag): Don't ignore status from
1854 read_memory_func.
1855
fe90ae8a
AM		 18562020-03-20 Alan Modra <amodra@gmail.com>
1857
1858 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1859 Initialize parts of buffer not written when handling a possible
1860 2-byte insn at end of section. Don't attempt decoding of such
1861 an insn by the 4-byte machinery.
1862
833d919c
AM		 18632020-03-20 Alan Modra <amodra@gmail.com>
1864
1865 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1866 partially filled buffer. Prevent lookup of 4-byte insns when
1867 only VLE 2-byte insns are possible due to section size. Print
1868 ".word" rather than ".long" for 2-byte leftovers.
1869
327ef784
NC		 18702020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1871
1872 PR 25641
1873 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1874
1673df32
JB		 18752020-03-13 Jan Beulich <jbeulich@suse.com>
1876
1877 * i386-dis.c (X86_64_0D): Rename to ...
1878 (X86_64_0E): ... this.
1879
384f3689
L		 18802020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1881
1882 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1883 * Makefile.in: Regenerated.
1884
865e2027
JB		 18852020-03-09 Jan Beulich <jbeulich@suse.com>
1886
1887 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1888 3-operand pseudos.
1889 * i386-tbl.h: Re-generate.
1890
2f13234b
JB		 18912020-03-09 Jan Beulich <jbeulich@suse.com>
1892
1893 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1894 vprot*, vpsha*, and vpshl*.
1895 * i386-tbl.h: Re-generate.
1896
3fabc179
JB		 18972020-03-09 Jan Beulich <jbeulich@suse.com>
1898
1899 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1900 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1901 * i386-tbl.h: Re-generate.
1902
3677e4c1
JB		 19032020-03-09 Jan Beulich <jbeulich@suse.com>
1904
1905 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1906 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1907 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1908 * i386-tbl.h: Re-generate.
1909
4c4898e8
JB		 19102020-03-09 Jan Beulich <jbeulich@suse.com>
1911
1912 * i386-gen.c (struct template_arg, struct template_instance,
1913 struct template_param, struct template, templates,
1914 parse_template, expand_templates): New.
1915 (process_i386_opcodes): Various local variables moved to
1916 expand_templates. Call parse_template and expand_templates.
1917 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1918 * i386-tbl.h: Re-generate.
1919
bc49bfd8
JB		 19202020-03-06 Jan Beulich <jbeulich@suse.com>
1921
1922 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1923 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1924 register and memory source templates. Replace VexW= by VexW*
1925 where applicable.
1926 * i386-tbl.h: Re-generate.
1927
4873e243
JB		 19282020-03-06 Jan Beulich <jbeulich@suse.com>
1929
1930 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1931 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1932 * i386-tbl.h: Re-generate.
1933
672a349b
JB		 19342020-03-06 Jan Beulich <jbeulich@suse.com>
1935
1936 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1937 * i386-tbl.h: Re-generate.
1938
4ed21b58
JB		 19392020-03-06 Jan Beulich <jbeulich@suse.com>
1940
1941 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1942 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1943 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1944 VexW0 on SSE2AVX variants.
1945 (vmovq): Drop NoRex64 from XMM/XMM variants.
1946 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1947 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1948 applicable use VexW0.
1949 * i386-tbl.h: Re-generate.
1950
643bb870
JB		 19512020-03-06 Jan Beulich <jbeulich@suse.com>
1952
1953 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1954 * i386-opc.h (Rex64): Delete.
1955 (struct i386_opcode_modifier): Remove rex64 field.
1956 * i386-opc.tbl (crc32): Drop Rex64.
1957 Replace Rex64 with Size64 everywhere else.
1958 * i386-tbl.h: Re-generate.
1959
a23b33b3
JB		 19602020-03-06 Jan Beulich <jbeulich@suse.com>
1961
1962 * i386-dis.c (OP_E_memory): Exclude recording of used address
1963 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1964 addressed memory operands for MPX insns.
1965
a0497384
JB		 19662020-03-06 Jan Beulich <jbeulich@suse.com>
1967
1968 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1969 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1970 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1971 (ptwrite): Split into non-64-bit and 64-bit forms.
1972 * i386-tbl.h: Re-generate.
1973
b630c145
JB		 19742020-03-06 Jan Beulich <jbeulich@suse.com>
1975
1976 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1977 template.
1978 * i386-tbl.h: Re-generate.
1979
a847e322
JB		 19802020-03-04 Jan Beulich <jbeulich@suse.com>
1981
1982 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1983 (prefix_table): Move vmmcall here. Add vmgexit.
1984 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1985 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1986 (cpu_flags): Add CpuSEV_ES entry.
1987 * i386-opc.h (CpuSEV_ES): New.
1988 (union i386_cpu_flags): Add cpusev_es field.
1989 * i386-opc.tbl (vmgexit): New.
1990 * i386-init.h, i386-tbl.h: Re-generate.
1991
3cd7f3e3
L		 19922020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1993
1994 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1995 with MnemonicSize.
1996 * i386-opc.h (IGNORESIZE): New.
1997 (DEFAULTSIZE): Likewise.
1998 (IgnoreSize): Removed.
1999 (DefaultSize): Likewise.
2000 (MnemonicSize): New.
2001 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2002 mnemonicsize.
2003 * i386-opc.tbl (IgnoreSize): New.
2004 (DefaultSize): Likewise.
2005 * i386-tbl.h: Regenerated.
2006
b8ba1385
SB		 20072020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2008
2009 PR 25627
2010 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2011 instructions.
2012
10d97a0f
L		 20132020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2014
2015 PR gas/25622
2016 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2017 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2018 * i386-tbl.h: Regenerated.
2019
dc1e8a47
AM		 20202020-02-26 Alan Modra <amodra@gmail.com>
2021
2022 * aarch64-asm.c: Indent labels correctly.
2023 * aarch64-dis.c: Likewise.
2024 * aarch64-gen.c: Likewise.
2025 * aarch64-opc.c: Likewise.
2026 * alpha-dis.c: Likewise.
2027 * i386-dis.c: Likewise.
2028 * nds32-asm.c: Likewise.
2029 * nfp-dis.c: Likewise.
2030 * visium-dis.c: Likewise.
2031
265b4673
CZ		 20322020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2033
2034 * arc-regs.h (int_vector_base): Make it available for all ARC
2035 CPUs.
2036
bd0cf5a6
NC		 20372020-02-20 Nelson Chu <nelson.chu@sifive.com>
2038
2039 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2040 changed.
2041
fa164239
JW		 20422020-02-19 Nelson Chu <nelson.chu@sifive.com>
2043
2044 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2045 c.mv/c.li if rs1 is zero.
2046
272a84b1
L		 20472020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2048
2049 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2050 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2051 CPU_POPCNT_FLAGS.
2052 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2053 * i386-opc.h (CpuABM): Removed.
2054 (CpuPOPCNT): New.
2055 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2056 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2057 popcnt. Remove CpuABM from lzcnt.
2058 * i386-init.h: Regenerated.
2059 * i386-tbl.h: Likewise.
2060
1f730c46
JB		 20612020-02-17 Jan Beulich <jbeulich@suse.com>
2062
2063 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2064 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2065 VexW1 instead of open-coding them.
2066 * i386-tbl.h: Re-generate.
2067
c8f8eebc
JB		 20682020-02-17 Jan Beulich <jbeulich@suse.com>
2069
2070 * i386-opc.tbl (AddrPrefixOpReg): Define.
2071 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2072 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2073 templates. Drop NoRex64.
2074 * i386-tbl.h: Re-generate.
2075
b9915cbc
JB		 20762020-02-17 Jan Beulich <jbeulich@suse.com>
2077
2078 PR gas/6518
2079 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2080 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2081 into Intel syntax instance (with Unpsecified) and AT&T one
2082 (without).
2083 (vcvtneps2bf16): Likewise, along with folding the two so far
2084 separate ones.
2085 * i386-tbl.h: Re-generate.
2086
ce504911
L		 20872020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2088
2089 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2090 CPU_ANY_SSE4A_FLAGS.
2091
dabec65d
AM		 20922020-02-17 Alan Modra <amodra@gmail.com>
2093
2094 * i386-gen.c (cpu_flag_init): Correct last change.
2095
af5c13b0
L		 20962020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2097
2098 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2099 CPU_ANY_SSE4_FLAGS.
2100
6867aac0
L		 21012020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2102
2103 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2104 (movzx): Likewise.
2105
65fca059
JB		 21062020-02-14 Jan Beulich <jbeulich@suse.com>
2107
2108 PR gas/25438
2109 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2110 destination for Cpu64-only variant.
2111 (movzx): Fold patterns.
2112 * i386-tbl.h: Re-generate.
2113
7deea9aa
JB		 21142020-02-13 Jan Beulich <jbeulich@suse.com>
2115
2116 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2117 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2118 CPU_ANY_SSE4_FLAGS entry.
2119 * i386-init.h: Re-generate.
2120
6c0946d0
JB		 21212020-02-12 Jan Beulich <jbeulich@suse.com>
2122
2123 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2124 with Unspecified, making the present one AT&T syntax only.
2125 * i386-tbl.h: Re-generate.
2126
ddb56fe6
JB		 21272020-02-12 Jan Beulich <jbeulich@suse.com>
2128
2129 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2130 * i386-tbl.h: Re-generate.
2131
5990e377
JB		 21322020-02-12 Jan Beulich <jbeulich@suse.com>
2133
2134 PR gas/24546
2135 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2136 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2137 Amd64 and Intel64 templates.
2138 (call, jmp): Likewise for far indirect variants. Dro
2139 Unspecified.
2140 * i386-tbl.h: Re-generate.
2141
50128d0c
JB		 21422020-02-11 Jan Beulich <jbeulich@suse.com>
2143
2144 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2145 * i386-opc.h (ShortForm): Delete.
2146 (struct i386_opcode_modifier): Remove shortform field.
2147 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2148 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2149 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2150 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2151 Drop ShortForm.
2152 * i386-tbl.h: Re-generate.
2153
1e05b5c4
JB		 21542020-02-11 Jan Beulich <jbeulich@suse.com>
2155
2156 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2157 fucompi): Drop ShortForm from operand-less templates.
2158 * i386-tbl.h: Re-generate.
2159
2f5dd314
AM		 21602020-02-11 Alan Modra <amodra@gmail.com>
2161
2162 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2163 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2164 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2165 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2166 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2167
5aae9ae9
MM		 21682020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2169
2170 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2171 (cde_opcodes): Add VCX* instructions.
2172
4934a27c
MM		 21732020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2174 Matthew Malcomson <matthew.malcomson@arm.com>
2175
2176 * arm-dis.c (struct cdeopcode32): New.
2177 (CDE_OPCODE): New macro.
2178 (cde_opcodes): New disassembly table.
2179 (regnames): New option to table.
2180 (cde_coprocs): New global variable.
2181 (print_insn_cde): New
2182 (print_insn_thumb32): Use print_insn_cde.
2183 (parse_arm_disassembler_options): Parse coprocN args.
2184
4b5aaf5f
L		 21852020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2186
2187 PR gas/25516
2188 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2189 with ISA64.
2190 * i386-opc.h (AMD64): Removed.
2191 (Intel64): Likewose.
2192 (AMD64): New.
2193 (INTEL64): Likewise.
2194 (INTEL64ONLY): Likewise.
2195 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2196 * i386-opc.tbl (Amd64): New.
2197 (Intel64): Likewise.
2198 (Intel64Only): Likewise.
2199 Replace AMD64 with Amd64. Update sysenter/sysenter with
2200 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2201 * i386-tbl.h: Regenerated.
2202
9fc0b501
SB		 22032020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2204
2205 PR 25469
2206 * z80-dis.c: Add support for GBZ80 opcodes.
2207
c5d7be0c
AM		 22082020-02-04 Alan Modra <amodra@gmail.com>
2209
2210 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2211
44e4546f
AM		 22122020-02-03 Alan Modra <amodra@gmail.com>
2213
2214 * m32c-ibld.c: Regenerate.
2215
b2b1453a
AM		 22162020-02-01 Alan Modra <amodra@gmail.com>
2217
2218 * frv-ibld.c: Regenerate.
2219
4102be5c
JB		 22202020-01-31 Jan Beulich <jbeulich@suse.com>
2221
2222 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2223 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2224 (OP_E_memory): Replace xmm_mdq_mode case label by
2225 vex_scalar_w_dq_mode one.
2226 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2227
825bd36c
JB		 22282020-01-31 Jan Beulich <jbeulich@suse.com>
2229
2230 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2231 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2232 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2233 (intel_operand_size): Drop vex_w_dq_mode case label.
2234
c3036ed0
RS		 22352020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2236
2237 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2238 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2239
0c115f84
AM		 22402020-01-30 Alan Modra <amodra@gmail.com>
2241
2242 * m32c-ibld.c: Regenerate.
2243
bd434cc4
JM		 22442020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2245
2246 * bpf-opc.c: Regenerate.
2247
aeab2b26
JB		 22482020-01-30 Jan Beulich <jbeulich@suse.com>
2249
2250 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2251 (dis386): Use them to replace C2/C3 table entries.
2252 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2253 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2254 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2255 * i386-tbl.h: Re-generate.
2256
62b3f548
JB		 22572020-01-30 Jan Beulich <jbeulich@suse.com>
2258
2259 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2260 forms.
2261 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2262 DefaultSize.
2263 * i386-tbl.h: Re-generate.
2264
1bd8ae10
AM		 22652020-01-30 Alan Modra <amodra@gmail.com>
2266
2267 * tic4x-dis.c (tic4x_dp): Make unsigned.
2268
bc31405e
L		 22692020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2270 Jan Beulich <jbeulich@suse.com>
2271
2272 PR binutils/25445
2273 * i386-dis.c (MOVSXD_Fixup): New function.
2274 (movsxd_mode): New enum.
2275 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2276 (intel_operand_size): Handle movsxd_mode.
2277 (OP_E_register): Likewise.
2278 (OP_G): Likewise.
2279 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2280 register on movsxd. Add movsxd with 16-bit destination register
2281 for AMD64 and Intel64 ISAs.
2282 * i386-tbl.h: Regenerated.
2283
7568c93b
TC		 22842020-01-27 Tamar Christina <tamar.christina@arm.com>
2285
2286 PR 25403
2287 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2288 * aarch64-asm-2.c: Regenerate
2289 * aarch64-dis-2.c: Likewise.
2290 * aarch64-opc-2.c: Likewise.
2291
c006a730
JB		 22922020-01-21 Jan Beulich <jbeulich@suse.com>
2293
2294 * i386-opc.tbl (sysret): Drop DefaultSize.
2295 * i386-tbl.h: Re-generate.
2296
c906a69a
JB		 22972020-01-21 Jan Beulich <jbeulich@suse.com>
2298
2299 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2300 Dword.
2301 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2302 * i386-tbl.h: Re-generate.
2303
26916852
NC		 23042020-01-20 Nick Clifton <nickc@redhat.com>
2305
2306 * po/de.po: Updated German translation.
2307 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2308 * po/uk.po: Updated Ukranian translation.
2309
4d6cbb64
AM		 23102020-01-20 Alan Modra <amodra@gmail.com>
2311
2312 * hppa-dis.c (fput_const): Remove useless cast.
2313
2bddb71a
AM		 23142020-01-20 Alan Modra <amodra@gmail.com>
2315
2316 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2317
1b1bb2c6
NC		 23182020-01-18 Nick Clifton <nickc@redhat.com>
2319
2320 * configure: Regenerate.
2321 * po/opcodes.pot: Regenerate.
2322
ae774686
NC		 23232020-01-18 Nick Clifton <nickc@redhat.com>
2324
2325 Binutils 2.34 branch created.
2326
07f1f3aa
CB		 23272020-01-17 Christian Biesinger <cbiesinger@google.com>
2328
2329 * opintl.h: Fix spelling error (seperate).
2330
42e04b36
L		 23312020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2332
2333 * i386-opc.tbl: Add {vex} pseudo prefix.
2334 * i386-tbl.h: Regenerated.
2335
2da2eaf4
AV		 23362020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2337
2338 PR 25376
2339 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2340 (neon_opcodes): Likewise.
2341 (select_arm_features): Make sure we enable MVE bits when selecting
2342 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2343 any architecture.
2344
d0849eed
JB		 23452020-01-16 Jan Beulich <jbeulich@suse.com>
2346
2347 * i386-opc.tbl: Drop stale comment from XOP section.
2348
9cf70a44
JB		 23492020-01-16 Jan Beulich <jbeulich@suse.com>
2350
2351 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2352 (extractps): Add VexWIG to SSE2AVX forms.
2353 * i386-tbl.h: Re-generate.
2354
4814632e
JB		 23552020-01-16 Jan Beulich <jbeulich@suse.com>
2356
2357 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2358 Size64 from and use VexW1 on SSE2AVX forms.
2359 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2360 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2361 * i386-tbl.h: Re-generate.
2362
aad09917
AM		 23632020-01-15 Alan Modra <amodra@gmail.com>
2364
2365 * tic4x-dis.c (tic4x_version): Make unsigned long.
2366 (optab, optab_special, registernames): New file scope vars.
2367 (tic4x_print_register): Set up registernames rather than
2368 malloc'd registertable.
2369 (tic4x_disassemble): Delete optable and optable_special. Use
2370 optab and optab_special instead. Throw away old optab,
2371 optab_special and registernames when info->mach changes.
2372
7a6bf3be
SB		 23732020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2374
2375 PR 25377
2376 * z80-dis.c (suffix): Use .db instruction to generate double
2377 prefix.
2378
ca1eaac0
AM		 23792020-01-14 Alan Modra <amodra@gmail.com>
2380
2381 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2382 values to unsigned before shifting.
2383
1d67fe3b
TT		 23842020-01-13 Thomas Troeger <tstroege@gmx.de>
2385
2386 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2387 flow instructions.
2388 (print_insn_thumb16, print_insn_thumb32): Likewise.
2389 (print_insn): Initialize the insn info.
2390 * i386-dis.c (print_insn): Initialize the insn info fields, and
2391 detect jumps.
2392
5e4f7e05
CZ		 23932012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2394
2395 * arc-opc.c (C_NE): Make it required.
2396
b9fe6b8a
CZ		 23972012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2398
2399 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2400 reserved register name.
2401
90dee485
AM		 24022020-01-13 Alan Modra <amodra@gmail.com>
2403
2404 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2405 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2406
febda64f
AM		 24072020-01-13 Alan Modra <amodra@gmail.com>
2408
2409 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2410 result of wasm_read_leb128 in a uint64_t and check that bits
2411 are not lost when copying to other locals. Use uint32_t for
2412 most locals. Use PRId64 when printing int64_t.
2413
df08b588
AM		 24142020-01-13 Alan Modra <amodra@gmail.com>
2415
2416 * score-dis.c: Formatting.
2417 * score7-dis.c: Formatting.
2418
b2c759ce
AM		 24192020-01-13 Alan Modra <amodra@gmail.com>
2420
2421 * score-dis.c (print_insn_score48): Use unsigned variables for
2422 unsigned values. Don't left shift negative values.
2423 (print_insn_score32): Likewise.
2424 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2425
5496abe1
AM		 24262020-01-13 Alan Modra <amodra@gmail.com>
2427
2428 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2429
202e762b
AM		 24302020-01-13 Alan Modra <amodra@gmail.com>
2431
2432 * fr30-ibld.c: Regenerate.
2433
7ef412cf
AM		 24342020-01-13 Alan Modra <amodra@gmail.com>
2435
2436 * xgate-dis.c (print_insn): Don't left shift signed value.
2437 (ripBits): Formatting, use 1u.
2438
7f578b95
AM		 24392020-01-10 Alan Modra <amodra@gmail.com>
2440
2441 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2442 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2443
441af85b
AM		 24442020-01-10 Alan Modra <amodra@gmail.com>
2445
2446 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2447 and XRREG value earlier to avoid a shift with negative exponent.
2448 * m10200-dis.c (disassemble): Similarly.
2449
bce58db4
NC		 24502020-01-09 Nick Clifton <nickc@redhat.com>
2451
2452 PR 25224
2453 * z80-dis.c (ld_ii_ii): Use correct cast.
2454
40c75bc8
SB		 24552020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2456
2457 PR 25224
2458 * z80-dis.c (ld_ii_ii): Use character constant when checking
2459 opcode byte value.
2460
d835a58b
JB		 24612020-01-09 Jan Beulich <jbeulich@suse.com>
2462
2463 * i386-dis.c (SEP_Fixup): New.
2464 (SEP): Define.
2465 (dis386_twobyte): Use it for sysenter/sysexit.
2466 (enum x86_64_isa): Change amd64 enumerator to value 1.
2467 (OP_J): Compare isa64 against intel64 instead of amd64.
2468 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2469 forms.
2470 * i386-tbl.h: Re-generate.
2471
030a2e78
AM		 24722020-01-08 Alan Modra <amodra@gmail.com>
2473
2474 * z8k-dis.c: Include libiberty.h
2475 (instr_data_s): Make max_fetched unsigned.
2476 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2477 Don't exceed byte_info bounds.
2478 (output_instr): Make num_bytes unsigned.
2479 (unpack_instr): Likewise for nibl_count and loop.
2480 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2481 idx unsigned.
2482 * z8k-opc.h: Regenerate.
2483
bb82aefe
SV		 24842020-01-07 Shahab Vahedi <shahab@synopsys.com>
2485
2486 * arc-tbl.h (llock): Use 'LLOCK' as class.
2487 (llockd): Likewise.
2488 (scond): Use 'SCOND' as class.
2489 (scondd): Likewise.
2490 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2491 (scondd): Likewise.
2492
cc6aa1a6
AM		 24932020-01-06 Alan Modra <amodra@gmail.com>
2494
2495 * m32c-ibld.c: Regenerate.
2496
660e62b1
AM		 24972020-01-06 Alan Modra <amodra@gmail.com>
2498
2499 PR 25344
2500 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2501 Peek at next byte to prevent recursion on repeated prefix bytes.
2502 Ensure uninitialised "mybuf" is not accessed.
2503 (print_insn_z80): Don't zero n_fetch and n_used here,..
2504 (print_insn_z80_buf): ..do it here instead.
2505
c9ae58fe
AM		 25062020-01-04 Alan Modra <amodra@gmail.com>
2507
2508 * m32r-ibld.c: Regenerate.
2509
5f57d4ec
AM		 25102020-01-04 Alan Modra <amodra@gmail.com>
2511
2512 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2513
2c5c1196
AM		 25142020-01-04 Alan Modra <amodra@gmail.com>
2515
2516 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2517
2e98c6c5
AM		 25182020-01-04 Alan Modra <amodra@gmail.com>
2519
2520 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2521
567dfba2
JB		 25222020-01-03 Jan Beulich <jbeulich@suse.com>
2523
5437a02a
JB		 2524 * aarch64-tbl.h (aarch64_opcode_table): Use
2525 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2526
25272020-01-03 Jan Beulich <jbeulich@suse.com>
2528
2529 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 2530 forms of SUDOT and USDOT.
2531
8c45011a
JB		 25322020-01-03 Jan Beulich <jbeulich@suse.com>
2533
5437a02a 2534 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 2535 uzip{1,2}.
2536 * opcodes/aarch64-dis-2.c: Re-generate.
2537
f4950f76
JB		 25382020-01-03 Jan Beulich <jbeulich@suse.com>
2539
5437a02a 2540 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 2541 FMMLA encoding.
2542 * opcodes/aarch64-dis-2.c: Re-generate.
2543
6655dba2
SB		 25442020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2545
2546 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2547
b14ce8bf
AM		 25482020-01-01 Alan Modra <amodra@gmail.com>
2549
2550 Update year range in copyright notice of all files.
2551
0b114740 2552For older changes see ChangeLog-2019
3499769a 2553\f
0b114740 2554Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 2555
2556Copying and distribution of this file, with or without modification,
2557are permitted in any medium without royalty provided the copyright
2558notice and this notice are preserved.
2559
2560Local Variables:
2561mode: change-log
2562left-margin: 8
2563fill-column: 74
2564version-control: never
2565End:
A mirror of the official binutils-gdb repository