[thirdparty/binutils-gdb.git] / opcodes / ChangeLog

2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>

	* configure.in: Handle bfd_k1om_arch.
	* configure: Regenerated.

	* disassemble.c (disassembler): Handle bfd_k1om_arch.

	* i386-dis.c (print_insn): Handle bfd_mach_k1om and
	bfd_mach_k1om_intel_syntax.

	* i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
	~(CpuL1OM|CpuK1OM).  Add CPU_K1OM_FLAGS.
	(cpu_flags): Add CpuK1OM.

	* i386-opc.h (CpuK1OM): New.
	(i386_cpu_flags): Add cpuk1om.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2011-07-12  Nick Clifton  <nickc@redhat.com>

	* arm-dis.c (print_insn_arm): Revert previous, undocumented,
	accidental change.

2011-07-01  Nick Clifton  <nickc@redhat.com>

	PR binutils/12329
	* avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
	insns using post-increment addressing.

2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (vex_len_table): Update rorxS.

2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2011)
	* i386-dis.c (vex_len_table): Correct rorxS.

	* i386-opc.tbl: Correct rorx.
	* i386-tbl.h: Regenerated.

2011-06-29  H.J. Lu  <hongjiu.lu@intel.com>

	* tilegx-opc.c (find_opcode): Replace "index" with "i".
	* tilepro-opc.c (find_opcode): Likewise.

2011-06-29  Richard Sandiford  <rdsandiford@googlemail.com>

	* mips16-opc.c (jalrc, jrc): Move earlier in file.

2011-06-21  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
	PREFIX_VEX_0F388E.

2011-06-17  Andreas Schwab  <schwab@redhat.com>

	* Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
	(MOSTLYCLEANFILES): ... here.
	* Makefile.in: Regenerate.

2011-06-14  Alan Modra  <amodra@gmail.com>

	* Makefile.in: Regenerate.

2011-06-13  Walter Lee  <walt@tilera.com>

	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
	tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
	* Makefile.in: Regenerate.
	* configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
	* configure: Regenerate.
	* disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
	* po/POTFILES.in: Regenerate.
	* tilegx-dis.c: New file.
	* tilegx-opc.c: New file.
	* tilepro-dis.c: New file.
	* tilepro-opc.c: New file.

2011-06-10  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2011)
	* i386-dis.c (XMGatherQ): New.
	* i386-dis.c (EXxmm_mb): New.
	(EXxmm_mb): Likewise.
	(EXxmm_mw): Likewise.
	(EXxmm_md): Likewise.
	(EXxmm_mq): Likewise.
	(EXxmmdw): Likewise.
	(EXxmmqd): Likewise.
	(VexGatherQ): Likewise.
	(MVexVSIBDWpX): Likewise.
	(MVexVSIBQWpX): Likewise.
	(xmm_mb_mode): Likewise.
	(xmm_mw_mode): Likewise.
	(xmm_md_mode): Likewise.
	(xmm_mq_mode): Likewise.
	(xmmdw_mode): Likewise.
	(xmmqd_mode): Likewise.
	(ymmxmm_mode): Likewise.
	(vex_vsib_d_w_dq_mode): Likewise.
	(vex_vsib_q_w_dq_mode): Likewise.
	(MOD_VEX_0F385A_PREFIX_2): Likewise.
	(MOD_VEX_0F388C_PREFIX_2): Likewise.
	(MOD_VEX_0F388E_PREFIX_2): Likewise.
	(PREFIX_0F3882): Likewise.
	(PREFIX_VEX_0F3816): Likewise.
	(PREFIX_VEX_0F3836): Likewise.
	(PREFIX_VEX_0F3845): Likewise.
	(PREFIX_VEX_0F3846): Likewise.
	(PREFIX_VEX_0F3847): Likewise.
	(PREFIX_VEX_0F3858): Likewise.
	(PREFIX_VEX_0F3859): Likewise.
	(PREFIX_VEX_0F385A): Likewise.
	(PREFIX_VEX_0F3878): Likewise.
	(PREFIX_VEX_0F3879): Likewise.
	(PREFIX_VEX_0F388C): Likewise.
	(PREFIX_VEX_0F388E): Likewise.
	(PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
	(PREFIX_VEX_0F38F5): Likewise.
	(PREFIX_VEX_0F38F6): Likewise.
	(PREFIX_VEX_0F3A00): Likewise.
	(PREFIX_VEX_0F3A01): Likewise.
	(PREFIX_VEX_0F3A02): Likewise.
	(PREFIX_VEX_0F3A38): Likewise.
	(PREFIX_VEX_0F3A39): Likewise.
	(PREFIX_VEX_0F3A46): Likewise.
	(PREFIX_VEX_0F3AF0): Likewise.
	(VEX_LEN_0F3816_P_2): Likewise.
	(VEX_LEN_0F3819_P_2): Likewise.
	(VEX_LEN_0F3836_P_2): Likewise.
	(VEX_LEN_0F385A_P_2_M_0): Likewise.
	(VEX_LEN_0F38F5_P_0): Likewise.
	(VEX_LEN_0F38F5_P_1): Likewise.
	(VEX_LEN_0F38F5_P_3): Likewise.
	(VEX_LEN_0F38F6_P_3): Likewise.
	(VEX_LEN_0F38F7_P_1): Likewise.
	(VEX_LEN_0F38F7_P_2): Likewise.
	(VEX_LEN_0F38F7_P_3): Likewise.
	(VEX_LEN_0F3A00_P_2): Likewise.
	(VEX_LEN_0F3A01_P_2): Likewise.
	(VEX_LEN_0F3A38_P_2): Likewise.
	(VEX_LEN_0F3A39_P_2): Likewise.
	(VEX_LEN_0F3A46_P_2): Likewise.
	(VEX_LEN_0F3AF0_P_3): Likewise.
	(VEX_W_0F3816_P_2): Likewise.
	(VEX_W_0F3818_P_2): Likewise.
	(VEX_W_0F3819_P_2): Likewise.
	(VEX_W_0F3836_P_2): Likewise.
	(VEX_W_0F3846_P_2): Likewise.
	(VEX_W_0F3858_P_2): Likewise.
	(VEX_W_0F3859_P_2): Likewise.
	(VEX_W_0F385A_P_2_M_0): Likewise.
	(VEX_W_0F3878_P_2): Likewise.
	(VEX_W_0F3879_P_2): Likewise.
	(VEX_W_0F3A00_P_2): Likewise.
	(VEX_W_0F3A01_P_2): Likewise.
	(VEX_W_0F3A02_P_2): Likewise.
	(VEX_W_0F3A38_P_2): Likewise.
	(VEX_W_0F3A39_P_2): Likewise.
	(VEX_W_0F3A46_P_2): Likewise.
	(MOD_VEX_0F3818_PREFIX_2): Removed.
	(MOD_VEX_0F3819_PREFIX_2): Likewise.
	(VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
	(VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
	(VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
	(VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
	(VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
	(VEX_LEN_0F3A0E_P_2): Likewise.
	(VEX_LEN_0F3A0F_P_2): Likewise.
	(VEX_LEN_0F3A42_P_2): Likewise.
	(VEX_LEN_0F3A4C_P_2): Likewise.
	(VEX_W_0F3818_P_2_M_0): Likewise.
	(VEX_W_0F3819_P_2_M_0): Likewise.
	(prefix_table): Updated.
	(three_byte_table): Likewise.
	(vex_table): Likewise.
	(vex_len_table): Likewise.
	(vex_w_table): Likewise.
	(mod_table): Likewise.
	(putop): Handle "LW".
	(intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
	xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
	vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
	(OP_EX): Likewise.
	(OP_E_memory): Handle vex_vsib_d_w_dq_mode and
	vex_vsib_q_w_dq_mode.
	(OP_XMM): Handle vex_vsib_q_w_dq_mode.
	(OP_VEX): Likewise.

	* i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
	and CPU_ANY_AVX_FLAGS.  Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
	CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
	(cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
	(opcode_modifiers): Add VecSIB.

	* i386-opc.h (CpuAVX2): New.
	(CpuBMI2): Likewise.
	(CpuLZCNT): Likewise.
	(CpuINVPCID): Likewise.
	(VecSIB128): Likewise.
	(VecSIB256): Likewise.
	(VecSIB): Likewise.
	(i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
	(i386_opcode_modifier): Add vecsib.

	* i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2011-06-03  Quentin Neill  <quentin.neill@amd.com>

	* i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
	* i386-init.h: Regenerated.

2011-06-03  Nick Clifton  <nickc@redhat.com>

	PR binutils/12752
	* arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
	computing address offsets.
	(print_arm_address): Likewise.
	(print_insn_arm): Likewise.
	(print_insn_thumb16): Likewise.
	(print_insn_thumb32): Likewise.

2011-06-02  Jie Zhang <jie@codesourcery.com>
	    Nathan Sidwell <nathan@codesourcery.com>
	    Maciej Rozycki <macro@codesourcery.com>

	* arm-dis.c (print_insn_coprocessor): Explicitly print #-0
	as address offset.
	(print_arm_address): Likewise. Elide positive #0 appropriately.
	(print_insn_arm): Likewise.

2011-06-02  Nick Clifton  <nickc@redhat.com>

	PR gas/12752
	* arm-dis.c (print_insn_thumb32): Do not sign extend  addresses
	passed to print_address_func.

2011-06-02  Nick Clifton  <nickc@redhat.com>

	* arm-dis.c: Fix spelling mistakes.
	* op/opcodes.pot: Regenerate.

2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* s390-opc.c: Replace S390_OPERAND_REG_EVEN with
	S390_OPERAND_REG_PAIR.  Fix INSTR_RRF_0UFEF instruction type.
	* s390-opc.txt: Fix cxr instruction type.

2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* s390-opc.c: Add new instruction types marking register pair
	operands.
	* s390-opc.txt: Match instructions having register pair operands
	to the new instruction types.

2011-05-19  Nick Clifton  <nickc@redhat.com>

	* v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
	operands.

2011-05-10  Quentin Neill  <quentin.neill@amd.com>

	* i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
	* i386-init.h: Regenerated.

2011-04-27  Nick Clifton  <nickc@redhat.com>

	* po/da.po: Updated Danish translation.

2011-04-26  Anton Blanchard  <anton@samba.org>

	* ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.

2011-04-21  DJ Delorie  <dj@redhat.com>

	* rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
	* rx-decode.c: Regenerate.

2011-04-20  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-init.h: Regenerated.

2011-04-19  Quentin Neill  <quentin.neill@amd.com>

	* i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
	from bdver1 flags.

2011-04-13  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (disassemble): Always print a closing square brace if
	an opening square brace was printed.

2011-04-12  Nick Clifton  <nickc@redhat.com>

	PR binutils/12534
	* arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
	patterns.
	(print_insn_thumb32): Handle %L.

2011-04-11  Julian Brown  <julian@codesourcery.com>

	* arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
	(print_insn_thumb32): Add APSR bitmask support.

2011-04-07  Paul Carroll<pcarroll@codesourcery.com>

	* arm-dis.c (print_insn): init vars moved into private_data structure.

2011-03-24  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.

2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>

	* avr-dis.c (avr_operand): Add opcode_str parameter. Check for
	post-increment to support LPM Z+ instruction. Add support for 'E'
	constraint for DES instruction.
	(print_insn_avr): Adjust calls to avr_operand. Rename variable.

2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>

	* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.

2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>

	* arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
	Use branch types instead.
	(print_insn): Likewise.

2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-opc.c (mips_builtin_opcodes): Correct register use
	annotation of "alnv.ps".

2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-opc.c (mips_builtin_opcodes): Add "pref" macro.

2011-02-22  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.

2011-02-22  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.

2011-02-19  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (saved_state): Mark static.  Change a[01]x to ax[] and
	a[01]w to aw[].  Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
	av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
	exception, end_of_registers, msize, memory, bfd_mach.
	(CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
	LB0REG, LC1REG, LT1REG, LB1REG): Delete
	(AXREG, AWREG, LCREG, LTREG, LBREG): Define.
	(get_allreg): Change to new defines.  Fallback to abort().

2011-02-14  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c: Add whitespace/parenthesis where needed.

2011-02-14  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
	than 7.

2011-02-13  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>

	* configure: Regenerate.

2011-02-13  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.

2011-02-13  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1.  Output
	dregs only when P is set, and dregs_lo otherwise.

2011-02-13  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.

2011-02-12  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.

2011-02-12  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (machine_registers): Delete REG_GP.
	(reg_names): Delete "GP".
	(decode_allregs): Change REG_GP to REG_LASTREG.

2011-02-12  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
	M_IH, M_IU): Delete.

2011-02-11  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (reg_names): Add const.
	(decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
	decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
	decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
	decode_counters, decode_allregs): Likewise.

2011-02-09  Michael Snyder  <msnyder@vmware.com>

	* i386-dis.c (OP_J): Parenthesize expression to prevent
	truncated addresses.
	(print_insn): Fix indentation off-by-one.

2011-02-01  Nick Clifton  <nickc@redhat.com>

	* po/da.po: Updated Danish translation.

2011-01-21  Dave Murphy  <davem@devkitpro.org>

	* ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.

2011-01-18  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (sIbT): New.
	(b_T_mode): Likewise.
	(dis386): Replace sIb with sIbT on "pushT".
	(x86_64_table): Replace sIb with Ib on "aam" and "aad".
	(OP_sI): Handle b_T_mode.  Properly sign-extend byte.

2011-01-18  Jan Kratochvil  <jan.kratochvil@redhat.com>

	* i386-init.h: Regenerated.
	* i386-tbl.h: Regenerated

2011-01-17  Quentin Neill  <quentin.neill@amd.com>

	* i386-dis.c (REG_XOP_TBM_01): New.
	(REG_XOP_TBM_02): New.
	(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
	(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
	entries, and add bextr instruction.

	* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
	(cpu_flags): Add CpuTBM.

	* i386-opc.h (CpuTBM) New.
	(i386_cpu_flags): Add bit cputbm.

	* i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
	blcs, blsfill, blsic, t1mskc, and tzmsk.

2011-01-12  DJ Delorie  <dj@redhat.com>

	* rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.

2011-01-11  Mingjie Xing  <mingjie.xing@gmail.com>

	* mips-dis.c (print_insn_args): Adjust the value to print the real
	offset for "+c" argument.

2011-01-10  Nick Clifton  <nickc@redhat.com>

	* po/da.po: Updated Danish translation.

2011-01-05  Nathan Sidwell  <nathan@codesourcery.com>

	* arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.

2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (REG_VEX_38F3): New.
	(PREFIX_0FBC): Likewise.
	(PREFIX_VEX_38F2): Likewise.
	(PREFIX_VEX_38F3_REG_1): Likewise.
	(PREFIX_VEX_38F3_REG_2): Likewise.
	(PREFIX_VEX_38F3_REG_3): Likewise.
	(PREFIX_VEX_38F7): Likewise.
	(VEX_LEN_38F2_P_0): Likewise.
	(VEX_LEN_38F3_R_1_P_0): Likewise.
	(VEX_LEN_38F3_R_2_P_0): Likewise.
	(VEX_LEN_38F3_R_3_P_0): Likewise.
	(VEX_LEN_38F7_P_0): Likewise.
	(dis386_twobyte): Use PREFIX_0FBC.
	(reg_table): Add REG_VEX_38F3.
	(prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
	PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
	PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
	(vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
	PREFIX_VEX_38F7.
	(vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
	VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
	VEX_LEN_38F7_P_0.

	* i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
	(cpu_flags): Add CpuBMI.

	* i386-opc.h (CpuBMI): New.
	(i386_cpu_flags): Add cpubmi.

	* i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (VexGdq): New.
	(OP_VEX): Handle dq_mode.

2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (process_copyright): Update copyright to 2011.

For older changes see ChangeLog-2010
\f
Local Variables:
mode: change-log
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fill-column: 74
version-control: never
End:
Commit	Line	Data
7a9068fe L	1	2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
	2
	3	* configure.in: Handle bfd_k1om_arch.
	4	* configure: Regenerated.
	5
	6	* disassemble.c (disassembler): Handle bfd_k1om_arch.
	7
	8	* i386-dis.c (print_insn): Handle bfd_mach_k1om and
	9	bfd_mach_k1om_intel_syntax.
	10
	11	* i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
	12	~(CpuL1OM\|CpuK1OM). Add CPU_K1OM_FLAGS.
	13	(cpu_flags): Add CpuK1OM.
	14
	15	* i386-opc.h (CpuK1OM): New.
	16	(i386_cpu_flags): Add cpuk1om.
	17
	18	* i386-init.h: Regenerated.
	19	* i386-tbl.h: Likewise.
	20
1b93226d NC	21	2011-07-12 Nick Clifton <nickc@redhat.com>
	22
	23	* arm-dis.c (print_insn_arm): Revert previous, undocumented,
	24	accidental change.
	25
5d73b1f1 NC	26	2011-07-01 Nick Clifton <nickc@redhat.com>
	27
	28	PR binutils/12329
	29	* avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
	30	insns using post-increment addressing.
	31
182ae480 L	32	2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
	33
	34	* i386-dis.c (vex_len_table): Update rorxS.
	35
4cb0953d L	36	2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
	37
	38	AVX Programming Reference (June, 2011)
	39	* i386-dis.c (vex_len_table): Correct rorxS.
	40
	41	* i386-opc.tbl: Correct rorx.
	42	* i386-tbl.h: Regenerated.
	43
906efcbc L	44	2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
	45
	46	* tilegx-opc.c (find_opcode): Replace "index" with "i".
	47	* tilepro-opc.c (find_opcode): Likewise.
	48
ceb94aa5 RS	49	2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
	50
	51	* mips16-opc.c (jalrc, jrc): Move earlier in file.
	52
f7002f42 L	53	2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
	54
	55	* i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
	56	PREFIX_VEX_0F388E.
	57
56300268 AS	58	2011-06-17 Andreas Schwab <schwab@redhat.com>
	59
	60	* Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
	61	(MOSTLYCLEANFILES): ... here.
	62	* Makefile.in: Regenerate.
	63
bcf2cf9f AM	64	2011-06-14 Alan Modra <amodra@gmail.com>
	65
	66	* Makefile.in: Regenerate.
	67
aa137e4d NC	68	2011-06-13 Walter Lee <walt@tilera.com>
	69
	70	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
	71	tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
	72	* Makefile.in: Regenerate.
	73	* configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
	74	* configure: Regenerate.
	75	* disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
	76	* po/POTFILES.in: Regenerate.
	77	* tilegx-dis.c: New file.
	78	* tilegx-opc.c: New file.
	79	* tilepro-dis.c: New file.
	80	* tilepro-opc.c: New file.
	81
6c30d220 L	82	2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
	83
	84	AVX Programming Reference (June, 2011)
	85	* i386-dis.c (XMGatherQ): New.
	86	* i386-dis.c (EXxmm_mb): New.
	87	(EXxmm_mb): Likewise.
	88	(EXxmm_mw): Likewise.
	89	(EXxmm_md): Likewise.
	90	(EXxmm_mq): Likewise.
	91	(EXxmmdw): Likewise.
	92	(EXxmmqd): Likewise.
	93	(VexGatherQ): Likewise.
	94	(MVexVSIBDWpX): Likewise.
	95	(MVexVSIBQWpX): Likewise.
	96	(xmm_mb_mode): Likewise.
	97	(xmm_mw_mode): Likewise.
	98	(xmm_md_mode): Likewise.
	99	(xmm_mq_mode): Likewise.
	100	(xmmdw_mode): Likewise.
	101	(xmmqd_mode): Likewise.
	102	(ymmxmm_mode): Likewise.
	103	(vex_vsib_d_w_dq_mode): Likewise.
	104	(vex_vsib_q_w_dq_mode): Likewise.
	105	(MOD_VEX_0F385A_PREFIX_2): Likewise.
	106	(MOD_VEX_0F388C_PREFIX_2): Likewise.
	107	(MOD_VEX_0F388E_PREFIX_2): Likewise.
	108	(PREFIX_0F3882): Likewise.
	109	(PREFIX_VEX_0F3816): Likewise.
	110	(PREFIX_VEX_0F3836): Likewise.
	111	(PREFIX_VEX_0F3845): Likewise.
	112	(PREFIX_VEX_0F3846): Likewise.
	113	(PREFIX_VEX_0F3847): Likewise.
	114	(PREFIX_VEX_0F3858): Likewise.
	115	(PREFIX_VEX_0F3859): Likewise.
	116	(PREFIX_VEX_0F385A): Likewise.
	117	(PREFIX_VEX_0F3878): Likewise.
	118	(PREFIX_VEX_0F3879): Likewise.
	119	(PREFIX_VEX_0F388C): Likewise.
	120	(PREFIX_VEX_0F388E): Likewise.
	121	(PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
	122	(PREFIX_VEX_0F38F5): Likewise.
	123	(PREFIX_VEX_0F38F6): Likewise.
	124	(PREFIX_VEX_0F3A00): Likewise.
	125	(PREFIX_VEX_0F3A01): Likewise.
	126	(PREFIX_VEX_0F3A02): Likewise.
	127	(PREFIX_VEX_0F3A38): Likewise.
	128	(PREFIX_VEX_0F3A39): Likewise.
	129	(PREFIX_VEX_0F3A46): Likewise.
	130	(PREFIX_VEX_0F3AF0): Likewise.
	131	(VEX_LEN_0F3816_P_2): Likewise.
	132	(VEX_LEN_0F3819_P_2): Likewise.
	133	(VEX_LEN_0F3836_P_2): Likewise.
	134	(VEX_LEN_0F385A_P_2_M_0): Likewise.
	135	(VEX_LEN_0F38F5_P_0): Likewise.
	136	(VEX_LEN_0F38F5_P_1): Likewise.
	137	(VEX_LEN_0F38F5_P_3): Likewise.
	138	(VEX_LEN_0F38F6_P_3): Likewise.
	139	(VEX_LEN_0F38F7_P_1): Likewise.
	140	(VEX_LEN_0F38F7_P_2): Likewise.
	141	(VEX_LEN_0F38F7_P_3): Likewise.
	142	(VEX_LEN_0F3A00_P_2): Likewise.
	143	(VEX_LEN_0F3A01_P_2): Likewise.
	144	(VEX_LEN_0F3A38_P_2): Likewise.
	145	(VEX_LEN_0F3A39_P_2): Likewise.
146	(VEX_LEN_0F3A46_P_2): Likewise.
147	(VEX_LEN_0F3AF0_P_3): Likewise.
148	(VEX_W_0F3816_P_2): Likewise.
149	(VEX_W_0F3818_P_2): Likewise.
150	(VEX_W_0F3819_P_2): Likewise.
151	(VEX_W_0F3836_P_2): Likewise.
152	(VEX_W_0F3846_P_2): Likewise.
153	(VEX_W_0F3858_P_2): Likewise.
154	(VEX_W_0F3859_P_2): Likewise.
155	(VEX_W_0F385A_P_2_M_0): Likewise.
156	(VEX_W_0F3878_P_2): Likewise.
157	(VEX_W_0F3879_P_2): Likewise.
158	(VEX_W_0F3A00_P_2): Likewise.
159	(VEX_W_0F3A01_P_2): Likewise.
160	(VEX_W_0F3A02_P_2): Likewise.
161	(VEX_W_0F3A38_P_2): Likewise.
162	(VEX_W_0F3A39_P_2): Likewise.
163	(VEX_W_0F3A46_P_2): Likewise.
164	(MOD_VEX_0F3818_PREFIX_2): Removed.
165	(MOD_VEX_0F3819_PREFIX_2): Likewise.
166	(VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
167	(VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
168	(VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
169	(VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
170	(VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
171	(VEX_LEN_0F3A0E_P_2): Likewise.
172	(VEX_LEN_0F3A0F_P_2): Likewise.
173	(VEX_LEN_0F3A42_P_2): Likewise.
174	(VEX_LEN_0F3A4C_P_2): Likewise.
175	(VEX_W_0F3818_P_2_M_0): Likewise.
176	(VEX_W_0F3819_P_2_M_0): Likewise.
177	(prefix_table): Updated.
178	(three_byte_table): Likewise.
179	(vex_table): Likewise.
180	(vex_len_table): Likewise.
181	(vex_w_table): Likewise.
182	(mod_table): Likewise.
183	(putop): Handle "LW".
184	(intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
185	xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
186	vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
187	(OP_EX): Likewise.
188	(OP_E_memory): Handle vex_vsib_d_w_dq_mode and
189	vex_vsib_q_w_dq_mode.
190	(OP_XMM): Handle vex_vsib_q_w_dq_mode.
191	(OP_VEX): Likewise.
192
193	* i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
194	and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
195	CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
196	(cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
197	(opcode_modifiers): Add VecSIB.
198
199	* i386-opc.h (CpuAVX2): New.
200	(CpuBMI2): Likewise.
201	(CpuLZCNT): Likewise.
202	(CpuINVPCID): Likewise.
203	(VecSIB128): Likewise.
204	(VecSIB256): Likewise.
205	(VecSIB): Likewise.
206	(i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
207	(i386_opcode_modifier): Add vecsib.
208
209	* i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
210	* i386-init.h: Regenerated.
211	* i386-tbl.h: Likewise.
212
d535accd QN	213	2011-06-03 Quentin Neill <quentin.neill@amd.com>
	214
	215	* i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
	216	* i386-init.h: Regenerated.
	217
f8b960bc NC	218	2011-06-03 Nick Clifton <nickc@redhat.com>
	219
	220	PR binutils/12752
	221	* arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
	222	computing address offsets.
	223	(print_arm_address): Likewise.
	224	(print_insn_arm): Likewise.
	225	(print_insn_thumb16): Likewise.
	226	(print_insn_thumb32): Likewise.
	227
26d97720 NS	228	2011-06-02 Jie Zhang <jie@codesourcery.com>
	229	Nathan Sidwell <nathan@codesourcery.com>
	230	Maciej Rozycki <macro@codesourcery.com>
	231
	232	* arm-dis.c (print_insn_coprocessor): Explicitly print #-0
	233	as address offset.
	234	(print_arm_address): Likewise. Elide positive #0 appropriately.
	235	(print_insn_arm): Likewise.
	236
f8b960bc NC	237	2011-06-02 Nick Clifton <nickc@redhat.com>
	238
	239	PR gas/12752
	240	* arm-dis.c (print_insn_thumb32): Do not sign extend addresses
	241	passed to print_address_func.
	242
cc643b88 NC	243	2011-06-02 Nick Clifton <nickc@redhat.com>
	244
	245	* arm-dis.c: Fix spelling mistakes.
	246	* op/opcodes.pot: Regenerate.
	247
c8fa16ed AK	248	2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
	249
	250	* s390-opc.c: Replace S390_OPERAND_REG_EVEN with
	251	S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
	252	* s390-opc.txt: Fix cxr instruction type.
	253
5e4b319c AK	254	2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
	255
	256	* s390-opc.c: Add new instruction types marking register pair
	257	operands.
	258	* s390-opc.txt: Match instructions having register pair operands
	259	to the new instruction types.
	260
fda544a2 NC	261	2011-05-19 Nick Clifton <nickc@redhat.com>
	262
	263	* v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
	264	operands.
	265
4cab4add QN	266	2011-05-10 Quentin Neill <quentin.neill@amd.com>
	267
	268	* i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
	269	* i386-init.h: Regenerated.
	270
b4e7b885 NC	271	2011-04-27 Nick Clifton <nickc@redhat.com>
	272
	273	* po/da.po: Updated Danish translation.
	274
2f7f7710 AM	275	2011-04-26 Anton Blanchard <anton@samba.org>
	276
	277	* ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
	278
9887672f DD	279	2011-04-21 DJ Delorie <dj@redhat.com>
	280
	281	* rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
	282	* rx-decode.c: Regenerate.
	283
3251b375 L	284	2011-04-20 H.J. Lu <hongjiu.lu@intel.com>
	285
	286	* i386-init.h: Regenerated.
	287
b13a3ca6 QN	288	2011-04-19 Quentin Neill <quentin.neill@amd.com>
	289
	290	* i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
	291	from bdver1 flags.
	292
7d063384 NC	293	2011-04-13 Nick Clifton <nickc@redhat.com>
	294
	295	* v850-dis.c (disassemble): Always print a closing square brace if
	296	an opening square brace was printed.
	297
32a94698 NC	298	2011-04-12 Nick Clifton <nickc@redhat.com>
	299
	300	PR binutils/12534
	301	* arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
	302	patterns.
	303	(print_insn_thumb32): Handle %L.
	304
d2cd1205 JB	305	2011-04-11 Julian Brown <julian@codesourcery.com>
	306
	307	* arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
	308	(print_insn_thumb32): Add APSR bitmask support.
	309
1fbaefec PB	310	2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
	311
	312	* arm-dis.c (print_insn): init vars moved into private_data structure.
	313
67171547 MF	314	2011-03-24 Mike Frysinger <vapier@gentoo.org>
	315
	316	* bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
	317
8cc66334 EW	318	2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
	319
	320	* avr-dis.c (avr_operand): Add opcode_str parameter. Check for
	321	post-increment to support LPM Z+ instruction. Add support for 'E'
	322	constraint for DES instruction.
	323	(print_insn_avr): Adjust calls to avr_operand. Rename variable.
	324
34e77a92 RS	325	2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
	326
	327	* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
	328
35fc36a8 RS	329	2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
	330
	331	* arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
	332	Use branch types instead.
	333	(print_insn): Likewise.
	334
0067d8fc MR	335	2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
	336
	337	* mips-opc.c (mips_builtin_opcodes): Correct register use
	338	annotation of "alnv.ps".
	339
3eebd5eb MR	340	2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
	341
	342	* mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
	343
500cccad MF	344	2011-02-22 Mike Frysinger <vapier@gentoo.org>
	345
	346	* bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
	347
f5caf9f4 MF	348	2011-02-22 Mike Frysinger <vapier@gentoo.org>
	349
	350	* bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
	351
e5bc4265 MF	352	2011-02-19 Mike Frysinger <vapier@gentoo.org>
	353
	354	* bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
	355	a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
	356	av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
	357	exception, end_of_registers, msize, memory, bfd_mach.
	358	(CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
	359	LB0REG, LC1REG, LT1REG, LB1REG): Delete
	360	(AXREG, AWREG, LCREG, LTREG, LBREG): Define.
	361	(get_allreg): Change to new defines. Fallback to abort().
	362
602427c4 MF	363	2011-02-14 Mike Frysinger <vapier@gentoo.org>
	364
	365	* bfin-dis.c: Add whitespace/parenthesis where needed.
	366
298c1ec2 MF	367	2011-02-14 Mike Frysinger <vapier@gentoo.org>
	368
	369	* bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
	370	than 7.
	371
822ce8ee RW	372	2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
	373
	374	* configure: Regenerate.
	375
13c02f06 MF	376	2011-02-13 Mike Frysinger <vapier@gentoo.org>
	377
	378	* bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
	379
4db66394 MF	380	2011-02-13 Mike Frysinger <vapier@gentoo.org>
	381
	382	* bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
	383	dregs only when P is set, and dregs_lo otherwise.
	384
36f44611 MF	385	2011-02-13 Mike Frysinger <vapier@gentoo.org>
	386
	387	* bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
	388
9805c0a5 MF	389	2011-02-12 Mike Frysinger <vapier@gentoo.org>
	390
	391	* bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
	392
43a6aa65 MF	393	2011-02-12 Mike Frysinger <vapier@gentoo.org>
	394
	395	* bfin-dis.c (machine_registers): Delete REG_GP.
	396	(reg_names): Delete "GP".
	397	(decode_allregs): Change REG_GP to REG_LASTREG.
	398
26bb3ddd MF	399	2011-02-12 Mike Frysinger <vapier@gentoo.org>
26bb3ddd MF	400
89c0d58c MR	401	* bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
89c0d58c MR	402	M_IH, M_IU): Delete.
26bb3ddd	403
69b8ea4a MF	404	2011-02-11 Mike Frysinger <vapier@gentoo.org>
	405
	406	* bfin-dis.c (reg_names): Add const.
	407	(decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
	408	decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
	409	decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
	410	decode_counters, decode_allregs): Likewise.
	411
42d5f9c6 MS	412	2011-02-09 Michael Snyder <msnyder@vmware.com>
42d5f9c6 MS	413
56300268	414	* i386-dis.c (OP_J): Parenthesize expression to prevent
42d5f9c6 MS	415	truncated addresses.
	416	(print_insn): Fix indentation off-by-one.
	417
4be0c941 NC	418	2011-02-01 Nick Clifton <nickc@redhat.com>
	419
	420	* po/da.po: Updated Danish translation.
	421
6b069ee7 AM	422	2011-01-21 Dave Murphy <davem@devkitpro.org>
	423
	424	* ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
	425
e3949f17 L	426	2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
	427
	428	* i386-dis.c (sIbT): New.
	429	(b_T_mode): Likewise.
	430	(dis386): Replace sIb with sIbT on "pushT".
	431	(x86_64_table): Replace sIb with Ib on "aam" and "aad".
	432	(OP_sI): Handle b_T_mode. Properly sign-extend byte.
	433
752573b2 JK	434	2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
	435
	436	* i386-init.h: Regenerated.
	437	* i386-tbl.h: Regenerated
	438
2a2a0f38 QN	439	2011-01-17 Quentin Neill <quentin.neill@amd.com>
	440
	441	* i386-dis.c (REG_XOP_TBM_01): New.
	442	(REG_XOP_TBM_02): New.
	443	(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
	444	(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
	445	entries, and add bextr instruction.
	446
	447	* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
	448	(cpu_flags): Add CpuTBM.
	449
	450	* i386-opc.h (CpuTBM) New.
	451	(i386_cpu_flags): Add bit cputbm.
	452
	453	* i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
	454	blcs, blsfill, blsic, t1mskc, and tzmsk.
	455
90d6ff62 DD	456	2011-01-12 DJ Delorie <dj@redhat.com>
	457
	458	* rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
	459
c95354ed MX	460	2011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
	461
	462	* mips-dis.c (print_insn_args): Adjust the value to print the real
	463	offset for "+c" argument.
	464
f7465604 NC	465	2011-01-10 Nick Clifton <nickc@redhat.com>
	466
	467	* po/da.po: Updated Danish translation.
	468
639e30d2 NS	469	2011-01-05 Nathan Sidwell <nathan@codesourcery.com>
	470
	471	* arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
	472
f12dc422 L	473	2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
	474
	475	* i386-dis.c (REG_VEX_38F3): New.
	476	(PREFIX_0FBC): Likewise.
	477	(PREFIX_VEX_38F2): Likewise.
	478	(PREFIX_VEX_38F3_REG_1): Likewise.
	479	(PREFIX_VEX_38F3_REG_2): Likewise.
	480	(PREFIX_VEX_38F3_REG_3): Likewise.
	481	(PREFIX_VEX_38F7): Likewise.
	482	(VEX_LEN_38F2_P_0): Likewise.
	483	(VEX_LEN_38F3_R_1_P_0): Likewise.
	484	(VEX_LEN_38F3_R_2_P_0): Likewise.
	485	(VEX_LEN_38F3_R_3_P_0): Likewise.
	486	(VEX_LEN_38F7_P_0): Likewise.
	487	(dis386_twobyte): Use PREFIX_0FBC.
	488	(reg_table): Add REG_VEX_38F3.
	489	(prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
	490	PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
	491	PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
	492	(vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
	493	PREFIX_VEX_38F7.
	494	(vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
	495	VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
	496	VEX_LEN_38F7_P_0.
	497
	498	* i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
	499	(cpu_flags): Add CpuBMI.
	500
	501	* i386-opc.h (CpuBMI): New.
	502	(i386_cpu_flags): Add cpubmi.
	503
	504	* i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
	505	* i386-init.h: Regenerated.
	506	* i386-tbl.h: Likewise.
	507
cb21baef L	508	2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
	509
	510	* i386-dis.c (VexGdq): New.
	511	(OP_VEX): Handle dq_mode.
	512
0db46eb4 L	513	2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
	514
	515	* i386-gen.c (process_copyright): Update copyright to 2011.
	516
9e9e0820	517	For older changes see ChangeLog-2010
252b5132 RH	518	\f
252b5132 RH	519	Local Variables:
2f6d2f85 NC	520	mode: change-log
	521	left-margin: 8
	522	fill-column: 74
252b5132 RH	523	version-control: never
252b5132 RH	524	End: