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MIPS/opcodes: Free up redundant `g' operand code
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
cccc84fa
MR		 12021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
2
3 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
4 and "mtthc2" to using the `G' rather than `g' operand code for
5 the coprocessor control register referred.
6
c9de3168
MR		 72021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
8
9 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
10 entries with each other.
11
ebcab741
PB		 122021-05-27 Peter Bergner <bergner@linux.ibm.com>
13
14 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
15
bc30a119
AM		 162021-05-25 Alan Modra <amodra@gmail.com>
17
18 * cris-desc.c: Regenerate.
19 * cris-desc.h: Regenerate.
20 * cris-opc.h: Regenerate.
21 * po/POTFILES.in: Regenerate.
22
54711280
MF		 232021-05-24 Mike Frysinger <vapier@gentoo.org>
24
25 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
26 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
27 (CGEN_CPUS): Add cris.
28 (CRIS_DEPS): Define.
29 (stamp-cris): New rule.
30 * cgen.sh: Handle desc action.
31 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
32 * Makefile.in, configure: Regenerate.
33
113bb761
JN		 342021-05-18 Job Noorman <mtvec@pm.me>
35
36 PR 27814
37 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
38 the elf objects.
39
e683cb41
AC		 402021-05-17 Alex Coplan <alex.coplan@arm.com>
41
42 * arm-dis.c (mve_opcodes): Fix disassembly of
43 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
44 (is_mve_encoding_conflict): MVE vector loads should not match
45 when P = W = 0.
46 (is_mve_unpredictable): It's not unpredictable to use the same
47 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
48
a680affc
NC		 492021-05-11 Nick Clifton <nickc@redhat.com>
50
51 PR 27840
52 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
53 the end of the code buffer.
54
0b3e14c9
SH		 552021-05-06 Stafford Horne <shorne@gmail.com>
56
57 PR 21464
58 * or1k-asm.c: Regenerate.
59
6aee2cb2
MF		 602021-05-01 Max Filippov <jcmvbkbc@gmail.com>
61
62 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
63 info->insn_info_valid.
64
fe134c65
JB		 652021-04-26 Jan Beulich <jbeulich@suse.com>
66
67 * i386-opc.tbl (lea): Add Optimize.
68 * opcodes/i386-tbl.h: Re-generate.
69
b3ea7639
MF		 702020-04-23 Max Filippov <jcmvbkbc@gmail.com>
71
72 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
73 of l32r fetch and display referenced literal value.
74
c1cbb7d8
MF		 752021-04-23 Max Filippov <jcmvbkbc@gmail.com>
76
77 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
78 to 4 for literal disassembly.
79
02202574
PW		 802021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
81
82 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
83 for TLBI instruction.
84
cd6608e4
PW		 852021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
86
87 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
88 DC instruction.
89
fe1640ff
JB		 902021-04-19 Jan Beulich <jbeulich@suse.com>
91
92 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
93 "qualifier".
94 (convert_mov_to_movewide): Add initializer for "value".
95
100e914d
PW		 962021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
97
98 * aarch64-opc.c: Add RME system registers.
99
a21b96dd
NC		 1002021-04-16 Lifang Xia <lifang_xia@c-sky.com>
101
102 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
103 "addi d,CV,z" to "c.mv d,CV".
104
43e05cd4
AM		 1052021-04-12 Alan Modra <amodra@gmail.com>
106
107 * configure.ac (--enable-checking): Add support.
108 * config.in: Regenerate.
109 * configure: Regenerate.
110
52efda82
TB		 1112021-04-09 Tejas Belagod <tejas.belagod@arm.com>
112
113 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
114 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
115
c3f72de4
AM		 1162021-04-09 Alan Modra <amodra@gmail.com>
117
118 * ppc-dis.c (struct dis_private): Add "special".
119 (POWERPC_DIALECT): Delete. Replace uses with..
120 (private_data): ..this. New inline function.
121 (disassemble_init_powerpc): Init "special" names.
122 (skip_optional_operands): Add is_pcrel arg, set when detecting R
123 field of prefix instructions.
124 (bsearch_reloc, print_got_plt): New functions.
125 (print_insn_powerpc): For pcrel instructions, print target address
126 and symbol if known, and decode plt and got loads too.
127
ce7d813a
AM		 1282021-04-08 Alan Modra <amodra@gmail.com>
129
130 PR 27684
131 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
132
97bf40d8
AM		 1332021-04-08 Alan Modra <amodra@gmail.com>
134
135 PR 27676
136 * ppc-opc.c (DCBT_EO): Move earlier.
137 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
138 (powerpc_operands): Add THCT and THDS entries.
139 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
140
a2e66773
AM		 1412021-04-06 Alan Modra <amodra@gmail.com>
142
143 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
144 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
145 symbol_at_address_func.
146
ab2af25e
AM		 1472021-04-05 Alan Modra <amodra@gmail.com>
148
149 * configure.ac: Don't check for limits.h, string.h, strings.h or
150 stdlib.h.
151 (AC_ISC_POSIX): Don't invoke.
152 * sysdep.h: Include stdlib.h and string.h unconditionally.
153 * i386-opc.h: Include limits.h unconditionally.
154 * wasm32-dis.c: Likewise.
155 * cgen-opc.c: Don't include alloca-conf.h.
156 * config.in: Regenerate.
157 * configure: Regenerate.
158
e9b095a5
ML		 1592021-04-01 Martin Liska <mliska@suse.cz>
160
161 * arm-dis.c (strneq): Remove strneq and use startswith.
162 * cr16-dis.c (print_insn_cr16): Likewise.
163 * score-dis.c (streq): Likewise.
164 (strneq): Likewise.
165 * score7-dis.c (strneq): Likewise.
166
1cb108e4
AM		 1672021-04-01 Alan Modra <amodra@gmail.com>
168
169 PR 27675
170 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
171
78933a4a
AM		 1722021-03-31 Alan Modra <amodra@gmail.com>
173
174 * sysdep.h (POISON_BFD_BOOLEAN): Define.
175 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
176 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
177 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
178 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
179 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
180 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
181 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
182 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
183 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
184 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
185 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
186 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
187 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
188 and TRUE with true throughout.
189
3dfb1b6d
AM		 1902021-03-31 Alan Modra <amodra@gmail.com>
191
192 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
193 * aarch64-dis.h: Likewise.
194 * aarch64-opc.c: Likewise.
195 * avr-dis.c: Likewise.
196 * csky-dis.c: Likewise.
197 * nds32-asm.c: Likewise.
198 * nds32-dis.c: Likewise.
199 * nfp-dis.c: Likewise.
200 * riscv-dis.c: Likewise.
201 * s12z-dis.c: Likewise.
202 * wasm32-dis.c: Likewise.
203
5e042380
JB		 2042021-03-30 Jan Beulich <jbeulich@suse.com>
205
206 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
207 (i386_seg_prefixes): New.
208 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
209 (i386_seg_prefixes): Declare.
210
34684862
JB		 2112021-03-30 Jan Beulich <jbeulich@suse.com>
212
213 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
214
6288d05f
JB		 2152021-03-30 Jan Beulich <jbeulich@suse.com>
216
217 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
218 * i386-reg.tbl (st): Move down.
219 (st(0)): Delete. Extend comment.
220 * i386-tbl.h: Re-generate.
221
bbe1eca6
JB		 2222021-03-29 Jan Beulich <jbeulich@suse.com>
223
224 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
225 (cmpsd): Move next to cmps.
226 (movsd): Move next to movs.
227 (cmpxchg16b): Move to separate section.
228 (fisttp, fisttpll): Likewise.
229 (monitor, mwait): Likewise.
230 * i386-tbl.h: Re-generate.
231
c8cad9d3
JB		 2322021-03-29 Jan Beulich <jbeulich@suse.com>
233
234 * i386-opc.tbl (psadbw): Add <sse2:comm>.
235 (vpsadbw): Add C.
236 * i386-tbl.h: Re-generate.
237
5cdaf100
JB		 2382021-03-29 Jan Beulich <jbeulich@suse.com>
239
240 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
241 pclmul, gfni): New templates. Use them wherever possible. Move
242 SSE4.1 pextrw into respective section.
243 * i386-tbl.h: Re-generate.
244
73e45eb2
JB		 2452021-03-29 Jan Beulich <jbeulich@suse.com>
246
247 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
248 strtoull(). Bump upper loop bound. Widen masks. Sanity check
249 "length".
250 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
251 Convert all of their uses to representation in opcode.
252
9df6f676
JB		 2532021-03-29 Jan Beulich <jbeulich@suse.com>
254
255 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
256 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
257 value of None. Shrink operands to 3 bits.
258
389d00a5
JB		 2592021-03-29 Jan Beulich <jbeulich@suse.com>
260
261 * i386-gen.c (process_i386_opcode_modifier): New parameter
262 "space".
263 (output_i386_opcode): New local variable "space". Adjust
264 process_i386_opcode_modifier() invocation.
265 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
266 invocation.
267 * i386-tbl.h: Re-generate.
268
63b4cc53
AM		 2692021-03-29 Alan Modra <amodra@gmail.com>
270
271 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
272 (fp_qualifier_p, get_data_pattern): Likewise.
273 (aarch64_get_operand_modifier_from_value): Likewise.
274 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
275 (operand_variant_qualifier_p): Likewise.
276 (qualifier_value_in_range_constraint_p): Likewise.
277 (aarch64_get_qualifier_esize): Likewise.
278 (aarch64_get_qualifier_nelem): Likewise.
279 (aarch64_get_qualifier_standard_value): Likewise.
280 (get_lower_bound, get_upper_bound): Likewise.
281 (aarch64_find_best_match, match_operands_qualifier): Likewise.
282 (aarch64_print_operand): Likewise.
283 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
284 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
285 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
286 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
287 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
288 (print_insn_tic6x): Likewise.
289
3d7d6c1b
AM		 2902021-03-29 Alan Modra <amodra@gmail.com>
291
292 * arc-dis.c (extract_operand_value): Correct NULL cast.
293 * frv-opc.h: Regenerate.
294
c3344b62
JB		 2952021-03-26 Jan Beulich <jbeulich@suse.com>
296
297 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
298 MMX form.
299 * i386-tbl.h: Re-generate.
300
efa30ac3
HAQ		 3012021-03-25 Abid Qadeer <abidh@codesourcery.com>
302
303 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
304 immediate in br.n instruction.
305
596a02ff
JB		 3062021-03-25 Jan Beulich <jbeulich@suse.com>
307
308 * i386-dis.c (XMGatherD, VexGatherD): New.
309 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
310 (print_insn): Check masking for S/G insns.
311 (OP_E_memory): New local variable check_gather. Extend mandatory
312 SIB check. Check register conflicts for (EVEX-encoded) gathers.
313 Extend check for disallowed 16-bit addressing.
314 (OP_VEX): New local variables modrm_reg and sib_index. Convert
315 if()s to switch(). Check register conflicts for (VEX-encoded)
316 gathers. Drop no longer reachable cases.
317 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
318 vgatherdp*.
319
53642852
JB		 3202021-03-25 Jan Beulich <jbeulich@suse.com>
321
322 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
323 zeroing-masking without masking.
324
c0e54661
JB		 3252021-03-25 Jan Beulich <jbeulich@suse.com>
326
327 * i386-opc.tbl (invlpgb): Fix multi-operand form.
328 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
329 single-operand forms as deprecated.
330 * i386-tbl.h: Re-generate.
331
5a403766
AM		 3322021-03-25 Alan Modra <amodra@gmail.com>
333
334 PR 27647
335 * ppc-opc.c (XLOCB_MASK): Delete.
336 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
337 XLBH_MASK.
338 (powerpc_opcodes): Accept a BH field on all extended forms of
339 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
340
9a182d04
JB		 3412021-03-24 Jan Beulich <jbeulich@suse.com>
342
343 * i386-gen.c (output_i386_opcode): Drop processing of
344 opcode_length. Calculate length from base_opcode. Adjust prefix
345 encoding determination.
346 (process_i386_opcodes): Drop output of fake opcode_length.
347 * i386-opc.h (struct insn_template): Drop opcode_length field.
348 * i386-opc.tbl: Drop opcode length field from all templates.
349 * i386-tbl.h: Re-generate.
350
35648716
JB		 3512021-03-24 Jan Beulich <jbeulich@suse.com>
352
353 * i386-gen.c (process_i386_opcode_modifier): Return void. New
354 parameter "prefix". Drop local variable "regular_encoding".
355 Record prefix setting / check for consistency.
356 (output_i386_opcode): Parse opcode_length and base_opcode
357 earlier. Derive prefix encoding. Drop no longer applicable
358 consistency checking. Adjust process_i386_opcode_modifier()
359 invocation.
360 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
361 invocation.
362 * i386-tbl.h: Re-generate.
363
31184569
JB		 3642021-03-24 Jan Beulich <jbeulich@suse.com>
365
366 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
367 check.
368 * i386-opc.h (Prefix_*): Move #define-s.
369 * i386-opc.tbl: Move pseudo prefix enumerator values to
370 extension opcode field. Introduce pseudopfx template.
371 * i386-tbl.h: Re-generate.
372
b933fa4b
JB		 3732021-03-23 Jan Beulich <jbeulich@suse.com>
374
375 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
376 comment.
377 * i386-tbl.h: Re-generate.
378
dac10fb0
JB		 3792021-03-23 Jan Beulich <jbeulich@suse.com>
380
381 * i386-opc.h (struct insn_template): Move cpu_flags field past
382 opcode_modifier one.
383 * i386-tbl.h: Re-generate.
384
441f6aca
JB		 3852021-03-23 Jan Beulich <jbeulich@suse.com>
386
387 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
388 * i386-opc.h (OpcodeSpace): New enumerator.
389 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
390 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
391 SPACE_XOP09, SPACE_XOP0A): ... respectively.
392 (struct i386_opcode_modifier): New field opcodespace. Shrink
393 opcodeprefix field.
394 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
395 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
396 OpcodePrefix uses.
397 * i386-tbl.h: Re-generate.
398
08dedd66
ML		 3992021-03-22 Martin Liska <mliska@suse.cz>
400
401 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
402 * arc-dis.c (parse_option): Likewise.
403 * arm-dis.c (parse_arm_disassembler_options): Likewise.
404 * cris-dis.c (print_with_operands): Likewise.
405 * h8300-dis.c (bfd_h8_disassemble): Likewise.
406 * i386-dis.c (print_insn): Likewise.
407 * ia64-gen.c (fetch_insn_class): Likewise.
408 (parse_resource_users): Likewise.
409 (in_iclass): Likewise.
410 (lookup_specifier): Likewise.
411 (insert_opcode_dependencies): Likewise.
412 * mips-dis.c (parse_mips_ase_option): Likewise.
413 (parse_mips_dis_option): Likewise.
414 * s390-dis.c (disassemble_init_s390): Likewise.
415 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
416
80d49d6a
KLC		 4172021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
418
419 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
420
7fce7ea9
PW		 4212021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
422
423 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
424 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
425
78c84bf9
AM		 4262021-03-12 Alan Modra <amodra@gmail.com>
427
428 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
429
fd1fd061
JB		 4302021-03-11 Jan Beulich <jbeulich@suse.com>
431
432 * i386-dis.c (OP_XMM): Re-order checks.
433
ac7a2311
JB		 4342021-03-11 Jan Beulich <jbeulich@suse.com>
435
436 * i386-dis.c (putop): Drop need_vex check when also checking
437 vex.evex.
438 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
439 checking vex.b.
440
da944c8a
JB		 4412021-03-11 Jan Beulich <jbeulich@suse.com>
442
443 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
444 checks. Move case label past broadcast check.
445
b763d508
JB		 4462021-03-10 Jan Beulich <jbeulich@suse.com>
447
448 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
449 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
450 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
451 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
452 EVEX_W_0F38C7_M_0_L_2): Delete.
453 (REG_EVEX_0F38C7_M_0_L_2): New.
454 (intel_operand_size): Handle VEX and EVEX the same for
455 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
456 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
457 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
458 vex_vsib_q_w_d_mode uses.
459 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
460 0F38A1, and 0F38A3 entries.
461 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
462 entry.
463 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
464 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
465 0F38A3 entries.
466
32e31ad7
JB		 4672021-03-10 Jan Beulich <jbeulich@suse.com>
468
469 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
470 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
471 MOD_VEX_0FXOP_09_12): Rename to ...
472 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
473 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
474 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
475 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
476 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
477 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
478 (reg_table): Adjust comments.
479 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
480 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
481 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
482 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
483 (vex_len_table): Adjust opcode 0A_12 entry.
484 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
485 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
486 (rm_table): Move hreset entry.
487
85ba7507
JB		 4882021-03-10 Jan Beulich <jbeulich@suse.com>
489
490 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
491 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
492 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
493 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
494 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
495 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
496 (get_valid_dis386): Also handle 512-bit vector length when
497 vectoring into vex_len_table[].
498 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
499 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
500 entries.
501 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
502 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
503 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
504 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
505 entries.
506
066f82b9
JB		 5072021-03-10 Jan Beulich <jbeulich@suse.com>
508
509 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
510 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
511 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
512 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
513 entries.
514 * i386-dis-evex-len.h (evex_len_table): Likewise.
515 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
516
fc681dd6
JB		 5172021-03-10 Jan Beulich <jbeulich@suse.com>
518
519 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
520 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
521 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
522 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
523 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
524 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
525 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
526 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
527 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
528 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
529 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
530 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
531 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
532 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
533 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
534 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
535 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
536 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
537 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
538 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
539 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
540 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
541 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
542 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
543 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
544 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
545 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
546 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
547 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
548 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
549 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
550 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
551 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
552 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
553 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
554 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
555 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
556 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
557 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
558 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
559 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
560 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
561 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
562 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
563 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
564 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
565 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
566 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
567 EVEX_W_0F3A43_L_n): New.
568 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
569 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
570 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
571 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
572 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
573 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
574 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
575 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
576 0F385B, 0F38C6, and 0F38C7 entries.
577 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
578 0F38C6 and 0F38C7.
579 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
580 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
581 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
582 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
583
13954a31
JB		 5842021-03-10 Jan Beulich <jbeulich@suse.com>
585
586 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
587 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
588 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
589 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
590 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
591 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
592 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
593 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
594 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
595 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
596 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
597 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
598 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
599 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
600 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
601 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
602 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
603 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
604 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
605 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
606 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
607 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
608 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
609 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
610 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
611 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
612 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
613 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
614 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
615 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
616 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
617 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
618 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
619 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
620 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
621 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
622 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
623 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
624 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
625 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
626 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
627 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
628 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
629 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
630 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
631 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
632 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
633 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
634 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
635 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
636 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
637 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
638 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
639 VEX_W_0F99_P_2_LEN_0): Delete.
640 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
641 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
642 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
643 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
644 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
645 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
646 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
647 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
648 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
649 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
650 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
651 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
652 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
653 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
654 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
655 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
656 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
657 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
658 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
659 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
660 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
661 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
662 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
663 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
664 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
665 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
666 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
667 (prefix_table): No longer link to vex_len_table[] for opcodes
668 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
669 0F92, 0F93, 0F98, and 0F99.
670 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
671 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
672 0F98, and 0F99.
673 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
674 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
675 0F98, and 0F99.
676 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
677 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
678 0F98, and 0F99.
679 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
680 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
681 0F98, and 0F99.
682
14d10c6c
JB		 6832021-03-10 Jan Beulich <jbeulich@suse.com>
684
685 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
686 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
687 REG_VEX_0F73_M_0 respectively.
688 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
689 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
690 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
691 MOD_VEX_0F73_REG_7): Delete.
692 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
693 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
694 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
695 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
696 PREFIX_VEX_0F3AF0_L_0 respectively.
697 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
698 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
699 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
700 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
701 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
702 VEX_LEN_0F38F7): New.
703 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
704 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
705 0F72, and 0F73. No longer link to vex_len_table[] for opcode
706 0F38F3.
707 (prefix_table): No longer link to vex_len_table[] for opcodes
708 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
709 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
710 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
711 0F38F6, 0F38F7, and 0F3AF0.
712 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
713 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
714 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
715 0F73.
716
00ec1875
JB		 7172021-03-10 Jan Beulich <jbeulich@suse.com>
718
719 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
720 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
721 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
722 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
723 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
724 (MOD_0F71, MOD_0F72, MOD_0F73): New.
725 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
726 73.
727 (reg_table): No longer link to mod_table[] for opcodes 0F71,
728 0F72, and 0F73.
729 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
730 0F73.
731
31941983
JB		 7322021-03-10 Jan Beulich <jbeulich@suse.com>
733
734 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
735 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
736 (reg_table): Don't link to mod_table[] where not needed. Add
737 PREFIX_IGNORED to nop entries.
738 (prefix_table): Replace PREFIX_OPCODE in nop entries.
739 (mod_table): Add nop entries next to prefetch ones. Drop
740 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
741 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
742 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
743 PREFIX_OPCODE from endbr* entries.
744 (get_valid_dis386): Also consider entry's name when zapping
745 vindex.
746 (print_insn): Handle PREFIX_IGNORED.
747
742732c7
JB		 7482021-03-09 Jan Beulich <jbeulich@suse.com>
749
750 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
751 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
752 element.
753 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
754 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
755 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
756 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
757 (struct i386_opcode_modifier): Delete notrackprefixok,
758 islockable, hleprefixok, and repprefixok fields. Add prefixok
759 field.
760 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
761 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
762 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
763 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
764 Replace HLEPrefixOk.
765 * opcodes/i386-tbl.h: Re-generate.
766
e93a3b27
JB		 7672021-03-09 Jan Beulich <jbeulich@suse.com>
768
769 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
770 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
771 64-bit form.
772 * opcodes/i386-tbl.h: Re-generate.
773
75363b6d
JB		 7742021-03-03 Jan Beulich <jbeulich@suse.com>
775
776 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
777 for {} instead of {0}. Don't look for '0'.
778 * i386-opc.tbl: Drop operand count field. Drop redundant operand
779 size specifiers.
780
5a9f5403
NC		 7812021-02-19 Nelson Chu <nelson.chu@sifive.com>
782
783 PR 27158
784 * riscv-dis.c (print_insn_args): Updated encoding macros.
785 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
786 (match_c_addi16sp): Updated encoding macros.
787 (match_c_lui): Likewise.
788 (match_c_lui_with_hint): Likewise.
789 (match_c_addi4spn): Likewise.
790 (match_c_slli): Likewise.
791 (match_slli_as_c_slli): Likewise.
792 (match_c_slli64): Likewise.
793 (match_srxi_as_c_srxi): Likewise.
794 (riscv_insn_types): Added .insn css/cl/cs.
795
3d73d29e
NC		 7962021-02-18 Nelson Chu <nelson.chu@sifive.com>
797
798 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
799 (default_priv_spec): Updated type to riscv_spec_class.
800 (parse_riscv_dis_option): Updated.
801 * riscv-opc.c: Moved stuff and make the file tidy.
802
b9b204b3
AM		 8032021-02-17 Alan Modra <amodra@gmail.com>
804
805 * wasm32-dis.c: Include limits.h.
806 (CHAR_BIT): Provide backup define.
807 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
808 Correct signed overflow checking.
809
394ae71f
JB		 8102021-02-16 Jan Beulich <jbeulich@suse.com>
811
812 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
813 * i386-tbl.h: Re-generate.
814
b818b220
JB		 8152021-02-16 Jan Beulich <jbeulich@suse.com>
816
817 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
818 Oword.
819 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
820
ba2b480f
AK		 8212021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
822
823 * s390-mkopc.c (main): Accept arch14 as cpu string.
824 * s390-opc.txt: Add new arch14 instructions.
825
95148614
NA		 8262021-02-04 Nick Alcock <nick.alcock@oracle.com>
827
828 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
829 favour of LIBINTL.
830 * configure: Regenerated.
831
bfd428bc
MF		 8322021-02-08 Mike Frysinger <vapier@gentoo.org>
833
834 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
835 * tic54x-opc.c (regs): Rename to ...
836 (tic54x_regs): ... this.
837 (mmregs): Rename to ...
838 (tic54x_mmregs): ... this.
839 (condition_codes): Rename to ...
840 (tic54x_condition_codes): ... this.
841 (cc2_codes): Rename to ...
842 (tic54x_cc2_codes): ... this.
843 (cc3_codes): Rename to ...
844 (tic54x_cc3_codes): ... this.
845 (status_bits): Rename to ...
846 (tic54x_status_bits): ... this.
847 (misc_symbols): Rename to ...
848 (tic54x_misc_symbols): ... this.
849
24075dcc
NC		 8502021-02-04 Nelson Chu <nelson.chu@sifive.com>
851
852 * riscv-opc.c (MASK_RVB_IMM): Removed.
853 (riscv_opcodes): Removed zb* instructions.
854 (riscv_ext_version_table): Removed versions for zb*.
855
c3ffb8f3
AM		 8562021-01-26 Alan Modra <amodra@gmail.com>
857
858 * i386-gen.c (parse_template): Ensure entire template_instance
859 is initialised.
860
1942a048
NC		 8612021-01-15 Nelson Chu <nelson.chu@sifive.com>
862
863 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
864 (riscv_fpr_names_abi): Likewise.
865 (riscv_opcodes): Likewise.
866 (riscv_insn_types): Likewise.
867
b800637e
NC		 8682021-01-15 Nelson Chu <nelson.chu@sifive.com>
869
870 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
871
dcd709e0
NC		 8722021-01-15 Nelson Chu <nelson.chu@sifive.com>
873
874 * riscv-dis.c: Comments tidy and improvement.
875 * riscv-opc.c: Likewise.
876
5347ed60
AM		 8772021-01-13 Alan Modra <amodra@gmail.com>
878
879 * Makefile.in: Regenerate.
880
d546b610
L		 8812021-01-12 H.J. Lu <hongjiu.lu@intel.com>
882
883 PR binutils/26792
884 * configure.ac: Use GNU_MAKE_JOBSERVER.
885 * aclocal.m4: Regenerated.
886 * configure: Likewise.
887
6d104cac
NC		 8882021-01-12 Nick Clifton <nickc@redhat.com>
889
890 * po/sr.po: Updated Serbian translation.
891
83b33c6c
L		 8922021-01-11 H.J. Lu <hongjiu.lu@intel.com>
893
894 PR ld/27173
895 * configure: Regenerated.
896
82c70b08
KT		 8972021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
898
899 * aarch64-asm-2.c: Regenerate.
900 * aarch64-dis-2.c: Likewise.
901 * aarch64-opc-2.c: Likewise.
902 * aarch64-opc.c (aarch64_print_operand):
903 Delete handling of AARCH64_OPND_CSRE_CSR.
904 * aarch64-tbl.h (aarch64_feature_csre): Delete.
905 (CSRE): Likewise.
906 (_CSRE_INSN): Likewise.
907 (aarch64_opcode_table): Delete csr.
908
a8aa72b9
NC		 9092021-01-11 Nick Clifton <nickc@redhat.com>
910
911 * po/de.po: Updated German translation.
912 * po/fr.po: Updated French translation.
913 * po/pt_BR.po: Updated Brazilian Portuguese translation.
914 * po/sv.po: Updated Swedish translation.
915 * po/uk.po: Updated Ukranian translation.
916
a4966cd9
L		 9172021-01-09 H.J. Lu <hongjiu.lu@intel.com>
918
919 * configure: Regenerated.
920
573fe3fb
NC		 9212021-01-09 Nick Clifton <nickc@redhat.com>
922
923 * configure: Regenerate.
924 * po/opcodes.pot: Regenerate.
925
055bc77a
NC		 9262021-01-09 Nick Clifton <nickc@redhat.com>
927
928 * 2.36 release branch crated.
929
aae7fcb8
PB		 9302021-01-08 Peter Bergner <bergner@linux.ibm.com>
931
932 * ppc-opc.c (insert_dw, (extract_dw): New functions.
933 (DW, (XRC_MASK): Define.
934 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
935
64307045
AM		 9362021-01-09 Alan Modra <amodra@gmail.com>
937
938 * configure: Regenerate.
939
ed205222
NC		 9402021-01-08 Nick Clifton <nickc@redhat.com>
941
942 * po/sv.po: Updated Swedish translation.
943
fb932b57
NC		 9442021-01-08 Nick Clifton <nickc@redhat.com>
945
e84c8716
NC		 946 PR 27129
947 * aarch64-dis.c (determine_disassembling_preference): Move call to
948 aarch64_match_operands_constraint outside of the assertion.
949 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
950 Replace with a return of FALSE.
951
fb932b57
NC		 952 PR 27139
953 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
954 core system register.
955
f4782128
ST		 9562021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
957
958 * configure: Regenerate.
959
1b0927db
NC		 9602021-01-07 Nick Clifton <nickc@redhat.com>
961
962 * po/fr.po: Updated French translation.
963
3b288c8e
FN		 9642021-01-07 Fredrik Noring <noring@nocrew.org>
965
966 * m68k-opc.c (chkl): Change minimum architecture requirement to
967 m68020.
968
aa881ecd
PT		 9692021-01-07 Philipp Tomsich <prt@gnu.org>
970
971 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
972
2652cfad
CXW		 9732021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
974 Jim Wilson <jimw@sifive.com>
975 Andrew Waterman <andrew@sifive.com>
976 Maxim Blinov <maxim.blinov@embecosm.com>
977 Kito Cheng <kito.cheng@sifive.com>
978 Nelson Chu <nelson.chu@sifive.com>
979
980 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
981 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
982
250d07de
AM		 9832021-01-01 Alan Modra <amodra@gmail.com>
984
985 Update year range in copyright notice of all files.
986
c2795844 987For older changes see ChangeLog-2020
3499769a 988\f
c2795844 989Copyright (C) 2021 Free Software Foundation, Inc.
3499769a
AM		 990
991Copying and distribution of this file, with or without modification,
992are permitted in any medium without royalty provided the copyright
993notice and this notice are preserved.
994
995Local Variables:
996mode: change-log
997left-margin: 8
998fill-column: 74
999version-control: never
1000End:
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