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gdb/testsuite: only add -J option when compiling with gfortran
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
1ff6a3b8
AM		 12021-05-29 Alan Modra <amodra@gmail.com>
2
3 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
4 Don't special case PPC_OPCODE_RAW.
5 (lookup_prefix): Likewise.
6 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
7 (print_insn_powerpc): ..update caller.
8 * ppc-opc.c (EXT): Define.
9 (powerpc_opcodes): Mark extended mnemonics with EXT.
10 (prefix_opcodes, vle_opcodes): Likewise.
11 (XISEL, XISEL_MASK): Add cr field and simplify.
12 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
13 all isel variants to where the base mnemonic belongs. Sort dstt,
14 dststt and dssall.
15
49149d59
MR		 162021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
17
18 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
19 COP3 opcode instructions.
20
9573a461
MR		 212021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
22
23 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
24 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
25 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
26 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
27 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
28 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
29 "cop2", and "cop3" entries.
30
fa495743
MR		 312021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
32
33 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
34 entries and associated comments.
35
b930964c
MR		 362021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
37
38 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
39 of "c0".
40
dd844468
MR		 412021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
42
43 * mips-dis.c (mips_cp1_names_mips): New variable.
44 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
45 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
46 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
47 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
48 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
49 "loongson2f".
50
9204ccd4
MR		 512021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
52
53 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
54 handling code over to...
55 <OP_REG_CONTROL>: ... this new case.
56 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
57 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
58 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
59 replacing the `G' operand code with `g'. Update "cftc1" and
60 "cftc2" entries replacing the `E' operand code with `y'.
61 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
62 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
63 entries replacing the `G' operand code with `g'.
64
a3fb396f
MR		 652021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
66
67 * mips-dis.c (mips_cp0_names_r3900): New variable.
68 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
69 for "r3900".
70
cccc84fa
MR		 712021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
72
73 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
74 and "mtthc2" to using the `G' rather than `g' operand code for
75 the coprocessor control register referred.
76
c9de3168
MR		 772021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
78
79 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
80 entries with each other.
81
ebcab741
PB		 822021-05-27 Peter Bergner <bergner@linux.ibm.com>
83
84 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
85
bc30a119
AM		 862021-05-25 Alan Modra <amodra@gmail.com>
87
88 * cris-desc.c: Regenerate.
89 * cris-desc.h: Regenerate.
90 * cris-opc.h: Regenerate.
91 * po/POTFILES.in: Regenerate.
92
54711280
MF		 932021-05-24 Mike Frysinger <vapier@gentoo.org>
94
95 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
96 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
97 (CGEN_CPUS): Add cris.
98 (CRIS_DEPS): Define.
99 (stamp-cris): New rule.
100 * cgen.sh: Handle desc action.
101 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
102 * Makefile.in, configure: Regenerate.
103
113bb761
JN		 1042021-05-18 Job Noorman <mtvec@pm.me>
105
106 PR 27814
107 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
108 the elf objects.
109
e683cb41
AC		 1102021-05-17 Alex Coplan <alex.coplan@arm.com>
111
112 * arm-dis.c (mve_opcodes): Fix disassembly of
113 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
114 (is_mve_encoding_conflict): MVE vector loads should not match
115 when P = W = 0.
116 (is_mve_unpredictable): It's not unpredictable to use the same
117 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
118
a680affc
NC		 1192021-05-11 Nick Clifton <nickc@redhat.com>
120
121 PR 27840
122 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
123 the end of the code buffer.
124
0b3e14c9
SH		 1252021-05-06 Stafford Horne <shorne@gmail.com>
126
127 PR 21464
128 * or1k-asm.c: Regenerate.
129
6aee2cb2
MF		 1302021-05-01 Max Filippov <jcmvbkbc@gmail.com>
131
132 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
133 info->insn_info_valid.
134
fe134c65
JB		 1352021-04-26 Jan Beulich <jbeulich@suse.com>
136
137 * i386-opc.tbl (lea): Add Optimize.
138 * opcodes/i386-tbl.h: Re-generate.
139
b3ea7639
MF		 1402020-04-23 Max Filippov <jcmvbkbc@gmail.com>
141
142 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
143 of l32r fetch and display referenced literal value.
144
c1cbb7d8
MF		 1452021-04-23 Max Filippov <jcmvbkbc@gmail.com>
146
147 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
148 to 4 for literal disassembly.
149
02202574
PW		 1502021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
151
152 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
153 for TLBI instruction.
154
cd6608e4
PW		 1552021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
156
157 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
158 DC instruction.
159
fe1640ff
JB		 1602021-04-19 Jan Beulich <jbeulich@suse.com>
161
162 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
163 "qualifier".
164 (convert_mov_to_movewide): Add initializer for "value".
165
100e914d
PW		 1662021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
167
168 * aarch64-opc.c: Add RME system registers.
169
a21b96dd
NC		 1702021-04-16 Lifang Xia <lifang_xia@c-sky.com>
171
172 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
173 "addi d,CV,z" to "c.mv d,CV".
174
43e05cd4
AM		 1752021-04-12 Alan Modra <amodra@gmail.com>
176
177 * configure.ac (--enable-checking): Add support.
178 * config.in: Regenerate.
179 * configure: Regenerate.
180
52efda82
TB		 1812021-04-09 Tejas Belagod <tejas.belagod@arm.com>
182
183 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
184 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
185
c3f72de4
AM		 1862021-04-09 Alan Modra <amodra@gmail.com>
187
188 * ppc-dis.c (struct dis_private): Add "special".
189 (POWERPC_DIALECT): Delete. Replace uses with..
190 (private_data): ..this. New inline function.
191 (disassemble_init_powerpc): Init "special" names.
192 (skip_optional_operands): Add is_pcrel arg, set when detecting R
193 field of prefix instructions.
194 (bsearch_reloc, print_got_plt): New functions.
195 (print_insn_powerpc): For pcrel instructions, print target address
196 and symbol if known, and decode plt and got loads too.
197
ce7d813a
AM		 1982021-04-08 Alan Modra <amodra@gmail.com>
199
200 PR 27684
201 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
202
97bf40d8
AM		 2032021-04-08 Alan Modra <amodra@gmail.com>
204
205 PR 27676
206 * ppc-opc.c (DCBT_EO): Move earlier.
207 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
208 (powerpc_operands): Add THCT and THDS entries.
209 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
210
a2e66773
AM		 2112021-04-06 Alan Modra <amodra@gmail.com>
212
213 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
214 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
215 symbol_at_address_func.
216
ab2af25e
AM		 2172021-04-05 Alan Modra <amodra@gmail.com>
218
219 * configure.ac: Don't check for limits.h, string.h, strings.h or
220 stdlib.h.
221 (AC_ISC_POSIX): Don't invoke.
222 * sysdep.h: Include stdlib.h and string.h unconditionally.
223 * i386-opc.h: Include limits.h unconditionally.
224 * wasm32-dis.c: Likewise.
225 * cgen-opc.c: Don't include alloca-conf.h.
226 * config.in: Regenerate.
227 * configure: Regenerate.
228
e9b095a5
ML		 2292021-04-01 Martin Liska <mliska@suse.cz>
230
231 * arm-dis.c (strneq): Remove strneq and use startswith.
232 * cr16-dis.c (print_insn_cr16): Likewise.
233 * score-dis.c (streq): Likewise.
234 (strneq): Likewise.
235 * score7-dis.c (strneq): Likewise.
236
1cb108e4
AM		 2372021-04-01 Alan Modra <amodra@gmail.com>
238
239 PR 27675
240 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
241
78933a4a
AM		 2422021-03-31 Alan Modra <amodra@gmail.com>
243
244 * sysdep.h (POISON_BFD_BOOLEAN): Define.
245 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
246 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
247 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
248 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
249 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
250 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
251 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
252 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
253 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
254 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
255 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
256 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
257 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
258 and TRUE with true throughout.
259
3dfb1b6d
AM		 2602021-03-31 Alan Modra <amodra@gmail.com>
261
262 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
263 * aarch64-dis.h: Likewise.
264 * aarch64-opc.c: Likewise.
265 * avr-dis.c: Likewise.
266 * csky-dis.c: Likewise.
267 * nds32-asm.c: Likewise.
268 * nds32-dis.c: Likewise.
269 * nfp-dis.c: Likewise.
270 * riscv-dis.c: Likewise.
271 * s12z-dis.c: Likewise.
272 * wasm32-dis.c: Likewise.
273
5e042380
JB		 2742021-03-30 Jan Beulich <jbeulich@suse.com>
275
276 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
277 (i386_seg_prefixes): New.
278 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
279 (i386_seg_prefixes): Declare.
280
34684862
JB		 2812021-03-30 Jan Beulich <jbeulich@suse.com>
282
283 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
284
6288d05f
JB		 2852021-03-30 Jan Beulich <jbeulich@suse.com>
286
287 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
288 * i386-reg.tbl (st): Move down.
289 (st(0)): Delete. Extend comment.
290 * i386-tbl.h: Re-generate.
291
bbe1eca6
JB		 2922021-03-29 Jan Beulich <jbeulich@suse.com>
293
294 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
295 (cmpsd): Move next to cmps.
296 (movsd): Move next to movs.
297 (cmpxchg16b): Move to separate section.
298 (fisttp, fisttpll): Likewise.
299 (monitor, mwait): Likewise.
300 * i386-tbl.h: Re-generate.
301
c8cad9d3
JB		 3022021-03-29 Jan Beulich <jbeulich@suse.com>
303
304 * i386-opc.tbl (psadbw): Add <sse2:comm>.
305 (vpsadbw): Add C.
306 * i386-tbl.h: Re-generate.
307
5cdaf100
JB		 3082021-03-29 Jan Beulich <jbeulich@suse.com>
309
310 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
311 pclmul, gfni): New templates. Use them wherever possible. Move
312 SSE4.1 pextrw into respective section.
313 * i386-tbl.h: Re-generate.
314
73e45eb2
JB		 3152021-03-29 Jan Beulich <jbeulich@suse.com>
316
317 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
318 strtoull(). Bump upper loop bound. Widen masks. Sanity check
319 "length".
320 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
321 Convert all of their uses to representation in opcode.
322
9df6f676
JB		 3232021-03-29 Jan Beulich <jbeulich@suse.com>
324
325 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
326 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
327 value of None. Shrink operands to 3 bits.
328
389d00a5
JB		 3292021-03-29 Jan Beulich <jbeulich@suse.com>
330
331 * i386-gen.c (process_i386_opcode_modifier): New parameter
332 "space".
333 (output_i386_opcode): New local variable "space". Adjust
334 process_i386_opcode_modifier() invocation.
335 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
336 invocation.
337 * i386-tbl.h: Re-generate.
338
63b4cc53
AM		 3392021-03-29 Alan Modra <amodra@gmail.com>
340
341 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
342 (fp_qualifier_p, get_data_pattern): Likewise.
343 (aarch64_get_operand_modifier_from_value): Likewise.
344 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
345 (operand_variant_qualifier_p): Likewise.
346 (qualifier_value_in_range_constraint_p): Likewise.
347 (aarch64_get_qualifier_esize): Likewise.
348 (aarch64_get_qualifier_nelem): Likewise.
349 (aarch64_get_qualifier_standard_value): Likewise.
350 (get_lower_bound, get_upper_bound): Likewise.
351 (aarch64_find_best_match, match_operands_qualifier): Likewise.
352 (aarch64_print_operand): Likewise.
353 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
354 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
355 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
356 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
357 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
358 (print_insn_tic6x): Likewise.
359
3d7d6c1b
AM		 3602021-03-29 Alan Modra <amodra@gmail.com>
361
362 * arc-dis.c (extract_operand_value): Correct NULL cast.
363 * frv-opc.h: Regenerate.
364
c3344b62
JB		 3652021-03-26 Jan Beulich <jbeulich@suse.com>
366
367 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
368 MMX form.
369 * i386-tbl.h: Re-generate.
370
efa30ac3
HAQ		 3712021-03-25 Abid Qadeer <abidh@codesourcery.com>
372
373 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
374 immediate in br.n instruction.
375
596a02ff
JB		 3762021-03-25 Jan Beulich <jbeulich@suse.com>
377
378 * i386-dis.c (XMGatherD, VexGatherD): New.
379 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
380 (print_insn): Check masking for S/G insns.
381 (OP_E_memory): New local variable check_gather. Extend mandatory
382 SIB check. Check register conflicts for (EVEX-encoded) gathers.
383 Extend check for disallowed 16-bit addressing.
384 (OP_VEX): New local variables modrm_reg and sib_index. Convert
385 if()s to switch(). Check register conflicts for (VEX-encoded)
386 gathers. Drop no longer reachable cases.
387 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
388 vgatherdp*.
389
53642852
JB		 3902021-03-25 Jan Beulich <jbeulich@suse.com>
391
392 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
393 zeroing-masking without masking.
394
c0e54661
JB		 3952021-03-25 Jan Beulich <jbeulich@suse.com>
396
397 * i386-opc.tbl (invlpgb): Fix multi-operand form.
398 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
399 single-operand forms as deprecated.
400 * i386-tbl.h: Re-generate.
401
5a403766
AM		 4022021-03-25 Alan Modra <amodra@gmail.com>
403
404 PR 27647
405 * ppc-opc.c (XLOCB_MASK): Delete.
406 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
407 XLBH_MASK.
408 (powerpc_opcodes): Accept a BH field on all extended forms of
409 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
410
9a182d04
JB		 4112021-03-24 Jan Beulich <jbeulich@suse.com>
412
413 * i386-gen.c (output_i386_opcode): Drop processing of
414 opcode_length. Calculate length from base_opcode. Adjust prefix
415 encoding determination.
416 (process_i386_opcodes): Drop output of fake opcode_length.
417 * i386-opc.h (struct insn_template): Drop opcode_length field.
418 * i386-opc.tbl: Drop opcode length field from all templates.
419 * i386-tbl.h: Re-generate.
420
35648716
JB		 4212021-03-24 Jan Beulich <jbeulich@suse.com>
422
423 * i386-gen.c (process_i386_opcode_modifier): Return void. New
424 parameter "prefix". Drop local variable "regular_encoding".
425 Record prefix setting / check for consistency.
426 (output_i386_opcode): Parse opcode_length and base_opcode
427 earlier. Derive prefix encoding. Drop no longer applicable
428 consistency checking. Adjust process_i386_opcode_modifier()
429 invocation.
430 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
431 invocation.
432 * i386-tbl.h: Re-generate.
433
31184569
JB		 4342021-03-24 Jan Beulich <jbeulich@suse.com>
435
436 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
437 check.
438 * i386-opc.h (Prefix_*): Move #define-s.
439 * i386-opc.tbl: Move pseudo prefix enumerator values to
440 extension opcode field. Introduce pseudopfx template.
441 * i386-tbl.h: Re-generate.
442
b933fa4b
JB		 4432021-03-23 Jan Beulich <jbeulich@suse.com>
444
445 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
446 comment.
447 * i386-tbl.h: Re-generate.
448
dac10fb0
JB		 4492021-03-23 Jan Beulich <jbeulich@suse.com>
450
451 * i386-opc.h (struct insn_template): Move cpu_flags field past
452 opcode_modifier one.
453 * i386-tbl.h: Re-generate.
454
441f6aca
JB		 4552021-03-23 Jan Beulich <jbeulich@suse.com>
456
457 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
458 * i386-opc.h (OpcodeSpace): New enumerator.
459 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
460 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
461 SPACE_XOP09, SPACE_XOP0A): ... respectively.
462 (struct i386_opcode_modifier): New field opcodespace. Shrink
463 opcodeprefix field.
464 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
465 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
466 OpcodePrefix uses.
467 * i386-tbl.h: Re-generate.
468
08dedd66
ML		 4692021-03-22 Martin Liska <mliska@suse.cz>
470
471 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
472 * arc-dis.c (parse_option): Likewise.
473 * arm-dis.c (parse_arm_disassembler_options): Likewise.
474 * cris-dis.c (print_with_operands): Likewise.
475 * h8300-dis.c (bfd_h8_disassemble): Likewise.
476 * i386-dis.c (print_insn): Likewise.
477 * ia64-gen.c (fetch_insn_class): Likewise.
478 (parse_resource_users): Likewise.
479 (in_iclass): Likewise.
480 (lookup_specifier): Likewise.
481 (insert_opcode_dependencies): Likewise.
482 * mips-dis.c (parse_mips_ase_option): Likewise.
483 (parse_mips_dis_option): Likewise.
484 * s390-dis.c (disassemble_init_s390): Likewise.
485 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
486
80d49d6a
KLC		 4872021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
488
489 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
490
7fce7ea9
PW		 4912021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
492
493 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
494 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
495
78c84bf9
AM		 4962021-03-12 Alan Modra <amodra@gmail.com>
497
498 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
499
fd1fd061
JB		 5002021-03-11 Jan Beulich <jbeulich@suse.com>
501
502 * i386-dis.c (OP_XMM): Re-order checks.
503
ac7a2311
JB		 5042021-03-11 Jan Beulich <jbeulich@suse.com>
505
506 * i386-dis.c (putop): Drop need_vex check when also checking
507 vex.evex.
508 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
509 checking vex.b.
510
da944c8a
JB		 5112021-03-11 Jan Beulich <jbeulich@suse.com>
512
513 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
514 checks. Move case label past broadcast check.
515
b763d508
JB		 5162021-03-10 Jan Beulich <jbeulich@suse.com>
517
518 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
519 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
520 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
521 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
522 EVEX_W_0F38C7_M_0_L_2): Delete.
523 (REG_EVEX_0F38C7_M_0_L_2): New.
524 (intel_operand_size): Handle VEX and EVEX the same for
525 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
526 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
527 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
528 vex_vsib_q_w_d_mode uses.
529 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
530 0F38A1, and 0F38A3 entries.
531 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
532 entry.
533 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
534 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
535 0F38A3 entries.
536
32e31ad7
JB		 5372021-03-10 Jan Beulich <jbeulich@suse.com>
538
539 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
540 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
541 MOD_VEX_0FXOP_09_12): Rename to ...
542 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
543 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
544 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
545 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
546 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
547 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
548 (reg_table): Adjust comments.
549 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
550 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
551 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
552 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
553 (vex_len_table): Adjust opcode 0A_12 entry.
554 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
555 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
556 (rm_table): Move hreset entry.
557
85ba7507
JB		 5582021-03-10 Jan Beulich <jbeulich@suse.com>
559
560 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
561 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
562 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
563 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
564 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
565 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
566 (get_valid_dis386): Also handle 512-bit vector length when
567 vectoring into vex_len_table[].
568 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
569 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
570 entries.
571 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
572 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
573 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
574 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
575 entries.
576
066f82b9
JB		 5772021-03-10 Jan Beulich <jbeulich@suse.com>
578
579 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
580 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
581 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
582 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
583 entries.
584 * i386-dis-evex-len.h (evex_len_table): Likewise.
585 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
586
fc681dd6
JB		 5872021-03-10 Jan Beulich <jbeulich@suse.com>
588
589 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
590 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
591 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
592 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
593 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
594 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
595 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
596 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
597 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
598 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
599 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
600 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
601 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
602 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
603 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
604 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
605 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
606 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
607 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
608 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
609 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
610 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
611 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
612 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
613 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
614 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
615 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
616 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
617 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
618 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
619 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
620 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
621 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
622 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
623 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
624 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
625 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
626 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
627 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
628 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
629 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
630 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
631 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
632 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
633 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
634 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
635 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
636 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
637 EVEX_W_0F3A43_L_n): New.
638 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
639 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
640 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
641 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
642 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
643 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
644 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
645 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
646 0F385B, 0F38C6, and 0F38C7 entries.
647 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
648 0F38C6 and 0F38C7.
649 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
650 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
651 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
652 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
653
13954a31
JB		 6542021-03-10 Jan Beulich <jbeulich@suse.com>
655
656 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
657 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
658 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
659 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
660 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
661 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
662 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
663 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
664 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
665 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
666 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
667 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
668 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
669 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
670 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
671 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
672 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
673 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
674 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
675 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
676 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
677 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
678 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
679 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
680 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
681 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
682 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
683 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
684 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
685 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
686 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
687 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
688 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
689 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
690 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
691 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
692 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
693 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
694 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
695 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
696 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
697 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
698 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
699 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
700 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
701 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
702 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
703 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
704 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
705 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
706 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
707 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
708 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
709 VEX_W_0F99_P_2_LEN_0): Delete.
710 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
711 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
712 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
713 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
714 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
715 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
716 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
717 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
718 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
719 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
720 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
721 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
722 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
723 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
724 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
725 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
726 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
727 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
728 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
729 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
730 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
731 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
732 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
733 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
734 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
735 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
736 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
737 (prefix_table): No longer link to vex_len_table[] for opcodes
738 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
739 0F92, 0F93, 0F98, and 0F99.
740 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
741 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
742 0F98, and 0F99.
743 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
744 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
745 0F98, and 0F99.
746 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
747 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
748 0F98, and 0F99.
749 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
750 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
751 0F98, and 0F99.
752
14d10c6c
JB		 7532021-03-10 Jan Beulich <jbeulich@suse.com>
754
755 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
756 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
757 REG_VEX_0F73_M_0 respectively.
758 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
759 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
760 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
761 MOD_VEX_0F73_REG_7): Delete.
762 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
763 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
764 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
765 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
766 PREFIX_VEX_0F3AF0_L_0 respectively.
767 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
768 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
769 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
770 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
771 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
772 VEX_LEN_0F38F7): New.
773 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
774 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
775 0F72, and 0F73. No longer link to vex_len_table[] for opcode
776 0F38F3.
777 (prefix_table): No longer link to vex_len_table[] for opcodes
778 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
779 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
780 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
781 0F38F6, 0F38F7, and 0F3AF0.
782 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
783 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
784 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
785 0F73.
786
00ec1875
JB		 7872021-03-10 Jan Beulich <jbeulich@suse.com>
788
789 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
790 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
791 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
792 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
793 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
794 (MOD_0F71, MOD_0F72, MOD_0F73): New.
795 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
796 73.
797 (reg_table): No longer link to mod_table[] for opcodes 0F71,
798 0F72, and 0F73.
799 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
800 0F73.
801
31941983
JB		 8022021-03-10 Jan Beulich <jbeulich@suse.com>
803
804 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
805 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
806 (reg_table): Don't link to mod_table[] where not needed. Add
807 PREFIX_IGNORED to nop entries.
808 (prefix_table): Replace PREFIX_OPCODE in nop entries.
809 (mod_table): Add nop entries next to prefetch ones. Drop
810 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
811 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
812 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
813 PREFIX_OPCODE from endbr* entries.
814 (get_valid_dis386): Also consider entry's name when zapping
815 vindex.
816 (print_insn): Handle PREFIX_IGNORED.
817
742732c7
JB		 8182021-03-09 Jan Beulich <jbeulich@suse.com>
819
820 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
821 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
822 element.
823 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
824 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
825 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
826 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
827 (struct i386_opcode_modifier): Delete notrackprefixok,
828 islockable, hleprefixok, and repprefixok fields. Add prefixok
829 field.
830 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
831 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
832 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
833 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
834 Replace HLEPrefixOk.
835 * opcodes/i386-tbl.h: Re-generate.
836
e93a3b27
JB		 8372021-03-09 Jan Beulich <jbeulich@suse.com>
838
839 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
840 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
841 64-bit form.
842 * opcodes/i386-tbl.h: Re-generate.
843
75363b6d
JB		 8442021-03-03 Jan Beulich <jbeulich@suse.com>
845
846 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
847 for {} instead of {0}. Don't look for '0'.
848 * i386-opc.tbl: Drop operand count field. Drop redundant operand
849 size specifiers.
850
5a9f5403
NC		 8512021-02-19 Nelson Chu <nelson.chu@sifive.com>
852
853 PR 27158
854 * riscv-dis.c (print_insn_args): Updated encoding macros.
855 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
856 (match_c_addi16sp): Updated encoding macros.
857 (match_c_lui): Likewise.
858 (match_c_lui_with_hint): Likewise.
859 (match_c_addi4spn): Likewise.
860 (match_c_slli): Likewise.
861 (match_slli_as_c_slli): Likewise.
862 (match_c_slli64): Likewise.
863 (match_srxi_as_c_srxi): Likewise.
864 (riscv_insn_types): Added .insn css/cl/cs.
865
3d73d29e
NC		 8662021-02-18 Nelson Chu <nelson.chu@sifive.com>
867
868 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
869 (default_priv_spec): Updated type to riscv_spec_class.
870 (parse_riscv_dis_option): Updated.
871 * riscv-opc.c: Moved stuff and make the file tidy.
872
b9b204b3
AM		 8732021-02-17 Alan Modra <amodra@gmail.com>
874
875 * wasm32-dis.c: Include limits.h.
876 (CHAR_BIT): Provide backup define.
877 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
878 Correct signed overflow checking.
879
394ae71f
JB		 8802021-02-16 Jan Beulich <jbeulich@suse.com>
881
882 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
883 * i386-tbl.h: Re-generate.
884
b818b220
JB		 8852021-02-16 Jan Beulich <jbeulich@suse.com>
886
887 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
888 Oword.
889 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
890
ba2b480f
AK		 8912021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
892
893 * s390-mkopc.c (main): Accept arch14 as cpu string.
894 * s390-opc.txt: Add new arch14 instructions.
895
95148614
NA		 8962021-02-04 Nick Alcock <nick.alcock@oracle.com>
897
898 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
899 favour of LIBINTL.
900 * configure: Regenerated.
901
bfd428bc
MF		 9022021-02-08 Mike Frysinger <vapier@gentoo.org>
903
904 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
905 * tic54x-opc.c (regs): Rename to ...
906 (tic54x_regs): ... this.
907 (mmregs): Rename to ...
908 (tic54x_mmregs): ... this.
909 (condition_codes): Rename to ...
910 (tic54x_condition_codes): ... this.
911 (cc2_codes): Rename to ...
912 (tic54x_cc2_codes): ... this.
913 (cc3_codes): Rename to ...
914 (tic54x_cc3_codes): ... this.
915 (status_bits): Rename to ...
916 (tic54x_status_bits): ... this.
917 (misc_symbols): Rename to ...
918 (tic54x_misc_symbols): ... this.
919
24075dcc
NC		 9202021-02-04 Nelson Chu <nelson.chu@sifive.com>
921
922 * riscv-opc.c (MASK_RVB_IMM): Removed.
923 (riscv_opcodes): Removed zb* instructions.
924 (riscv_ext_version_table): Removed versions for zb*.
925
c3ffb8f3
AM		 9262021-01-26 Alan Modra <amodra@gmail.com>
927
928 * i386-gen.c (parse_template): Ensure entire template_instance
929 is initialised.
930
1942a048
NC		 9312021-01-15 Nelson Chu <nelson.chu@sifive.com>
932
933 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
934 (riscv_fpr_names_abi): Likewise.
935 (riscv_opcodes): Likewise.
936 (riscv_insn_types): Likewise.
937
b800637e
NC		 9382021-01-15 Nelson Chu <nelson.chu@sifive.com>
939
940 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
941
dcd709e0
NC		 9422021-01-15 Nelson Chu <nelson.chu@sifive.com>
943
944 * riscv-dis.c: Comments tidy and improvement.
945 * riscv-opc.c: Likewise.
946
5347ed60
AM		 9472021-01-13 Alan Modra <amodra@gmail.com>
948
949 * Makefile.in: Regenerate.
950
d546b610
L		 9512021-01-12 H.J. Lu <hongjiu.lu@intel.com>
952
953 PR binutils/26792
954 * configure.ac: Use GNU_MAKE_JOBSERVER.
955 * aclocal.m4: Regenerated.
956 * configure: Likewise.
957
6d104cac
NC		 9582021-01-12 Nick Clifton <nickc@redhat.com>
959
960 * po/sr.po: Updated Serbian translation.
961
83b33c6c
L		 9622021-01-11 H.J. Lu <hongjiu.lu@intel.com>
963
964 PR ld/27173
965 * configure: Regenerated.
966
82c70b08
KT		 9672021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
968
969 * aarch64-asm-2.c: Regenerate.
970 * aarch64-dis-2.c: Likewise.
971 * aarch64-opc-2.c: Likewise.
972 * aarch64-opc.c (aarch64_print_operand):
973 Delete handling of AARCH64_OPND_CSRE_CSR.
974 * aarch64-tbl.h (aarch64_feature_csre): Delete.
975 (CSRE): Likewise.
976 (_CSRE_INSN): Likewise.
977 (aarch64_opcode_table): Delete csr.
978
a8aa72b9
NC		 9792021-01-11 Nick Clifton <nickc@redhat.com>
980
981 * po/de.po: Updated German translation.
982 * po/fr.po: Updated French translation.
983 * po/pt_BR.po: Updated Brazilian Portuguese translation.
984 * po/sv.po: Updated Swedish translation.
985 * po/uk.po: Updated Ukranian translation.
986
a4966cd9
L		 9872021-01-09 H.J. Lu <hongjiu.lu@intel.com>
988
989 * configure: Regenerated.
990
573fe3fb
NC		 9912021-01-09 Nick Clifton <nickc@redhat.com>
992
993 * configure: Regenerate.
994 * po/opcodes.pot: Regenerate.
995
055bc77a
NC		 9962021-01-09 Nick Clifton <nickc@redhat.com>
997
998 * 2.36 release branch crated.
999
aae7fcb8
PB		 10002021-01-08 Peter Bergner <bergner@linux.ibm.com>
1001
1002 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1003 (DW, (XRC_MASK): Define.
1004 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1005
64307045
AM		 10062021-01-09 Alan Modra <amodra@gmail.com>
1007
1008 * configure: Regenerate.
1009
ed205222
NC		 10102021-01-08 Nick Clifton <nickc@redhat.com>
1011
1012 * po/sv.po: Updated Swedish translation.
1013
fb932b57
NC		 10142021-01-08 Nick Clifton <nickc@redhat.com>
1015
e84c8716
NC		 1016 PR 27129
1017 * aarch64-dis.c (determine_disassembling_preference): Move call to
1018 aarch64_match_operands_constraint outside of the assertion.
1019 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1020 Replace with a return of FALSE.
1021
fb932b57
NC		 1022 PR 27139
1023 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1024 core system register.
1025
f4782128
ST		 10262021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1027
1028 * configure: Regenerate.
1029
1b0927db
NC		 10302021-01-07 Nick Clifton <nickc@redhat.com>
1031
1032 * po/fr.po: Updated French translation.
1033
3b288c8e
FN		 10342021-01-07 Fredrik Noring <noring@nocrew.org>
1035
1036 * m68k-opc.c (chkl): Change minimum architecture requirement to
1037 m68020.
1038
aa881ecd
PT		 10392021-01-07 Philipp Tomsich <prt@gnu.org>
1040
1041 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1042
2652cfad
CXW		 10432021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1044 Jim Wilson <jimw@sifive.com>
1045 Andrew Waterman <andrew@sifive.com>
1046 Maxim Blinov <maxim.blinov@embecosm.com>
1047 Kito Cheng <kito.cheng@sifive.com>
1048 Nelson Chu <nelson.chu@sifive.com>
1049
1050 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1051 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1052
250d07de
AM		 10532021-01-01 Alan Modra <amodra@gmail.com>
1054
1055 Update year range in copyright notice of all files.
1056
c2795844 1057For older changes see ChangeLog-2020
3499769a 1058\f
c2795844 1059Copyright (C) 2021 Free Software Foundation, Inc.
3499769a
AM		 1060
1061Copying and distribution of this file, with or without modification,
1062are permitted in any medium without royalty provided the copyright
1063notice and this notice are preserved.
1064
1065Local Variables:
1066mode: change-log
1067left-margin: 8
1068fill-column: 74
1069version-control: never
1070End:
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