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a06ea964 | 1 | /* aarch64-dis.c -- AArch64 disassembler. |
b3adc24a | 2 | Copyright (C) 2009-2020 Free Software Foundation, Inc. |
a06ea964 NC |
3 | Contributed by ARM Ltd. |
4 | ||
5 | This file is part of the GNU opcodes library. | |
6 | ||
7 | This library is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | It is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; see the file COPYING3. If not, | |
19 | see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "sysdep.h" | |
22 | #include "bfd_stdint.h" | |
6394c606 | 23 | #include "disassemble.h" |
a06ea964 NC |
24 | #include "libiberty.h" |
25 | #include "opintl.h" | |
26 | #include "aarch64-dis.h" | |
a06ea964 | 27 | #include "elf-bfd.h" |
8b21361b | 28 | #include "elf/aarch64.h" |
a06ea964 | 29 | |
a06ea964 NC |
30 | #define INSNLEN 4 |
31 | ||
95830c98 | 32 | static aarch64_feature_set arch_variant; /* See select_aarch64_variant. */ |
a06ea964 NC |
33 | static enum map_type last_type; |
34 | static int last_mapping_sym = -1; | |
53b2f36b | 35 | static bfd_vma last_stop_offset = 0; |
a06ea964 NC |
36 | static bfd_vma last_mapping_addr = 0; |
37 | ||
c900c916 | 38 | #define MAYBE_C64 (last_type == MAP_TYPE_C64 ? AARCH64_FEATURE_C64 : 0) |
3979cf50 | 39 | |
a06ea964 NC |
40 | /* Other options */ |
41 | static int no_aliases = 0; /* If set disassemble as most general inst. */ | |
7d02540a TC |
42 | \fstatic int no_notes = 1; /* If set do not print disassemble notes in the |
43 | output as comments. */ | |
a06ea964 | 44 | |
7e84b55d | 45 | /* Currently active instruction sequence. */ |
bde90be2 | 46 | static aarch64_instr_sequence insn_sequence; |
7e84b55d | 47 | |
a06ea964 NC |
48 | static void |
49 | set_default_aarch64_dis_options (struct disassemble_info *info ATTRIBUTE_UNUSED) | |
50 | { | |
51 | } | |
52 | ||
53 | static void | |
54 | parse_aarch64_dis_option (const char *option, unsigned int len ATTRIBUTE_UNUSED) | |
55 | { | |
56 | /* Try to match options that are simple flags */ | |
57 | if (CONST_STRNEQ (option, "no-aliases")) | |
58 | { | |
59 | no_aliases = 1; | |
60 | return; | |
61 | } | |
62 | ||
63 | if (CONST_STRNEQ (option, "aliases")) | |
64 | { | |
65 | no_aliases = 0; | |
66 | return; | |
67 | } | |
68 | ||
7d02540a TC |
69 | if (CONST_STRNEQ (option, "no-notes")) |
70 | { | |
71 | no_notes = 1; | |
72 | return; | |
73 | } | |
74 | ||
75 | if (CONST_STRNEQ (option, "notes")) | |
76 | { | |
77 | no_notes = 0; | |
78 | return; | |
79 | } | |
80 | ||
a06ea964 NC |
81 | #ifdef DEBUG_AARCH64 |
82 | if (CONST_STRNEQ (option, "debug_dump")) | |
83 | { | |
84 | debug_dump = 1; | |
85 | return; | |
86 | } | |
87 | #endif /* DEBUG_AARCH64 */ | |
88 | ||
89 | /* Invalid option. */ | |
a6743a54 | 90 | opcodes_error_handler (_("unrecognised disassembler option: %s"), option); |
a06ea964 NC |
91 | } |
92 | ||
93 | static void | |
94 | parse_aarch64_dis_options (const char *options) | |
95 | { | |
96 | const char *option_end; | |
97 | ||
98 | if (options == NULL) | |
99 | return; | |
100 | ||
101 | while (*options != '\0') | |
102 | { | |
103 | /* Skip empty options. */ | |
104 | if (*options == ',') | |
105 | { | |
106 | options++; | |
107 | continue; | |
108 | } | |
109 | ||
110 | /* We know that *options is neither NUL or a comma. */ | |
111 | option_end = options + 1; | |
112 | while (*option_end != ',' && *option_end != '\0') | |
113 | option_end++; | |
114 | ||
115 | parse_aarch64_dis_option (options, option_end - options); | |
116 | ||
117 | /* Go on to the next one. If option_end points to a comma, it | |
118 | will be skipped above. */ | |
119 | options = option_end; | |
120 | } | |
121 | } | |
122 | \f | |
123 | /* Functions doing the instruction disassembling. */ | |
124 | ||
125 | /* The unnamed arguments consist of the number of fields and information about | |
126 | these fields where the VALUE will be extracted from CODE and returned. | |
127 | MASK can be zero or the base mask of the opcode. | |
128 | ||
129 | N.B. the fields are required to be in such an order than the most signficant | |
130 | field for VALUE comes the first, e.g. the <index> in | |
131 | SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>] | |
9aff4b7a | 132 | is encoded in H:L:M in some cases, the fields H:L:M should be passed in |
a06ea964 NC |
133 | the order of H, L, M. */ |
134 | ||
c0890d26 | 135 | aarch64_insn |
a06ea964 NC |
136 | extract_fields (aarch64_insn code, aarch64_insn mask, ...) |
137 | { | |
138 | uint32_t num; | |
139 | const aarch64_field *field; | |
140 | enum aarch64_field_kind kind; | |
141 | va_list va; | |
142 | ||
143 | va_start (va, mask); | |
144 | num = va_arg (va, uint32_t); | |
145 | assert (num <= 5); | |
146 | aarch64_insn value = 0x0; | |
147 | while (num--) | |
148 | { | |
149 | kind = va_arg (va, enum aarch64_field_kind); | |
150 | field = &fields[kind]; | |
151 | value <<= field->width; | |
152 | value |= extract_field (kind, code, mask); | |
153 | } | |
154 | return value; | |
155 | } | |
156 | ||
b5464a68 RS |
157 | /* Extract the value of all fields in SELF->fields from instruction CODE. |
158 | The least significant bit comes from the final field. */ | |
159 | ||
160 | static aarch64_insn | |
161 | extract_all_fields (const aarch64_operand *self, aarch64_insn code) | |
162 | { | |
163 | aarch64_insn value; | |
164 | unsigned int i; | |
165 | enum aarch64_field_kind kind; | |
166 | ||
167 | value = 0; | |
168 | for (i = 0; i < ARRAY_SIZE (self->fields) && self->fields[i] != FLD_NIL; ++i) | |
169 | { | |
170 | kind = self->fields[i]; | |
171 | value <<= fields[kind].width; | |
172 | value |= extract_field (kind, code, 0); | |
173 | } | |
174 | return value; | |
175 | } | |
176 | ||
a06ea964 | 177 | /* Sign-extend bit I of VALUE. */ |
f81e7e2d | 178 | static inline uint64_t |
a06ea964 NC |
179 | sign_extend (aarch64_insn value, unsigned i) |
180 | { | |
f81e7e2d | 181 | uint64_t ret, sign; |
a06ea964 NC |
182 | |
183 | assert (i < 32); | |
f81e7e2d AM |
184 | ret = value; |
185 | sign = (uint64_t) 1 << i; | |
186 | return ((ret & (sign + sign - 1)) ^ sign) - sign; | |
a06ea964 NC |
187 | } |
188 | ||
189 | /* N.B. the following inline helpfer functions create a dependency on the | |
190 | order of operand qualifier enumerators. */ | |
191 | ||
192 | /* Given VALUE, return qualifier for a general purpose register. */ | |
193 | static inline enum aarch64_opnd_qualifier | |
194 | get_greg_qualifier_from_value (aarch64_insn value) | |
195 | { | |
196 | enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_W + value; | |
197 | assert (value <= 0x1 | |
198 | && aarch64_get_qualifier_standard_value (qualifier) == value); | |
199 | return qualifier; | |
200 | } | |
201 | ||
3067d3b9 MW |
202 | /* Given VALUE, return qualifier for a vector register. This does not support |
203 | decoding instructions that accept the 2H vector type. */ | |
204 | ||
a06ea964 NC |
205 | static inline enum aarch64_opnd_qualifier |
206 | get_vreg_qualifier_from_value (aarch64_insn value) | |
207 | { | |
208 | enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_V_8B + value; | |
209 | ||
3067d3b9 MW |
210 | /* Instructions using vector type 2H should not call this function. Skip over |
211 | the 2H qualifier. */ | |
212 | if (qualifier >= AARCH64_OPND_QLF_V_2H) | |
213 | qualifier += 1; | |
214 | ||
a06ea964 NC |
215 | assert (value <= 0x8 |
216 | && aarch64_get_qualifier_standard_value (qualifier) == value); | |
217 | return qualifier; | |
218 | } | |
219 | ||
220 | /* Given VALUE, return qualifier for an FP or AdvSIMD scalar register. */ | |
221 | static inline enum aarch64_opnd_qualifier | |
222 | get_sreg_qualifier_from_value (aarch64_insn value) | |
223 | { | |
224 | enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_S_B + value; | |
225 | ||
226 | assert (value <= 0x4 | |
227 | && aarch64_get_qualifier_standard_value (qualifier) == value); | |
228 | return qualifier; | |
229 | } | |
230 | ||
231 | /* Given the instruction in *INST which is probably half way through the | |
232 | decoding and our caller wants to know the expected qualifier for operand | |
233 | I. Return such a qualifier if we can establish it; otherwise return | |
234 | AARCH64_OPND_QLF_NIL. */ | |
235 | ||
236 | static aarch64_opnd_qualifier_t | |
237 | get_expected_qualifier (const aarch64_inst *inst, int i) | |
238 | { | |
239 | aarch64_opnd_qualifier_seq_t qualifiers; | |
240 | /* Should not be called if the qualifier is known. */ | |
241 | assert (inst->operands[i].qualifier == AARCH64_OPND_QLF_NIL); | |
242 | if (aarch64_find_best_match (inst, inst->opcode->qualifiers_list, | |
243 | i, qualifiers)) | |
244 | return qualifiers[i]; | |
245 | else | |
246 | return AARCH64_OPND_QLF_NIL; | |
247 | } | |
248 | ||
249 | /* Operand extractors. */ | |
250 | ||
c2e5c986 SD |
251 | bfd_boolean |
252 | aarch64_ext_none (const aarch64_operand *self ATTRIBUTE_UNUSED, | |
253 | aarch64_opnd_info *info ATTRIBUTE_UNUSED, | |
254 | const aarch64_insn code ATTRIBUTE_UNUSED, | |
255 | const aarch64_inst *inst ATTRIBUTE_UNUSED, | |
256 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
257 | { | |
258 | return TRUE; | |
259 | } | |
260 | ||
561a72d4 | 261 | bfd_boolean |
a06ea964 NC |
262 | aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info, |
263 | const aarch64_insn code, | |
561a72d4 TC |
264 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
265 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
266 | { |
267 | info->reg.regno = extract_field (self->fields[0], code, 0); | |
dc64c2ba SP |
268 | /* For capability registers, set the qualifier. */ |
269 | if (aarch64_get_operand_class (info->type) == AARCH64_OPND_CLASS_CAP_REG) | |
270 | info->qualifier = AARCH64_OPND_QLF_CA; | |
271 | ||
321c4e1a SP |
272 | /* Reject the A64 disassembly of ADR when in C64. */ |
273 | if (inst->opcode->iclass == pcreladdr && MAYBE_C64 | |
274 | && info->type != AARCH64_OPND_Cad) | |
275 | return FALSE; | |
276 | ||
adffaa8e SP |
277 | /* Allow disassembly of A64 RET when encountered in C64 code. */ |
278 | if (inst->opcode->iclass == branch_reg) | |
279 | info->present = 1; | |
280 | ||
561a72d4 | 281 | return TRUE; |
a06ea964 NC |
282 | } |
283 | ||
561a72d4 | 284 | bfd_boolean |
ee804238 JW |
285 | aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, |
286 | const aarch64_insn code ATTRIBUTE_UNUSED, | |
561a72d4 TC |
287 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
288 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
ee804238 JW |
289 | { |
290 | assert (info->idx == 1 | |
291 | || info->idx ==3); | |
292 | info->reg.regno = inst->operands[info->idx - 1].reg.regno + 1; | |
561a72d4 | 293 | return TRUE; |
ee804238 JW |
294 | } |
295 | ||
a06ea964 | 296 | /* e.g. IC <ic_op>{, <Xt>}. */ |
561a72d4 | 297 | bfd_boolean |
a06ea964 NC |
298 | aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info, |
299 | const aarch64_insn code, | |
561a72d4 TC |
300 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
301 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
302 | { |
303 | info->reg.regno = extract_field (self->fields[0], code, 0); | |
304 | assert (info->idx == 1 | |
305 | && (aarch64_get_operand_class (inst->operands[0].type) | |
306 | == AARCH64_OPND_CLASS_SYSTEM)); | |
307 | /* This will make the constraint checking happy and more importantly will | |
308 | help the disassembler determine whether this operand is optional or | |
309 | not. */ | |
ea2deeec | 310 | info->present = aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op); |
a06ea964 | 311 | |
561a72d4 | 312 | return TRUE; |
a06ea964 NC |
313 | } |
314 | ||
315 | /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */ | |
561a72d4 | 316 | bfd_boolean |
a06ea964 NC |
317 | aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, |
318 | const aarch64_insn code, | |
561a72d4 TC |
319 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
320 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
321 | { |
322 | /* regno */ | |
323 | info->reglane.regno = extract_field (self->fields[0], code, | |
324 | inst->opcode->mask); | |
325 | ||
326 | /* Index and/or type. */ | |
327 | if (inst->opcode->iclass == asisdone | |
328 | || inst->opcode->iclass == asimdins) | |
329 | { | |
330 | if (info->type == AARCH64_OPND_En | |
331 | && inst->opcode->operands[0] == AARCH64_OPND_Ed) | |
332 | { | |
333 | unsigned shift; | |
334 | /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */ | |
335 | assert (info->idx == 1); /* Vn */ | |
336 | aarch64_insn value = extract_field (FLD_imm4, code, 0); | |
337 | /* Depend on AARCH64_OPND_Ed to determine the qualifier. */ | |
338 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
339 | shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier)); | |
340 | info->reglane.index = value >> shift; | |
341 | } | |
342 | else | |
343 | { | |
344 | /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>]. | |
345 | imm5<3:0> <V> | |
346 | 0000 RESERVED | |
347 | xxx1 B | |
348 | xx10 H | |
349 | x100 S | |
350 | 1000 D */ | |
351 | int pos = -1; | |
352 | aarch64_insn value = extract_field (FLD_imm5, code, 0); | |
353 | while (++pos <= 3 && (value & 0x1) == 0) | |
354 | value >>= 1; | |
355 | if (pos > 3) | |
561a72d4 | 356 | return FALSE; |
a06ea964 NC |
357 | info->qualifier = get_sreg_qualifier_from_value (pos); |
358 | info->reglane.index = (unsigned) (value >> 1); | |
359 | } | |
360 | } | |
65a55fbb TC |
361 | else if (inst->opcode->iclass == dotproduct) |
362 | { | |
363 | /* Need information in other operand(s) to help decoding. */ | |
364 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
365 | switch (info->qualifier) | |
366 | { | |
00c2093f | 367 | case AARCH64_OPND_QLF_S_4B: |
df678013 | 368 | case AARCH64_OPND_QLF_S_2H: |
65a55fbb TC |
369 | /* L:H */ |
370 | info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); | |
371 | info->reglane.regno &= 0x1f; | |
372 | break; | |
373 | default: | |
561a72d4 | 374 | return FALSE; |
65a55fbb TC |
375 | } |
376 | } | |
f42f1a1d TC |
377 | else if (inst->opcode->iclass == cryptosm3) |
378 | { | |
379 | /* index for e.g. SM3TT2A <Vd>.4S, <Vn>.4S, <Vm>S[<imm2>]. */ | |
380 | info->reglane.index = extract_field (FLD_SM3_imm2, code, 0); | |
381 | } | |
a06ea964 NC |
382 | else |
383 | { | |
384 | /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>] | |
385 | or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */ | |
386 | ||
387 | /* Need information in other operand(s) to help decoding. */ | |
388 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
389 | switch (info->qualifier) | |
390 | { | |
391 | case AARCH64_OPND_QLF_S_H: | |
369c9167 TC |
392 | if (info->type == AARCH64_OPND_Em16) |
393 | { | |
394 | /* h:l:m */ | |
395 | info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L, | |
396 | FLD_M); | |
397 | info->reglane.regno &= 0xf; | |
398 | } | |
399 | else | |
400 | { | |
401 | /* h:l */ | |
402 | info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); | |
403 | } | |
a06ea964 NC |
404 | break; |
405 | case AARCH64_OPND_QLF_S_S: | |
406 | /* h:l */ | |
407 | info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); | |
408 | break; | |
409 | case AARCH64_OPND_QLF_S_D: | |
410 | /* H */ | |
411 | info->reglane.index = extract_field (FLD_H, code, 0); | |
412 | break; | |
413 | default: | |
561a72d4 | 414 | return FALSE; |
a06ea964 | 415 | } |
c2c4ff8d | 416 | |
369c9167 TC |
417 | if (inst->opcode->op == OP_FCMLA_ELEM |
418 | && info->qualifier != AARCH64_OPND_QLF_S_H) | |
c2c4ff8d SN |
419 | { |
420 | /* Complex operand takes two elements. */ | |
421 | if (info->reglane.index & 1) | |
561a72d4 | 422 | return FALSE; |
c2c4ff8d SN |
423 | info->reglane.index /= 2; |
424 | } | |
a06ea964 NC |
425 | } |
426 | ||
561a72d4 | 427 | return TRUE; |
a06ea964 NC |
428 | } |
429 | ||
561a72d4 | 430 | bfd_boolean |
a06ea964 NC |
431 | aarch64_ext_reglist (const aarch64_operand *self, aarch64_opnd_info *info, |
432 | const aarch64_insn code, | |
561a72d4 TC |
433 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
434 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
435 | { |
436 | /* R */ | |
437 | info->reglist.first_regno = extract_field (self->fields[0], code, 0); | |
438 | /* len */ | |
439 | info->reglist.num_regs = extract_field (FLD_len, code, 0) + 1; | |
561a72d4 | 440 | return TRUE; |
a06ea964 NC |
441 | } |
442 | ||
443 | /* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions. */ | |
561a72d4 | 444 | bfd_boolean |
a06ea964 NC |
445 | aarch64_ext_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED, |
446 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
447 | const aarch64_inst *inst, |
448 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
449 | { |
450 | aarch64_insn value; | |
451 | /* Number of elements in each structure to be loaded/stored. */ | |
452 | unsigned expected_num = get_opcode_dependent_value (inst->opcode); | |
453 | ||
454 | struct | |
455 | { | |
456 | unsigned is_reserved; | |
457 | unsigned num_regs; | |
458 | unsigned num_elements; | |
459 | } data [] = | |
460 | { {0, 4, 4}, | |
461 | {1, 4, 4}, | |
462 | {0, 4, 1}, | |
463 | {0, 4, 2}, | |
464 | {0, 3, 3}, | |
465 | {1, 3, 3}, | |
466 | {0, 3, 1}, | |
467 | {0, 1, 1}, | |
468 | {0, 2, 2}, | |
469 | {1, 2, 2}, | |
470 | {0, 2, 1}, | |
471 | }; | |
472 | ||
473 | /* Rt */ | |
474 | info->reglist.first_regno = extract_field (FLD_Rt, code, 0); | |
475 | /* opcode */ | |
476 | value = extract_field (FLD_opcode, code, 0); | |
cd3ea7c6 NC |
477 | /* PR 21595: Check for a bogus value. */ |
478 | if (value >= ARRAY_SIZE (data)) | |
561a72d4 | 479 | return FALSE; |
a06ea964 | 480 | if (expected_num != data[value].num_elements || data[value].is_reserved) |
561a72d4 | 481 | return FALSE; |
a06ea964 NC |
482 | info->reglist.num_regs = data[value].num_regs; |
483 | ||
561a72d4 | 484 | return TRUE; |
a06ea964 NC |
485 | } |
486 | ||
487 | /* Decode Rt and S fields of Vt in AdvSIMD load single structure to all | |
488 | lanes instructions. */ | |
561a72d4 | 489 | bfd_boolean |
a06ea964 NC |
490 | aarch64_ext_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED, |
491 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
492 | const aarch64_inst *inst, |
493 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
494 | { |
495 | aarch64_insn value; | |
496 | ||
497 | /* Rt */ | |
498 | info->reglist.first_regno = extract_field (FLD_Rt, code, 0); | |
499 | /* S */ | |
500 | value = extract_field (FLD_S, code, 0); | |
501 | ||
502 | /* Number of registers is equal to the number of elements in | |
503 | each structure to be loaded/stored. */ | |
504 | info->reglist.num_regs = get_opcode_dependent_value (inst->opcode); | |
505 | assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4); | |
506 | ||
507 | /* Except when it is LD1R. */ | |
508 | if (info->reglist.num_regs == 1 && value == (aarch64_insn) 1) | |
509 | info->reglist.num_regs = 2; | |
510 | ||
561a72d4 | 511 | return TRUE; |
a06ea964 NC |
512 | } |
513 | ||
514 | /* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD | |
515 | load/store single element instructions. */ | |
561a72d4 | 516 | bfd_boolean |
a06ea964 NC |
517 | aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, |
518 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
519 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
520 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
521 | { |
522 | aarch64_field field = {0, 0}; | |
523 | aarch64_insn QSsize; /* fields Q:S:size. */ | |
524 | aarch64_insn opcodeh2; /* opcode<2:1> */ | |
525 | ||
526 | /* Rt */ | |
527 | info->reglist.first_regno = extract_field (FLD_Rt, code, 0); | |
528 | ||
529 | /* Decode the index, opcode<2:1> and size. */ | |
530 | gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field); | |
531 | opcodeh2 = extract_field_2 (&field, code, 0); | |
532 | QSsize = extract_fields (code, 0, 3, FLD_Q, FLD_S, FLD_vldst_size); | |
533 | switch (opcodeh2) | |
534 | { | |
535 | case 0x0: | |
536 | info->qualifier = AARCH64_OPND_QLF_S_B; | |
537 | /* Index encoded in "Q:S:size". */ | |
538 | info->reglist.index = QSsize; | |
539 | break; | |
540 | case 0x1: | |
76dfed02 YZ |
541 | if (QSsize & 0x1) |
542 | /* UND. */ | |
561a72d4 | 543 | return FALSE; |
a06ea964 NC |
544 | info->qualifier = AARCH64_OPND_QLF_S_H; |
545 | /* Index encoded in "Q:S:size<1>". */ | |
546 | info->reglist.index = QSsize >> 1; | |
547 | break; | |
548 | case 0x2: | |
76dfed02 YZ |
549 | if ((QSsize >> 1) & 0x1) |
550 | /* UND. */ | |
561a72d4 | 551 | return FALSE; |
a06ea964 NC |
552 | if ((QSsize & 0x1) == 0) |
553 | { | |
554 | info->qualifier = AARCH64_OPND_QLF_S_S; | |
555 | /* Index encoded in "Q:S". */ | |
556 | info->reglist.index = QSsize >> 2; | |
557 | } | |
558 | else | |
559 | { | |
a06ea964 NC |
560 | if (extract_field (FLD_S, code, 0)) |
561 | /* UND */ | |
561a72d4 | 562 | return FALSE; |
76dfed02 YZ |
563 | info->qualifier = AARCH64_OPND_QLF_S_D; |
564 | /* Index encoded in "Q". */ | |
565 | info->reglist.index = QSsize >> 3; | |
a06ea964 NC |
566 | } |
567 | break; | |
568 | default: | |
561a72d4 | 569 | return FALSE; |
a06ea964 NC |
570 | } |
571 | ||
572 | info->reglist.has_index = 1; | |
573 | info->reglist.num_regs = 0; | |
574 | /* Number of registers is equal to the number of elements in | |
575 | each structure to be loaded/stored. */ | |
576 | info->reglist.num_regs = get_opcode_dependent_value (inst->opcode); | |
577 | assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4); | |
578 | ||
561a72d4 | 579 | return TRUE; |
a06ea964 NC |
580 | } |
581 | ||
582 | /* Decode fields immh:immb and/or Q for e.g. | |
583 | SSHR <Vd>.<T>, <Vn>.<T>, #<shift> | |
584 | or SSHR <V><d>, <V><n>, #<shift>. */ | |
585 | ||
561a72d4 | 586 | bfd_boolean |
a06ea964 NC |
587 | aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED, |
588 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
589 | const aarch64_inst *inst, |
590 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
591 | { |
592 | int pos; | |
593 | aarch64_insn Q, imm, immh; | |
594 | enum aarch64_insn_class iclass = inst->opcode->iclass; | |
595 | ||
596 | immh = extract_field (FLD_immh, code, 0); | |
597 | if (immh == 0) | |
561a72d4 | 598 | return FALSE; |
a06ea964 NC |
599 | imm = extract_fields (code, 0, 2, FLD_immh, FLD_immb); |
600 | pos = 4; | |
601 | /* Get highest set bit in immh. */ | |
602 | while (--pos >= 0 && (immh & 0x8) == 0) | |
603 | immh <<= 1; | |
604 | ||
605 | assert ((iclass == asimdshf || iclass == asisdshf) | |
606 | && (info->type == AARCH64_OPND_IMM_VLSR | |
607 | || info->type == AARCH64_OPND_IMM_VLSL)); | |
608 | ||
609 | if (iclass == asimdshf) | |
610 | { | |
611 | Q = extract_field (FLD_Q, code, 0); | |
612 | /* immh Q <T> | |
613 | 0000 x SEE AdvSIMD modified immediate | |
614 | 0001 0 8B | |
615 | 0001 1 16B | |
616 | 001x 0 4H | |
617 | 001x 1 8H | |
618 | 01xx 0 2S | |
619 | 01xx 1 4S | |
620 | 1xxx 0 RESERVED | |
621 | 1xxx 1 2D */ | |
622 | info->qualifier = | |
623 | get_vreg_qualifier_from_value ((pos << 1) | (int) Q); | |
624 | } | |
625 | else | |
626 | info->qualifier = get_sreg_qualifier_from_value (pos); | |
627 | ||
628 | if (info->type == AARCH64_OPND_IMM_VLSR) | |
629 | /* immh <shift> | |
630 | 0000 SEE AdvSIMD modified immediate | |
631 | 0001 (16-UInt(immh:immb)) | |
632 | 001x (32-UInt(immh:immb)) | |
633 | 01xx (64-UInt(immh:immb)) | |
634 | 1xxx (128-UInt(immh:immb)) */ | |
635 | info->imm.value = (16 << pos) - imm; | |
636 | else | |
637 | /* immh:immb | |
638 | immh <shift> | |
639 | 0000 SEE AdvSIMD modified immediate | |
640 | 0001 (UInt(immh:immb)-8) | |
641 | 001x (UInt(immh:immb)-16) | |
642 | 01xx (UInt(immh:immb)-32) | |
643 | 1xxx (UInt(immh:immb)-64) */ | |
644 | info->imm.value = imm - (8 << pos); | |
645 | ||
561a72d4 | 646 | return TRUE; |
a06ea964 NC |
647 | } |
648 | ||
649 | /* Decode shift immediate for e.g. sshr (imm). */ | |
561a72d4 | 650 | bfd_boolean |
a06ea964 NC |
651 | aarch64_ext_shll_imm (const aarch64_operand *self ATTRIBUTE_UNUSED, |
652 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
653 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
654 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
655 | { |
656 | int64_t imm; | |
657 | aarch64_insn val; | |
658 | val = extract_field (FLD_size, code, 0); | |
659 | switch (val) | |
660 | { | |
661 | case 0: imm = 8; break; | |
662 | case 1: imm = 16; break; | |
663 | case 2: imm = 32; break; | |
561a72d4 | 664 | default: return FALSE; |
a06ea964 NC |
665 | } |
666 | info->imm.value = imm; | |
561a72d4 | 667 | return TRUE; |
a06ea964 NC |
668 | } |
669 | ||
670 | /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>. | |
671 | value in the field(s) will be extracted as unsigned immediate value. */ | |
561a72d4 | 672 | bfd_boolean |
a06ea964 NC |
673 | aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info, |
674 | const aarch64_insn code, | |
561a72d4 TC |
675 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
676 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 | 677 | { |
f81e7e2d | 678 | uint64_t imm; |
b107ba42 | 679 | unsigned width_ofs = 1; |
a06ea964 | 680 | |
b5464a68 | 681 | imm = extract_all_fields (self, code); |
a06ea964 | 682 | |
321c4e1a SP |
683 | if (MAYBE_C64 && info->type == AARCH64_OPND_ADDR_ADRP) |
684 | { | |
685 | unsigned long highbit = 1UL << 20; | |
686 | ||
687 | /* False match, this is an ADRDP. */ | |
688 | if (!(imm & highbit)) | |
689 | return FALSE; | |
690 | ||
691 | imm &= (1UL << 20) - 1; | |
b107ba42 | 692 | width_ofs++; |
321c4e1a SP |
693 | } |
694 | ||
a06ea964 | 695 | if (operand_need_sign_extension (self)) |
b107ba42 | 696 | imm = sign_extend (imm, get_operand_fields_width (self) - width_ofs); |
a06ea964 NC |
697 | |
698 | if (operand_need_shift_by_two (self)) | |
699 | imm <<= 2; | |
193614f2 SD |
700 | else if (operand_need_shift_by_four (self)) |
701 | imm <<= 4; | |
a06ea964 | 702 | |
321c4e1a SP |
703 | if (info->type == AARCH64_OPND_ADDR_ADRP |
704 | || info->type == AARCH64_OPND_A64C_ADDR_ADRDP) | |
a06ea964 NC |
705 | imm <<= 12; |
706 | ||
707 | info->imm.value = imm; | |
561a72d4 | 708 | return TRUE; |
a06ea964 NC |
709 | } |
710 | ||
adffaa8e SP |
711 | /* Set immediate value #4 when decoding for e.g. BX. */ |
712 | bfd_boolean | |
713 | aarch64_ext_a64c_immv (const aarch64_operand *self ATTRIBUTE_UNUSED, | |
714 | aarch64_opnd_info *info, | |
715 | const aarch64_insn code ATTRIBUTE_UNUSED, | |
716 | const aarch64_inst *inst ATTRIBUTE_UNUSED, | |
717 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
718 | { | |
719 | if (info->type == AARCH64_OPND_A64C_IMMV4) | |
720 | { | |
721 | info->imm.value = 4; | |
722 | return TRUE; | |
723 | } | |
724 | if (info->type == AARCH64_OPND_A64C_CST_REG | |
725 | && (inst->opcode->iclass == br_sealed)) | |
726 | { | |
727 | info->reg.regno = 29; | |
728 | return TRUE; | |
729 | } | |
730 | ||
731 | return FALSE; | |
732 | } | |
733 | ||
a06ea964 | 734 | /* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */ |
561a72d4 | 735 | bfd_boolean |
a06ea964 NC |
736 | aarch64_ext_imm_half (const aarch64_operand *self, aarch64_opnd_info *info, |
737 | const aarch64_insn code, | |
561a72d4 TC |
738 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
739 | aarch64_operand_error *errors) | |
a06ea964 | 740 | { |
561a72d4 | 741 | aarch64_ext_imm (self, info, code, inst, errors); |
a06ea964 NC |
742 | info->shifter.kind = AARCH64_MOD_LSL; |
743 | info->shifter.amount = extract_field (FLD_hw, code, 0) << 4; | |
561a72d4 | 744 | return TRUE; |
a06ea964 NC |
745 | } |
746 | ||
747 | /* Decode cmode and "a:b:c:d:e:f:g:h" for e.g. | |
748 | MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */ | |
561a72d4 | 749 | bfd_boolean |
a06ea964 NC |
750 | aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, |
751 | aarch64_opnd_info *info, | |
752 | const aarch64_insn code, | |
561a72d4 TC |
753 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
754 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
755 | { |
756 | uint64_t imm; | |
757 | enum aarch64_opnd_qualifier opnd0_qualifier = inst->operands[0].qualifier; | |
758 | aarch64_field field = {0, 0}; | |
759 | ||
760 | assert (info->idx == 1); | |
761 | ||
762 | if (info->type == AARCH64_OPND_SIMD_FPIMM) | |
763 | info->imm.is_fp = 1; | |
764 | ||
765 | /* a:b:c:d:e:f:g:h */ | |
766 | imm = extract_fields (code, 0, 2, FLD_abc, FLD_defgh); | |
767 | if (!info->imm.is_fp && aarch64_get_qualifier_esize (opnd0_qualifier) == 8) | |
768 | { | |
769 | /* Either MOVI <Dd>, #<imm> | |
770 | or MOVI <Vd>.2D, #<imm>. | |
771 | <imm> is a 64-bit immediate | |
772 | 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh', | |
773 | encoded in "a:b:c:d:e:f:g:h". */ | |
774 | int i; | |
775 | unsigned abcdefgh = imm; | |
776 | for (imm = 0ull, i = 0; i < 8; i++) | |
777 | if (((abcdefgh >> i) & 0x1) != 0) | |
778 | imm |= 0xffull << (8 * i); | |
779 | } | |
780 | info->imm.value = imm; | |
781 | ||
782 | /* cmode */ | |
783 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
784 | switch (info->qualifier) | |
785 | { | |
786 | case AARCH64_OPND_QLF_NIL: | |
787 | /* no shift */ | |
788 | info->shifter.kind = AARCH64_MOD_NONE; | |
789 | return 1; | |
790 | case AARCH64_OPND_QLF_LSL: | |
791 | /* shift zeros */ | |
792 | info->shifter.kind = AARCH64_MOD_LSL; | |
793 | switch (aarch64_get_qualifier_esize (opnd0_qualifier)) | |
794 | { | |
795 | case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break; /* per word */ | |
796 | case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break; /* per half */ | |
f5555712 | 797 | case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break; /* per byte */ |
561a72d4 | 798 | default: assert (0); return FALSE; |
a06ea964 NC |
799 | } |
800 | /* 00: 0; 01: 8; 10:16; 11:24. */ | |
801 | info->shifter.amount = extract_field_2 (&field, code, 0) << 3; | |
802 | break; | |
803 | case AARCH64_OPND_QLF_MSL: | |
804 | /* shift ones */ | |
805 | info->shifter.kind = AARCH64_MOD_MSL; | |
806 | gen_sub_field (FLD_cmode, 0, 1, &field); /* per word */ | |
807 | info->shifter.amount = extract_field_2 (&field, code, 0) ? 16 : 8; | |
808 | break; | |
809 | default: | |
810 | assert (0); | |
561a72d4 | 811 | return FALSE; |
a06ea964 NC |
812 | } |
813 | ||
561a72d4 | 814 | return TRUE; |
a06ea964 NC |
815 | } |
816 | ||
aa2aa4c6 | 817 | /* Decode an 8-bit floating-point immediate. */ |
561a72d4 | 818 | bfd_boolean |
aa2aa4c6 RS |
819 | aarch64_ext_fpimm (const aarch64_operand *self, aarch64_opnd_info *info, |
820 | const aarch64_insn code, | |
561a72d4 TC |
821 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
822 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
aa2aa4c6 RS |
823 | { |
824 | info->imm.value = extract_all_fields (self, code); | |
825 | info->imm.is_fp = 1; | |
561a72d4 | 826 | return TRUE; |
aa2aa4c6 RS |
827 | } |
828 | ||
582e12bf | 829 | /* Decode a 1-bit rotate immediate (#90 or #270). */ |
561a72d4 | 830 | bfd_boolean |
582e12bf RS |
831 | aarch64_ext_imm_rotate1 (const aarch64_operand *self, aarch64_opnd_info *info, |
832 | const aarch64_insn code, | |
561a72d4 TC |
833 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
834 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
c2c4ff8d SN |
835 | { |
836 | uint64_t rot = extract_field (self->fields[0], code, 0); | |
582e12bf RS |
837 | assert (rot < 2U); |
838 | info->imm.value = rot * 180 + 90; | |
561a72d4 | 839 | return TRUE; |
582e12bf | 840 | } |
c2c4ff8d | 841 | |
582e12bf | 842 | /* Decode a 2-bit rotate immediate (#0, #90, #180 or #270). */ |
561a72d4 | 843 | bfd_boolean |
582e12bf RS |
844 | aarch64_ext_imm_rotate2 (const aarch64_operand *self, aarch64_opnd_info *info, |
845 | const aarch64_insn code, | |
561a72d4 TC |
846 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
847 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
582e12bf RS |
848 | { |
849 | uint64_t rot = extract_field (self->fields[0], code, 0); | |
850 | assert (rot < 4U); | |
c2c4ff8d | 851 | info->imm.value = rot * 90; |
561a72d4 | 852 | return TRUE; |
c2c4ff8d SN |
853 | } |
854 | ||
a06ea964 | 855 | /* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */ |
561a72d4 | 856 | bfd_boolean |
a06ea964 NC |
857 | aarch64_ext_fbits (const aarch64_operand *self ATTRIBUTE_UNUSED, |
858 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
859 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
860 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
861 | { |
862 | info->imm.value = 64- extract_field (FLD_scale, code, 0); | |
561a72d4 | 863 | return TRUE; |
a06ea964 NC |
864 | } |
865 | ||
dc64c2ba SP |
866 | static bfd_boolean |
867 | do_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED, | |
a06ea964 | 868 | aarch64_opnd_info *info, const aarch64_insn code, |
561a72d4 | 869 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
dc64c2ba SP |
870 | aarch64_operand_error *errors ATTRIBUTE_UNUSED, |
871 | int shift_amount, enum aarch64_field_kind imm, | |
872 | enum aarch64_field_kind shift) | |
a06ea964 NC |
873 | { |
874 | aarch64_insn value; | |
875 | ||
876 | info->shifter.kind = AARCH64_MOD_LSL; | |
877 | /* shift */ | |
dc64c2ba | 878 | value = extract_field (shift, code, 0); |
a06ea964 | 879 | if (value >= 2) |
561a72d4 | 880 | return FALSE; |
dc64c2ba SP |
881 | info->shifter.amount = value ? shift_amount : 0; |
882 | info->imm.value = extract_field (imm, code, 0); | |
a06ea964 | 883 | |
561a72d4 | 884 | return TRUE; |
a06ea964 NC |
885 | } |
886 | ||
0bd71233 SP |
887 | /* Decode arithmetic immediate for e.g. |
888 | SCBNDS <Cd|CSP>, <Cn|CSP>, #<imm> {, <shift>}. */ | |
889 | bfd_boolean | |
890 | aarch64_ext_a64c_imm6 (const aarch64_operand *self ATTRIBUTE_UNUSED, | |
891 | aarch64_opnd_info *info, const aarch64_insn code, | |
892 | const aarch64_inst *inst ATTRIBUTE_UNUSED, | |
893 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
894 | { | |
895 | return do_ext_aimm (self, info, code, inst, errors, 4, FLD_imm6_2, | |
896 | FLD_a64c_shift); | |
897 | } | |
898 | ||
dc64c2ba SP |
899 | /* Decode arithmetic immediate for e.g. |
900 | SUBS <Cd>, <Cn|CSP>, #<imm> {, <shift>}. */ | |
901 | bfd_boolean | |
902 | aarch64_ext_a64c_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED, | |
903 | aarch64_opnd_info *info, const aarch64_insn code, | |
904 | const aarch64_inst *inst ATTRIBUTE_UNUSED, | |
905 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
906 | { | |
907 | return do_ext_aimm (self, info, code, inst, errors, 12, FLD_imm12, | |
908 | FLD_a64c_shift_ai); | |
909 | } | |
910 | ||
911 | /* Decode arithmetic immediate for e.g. | |
912 | SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */ | |
913 | bfd_boolean | |
914 | aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED, | |
915 | aarch64_opnd_info *info, const aarch64_insn code, | |
916 | const aarch64_inst *inst ATTRIBUTE_UNUSED, | |
917 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
918 | { | |
919 | return do_ext_aimm (self, info, code, inst, errors, 12, FLD_imm12, | |
920 | FLD_shift); | |
921 | } | |
922 | ||
e950b345 RS |
923 | /* Return true if VALUE is a valid logical immediate encoding, storing the |
924 | decoded value in *RESULT if so. ESIZE is the number of bytes in the | |
925 | decoded immediate. */ | |
561a72d4 | 926 | static bfd_boolean |
e950b345 | 927 | decode_limm (uint32_t esize, aarch64_insn value, int64_t *result) |
a06ea964 NC |
928 | { |
929 | uint64_t imm, mask; | |
a06ea964 NC |
930 | uint32_t N, R, S; |
931 | unsigned simd_size; | |
a06ea964 NC |
932 | |
933 | /* value is N:immr:imms. */ | |
934 | S = value & 0x3f; | |
935 | R = (value >> 6) & 0x3f; | |
936 | N = (value >> 12) & 0x1; | |
937 | ||
a06ea964 NC |
938 | /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R |
939 | (in other words, right rotated by R), then replicated. */ | |
940 | if (N != 0) | |
941 | { | |
942 | simd_size = 64; | |
943 | mask = 0xffffffffffffffffull; | |
944 | } | |
945 | else | |
946 | { | |
947 | switch (S) | |
948 | { | |
949 | case 0x00 ... 0x1f: /* 0xxxxx */ simd_size = 32; break; | |
950 | case 0x20 ... 0x2f: /* 10xxxx */ simd_size = 16; S &= 0xf; break; | |
951 | case 0x30 ... 0x37: /* 110xxx */ simd_size = 8; S &= 0x7; break; | |
952 | case 0x38 ... 0x3b: /* 1110xx */ simd_size = 4; S &= 0x3; break; | |
953 | case 0x3c ... 0x3d: /* 11110x */ simd_size = 2; S &= 0x1; break; | |
561a72d4 | 954 | default: return FALSE; |
a06ea964 NC |
955 | } |
956 | mask = (1ull << simd_size) - 1; | |
957 | /* Top bits are IGNORED. */ | |
958 | R &= simd_size - 1; | |
959 | } | |
e950b345 RS |
960 | |
961 | if (simd_size > esize * 8) | |
561a72d4 | 962 | return FALSE; |
e950b345 | 963 | |
a06ea964 NC |
964 | /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */ |
965 | if (S == simd_size - 1) | |
561a72d4 | 966 | return FALSE; |
a06ea964 NC |
967 | /* S+1 consecutive bits to 1. */ |
968 | /* NOTE: S can't be 63 due to detection above. */ | |
969 | imm = (1ull << (S + 1)) - 1; | |
970 | /* Rotate to the left by simd_size - R. */ | |
971 | if (R != 0) | |
972 | imm = ((imm << (simd_size - R)) & mask) | (imm >> R); | |
973 | /* Replicate the value according to SIMD size. */ | |
974 | switch (simd_size) | |
975 | { | |
976 | case 2: imm = (imm << 2) | imm; | |
1a0670f3 | 977 | /* Fall through. */ |
a06ea964 | 978 | case 4: imm = (imm << 4) | imm; |
1a0670f3 | 979 | /* Fall through. */ |
a06ea964 | 980 | case 8: imm = (imm << 8) | imm; |
1a0670f3 | 981 | /* Fall through. */ |
a06ea964 | 982 | case 16: imm = (imm << 16) | imm; |
1a0670f3 | 983 | /* Fall through. */ |
a06ea964 | 984 | case 32: imm = (imm << 32) | imm; |
1a0670f3 | 985 | /* Fall through. */ |
a06ea964 NC |
986 | case 64: break; |
987 | default: assert (0); return 0; | |
988 | } | |
989 | ||
e950b345 RS |
990 | *result = imm & ~((uint64_t) -1 << (esize * 4) << (esize * 4)); |
991 | ||
561a72d4 | 992 | return TRUE; |
e950b345 RS |
993 | } |
994 | ||
995 | /* Decode a logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */ | |
561a72d4 | 996 | bfd_boolean |
e950b345 RS |
997 | aarch64_ext_limm (const aarch64_operand *self, |
998 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
999 | const aarch64_inst *inst, |
1000 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
e950b345 RS |
1001 | { |
1002 | uint32_t esize; | |
1003 | aarch64_insn value; | |
1004 | ||
1005 | value = extract_fields (code, 0, 3, self->fields[0], self->fields[1], | |
1006 | self->fields[2]); | |
1007 | esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier); | |
1008 | return decode_limm (esize, value, &info->imm.value); | |
1009 | } | |
a06ea964 | 1010 | |
e950b345 | 1011 | /* Decode a logical immediate for the BIC alias of AND (etc.). */ |
561a72d4 | 1012 | bfd_boolean |
e950b345 RS |
1013 | aarch64_ext_inv_limm (const aarch64_operand *self, |
1014 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
1015 | const aarch64_inst *inst, |
1016 | aarch64_operand_error *errors) | |
e950b345 | 1017 | { |
561a72d4 TC |
1018 | if (!aarch64_ext_limm (self, info, code, inst, errors)) |
1019 | return FALSE; | |
e950b345 | 1020 | info->imm.value = ~info->imm.value; |
561a72d4 | 1021 | return TRUE; |
a06ea964 NC |
1022 | } |
1023 | ||
08da6e93 SP |
1024 | /* Decode register using an additional field that specifies size. |
1025 | e.g. altbase instructions. */ | |
1026 | bfd_boolean | |
1027 | aarch64_ext_regsz (const aarch64_operand *self ATTRIBUTE_UNUSED, | |
1028 | aarch64_opnd_info *info, | |
1029 | const aarch64_insn code, | |
1030 | const aarch64_inst *inst ATTRIBUTE_UNUSED, | |
1031 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
1032 | { | |
1033 | ||
1034 | aarch64_insn value = extract_field (self->fields[1], code, 0); | |
1035 | info->reg.regno = extract_field (self->fields[0], code, 0); | |
1036 | info->qualifier = value == 1 ? AARCH64_OPND_QLF_X : AARCH64_OPND_QLF_W; | |
1037 | ||
1038 | return TRUE; | |
1039 | } | |
1040 | ||
ec87fc0f SP |
1041 | /* Decode SIMD register using an additional field that specifies size. |
1042 | e.g. altbase instructions. */ | |
1043 | bfd_boolean | |
1044 | aarch64_ext_fregsz (const aarch64_operand *self ATTRIBUTE_UNUSED, | |
1045 | aarch64_opnd_info *info, | |
1046 | const aarch64_insn code, | |
1047 | const aarch64_inst *inst ATTRIBUTE_UNUSED, | |
1048 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
1049 | { | |
1050 | ||
1051 | enum aarch64_opnd_qualifier qualifier; | |
1052 | aarch64_insn value = extract_field (self->fields[1], code, 0); | |
1053 | ||
1054 | info->reg.regno = extract_field (self->fields[0], code, 0); | |
1055 | ||
1056 | switch (value) | |
1057 | { | |
1058 | case 0: qualifier = AARCH64_OPND_QLF_S_B; break; | |
1059 | case 1: qualifier = AARCH64_OPND_QLF_S_H; break; | |
1060 | case 2: qualifier = AARCH64_OPND_QLF_S_S; break; | |
1061 | case 3: qualifier = AARCH64_OPND_QLF_S_D; break; | |
1062 | default: return FALSE; | |
1063 | } | |
1064 | info->qualifier = qualifier; | |
1065 | ||
1066 | return TRUE; | |
1067 | } | |
1068 | ||
a06ea964 NC |
1069 | /* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}] |
1070 | or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */ | |
561a72d4 | 1071 | bfd_boolean |
a06ea964 NC |
1072 | aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1073 | aarch64_opnd_info *info, | |
561a72d4 TC |
1074 | const aarch64_insn code, const aarch64_inst *inst, |
1075 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1076 | { |
1077 | aarch64_insn value; | |
1078 | ||
1079 | /* Rt */ | |
1080 | info->reg.regno = extract_field (FLD_Rt, code, 0); | |
1081 | ||
08da6e93 SP |
1082 | if (inst->opcode->iclass == ldst_altbase) |
1083 | { | |
1084 | enum aarch64_opnd_qualifier qualifier; | |
1085 | value = extract_field (FLD_altbase_sf, code, 0); | |
1086 | switch (value) | |
1087 | { | |
1088 | case 0: qualifier = AARCH64_OPND_QLF_S_D; break; | |
1089 | case 1: qualifier = AARCH64_OPND_QLF_S_S; break; | |
1090 | default: return FALSE; | |
1091 | } | |
1092 | info->qualifier = qualifier; | |
1093 | ||
1094 | return TRUE; | |
1095 | } | |
1096 | ||
a06ea964 NC |
1097 | /* size */ |
1098 | value = extract_field (FLD_ldst_size, code, 0); | |
1099 | if (inst->opcode->iclass == ldstpair_indexed | |
1100 | || inst->opcode->iclass == ldstnapair_offs | |
1101 | || inst->opcode->iclass == ldstpair_off | |
1102 | || inst->opcode->iclass == loadlit) | |
1103 | { | |
1104 | enum aarch64_opnd_qualifier qualifier; | |
1105 | switch (value) | |
1106 | { | |
1107 | case 0: qualifier = AARCH64_OPND_QLF_S_S; break; | |
1108 | case 1: qualifier = AARCH64_OPND_QLF_S_D; break; | |
1109 | case 2: qualifier = AARCH64_OPND_QLF_S_Q; break; | |
561a72d4 | 1110 | default: return FALSE; |
a06ea964 NC |
1111 | } |
1112 | info->qualifier = qualifier; | |
1113 | } | |
1114 | else | |
1115 | { | |
1116 | /* opc1:size */ | |
1117 | value = extract_fields (code, 0, 2, FLD_opc1, FLD_ldst_size); | |
1118 | if (value > 0x4) | |
561a72d4 | 1119 | return FALSE; |
a06ea964 NC |
1120 | info->qualifier = get_sreg_qualifier_from_value (value); |
1121 | } | |
1122 | ||
561a72d4 | 1123 | return TRUE; |
a06ea964 NC |
1124 | } |
1125 | ||
1126 | /* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */ | |
561a72d4 | 1127 | bfd_boolean |
a06ea964 NC |
1128 | aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1129 | aarch64_opnd_info *info, | |
1130 | aarch64_insn code, | |
561a72d4 TC |
1131 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1132 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 | 1133 | { |
f260da95 | 1134 | /* Rn/Can */ |
a06ea964 | 1135 | info->addr.base_regno = extract_field (FLD_Rn, code, 0); |
561a72d4 | 1136 | return TRUE; |
a06ea964 NC |
1137 | } |
1138 | ||
f42f1a1d TC |
1139 | /* Decode the address operand for e.g. |
1140 | stlur <Xt>, [<Xn|SP>{, <amount>}]. */ | |
561a72d4 | 1141 | bfd_boolean |
f42f1a1d TC |
1142 | aarch64_ext_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1143 | aarch64_opnd_info *info, | |
561a72d4 TC |
1144 | aarch64_insn code, const aarch64_inst *inst, |
1145 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
f42f1a1d TC |
1146 | { |
1147 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
1148 | ||
1149 | /* Rn */ | |
1150 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1151 | ||
1152 | /* simm9 */ | |
1153 | aarch64_insn imm = extract_fields (code, 0, 1, self->fields[1]); | |
1154 | info->addr.offset.imm = sign_extend (imm, 8); | |
1155 | if (extract_field (self->fields[2], code, 0) == 1) { | |
1156 | info->addr.writeback = 1; | |
1157 | info->addr.preind = 1; | |
1158 | } | |
561a72d4 | 1159 | return TRUE; |
f42f1a1d TC |
1160 | } |
1161 | ||
a06ea964 NC |
1162 | /* Decode the address operand for e.g. |
1163 | STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
561a72d4 | 1164 | bfd_boolean |
a06ea964 NC |
1165 | aarch64_ext_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1166 | aarch64_opnd_info *info, | |
561a72d4 TC |
1167 | aarch64_insn code, const aarch64_inst *inst, |
1168 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1169 | { |
1170 | aarch64_insn S, value; | |
1171 | ||
1172 | /* Rn */ | |
1173 | info->addr.base_regno = extract_field (FLD_Rn, code, 0); | |
1174 | /* Rm */ | |
1175 | info->addr.offset.regno = extract_field (FLD_Rm, code, 0); | |
1176 | /* option */ | |
1177 | value = extract_field (FLD_option, code, 0); | |
1178 | info->shifter.kind = | |
1179 | aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */); | |
1180 | /* Fix-up the shifter kind; although the table-driven approach is | |
1181 | efficient, it is slightly inflexible, thus needing this fix-up. */ | |
1182 | if (info->shifter.kind == AARCH64_MOD_UXTX) | |
1183 | info->shifter.kind = AARCH64_MOD_LSL; | |
1184 | /* S */ | |
1185 | S = extract_field (FLD_S, code, 0); | |
1186 | if (S == 0) | |
1187 | { | |
1188 | info->shifter.amount = 0; | |
1189 | info->shifter.amount_present = 0; | |
1190 | } | |
1191 | else | |
1192 | { | |
1193 | int size; | |
1194 | /* Need information in other operand(s) to help achieve the decoding | |
1195 | from 'S' field. */ | |
1196 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
1197 | /* Get the size of the data element that is accessed, which may be | |
1198 | different from that of the source register size, e.g. in strb/ldrb. */ | |
1199 | size = aarch64_get_qualifier_esize (info->qualifier); | |
1200 | info->shifter.amount = get_logsz (size); | |
1201 | info->shifter.amount_present = 1; | |
1202 | } | |
1203 | ||
561a72d4 | 1204 | return TRUE; |
a06ea964 NC |
1205 | } |
1206 | ||
1207 | /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>. */ | |
561a72d4 | 1208 | bfd_boolean |
a06ea964 | 1209 | aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info, |
561a72d4 TC |
1210 | aarch64_insn code, const aarch64_inst *inst, |
1211 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1212 | { |
1213 | aarch64_insn imm; | |
1214 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
1215 | ||
f260da95 | 1216 | /* Rn/Can */ |
a06ea964 NC |
1217 | info->addr.base_regno = extract_field (FLD_Rn, code, 0); |
1218 | /* simm (imm9 or imm7) */ | |
1219 | imm = extract_field (self->fields[0], code, 0); | |
1220 | info->addr.offset.imm = sign_extend (imm, fields[self->fields[0]].width - 1); | |
324988cf SP |
1221 | if (operand_need_shift_by_four (self)) |
1222 | info->addr.offset.imm <<= 4; | |
1223 | else if (self->fields[0] == FLD_imm7 | |
1224 | || info->qualifier == AARCH64_OPND_QLF_imm_tag) | |
a06ea964 NC |
1225 | /* scaled immediate in ld/st pair instructions. */ |
1226 | info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier); | |
1227 | /* qualifier */ | |
1228 | if (inst->opcode->iclass == ldst_unscaled | |
1229 | || inst->opcode->iclass == ldstnapair_offs | |
1230 | || inst->opcode->iclass == ldstpair_off | |
f260da95 | 1231 | || inst->opcode->iclass == ldst_unpriv |
ec87fc0f SP |
1232 | || inst->opcode->iclass == br_capaddr |
1233 | || inst->opcode->iclass == ldst_altbase) | |
a06ea964 NC |
1234 | info->addr.writeback = 0; |
1235 | else | |
1236 | { | |
1237 | /* pre/post- index */ | |
1238 | info->addr.writeback = 1; | |
1239 | if (extract_field (self->fields[1], code, 0) == 1) | |
1240 | info->addr.preind = 1; | |
1241 | else | |
1242 | info->addr.postind = 1; | |
1243 | } | |
1244 | ||
561a72d4 | 1245 | return TRUE; |
a06ea964 NC |
1246 | } |
1247 | ||
1248 | /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}]. */ | |
561a72d4 | 1249 | bfd_boolean |
08da6e93 SP |
1250 | aarch64_ext_addr_uimm (const aarch64_operand *self, aarch64_opnd_info *info, |
1251 | aarch64_insn code, | |
1252 | const aarch64_inst *inst ATTRIBUTE_UNUSED, | |
1253 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1254 | { |
1255 | int shift; | |
1256 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
1257 | shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier)); | |
1258 | /* Rn */ | |
1259 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1260 | /* uimm12 */ | |
1261 | info->addr.offset.imm = extract_field (self->fields[1], code, 0) << shift; | |
561a72d4 | 1262 | return TRUE; |
a06ea964 NC |
1263 | } |
1264 | ||
3f06e550 | 1265 | /* Decode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */ |
561a72d4 | 1266 | bfd_boolean |
3f06e550 SN |
1267 | aarch64_ext_addr_simm10 (const aarch64_operand *self, aarch64_opnd_info *info, |
1268 | aarch64_insn code, | |
561a72d4 TC |
1269 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1270 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
3f06e550 SN |
1271 | { |
1272 | aarch64_insn imm; | |
1273 | ||
1274 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
1275 | /* Rn */ | |
1276 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1277 | /* simm10 */ | |
1278 | imm = extract_fields (code, 0, 2, self->fields[1], self->fields[2]); | |
1279 | info->addr.offset.imm = sign_extend (imm, 9) << 3; | |
1280 | if (extract_field (self->fields[3], code, 0) == 1) { | |
1281 | info->addr.writeback = 1; | |
1282 | info->addr.preind = 1; | |
1283 | } | |
561a72d4 | 1284 | return TRUE; |
3f06e550 SN |
1285 | } |
1286 | ||
a06ea964 NC |
1287 | /* Decode the address operand for e.g. |
1288 | LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */ | |
561a72d4 | 1289 | bfd_boolean |
a06ea964 NC |
1290 | aarch64_ext_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1291 | aarch64_opnd_info *info, | |
561a72d4 TC |
1292 | aarch64_insn code, const aarch64_inst *inst, |
1293 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1294 | { |
1295 | /* The opcode dependent area stores the number of elements in | |
1296 | each structure to be loaded/stored. */ | |
1297 | int is_ld1r = get_opcode_dependent_value (inst->opcode) == 1; | |
1298 | ||
1299 | /* Rn */ | |
1300 | info->addr.base_regno = extract_field (FLD_Rn, code, 0); | |
1301 | /* Rm | #<amount> */ | |
1302 | info->addr.offset.regno = extract_field (FLD_Rm, code, 0); | |
1303 | if (info->addr.offset.regno == 31) | |
1304 | { | |
1305 | if (inst->opcode->operands[0] == AARCH64_OPND_LVt_AL) | |
1306 | /* Special handling of loading single structure to all lane. */ | |
1307 | info->addr.offset.imm = (is_ld1r ? 1 | |
1308 | : inst->operands[0].reglist.num_regs) | |
1309 | * aarch64_get_qualifier_esize (inst->operands[0].qualifier); | |
1310 | else | |
1311 | info->addr.offset.imm = inst->operands[0].reglist.num_regs | |
1312 | * aarch64_get_qualifier_esize (inst->operands[0].qualifier) | |
1313 | * aarch64_get_qualifier_nelem (inst->operands[0].qualifier); | |
1314 | } | |
1315 | else | |
1316 | info->addr.offset.is_reg = 1; | |
1317 | info->addr.writeback = 1; | |
1318 | ||
561a72d4 | 1319 | return TRUE; |
a06ea964 NC |
1320 | } |
1321 | ||
1322 | /* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */ | |
561a72d4 | 1323 | bfd_boolean |
a06ea964 NC |
1324 | aarch64_ext_cond (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1325 | aarch64_opnd_info *info, | |
561a72d4 TC |
1326 | aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1327 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1328 | { |
1329 | aarch64_insn value; | |
1330 | /* cond */ | |
1331 | value = extract_field (FLD_cond, code, 0); | |
1332 | info->cond = get_cond_from_value (value); | |
561a72d4 | 1333 | return TRUE; |
a06ea964 NC |
1334 | } |
1335 | ||
3e2ac3d2 SP |
1336 | /* Decode the permission operand for e.g. CLRPERM <Cd>, <Cn>, <perm>. */ |
1337 | bfd_boolean | |
1338 | aarch64_ext_perm (const aarch64_operand *self ATTRIBUTE_UNUSED, | |
1339 | aarch64_opnd_info *info, | |
1340 | aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, | |
1341 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
1342 | { | |
1343 | /* perm */ | |
1344 | info->perm = extract_field (FLD_perm, code, 0); | |
1345 | return TRUE; | |
1346 | } | |
1347 | ||
7ce74d61 SP |
1348 | /* Decode the form operand for e.g. SEAL <Cd>, <Cn>, <form>. */ |
1349 | bfd_boolean | |
1350 | aarch64_ext_form (const aarch64_operand *self ATTRIBUTE_UNUSED, | |
1351 | aarch64_opnd_info *info, | |
1352 | aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, | |
1353 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
1354 | { | |
1355 | aarch64_insn value; | |
1356 | /* form */ | |
1357 | value = extract_field (FLD_form, code, 0); | |
1358 | info->form = get_form_from_value (value); | |
1359 | return TRUE; | |
1360 | } | |
1361 | ||
a06ea964 | 1362 | /* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */ |
561a72d4 | 1363 | bfd_boolean |
a06ea964 NC |
1364 | aarch64_ext_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1365 | aarch64_opnd_info *info, | |
1366 | aarch64_insn code, | |
561a72d4 TC |
1367 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1368 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 | 1369 | { |
801f0a7d SP |
1370 | |
1371 | /* Value is : op0:op1:CRn:CRm:op2. In Morello we need to add the implicit | |
1372 | 0x2. XXX It should be the same for A64 too but there's some interaction | |
1373 | with sys/sysl that breaks this on A64. This should eventually be fixed to | |
1374 | harmonize the implementations. */ | |
1375 | aarch64_insn val; | |
1376 | ||
1377 | if (inst->opcode->iclass == a64c) | |
1378 | { | |
1379 | /* Leave space for the operands. */ | |
1380 | unsigned shift = 1U << (fields[FLD_a64c_op0].width | |
1381 | + fields[FLD_op1].width + fields[FLD_CRn].width | |
1382 | + fields[FLD_CRm].width + fields[FLD_op2].width); | |
1383 | ||
1384 | val = shift | extract_fields (code, 0, 5, FLD_a64c_op0, FLD_op1, FLD_CRn, | |
1385 | FLD_CRm, FLD_op2); | |
1386 | } | |
1387 | else | |
1388 | val = extract_fields (code, 0, 5, FLD_op0, FLD_op1, FLD_CRn, FLD_CRm, FLD_op2); | |
1389 | ||
1390 | info->sysreg.value = val; | |
1391 | ||
f9830ec1 TC |
1392 | info->sysreg.flags = 0; |
1393 | ||
1394 | /* If a system instruction, check which restrictions should be on the register | |
1395 | value during decoding, these will be enforced then. */ | |
801f0a7d SP |
1396 | if (inst->opcode->iclass == ic_system |
1397 | || inst->opcode->iclass == a64c) | |
f9830ec1 TC |
1398 | { |
1399 | /* Check to see if it's read-only, else check if it's write only. | |
1400 | if it's both or unspecified don't care. */ | |
1401 | if ((inst->opcode->flags & (F_SYS_READ | F_SYS_WRITE)) == F_SYS_READ) | |
1402 | info->sysreg.flags = F_REG_READ; | |
1403 | else if ((inst->opcode->flags & (F_SYS_READ | F_SYS_WRITE)) | |
1404 | == F_SYS_WRITE) | |
1405 | info->sysreg.flags = F_REG_WRITE; | |
1406 | } | |
1407 | ||
1408 | return TRUE; | |
a06ea964 NC |
1409 | } |
1410 | ||
1411 | /* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */ | |
561a72d4 | 1412 | bfd_boolean |
a06ea964 NC |
1413 | aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1414 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1415 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1416 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1417 | { |
1418 | int i; | |
1419 | /* op1:op2 */ | |
1420 | info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2); | |
1421 | for (i = 0; aarch64_pstatefields[i].name != NULL; ++i) | |
1422 | if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield) | |
561a72d4 | 1423 | return TRUE; |
a06ea964 | 1424 | /* Reserved value in <pstatefield>. */ |
561a72d4 | 1425 | return FALSE; |
a06ea964 NC |
1426 | } |
1427 | ||
1428 | /* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>. */ | |
561a72d4 | 1429 | bfd_boolean |
a06ea964 NC |
1430 | aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1431 | aarch64_opnd_info *info, | |
1432 | aarch64_insn code, | |
561a72d4 TC |
1433 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1434 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1435 | { |
1436 | int i; | |
1437 | aarch64_insn value; | |
1438 | const aarch64_sys_ins_reg *sysins_ops; | |
1439 | /* op0:op1:CRn:CRm:op2 */ | |
1440 | value = extract_fields (code, 0, 5, | |
1441 | FLD_op0, FLD_op1, FLD_CRn, | |
1442 | FLD_CRm, FLD_op2); | |
1443 | ||
1444 | switch (info->type) | |
1445 | { | |
1446 | case AARCH64_OPND_SYSREG_AT: sysins_ops = aarch64_sys_regs_at; break; | |
1447 | case AARCH64_OPND_SYSREG_DC: sysins_ops = aarch64_sys_regs_dc; break; | |
1448 | case AARCH64_OPND_SYSREG_IC: sysins_ops = aarch64_sys_regs_ic; break; | |
1449 | case AARCH64_OPND_SYSREG_TLBI: sysins_ops = aarch64_sys_regs_tlbi; break; | |
2ac435d4 SD |
1450 | case AARCH64_OPND_SYSREG_SR: |
1451 | sysins_ops = aarch64_sys_regs_sr; | |
1452 | /* Let's remove op2 for rctx. Refer to comments in the definition of | |
1453 | aarch64_sys_regs_sr[]. */ | |
1454 | value = value & ~(0x7); | |
1455 | break; | |
561a72d4 | 1456 | default: assert (0); return FALSE; |
a06ea964 NC |
1457 | } |
1458 | ||
875880c6 | 1459 | for (i = 0; sysins_ops[i].name != NULL; ++i) |
a06ea964 NC |
1460 | if (sysins_ops[i].value == value) |
1461 | { | |
1462 | info->sysins_op = sysins_ops + i; | |
1463 | DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.", | |
875880c6 | 1464 | info->sysins_op->name, |
a06ea964 | 1465 | (unsigned)info->sysins_op->value, |
ea2deeec | 1466 | aarch64_sys_ins_reg_has_xt (info->sysins_op), i); |
561a72d4 | 1467 | return TRUE; |
a06ea964 NC |
1468 | } |
1469 | ||
561a72d4 | 1470 | return FALSE; |
a06ea964 NC |
1471 | } |
1472 | ||
1473 | /* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>. */ | |
1474 | ||
561a72d4 | 1475 | bfd_boolean |
a06ea964 NC |
1476 | aarch64_ext_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1477 | aarch64_opnd_info *info, | |
1478 | aarch64_insn code, | |
561a72d4 TC |
1479 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1480 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1481 | { |
1482 | /* CRm */ | |
1483 | info->barrier = aarch64_barrier_options + extract_field (FLD_CRm, code, 0); | |
561a72d4 | 1484 | return TRUE; |
a06ea964 NC |
1485 | } |
1486 | ||
1487 | /* Decode the prefetch operation option operand for e.g. | |
1488 | PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */ | |
1489 | ||
561a72d4 | 1490 | bfd_boolean |
a06ea964 NC |
1491 | aarch64_ext_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1492 | aarch64_opnd_info *info, | |
561a72d4 TC |
1493 | aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1494 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1495 | { |
1496 | /* prfop in Rt */ | |
1497 | info->prfop = aarch64_prfops + extract_field (FLD_Rt, code, 0); | |
561a72d4 | 1498 | return TRUE; |
a06ea964 NC |
1499 | } |
1500 | ||
9ed608f9 MW |
1501 | /* Decode the hint number for an alias taking an operand. Set info->hint_option |
1502 | to the matching name/value pair in aarch64_hint_options. */ | |
1503 | ||
561a72d4 | 1504 | bfd_boolean |
9ed608f9 MW |
1505 | aarch64_ext_hint (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1506 | aarch64_opnd_info *info, | |
1507 | aarch64_insn code, | |
561a72d4 TC |
1508 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1509 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
9ed608f9 MW |
1510 | { |
1511 | /* CRm:op2. */ | |
1512 | unsigned hint_number; | |
1513 | int i; | |
1514 | ||
1515 | hint_number = extract_fields (code, 0, 2, FLD_CRm, FLD_op2); | |
1516 | ||
1517 | for (i = 0; aarch64_hint_options[i].name != NULL; i++) | |
1518 | { | |
ff605452 | 1519 | if (hint_number == HINT_VAL (aarch64_hint_options[i].value)) |
9ed608f9 MW |
1520 | { |
1521 | info->hint_option = &(aarch64_hint_options[i]); | |
561a72d4 | 1522 | return TRUE; |
9ed608f9 MW |
1523 | } |
1524 | } | |
1525 | ||
561a72d4 | 1526 | return FALSE; |
9ed608f9 MW |
1527 | } |
1528 | ||
a06ea964 NC |
1529 | /* Decode the extended register operand for e.g. |
1530 | STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
561a72d4 | 1531 | bfd_boolean |
a06ea964 NC |
1532 | aarch64_ext_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1533 | aarch64_opnd_info *info, | |
1534 | aarch64_insn code, | |
561a72d4 TC |
1535 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1536 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1537 | { |
1538 | aarch64_insn value; | |
1539 | ||
1540 | /* Rm */ | |
1541 | info->reg.regno = extract_field (FLD_Rm, code, 0); | |
1542 | /* option */ | |
1543 | value = extract_field (FLD_option, code, 0); | |
1544 | info->shifter.kind = | |
1545 | aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */); | |
1546 | /* imm3 */ | |
1547 | info->shifter.amount = extract_field (FLD_imm3, code, 0); | |
1548 | ||
1549 | /* This makes the constraint checking happy. */ | |
1550 | info->shifter.operator_present = 1; | |
1551 | ||
1552 | /* Assume inst->operands[0].qualifier has been resolved. */ | |
1553 | assert (inst->operands[0].qualifier != AARCH64_OPND_QLF_NIL); | |
1554 | info->qualifier = AARCH64_OPND_QLF_W; | |
dc64c2ba SP |
1555 | if ((inst->operands[0].qualifier == AARCH64_OPND_QLF_CA |
1556 | || inst->operands[0].qualifier == AARCH64_OPND_QLF_X) | |
a06ea964 NC |
1557 | && (info->shifter.kind == AARCH64_MOD_UXTX |
1558 | || info->shifter.kind == AARCH64_MOD_SXTX)) | |
1559 | info->qualifier = AARCH64_OPND_QLF_X; | |
1560 | ||
561a72d4 | 1561 | return TRUE; |
a06ea964 NC |
1562 | } |
1563 | ||
1564 | /* Decode the shifted register operand for e.g. | |
1565 | SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */ | |
561a72d4 | 1566 | bfd_boolean |
a06ea964 NC |
1567 | aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1568 | aarch64_opnd_info *info, | |
1569 | aarch64_insn code, | |
561a72d4 TC |
1570 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1571 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1572 | { |
1573 | aarch64_insn value; | |
1574 | ||
1575 | /* Rm */ | |
1576 | info->reg.regno = extract_field (FLD_Rm, code, 0); | |
1577 | /* shift */ | |
1578 | value = extract_field (FLD_shift, code, 0); | |
1579 | info->shifter.kind = | |
1580 | aarch64_get_operand_modifier_from_value (value, FALSE /* extend_p */); | |
1581 | if (info->shifter.kind == AARCH64_MOD_ROR | |
1582 | && inst->opcode->iclass != log_shift) | |
1583 | /* ROR is not available for the shifted register operand in arithmetic | |
1584 | instructions. */ | |
561a72d4 | 1585 | return FALSE; |
a06ea964 NC |
1586 | /* imm6 */ |
1587 | info->shifter.amount = extract_field (FLD_imm6, code, 0); | |
1588 | ||
1589 | /* This makes the constraint checking happy. */ | |
1590 | info->shifter.operator_present = 1; | |
1591 | ||
561a72d4 | 1592 | return TRUE; |
a06ea964 | 1593 | } |
f11ad6bc | 1594 | |
98907a70 RS |
1595 | /* Decode an SVE address [<base>, #<offset>*<factor>, MUL VL], |
1596 | where <offset> is given by the OFFSET parameter and where <factor> is | |
1597 | 1 plus SELF's operand-dependent value. fields[0] specifies the field | |
1598 | that holds <base>. */ | |
561a72d4 | 1599 | static bfd_boolean |
98907a70 RS |
1600 | aarch64_ext_sve_addr_reg_mul_vl (const aarch64_operand *self, |
1601 | aarch64_opnd_info *info, aarch64_insn code, | |
1602 | int64_t offset) | |
1603 | { | |
1604 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1605 | info->addr.offset.imm = offset * (1 + get_operand_specific_data (self)); | |
1606 | info->addr.offset.is_reg = FALSE; | |
1607 | info->addr.writeback = FALSE; | |
1608 | info->addr.preind = TRUE; | |
1609 | if (offset != 0) | |
1610 | info->shifter.kind = AARCH64_MOD_MUL_VL; | |
1611 | info->shifter.amount = 1; | |
1612 | info->shifter.operator_present = (info->addr.offset.imm != 0); | |
1613 | info->shifter.amount_present = FALSE; | |
561a72d4 | 1614 | return TRUE; |
98907a70 RS |
1615 | } |
1616 | ||
1617 | /* Decode an SVE address [<base>, #<simm4>*<factor>, MUL VL], | |
1618 | where <simm4> is a 4-bit signed value and where <factor> is 1 plus | |
1619 | SELF's operand-dependent value. fields[0] specifies the field that | |
1620 | holds <base>. <simm4> is encoded in the SVE_imm4 field. */ | |
561a72d4 | 1621 | bfd_boolean |
98907a70 RS |
1622 | aarch64_ext_sve_addr_ri_s4xvl (const aarch64_operand *self, |
1623 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1624 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1625 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
98907a70 RS |
1626 | { |
1627 | int offset; | |
1628 | ||
1629 | offset = extract_field (FLD_SVE_imm4, code, 0); | |
1630 | offset = ((offset + 8) & 15) - 8; | |
1631 | return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset); | |
1632 | } | |
1633 | ||
1634 | /* Decode an SVE address [<base>, #<simm6>*<factor>, MUL VL], | |
1635 | where <simm6> is a 6-bit signed value and where <factor> is 1 plus | |
1636 | SELF's operand-dependent value. fields[0] specifies the field that | |
1637 | holds <base>. <simm6> is encoded in the SVE_imm6 field. */ | |
561a72d4 | 1638 | bfd_boolean |
98907a70 RS |
1639 | aarch64_ext_sve_addr_ri_s6xvl (const aarch64_operand *self, |
1640 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1641 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1642 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
98907a70 RS |
1643 | { |
1644 | int offset; | |
1645 | ||
1646 | offset = extract_field (FLD_SVE_imm6, code, 0); | |
1647 | offset = (((offset + 32) & 63) - 32); | |
1648 | return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset); | |
1649 | } | |
1650 | ||
1651 | /* Decode an SVE address [<base>, #<simm9>*<factor>, MUL VL], | |
1652 | where <simm9> is a 9-bit signed value and where <factor> is 1 plus | |
1653 | SELF's operand-dependent value. fields[0] specifies the field that | |
1654 | holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6 | |
1655 | and imm3 fields, with imm3 being the less-significant part. */ | |
561a72d4 | 1656 | bfd_boolean |
98907a70 RS |
1657 | aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand *self, |
1658 | aarch64_opnd_info *info, | |
1659 | aarch64_insn code, | |
561a72d4 TC |
1660 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1661 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
98907a70 RS |
1662 | { |
1663 | int offset; | |
1664 | ||
1665 | offset = extract_fields (code, 0, 2, FLD_SVE_imm6, FLD_imm3); | |
1666 | offset = (((offset + 256) & 511) - 256); | |
1667 | return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset); | |
1668 | } | |
1669 | ||
4df068de RS |
1670 | /* Decode an SVE address [<base>, #<offset> << <shift>], where <offset> |
1671 | is given by the OFFSET parameter and where <shift> is SELF's operand- | |
1672 | dependent value. fields[0] specifies the base register field <base>. */ | |
561a72d4 | 1673 | static bfd_boolean |
4df068de RS |
1674 | aarch64_ext_sve_addr_reg_imm (const aarch64_operand *self, |
1675 | aarch64_opnd_info *info, aarch64_insn code, | |
1676 | int64_t offset) | |
1677 | { | |
1678 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1679 | info->addr.offset.imm = offset * (1 << get_operand_specific_data (self)); | |
1680 | info->addr.offset.is_reg = FALSE; | |
1681 | info->addr.writeback = FALSE; | |
1682 | info->addr.preind = TRUE; | |
1683 | info->shifter.operator_present = FALSE; | |
1684 | info->shifter.amount_present = FALSE; | |
561a72d4 | 1685 | return TRUE; |
4df068de RS |
1686 | } |
1687 | ||
582e12bf RS |
1688 | /* Decode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4> |
1689 | is a 4-bit signed number and where <shift> is SELF's operand-dependent | |
1690 | value. fields[0] specifies the base register field. */ | |
561a72d4 | 1691 | bfd_boolean |
582e12bf RS |
1692 | aarch64_ext_sve_addr_ri_s4 (const aarch64_operand *self, |
1693 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1694 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1695 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
582e12bf RS |
1696 | { |
1697 | int offset = sign_extend (extract_field (FLD_SVE_imm4, code, 0), 3); | |
1698 | return aarch64_ext_sve_addr_reg_imm (self, info, code, offset); | |
1699 | } | |
1700 | ||
4df068de RS |
1701 | /* Decode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6> |
1702 | is a 6-bit unsigned number and where <shift> is SELF's operand-dependent | |
1703 | value. fields[0] specifies the base register field. */ | |
561a72d4 | 1704 | bfd_boolean |
4df068de RS |
1705 | aarch64_ext_sve_addr_ri_u6 (const aarch64_operand *self, |
1706 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1707 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1708 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de RS |
1709 | { |
1710 | int offset = extract_field (FLD_SVE_imm6, code, 0); | |
1711 | return aarch64_ext_sve_addr_reg_imm (self, info, code, offset); | |
1712 | } | |
1713 | ||
1714 | /* Decode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift> | |
1715 | is SELF's operand-dependent value. fields[0] specifies the base | |
1716 | register field and fields[1] specifies the offset register field. */ | |
561a72d4 | 1717 | bfd_boolean |
4df068de RS |
1718 | aarch64_ext_sve_addr_rr_lsl (const aarch64_operand *self, |
1719 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1720 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1721 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de | 1722 | { |
eaf02703 | 1723 | int index_regno; |
4df068de | 1724 | |
eaf02703 MR |
1725 | index_regno = extract_field (self->fields[1], code, 0); |
1726 | if (index_regno == 31 && (self->flags & OPD_F_NO_ZR) != 0) | |
561a72d4 | 1727 | return FALSE; |
4df068de RS |
1728 | |
1729 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
eaf02703 | 1730 | info->addr.offset.regno = index_regno; |
4df068de RS |
1731 | info->addr.offset.is_reg = TRUE; |
1732 | info->addr.writeback = FALSE; | |
1733 | info->addr.preind = TRUE; | |
1734 | info->shifter.kind = AARCH64_MOD_LSL; | |
1735 | info->shifter.amount = get_operand_specific_data (self); | |
1736 | info->shifter.operator_present = (info->shifter.amount != 0); | |
1737 | info->shifter.amount_present = (info->shifter.amount != 0); | |
561a72d4 | 1738 | return TRUE; |
4df068de RS |
1739 | } |
1740 | ||
1741 | /* Decode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where | |
1742 | <shift> is SELF's operand-dependent value. fields[0] specifies the | |
1743 | base register field, fields[1] specifies the offset register field and | |
1744 | fields[2] is a single-bit field that selects SXTW over UXTW. */ | |
561a72d4 | 1745 | bfd_boolean |
4df068de RS |
1746 | aarch64_ext_sve_addr_rz_xtw (const aarch64_operand *self, |
1747 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1748 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1749 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de RS |
1750 | { |
1751 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1752 | info->addr.offset.regno = extract_field (self->fields[1], code, 0); | |
1753 | info->addr.offset.is_reg = TRUE; | |
1754 | info->addr.writeback = FALSE; | |
1755 | info->addr.preind = TRUE; | |
1756 | if (extract_field (self->fields[2], code, 0)) | |
1757 | info->shifter.kind = AARCH64_MOD_SXTW; | |
1758 | else | |
1759 | info->shifter.kind = AARCH64_MOD_UXTW; | |
1760 | info->shifter.amount = get_operand_specific_data (self); | |
1761 | info->shifter.operator_present = TRUE; | |
1762 | info->shifter.amount_present = (info->shifter.amount != 0); | |
561a72d4 | 1763 | return TRUE; |
4df068de RS |
1764 | } |
1765 | ||
1766 | /* Decode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a | |
1767 | 5-bit unsigned number and where <shift> is SELF's operand-dependent value. | |
1768 | fields[0] specifies the base register field. */ | |
561a72d4 | 1769 | bfd_boolean |
4df068de RS |
1770 | aarch64_ext_sve_addr_zi_u5 (const aarch64_operand *self, |
1771 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1772 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1773 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de RS |
1774 | { |
1775 | int offset = extract_field (FLD_imm5, code, 0); | |
1776 | return aarch64_ext_sve_addr_reg_imm (self, info, code, offset); | |
1777 | } | |
1778 | ||
1779 | /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}], | |
1780 | where <modifier> is given by KIND and where <msz> is a 2-bit unsigned | |
1781 | number. fields[0] specifies the base register field and fields[1] | |
1782 | specifies the offset register field. */ | |
561a72d4 | 1783 | static bfd_boolean |
4df068de RS |
1784 | aarch64_ext_sve_addr_zz (const aarch64_operand *self, aarch64_opnd_info *info, |
1785 | aarch64_insn code, enum aarch64_modifier_kind kind) | |
1786 | { | |
1787 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1788 | info->addr.offset.regno = extract_field (self->fields[1], code, 0); | |
1789 | info->addr.offset.is_reg = TRUE; | |
1790 | info->addr.writeback = FALSE; | |
1791 | info->addr.preind = TRUE; | |
1792 | info->shifter.kind = kind; | |
1793 | info->shifter.amount = extract_field (FLD_SVE_msz, code, 0); | |
1794 | info->shifter.operator_present = (kind != AARCH64_MOD_LSL | |
1795 | || info->shifter.amount != 0); | |
1796 | info->shifter.amount_present = (info->shifter.amount != 0); | |
561a72d4 | 1797 | return TRUE; |
4df068de RS |
1798 | } |
1799 | ||
1800 | /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where | |
1801 | <msz> is a 2-bit unsigned number. fields[0] specifies the base register | |
1802 | field and fields[1] specifies the offset register field. */ | |
561a72d4 | 1803 | bfd_boolean |
4df068de RS |
1804 | aarch64_ext_sve_addr_zz_lsl (const aarch64_operand *self, |
1805 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1806 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1807 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de RS |
1808 | { |
1809 | return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_LSL); | |
1810 | } | |
1811 | ||
1812 | /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where | |
1813 | <msz> is a 2-bit unsigned number. fields[0] specifies the base register | |
1814 | field and fields[1] specifies the offset register field. */ | |
561a72d4 | 1815 | bfd_boolean |
4df068de RS |
1816 | aarch64_ext_sve_addr_zz_sxtw (const aarch64_operand *self, |
1817 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1818 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1819 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de RS |
1820 | { |
1821 | return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_SXTW); | |
1822 | } | |
1823 | ||
1824 | /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where | |
1825 | <msz> is a 2-bit unsigned number. fields[0] specifies the base register | |
1826 | field and fields[1] specifies the offset register field. */ | |
561a72d4 | 1827 | bfd_boolean |
4df068de RS |
1828 | aarch64_ext_sve_addr_zz_uxtw (const aarch64_operand *self, |
1829 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1830 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1831 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de RS |
1832 | { |
1833 | return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_UXTW); | |
1834 | } | |
1835 | ||
e950b345 RS |
1836 | /* Finish decoding an SVE arithmetic immediate, given that INFO already |
1837 | has the raw field value and that the low 8 bits decode to VALUE. */ | |
561a72d4 | 1838 | static bfd_boolean |
e950b345 RS |
1839 | decode_sve_aimm (aarch64_opnd_info *info, int64_t value) |
1840 | { | |
1841 | info->shifter.kind = AARCH64_MOD_LSL; | |
1842 | info->shifter.amount = 0; | |
1843 | if (info->imm.value & 0x100) | |
1844 | { | |
1845 | if (value == 0) | |
1846 | /* Decode 0x100 as #0, LSL #8. */ | |
1847 | info->shifter.amount = 8; | |
1848 | else | |
1849 | value *= 256; | |
1850 | } | |
1851 | info->shifter.operator_present = (info->shifter.amount != 0); | |
1852 | info->shifter.amount_present = (info->shifter.amount != 0); | |
1853 | info->imm.value = value; | |
561a72d4 | 1854 | return TRUE; |
e950b345 RS |
1855 | } |
1856 | ||
1857 | /* Decode an SVE ADD/SUB immediate. */ | |
561a72d4 | 1858 | bfd_boolean |
e950b345 RS |
1859 | aarch64_ext_sve_aimm (const aarch64_operand *self, |
1860 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
1861 | const aarch64_inst *inst, |
1862 | aarch64_operand_error *errors) | |
e950b345 | 1863 | { |
561a72d4 | 1864 | return (aarch64_ext_imm (self, info, code, inst, errors) |
e950b345 RS |
1865 | && decode_sve_aimm (info, (uint8_t) info->imm.value)); |
1866 | } | |
1867 | ||
1868 | /* Decode an SVE CPY/DUP immediate. */ | |
561a72d4 | 1869 | bfd_boolean |
e950b345 RS |
1870 | aarch64_ext_sve_asimm (const aarch64_operand *self, |
1871 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
1872 | const aarch64_inst *inst, |
1873 | aarch64_operand_error *errors) | |
e950b345 | 1874 | { |
561a72d4 | 1875 | return (aarch64_ext_imm (self, info, code, inst, errors) |
e950b345 RS |
1876 | && decode_sve_aimm (info, (int8_t) info->imm.value)); |
1877 | } | |
1878 | ||
165d4950 RS |
1879 | /* Decode a single-bit immediate that selects between #0.5 and #1.0. |
1880 | The fields array specifies which field to use. */ | |
561a72d4 | 1881 | bfd_boolean |
165d4950 RS |
1882 | aarch64_ext_sve_float_half_one (const aarch64_operand *self, |
1883 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1884 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1885 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
165d4950 RS |
1886 | { |
1887 | if (extract_field (self->fields[0], code, 0)) | |
1888 | info->imm.value = 0x3f800000; | |
1889 | else | |
1890 | info->imm.value = 0x3f000000; | |
1891 | info->imm.is_fp = TRUE; | |
561a72d4 | 1892 | return TRUE; |
165d4950 RS |
1893 | } |
1894 | ||
1895 | /* Decode a single-bit immediate that selects between #0.5 and #2.0. | |
1896 | The fields array specifies which field to use. */ | |
561a72d4 | 1897 | bfd_boolean |
165d4950 RS |
1898 | aarch64_ext_sve_float_half_two (const aarch64_operand *self, |
1899 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1900 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1901 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
165d4950 RS |
1902 | { |
1903 | if (extract_field (self->fields[0], code, 0)) | |
1904 | info->imm.value = 0x40000000; | |
1905 | else | |
1906 | info->imm.value = 0x3f000000; | |
1907 | info->imm.is_fp = TRUE; | |
561a72d4 | 1908 | return TRUE; |
165d4950 RS |
1909 | } |
1910 | ||
1911 | /* Decode a single-bit immediate that selects between #0.0 and #1.0. | |
1912 | The fields array specifies which field to use. */ | |
561a72d4 | 1913 | bfd_boolean |
165d4950 RS |
1914 | aarch64_ext_sve_float_zero_one (const aarch64_operand *self, |
1915 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1916 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1917 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
165d4950 RS |
1918 | { |
1919 | if (extract_field (self->fields[0], code, 0)) | |
1920 | info->imm.value = 0x3f800000; | |
1921 | else | |
1922 | info->imm.value = 0x0; | |
1923 | info->imm.is_fp = TRUE; | |
561a72d4 | 1924 | return TRUE; |
165d4950 RS |
1925 | } |
1926 | ||
f11ad6bc RS |
1927 | /* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields |
1928 | array specifies which field to use for Zn. MM is encoded in the | |
1929 | concatenation of imm5 and SVE_tszh, with imm5 being the less | |
1930 | significant part. */ | |
561a72d4 | 1931 | bfd_boolean |
f11ad6bc RS |
1932 | aarch64_ext_sve_index (const aarch64_operand *self, |
1933 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1934 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1935 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
f11ad6bc RS |
1936 | { |
1937 | int val; | |
1938 | ||
1939 | info->reglane.regno = extract_field (self->fields[0], code, 0); | |
1940 | val = extract_fields (code, 0, 2, FLD_SVE_tszh, FLD_imm5); | |
582e12bf | 1941 | if ((val & 31) == 0) |
f11ad6bc RS |
1942 | return 0; |
1943 | while ((val & 1) == 0) | |
1944 | val /= 2; | |
1945 | info->reglane.index = val / 2; | |
561a72d4 | 1946 | return TRUE; |
f11ad6bc RS |
1947 | } |
1948 | ||
e950b345 | 1949 | /* Decode a logical immediate for the MOV alias of SVE DUPM. */ |
561a72d4 | 1950 | bfd_boolean |
e950b345 RS |
1951 | aarch64_ext_sve_limm_mov (const aarch64_operand *self, |
1952 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
1953 | const aarch64_inst *inst, |
1954 | aarch64_operand_error *errors) | |
e950b345 RS |
1955 | { |
1956 | int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier); | |
561a72d4 | 1957 | return (aarch64_ext_limm (self, info, code, inst, errors) |
e950b345 RS |
1958 | && aarch64_sve_dupm_mov_immediate_p (info->imm.value, esize)); |
1959 | } | |
1960 | ||
582e12bf RS |
1961 | /* Decode Zn[MM], where Zn occupies the least-significant part of the field |
1962 | and where MM occupies the most-significant part. The operand-dependent | |
1963 | value specifies the number of bits in Zn. */ | |
561a72d4 | 1964 | bfd_boolean |
582e12bf RS |
1965 | aarch64_ext_sve_quad_index (const aarch64_operand *self, |
1966 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1967 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1968 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
582e12bf RS |
1969 | { |
1970 | unsigned int reg_bits = get_operand_specific_data (self); | |
1971 | unsigned int val = extract_all_fields (self, code); | |
1972 | info->reglane.regno = val & ((1 << reg_bits) - 1); | |
1973 | info->reglane.index = val >> reg_bits; | |
561a72d4 | 1974 | return TRUE; |
582e12bf RS |
1975 | } |
1976 | ||
f11ad6bc RS |
1977 | /* Decode {Zn.<T> - Zm.<T>}. The fields array specifies which field |
1978 | to use for Zn. The opcode-dependent value specifies the number | |
1979 | of registers in the list. */ | |
561a72d4 | 1980 | bfd_boolean |
f11ad6bc RS |
1981 | aarch64_ext_sve_reglist (const aarch64_operand *self, |
1982 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1983 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1984 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
f11ad6bc RS |
1985 | { |
1986 | info->reglist.first_regno = extract_field (self->fields[0], code, 0); | |
1987 | info->reglist.num_regs = get_opcode_dependent_value (inst->opcode); | |
561a72d4 | 1988 | return TRUE; |
f11ad6bc | 1989 | } |
2442d846 RS |
1990 | |
1991 | /* Decode <pattern>{, MUL #<amount>}. The fields array specifies which | |
1992 | fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4 | |
1993 | field. */ | |
561a72d4 | 1994 | bfd_boolean |
2442d846 RS |
1995 | aarch64_ext_sve_scale (const aarch64_operand *self, |
1996 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 | 1997 | const aarch64_inst *inst, aarch64_operand_error *errors) |
2442d846 RS |
1998 | { |
1999 | int val; | |
2000 | ||
561a72d4 TC |
2001 | if (!aarch64_ext_imm (self, info, code, inst, errors)) |
2002 | return FALSE; | |
2442d846 RS |
2003 | val = extract_field (FLD_SVE_imm4, code, 0); |
2004 | info->shifter.kind = AARCH64_MOD_MUL; | |
2005 | info->shifter.amount = val + 1; | |
2006 | info->shifter.operator_present = (val != 0); | |
2007 | info->shifter.amount_present = (val != 0); | |
561a72d4 | 2008 | return TRUE; |
2442d846 | 2009 | } |
e950b345 RS |
2010 | |
2011 | /* Return the top set bit in VALUE, which is expected to be relatively | |
2012 | small. */ | |
2013 | static uint64_t | |
2014 | get_top_bit (uint64_t value) | |
2015 | { | |
2016 | while ((value & -value) != value) | |
2017 | value -= value & -value; | |
2018 | return value; | |
2019 | } | |
2020 | ||
2021 | /* Decode an SVE shift-left immediate. */ | |
561a72d4 | 2022 | bfd_boolean |
e950b345 RS |
2023 | aarch64_ext_sve_shlimm (const aarch64_operand *self, |
2024 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 | 2025 | const aarch64_inst *inst, aarch64_operand_error *errors) |
e950b345 | 2026 | { |
561a72d4 | 2027 | if (!aarch64_ext_imm (self, info, code, inst, errors) |
e950b345 | 2028 | || info->imm.value == 0) |
561a72d4 | 2029 | return FALSE; |
e950b345 RS |
2030 | |
2031 | info->imm.value -= get_top_bit (info->imm.value); | |
561a72d4 | 2032 | return TRUE; |
e950b345 RS |
2033 | } |
2034 | ||
2035 | /* Decode an SVE shift-right immediate. */ | |
561a72d4 | 2036 | bfd_boolean |
e950b345 RS |
2037 | aarch64_ext_sve_shrimm (const aarch64_operand *self, |
2038 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 | 2039 | const aarch64_inst *inst, aarch64_operand_error *errors) |
e950b345 | 2040 | { |
561a72d4 | 2041 | if (!aarch64_ext_imm (self, info, code, inst, errors) |
e950b345 | 2042 | || info->imm.value == 0) |
561a72d4 | 2043 | return FALSE; |
e950b345 RS |
2044 | |
2045 | info->imm.value = get_top_bit (info->imm.value) * 2 - info->imm.value; | |
561a72d4 | 2046 | return TRUE; |
e950b345 | 2047 | } |
a06ea964 NC |
2048 | \f |
2049 | /* Bitfields that are commonly used to encode certain operands' information | |
2050 | may be partially used as part of the base opcode in some instructions. | |
2051 | For example, the bit 1 of the field 'size' in | |
2052 | FCVTXN <Vb><d>, <Va><n> | |
2053 | is actually part of the base opcode, while only size<0> is available | |
2054 | for encoding the register type. Another example is the AdvSIMD | |
2055 | instruction ORR (register), in which the field 'size' is also used for | |
2056 | the base opcode, leaving only the field 'Q' available to encode the | |
2057 | vector register arrangement specifier '8B' or '16B'. | |
2058 | ||
2059 | This function tries to deduce the qualifier from the value of partially | |
2060 | constrained field(s). Given the VALUE of such a field or fields, the | |
2061 | qualifiers CANDIDATES and the MASK (indicating which bits are valid for | |
2062 | operand encoding), the function returns the matching qualifier or | |
2063 | AARCH64_OPND_QLF_NIL if nothing matches. | |
2064 | ||
2065 | N.B. CANDIDATES is a group of possible qualifiers that are valid for | |
2066 | one operand; it has a maximum of AARCH64_MAX_QLF_SEQ_NUM qualifiers and | |
2067 | may end with AARCH64_OPND_QLF_NIL. */ | |
2068 | ||
2069 | static enum aarch64_opnd_qualifier | |
2070 | get_qualifier_from_partial_encoding (aarch64_insn value, | |
2071 | const enum aarch64_opnd_qualifier* \ | |
2072 | candidates, | |
2073 | aarch64_insn mask) | |
2074 | { | |
2075 | int i; | |
2076 | DEBUG_TRACE ("enter with value: %d, mask: %d", (int)value, (int)mask); | |
2077 | for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i) | |
2078 | { | |
2079 | aarch64_insn standard_value; | |
2080 | if (candidates[i] == AARCH64_OPND_QLF_NIL) | |
2081 | break; | |
2082 | standard_value = aarch64_get_qualifier_standard_value (candidates[i]); | |
2083 | if ((standard_value & mask) == (value & mask)) | |
2084 | return candidates[i]; | |
2085 | } | |
2086 | return AARCH64_OPND_QLF_NIL; | |
2087 | } | |
2088 | ||
2089 | /* Given a list of qualifier sequences, return all possible valid qualifiers | |
2090 | for operand IDX in QUALIFIERS. | |
2091 | Assume QUALIFIERS is an array whose length is large enough. */ | |
2092 | ||
2093 | static void | |
2094 | get_operand_possible_qualifiers (int idx, | |
2095 | const aarch64_opnd_qualifier_seq_t *list, | |
2096 | enum aarch64_opnd_qualifier *qualifiers) | |
2097 | { | |
2098 | int i; | |
2099 | for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i) | |
2100 | if ((qualifiers[i] = list[i][idx]) == AARCH64_OPND_QLF_NIL) | |
2101 | break; | |
2102 | } | |
2103 | ||
2104 | /* Decode the size Q field for e.g. SHADD. | |
2105 | We tag one operand with the qualifer according to the code; | |
2106 | whether the qualifier is valid for this opcode or not, it is the | |
2107 | duty of the semantic checking. */ | |
2108 | ||
2109 | static int | |
2110 | decode_sizeq (aarch64_inst *inst) | |
2111 | { | |
2112 | int idx; | |
2113 | enum aarch64_opnd_qualifier qualifier; | |
2114 | aarch64_insn code; | |
2115 | aarch64_insn value, mask; | |
2116 | enum aarch64_field_kind fld_sz; | |
2117 | enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM]; | |
2118 | ||
2119 | if (inst->opcode->iclass == asisdlse | |
2120 | || inst->opcode->iclass == asisdlsep | |
2121 | || inst->opcode->iclass == asisdlso | |
2122 | || inst->opcode->iclass == asisdlsop) | |
2123 | fld_sz = FLD_vldst_size; | |
2124 | else | |
2125 | fld_sz = FLD_size; | |
2126 | ||
2127 | code = inst->value; | |
2128 | value = extract_fields (code, inst->opcode->mask, 2, fld_sz, FLD_Q); | |
2129 | /* Obtain the info that which bits of fields Q and size are actually | |
2130 | available for operand encoding. Opcodes like FMAXNM and FMLA have | |
2131 | size[1] unavailable. */ | |
2132 | mask = extract_fields (~inst->opcode->mask, 0, 2, fld_sz, FLD_Q); | |
2133 | ||
2134 | /* The index of the operand we are going to tag a qualifier and the qualifer | |
2135 | itself are reasoned from the value of the size and Q fields and the | |
2136 | possible valid qualifier lists. */ | |
2137 | idx = aarch64_select_operand_for_sizeq_field_coding (inst->opcode); | |
2138 | DEBUG_TRACE ("key idx: %d", idx); | |
2139 | ||
2140 | /* For most related instruciton, size:Q are fully available for operand | |
2141 | encoding. */ | |
2142 | if (mask == 0x7) | |
2143 | { | |
2144 | inst->operands[idx].qualifier = get_vreg_qualifier_from_value (value); | |
2145 | return 1; | |
2146 | } | |
2147 | ||
2148 | get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list, | |
2149 | candidates); | |
2150 | #ifdef DEBUG_AARCH64 | |
2151 | if (debug_dump) | |
2152 | { | |
2153 | int i; | |
2154 | for (i = 0; candidates[i] != AARCH64_OPND_QLF_NIL | |
2155 | && i < AARCH64_MAX_QLF_SEQ_NUM; ++i) | |
2156 | DEBUG_TRACE ("qualifier %d: %s", i, | |
2157 | aarch64_get_qualifier_name(candidates[i])); | |
2158 | DEBUG_TRACE ("%d, %d", (int)value, (int)mask); | |
2159 | } | |
2160 | #endif /* DEBUG_AARCH64 */ | |
2161 | ||
2162 | qualifier = get_qualifier_from_partial_encoding (value, candidates, mask); | |
2163 | ||
2164 | if (qualifier == AARCH64_OPND_QLF_NIL) | |
2165 | return 0; | |
2166 | ||
2167 | inst->operands[idx].qualifier = qualifier; | |
2168 | return 1; | |
2169 | } | |
2170 | ||
2171 | /* Decode size[0]:Q, i.e. bit 22 and bit 30, for | |
2172 | e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
2173 | ||
2174 | static int | |
2175 | decode_asimd_fcvt (aarch64_inst *inst) | |
2176 | { | |
2177 | aarch64_field field = {0, 0}; | |
2178 | aarch64_insn value; | |
2179 | enum aarch64_opnd_qualifier qualifier; | |
2180 | ||
2181 | gen_sub_field (FLD_size, 0, 1, &field); | |
2182 | value = extract_field_2 (&field, inst->value, 0); | |
2183 | qualifier = value == 0 ? AARCH64_OPND_QLF_V_4S | |
2184 | : AARCH64_OPND_QLF_V_2D; | |
2185 | switch (inst->opcode->op) | |
2186 | { | |
2187 | case OP_FCVTN: | |
2188 | case OP_FCVTN2: | |
2189 | /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
2190 | inst->operands[1].qualifier = qualifier; | |
2191 | break; | |
2192 | case OP_FCVTL: | |
2193 | case OP_FCVTL2: | |
2194 | /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */ | |
2195 | inst->operands[0].qualifier = qualifier; | |
2196 | break; | |
2197 | default: | |
2198 | assert (0); | |
2199 | return 0; | |
2200 | } | |
2201 | ||
2202 | return 1; | |
2203 | } | |
2204 | ||
2205 | /* Decode size[0], i.e. bit 22, for | |
2206 | e.g. FCVTXN <Vb><d>, <Va><n>. */ | |
2207 | ||
2208 | static int | |
2209 | decode_asisd_fcvtxn (aarch64_inst *inst) | |
2210 | { | |
2211 | aarch64_field field = {0, 0}; | |
2212 | gen_sub_field (FLD_size, 0, 1, &field); | |
2213 | if (!extract_field_2 (&field, inst->value, 0)) | |
2214 | return 0; | |
2215 | inst->operands[0].qualifier = AARCH64_OPND_QLF_S_S; | |
2216 | return 1; | |
2217 | } | |
2218 | ||
2219 | /* Decode the 'opc' field for e.g. FCVT <Dd>, <Sn>. */ | |
2220 | static int | |
2221 | decode_fcvt (aarch64_inst *inst) | |
2222 | { | |
2223 | enum aarch64_opnd_qualifier qualifier; | |
2224 | aarch64_insn value; | |
2225 | const aarch64_field field = {15, 2}; | |
2226 | ||
2227 | /* opc dstsize */ | |
2228 | value = extract_field_2 (&field, inst->value, 0); | |
2229 | switch (value) | |
2230 | { | |
2231 | case 0: qualifier = AARCH64_OPND_QLF_S_S; break; | |
2232 | case 1: qualifier = AARCH64_OPND_QLF_S_D; break; | |
2233 | case 3: qualifier = AARCH64_OPND_QLF_S_H; break; | |
2234 | default: return 0; | |
2235 | } | |
2236 | inst->operands[0].qualifier = qualifier; | |
2237 | ||
2238 | return 1; | |
2239 | } | |
2240 | ||
2241 | /* Do miscellaneous decodings that are not common enough to be driven by | |
2242 | flags. */ | |
2243 | ||
2244 | static int | |
2245 | do_misc_decoding (aarch64_inst *inst) | |
2246 | { | |
c0890d26 | 2247 | unsigned int value; |
a06ea964 NC |
2248 | switch (inst->opcode->op) |
2249 | { | |
2250 | case OP_FCVT: | |
2251 | return decode_fcvt (inst); | |
c0890d26 | 2252 | |
a06ea964 NC |
2253 | case OP_FCVTN: |
2254 | case OP_FCVTN2: | |
2255 | case OP_FCVTL: | |
2256 | case OP_FCVTL2: | |
2257 | return decode_asimd_fcvt (inst); | |
c0890d26 | 2258 | |
a06ea964 NC |
2259 | case OP_FCVTXN_S: |
2260 | return decode_asisd_fcvtxn (inst); | |
c0890d26 RS |
2261 | |
2262 | case OP_MOV_P_P: | |
2263 | case OP_MOVS_P_P: | |
2264 | value = extract_field (FLD_SVE_Pn, inst->value, 0); | |
2265 | return (value == extract_field (FLD_SVE_Pm, inst->value, 0) | |
2266 | && value == extract_field (FLD_SVE_Pg4_10, inst->value, 0)); | |
2267 | ||
2268 | case OP_MOV_Z_P_Z: | |
2269 | return (extract_field (FLD_SVE_Zd, inst->value, 0) | |
2270 | == extract_field (FLD_SVE_Zm_16, inst->value, 0)); | |
2271 | ||
2272 | case OP_MOV_Z_V: | |
2273 | /* Index must be zero. */ | |
2274 | value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5); | |
582e12bf | 2275 | return value > 0 && value <= 16 && value == (value & -value); |
c0890d26 RS |
2276 | |
2277 | case OP_MOV_Z_Z: | |
2278 | return (extract_field (FLD_SVE_Zn, inst->value, 0) | |
2279 | == extract_field (FLD_SVE_Zm_16, inst->value, 0)); | |
2280 | ||
2281 | case OP_MOV_Z_Zi: | |
2282 | /* Index must be nonzero. */ | |
2283 | value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5); | |
582e12bf | 2284 | return value > 0 && value != (value & -value); |
c0890d26 RS |
2285 | |
2286 | case OP_MOVM_P_P_P: | |
2287 | return (extract_field (FLD_SVE_Pd, inst->value, 0) | |
2288 | == extract_field (FLD_SVE_Pm, inst->value, 0)); | |
2289 | ||
2290 | case OP_MOVZS_P_P_P: | |
2291 | case OP_MOVZ_P_P_P: | |
2292 | return (extract_field (FLD_SVE_Pn, inst->value, 0) | |
2293 | == extract_field (FLD_SVE_Pm, inst->value, 0)); | |
2294 | ||
2295 | case OP_NOTS_P_P_P_Z: | |
2296 | case OP_NOT_P_P_P_Z: | |
2297 | return (extract_field (FLD_SVE_Pm, inst->value, 0) | |
2298 | == extract_field (FLD_SVE_Pg4_10, inst->value, 0)); | |
2299 | ||
a06ea964 NC |
2300 | default: |
2301 | return 0; | |
2302 | } | |
2303 | } | |
2304 | ||
2305 | /* Opcodes that have fields shared by multiple operands are usually flagged | |
2306 | with flags. In this function, we detect such flags, decode the related | |
2307 | field(s) and store the information in one of the related operands. The | |
2308 | 'one' operand is not any operand but one of the operands that can | |
2309 | accommadate all the information that has been decoded. */ | |
2310 | ||
2311 | static int | |
2312 | do_special_decoding (aarch64_inst *inst) | |
2313 | { | |
2314 | int idx; | |
2315 | aarch64_insn value; | |
2316 | /* Condition for truly conditional executed instructions, e.g. b.cond. */ | |
2317 | if (inst->opcode->flags & F_COND) | |
2318 | { | |
2319 | value = extract_field (FLD_cond2, inst->value, 0); | |
2320 | inst->cond = get_cond_from_value (value); | |
2321 | } | |
2322 | /* 'sf' field. */ | |
2323 | if (inst->opcode->flags & F_SF) | |
2324 | { | |
2325 | idx = select_operand_for_sf_field_coding (inst->opcode); | |
2326 | value = extract_field (FLD_sf, inst->value, 0); | |
2327 | inst->operands[idx].qualifier = get_greg_qualifier_from_value (value); | |
2328 | if ((inst->opcode->flags & F_N) | |
2329 | && extract_field (FLD_N, inst->value, 0) != value) | |
2330 | return 0; | |
2331 | } | |
ee804238 JW |
2332 | /* 'sf' field. */ |
2333 | if (inst->opcode->flags & F_LSE_SZ) | |
2334 | { | |
2335 | idx = select_operand_for_sf_field_coding (inst->opcode); | |
2336 | value = extract_field (FLD_lse_sz, inst->value, 0); | |
2337 | inst->operands[idx].qualifier = get_greg_qualifier_from_value (value); | |
2338 | } | |
a06ea964 NC |
2339 | /* size:Q fields. */ |
2340 | if (inst->opcode->flags & F_SIZEQ) | |
2341 | return decode_sizeq (inst); | |
2342 | ||
2343 | if (inst->opcode->flags & F_FPTYPE) | |
2344 | { | |
2345 | idx = select_operand_for_fptype_field_coding (inst->opcode); | |
2346 | value = extract_field (FLD_type, inst->value, 0); | |
2347 | switch (value) | |
2348 | { | |
2349 | case 0: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_S; break; | |
2350 | case 1: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_D; break; | |
2351 | case 3: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_H; break; | |
2352 | default: return 0; | |
2353 | } | |
2354 | } | |
2355 | ||
2356 | if (inst->opcode->flags & F_SSIZE) | |
2357 | { | |
2358 | /* N.B. some opcodes like FCMGT <V><d>, <V><n>, #0 have the size[1] as part | |
2359 | of the base opcode. */ | |
2360 | aarch64_insn mask; | |
2361 | enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM]; | |
2362 | idx = select_operand_for_scalar_size_field_coding (inst->opcode); | |
2363 | value = extract_field (FLD_size, inst->value, inst->opcode->mask); | |
2364 | mask = extract_field (FLD_size, ~inst->opcode->mask, 0); | |
2365 | /* For most related instruciton, the 'size' field is fully available for | |
2366 | operand encoding. */ | |
2367 | if (mask == 0x3) | |
2368 | inst->operands[idx].qualifier = get_sreg_qualifier_from_value (value); | |
2369 | else | |
2370 | { | |
2371 | get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list, | |
2372 | candidates); | |
2373 | inst->operands[idx].qualifier | |
2374 | = get_qualifier_from_partial_encoding (value, candidates, mask); | |
2375 | } | |
2376 | } | |
2377 | ||
2378 | if (inst->opcode->flags & F_T) | |
2379 | { | |
2380 | /* Num of consecutive '0's on the right side of imm5<3:0>. */ | |
2381 | int num = 0; | |
2382 | unsigned val, Q; | |
2383 | assert (aarch64_get_operand_class (inst->opcode->operands[0]) | |
2384 | == AARCH64_OPND_CLASS_SIMD_REG); | |
2385 | /* imm5<3:0> q <t> | |
2386 | 0000 x reserved | |
2387 | xxx1 0 8b | |
2388 | xxx1 1 16b | |
2389 | xx10 0 4h | |
2390 | xx10 1 8h | |
2391 | x100 0 2s | |
2392 | x100 1 4s | |
2393 | 1000 0 reserved | |
2394 | 1000 1 2d */ | |
2395 | val = extract_field (FLD_imm5, inst->value, 0); | |
2396 | while ((val & 0x1) == 0 && ++num <= 3) | |
2397 | val >>= 1; | |
2398 | if (num > 3) | |
2399 | return 0; | |
2400 | Q = (unsigned) extract_field (FLD_Q, inst->value, inst->opcode->mask); | |
2401 | inst->operands[0].qualifier = | |
2402 | get_vreg_qualifier_from_value ((num << 1) | Q); | |
2403 | } | |
2404 | ||
2405 | if (inst->opcode->flags & F_GPRSIZE_IN_Q) | |
2406 | { | |
2407 | /* Use Rt to encode in the case of e.g. | |
2408 | STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */ | |
2409 | idx = aarch64_operand_index (inst->opcode->operands, AARCH64_OPND_Rt); | |
2410 | if (idx == -1) | |
2411 | { | |
2412 | /* Otherwise use the result operand, which has to be a integer | |
2413 | register. */ | |
2414 | assert (aarch64_get_operand_class (inst->opcode->operands[0]) | |
2415 | == AARCH64_OPND_CLASS_INT_REG); | |
2416 | idx = 0; | |
2417 | } | |
2418 | assert (idx == 0 || idx == 1); | |
2419 | value = extract_field (FLD_Q, inst->value, 0); | |
2420 | inst->operands[idx].qualifier = get_greg_qualifier_from_value (value); | |
2421 | } | |
2422 | ||
2423 | if (inst->opcode->flags & F_LDS_SIZE) | |
2424 | { | |
2425 | aarch64_field field = {0, 0}; | |
2426 | assert (aarch64_get_operand_class (inst->opcode->operands[0]) | |
2427 | == AARCH64_OPND_CLASS_INT_REG); | |
2428 | gen_sub_field (FLD_opc, 0, 1, &field); | |
2429 | value = extract_field_2 (&field, inst->value, 0); | |
2430 | inst->operands[0].qualifier | |
2431 | = value ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X; | |
2432 | } | |
2433 | ||
2434 | /* Miscellaneous decoding; done as the last step. */ | |
2435 | if (inst->opcode->flags & F_MISC) | |
2436 | return do_misc_decoding (inst); | |
2437 | ||
2438 | return 1; | |
2439 | } | |
2440 | ||
2441 | /* Converters converting a real opcode instruction to its alias form. */ | |
2442 | ||
2443 | /* ROR <Wd>, <Ws>, #<shift> | |
2444 | is equivalent to: | |
2445 | EXTR <Wd>, <Ws>, <Ws>, #<shift>. */ | |
2446 | static int | |
2447 | convert_extr_to_ror (aarch64_inst *inst) | |
2448 | { | |
2449 | if (inst->operands[1].reg.regno == inst->operands[2].reg.regno) | |
2450 | { | |
2451 | copy_operand_info (inst, 2, 3); | |
2452 | inst->operands[3].type = AARCH64_OPND_NIL; | |
2453 | return 1; | |
2454 | } | |
2455 | return 0; | |
2456 | } | |
2457 | ||
e30181a5 YZ |
2458 | /* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb> |
2459 | is equivalent to: | |
2460 | USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */ | |
2461 | static int | |
2462 | convert_shll_to_xtl (aarch64_inst *inst) | |
2463 | { | |
2464 | if (inst->operands[2].imm.value == 0) | |
2465 | { | |
2466 | inst->operands[2].type = AARCH64_OPND_NIL; | |
2467 | return 1; | |
2468 | } | |
2469 | return 0; | |
2470 | } | |
2471 | ||
a06ea964 NC |
2472 | /* Convert |
2473 | UBFM <Xd>, <Xn>, #<shift>, #63. | |
2474 | to | |
2475 | LSR <Xd>, <Xn>, #<shift>. */ | |
2476 | static int | |
2477 | convert_bfm_to_sr (aarch64_inst *inst) | |
2478 | { | |
2479 | int64_t imms, val; | |
2480 | ||
2481 | imms = inst->operands[3].imm.value; | |
2482 | val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63; | |
2483 | if (imms == val) | |
2484 | { | |
2485 | inst->operands[3].type = AARCH64_OPND_NIL; | |
2486 | return 1; | |
2487 | } | |
2488 | ||
2489 | return 0; | |
2490 | } | |
2491 | ||
2492 | /* Convert MOV to ORR. */ | |
2493 | static int | |
2494 | convert_orr_to_mov (aarch64_inst *inst) | |
2495 | { | |
2496 | /* MOV <Vd>.<T>, <Vn>.<T> | |
2497 | is equivalent to: | |
2498 | ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>. */ | |
2499 | if (inst->operands[1].reg.regno == inst->operands[2].reg.regno) | |
2500 | { | |
2501 | inst->operands[2].type = AARCH64_OPND_NIL; | |
2502 | return 1; | |
2503 | } | |
2504 | return 0; | |
2505 | } | |
2506 | ||
2507 | /* When <imms> >= <immr>, the instruction written: | |
2508 | SBFX <Xd>, <Xn>, #<lsb>, #<width> | |
2509 | is equivalent to: | |
2510 | SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1). */ | |
2511 | ||
2512 | static int | |
2513 | convert_bfm_to_bfx (aarch64_inst *inst) | |
2514 | { | |
2515 | int64_t immr, imms; | |
2516 | ||
2517 | immr = inst->operands[2].imm.value; | |
2518 | imms = inst->operands[3].imm.value; | |
2519 | if (imms >= immr) | |
2520 | { | |
2521 | int64_t lsb = immr; | |
2522 | inst->operands[2].imm.value = lsb; | |
2523 | inst->operands[3].imm.value = imms + 1 - lsb; | |
2524 | /* The two opcodes have different qualifiers for | |
2525 | the immediate operands; reset to help the checking. */ | |
2526 | reset_operand_qualifier (inst, 2); | |
2527 | reset_operand_qualifier (inst, 3); | |
2528 | return 1; | |
2529 | } | |
2530 | ||
2531 | return 0; | |
2532 | } | |
2533 | ||
2534 | /* When <imms> < <immr>, the instruction written: | |
2535 | SBFIZ <Xd>, <Xn>, #<lsb>, #<width> | |
2536 | is equivalent to: | |
2537 | SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1). */ | |
2538 | ||
2539 | static int | |
2540 | convert_bfm_to_bfi (aarch64_inst *inst) | |
2541 | { | |
2542 | int64_t immr, imms, val; | |
2543 | ||
2544 | immr = inst->operands[2].imm.value; | |
2545 | imms = inst->operands[3].imm.value; | |
2546 | val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64; | |
2547 | if (imms < immr) | |
2548 | { | |
2549 | inst->operands[2].imm.value = (val - immr) & (val - 1); | |
2550 | inst->operands[3].imm.value = imms + 1; | |
2551 | /* The two opcodes have different qualifiers for | |
2552 | the immediate operands; reset to help the checking. */ | |
2553 | reset_operand_qualifier (inst, 2); | |
2554 | reset_operand_qualifier (inst, 3); | |
2555 | return 1; | |
2556 | } | |
2557 | ||
2558 | return 0; | |
2559 | } | |
2560 | ||
d685192a MW |
2561 | /* The instruction written: |
2562 | BFC <Xd>, #<lsb>, #<width> | |
2563 | is equivalent to: | |
2564 | BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1). */ | |
2565 | ||
2566 | static int | |
2567 | convert_bfm_to_bfc (aarch64_inst *inst) | |
2568 | { | |
2569 | int64_t immr, imms, val; | |
2570 | ||
2571 | /* Should have been assured by the base opcode value. */ | |
2572 | assert (inst->operands[1].reg.regno == 0x1f); | |
2573 | ||
2574 | immr = inst->operands[2].imm.value; | |
2575 | imms = inst->operands[3].imm.value; | |
2576 | val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64; | |
2577 | if (imms < immr) | |
2578 | { | |
2579 | /* Drop XZR from the second operand. */ | |
2580 | copy_operand_info (inst, 1, 2); | |
2581 | copy_operand_info (inst, 2, 3); | |
2582 | inst->operands[3].type = AARCH64_OPND_NIL; | |
2583 | ||
2584 | /* Recalculate the immediates. */ | |
2585 | inst->operands[1].imm.value = (val - immr) & (val - 1); | |
2586 | inst->operands[2].imm.value = imms + 1; | |
2587 | ||
2588 | /* The two opcodes have different qualifiers for the operands; reset to | |
2589 | help the checking. */ | |
2590 | reset_operand_qualifier (inst, 1); | |
2591 | reset_operand_qualifier (inst, 2); | |
2592 | reset_operand_qualifier (inst, 3); | |
2593 | ||
2594 | return 1; | |
2595 | } | |
2596 | ||
2597 | return 0; | |
2598 | } | |
2599 | ||
a06ea964 NC |
2600 | /* The instruction written: |
2601 | LSL <Xd>, <Xn>, #<shift> | |
2602 | is equivalent to: | |
2603 | UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>). */ | |
2604 | ||
2605 | static int | |
2606 | convert_ubfm_to_lsl (aarch64_inst *inst) | |
2607 | { | |
2608 | int64_t immr = inst->operands[2].imm.value; | |
2609 | int64_t imms = inst->operands[3].imm.value; | |
2610 | int64_t val | |
2611 | = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63; | |
2612 | ||
2613 | if ((immr == 0 && imms == val) || immr == imms + 1) | |
2614 | { | |
2615 | inst->operands[3].type = AARCH64_OPND_NIL; | |
2616 | inst->operands[2].imm.value = val - imms; | |
2617 | return 1; | |
2618 | } | |
2619 | ||
2620 | return 0; | |
2621 | } | |
2622 | ||
2623 | /* CINC <Wd>, <Wn>, <cond> | |
2624 | is equivalent to: | |
68a64283 YZ |
2625 | CSINC <Wd>, <Wn>, <Wn>, invert(<cond>) |
2626 | where <cond> is not AL or NV. */ | |
a06ea964 NC |
2627 | |
2628 | static int | |
2629 | convert_from_csel (aarch64_inst *inst) | |
2630 | { | |
68a64283 YZ |
2631 | if (inst->operands[1].reg.regno == inst->operands[2].reg.regno |
2632 | && (inst->operands[3].cond->value & 0xe) != 0xe) | |
a06ea964 NC |
2633 | { |
2634 | copy_operand_info (inst, 2, 3); | |
2635 | inst->operands[2].cond = get_inverted_cond (inst->operands[3].cond); | |
2636 | inst->operands[3].type = AARCH64_OPND_NIL; | |
2637 | return 1; | |
2638 | } | |
2639 | return 0; | |
2640 | } | |
2641 | ||
2642 | /* CSET <Wd>, <cond> | |
2643 | is equivalent to: | |
68a64283 YZ |
2644 | CSINC <Wd>, WZR, WZR, invert(<cond>) |
2645 | where <cond> is not AL or NV. */ | |
a06ea964 NC |
2646 | |
2647 | static int | |
2648 | convert_csinc_to_cset (aarch64_inst *inst) | |
2649 | { | |
2650 | if (inst->operands[1].reg.regno == 0x1f | |
68a64283 YZ |
2651 | && inst->operands[2].reg.regno == 0x1f |
2652 | && (inst->operands[3].cond->value & 0xe) != 0xe) | |
a06ea964 NC |
2653 | { |
2654 | copy_operand_info (inst, 1, 3); | |
2655 | inst->operands[1].cond = get_inverted_cond (inst->operands[3].cond); | |
2656 | inst->operands[3].type = AARCH64_OPND_NIL; | |
2657 | inst->operands[2].type = AARCH64_OPND_NIL; | |
2658 | return 1; | |
2659 | } | |
2660 | return 0; | |
2661 | } | |
2662 | ||
2663 | /* MOV <Wd>, #<imm> | |
2664 | is equivalent to: | |
2665 | MOVZ <Wd>, #<imm16>, LSL #<shift>. | |
2666 | ||
2667 | A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when | |
2668 | ORR has an immediate that could be generated by a MOVZ or MOVN instruction, | |
2669 | or where a MOVN has an immediate that could be encoded by MOVZ, or where | |
2670 | MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the | |
2671 | machine-instruction mnemonic must be used. */ | |
2672 | ||
2673 | static int | |
2674 | convert_movewide_to_mov (aarch64_inst *inst) | |
2675 | { | |
2676 | uint64_t value = inst->operands[1].imm.value; | |
2677 | /* MOVZ/MOVN #0 have a shift amount other than LSL #0. */ | |
2678 | if (value == 0 && inst->operands[1].shifter.amount != 0) | |
2679 | return 0; | |
2680 | inst->operands[1].type = AARCH64_OPND_IMM_MOV; | |
2681 | inst->operands[1].shifter.kind = AARCH64_MOD_NONE; | |
2682 | value <<= inst->operands[1].shifter.amount; | |
2683 | /* As an alias convertor, it has to be clear that the INST->OPCODE | |
2684 | is the opcode of the real instruction. */ | |
2685 | if (inst->opcode->op == OP_MOVN) | |
2686 | { | |
2687 | int is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W; | |
2688 | value = ~value; | |
2689 | /* A MOVN has an immediate that could be encoded by MOVZ. */ | |
535b785f | 2690 | if (aarch64_wide_constant_p (value, is32, NULL)) |
a06ea964 NC |
2691 | return 0; |
2692 | } | |
2693 | inst->operands[1].imm.value = value; | |
2694 | inst->operands[1].shifter.amount = 0; | |
2695 | return 1; | |
2696 | } | |
2697 | ||
2698 | /* MOV <Wd>, #<imm> | |
2699 | is equivalent to: | |
2700 | ORR <Wd>, WZR, #<imm>. | |
2701 | ||
2702 | A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when | |
2703 | ORR has an immediate that could be generated by a MOVZ or MOVN instruction, | |
2704 | or where a MOVN has an immediate that could be encoded by MOVZ, or where | |
2705 | MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the | |
2706 | machine-instruction mnemonic must be used. */ | |
2707 | ||
2708 | static int | |
2709 | convert_movebitmask_to_mov (aarch64_inst *inst) | |
2710 | { | |
2711 | int is32; | |
2712 | uint64_t value; | |
2713 | ||
2714 | /* Should have been assured by the base opcode value. */ | |
2715 | assert (inst->operands[1].reg.regno == 0x1f); | |
2716 | copy_operand_info (inst, 1, 2); | |
2717 | is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W; | |
2718 | inst->operands[1].type = AARCH64_OPND_IMM_MOV; | |
2719 | value = inst->operands[1].imm.value; | |
2720 | /* ORR has an immediate that could be generated by a MOVZ or MOVN | |
2721 | instruction. */ | |
2722 | if (inst->operands[0].reg.regno != 0x1f | |
535b785f AM |
2723 | && (aarch64_wide_constant_p (value, is32, NULL) |
2724 | || aarch64_wide_constant_p (~value, is32, NULL))) | |
a06ea964 NC |
2725 | return 0; |
2726 | ||
2727 | inst->operands[2].type = AARCH64_OPND_NIL; | |
2728 | return 1; | |
2729 | } | |
2730 | ||
2731 | /* Some alias opcodes are disassembled by being converted from their real-form. | |
2732 | N.B. INST->OPCODE is the real opcode rather than the alias. */ | |
2733 | ||
2734 | static int | |
2735 | convert_to_alias (aarch64_inst *inst, const aarch64_opcode *alias) | |
2736 | { | |
2737 | switch (alias->op) | |
2738 | { | |
2739 | case OP_ASR_IMM: | |
2740 | case OP_LSR_IMM: | |
2741 | return convert_bfm_to_sr (inst); | |
2742 | case OP_LSL_IMM: | |
2743 | return convert_ubfm_to_lsl (inst); | |
2744 | case OP_CINC: | |
2745 | case OP_CINV: | |
2746 | case OP_CNEG: | |
2747 | return convert_from_csel (inst); | |
2748 | case OP_CSET: | |
2749 | case OP_CSETM: | |
2750 | return convert_csinc_to_cset (inst); | |
2751 | case OP_UBFX: | |
2752 | case OP_BFXIL: | |
2753 | case OP_SBFX: | |
2754 | return convert_bfm_to_bfx (inst); | |
2755 | case OP_SBFIZ: | |
2756 | case OP_BFI: | |
2757 | case OP_UBFIZ: | |
2758 | return convert_bfm_to_bfi (inst); | |
d685192a MW |
2759 | case OP_BFC: |
2760 | return convert_bfm_to_bfc (inst); | |
a06ea964 NC |
2761 | case OP_MOV_V: |
2762 | return convert_orr_to_mov (inst); | |
2763 | case OP_MOV_IMM_WIDE: | |
2764 | case OP_MOV_IMM_WIDEN: | |
2765 | return convert_movewide_to_mov (inst); | |
2766 | case OP_MOV_IMM_LOG: | |
2767 | return convert_movebitmask_to_mov (inst); | |
2768 | case OP_ROR_IMM: | |
2769 | return convert_extr_to_ror (inst); | |
e30181a5 YZ |
2770 | case OP_SXTL: |
2771 | case OP_SXTL2: | |
2772 | case OP_UXTL: | |
2773 | case OP_UXTL2: | |
2774 | return convert_shll_to_xtl (inst); | |
a06ea964 NC |
2775 | default: |
2776 | return 0; | |
2777 | } | |
2778 | } | |
2779 | ||
561a72d4 TC |
2780 | static bfd_boolean |
2781 | aarch64_opcode_decode (const aarch64_opcode *, const aarch64_insn, | |
2782 | aarch64_inst *, int, aarch64_operand_error *errors); | |
a06ea964 NC |
2783 | |
2784 | /* Given the instruction information in *INST, check if the instruction has | |
2785 | any alias form that can be used to represent *INST. If the answer is yes, | |
2786 | update *INST to be in the form of the determined alias. */ | |
2787 | ||
2788 | /* In the opcode description table, the following flags are used in opcode | |
2789 | entries to help establish the relations between the real and alias opcodes: | |
2790 | ||
2791 | F_ALIAS: opcode is an alias | |
2792 | F_HAS_ALIAS: opcode has alias(es) | |
2793 | F_P1 | |
2794 | F_P2 | |
2795 | F_P3: Disassembly preference priority 1-3 (the larger the | |
2796 | higher). If nothing is specified, it is the priority | |
2797 | 0 by default, i.e. the lowest priority. | |
2798 | ||
2799 | Although the relation between the machine and the alias instructions are not | |
2800 | explicitly described, it can be easily determined from the base opcode | |
2801 | values, masks and the flags F_ALIAS and F_HAS_ALIAS in their opcode | |
2802 | description entries: | |
2803 | ||
2804 | The mask of an alias opcode must be equal to or a super-set (i.e. more | |
2805 | constrained) of that of the aliased opcode; so is the base opcode value. | |
2806 | ||
2807 | if (opcode_has_alias (real) && alias_opcode_p (opcode) | |
2808 | && (opcode->mask & real->mask) == real->mask | |
2809 | && (real->mask & opcode->opcode) == (real->mask & real->opcode)) | |
2810 | then OPCODE is an alias of, and only of, the REAL instruction | |
2811 | ||
2812 | The alias relationship is forced flat-structured to keep related algorithm | |
2813 | simple; an opcode entry cannot be flagged with both F_ALIAS and F_HAS_ALIAS. | |
2814 | ||
2815 | During the disassembling, the decoding decision tree (in | |
2816 | opcodes/aarch64-dis-2.c) always returns an machine instruction opcode entry; | |
2817 | if the decoding of such a machine instruction succeeds (and -Mno-aliases is | |
2818 | not specified), the disassembler will check whether there is any alias | |
2819 | instruction exists for this real instruction. If there is, the disassembler | |
2820 | will try to disassemble the 32-bit binary again using the alias's rule, or | |
2821 | try to convert the IR to the form of the alias. In the case of the multiple | |
2822 | aliases, the aliases are tried one by one from the highest priority | |
2823 | (currently the flag F_P3) to the lowest priority (no priority flag), and the | |
2824 | first succeeds first adopted. | |
2825 | ||
2826 | You may ask why there is a need for the conversion of IR from one form to | |
2827 | another in handling certain aliases. This is because on one hand it avoids | |
2828 | adding more operand code to handle unusual encoding/decoding; on other | |
2829 | hand, during the disassembling, the conversion is an effective approach to | |
2830 | check the condition of an alias (as an alias may be adopted only if certain | |
2831 | conditions are met). | |
2832 | ||
2833 | In order to speed up the alias opcode lookup, aarch64-gen has preprocessed | |
2834 | aarch64_opcode_table and generated aarch64_find_alias_opcode and | |
2835 | aarch64_find_next_alias_opcode (in opcodes/aarch64-dis-2.c) to help. */ | |
2836 | ||
2837 | static void | |
561a72d4 TC |
2838 | determine_disassembling_preference (struct aarch64_inst *inst, |
2839 | aarch64_operand_error *errors) | |
a06ea964 NC |
2840 | { |
2841 | const aarch64_opcode *opcode; | |
2842 | const aarch64_opcode *alias; | |
2843 | ||
2844 | opcode = inst->opcode; | |
2845 | ||
2846 | /* This opcode does not have an alias, so use itself. */ | |
535b785f | 2847 | if (!opcode_has_alias (opcode)) |
a06ea964 NC |
2848 | return; |
2849 | ||
2850 | alias = aarch64_find_alias_opcode (opcode); | |
2851 | assert (alias); | |
2852 | ||
2853 | #ifdef DEBUG_AARCH64 | |
2854 | if (debug_dump) | |
2855 | { | |
2856 | const aarch64_opcode *tmp = alias; | |
2857 | printf ("#### LIST orderd: "); | |
2858 | while (tmp) | |
2859 | { | |
2860 | printf ("%s, ", tmp->name); | |
2861 | tmp = aarch64_find_next_alias_opcode (tmp); | |
2862 | } | |
2863 | printf ("\n"); | |
2864 | } | |
2865 | #endif /* DEBUG_AARCH64 */ | |
2866 | ||
2867 | for (; alias; alias = aarch64_find_next_alias_opcode (alias)) | |
2868 | { | |
2869 | DEBUG_TRACE ("try %s", alias->name); | |
35822b38 | 2870 | assert (alias_opcode_p (alias) || opcode_has_alias (opcode)); |
a06ea964 NC |
2871 | |
2872 | /* An alias can be a pseudo opcode which will never be used in the | |
2873 | disassembly, e.g. BIC logical immediate is such a pseudo opcode | |
2874 | aliasing AND. */ | |
2875 | if (pseudo_opcode_p (alias)) | |
2876 | { | |
2877 | DEBUG_TRACE ("skip pseudo %s", alias->name); | |
2878 | continue; | |
2879 | } | |
2880 | ||
2881 | if ((inst->value & alias->mask) != alias->opcode) | |
2882 | { | |
2883 | DEBUG_TRACE ("skip %s as base opcode not match", alias->name); | |
2884 | continue; | |
2885 | } | |
95830c98 AC |
2886 | |
2887 | if (!AARCH64_CPU_HAS_FEATURE (arch_variant, *alias->avariant)) | |
2888 | { | |
2889 | DEBUG_TRACE ("skip %s: we're missing features", alias->name); | |
2890 | continue; | |
2891 | } | |
2892 | ||
a06ea964 NC |
2893 | /* No need to do any complicated transformation on operands, if the alias |
2894 | opcode does not have any operand. */ | |
2895 | if (aarch64_num_of_operands (alias) == 0 && alias->opcode == inst->value) | |
2896 | { | |
2897 | DEBUG_TRACE ("succeed with 0-operand opcode %s", alias->name); | |
2898 | aarch64_replace_opcode (inst, alias); | |
2899 | return; | |
2900 | } | |
2901 | if (alias->flags & F_CONV) | |
2902 | { | |
2903 | aarch64_inst copy; | |
2904 | memcpy (©, inst, sizeof (aarch64_inst)); | |
2905 | /* ALIAS is the preference as long as the instruction can be | |
2906 | successfully converted to the form of ALIAS. */ | |
2907 | if (convert_to_alias (©, alias) == 1) | |
2908 | { | |
2909 | aarch64_replace_opcode (©, alias); | |
3979cf50 SP |
2910 | assert (aarch64_match_operands_constraint (MAYBE_C64, ©, |
2911 | NULL)); | |
a06ea964 NC |
2912 | DEBUG_TRACE ("succeed with %s via conversion", alias->name); |
2913 | memcpy (inst, ©, sizeof (aarch64_inst)); | |
2914 | return; | |
2915 | } | |
2916 | } | |
2917 | else | |
2918 | { | |
2919 | /* Directly decode the alias opcode. */ | |
2920 | aarch64_inst temp; | |
2921 | memset (&temp, '\0', sizeof (aarch64_inst)); | |
561a72d4 | 2922 | if (aarch64_opcode_decode (alias, inst->value, &temp, 1, errors) == 1) |
a06ea964 NC |
2923 | { |
2924 | DEBUG_TRACE ("succeed with %s via direct decoding", alias->name); | |
2925 | memcpy (inst, &temp, sizeof (aarch64_inst)); | |
2926 | return; | |
2927 | } | |
2928 | } | |
2929 | } | |
2930 | } | |
2931 | ||
116b6019 RS |
2932 | /* Some instructions (including all SVE ones) use the instruction class |
2933 | to describe how a qualifiers_list index is represented in the instruction | |
2934 | encoding. If INST is such an instruction, decode the appropriate fields | |
2935 | and fill in the operand qualifiers accordingly. Return true if no | |
2936 | problems are found. */ | |
2937 | ||
2938 | static bfd_boolean | |
2939 | aarch64_decode_variant_using_iclass (aarch64_inst *inst) | |
2940 | { | |
2941 | int i, variant; | |
2942 | ||
2943 | variant = 0; | |
2944 | switch (inst->opcode->iclass) | |
2945 | { | |
2946 | case sve_cpy: | |
2947 | variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_14); | |
2948 | break; | |
2949 | ||
2950 | case sve_index: | |
582e12bf RS |
2951 | i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5); |
2952 | if ((i & 31) == 0) | |
116b6019 RS |
2953 | return FALSE; |
2954 | while ((i & 1) == 0) | |
2955 | { | |
2956 | i >>= 1; | |
2957 | variant += 1; | |
2958 | } | |
2959 | break; | |
2960 | ||
2961 | case sve_limm: | |
2962 | /* Pick the smallest applicable element size. */ | |
2963 | if ((inst->value & 0x20600) == 0x600) | |
2964 | variant = 0; | |
2965 | else if ((inst->value & 0x20400) == 0x400) | |
2966 | variant = 1; | |
2967 | else if ((inst->value & 0x20000) == 0) | |
2968 | variant = 2; | |
2969 | else | |
2970 | variant = 3; | |
2971 | break; | |
2972 | ||
2973 | case sve_misc: | |
2974 | /* sve_misc instructions have only a single variant. */ | |
2975 | break; | |
2976 | ||
2977 | case sve_movprfx: | |
2978 | variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_16); | |
2979 | break; | |
2980 | ||
2981 | case sve_pred_zm: | |
2982 | variant = extract_field (FLD_SVE_M_4, inst->value, 0); | |
2983 | break; | |
2984 | ||
2985 | case sve_shift_pred: | |
2986 | i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_8); | |
2987 | sve_shift: | |
2988 | if (i == 0) | |
2989 | return FALSE; | |
2990 | while (i != 1) | |
2991 | { | |
2992 | i >>= 1; | |
2993 | variant += 1; | |
2994 | } | |
2995 | break; | |
2996 | ||
2997 | case sve_shift_unpred: | |
2998 | i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_19); | |
2999 | goto sve_shift; | |
3000 | ||
3001 | case sve_size_bhs: | |
3002 | variant = extract_field (FLD_size, inst->value, 0); | |
3003 | if (variant >= 3) | |
3004 | return FALSE; | |
3005 | break; | |
3006 | ||
3007 | case sve_size_bhsd: | |
3008 | variant = extract_field (FLD_size, inst->value, 0); | |
3009 | break; | |
3010 | ||
3011 | case sve_size_hsd: | |
3012 | i = extract_field (FLD_size, inst->value, 0); | |
3013 | if (i < 1) | |
3014 | return FALSE; | |
3015 | variant = i - 1; | |
3016 | break; | |
3017 | ||
3c705960 | 3018 | case sve_size_bh: |
116b6019 RS |
3019 | case sve_size_sd: |
3020 | variant = extract_field (FLD_SVE_sz, inst->value, 0); | |
3021 | break; | |
3022 | ||
0a57e14f MM |
3023 | case sve_size_sd2: |
3024 | variant = extract_field (FLD_SVE_sz2, inst->value, 0); | |
3025 | break; | |
3026 | ||
3bd82c86 MM |
3027 | case sve_size_hsd2: |
3028 | i = extract_field (FLD_SVE_size, inst->value, 0); | |
3029 | if (i < 1) | |
3030 | return FALSE; | |
3031 | variant = i - 1; | |
3032 | break; | |
3033 | ||
41be57ca MM |
3034 | case sve_size_13: |
3035 | /* Ignore low bit of this field since that is set in the opcode for | |
3036 | instructions of this iclass. */ | |
3037 | i = (extract_field (FLD_size, inst->value, 0) & 2); | |
3038 | variant = (i >> 1); | |
cd50a87a MM |
3039 | break; |
3040 | ||
1be5f94f MM |
3041 | case sve_shift_tsz_bhsd: |
3042 | i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_19); | |
3043 | if (i == 0) | |
3044 | return FALSE; | |
3045 | while (i != 1) | |
3046 | { | |
3047 | i >>= 1; | |
3048 | variant += 1; | |
3049 | } | |
3050 | break; | |
3051 | ||
fd1dc4a0 MM |
3052 | case sve_size_tsz_bhs: |
3053 | i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19); | |
9d48687b AM |
3054 | if (i == 0) |
3055 | return FALSE; | |
fd1dc4a0 MM |
3056 | while (i != 1) |
3057 | { | |
3058 | if (i & 1) | |
3059 | return FALSE; | |
3060 | i >>= 1; | |
3061 | variant += 1; | |
3062 | } | |
3063 | break; | |
3064 | ||
3c17238b MM |
3065 | case sve_shift_tsz_hsd: |
3066 | i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19); | |
3067 | if (i == 0) | |
3068 | return FALSE; | |
3069 | while (i != 1) | |
3070 | { | |
3071 | i >>= 1; | |
3072 | variant += 1; | |
3073 | } | |
3074 | break; | |
3075 | ||
116b6019 RS |
3076 | default: |
3077 | /* No mapping between instruction class and qualifiers. */ | |
3078 | return TRUE; | |
3079 | } | |
3080 | ||
3081 | for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) | |
3082 | inst->operands[i].qualifier = inst->opcode->qualifiers_list[variant][i]; | |
3083 | return TRUE; | |
3084 | } | |
a06ea964 NC |
3085 | /* Decode the CODE according to OPCODE; fill INST. Return 0 if the decoding |
3086 | fails, which meanes that CODE is not an instruction of OPCODE; otherwise | |
3087 | return 1. | |
3088 | ||
3089 | If OPCODE has alias(es) and NOALIASES_P is 0, an alias opcode may be | |
3090 | determined and used to disassemble CODE; this is done just before the | |
3091 | return. */ | |
3092 | ||
561a72d4 | 3093 | static bfd_boolean |
a06ea964 | 3094 | aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code, |
561a72d4 TC |
3095 | aarch64_inst *inst, int noaliases_p, |
3096 | aarch64_operand_error *errors) | |
a06ea964 NC |
3097 | { |
3098 | int i; | |
3099 | ||
3100 | DEBUG_TRACE ("enter with %s", opcode->name); | |
3101 | ||
3102 | assert (opcode && inst); | |
3103 | ||
b3ac5c6c TC |
3104 | /* Clear inst. */ |
3105 | memset (inst, '\0', sizeof (aarch64_inst)); | |
3106 | ||
a06ea964 NC |
3107 | /* Check the base opcode. */ |
3108 | if ((code & opcode->mask) != (opcode->opcode & opcode->mask)) | |
3109 | { | |
3110 | DEBUG_TRACE ("base opcode match FAIL"); | |
3111 | goto decode_fail; | |
3112 | } | |
3113 | ||
a06ea964 NC |
3114 | inst->opcode = opcode; |
3115 | inst->value = code; | |
3116 | ||
3117 | /* Assign operand codes and indexes. */ | |
3118 | for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) | |
3119 | { | |
3120 | if (opcode->operands[i] == AARCH64_OPND_NIL) | |
3121 | break; | |
3122 | inst->operands[i].type = opcode->operands[i]; | |
3123 | inst->operands[i].idx = i; | |
3124 | } | |
3125 | ||
3126 | /* Call the opcode decoder indicated by flags. */ | |
3127 | if (opcode_has_special_coder (opcode) && do_special_decoding (inst) == 0) | |
3128 | { | |
3129 | DEBUG_TRACE ("opcode flag-based decoder FAIL"); | |
3130 | goto decode_fail; | |
3131 | } | |
3132 | ||
116b6019 RS |
3133 | /* Possibly use the instruction class to determine the correct |
3134 | qualifier. */ | |
3135 | if (!aarch64_decode_variant_using_iclass (inst)) | |
3136 | { | |
3137 | DEBUG_TRACE ("iclass-based decoder FAIL"); | |
3138 | goto decode_fail; | |
3139 | } | |
3140 | ||
a06ea964 NC |
3141 | /* Call operand decoders. */ |
3142 | for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) | |
3143 | { | |
3144 | const aarch64_operand *opnd; | |
3145 | enum aarch64_opnd type; | |
4bd13cde | 3146 | |
a06ea964 NC |
3147 | type = opcode->operands[i]; |
3148 | if (type == AARCH64_OPND_NIL) | |
3149 | break; | |
3150 | opnd = &aarch64_operands[type]; | |
3151 | if (operand_has_extractor (opnd) | |
561a72d4 TC |
3152 | && (! aarch64_extract_operand (opnd, &inst->operands[i], code, inst, |
3153 | errors))) | |
a06ea964 NC |
3154 | { |
3155 | DEBUG_TRACE ("operand decoder FAIL at operand %d", i); | |
3156 | goto decode_fail; | |
3157 | } | |
3158 | } | |
3159 | ||
4bd13cde | 3160 | /* If the opcode has a verifier, then check it now. */ |
755b748f TC |
3161 | if (opcode->verifier |
3162 | && opcode->verifier (inst, code, 0, FALSE, errors, NULL) != ERR_OK) | |
4bd13cde NC |
3163 | { |
3164 | DEBUG_TRACE ("operand verifier FAIL"); | |
3165 | goto decode_fail; | |
3166 | } | |
3167 | ||
a06ea964 | 3168 | /* Match the qualifiers. */ |
3979cf50 | 3169 | if (aarch64_match_operands_constraint (MAYBE_C64, inst, NULL) == 1) |
a06ea964 NC |
3170 | { |
3171 | /* Arriving here, the CODE has been determined as a valid instruction | |
3172 | of OPCODE and *INST has been filled with information of this OPCODE | |
3173 | instruction. Before the return, check if the instruction has any | |
3174 | alias and should be disassembled in the form of its alias instead. | |
3175 | If the answer is yes, *INST will be updated. */ | |
3176 | if (!noaliases_p) | |
561a72d4 | 3177 | determine_disassembling_preference (inst, errors); |
a06ea964 | 3178 | DEBUG_TRACE ("SUCCESS"); |
561a72d4 | 3179 | return TRUE; |
a06ea964 NC |
3180 | } |
3181 | else | |
3182 | { | |
3183 | DEBUG_TRACE ("constraint matching FAIL"); | |
3184 | } | |
3185 | ||
dc1e8a47 | 3186 | decode_fail: |
561a72d4 | 3187 | return FALSE; |
a06ea964 NC |
3188 | } |
3189 | \f | |
3190 | /* This does some user-friendly fix-up to *INST. It is currently focus on | |
3191 | the adjustment of qualifiers to help the printed instruction | |
3192 | recognized/understood more easily. */ | |
3193 | ||
3194 | static void | |
3195 | user_friendly_fixup (aarch64_inst *inst) | |
3196 | { | |
3197 | switch (inst->opcode->iclass) | |
3198 | { | |
3199 | case testbranch: | |
3200 | /* TBNZ Xn|Wn, #uimm6, label | |
3201 | Test and Branch Not Zero: conditionally jumps to label if bit number | |
3202 | uimm6 in register Xn is not zero. The bit number implies the width of | |
3203 | the register, which may be written and should be disassembled as Wn if | |
3204 | uimm is less than 32. Limited to a branch offset range of +/- 32KiB. | |
3205 | */ | |
3206 | if (inst->operands[1].imm.value < 32) | |
3207 | inst->operands[0].qualifier = AARCH64_OPND_QLF_W; | |
3208 | break; | |
3209 | default: break; | |
3210 | } | |
3211 | } | |
3212 | ||
43cdf5ae YQ |
3213 | /* Decode INSN and fill in *INST the instruction information. An alias |
3214 | opcode may be filled in *INSN if NOALIASES_P is FALSE. Return zero on | |
3215 | success. */ | |
a06ea964 | 3216 | |
1d482394 | 3217 | enum err_type |
43cdf5ae | 3218 | aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst, |
561a72d4 TC |
3219 | bfd_boolean noaliases_p, |
3220 | aarch64_operand_error *errors) | |
a06ea964 NC |
3221 | { |
3222 | const aarch64_opcode *opcode = aarch64_opcode_lookup (insn); | |
3223 | ||
3224 | #ifdef DEBUG_AARCH64 | |
3225 | if (debug_dump) | |
3226 | { | |
3227 | const aarch64_opcode *tmp = opcode; | |
3228 | printf ("\n"); | |
3229 | DEBUG_TRACE ("opcode lookup:"); | |
3230 | while (tmp != NULL) | |
3231 | { | |
3232 | aarch64_verbose (" %s", tmp->name); | |
3233 | tmp = aarch64_find_next_opcode (tmp); | |
3234 | } | |
3235 | } | |
3236 | #endif /* DEBUG_AARCH64 */ | |
3237 | ||
3238 | /* A list of opcodes may have been found, as aarch64_opcode_lookup cannot | |
3239 | distinguish some opcodes, e.g. SSHR and MOVI, which almost share the same | |
3240 | opcode field and value, apart from the difference that one of them has an | |
3241 | extra field as part of the opcode, but such a field is used for operand | |
3242 | encoding in other opcode(s) ('immh' in the case of the example). */ | |
3243 | while (opcode != NULL) | |
3244 | { | |
3245 | /* But only one opcode can be decoded successfully for, as the | |
3246 | decoding routine will check the constraint carefully. */ | |
561a72d4 | 3247 | if (aarch64_opcode_decode (opcode, insn, inst, noaliases_p, errors) == 1) |
a06ea964 NC |
3248 | return ERR_OK; |
3249 | opcode = aarch64_find_next_opcode (opcode); | |
3250 | } | |
3251 | ||
3252 | return ERR_UND; | |
3253 | } | |
3254 | ||
3255 | /* Print operands. */ | |
3256 | ||
3257 | static void | |
3258 | print_operands (bfd_vma pc, const aarch64_opcode *opcode, | |
bde90be2 TC |
3259 | const aarch64_opnd_info *opnds, struct disassemble_info *info, |
3260 | bfd_boolean *has_notes) | |
a06ea964 | 3261 | { |
7d02540a | 3262 | char *notes = NULL; |
bde90be2 | 3263 | int i, pcrel_p, num_printed; |
a06ea964 NC |
3264 | for (i = 0, num_printed = 0; i < AARCH64_MAX_OPND_NUM; ++i) |
3265 | { | |
0d2f91fe | 3266 | char str[128]; |
a06ea964 NC |
3267 | /* We regard the opcode operand info more, however we also look into |
3268 | the inst->operands to support the disassembling of the optional | |
3269 | operand. | |
3270 | The two operand code should be the same in all cases, apart from | |
3271 | when the operand can be optional. */ | |
3272 | if (opcode->operands[i] == AARCH64_OPND_NIL | |
3273 | || opnds[i].type == AARCH64_OPND_NIL) | |
3274 | break; | |
3275 | ||
3276 | /* Generate the operand string in STR. */ | |
0d2f91fe | 3277 | aarch64_print_operand (str, sizeof (str), pc, opcode, opnds, i, &pcrel_p, |
3979cf50 | 3278 | &info->target, ¬es, arch_variant | MAYBE_C64); |
a06ea964 NC |
3279 | |
3280 | /* Print the delimiter (taking account of omitted operand(s)). */ | |
3281 | if (str[0] != '\0') | |
3282 | (*info->fprintf_func) (info->stream, "%s", | |
3283 | num_printed++ == 0 ? "\t" : ", "); | |
3284 | ||
3285 | /* Print the operand. */ | |
3286 | if (pcrel_p) | |
3287 | (*info->print_address_func) (info->target, info); | |
3288 | else | |
3289 | (*info->fprintf_func) (info->stream, "%s", str); | |
3290 | } | |
7d02540a TC |
3291 | |
3292 | if (notes && !no_notes) | |
bde90be2 TC |
3293 | { |
3294 | *has_notes = TRUE; | |
3295 | (*info->fprintf_func) (info->stream, " // note: %s", notes); | |
3296 | } | |
a06ea964 NC |
3297 | } |
3298 | ||
bb7eff52 RS |
3299 | /* Set NAME to a copy of INST's mnemonic with the "." suffix removed. */ |
3300 | ||
3301 | static void | |
3302 | remove_dot_suffix (char *name, const aarch64_inst *inst) | |
3303 | { | |
3304 | char *ptr; | |
3305 | size_t len; | |
3306 | ||
3307 | ptr = strchr (inst->opcode->name, '.'); | |
3308 | assert (ptr && inst->cond); | |
3309 | len = ptr - inst->opcode->name; | |
3310 | assert (len < 8); | |
3311 | strncpy (name, inst->opcode->name, len); | |
3312 | name[len] = '\0'; | |
3313 | } | |
3314 | ||
a06ea964 NC |
3315 | /* Print the instruction mnemonic name. */ |
3316 | ||
3317 | static void | |
3318 | print_mnemonic_name (const aarch64_inst *inst, struct disassemble_info *info) | |
3319 | { | |
3320 | if (inst->opcode->flags & F_COND) | |
3321 | { | |
3322 | /* For instructions that are truly conditionally executed, e.g. b.cond, | |
3323 | prepare the full mnemonic name with the corresponding condition | |
3324 | suffix. */ | |
bb7eff52 RS |
3325 | char name[8]; |
3326 | ||
3327 | remove_dot_suffix (name, inst); | |
a06ea964 NC |
3328 | (*info->fprintf_func) (info->stream, "%s.%s", name, inst->cond->names[0]); |
3329 | } | |
3330 | else | |
3331 | (*info->fprintf_func) (info->stream, "%s", inst->opcode->name); | |
3332 | } | |
3333 | ||
bb7eff52 RS |
3334 | /* Decide whether we need to print a comment after the operands of |
3335 | instruction INST. */ | |
3336 | ||
3337 | static void | |
3338 | print_comment (const aarch64_inst *inst, struct disassemble_info *info) | |
3339 | { | |
3340 | if (inst->opcode->flags & F_COND) | |
3341 | { | |
3342 | char name[8]; | |
3343 | unsigned int i, num_conds; | |
3344 | ||
3345 | remove_dot_suffix (name, inst); | |
3346 | num_conds = ARRAY_SIZE (inst->cond->names); | |
3347 | for (i = 1; i < num_conds && inst->cond->names[i]; ++i) | |
3348 | (*info->fprintf_func) (info->stream, "%s %s.%s", | |
3349 | i == 1 ? " //" : ",", | |
3350 | name, inst->cond->names[i]); | |
3351 | } | |
3352 | } | |
3353 | ||
bde90be2 TC |
3354 | /* Build notes from verifiers into a string for printing. */ |
3355 | ||
3356 | static void | |
3357 | print_verifier_notes (aarch64_operand_error *detail, | |
3358 | struct disassemble_info *info) | |
3359 | { | |
3360 | if (no_notes) | |
3361 | return; | |
3362 | ||
3363 | /* The output of the verifier cannot be a fatal error, otherwise the assembly | |
3364 | would not have succeeded. We can safely ignore these. */ | |
3365 | assert (detail->non_fatal); | |
3366 | assert (detail->error); | |
3367 | ||
3368 | /* If there are multiple verifier messages, concat them up to 1k. */ | |
3369 | (*info->fprintf_func) (info->stream, " // note: %s", detail->error); | |
3370 | if (detail->index >= 0) | |
3371 | (*info->fprintf_func) (info->stream, " at operand %d", detail->index + 1); | |
3372 | } | |
3373 | ||
a06ea964 NC |
3374 | /* Print the instruction according to *INST. */ |
3375 | ||
3376 | static void | |
3377 | print_aarch64_insn (bfd_vma pc, const aarch64_inst *inst, | |
bde90be2 TC |
3378 | const aarch64_insn code, |
3379 | struct disassemble_info *info, | |
3380 | aarch64_operand_error *mismatch_details) | |
a06ea964 | 3381 | { |
bde90be2 TC |
3382 | bfd_boolean has_notes = FALSE; |
3383 | ||
a06ea964 | 3384 | print_mnemonic_name (inst, info); |
bde90be2 | 3385 | print_operands (pc, inst->opcode, inst->operands, info, &has_notes); |
bb7eff52 | 3386 | print_comment (inst, info); |
bde90be2 TC |
3387 | |
3388 | /* We've already printed a note, not enough space to print more so exit. | |
3389 | Usually notes shouldn't overlap so it shouldn't happen that we have a note | |
3390 | from a register and instruction at the same time. */ | |
3391 | if (has_notes) | |
3392 | return; | |
3393 | ||
3394 | /* Always run constraint verifiers, this is needed because constraints need to | |
3395 | maintain a global state regardless of whether the instruction has the flag | |
3396 | set or not. */ | |
3397 | enum err_type result = verify_constraints (inst, code, pc, FALSE, | |
3398 | mismatch_details, &insn_sequence); | |
3399 | switch (result) | |
3400 | { | |
3401 | case ERR_UND: | |
3402 | case ERR_UNP: | |
3403 | case ERR_NYI: | |
3404 | assert (0); | |
3405 | case ERR_VFI: | |
3406 | print_verifier_notes (mismatch_details, info); | |
3407 | break; | |
3408 | default: | |
3409 | break; | |
3410 | } | |
a06ea964 NC |
3411 | } |
3412 | ||
3413 | /* Entry-point of the instruction disassembler and printer. */ | |
3414 | ||
3415 | static void | |
3416 | print_insn_aarch64_word (bfd_vma pc, | |
3417 | uint32_t word, | |
561a72d4 TC |
3418 | struct disassemble_info *info, |
3419 | aarch64_operand_error *errors) | |
a06ea964 | 3420 | { |
1d482394 | 3421 | static const char *err_msg[ERR_NR_ENTRIES+1] = |
a06ea964 | 3422 | { |
1d482394 TC |
3423 | [ERR_OK] = "_", |
3424 | [ERR_UND] = "undefined", | |
3425 | [ERR_UNP] = "unpredictable", | |
3426 | [ERR_NYI] = "NYI" | |
a06ea964 NC |
3427 | }; |
3428 | ||
1d482394 | 3429 | enum err_type ret; |
a06ea964 NC |
3430 | aarch64_inst inst; |
3431 | ||
3432 | info->insn_info_valid = 1; | |
3433 | info->branch_delay_insns = 0; | |
3434 | info->data_size = 0; | |
3435 | info->target = 0; | |
3436 | info->target2 = 0; | |
3437 | ||
3438 | if (info->flags & INSN_HAS_RELOC) | |
3439 | /* If the instruction has a reloc associated with it, then | |
3440 | the offset field in the instruction will actually be the | |
3441 | addend for the reloc. (If we are using REL type relocs). | |
3442 | In such cases, we can ignore the pc when computing | |
3443 | addresses, since the addend is not currently pc-relative. */ | |
3444 | pc = 0; | |
3445 | ||
561a72d4 | 3446 | ret = aarch64_decode_insn (word, &inst, no_aliases, errors); |
a06ea964 NC |
3447 | |
3448 | if (((word >> 21) & 0x3ff) == 1) | |
3449 | { | |
3450 | /* RESERVED for ALES. */ | |
3451 | assert (ret != ERR_OK); | |
3452 | ret = ERR_NYI; | |
3453 | } | |
3454 | ||
3455 | switch (ret) | |
3456 | { | |
3457 | case ERR_UND: | |
3458 | case ERR_UNP: | |
3459 | case ERR_NYI: | |
3460 | /* Handle undefined instructions. */ | |
3461 | info->insn_type = dis_noninsn; | |
3462 | (*info->fprintf_func) (info->stream,".inst\t0x%08x ; %s", | |
1d482394 | 3463 | word, err_msg[ret]); |
a06ea964 NC |
3464 | break; |
3465 | case ERR_OK: | |
3466 | user_friendly_fixup (&inst); | |
bde90be2 | 3467 | print_aarch64_insn (pc, &inst, word, info, errors); |
a06ea964 NC |
3468 | break; |
3469 | default: | |
3470 | abort (); | |
3471 | } | |
3472 | } | |
3473 | ||
3474 | /* Disallow mapping symbols ($x, $d etc) from | |
3475 | being displayed in symbol relative addresses. */ | |
3476 | ||
3477 | bfd_boolean | |
3478 | aarch64_symbol_is_valid (asymbol * sym, | |
3479 | struct disassemble_info * info ATTRIBUTE_UNUSED) | |
3480 | { | |
3481 | const char * name; | |
3482 | ||
3483 | if (sym == NULL) | |
3484 | return FALSE; | |
3485 | ||
3486 | name = bfd_asymbol_name (sym); | |
3487 | ||
3488 | return name | |
3489 | && (name[0] != '$' | |
3979cf50 | 3490 | || (name[1] != 'x' && name[1] != 'd' && name[1] != 'c') |
a06ea964 NC |
3491 | || (name[2] != '\0' && name[2] != '.')); |
3492 | } | |
3493 | ||
3494 | /* Print data bytes on INFO->STREAM. */ | |
3495 | ||
3496 | static void | |
3497 | print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, | |
3498 | uint32_t word, | |
561a72d4 TC |
3499 | struct disassemble_info *info, |
3500 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
3501 | { |
3502 | switch (info->bytes_per_chunk) | |
3503 | { | |
3504 | case 1: | |
3505 | info->fprintf_func (info->stream, ".byte\t0x%02x", word); | |
3506 | break; | |
3507 | case 2: | |
3508 | info->fprintf_func (info->stream, ".short\t0x%04x", word); | |
3509 | break; | |
3510 | case 4: | |
3511 | info->fprintf_func (info->stream, ".word\t0x%08x", word); | |
3512 | break; | |
3513 | default: | |
3514 | abort (); | |
3515 | } | |
3516 | } | |
3517 | ||
3518 | /* Try to infer the code or data type from a symbol. | |
3519 | Returns nonzero if *MAP_TYPE was set. */ | |
3520 | ||
3521 | static int | |
3522 | get_sym_code_type (struct disassemble_info *info, int n, | |
3523 | enum map_type *map_type) | |
3524 | { | |
ccf61261 | 3525 | asymbol * as; |
a06ea964 NC |
3526 | elf_symbol_type *es; |
3527 | unsigned int type; | |
3528 | const char *name; | |
3529 | ||
4c5ae11b RL |
3530 | /* If the symbol is in a different section, ignore it. */ |
3531 | if (info->section != NULL && info->section != info->symtab[n]->section) | |
3532 | return FALSE; | |
3533 | ||
ccf61261 NC |
3534 | if (n >= info->symtab_size) |
3535 | return FALSE; | |
3536 | ||
3537 | as = info->symtab[n]; | |
3538 | if (bfd_asymbol_flavour (as) != bfd_target_elf_flavour) | |
3539 | return FALSE; | |
3540 | es = (elf_symbol_type *) as; | |
3541 | ||
a06ea964 NC |
3542 | type = ELF_ST_TYPE (es->internal_elf_sym.st_info); |
3543 | ||
e19e9199 SP |
3544 | /* ST_TARGET_INTERNAL is set for C64. For PLT stubs, depend only on the |
3545 | mapping symbol that the linker generated for it. */ | |
3546 | if (type == STT_FUNC && !(es->symbol.flags & BSF_SYNTHETIC)) | |
a06ea964 | 3547 | { |
8b21361b | 3548 | *map_type = (es->internal_elf_sym.st_target_internal & ST_BRANCH_TO_C64 |
c900c916 | 3549 | ? MAP_TYPE_C64 : MAP_TYPE_INSN); |
a06ea964 NC |
3550 | return TRUE; |
3551 | } | |
3552 | ||
3553 | /* Check for mapping symbols. */ | |
3554 | name = bfd_asymbol_name(info->symtab[n]); | |
3555 | if (name[0] == '$' | |
3979cf50 | 3556 | && (name[1] == 'x' || name[1] == 'd' || name[1] == 'c') |
a06ea964 NC |
3557 | && (name[2] == '\0' || name[2] == '.')) |
3558 | { | |
3979cf50 SP |
3559 | switch (name[1]) |
3560 | { | |
3561 | case 'd': | |
c900c916 | 3562 | *map_type = MAP_TYPE_DATA; |
3979cf50 SP |
3563 | break; |
3564 | case 'x': | |
c900c916 | 3565 | *map_type = MAP_TYPE_INSN; |
3979cf50 SP |
3566 | break; |
3567 | case 'c': | |
c900c916 | 3568 | *map_type = MAP_TYPE_C64; |
3979cf50 SP |
3569 | break; |
3570 | default: | |
3571 | abort (); | |
3572 | } | |
a06ea964 NC |
3573 | return TRUE; |
3574 | } | |
3575 | ||
3576 | return FALSE; | |
3577 | } | |
3578 | ||
95830c98 AC |
3579 | /* Set the feature bits in arch_variant in order to get the correct disassembly |
3580 | for the chosen architecture variant. | |
3581 | ||
3582 | Currently we only restrict disassembly for Armv8-R and otherwise enable all | |
3979cf50 SP |
3583 | non-R-profile features with the exception of C64, which is set based on |
3584 | mapping symbols. */ | |
95830c98 AC |
3585 | static void |
3586 | select_aarch64_variant (unsigned mach) | |
3587 | { | |
3588 | switch (mach) | |
3589 | { | |
3590 | case bfd_mach_aarch64_8R: | |
3591 | arch_variant = AARCH64_ARCH_V8_R; | |
3592 | break; | |
3593 | default: | |
3979cf50 SP |
3594 | arch_variant = AARCH64_ANY & ~(AARCH64_FEATURE_V8_R |
3595 | | AARCH64_FEATURE_C64); | |
95830c98 AC |
3596 | } |
3597 | } | |
3598 | ||
a06ea964 NC |
3599 | /* Entry-point of the AArch64 disassembler. */ |
3600 | ||
3601 | int | |
3602 | print_insn_aarch64 (bfd_vma pc, | |
3603 | struct disassemble_info *info) | |
3604 | { | |
3605 | bfd_byte buffer[INSNLEN]; | |
3606 | int status; | |
561a72d4 TC |
3607 | void (*printer) (bfd_vma, uint32_t, struct disassemble_info *, |
3608 | aarch64_operand_error *); | |
a06ea964 NC |
3609 | bfd_boolean found = FALSE; |
3610 | unsigned int size = 4; | |
3611 | unsigned long data; | |
561a72d4 | 3612 | aarch64_operand_error errors; |
95830c98 | 3613 | static bfd_boolean set_features; |
a06ea964 NC |
3614 | |
3615 | if (info->disassembler_options) | |
3616 | { | |
3617 | set_default_aarch64_dis_options (info); | |
3618 | ||
3619 | parse_aarch64_dis_options (info->disassembler_options); | |
3620 | ||
3621 | /* To avoid repeated parsing of these options, we remove them here. */ | |
3622 | info->disassembler_options = NULL; | |
3623 | } | |
3624 | ||
95830c98 AC |
3625 | if (!set_features) |
3626 | { | |
3627 | select_aarch64_variant (info->mach); | |
3628 | set_features = TRUE; | |
3629 | } | |
3630 | ||
a06ea964 NC |
3631 | /* Aarch64 instructions are always little-endian */ |
3632 | info->endian_code = BFD_ENDIAN_LITTLE; | |
3633 | ||
c900c916 LM |
3634 | enum map_type type; |
3635 | ||
3636 | if (info->private_data != NULL) | |
3637 | { | |
3638 | struct aarch64_private_data *aarch64_data | |
3639 | = (struct aarch64_private_data *) info->private_data; | |
3640 | type = aarch64_data->instruction_type; | |
3641 | } | |
3642 | else | |
3643 | { | |
3644 | /* Default to DATA. A text section is required by the ABI to contain an | |
3645 | INSN mapping symbol at the start. A data section has no such | |
3646 | requirement, hence if no mapping symbol is found the section must | |
3647 | contain only data. This however isn't very useful if the user has | |
3648 | fully stripped the binaries. If this is the case use the section | |
3649 | attributes to determine the default. If we have no section default to | |
3650 | INSN as well, as we may be disassembling some raw bytes on a baremetal | |
3651 | HEX file or similar. */ | |
3652 | type = MAP_TYPE_DATA; | |
3653 | if ((info->section && info->section->flags & SEC_CODE) || !info->section) | |
3654 | type = last_type == MAP_TYPE_C64 ? MAP_TYPE_C64 : MAP_TYPE_INSN; | |
3655 | } | |
51457761 | 3656 | |
a06ea964 NC |
3657 | /* First check the full symtab for a mapping symbol, even if there |
3658 | are no usable non-mapping symbols for this address. */ | |
3659 | if (info->symtab_size != 0 | |
3660 | && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) | |
3661 | { | |
a06ea964 | 3662 | int last_sym = -1; |
51457761 TC |
3663 | bfd_vma addr, section_vma = 0; |
3664 | bfd_boolean can_use_search_opt_p; | |
a06ea964 NC |
3665 | int n; |
3666 | ||
3667 | if (pc <= last_mapping_addr) | |
3668 | last_mapping_sym = -1; | |
3669 | ||
3670 | /* Start scanning at the start of the function, or wherever | |
3671 | we finished last time. */ | |
3672 | n = info->symtab_pos + 1; | |
51457761 | 3673 | |
53b2f36b TC |
3674 | /* If the last stop offset is different from the current one it means we |
3675 | are disassembling a different glob of bytes. As such the optimization | |
3676 | would not be safe and we should start over. */ | |
51457761 TC |
3677 | can_use_search_opt_p = last_mapping_sym >= 0 |
3678 | && info->stop_offset == last_stop_offset; | |
3679 | ||
3680 | if (n >= last_mapping_sym && can_use_search_opt_p) | |
a06ea964 NC |
3681 | n = last_mapping_sym; |
3682 | ||
51457761 TC |
3683 | /* Look down while we haven't passed the location being disassembled. |
3684 | The reason for this is that there's no defined order between a symbol | |
3685 | and an mapping symbol that may be at the same address. We may have to | |
3686 | look at least one position ahead. */ | |
a06ea964 NC |
3687 | for (; n < info->symtab_size; n++) |
3688 | { | |
3689 | addr = bfd_asymbol_value (info->symtab[n]); | |
3690 | if (addr > pc) | |
3691 | break; | |
4c5ae11b | 3692 | if (get_sym_code_type (info, n, &type)) |
a06ea964 NC |
3693 | { |
3694 | last_sym = n; | |
3695 | found = TRUE; | |
3696 | } | |
3697 | } | |
3698 | ||
3699 | if (!found) | |
3700 | { | |
3701 | n = info->symtab_pos; | |
51457761 | 3702 | if (n >= last_mapping_sym && can_use_search_opt_p) |
a06ea964 NC |
3703 | n = last_mapping_sym; |
3704 | ||
3705 | /* No mapping symbol found at this address. Look backwards | |
51457761 TC |
3706 | for a preceeding one, but don't go pass the section start |
3707 | otherwise a data section with no mapping symbol can pick up | |
3708 | a text mapping symbol of a preceeding section. The documentation | |
3709 | says section can be NULL, in which case we will seek up all the | |
3710 | way to the top. */ | |
3711 | if (info->section) | |
3712 | section_vma = info->section->vma; | |
3713 | ||
a06ea964 NC |
3714 | for (; n >= 0; n--) |
3715 | { | |
51457761 TC |
3716 | addr = bfd_asymbol_value (info->symtab[n]); |
3717 | if (addr < section_vma) | |
3718 | break; | |
3719 | ||
a06ea964 NC |
3720 | if (get_sym_code_type (info, n, &type)) |
3721 | { | |
3722 | last_sym = n; | |
3723 | found = TRUE; | |
3724 | break; | |
3725 | } | |
3726 | } | |
3727 | } | |
3728 | ||
3729 | last_mapping_sym = last_sym; | |
3730 | last_type = type; | |
53b2f36b | 3731 | last_stop_offset = info->stop_offset; |
a06ea964 NC |
3732 | |
3733 | /* Look a little bit ahead to see if we should print out | |
3734 | less than four bytes of data. If there's a symbol, | |
3735 | mapping or otherwise, after two bytes then don't | |
3736 | print more. */ | |
c900c916 | 3737 | if (last_type == MAP_TYPE_DATA) |
a06ea964 NC |
3738 | { |
3739 | size = 4 - (pc & 3); | |
3740 | for (n = last_sym + 1; n < info->symtab_size; n++) | |
3741 | { | |
3742 | addr = bfd_asymbol_value (info->symtab[n]); | |
3743 | if (addr > pc) | |
3744 | { | |
3745 | if (addr - pc < size) | |
3746 | size = addr - pc; | |
3747 | break; | |
3748 | } | |
3749 | } | |
3750 | /* If the next symbol is after three bytes, we need to | |
3751 | print only part of the data, so that we can use either | |
3752 | .byte or .short. */ | |
3753 | if (size == 3) | |
3754 | size = (pc & 1) ? 1 : 2; | |
3755 | } | |
3756 | } | |
51457761 TC |
3757 | else |
3758 | last_type = type; | |
a06ea964 | 3759 | |
60df3720 | 3760 | /* PR 10263: Disassemble data if requested to do so by the user. */ |
c900c916 | 3761 | if (last_type == MAP_TYPE_DATA && ((info->flags & DISASSEMBLE_DATA) == 0)) |
a06ea964 NC |
3762 | { |
3763 | /* size was set above. */ | |
3764 | info->bytes_per_chunk = size; | |
3765 | info->display_endian = info->endian; | |
3766 | printer = print_insn_data; | |
3767 | } | |
3768 | else | |
3769 | { | |
3770 | info->bytes_per_chunk = size = INSNLEN; | |
3771 | info->display_endian = info->endian_code; | |
3772 | printer = print_insn_aarch64_word; | |
3773 | } | |
3774 | ||
3775 | status = (*info->read_memory_func) (pc, buffer, size, info); | |
3776 | if (status != 0) | |
3777 | { | |
3778 | (*info->memory_error_func) (status, pc, info); | |
3779 | return -1; | |
3780 | } | |
3781 | ||
3782 | data = bfd_get_bits (buffer, size * 8, | |
3783 | info->display_endian == BFD_ENDIAN_BIG); | |
3784 | ||
561a72d4 | 3785 | (*printer) (pc, data, info, &errors); |
a06ea964 NC |
3786 | |
3787 | return size; | |
3788 | } | |
3789 | \f | |
3790 | void | |
3791 | print_aarch64_disassembler_options (FILE *stream) | |
3792 | { | |
3793 | fprintf (stream, _("\n\ | |
3794 | The following AARCH64 specific disassembler options are supported for use\n\ | |
3795 | with the -M switch (multiple options should be separated by commas):\n")); | |
3796 | ||
3797 | fprintf (stream, _("\n\ | |
3798 | no-aliases Don't print instruction aliases.\n")); | |
3799 | ||
3800 | fprintf (stream, _("\n\ | |
3801 | aliases Do print instruction aliases.\n")); | |
3802 | ||
7d02540a TC |
3803 | fprintf (stream, _("\n\ |
3804 | no-notes Don't print instruction notes.\n")); | |
3805 | ||
3806 | fprintf (stream, _("\n\ | |
3807 | notes Do print instruction notes.\n")); | |
3808 | ||
a06ea964 NC |
3809 | #ifdef DEBUG_AARCH64 |
3810 | fprintf (stream, _("\n\ | |
3811 | debug_dump Temp switch for debug trace.\n")); | |
3812 | #endif /* DEBUG_AARCH64 */ | |
3813 | ||
3814 | fprintf (stream, _("\n")); | |
3815 | } |