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aarch64: Add support for MPAM system registers
[thirdparty/binutils-gdb.git] / opcodes / aarch64-opc.c
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a06ea964 1/* aarch64-opc.c -- AArch64 opcode support.
b3adc24a 2 Copyright (C) 2009-2020 Free Software Foundation, Inc.
a06ea964
NC		 3 Contributed by ARM Ltd.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21#include "sysdep.h"
22#include <assert.h>
23#include <stdlib.h>
24#include <stdio.h>
2d5d5a8f 25#include "bfd_stdint.h"
a06ea964
NC		 26#include <stdarg.h>
27#include <inttypes.h>
28
29#include "opintl.h"
245d2e3f 30#include "libiberty.h"
a06ea964
NC		 31
32#include "aarch64-opc.h"
33
34#ifdef DEBUG_AARCH64
35int debug_dump = FALSE;
36#endif /* DEBUG_AARCH64 */
37
245d2e3f
RS		 38/* The enumeration strings associated with each value of a 5-bit SVE
39 pattern operand. A null entry indicates a reserved meaning. */
40const char *const aarch64_sve_pattern_array[32] = {
41 /* 0-7. */
42 "pow2",
43 "vl1",
44 "vl2",
45 "vl3",
46 "vl4",
47 "vl5",
48 "vl6",
49 "vl7",
50 /* 8-15. */
51 "vl8",
52 "vl16",
53 "vl32",
54 "vl64",
55 "vl128",
56 "vl256",
57 0,
58 0,
59 /* 16-23. */
60 0,
61 0,
62 0,
63 0,
64 0,
65 0,
66 0,
67 0,
68 /* 24-31. */
69 0,
70 0,
71 0,
72 0,
73 0,
74 "mul4",
75 "mul3",
76 "all"
77};
78
79/* The enumeration strings associated with each value of a 4-bit SVE
80 prefetch operand. A null entry indicates a reserved meaning. */
81const char *const aarch64_sve_prfop_array[16] = {
82 /* 0-7. */
83 "pldl1keep",
84 "pldl1strm",
85 "pldl2keep",
86 "pldl2strm",
87 "pldl3keep",
88 "pldl3strm",
89 0,
90 0,
91 /* 8-15. */
92 "pstl1keep",
93 "pstl1strm",
94 "pstl2keep",
95 "pstl2strm",
96 "pstl3keep",
97 "pstl3strm",
98 0,
99 0
100};
101
a06ea964
NC		 102/* Helper functions to determine which operand to be used to encode/decode
103 the size:Q fields for AdvSIMD instructions. */
104
105static inline bfd_boolean
106vector_qualifier_p (enum aarch64_opnd_qualifier qualifier)
107{
108 return ((qualifier >= AARCH64_OPND_QLF_V_8B
109 && qualifier <= AARCH64_OPND_QLF_V_1Q) ? TRUE
110 : FALSE);
111}
112
113static inline bfd_boolean
114fp_qualifier_p (enum aarch64_opnd_qualifier qualifier)
115{
116 return ((qualifier >= AARCH64_OPND_QLF_S_B
117 && qualifier <= AARCH64_OPND_QLF_S_Q) ? TRUE
118 : FALSE);
119}
120
121enum data_pattern
122{
123 DP_UNKNOWN,
124 DP_VECTOR_3SAME,
125 DP_VECTOR_LONG,
126 DP_VECTOR_WIDE,
127 DP_VECTOR_ACROSS_LANES,
128};
129
130static const char significant_operand_index [] =
131{
132 0, /* DP_UNKNOWN, by default using operand 0. */
133 0, /* DP_VECTOR_3SAME */
134 1, /* DP_VECTOR_LONG */
135 2, /* DP_VECTOR_WIDE */
136 1, /* DP_VECTOR_ACROSS_LANES */
137};
138
139/* Given a sequence of qualifiers in QUALIFIERS, determine and return
140 the data pattern.
141 N.B. QUALIFIERS is a possible sequence of qualifiers each of which
142 corresponds to one of a sequence of operands. */
143
144static enum data_pattern
145get_data_pattern (const aarch64_opnd_qualifier_seq_t qualifiers)
146{
147 if (vector_qualifier_p (qualifiers[0]) == TRUE)
148 {
149 /* e.g. v.4s, v.4s, v.4s
150 or v.4h, v.4h, v.h[3]. */
151 if (qualifiers[0] == qualifiers[1]
152 && vector_qualifier_p (qualifiers[2]) == TRUE
153 && (aarch64_get_qualifier_esize (qualifiers[0])
154 == aarch64_get_qualifier_esize (qualifiers[1]))
155 && (aarch64_get_qualifier_esize (qualifiers[0])
156 == aarch64_get_qualifier_esize (qualifiers[2])))
157 return DP_VECTOR_3SAME;
158 /* e.g. v.8h, v.8b, v.8b.
159 or v.4s, v.4h, v.h[2].
160 or v.8h, v.16b. */
161 if (vector_qualifier_p (qualifiers[1]) == TRUE
162 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
163 && (aarch64_get_qualifier_esize (qualifiers[0])
164 == aarch64_get_qualifier_esize (qualifiers[1]) << 1))
165 return DP_VECTOR_LONG;
166 /* e.g. v.8h, v.8h, v.8b. */
167 if (qualifiers[0] == qualifiers[1]
168 && vector_qualifier_p (qualifiers[2]) == TRUE
169 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
170 && (aarch64_get_qualifier_esize (qualifiers[0])
171 == aarch64_get_qualifier_esize (qualifiers[2]) << 1)
172 && (aarch64_get_qualifier_esize (qualifiers[0])
173 == aarch64_get_qualifier_esize (qualifiers[1])))
174 return DP_VECTOR_WIDE;
175 }
176 else if (fp_qualifier_p (qualifiers[0]) == TRUE)
177 {
178 /* e.g. SADDLV <V><d>, <Vn>.<T>. */
179 if (vector_qualifier_p (qualifiers[1]) == TRUE
180 && qualifiers[2] == AARCH64_OPND_QLF_NIL)
181 return DP_VECTOR_ACROSS_LANES;
182 }
183
184 return DP_UNKNOWN;
185}
186
187/* Select the operand to do the encoding/decoding of the 'size:Q' fields in
188 the AdvSIMD instructions. */
189/* N.B. it is possible to do some optimization that doesn't call
190 get_data_pattern each time when we need to select an operand. We can
191 either buffer the caculated the result or statically generate the data,
192 however, it is not obvious that the optimization will bring significant
193 benefit. */
194
195int
196aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode)
197{
198 return
199 significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])];
200}
201\f
202const aarch64_field fields[] =
203{
204 { 0, 0 }, /* NIL. */
205 { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
206 { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
207 { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
208 { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
209 { 5, 19 }, /* imm19: e.g. in CBZ. */
210 { 5, 19 }, /* immhi: e.g. in ADRP. */
211 { 29, 2 }, /* immlo: e.g. in ADRP. */
212 { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
213 { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
214 { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
215 { 30, 1 }, /* Q: in most AdvSIMD instructions. */
216 { 0, 5 }, /* Rt: in load/store instructions. */
217 { 0, 5 }, /* Rd: in many integer instructions. */
218 { 5, 5 }, /* Rn: in many integer instructions. */
219 { 10, 5 }, /* Rt2: in load/store pair instructions. */
220 { 10, 5 }, /* Ra: in fp instructions. */
221 { 5, 3 }, /* op2: in the system instructions. */
222 { 8, 4 }, /* CRm: in the system instructions. */
223 { 12, 4 }, /* CRn: in the system instructions. */
224 { 16, 3 }, /* op1: in the system instructions. */
225 { 19, 2 }, /* op0: in the system instructions. */
226 { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
227 { 12, 4 }, /* cond: condition flags as a source operand. */
228 { 12, 4 }, /* opcode: in advsimd load/store instructions. */
229 { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
230 { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
231 { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
232 { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
233 { 16, 5 }, /* Rs: in load/store exclusive instructions. */
234 { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
235 { 12, 1 }, /* S: in load/store reg offset instructions. */
236 { 21, 2 }, /* hw: in move wide constant instructions. */
237 { 22, 2 }, /* opc: in load/store reg offset instructions. */
238 { 23, 1 }, /* opc1: in load/store reg offset instructions. */
239 { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
240 { 22, 2 }, /* type: floating point type field in fp data inst. */
241 { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
242 { 10, 6 }, /* imm6: in add/sub reg shifted instructions. */
f42f1a1d 243 { 15, 6 }, /* imm6_2: in rmif instructions. */
a06ea964 244 { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
f42f1a1d 245 { 0, 4 }, /* imm4_2: in rmif instructions. */
193614f2 246 { 10, 4 }, /* imm4_3: in adddg/subg instructions. */
a06ea964
NC		 247 { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
248 { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
249 { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
250 { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
251 { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
252 { 5, 14 }, /* imm14: in test bit and branch instructions. */
253 { 5, 16 }, /* imm16: in exception instructions. */
09c1e68a 254 { 0, 16 }, /* imm16_2: in udf instruction. */
a06ea964
NC		 255 { 0, 26 }, /* imm26: in unconditional branch instructions. */
256 { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
257 { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
258 { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
259 { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
3f06e550 260 { 22, 1 }, /* S: in LDRAA and LDRAB instructions. */
a06ea964
NC		 261 { 22, 1 }, /* N: in logical (immediate) instructions. */
262 { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
263 { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
264 { 31, 1 }, /* sf: in integer data processing instructions. */
ee804238 265 { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */
a06ea964
NC		 266 { 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
267 { 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
268 { 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
269 { 31, 1 }, /* b5: in the test bit and branch instructions. */
270 { 19, 5 }, /* b40: in the test bit and branch instructions. */
271 { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
116b6019
RS		 272 { 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
273 { 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
274 { 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
e950b345 275 { 17, 1 }, /* SVE_N: SVE equivalent of N. */
f11ad6bc
RS		 276 { 0, 4 }, /* SVE_Pd: p0-p15, bits [3,0]. */
277 { 10, 3 }, /* SVE_Pg3: p0-p7, bits [12,10]. */
278 { 5, 4 }, /* SVE_Pg4_5: p0-p15, bits [8,5]. */
279 { 10, 4 }, /* SVE_Pg4_10: p0-p15, bits [13,10]. */
280 { 16, 4 }, /* SVE_Pg4_16: p0-p15, bits [19,16]. */
281 { 16, 4 }, /* SVE_Pm: p0-p15, bits [19,16]. */
282 { 5, 4 }, /* SVE_Pn: p0-p15, bits [8,5]. */
283 { 0, 4 }, /* SVE_Pt: p0-p15, bits [3,0]. */
047cd301
RS		 284 { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
285 { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
286 { 0, 5 }, /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */
287 { 5, 5 }, /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */
288 { 5, 5 }, /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */
f11ad6bc
RS		 289 { 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
290 { 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
291 { 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
292 { 5, 5 }, /* SVE_Zm_5: SVE vector register, bits [9,5]. */
293 { 16, 5 }, /* SVE_Zm_16: SVE vector register, bits [20,16]. */
294 { 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
295 { 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
165d4950 296 { 5, 1 }, /* SVE_i1: single-bit immediate. */
582e12bf 297 { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
116adc27
MM		 298 { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
299 { 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */
31e36ab3 300 { 20, 1 }, /* SVE_i2h: high bit of 2bit immediate, bits. */
e950b345 301 { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
2442d846 302 { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
e950b345
RS		 303 { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
304 { 16, 5 }, /* SVE_imm5b: secondary 5-bit immediate field. */
4df068de 305 { 16, 6 }, /* SVE_imm6: 6-bit immediate field. */
e950b345
RS		 306 { 14, 7 }, /* SVE_imm7: 7-bit immediate field. */
307 { 5, 8 }, /* SVE_imm8: 8-bit immediate field. */
308 { 5, 9 }, /* SVE_imm9: 9-bit immediate field. */
309 { 11, 6 }, /* SVE_immr: SVE equivalent of immr. */
310 { 5, 6 }, /* SVE_imms: SVE equivalent of imms. */
4df068de 311 { 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */
245d2e3f
RS		 312 { 5, 5 }, /* SVE_pattern: vector pattern enumeration. */
313 { 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
582e12bf
RS		 314 { 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
315 { 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
adccc507 316 { 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */
116b6019 317 { 22, 1 }, /* SVE_sz: 1-bit element size select. */
3bd82c86 318 { 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */
0a57e14f 319 { 30, 1 }, /* SVE_sz2: 1-bit element size select. */
116b6019 320 { 16, 4 }, /* SVE_tsz: triangular size select. */
f11ad6bc 321 { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
116b6019
RS		 322 { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */
323 { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
4df068de 324 { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
c2c4ff8d
SN		 325 { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
326 { 11, 2 }, /* rotate1: FCMLA immediate rotate. */
327 { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
328 { 12, 1 }, /* rotate3: FCADD immediate rotate. */
f42f1a1d 329 { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
6456d318 330 { 22, 1 }, /* sz: 1-bit element size select. */
a06ea964
NC		 331};
332
333enum aarch64_operand_class
334aarch64_get_operand_class (enum aarch64_opnd type)
335{
336 return aarch64_operands[type].op_class;
337}
338
339const char *
340aarch64_get_operand_name (enum aarch64_opnd type)
341{
342 return aarch64_operands[type].name;
343}
344
345/* Get operand description string.
346 This is usually for the diagnosis purpose. */
347const char *
348aarch64_get_operand_desc (enum aarch64_opnd type)
349{
350 return aarch64_operands[type].desc;
351}
352
353/* Table of all conditional affixes. */
354const aarch64_cond aarch64_conds[16] =
355{
bb7eff52
RS		 356 {{"eq", "none"}, 0x0},
357 {{"ne", "any"}, 0x1},
358 {{"cs", "hs", "nlast"}, 0x2},
359 {{"cc", "lo", "ul", "last"}, 0x3},
360 {{"mi", "first"}, 0x4},
361 {{"pl", "nfrst"}, 0x5},
a06ea964
NC		 362 {{"vs"}, 0x6},
363 {{"vc"}, 0x7},
bb7eff52
RS		 364 {{"hi", "pmore"}, 0x8},
365 {{"ls", "plast"}, 0x9},
366 {{"ge", "tcont"}, 0xa},
367 {{"lt", "tstop"}, 0xb},
a06ea964
NC		 368 {{"gt"}, 0xc},
369 {{"le"}, 0xd},
370 {{"al"}, 0xe},
371 {{"nv"}, 0xf},
372};
373
374const aarch64_cond *
375get_cond_from_value (aarch64_insn value)
376{
377 assert (value < 16);
378 return &aarch64_conds[(unsigned int) value];
379}
380
381const aarch64_cond *
382get_inverted_cond (const aarch64_cond *cond)
383{
384 return &aarch64_conds[cond->value ^ 0x1];
385}
386
387/* Table describing the operand extension/shifting operators; indexed by
388 enum aarch64_modifier_kind.
389
390 The value column provides the most common values for encoding modifiers,
391 which enables table-driven encoding/decoding for the modifiers. */
392const struct aarch64_name_value_pair aarch64_operand_modifiers [] =
393{
394 {"none", 0x0},
395 {"msl", 0x0},
396 {"ror", 0x3},
397 {"asr", 0x2},
398 {"lsr", 0x1},
399 {"lsl", 0x0},
400 {"uxtb", 0x0},
401 {"uxth", 0x1},
402 {"uxtw", 0x2},
403 {"uxtx", 0x3},
404 {"sxtb", 0x4},
405 {"sxth", 0x5},
406 {"sxtw", 0x6},
407 {"sxtx", 0x7},
2442d846 408 {"mul", 0x0},
98907a70 409 {"mul vl", 0x0},
a06ea964
NC		 410 {NULL, 0},
411};
412
413enum aarch64_modifier_kind
414aarch64_get_operand_modifier (const struct aarch64_name_value_pair *desc)
415{
416 return desc - aarch64_operand_modifiers;
417}
418
419aarch64_insn
420aarch64_get_operand_modifier_value (enum aarch64_modifier_kind kind)
421{
422 return aarch64_operand_modifiers[kind].value;
423}
424
425enum aarch64_modifier_kind
426aarch64_get_operand_modifier_from_value (aarch64_insn value,
427 bfd_boolean extend_p)
428{
429 if (extend_p == TRUE)
430 return AARCH64_MOD_UXTB + value;
431 else
432 return AARCH64_MOD_LSL - value;
433}
434
435bfd_boolean
436aarch64_extend_operator_p (enum aarch64_modifier_kind kind)
437{
438 return (kind > AARCH64_MOD_LSL && kind <= AARCH64_MOD_SXTX)
439 ? TRUE : FALSE;
440}
441
442static inline bfd_boolean
443aarch64_shift_operator_p (enum aarch64_modifier_kind kind)
444{
445 return (kind >= AARCH64_MOD_ROR && kind <= AARCH64_MOD_LSL)
446 ? TRUE : FALSE;
447}
448
449const struct aarch64_name_value_pair aarch64_barrier_options[16] =
450{
451 { "#0x00", 0x0 },
452 { "oshld", 0x1 },
453 { "oshst", 0x2 },
454 { "osh", 0x3 },
455 { "#0x04", 0x4 },
456 { "nshld", 0x5 },
457 { "nshst", 0x6 },
458 { "nsh", 0x7 },
459 { "#0x08", 0x8 },
460 { "ishld", 0x9 },
461 { "ishst", 0xa },
462 { "ish", 0xb },
463 { "#0x0c", 0xc },
464 { "ld", 0xd },
465 { "st", 0xe },
466 { "sy", 0xf },
467};
468
9ed608f9
MW		 469/* Table describing the operands supported by the aliases of the HINT
470 instruction.
471
472 The name column is the operand that is accepted for the alias. The value
473 column is the hint number of the alias. The list of operands is terminated
474 by NULL in the name column. */
475
476const struct aarch64_name_value_pair aarch64_hint_options[] =
477{
ff605452
SD		 478 /* BTI. This is also the F_DEFAULT entry for AARCH64_OPND_BTI_TARGET. */
479 { " ", HINT_ENCODE (HINT_OPD_F_NOPRINT, 0x20) },
480 { "csync", HINT_OPD_CSYNC }, /* PSB CSYNC. */
481 { "c", HINT_OPD_C }, /* BTI C. */
482 { "j", HINT_OPD_J }, /* BTI J. */
483 { "jc", HINT_OPD_JC }, /* BTI JC. */
484 { NULL, HINT_OPD_NULL },
9ed608f9
MW		 485};
486
a32c3ff8 487/* op -> op: load = 0 instruction = 1 store = 2
a06ea964
NC		 488 l -> level: 1-3
489 t -> temporal: temporal (retained) = 0 non-temporal (streaming) = 1 */
a32c3ff8 490#define B(op,l,t) (((op) << 3) | (((l) - 1) << 1) | (t))
a06ea964
NC		 491const struct aarch64_name_value_pair aarch64_prfops[32] =
492{
493 { "pldl1keep", B(0, 1, 0) },
494 { "pldl1strm", B(0, 1, 1) },
495 { "pldl2keep", B(0, 2, 0) },
496 { "pldl2strm", B(0, 2, 1) },
497 { "pldl3keep", B(0, 3, 0) },
498 { "pldl3strm", B(0, 3, 1) },
a1ccaec9
YZ		 499 { NULL, 0x06 },
500 { NULL, 0x07 },
a32c3ff8
NC		 501 { "plil1keep", B(1, 1, 0) },
502 { "plil1strm", B(1, 1, 1) },
503 { "plil2keep", B(1, 2, 0) },
504 { "plil2strm", B(1, 2, 1) },
505 { "plil3keep", B(1, 3, 0) },
506 { "plil3strm", B(1, 3, 1) },
a1ccaec9
YZ		 507 { NULL, 0x0e },
508 { NULL, 0x0f },
a32c3ff8
NC		 509 { "pstl1keep", B(2, 1, 0) },
510 { "pstl1strm", B(2, 1, 1) },
511 { "pstl2keep", B(2, 2, 0) },
512 { "pstl2strm", B(2, 2, 1) },
513 { "pstl3keep", B(2, 3, 0) },
514 { "pstl3strm", B(2, 3, 1) },
a1ccaec9
YZ		 515 { NULL, 0x16 },
516 { NULL, 0x17 },
517 { NULL, 0x18 },
518 { NULL, 0x19 },
519 { NULL, 0x1a },
520 { NULL, 0x1b },
521 { NULL, 0x1c },
522 { NULL, 0x1d },
523 { NULL, 0x1e },
524 { NULL, 0x1f },
a06ea964
NC		 525};
526#undef B
527\f
528/* Utilities on value constraint. */
529
530static inline int
531value_in_range_p (int64_t value, int low, int high)
532{
533 return (value >= low && value <= high) ? 1 : 0;
534}
535
98907a70 536/* Return true if VALUE is a multiple of ALIGN. */
a06ea964
NC		 537static inline int
538value_aligned_p (int64_t value, int align)
539{
98907a70 540 return (value % align) == 0;
a06ea964
NC		 541}
542
543/* A signed value fits in a field. */
544static inline int
545value_fit_signed_field_p (int64_t value, unsigned width)
546{
547 assert (width < 32);
548 if (width < sizeof (value) * 8)
549 {
29298bf6 550 int64_t lim = (uint64_t) 1 << (width - 1);
a06ea964
NC		 551 if (value >= -lim && value < lim)
552 return 1;
553 }
554 return 0;
555}
556
557/* An unsigned value fits in a field. */
558static inline int
559value_fit_unsigned_field_p (int64_t value, unsigned width)
560{
561 assert (width < 32);
562 if (width < sizeof (value) * 8)
563 {
29298bf6 564 int64_t lim = (uint64_t) 1 << width;
a06ea964
NC		 565 if (value >= 0 && value < lim)
566 return 1;
567 }
568 return 0;
569}
570
571/* Return 1 if OPERAND is SP or WSP. */
572int
573aarch64_stack_pointer_p (const aarch64_opnd_info *operand)
574{
575 return ((aarch64_get_operand_class (operand->type)
576 == AARCH64_OPND_CLASS_INT_REG)
577 && operand_maybe_stack_pointer (aarch64_operands + operand->type)
578 && operand->reg.regno == 31);
579}
580
581/* Return 1 if OPERAND is XZR or WZP. */
582int
583aarch64_zero_register_p (const aarch64_opnd_info *operand)
584{
585 return ((aarch64_get_operand_class (operand->type)
586 == AARCH64_OPND_CLASS_INT_REG)
587 && !operand_maybe_stack_pointer (aarch64_operands + operand->type)
588 && operand->reg.regno == 31);
589}
590
591/* Return true if the operand *OPERAND that has the operand code
592 OPERAND->TYPE and been qualified by OPERAND->QUALIFIER can be also
593 qualified by the qualifier TARGET. */
594
595static inline int
596operand_also_qualified_p (const struct aarch64_opnd_info *operand,
597 aarch64_opnd_qualifier_t target)
598{
599 switch (operand->qualifier)
600 {
601 case AARCH64_OPND_QLF_W:
602 if (target == AARCH64_OPND_QLF_WSP && aarch64_stack_pointer_p (operand))
603 return 1;
604 break;
605 case AARCH64_OPND_QLF_X:
606 if (target == AARCH64_OPND_QLF_SP && aarch64_stack_pointer_p (operand))
607 return 1;
608 break;
609 case AARCH64_OPND_QLF_WSP:
610 if (target == AARCH64_OPND_QLF_W
611 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
612 return 1;
613 break;
614 case AARCH64_OPND_QLF_SP:
615 if (target == AARCH64_OPND_QLF_X
616 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
617 return 1;
618 break;
619 default:
620 break;
621 }
622
623 return 0;
624}
625
626/* Given qualifier sequence list QSEQ_LIST and the known qualifier KNOWN_QLF
627 for operand KNOWN_IDX, return the expected qualifier for operand IDX.
628
629 Return NIL if more than one expected qualifiers are found. */
630
631aarch64_opnd_qualifier_t
632aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *qseq_list,
633 int idx,
634 const aarch64_opnd_qualifier_t known_qlf,
635 int known_idx)
636{
637 int i, saved_i;
638
639 /* Special case.
640
641 When the known qualifier is NIL, we have to assume that there is only
642 one qualifier sequence in the *QSEQ_LIST and return the corresponding
643 qualifier directly. One scenario is that for instruction
644 PRFM <prfop>, [<Xn|SP>, #:lo12:<symbol>]
645 which has only one possible valid qualifier sequence
646 NIL, S_D
647 the caller may pass NIL in KNOWN_QLF to obtain S_D so that it can
648 determine the correct relocation type (i.e. LDST64_LO12) for PRFM.
649
650 Because the qualifier NIL has dual roles in the qualifier sequence:
651 it can mean no qualifier for the operand, or the qualifer sequence is
652 not in use (when all qualifiers in the sequence are NILs), we have to
653 handle this special case here. */
654 if (known_qlf == AARCH64_OPND_NIL)
655 {
656 assert (qseq_list[0][known_idx] == AARCH64_OPND_NIL);
657 return qseq_list[0][idx];
658 }
659
660 for (i = 0, saved_i = -1; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
661 {
662 if (qseq_list[i][known_idx] == known_qlf)
663 {
664 if (saved_i != -1)
665 /* More than one sequences are found to have KNOWN_QLF at
666 KNOWN_IDX. */
667 return AARCH64_OPND_NIL;
668 saved_i = i;
669 }
670 }
671
672 return qseq_list[saved_i][idx];
673}
674
675enum operand_qualifier_kind
676{
677 OQK_NIL,
678 OQK_OPD_VARIANT,
679 OQK_VALUE_IN_RANGE,
680 OQK_MISC,
681};
682
683/* Operand qualifier description. */
684struct operand_qualifier_data
685{
686 /* The usage of the three data fields depends on the qualifier kind. */
687 int data0;
688 int data1;
689 int data2;
690 /* Description. */
691 const char *desc;
692 /* Kind. */
693 enum operand_qualifier_kind kind;
694};
695
696/* Indexed by the operand qualifier enumerators. */
697struct operand_qualifier_data aarch64_opnd_qualifiers[] =
698{
699 {0, 0, 0, "NIL", OQK_NIL},
700
701 /* Operand variant qualifiers.
702 First 3 fields:
703 element size, number of elements and common value for encoding. */
704
705 {4, 1, 0x0, "w", OQK_OPD_VARIANT},
706 {8, 1, 0x1, "x", OQK_OPD_VARIANT},
707 {4, 1, 0x0, "wsp", OQK_OPD_VARIANT},
708 {8, 1, 0x1, "sp", OQK_OPD_VARIANT},
709
710 {1, 1, 0x0, "b", OQK_OPD_VARIANT},
711 {2, 1, 0x1, "h", OQK_OPD_VARIANT},
712 {4, 1, 0x2, "s", OQK_OPD_VARIANT},
713 {8, 1, 0x3, "d", OQK_OPD_VARIANT},
714 {16, 1, 0x4, "q", OQK_OPD_VARIANT},
66e6f0b7 715 {4, 1, 0x0, "4b", OQK_OPD_VARIANT},
df678013 716 {4, 1, 0x0, "2h", OQK_OPD_VARIANT},
a06ea964 717
a3b3345a 718 {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
a06ea964
NC		 719 {1, 8, 0x0, "8b", OQK_OPD_VARIANT},
720 {1, 16, 0x1, "16b", OQK_OPD_VARIANT},
3067d3b9 721 {2, 2, 0x0, "2h", OQK_OPD_VARIANT},
a06ea964
NC		 722 {2, 4, 0x2, "4h", OQK_OPD_VARIANT},
723 {2, 8, 0x3, "8h", OQK_OPD_VARIANT},
724 {4, 2, 0x4, "2s", OQK_OPD_VARIANT},
725 {4, 4, 0x5, "4s", OQK_OPD_VARIANT},
726 {8, 1, 0x6, "1d", OQK_OPD_VARIANT},
727 {8, 2, 0x7, "2d", OQK_OPD_VARIANT},
728 {16, 1, 0x8, "1q", OQK_OPD_VARIANT},
729
d50c751e
RS		 730 {0, 0, 0, "z", OQK_OPD_VARIANT},
731 {0, 0, 0, "m", OQK_OPD_VARIANT},
732
fb3265b3
SD		 733 /* Qualifier for scaled immediate for Tag granule (stg,st2g,etc). */
734 {16, 0, 0, "tag", OQK_OPD_VARIANT},
735
a06ea964
NC		 736 /* Qualifiers constraining the value range.
737 First 3 fields:
738 Lower bound, higher bound, unused. */
739
a6a51754 740 {0, 15, 0, "CR", OQK_VALUE_IN_RANGE},
a06ea964
NC		 741 {0, 7, 0, "imm_0_7" , OQK_VALUE_IN_RANGE},
742 {0, 15, 0, "imm_0_15", OQK_VALUE_IN_RANGE},
743 {0, 31, 0, "imm_0_31", OQK_VALUE_IN_RANGE},
744 {0, 63, 0, "imm_0_63", OQK_VALUE_IN_RANGE},
745 {1, 32, 0, "imm_1_32", OQK_VALUE_IN_RANGE},
746 {1, 64, 0, "imm_1_64", OQK_VALUE_IN_RANGE},
747
748 /* Qualifiers for miscellaneous purpose.
749 First 3 fields:
750 unused, unused and unused. */
751
752 {0, 0, 0, "lsl", 0},
753 {0, 0, 0, "msl", 0},
754
755 {0, 0, 0, "retrieving", 0},
756};
757
758static inline bfd_boolean
759operand_variant_qualifier_p (aarch64_opnd_qualifier_t qualifier)
760{
761 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_OPD_VARIANT)
762 ? TRUE : FALSE;
763}
764
765static inline bfd_boolean
766qualifier_value_in_range_constraint_p (aarch64_opnd_qualifier_t qualifier)
767{
768 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_VALUE_IN_RANGE)
769 ? TRUE : FALSE;
770}
771
772const char*
773aarch64_get_qualifier_name (aarch64_opnd_qualifier_t qualifier)
774{
775 return aarch64_opnd_qualifiers[qualifier].desc;
776}
777
778/* Given an operand qualifier, return the expected data element size
779 of a qualified operand. */
780unsigned char
781aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t qualifier)
782{
783 assert (operand_variant_qualifier_p (qualifier) == TRUE);
784 return aarch64_opnd_qualifiers[qualifier].data0;
785}
786
787unsigned char
788aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t qualifier)
789{
790 assert (operand_variant_qualifier_p (qualifier) == TRUE);
791 return aarch64_opnd_qualifiers[qualifier].data1;
792}
793
794aarch64_insn
795aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t qualifier)
796{
797 assert (operand_variant_qualifier_p (qualifier) == TRUE);
798 return aarch64_opnd_qualifiers[qualifier].data2;
799}
800
801static int
802get_lower_bound (aarch64_opnd_qualifier_t qualifier)
803{
804 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
805 return aarch64_opnd_qualifiers[qualifier].data0;
806}
807
808static int
809get_upper_bound (aarch64_opnd_qualifier_t qualifier)
810{
811 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
812 return aarch64_opnd_qualifiers[qualifier].data1;
813}
814
815#ifdef DEBUG_AARCH64
816void
817aarch64_verbose (const char *str, ...)
818{
819 va_list ap;
820 va_start (ap, str);
821 printf ("#### ");
822 vprintf (str, ap);
823 printf ("\n");
824 va_end (ap);
825}
826
827static inline void
828dump_qualifier_sequence (const aarch64_opnd_qualifier_t *qualifier)
829{
830 int i;
831 printf ("#### \t");
832 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i, ++qualifier)
833 printf ("%s,", aarch64_get_qualifier_name (*qualifier));
834 printf ("\n");
835}
836
837static void
838dump_match_qualifiers (const struct aarch64_opnd_info *opnd,
839 const aarch64_opnd_qualifier_t *qualifier)
840{
841 int i;
842 aarch64_opnd_qualifier_t curr[AARCH64_MAX_OPND_NUM];
843
844 aarch64_verbose ("dump_match_qualifiers:");
845 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
846 curr[i] = opnd[i].qualifier;
847 dump_qualifier_sequence (curr);
848 aarch64_verbose ("against");
849 dump_qualifier_sequence (qualifier);
850}
851#endif /* DEBUG_AARCH64 */
852
a68f4cd2
TC		 853/* This function checks if the given instruction INSN is a destructive
854 instruction based on the usage of the registers. It does not recognize
855 unary destructive instructions. */
856bfd_boolean
857aarch64_is_destructive_by_operands (const aarch64_opcode *opcode)
858{
859 int i = 0;
860 const enum aarch64_opnd *opnds = opcode->operands;
861
862 if (opnds[0] == AARCH64_OPND_NIL)
863 return FALSE;
864
865 while (opnds[++i] != AARCH64_OPND_NIL)
866 if (opnds[i] == opnds[0])
867 return TRUE;
868
869 return FALSE;
870}
871
a06ea964
NC		 872/* TODO improve this, we can have an extra field at the runtime to
873 store the number of operands rather than calculating it every time. */
874
875int
876aarch64_num_of_operands (const aarch64_opcode *opcode)
877{
878 int i = 0;
879 const enum aarch64_opnd *opnds = opcode->operands;
880 while (opnds[i++] != AARCH64_OPND_NIL)
881 ;
882 --i;
883 assert (i >= 0 && i <= AARCH64_MAX_OPND_NUM);
884 return i;
885}
886
887/* Find the best matched qualifier sequence in *QUALIFIERS_LIST for INST.
888 If succeeds, fill the found sequence in *RET, return 1; otherwise return 0.
889
890 N.B. on the entry, it is very likely that only some operands in *INST
891 have had their qualifiers been established.
892
893 If STOP_AT is not -1, the function will only try to match
894 the qualifier sequence for operands before and including the operand
895 of index STOP_AT; and on success *RET will only be filled with the first
896 (STOP_AT+1) qualifiers.
897
898 A couple examples of the matching algorithm:
899
900 X,W,NIL should match
901 X,W,NIL
902
903 NIL,NIL should match
904 X ,NIL
905
906 Apart from serving the main encoding routine, this can also be called
907 during or after the operand decoding. */
908
909int
910aarch64_find_best_match (const aarch64_inst *inst,
911 const aarch64_opnd_qualifier_seq_t *qualifiers_list,
912 int stop_at, aarch64_opnd_qualifier_t *ret)
913{
914 int found = 0;
915 int i, num_opnds;
916 const aarch64_opnd_qualifier_t *qualifiers;
917
918 num_opnds = aarch64_num_of_operands (inst->opcode);
919 if (num_opnds == 0)
920 {
921 DEBUG_TRACE ("SUCCEED: no operand");
922 return 1;
923 }
924
925 if (stop_at < 0 || stop_at >= num_opnds)
926 stop_at = num_opnds - 1;
927
928 /* For each pattern. */
929 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
930 {
931 int j;
932 qualifiers = *qualifiers_list;
933
934 /* Start as positive. */
935 found = 1;
936
937 DEBUG_TRACE ("%d", i);
938#ifdef DEBUG_AARCH64
939 if (debug_dump)
940 dump_match_qualifiers (inst->operands, qualifiers);
941#endif
942
943 /* Most opcodes has much fewer patterns in the list.
944 First NIL qualifier indicates the end in the list. */
945 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
946 {
947 DEBUG_TRACE_IF (i == 0, "SUCCEED: empty qualifier list");
948 if (i)
949 found = 0;
950 break;
951 }
952
953 for (j = 0; j < num_opnds && j <= stop_at; ++j, ++qualifiers)
954 {
955 if (inst->operands[j].qualifier == AARCH64_OPND_QLF_NIL)
956 {
957 /* Either the operand does not have qualifier, or the qualifier
958 for the operand needs to be deduced from the qualifier
959 sequence.
960 In the latter case, any constraint checking related with
961 the obtained qualifier should be done later in
962 operand_general_constraint_met_p. */
963 continue;
964 }
965 else if (*qualifiers != inst->operands[j].qualifier)
966 {
967 /* Unless the target qualifier can also qualify the operand
968 (which has already had a non-nil qualifier), non-equal
969 qualifiers are generally un-matched. */
970 if (operand_also_qualified_p (inst->operands + j, *qualifiers))
971 continue;
972 else
973 {
974 found = 0;
975 break;
976 }
977 }
978 else
979 continue; /* Equal qualifiers are certainly matched. */
980 }
981
982 /* Qualifiers established. */
983 if (found == 1)
984 break;
985 }
986
987 if (found == 1)
988 {
989 /* Fill the result in *RET. */
990 int j;
991 qualifiers = *qualifiers_list;
992
993 DEBUG_TRACE ("complete qualifiers using list %d", i);
994#ifdef DEBUG_AARCH64
995 if (debug_dump)
996 dump_qualifier_sequence (qualifiers);
997#endif
998
999 for (j = 0; j <= stop_at; ++j, ++qualifiers)
1000 ret[j] = *qualifiers;
1001 for (; j < AARCH64_MAX_OPND_NUM; ++j)
1002 ret[j] = AARCH64_OPND_QLF_NIL;
1003
1004 DEBUG_TRACE ("SUCCESS");
1005 return 1;
1006 }
1007
1008 DEBUG_TRACE ("FAIL");
1009 return 0;
1010}
1011
1012/* Operand qualifier matching and resolving.
1013
1014 Return 1 if the operand qualifier(s) in *INST match one of the qualifier
1015 sequences in INST->OPCODE->qualifiers_list; otherwise return 0.
1016
1017 if UPDATE_P == TRUE, update the qualifier(s) in *INST after the matching
1018 succeeds. */
1019
1020static int
1021match_operands_qualifier (aarch64_inst *inst, bfd_boolean update_p)
1022{
4989adac 1023 int i, nops;
a06ea964
NC		 1024 aarch64_opnd_qualifier_seq_t qualifiers;
1025
1026 if (!aarch64_find_best_match (inst, inst->opcode->qualifiers_list, -1,
1027 qualifiers))
1028 {
1029 DEBUG_TRACE ("matching FAIL");
1030 return 0;
1031 }
1032
4989adac
RS		 1033 if (inst->opcode->flags & F_STRICT)
1034 {
1035 /* Require an exact qualifier match, even for NIL qualifiers. */
1036 nops = aarch64_num_of_operands (inst->opcode);
1037 for (i = 0; i < nops; ++i)
1038 if (inst->operands[i].qualifier != qualifiers[i])
1039 return FALSE;
1040 }
1041
a06ea964
NC		 1042 /* Update the qualifiers. */
1043 if (update_p == TRUE)
1044 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
1045 {
1046 if (inst->opcode->operands[i] == AARCH64_OPND_NIL)
1047 break;
1048 DEBUG_TRACE_IF (inst->operands[i].qualifier != qualifiers[i],
1049 "update %s with %s for operand %d",
1050 aarch64_get_qualifier_name (inst->operands[i].qualifier),
1051 aarch64_get_qualifier_name (qualifiers[i]), i);
1052 inst->operands[i].qualifier = qualifiers[i];
1053 }
1054
1055 DEBUG_TRACE ("matching SUCCESS");
1056 return 1;
1057}
1058
1059/* Return TRUE if VALUE is a wide constant that can be moved into a general
1060 register by MOVZ.
1061
1062 IS32 indicates whether value is a 32-bit immediate or not.
1063 If SHIFT_AMOUNT is not NULL, on the return of TRUE, the logical left shift
1064 amount will be returned in *SHIFT_AMOUNT. */
1065
1066bfd_boolean
29298bf6 1067aarch64_wide_constant_p (uint64_t value, int is32, unsigned int *shift_amount)
a06ea964
NC		 1068{
1069 int amount;
1070
1071 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1072
1073 if (is32)
1074 {
1075 /* Allow all zeros or all ones in top 32-bits, so that
1076 32-bit constant expressions like ~0x80000000 are
1077 permitted. */
29298bf6 1078 if (value >> 32 != 0 && value >> 32 != 0xffffffff)
a06ea964
NC		 1079 /* Immediate out of range. */
1080 return FALSE;
29298bf6 1081 value &= 0xffffffff;
a06ea964
NC		 1082 }
1083
1084 /* first, try movz then movn */
1085 amount = -1;
29298bf6 1086 if ((value & ((uint64_t) 0xffff << 0)) == value)
a06ea964 1087 amount = 0;
29298bf6 1088 else if ((value & ((uint64_t) 0xffff << 16)) == value)
a06ea964 1089 amount = 16;
29298bf6 1090 else if (!is32 && (value & ((uint64_t) 0xffff << 32)) == value)
a06ea964 1091 amount = 32;
29298bf6 1092 else if (!is32 && (value & ((uint64_t) 0xffff << 48)) == value)
a06ea964
NC		 1093 amount = 48;
1094
1095 if (amount == -1)
1096 {
1097 DEBUG_TRACE ("exit FALSE with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1098 return FALSE;
1099 }
1100
1101 if (shift_amount != NULL)
1102 *shift_amount = amount;
1103
1104 DEBUG_TRACE ("exit TRUE with amount %d", amount);
1105
1106 return TRUE;
1107}
1108
1109/* Build the accepted values for immediate logical SIMD instructions.
1110
1111 The standard encodings of the immediate value are:
1112 N imms immr SIMD size R S
1113 1 ssssss rrrrrr 64 UInt(rrrrrr) UInt(ssssss)
1114 0 0sssss 0rrrrr 32 UInt(rrrrr) UInt(sssss)
1115 0 10ssss 00rrrr 16 UInt(rrrr) UInt(ssss)
1116 0 110sss 000rrr 8 UInt(rrr) UInt(sss)
1117 0 1110ss 0000rr 4 UInt(rr) UInt(ss)
1118 0 11110s 00000r 2 UInt(r) UInt(s)
1119 where all-ones value of S is reserved.
1120
1121 Let's call E the SIMD size.
1122
1123 The immediate value is: S+1 bits '1' rotated to the right by R.
1124
1125 The total of valid encodings is 64*63 + 32*31 + ... + 2*1 = 5334
1126 (remember S != E - 1). */
1127
1128#define TOTAL_IMM_NB 5334
1129
1130typedef struct
1131{
1132 uint64_t imm;
1133 aarch64_insn encoding;
1134} simd_imm_encoding;
1135
1136static simd_imm_encoding simd_immediates[TOTAL_IMM_NB];
1137
1138static int
1139simd_imm_encoding_cmp(const void *i1, const void *i2)
1140{
1141 const simd_imm_encoding *imm1 = (const simd_imm_encoding *)i1;
1142 const simd_imm_encoding *imm2 = (const simd_imm_encoding *)i2;
1143
1144 if (imm1->imm < imm2->imm)
1145 return -1;
1146 if (imm1->imm > imm2->imm)
1147 return +1;
1148 return 0;
1149}
1150
1151/* immediate bitfield standard encoding
1152 imm13<12> imm13<5:0> imm13<11:6> SIMD size R S
1153 1 ssssss rrrrrr 64 rrrrrr ssssss
1154 0 0sssss 0rrrrr 32 rrrrr sssss
1155 0 10ssss 00rrrr 16 rrrr ssss
1156 0 110sss 000rrr 8 rrr sss
1157 0 1110ss 0000rr 4 rr ss
1158 0 11110s 00000r 2 r s */
1159static inline int
1160encode_immediate_bitfield (int is64, uint32_t s, uint32_t r)
1161{
1162 return (is64 << 12) | (r << 6) | s;
1163}
1164
1165static void
1166build_immediate_table (void)
1167{
1168 uint32_t log_e, e, s, r, s_mask;
1169 uint64_t mask, imm;
1170 int nb_imms;
1171 int is64;
1172
1173 nb_imms = 0;
1174 for (log_e = 1; log_e <= 6; log_e++)
1175 {
1176 /* Get element size. */
1177 e = 1u << log_e;
1178 if (log_e == 6)
1179 {
1180 is64 = 1;
1181 mask = 0xffffffffffffffffull;
1182 s_mask = 0;
1183 }
1184 else
1185 {
1186 is64 = 0;
1187 mask = (1ull << e) - 1;
1188 /* log_e s_mask
1189 1 ((1 << 4) - 1) << 2 = 111100
1190 2 ((1 << 3) - 1) << 3 = 111000
1191 3 ((1 << 2) - 1) << 4 = 110000
1192 4 ((1 << 1) - 1) << 5 = 100000
1193 5 ((1 << 0) - 1) << 6 = 000000 */
1194 s_mask = ((1u << (5 - log_e)) - 1) << (log_e + 1);
1195 }
1196 for (s = 0; s < e - 1; s++)
1197 for (r = 0; r < e; r++)
1198 {
1199 /* s+1 consecutive bits to 1 (s < 63) */
1200 imm = (1ull << (s + 1)) - 1;
1201 /* rotate right by r */
1202 if (r != 0)
1203 imm = (imm >> r) | ((imm << (e - r)) & mask);
1204 /* replicate the constant depending on SIMD size */
1205 switch (log_e)
1206 {
1207 case 1: imm = (imm << 2) | imm;
1a0670f3 1208 /* Fall through. */
a06ea964 1209 case 2: imm = (imm << 4) | imm;
1a0670f3 1210 /* Fall through. */
a06ea964 1211 case 3: imm = (imm << 8) | imm;
1a0670f3 1212 /* Fall through. */
a06ea964 1213 case 4: imm = (imm << 16) | imm;
1a0670f3 1214 /* Fall through. */
a06ea964 1215 case 5: imm = (imm << 32) | imm;
1a0670f3 1216 /* Fall through. */
a06ea964
NC		 1217 case 6: break;
1218 default: abort ();
1219 }
1220 simd_immediates[nb_imms].imm = imm;
1221 simd_immediates[nb_imms].encoding =
1222 encode_immediate_bitfield(is64, s | s_mask, r);
1223 nb_imms++;
1224 }
1225 }
1226 assert (nb_imms == TOTAL_IMM_NB);
1227 qsort(simd_immediates, nb_imms,
1228 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1229}
1230
1231/* Return TRUE if VALUE is a valid logical immediate, i.e. bitmask, that can
1232 be accepted by logical (immediate) instructions
1233 e.g. ORR <Xd|SP>, <Xn>, #<imm>.
1234
42408347 1235 ESIZE is the number of bytes in the decoded immediate value.
a06ea964
NC		 1236 If ENCODING is not NULL, on the return of TRUE, the standard encoding for
1237 VALUE will be returned in *ENCODING. */
1238
1239bfd_boolean
42408347 1240aarch64_logical_immediate_p (uint64_t value, int esize, aarch64_insn *encoding)
a06ea964
NC		 1241{
1242 simd_imm_encoding imm_enc;
1243 const simd_imm_encoding *imm_encoding;
1244 static bfd_boolean initialized = FALSE;
42408347
RS		 1245 uint64_t upper;
1246 int i;
a06ea964 1247
957f6b39
TC		 1248 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 "), esize: %d", value,
1249 value, esize);
a06ea964 1250
535b785f 1251 if (!initialized)
a06ea964
NC		 1252 {
1253 build_immediate_table ();
1254 initialized = TRUE;
1255 }
1256
42408347
RS		 1257 /* Allow all zeros or all ones in top bits, so that
1258 constant expressions like ~1 are permitted. */
1259 upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
1260 if ((value & ~upper) != value && (value | upper) != value)
1261 return FALSE;
7e105031 1262
42408347
RS		 1263 /* Replicate to a full 64-bit value. */
1264 value &= ~upper;
1265 for (i = esize * 8; i < 64; i *= 2)
1266 value |= (value << i);
a06ea964
NC		 1267
1268 imm_enc.imm = value;
1269 imm_encoding = (const simd_imm_encoding *)
1270 bsearch(&imm_enc, simd_immediates, TOTAL_IMM_NB,
1271 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1272 if (imm_encoding == NULL)
1273 {
1274 DEBUG_TRACE ("exit with FALSE");
1275 return FALSE;
1276 }
1277 if (encoding != NULL)
1278 *encoding = imm_encoding->encoding;
1279 DEBUG_TRACE ("exit with TRUE");
1280 return TRUE;
1281}
1282
1283/* If 64-bit immediate IMM is in the format of
1284 "aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh",
1285 where a, b, c, d, e, f, g and h are independently 0 or 1, return an integer
1286 of value "abcdefgh". Otherwise return -1. */
1287int
1288aarch64_shrink_expanded_imm8 (uint64_t imm)
1289{
1290 int i, ret;
1291 uint32_t byte;
1292
1293 ret = 0;
1294 for (i = 0; i < 8; i++)
1295 {
1296 byte = (imm >> (8 * i)) & 0xff;
1297 if (byte == 0xff)
1298 ret |= 1 << i;
1299 else if (byte != 0x00)
1300 return -1;
1301 }
1302 return ret;
1303}
1304
1305/* Utility inline functions for operand_general_constraint_met_p. */
1306
1307static inline void
1308set_error (aarch64_operand_error *mismatch_detail,
1309 enum aarch64_operand_error_kind kind, int idx,
1310 const char* error)
1311{
1312 if (mismatch_detail == NULL)
1313 return;
1314 mismatch_detail->kind = kind;
1315 mismatch_detail->index = idx;
1316 mismatch_detail->error = error;
1317}
1318
4e50d5f8
YZ		 1319static inline void
1320set_syntax_error (aarch64_operand_error *mismatch_detail, int idx,
1321 const char* error)
1322{
1323 if (mismatch_detail == NULL)
1324 return;
1325 set_error (mismatch_detail, AARCH64_OPDE_SYNTAX_ERROR, idx, error);
1326}
1327
a06ea964
NC		 1328static inline void
1329set_out_of_range_error (aarch64_operand_error *mismatch_detail,
1330 int idx, int lower_bound, int upper_bound,
1331 const char* error)
1332{
1333 if (mismatch_detail == NULL)
1334 return;
1335 set_error (mismatch_detail, AARCH64_OPDE_OUT_OF_RANGE, idx, error);
1336 mismatch_detail->data[0] = lower_bound;
1337 mismatch_detail->data[1] = upper_bound;
1338}
1339
1340static inline void
1341set_imm_out_of_range_error (aarch64_operand_error *mismatch_detail,
1342 int idx, int lower_bound, int upper_bound)
1343{
1344 if (mismatch_detail == NULL)
1345 return;
1346 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1347 _("immediate value"));
1348}
1349
1350static inline void
1351set_offset_out_of_range_error (aarch64_operand_error *mismatch_detail,
1352 int idx, int lower_bound, int upper_bound)
1353{
1354 if (mismatch_detail == NULL)
1355 return;
1356 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1357 _("immediate offset"));
1358}
1359
1360static inline void
1361set_regno_out_of_range_error (aarch64_operand_error *mismatch_detail,
1362 int idx, int lower_bound, int upper_bound)
1363{
1364 if (mismatch_detail == NULL)
1365 return;
1366 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1367 _("register number"));
1368}
1369
1370static inline void
1371set_elem_idx_out_of_range_error (aarch64_operand_error *mismatch_detail,
1372 int idx, int lower_bound, int upper_bound)
1373{
1374 if (mismatch_detail == NULL)
1375 return;
1376 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1377 _("register element index"));
1378}
1379
1380static inline void
1381set_sft_amount_out_of_range_error (aarch64_operand_error *mismatch_detail,
1382 int idx, int lower_bound, int upper_bound)
1383{
1384 if (mismatch_detail == NULL)
1385 return;
1386 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1387 _("shift amount"));
1388}
1389
2442d846
RS		 1390/* Report that the MUL modifier in operand IDX should be in the range
1391 [LOWER_BOUND, UPPER_BOUND]. */
1392static inline void
1393set_multiplier_out_of_range_error (aarch64_operand_error *mismatch_detail,
1394 int idx, int lower_bound, int upper_bound)
1395{
1396 if (mismatch_detail == NULL)
1397 return;
1398 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1399 _("multiplier"));
1400}
1401
a06ea964
NC		 1402static inline void
1403set_unaligned_error (aarch64_operand_error *mismatch_detail, int idx,
1404 int alignment)
1405{
1406 if (mismatch_detail == NULL)
1407 return;
1408 set_error (mismatch_detail, AARCH64_OPDE_UNALIGNED, idx, NULL);
1409 mismatch_detail->data[0] = alignment;
1410}
1411
1412static inline void
1413set_reg_list_error (aarch64_operand_error *mismatch_detail, int idx,
1414 int expected_num)
1415{
1416 if (mismatch_detail == NULL)
1417 return;
1418 set_error (mismatch_detail, AARCH64_OPDE_REG_LIST, idx, NULL);
1419 mismatch_detail->data[0] = expected_num;
1420}
1421
1422static inline void
1423set_other_error (aarch64_operand_error *mismatch_detail, int idx,
1424 const char* error)
1425{
1426 if (mismatch_detail == NULL)
1427 return;
1428 set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
1429}
1430
1431/* General constraint checking based on operand code.
1432
1433 Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE
1434 as the IDXth operand of opcode OPCODE. Otherwise return 0.
1435
1436 This function has to be called after the qualifiers for all operands
1437 have been resolved.
1438
1439 Mismatching error message is returned in *MISMATCH_DETAIL upon request,
1440 i.e. when MISMATCH_DETAIL is non-NULL. This avoids the generation
1441 of error message during the disassembling where error message is not
1442 wanted. We avoid the dynamic construction of strings of error messages
1443 here (i.e. in libopcodes), as it is costly and complicated; instead, we
1444 use a combination of error code, static string and some integer data to
1445 represent an error. */
1446
1447static int
1448operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
1449 enum aarch64_opnd type,
1450 const aarch64_opcode *opcode,
1451 aarch64_operand_error *mismatch_detail)
1452{
e950b345 1453 unsigned num, modifiers, shift;
a06ea964 1454 unsigned char size;
4df068de 1455 int64_t imm, min_value, max_value;
e950b345 1456 uint64_t uvalue, mask;
a06ea964
NC		 1457 const aarch64_opnd_info *opnd = opnds + idx;
1458 aarch64_opnd_qualifier_t qualifier = opnd->qualifier;
1459
1460 assert (opcode->operands[idx] == opnd->type && opnd->type == type);
1461
1462 switch (aarch64_operands[type].op_class)
1463 {
1464 case AARCH64_OPND_CLASS_INT_REG:
ee804238
JW		 1465 /* Check pair reg constraints for cas* instructions. */
1466 if (type == AARCH64_OPND_PAIRREG)
1467 {
1468 assert (idx == 1 || idx == 3);
1469 if (opnds[idx - 1].reg.regno % 2 != 0)
1470 {
1471 set_syntax_error (mismatch_detail, idx - 1,
1472 _("reg pair must start from even reg"));
1473 return 0;
1474 }
1475 if (opnds[idx].reg.regno != opnds[idx - 1].reg.regno + 1)
1476 {
1477 set_syntax_error (mismatch_detail, idx,
1478 _("reg pair must be contiguous"));
1479 return 0;
1480 }
1481 break;
1482 }
1483
a06ea964
NC		 1484 /* <Xt> may be optional in some IC and TLBI instructions. */
1485 if (type == AARCH64_OPND_Rt_SYS)
1486 {
1487 assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
1488 == AARCH64_OPND_CLASS_SYSTEM));
ea2deeec
MW		 1489 if (opnds[1].present
1490 && !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
a06ea964
NC		 1491 {
1492 set_other_error (mismatch_detail, idx, _("extraneous register"));
1493 return 0;
1494 }
ea2deeec
MW		 1495 if (!opnds[1].present
1496 && aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
a06ea964
NC		 1497 {
1498 set_other_error (mismatch_detail, idx, _("missing register"));
1499 return 0;
1500 }
1501 }
1502 switch (qualifier)
1503 {
1504 case AARCH64_OPND_QLF_WSP:
1505 case AARCH64_OPND_QLF_SP:
1506 if (!aarch64_stack_pointer_p (opnd))
1507 {
1508 set_other_error (mismatch_detail, idx,
1509 _("stack pointer register expected"));
1510 return 0;
1511 }
1512 break;
1513 default:
1514 break;
1515 }
1516 break;
1517
f11ad6bc
RS		 1518 case AARCH64_OPND_CLASS_SVE_REG:
1519 switch (type)
1520 {
582e12bf
RS		 1521 case AARCH64_OPND_SVE_Zm3_INDEX:
1522 case AARCH64_OPND_SVE_Zm3_22_INDEX:
116adc27 1523 case AARCH64_OPND_SVE_Zm3_11_INDEX:
31e36ab3 1524 case AARCH64_OPND_SVE_Zm4_11_INDEX:
582e12bf
RS		 1525 case AARCH64_OPND_SVE_Zm4_INDEX:
1526 size = get_operand_fields_width (get_operand_from_code (type));
1527 shift = get_operand_specific_data (&aarch64_operands[type]);
1528 mask = (1 << shift) - 1;
1529 if (opnd->reg.regno > mask)
1530 {
1531 assert (mask == 7 || mask == 15);
1532 set_other_error (mismatch_detail, idx,
1533 mask == 15
1534 ? _("z0-z15 expected")
1535 : _("z0-z7 expected"));
1536 return 0;
1537 }
29298bf6 1538 mask = (1u << (size - shift)) - 1;
582e12bf
RS		 1539 if (!value_in_range_p (opnd->reglane.index, 0, mask))
1540 {
1541 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask);
1542 return 0;
1543 }
1544 break;
1545
f11ad6bc
RS		 1546 case AARCH64_OPND_SVE_Zn_INDEX:
1547 size = aarch64_get_qualifier_esize (opnd->qualifier);
1548 if (!value_in_range_p (opnd->reglane.index, 0, 64 / size - 1))
1549 {
1550 set_elem_idx_out_of_range_error (mismatch_detail, idx,
1551 0, 64 / size - 1);
1552 return 0;
1553 }
1554 break;
1555
1556 case AARCH64_OPND_SVE_ZnxN:
1557 case AARCH64_OPND_SVE_ZtxN:
1558 if (opnd->reglist.num_regs != get_opcode_dependent_value (opcode))
1559 {
1560 set_other_error (mismatch_detail, idx,
1561 _("invalid register list"));
1562 return 0;
1563 }
1564 break;
1565
1566 default:
1567 break;
1568 }
1569 break;
1570
1571 case AARCH64_OPND_CLASS_PRED_REG:
1572 if (opnd->reg.regno >= 8
1573 && get_operand_fields_width (get_operand_from_code (type)) == 3)
1574 {
1575 set_other_error (mismatch_detail, idx, _("p0-p7 expected"));
1576 return 0;
1577 }
1578 break;
1579
68a64283
YZ		 1580 case AARCH64_OPND_CLASS_COND:
1581 if (type == AARCH64_OPND_COND1
1582 && (opnds[idx].cond->value & 0xe) == 0xe)
1583 {
1584 /* Not allow AL or NV. */
1585 set_syntax_error (mismatch_detail, idx, NULL);
1586 }
1587 break;
1588
a06ea964
NC		 1589 case AARCH64_OPND_CLASS_ADDRESS:
1590 /* Check writeback. */
1591 switch (opcode->iclass)
1592 {
1593 case ldst_pos:
1594 case ldst_unscaled:
1595 case ldstnapair_offs:
1596 case ldstpair_off:
1597 case ldst_unpriv:
1598 if (opnd->addr.writeback == 1)
1599 {
4e50d5f8
YZ		 1600 set_syntax_error (mismatch_detail, idx,
1601 _("unexpected address writeback"));
a06ea964
NC		 1602 return 0;
1603 }
1604 break;
3f06e550
SN		 1605 case ldst_imm10:
1606 if (opnd->addr.writeback == 1 && opnd->addr.preind != 1)
1607 {
1608 set_syntax_error (mismatch_detail, idx,
1609 _("unexpected address writeback"));
1610 return 0;
1611 }
1612 break;
a06ea964
NC		 1613 case ldst_imm9:
1614 case ldstpair_indexed:
1615 case asisdlsep:
1616 case asisdlsop:
1617 if (opnd->addr.writeback == 0)
1618 {
4e50d5f8
YZ		 1619 set_syntax_error (mismatch_detail, idx,
1620 _("address writeback expected"));
a06ea964
NC		 1621 return 0;
1622 }
1623 break;
1624 default:
1625 assert (opnd->addr.writeback == 0);
1626 break;
1627 }
1628 switch (type)
1629 {
1630 case AARCH64_OPND_ADDR_SIMM7:
1631 /* Scaled signed 7 bits immediate offset. */
1632 /* Get the size of the data element that is accessed, which may be
1633 different from that of the source register size,
1634 e.g. in strb/ldrb. */
1635 size = aarch64_get_qualifier_esize (opnd->qualifier);
1636 if (!value_in_range_p (opnd->addr.offset.imm, -64 * size, 63 * size))
1637 {
1638 set_offset_out_of_range_error (mismatch_detail, idx,
1639 -64 * size, 63 * size);
1640 return 0;
1641 }
1642 if (!value_aligned_p (opnd->addr.offset.imm, size))
1643 {
1644 set_unaligned_error (mismatch_detail, idx, size);
1645 return 0;
1646 }
1647 break;
f42f1a1d 1648 case AARCH64_OPND_ADDR_OFFSET:
a06ea964
NC		 1649 case AARCH64_OPND_ADDR_SIMM9:
1650 /* Unscaled signed 9 bits immediate offset. */
1651 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
1652 {
1653 set_offset_out_of_range_error (mismatch_detail, idx, -256, 255);
1654 return 0;
1655 }
1656 break;
1657
1658 case AARCH64_OPND_ADDR_SIMM9_2:
1659 /* Unscaled signed 9 bits immediate offset, which has to be negative
1660 or unaligned. */
1661 size = aarch64_get_qualifier_esize (qualifier);
1662 if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
1663 && !value_aligned_p (opnd->addr.offset.imm, size))
1664 || value_in_range_p (opnd->addr.offset.imm, -256, -1))
1665 return 1;
1666 set_other_error (mismatch_detail, idx,
1667 _("negative or unaligned offset expected"));
1668 return 0;
1669
3f06e550
SN		 1670 case AARCH64_OPND_ADDR_SIMM10:
1671 /* Scaled signed 10 bits immediate offset. */
1672 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
1673 {
1674 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4088);
1675 return 0;
1676 }
1677 if (!value_aligned_p (opnd->addr.offset.imm, 8))
1678 {
1679 set_unaligned_error (mismatch_detail, idx, 8);
1680 return 0;
1681 }
1682 break;
1683
fb3265b3
SD		 1684 case AARCH64_OPND_ADDR_SIMM11:
1685 /* Signed 11 bits immediate offset (multiple of 16). */
1686 if (!value_in_range_p (opnd->addr.offset.imm, -1024, 1008))
1687 {
1688 set_offset_out_of_range_error (mismatch_detail, idx, -1024, 1008);
1689 return 0;
1690 }
1691
1692 if (!value_aligned_p (opnd->addr.offset.imm, 16))
1693 {
1694 set_unaligned_error (mismatch_detail, idx, 16);
1695 return 0;
1696 }
1697 break;
1698
1699 case AARCH64_OPND_ADDR_SIMM13:
1700 /* Signed 13 bits immediate offset (multiple of 16). */
1701 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4080))
1702 {
1703 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4080);
1704 return 0;
1705 }
1706
1707 if (!value_aligned_p (opnd->addr.offset.imm, 16))
1708 {
1709 set_unaligned_error (mismatch_detail, idx, 16);
1710 return 0;
1711 }
1712 break;
1713
a06ea964
NC		 1714 case AARCH64_OPND_SIMD_ADDR_POST:
1715 /* AdvSIMD load/store multiple structures, post-index. */
1716 assert (idx == 1);
1717 if (opnd->addr.offset.is_reg)
1718 {
1719 if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
1720 return 1;
1721 else
1722 {
1723 set_other_error (mismatch_detail, idx,
1724 _("invalid register offset"));
1725 return 0;
1726 }
1727 }
1728 else
1729 {
1730 const aarch64_opnd_info *prev = &opnds[idx-1];
1731 unsigned num_bytes; /* total number of bytes transferred. */
1732 /* The opcode dependent area stores the number of elements in
1733 each structure to be loaded/stored. */
1734 int is_ld1r = get_opcode_dependent_value (opcode) == 1;
1735 if (opcode->operands[0] == AARCH64_OPND_LVt_AL)
1736 /* Special handling of loading single structure to all lane. */
1737 num_bytes = (is_ld1r ? 1 : prev->reglist.num_regs)
1738 * aarch64_get_qualifier_esize (prev->qualifier);
1739 else
1740 num_bytes = prev->reglist.num_regs
1741 * aarch64_get_qualifier_esize (prev->qualifier)
1742 * aarch64_get_qualifier_nelem (prev->qualifier);
1743 if ((int) num_bytes != opnd->addr.offset.imm)
1744 {
1745 set_other_error (mismatch_detail, idx,
1746 _("invalid post-increment amount"));
1747 return 0;
1748 }
1749 }
1750 break;
1751
1752 case AARCH64_OPND_ADDR_REGOFF:
1753 /* Get the size of the data element that is accessed, which may be
1754 different from that of the source register size,
1755 e.g. in strb/ldrb. */
1756 size = aarch64_get_qualifier_esize (opnd->qualifier);
1757 /* It is either no shift or shift by the binary logarithm of SIZE. */
1758 if (opnd->shifter.amount != 0
1759 && opnd->shifter.amount != (int)get_logsz (size))
1760 {
1761 set_other_error (mismatch_detail, idx,
1762 _("invalid shift amount"));
1763 return 0;
1764 }
1765 /* Only UXTW, LSL, SXTW and SXTX are the accepted extending
1766 operators. */
1767 switch (opnd->shifter.kind)
1768 {
1769 case AARCH64_MOD_UXTW:
1770 case AARCH64_MOD_LSL:
1771 case AARCH64_MOD_SXTW:
1772 case AARCH64_MOD_SXTX: break;
1773 default:
1774 set_other_error (mismatch_detail, idx,
1775 _("invalid extend/shift operator"));
1776 return 0;
1777 }
1778 break;
1779
1780 case AARCH64_OPND_ADDR_UIMM12:
1781 imm = opnd->addr.offset.imm;
1782 /* Get the size of the data element that is accessed, which may be
1783 different from that of the source register size,
1784 e.g. in strb/ldrb. */
1785 size = aarch64_get_qualifier_esize (qualifier);
1786 if (!value_in_range_p (opnd->addr.offset.imm, 0, 4095 * size))
1787 {
1788 set_offset_out_of_range_error (mismatch_detail, idx,
1789 0, 4095 * size);
1790 return 0;
1791 }
9de794e1 1792 if (!value_aligned_p (opnd->addr.offset.imm, size))
a06ea964
NC		 1793 {
1794 set_unaligned_error (mismatch_detail, idx, size);
1795 return 0;
1796 }
1797 break;
1798
1799 case AARCH64_OPND_ADDR_PCREL14:
1800 case AARCH64_OPND_ADDR_PCREL19:
1801 case AARCH64_OPND_ADDR_PCREL21:
1802 case AARCH64_OPND_ADDR_PCREL26:
1803 imm = opnd->imm.value;
1804 if (operand_need_shift_by_two (get_operand_from_code (type)))
1805 {
1806 /* The offset value in a PC-relative branch instruction is alway
1807 4-byte aligned and is encoded without the lowest 2 bits. */
1808 if (!value_aligned_p (imm, 4))
1809 {
1810 set_unaligned_error (mismatch_detail, idx, 4);
1811 return 0;
1812 }
1813 /* Right shift by 2 so that we can carry out the following check
1814 canonically. */
1815 imm >>= 2;
1816 }
1817 size = get_operand_fields_width (get_operand_from_code (type));
1818 if (!value_fit_signed_field_p (imm, size))
1819 {
1820 set_other_error (mismatch_detail, idx,
1821 _("immediate out of range"));
1822 return 0;
1823 }
1824 break;
1825
98907a70
RS		 1826 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
1827 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
1828 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
1829 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
1830 min_value = -8;
1831 max_value = 7;
1832 sve_imm_offset_vl:
1833 assert (!opnd->addr.offset.is_reg);
1834 assert (opnd->addr.preind);
1835 num = 1 + get_operand_specific_data (&aarch64_operands[type]);
1836 min_value *= num;
1837 max_value *= num;
1838 if ((opnd->addr.offset.imm != 0 && !opnd->shifter.operator_present)
1839 || (opnd->shifter.operator_present
1840 && opnd->shifter.kind != AARCH64_MOD_MUL_VL))
1841 {
1842 set_other_error (mismatch_detail, idx,
1843 _("invalid addressing mode"));
1844 return 0;
1845 }
1846 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1847 {
1848 set_offset_out_of_range_error (mismatch_detail, idx,
1849 min_value, max_value);
1850 return 0;
1851 }
1852 if (!value_aligned_p (opnd->addr.offset.imm, num))
1853 {
1854 set_unaligned_error (mismatch_detail, idx, num);
1855 return 0;
1856 }
1857 break;
1858
1859 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
1860 min_value = -32;
1861 max_value = 31;
1862 goto sve_imm_offset_vl;
1863
1864 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
1865 min_value = -256;
1866 max_value = 255;
1867 goto sve_imm_offset_vl;
1868
4df068de
RS		 1869 case AARCH64_OPND_SVE_ADDR_RI_U6:
1870 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
1871 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
1872 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
1873 min_value = 0;
1874 max_value = 63;
1875 sve_imm_offset:
1876 assert (!opnd->addr.offset.is_reg);
1877 assert (opnd->addr.preind);
1878 num = 1 << get_operand_specific_data (&aarch64_operands[type]);
1879 min_value *= num;
1880 max_value *= num;
1881 if (opnd->shifter.operator_present
1882 || opnd->shifter.amount_present)
1883 {
1884 set_other_error (mismatch_detail, idx,
1885 _("invalid addressing mode"));
1886 return 0;
1887 }
1888 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1889 {
1890 set_offset_out_of_range_error (mismatch_detail, idx,
1891 min_value, max_value);
1892 return 0;
1893 }
1894 if (!value_aligned_p (opnd->addr.offset.imm, num))
1895 {
1896 set_unaligned_error (mismatch_detail, idx, num);
1897 return 0;
1898 }
1899 break;
1900
582e12bf 1901 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
8382113f 1902 case AARCH64_OPND_SVE_ADDR_RI_S4x32:
582e12bf
RS		 1903 min_value = -8;
1904 max_value = 7;
1905 goto sve_imm_offset;
1906
c469c864
MM		 1907 case AARCH64_OPND_SVE_ADDR_ZX:
1908 /* Everything is already ensured by parse_operands or
1909 aarch64_ext_sve_addr_rr_lsl (because this is a very specific
1910 argument type). */
1911 assert (opnd->addr.offset.is_reg);
1912 assert (opnd->addr.preind);
1913 assert ((aarch64_operands[type].flags & OPD_F_NO_ZR) == 0);
1914 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
1915 assert (opnd->shifter.operator_present == 0);
1916 break;
1917
c8d59609 1918 case AARCH64_OPND_SVE_ADDR_R:
4df068de
RS		 1919 case AARCH64_OPND_SVE_ADDR_RR:
1920 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
1921 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
1922 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
1923 case AARCH64_OPND_SVE_ADDR_RX:
1924 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
1925 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
1926 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
1927 case AARCH64_OPND_SVE_ADDR_RZ:
1928 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
1929 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
1930 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
1931 modifiers = 1 << AARCH64_MOD_LSL;
1932 sve_rr_operand:
1933 assert (opnd->addr.offset.is_reg);
1934 assert (opnd->addr.preind);
1935 if ((aarch64_operands[type].flags & OPD_F_NO_ZR) != 0
1936 && opnd->addr.offset.regno == 31)
1937 {
1938 set_other_error (mismatch_detail, idx,
1939 _("index register xzr is not allowed"));
1940 return 0;
1941 }
1942 if (((1 << opnd->shifter.kind) & modifiers) == 0
1943 || (opnd->shifter.amount
1944 != get_operand_specific_data (&aarch64_operands[type])))
1945 {
1946 set_other_error (mismatch_detail, idx,
1947 _("invalid addressing mode"));
1948 return 0;
1949 }
1950 break;
1951
1952 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
1953 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
1954 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
1955 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
1956 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
1957 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
1958 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
1959 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
1960 modifiers = (1 << AARCH64_MOD_SXTW) | (1 << AARCH64_MOD_UXTW);
1961 goto sve_rr_operand;
1962
1963 case AARCH64_OPND_SVE_ADDR_ZI_U5:
1964 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
1965 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
1966 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
1967 min_value = 0;
1968 max_value = 31;
1969 goto sve_imm_offset;
1970
1971 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
1972 modifiers = 1 << AARCH64_MOD_LSL;
1973 sve_zz_operand:
1974 assert (opnd->addr.offset.is_reg);
1975 assert (opnd->addr.preind);
1976 if (((1 << opnd->shifter.kind) & modifiers) == 0
1977 || opnd->shifter.amount < 0
1978 || opnd->shifter.amount > 3)
1979 {
1980 set_other_error (mismatch_detail, idx,
1981 _("invalid addressing mode"));
1982 return 0;
1983 }
1984 break;
1985
1986 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
1987 modifiers = (1 << AARCH64_MOD_SXTW);
1988 goto sve_zz_operand;
1989
1990 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
1991 modifiers = 1 << AARCH64_MOD_UXTW;
1992 goto sve_zz_operand;
1993
a06ea964
NC		 1994 default:
1995 break;
1996 }
1997 break;
1998
1999 case AARCH64_OPND_CLASS_SIMD_REGLIST:
dab26bf4
RS		 2000 if (type == AARCH64_OPND_LEt)
2001 {
2002 /* Get the upper bound for the element index. */
2003 num = 16 / aarch64_get_qualifier_esize (qualifier) - 1;
2004 if (!value_in_range_p (opnd->reglist.index, 0, num))
2005 {
2006 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2007 return 0;
2008 }
2009 }
a06ea964
NC		 2010 /* The opcode dependent area stores the number of elements in
2011 each structure to be loaded/stored. */
2012 num = get_opcode_dependent_value (opcode);
2013 switch (type)
2014 {
2015 case AARCH64_OPND_LVt:
2016 assert (num >= 1 && num <= 4);
2017 /* Unless LD1/ST1, the number of registers should be equal to that
2018 of the structure elements. */
2019 if (num != 1 && opnd->reglist.num_regs != num)
2020 {
2021 set_reg_list_error (mismatch_detail, idx, num);
2022 return 0;
2023 }
2024 break;
2025 case AARCH64_OPND_LVt_AL:
2026 case AARCH64_OPND_LEt:
2027 assert (num >= 1 && num <= 4);
2028 /* The number of registers should be equal to that of the structure
2029 elements. */
2030 if (opnd->reglist.num_regs != num)
2031 {
2032 set_reg_list_error (mismatch_detail, idx, num);
2033 return 0;
2034 }
2035 break;
2036 default:
2037 break;
2038 }
2039 break;
2040
2041 case AARCH64_OPND_CLASS_IMMEDIATE:
2042 /* Constraint check on immediate operand. */
2043 imm = opnd->imm.value;
2044 /* E.g. imm_0_31 constrains value to be 0..31. */
2045 if (qualifier_value_in_range_constraint_p (qualifier)
2046 && !value_in_range_p (imm, get_lower_bound (qualifier),
2047 get_upper_bound (qualifier)))
2048 {
2049 set_imm_out_of_range_error (mismatch_detail, idx,
2050 get_lower_bound (qualifier),
2051 get_upper_bound (qualifier));
2052 return 0;
2053 }
2054
2055 switch (type)
2056 {
2057 case AARCH64_OPND_AIMM:
2058 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2059 {
2060 set_other_error (mismatch_detail, idx,
2061 _("invalid shift operator"));
2062 return 0;
2063 }
2064 if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
2065 {
2066 set_other_error (mismatch_detail, idx,
ab3b8fcf 2067 _("shift amount must be 0 or 12"));
a06ea964
NC		 2068 return 0;
2069 }
2070 if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
2071 {
2072 set_other_error (mismatch_detail, idx,
2073 _("immediate out of range"));
2074 return 0;
2075 }
2076 break;
2077
2078 case AARCH64_OPND_HALF:
2079 assert (idx == 1 && opnds[0].type == AARCH64_OPND_Rd);
2080 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2081 {
2082 set_other_error (mismatch_detail, idx,
2083 _("invalid shift operator"));
2084 return 0;
2085 }
2086 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2087 if (!value_aligned_p (opnd->shifter.amount, 16))
2088 {
2089 set_other_error (mismatch_detail, idx,
ab3b8fcf 2090 _("shift amount must be a multiple of 16"));
a06ea964
NC		 2091 return 0;
2092 }
2093 if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
2094 {
2095 set_sft_amount_out_of_range_error (mismatch_detail, idx,
2096 0, size * 8 - 16);
2097 return 0;
2098 }
2099 if (opnd->imm.value < 0)
2100 {
2101 set_other_error (mismatch_detail, idx,
2102 _("negative immediate value not allowed"));
2103 return 0;
2104 }
2105 if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
2106 {
2107 set_other_error (mismatch_detail, idx,
2108 _("immediate out of range"));
2109 return 0;
2110 }
2111 break;
2112
2113 case AARCH64_OPND_IMM_MOV:
2114 {
42408347 2115 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
a06ea964
NC		 2116 imm = opnd->imm.value;
2117 assert (idx == 1);
2118 switch (opcode->op)
2119 {
2120 case OP_MOV_IMM_WIDEN:
2121 imm = ~imm;
1a0670f3 2122 /* Fall through. */
a06ea964 2123 case OP_MOV_IMM_WIDE:
42408347 2124 if (!aarch64_wide_constant_p (imm, esize == 4, NULL))
a06ea964
NC		 2125 {
2126 set_other_error (mismatch_detail, idx,
2127 _("immediate out of range"));
2128 return 0;
2129 }
2130 break;
2131 case OP_MOV_IMM_LOG:
42408347 2132 if (!aarch64_logical_immediate_p (imm, esize, NULL))
a06ea964
NC		 2133 {
2134 set_other_error (mismatch_detail, idx,
2135 _("immediate out of range"));
2136 return 0;
2137 }
2138 break;
2139 default:
2140 assert (0);
2141 return 0;
2142 }
2143 }
2144 break;
2145
2146 case AARCH64_OPND_NZCV:
2147 case AARCH64_OPND_CCMP_IMM:
2148 case AARCH64_OPND_EXCEPTION:
09c1e68a 2149 case AARCH64_OPND_UNDEFINED:
b83b4b13 2150 case AARCH64_OPND_TME_UIMM16:
a06ea964 2151 case AARCH64_OPND_UIMM4:
193614f2 2152 case AARCH64_OPND_UIMM4_ADDG:
a06ea964
NC		 2153 case AARCH64_OPND_UIMM7:
2154 case AARCH64_OPND_UIMM3_OP1:
2155 case AARCH64_OPND_UIMM3_OP2:
e950b345
RS		 2156 case AARCH64_OPND_SVE_UIMM3:
2157 case AARCH64_OPND_SVE_UIMM7:
2158 case AARCH64_OPND_SVE_UIMM8:
2159 case AARCH64_OPND_SVE_UIMM8_53:
a06ea964
NC		 2160 size = get_operand_fields_width (get_operand_from_code (type));
2161 assert (size < 32);
2162 if (!value_fit_unsigned_field_p (opnd->imm.value, size))
2163 {
2164 set_imm_out_of_range_error (mismatch_detail, idx, 0,
29298bf6 2165 (1u << size) - 1);
a06ea964
NC		 2166 return 0;
2167 }
2168 break;
2169
193614f2
SD		 2170 case AARCH64_OPND_UIMM10:
2171 /* Scaled unsigned 10 bits immediate offset. */
2172 if (!value_in_range_p (opnd->imm.value, 0, 1008))
2173 {
2174 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1008);
2175 return 0;
2176 }
2177
2178 if (!value_aligned_p (opnd->imm.value, 16))
2179 {
2180 set_unaligned_error (mismatch_detail, idx, 16);
2181 return 0;
2182 }
2183 break;
2184
e950b345
RS		 2185 case AARCH64_OPND_SIMM5:
2186 case AARCH64_OPND_SVE_SIMM5:
2187 case AARCH64_OPND_SVE_SIMM5B:
2188 case AARCH64_OPND_SVE_SIMM6:
2189 case AARCH64_OPND_SVE_SIMM8:
2190 size = get_operand_fields_width (get_operand_from_code (type));
2191 assert (size < 32);
2192 if (!value_fit_signed_field_p (opnd->imm.value, size))
2193 {
2194 set_imm_out_of_range_error (mismatch_detail, idx,
2195 -(1 << (size - 1)),
2196 (1 << (size - 1)) - 1);
2197 return 0;
2198 }
2199 break;
2200
a06ea964 2201 case AARCH64_OPND_WIDTH:
d685192a 2202 assert (idx > 1 && opnds[idx-1].type == AARCH64_OPND_IMM
a06ea964
NC		 2203 && opnds[0].type == AARCH64_OPND_Rd);
2204 size = get_upper_bound (qualifier);
2205 if (opnd->imm.value + opnds[idx-1].imm.value > size)
2206 /* lsb+width <= reg.size */
2207 {
2208 set_imm_out_of_range_error (mismatch_detail, idx, 1,
2209 size - opnds[idx-1].imm.value);
2210 return 0;
2211 }
2212 break;
2213
2214 case AARCH64_OPND_LIMM:
e950b345 2215 case AARCH64_OPND_SVE_LIMM:
42408347
RS		 2216 {
2217 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2218 uint64_t uimm = opnd->imm.value;
2219 if (opcode->op == OP_BIC)
2220 uimm = ~uimm;
535b785f 2221 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
42408347
RS		 2222 {
2223 set_other_error (mismatch_detail, idx,
2224 _("immediate out of range"));
2225 return 0;
2226 }
2227 }
a06ea964
NC		 2228 break;
2229
2230 case AARCH64_OPND_IMM0:
2231 case AARCH64_OPND_FPIMM0:
2232 if (opnd->imm.value != 0)
2233 {
2234 set_other_error (mismatch_detail, idx,
2235 _("immediate zero expected"));
2236 return 0;
2237 }
2238 break;
2239
c2c4ff8d
SN		 2240 case AARCH64_OPND_IMM_ROT1:
2241 case AARCH64_OPND_IMM_ROT2:
582e12bf 2242 case AARCH64_OPND_SVE_IMM_ROT2:
c2c4ff8d
SN		 2243 if (opnd->imm.value != 0
2244 && opnd->imm.value != 90
2245 && opnd->imm.value != 180
2246 && opnd->imm.value != 270)
2247 {
2248 set_other_error (mismatch_detail, idx,
2249 _("rotate expected to be 0, 90, 180 or 270"));
2250 return 0;
2251 }
2252 break;
2253
2254 case AARCH64_OPND_IMM_ROT3:
582e12bf 2255 case AARCH64_OPND_SVE_IMM_ROT1:
adccc507 2256 case AARCH64_OPND_SVE_IMM_ROT3:
c2c4ff8d
SN		 2257 if (opnd->imm.value != 90 && opnd->imm.value != 270)
2258 {
2259 set_other_error (mismatch_detail, idx,
2260 _("rotate expected to be 90 or 270"));
2261 return 0;
2262 }
2263 break;
2264
a06ea964
NC		 2265 case AARCH64_OPND_SHLL_IMM:
2266 assert (idx == 2);
2267 size = 8 * aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2268 if (opnd->imm.value != size)
2269 {
2270 set_other_error (mismatch_detail, idx,
2271 _("invalid shift amount"));
2272 return 0;
2273 }
2274 break;
2275
2276 case AARCH64_OPND_IMM_VLSL:
2277 size = aarch64_get_qualifier_esize (qualifier);
2278 if (!value_in_range_p (opnd->imm.value, 0, size * 8 - 1))
2279 {
2280 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2281 size * 8 - 1);
2282 return 0;
2283 }
2284 break;
2285
2286 case AARCH64_OPND_IMM_VLSR:
2287 size = aarch64_get_qualifier_esize (qualifier);
2288 if (!value_in_range_p (opnd->imm.value, 1, size * 8))
2289 {
2290 set_imm_out_of_range_error (mismatch_detail, idx, 1, size * 8);
2291 return 0;
2292 }
2293 break;
2294
2295 case AARCH64_OPND_SIMD_IMM:
2296 case AARCH64_OPND_SIMD_IMM_SFT:
2297 /* Qualifier check. */
2298 switch (qualifier)
2299 {
2300 case AARCH64_OPND_QLF_LSL:
2301 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2302 {
2303 set_other_error (mismatch_detail, idx,
2304 _("invalid shift operator"));
2305 return 0;
2306 }
2307 break;
2308 case AARCH64_OPND_QLF_MSL:
2309 if (opnd->shifter.kind != AARCH64_MOD_MSL)
2310 {
2311 set_other_error (mismatch_detail, idx,
2312 _("invalid shift operator"));
2313 return 0;
2314 }
2315 break;
2316 case AARCH64_OPND_QLF_NIL:
2317 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2318 {
2319 set_other_error (mismatch_detail, idx,
2320 _("shift is not permitted"));
2321 return 0;
2322 }
2323 break;
2324 default:
2325 assert (0);
2326 return 0;
2327 }
2328 /* Is the immediate valid? */
2329 assert (idx == 1);
2330 if (aarch64_get_qualifier_esize (opnds[0].qualifier) != 8)
2331 {
d2865ed3
YZ		 2332 /* uimm8 or simm8 */
2333 if (!value_in_range_p (opnd->imm.value, -128, 255))
a06ea964 2334 {
d2865ed3 2335 set_imm_out_of_range_error (mismatch_detail, idx, -128, 255);
a06ea964
NC		 2336 return 0;
2337 }
2338 }
2339 else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
2340 {
2341 /* uimm64 is not
2342 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeee
2343 ffffffffgggggggghhhhhhhh'. */
2344 set_other_error (mismatch_detail, idx,
2345 _("invalid value for immediate"));
2346 return 0;
2347 }
2348 /* Is the shift amount valid? */
2349 switch (opnd->shifter.kind)
2350 {
2351 case AARCH64_MOD_LSL:
2352 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
f5555712 2353 if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8))
a06ea964 2354 {
f5555712
YZ		 2355 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0,
2356 (size - 1) * 8);
a06ea964
NC		 2357 return 0;
2358 }
f5555712 2359 if (!value_aligned_p (opnd->shifter.amount, 8))
a06ea964 2360 {
f5555712 2361 set_unaligned_error (mismatch_detail, idx, 8);
a06ea964
NC		 2362 return 0;
2363 }
2364 break;
2365 case AARCH64_MOD_MSL:
2366 /* Only 8 and 16 are valid shift amount. */
2367 if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
2368 {
2369 set_other_error (mismatch_detail, idx,
ab3b8fcf 2370 _("shift amount must be 0 or 16"));
a06ea964
NC		 2371 return 0;
2372 }
2373 break;
2374 default:
2375 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2376 {
2377 set_other_error (mismatch_detail, idx,
2378 _("invalid shift operator"));
2379 return 0;
2380 }
2381 break;
2382 }
2383 break;
2384
2385 case AARCH64_OPND_FPIMM:
2386 case AARCH64_OPND_SIMD_FPIMM:
165d4950 2387 case AARCH64_OPND_SVE_FPIMM8:
a06ea964
NC		 2388 if (opnd->imm.is_fp == 0)
2389 {
2390 set_other_error (mismatch_detail, idx,
2391 _("floating-point immediate expected"));
2392 return 0;
2393 }
2394 /* The value is expected to be an 8-bit floating-point constant with
2395 sign, 3-bit exponent and normalized 4 bits of precision, encoded
2396 in "a:b:c:d:e:f:g:h" or FLD_imm8 (depending on the type of the
2397 instruction). */
2398 if (!value_in_range_p (opnd->imm.value, 0, 255))
2399 {
2400 set_other_error (mismatch_detail, idx,
2401 _("immediate out of range"));
2402 return 0;
2403 }
2404 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2405 {
2406 set_other_error (mismatch_detail, idx,
2407 _("invalid shift operator"));
2408 return 0;
2409 }
2410 break;
2411
e950b345
RS		 2412 case AARCH64_OPND_SVE_AIMM:
2413 min_value = 0;
2414 sve_aimm:
2415 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
2416 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2417 mask = ~((uint64_t) -1 << (size * 4) << (size * 4));
2418 uvalue = opnd->imm.value;
2419 shift = opnd->shifter.amount;
2420 if (size == 1)
2421 {
2422 if (shift != 0)
2423 {
2424 set_other_error (mismatch_detail, idx,
2425 _("no shift amount allowed for"
2426 " 8-bit constants"));
2427 return 0;
2428 }
2429 }
2430 else
2431 {
2432 if (shift != 0 && shift != 8)
2433 {
2434 set_other_error (mismatch_detail, idx,
2435 _("shift amount must be 0 or 8"));
2436 return 0;
2437 }
2438 if (shift == 0 && (uvalue & 0xff) == 0)
2439 {
2440 shift = 8;
2441 uvalue = (int64_t) uvalue / 256;
2442 }
2443 }
2444 mask >>= shift;
2445 if ((uvalue & mask) != uvalue && (uvalue | ~mask) != uvalue)
2446 {
2447 set_other_error (mismatch_detail, idx,
2448 _("immediate too big for element size"));
2449 return 0;
2450 }
2451 uvalue = (uvalue - min_value) & mask;
2452 if (uvalue > 0xff)
2453 {
2454 set_other_error (mismatch_detail, idx,
2455 _("invalid arithmetic immediate"));
2456 return 0;
2457 }
2458 break;
2459
2460 case AARCH64_OPND_SVE_ASIMM:
2461 min_value = -128;
2462 goto sve_aimm;
2463
165d4950
RS		 2464 case AARCH64_OPND_SVE_I1_HALF_ONE:
2465 assert (opnd->imm.is_fp);
2466 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x3f800000)
2467 {
2468 set_other_error (mismatch_detail, idx,
2469 _("floating-point value must be 0.5 or 1.0"));
2470 return 0;
2471 }
2472 break;
2473
2474 case AARCH64_OPND_SVE_I1_HALF_TWO:
2475 assert (opnd->imm.is_fp);
2476 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x40000000)
2477 {
2478 set_other_error (mismatch_detail, idx,
2479 _("floating-point value must be 0.5 or 2.0"));
2480 return 0;
2481 }
2482 break;
2483
2484 case AARCH64_OPND_SVE_I1_ZERO_ONE:
2485 assert (opnd->imm.is_fp);
2486 if (opnd->imm.value != 0 && opnd->imm.value != 0x3f800000)
2487 {
2488 set_other_error (mismatch_detail, idx,
2489 _("floating-point value must be 0.0 or 1.0"));
2490 return 0;
2491 }
2492 break;
2493
e950b345
RS		 2494 case AARCH64_OPND_SVE_INV_LIMM:
2495 {
2496 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2497 uint64_t uimm = ~opnd->imm.value;
2498 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2499 {
2500 set_other_error (mismatch_detail, idx,
2501 _("immediate out of range"));
2502 return 0;
2503 }
2504 }
2505 break;
2506
2507 case AARCH64_OPND_SVE_LIMM_MOV:
2508 {
2509 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2510 uint64_t uimm = opnd->imm.value;
2511 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2512 {
2513 set_other_error (mismatch_detail, idx,
2514 _("immediate out of range"));
2515 return 0;
2516 }
2517 if (!aarch64_sve_dupm_mov_immediate_p (uimm, esize))
2518 {
2519 set_other_error (mismatch_detail, idx,
2520 _("invalid replicated MOV immediate"));
2521 return 0;
2522 }
2523 }
2524 break;
2525
2442d846
RS		 2526 case AARCH64_OPND_SVE_PATTERN_SCALED:
2527 assert (opnd->shifter.kind == AARCH64_MOD_MUL);
2528 if (!value_in_range_p (opnd->shifter.amount, 1, 16))
2529 {
2530 set_multiplier_out_of_range_error (mismatch_detail, idx, 1, 16);
2531 return 0;
2532 }
2533 break;
2534
e950b345
RS		 2535 case AARCH64_OPND_SVE_SHLIMM_PRED:
2536 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
28ed815a 2537 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
e950b345
RS		 2538 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2539 if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
2540 {
2541 set_imm_out_of_range_error (mismatch_detail, idx,
2542 0, 8 * size - 1);
2543 return 0;
2544 }
2545 break;
2546
2547 case AARCH64_OPND_SVE_SHRIMM_PRED:
2548 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
3c17238b 2549 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
4f5fc85d
JB		 2550 num = (type == AARCH64_OPND_SVE_SHRIMM_UNPRED_22) ? 2 : 1;
2551 size = aarch64_get_qualifier_esize (opnds[idx - num].qualifier);
2552 if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
e950b345 2553 {
4f5fc85d
JB		 2554 set_imm_out_of_range_error (mismatch_detail, idx, 1, 8*size);
2555 return 0;
2556 }
2557 break;
e950b345 2558
a06ea964
NC		 2559 default:
2560 break;
2561 }
2562 break;
2563
a06ea964
NC		 2564 case AARCH64_OPND_CLASS_SYSTEM:
2565 switch (type)
2566 {
2567 case AARCH64_OPND_PSTATEFIELD:
2568 assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
0bff6e2d
MW		 2569 /* MSR UAO, #uimm4
2570 MSR PAN, #uimm4
104fefee 2571 MSR SSBS,#uimm4
c2825638 2572 The immediate must be #0 or #1. */
0bff6e2d 2573 if ((opnd->pstatefield == 0x03 /* UAO. */
793a1948 2574 || opnd->pstatefield == 0x04 /* PAN. */
104fefee 2575 || opnd->pstatefield == 0x19 /* SSBS. */
793a1948 2576 || opnd->pstatefield == 0x1a) /* DIT. */
c2825638
MW		 2577 && opnds[1].imm.value > 1)
2578 {
2579 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2580 return 0;
2581 }
a06ea964
NC		 2582 /* MSR SPSel, #uimm4
2583 Uses uimm4 as a control value to select the stack pointer: if
2584 bit 0 is set it selects the current exception level's stack
2585 pointer, if bit 0 is clear it selects shared EL0 stack pointer.
2586 Bits 1 to 3 of uimm4 are reserved and should be zero. */
2587 if (opnd->pstatefield == 0x05 /* spsel */ && opnds[1].imm.value > 1)
2588 {
2589 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2590 return 0;
2591 }
2592 break;
2593 default:
2594 break;
2595 }
2596 break;
2597
2598 case AARCH64_OPND_CLASS_SIMD_ELEMENT:
2599 /* Get the upper bound for the element index. */
c2c4ff8d
SN		 2600 if (opcode->op == OP_FCMLA_ELEM)
2601 /* FCMLA index range depends on the vector size of other operands
2602 and is halfed because complex numbers take two elements. */
2603 num = aarch64_get_qualifier_nelem (opnds[0].qualifier)
2604 * aarch64_get_qualifier_esize (opnds[0].qualifier) / 2;
2605 else
2606 num = 16;
2607 num = num / aarch64_get_qualifier_esize (qualifier) - 1;
66e6f0b7 2608 assert (aarch64_get_qualifier_nelem (qualifier) == 1);
c2c4ff8d 2609
a06ea964
NC		 2610 /* Index out-of-range. */
2611 if (!value_in_range_p (opnd->reglane.index, 0, num))
2612 {
2613 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2614 return 0;
2615 }
2616 /* SMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].
2617 <Vm> Is the vector register (V0-V31) or (V0-V15), whose
2618 number is encoded in "size:M:Rm":
2619 size <Vm>
2620 00 RESERVED
2621 01 0:Rm
2622 10 M:Rm
2623 11 RESERVED */
369c9167 2624 if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H
a06ea964
NC		 2625 && !value_in_range_p (opnd->reglane.regno, 0, 15))
2626 {
2627 set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
2628 return 0;
2629 }
2630 break;
2631
2632 case AARCH64_OPND_CLASS_MODIFIED_REG:
2633 assert (idx == 1 || idx == 2);
2634 switch (type)
2635 {
2636 case AARCH64_OPND_Rm_EXT:
535b785f 2637 if (!aarch64_extend_operator_p (opnd->shifter.kind)
a06ea964
NC		 2638 && opnd->shifter.kind != AARCH64_MOD_LSL)
2639 {
2640 set_other_error (mismatch_detail, idx,
2641 _("extend operator expected"));
2642 return 0;
2643 }
2644 /* It is not optional unless at least one of "Rd" or "Rn" is '11111'
2645 (i.e. SP), in which case it defaults to LSL. The LSL alias is
2646 only valid when "Rd" or "Rn" is '11111', and is preferred in that
2647 case. */
2648 if (!aarch64_stack_pointer_p (opnds + 0)
2649 && (idx != 2 || !aarch64_stack_pointer_p (opnds + 1)))
2650 {
2651 if (!opnd->shifter.operator_present)
2652 {
2653 set_other_error (mismatch_detail, idx,
2654 _("missing extend operator"));
2655 return 0;
2656 }
2657 else if (opnd->shifter.kind == AARCH64_MOD_LSL)
2658 {
2659 set_other_error (mismatch_detail, idx,
2660 _("'LSL' operator not allowed"));
2661 return 0;
2662 }
2663 }
2664 assert (opnd->shifter.operator_present /* Default to LSL. */
2665 || opnd->shifter.kind == AARCH64_MOD_LSL);
2666 if (!value_in_range_p (opnd->shifter.amount, 0, 4))
2667 {
2668 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, 4);
2669 return 0;
2670 }
2671 /* In the 64-bit form, the final register operand is written as Wm
2672 for all but the (possibly omitted) UXTX/LSL and SXTX
2673 operators.
2674 N.B. GAS allows X register to be used with any operator as a
2675 programming convenience. */
2676 if (qualifier == AARCH64_OPND_QLF_X
2677 && opnd->shifter.kind != AARCH64_MOD_LSL
2678 && opnd->shifter.kind != AARCH64_MOD_UXTX
2679 && opnd->shifter.kind != AARCH64_MOD_SXTX)
2680 {
2681 set_other_error (mismatch_detail, idx, _("W register expected"));
2682 return 0;
2683 }
2684 break;
2685
2686 case AARCH64_OPND_Rm_SFT:
2687 /* ROR is not available to the shifted register operand in
2688 arithmetic instructions. */
535b785f 2689 if (!aarch64_shift_operator_p (opnd->shifter.kind))
a06ea964
NC		 2690 {
2691 set_other_error (mismatch_detail, idx,
2692 _("shift operator expected"));
2693 return 0;
2694 }
2695 if (opnd->shifter.kind == AARCH64_MOD_ROR
2696 && opcode->iclass != log_shift)
2697 {
2698 set_other_error (mismatch_detail, idx,
2699 _("'ROR' operator not allowed"));
2700 return 0;
2701 }
2702 num = qualifier == AARCH64_OPND_QLF_W ? 31 : 63;
2703 if (!value_in_range_p (opnd->shifter.amount, 0, num))
2704 {
2705 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, num);
2706 return 0;
2707 }
2708 break;
2709
2710 default:
2711 break;
2712 }
2713 break;
2714
2715 default:
2716 break;
2717 }
2718
2719 return 1;
2720}
2721
2722/* Main entrypoint for the operand constraint checking.
2723
2724 Return 1 if operands of *INST meet the constraint applied by the operand
2725 codes and operand qualifiers; otherwise return 0 and if MISMATCH_DETAIL is
2726 not NULL, return the detail of the error in *MISMATCH_DETAIL. N.B. when
2727 adding more constraint checking, make sure MISMATCH_DETAIL->KIND is set
2728 with a proper error kind rather than AARCH64_OPDE_NIL (GAS asserts non-NIL
2729 error kind when it is notified that an instruction does not pass the check).
2730
2731 Un-determined operand qualifiers may get established during the process. */
2732
2733int
2734aarch64_match_operands_constraint (aarch64_inst *inst,
2735 aarch64_operand_error *mismatch_detail)
2736{
2737 int i;
2738
2739 DEBUG_TRACE ("enter");
2740
0c608d6b
RS		 2741 /* Check for cases where a source register needs to be the same as the
2742 destination register. Do this before matching qualifiers since if
2743 an instruction has both invalid tying and invalid qualifiers,
2744 the error about qualifiers would suggest several alternative
2745 instructions that also have invalid tying. */
2746 i = inst->opcode->tied_operand;
2747 if (i > 0 && (inst->operands[0].reg.regno != inst->operands[i].reg.regno))
2748 {
2749 if (mismatch_detail)
2750 {
2751 mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
2752 mismatch_detail->index = i;
2753 mismatch_detail->error = NULL;
2754 }
2755 return 0;
2756 }
2757
a06ea964
NC		 2758 /* Match operands' qualifier.
2759 *INST has already had qualifier establish for some, if not all, of
2760 its operands; we need to find out whether these established
2761 qualifiers match one of the qualifier sequence in
2762 INST->OPCODE->QUALIFIERS_LIST. If yes, we will assign each operand
2763 with the corresponding qualifier in such a sequence.
2764 Only basic operand constraint checking is done here; the more thorough
2765 constraint checking will carried out by operand_general_constraint_met_p,
2766 which has be to called after this in order to get all of the operands'
2767 qualifiers established. */
2768 if (match_operands_qualifier (inst, TRUE /* update_p */) == 0)
2769 {
2770 DEBUG_TRACE ("FAIL on operand qualifier matching");
2771 if (mismatch_detail)
2772 {
2773 /* Return an error type to indicate that it is the qualifier
2774 matching failure; we don't care about which operand as there
2775 are enough information in the opcode table to reproduce it. */
2776 mismatch_detail->kind = AARCH64_OPDE_INVALID_VARIANT;
2777 mismatch_detail->index = -1;
2778 mismatch_detail->error = NULL;
2779 }
2780 return 0;
2781 }
2782
2783 /* Match operands' constraint. */
2784 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2785 {
2786 enum aarch64_opnd type = inst->opcode->operands[i];
2787 if (type == AARCH64_OPND_NIL)
2788 break;
2789 if (inst->operands[i].skip)
2790 {
2791 DEBUG_TRACE ("skip the incomplete operand %d", i);
2792 continue;
2793 }
2794 if (operand_general_constraint_met_p (inst->operands, i, type,
2795 inst->opcode, mismatch_detail) == 0)
2796 {
2797 DEBUG_TRACE ("FAIL on operand %d", i);
2798 return 0;
2799 }
2800 }
2801
2802 DEBUG_TRACE ("PASS");
2803
2804 return 1;
2805}
2806
2807/* Replace INST->OPCODE with OPCODE and return the replaced OPCODE.
2808 Also updates the TYPE of each INST->OPERANDS with the corresponding
2809 value of OPCODE->OPERANDS.
2810
2811 Note that some operand qualifiers may need to be manually cleared by
2812 the caller before it further calls the aarch64_opcode_encode; by
2813 doing this, it helps the qualifier matching facilities work
2814 properly. */
2815
2816const aarch64_opcode*
2817aarch64_replace_opcode (aarch64_inst *inst, const aarch64_opcode *opcode)
2818{
2819 int i;
2820 const aarch64_opcode *old = inst->opcode;
2821
2822 inst->opcode = opcode;
2823
2824 /* Update the operand types. */
2825 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2826 {
2827 inst->operands[i].type = opcode->operands[i];
2828 if (opcode->operands[i] == AARCH64_OPND_NIL)
2829 break;
2830 }
2831
2832 DEBUG_TRACE ("replace %s with %s", old->name, opcode->name);
2833
2834 return old;
2835}
2836
2837int
2838aarch64_operand_index (const enum aarch64_opnd *operands, enum aarch64_opnd operand)
2839{
2840 int i;
2841 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2842 if (operands[i] == operand)
2843 return i;
2844 else if (operands[i] == AARCH64_OPND_NIL)
2845 break;
2846 return -1;
2847}
2848\f
72e9f319
RS		 2849/* R0...R30, followed by FOR31. */
2850#define BANK(R, FOR31) \
2851 { R (0), R (1), R (2), R (3), R (4), R (5), R (6), R (7), \
2852 R (8), R (9), R (10), R (11), R (12), R (13), R (14), R (15), \
2853 R (16), R (17), R (18), R (19), R (20), R (21), R (22), R (23), \
2854 R (24), R (25), R (26), R (27), R (28), R (29), R (30), FOR31 }
a06ea964
NC		 2855/* [0][0] 32-bit integer regs with sp Wn
2856 [0][1] 64-bit integer regs with sp Xn sf=1
2857 [1][0] 32-bit integer regs with #0 Wn
2858 [1][1] 64-bit integer regs with #0 Xn sf=1 */
2859static const char *int_reg[2][2][32] = {
72e9f319
RS		 2860#define R32(X) "w" #X
2861#define R64(X) "x" #X
2862 { BANK (R32, "wsp"), BANK (R64, "sp") },
2863 { BANK (R32, "wzr"), BANK (R64, "xzr") }
a06ea964
NC		 2864#undef R64
2865#undef R32
2866};
4df068de
RS		 2867
2868/* Names of the SVE vector registers, first with .S suffixes,
2869 then with .D suffixes. */
2870
2871static const char *sve_reg[2][32] = {
2872#define ZS(X) "z" #X ".s"
2873#define ZD(X) "z" #X ".d"
2874 BANK (ZS, ZS (31)), BANK (ZD, ZD (31))
2875#undef ZD
2876#undef ZS
2877};
72e9f319 2878#undef BANK
a06ea964
NC		 2879
2880/* Return the integer register name.
2881 if SP_REG_P is not 0, R31 is an SP reg, other R31 is the zero reg. */
2882
2883static inline const char *
2884get_int_reg_name (int regno, aarch64_opnd_qualifier_t qualifier, int sp_reg_p)
2885{
2886 const int has_zr = sp_reg_p ? 0 : 1;
2887 const int is_64 = aarch64_get_qualifier_esize (qualifier) == 4 ? 0 : 1;
2888 return int_reg[has_zr][is_64][regno];
2889}
2890
2891/* Like get_int_reg_name, but IS_64 is always 1. */
2892
2893static inline const char *
2894get_64bit_int_reg_name (int regno, int sp_reg_p)
2895{
2896 const int has_zr = sp_reg_p ? 0 : 1;
2897 return int_reg[has_zr][1][regno];
2898}
2899
01dbfe4c
RS		 2900/* Get the name of the integer offset register in OPND, using the shift type
2901 to decide whether it's a word or doubleword. */
2902
2903static inline const char *
2904get_offset_int_reg_name (const aarch64_opnd_info *opnd)
2905{
2906 switch (opnd->shifter.kind)
2907 {
2908 case AARCH64_MOD_UXTW:
2909 case AARCH64_MOD_SXTW:
2910 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_W, 0);
2911
2912 case AARCH64_MOD_LSL:
2913 case AARCH64_MOD_SXTX:
2914 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_X, 0);
2915
2916 default:
2917 abort ();
2918 }
2919}
2920
4df068de
RS		 2921/* Get the name of the SVE vector offset register in OPND, using the operand
2922 qualifier to decide whether the suffix should be .S or .D. */
2923
2924static inline const char *
2925get_addr_sve_reg_name (int regno, aarch64_opnd_qualifier_t qualifier)
2926{
2927 assert (qualifier == AARCH64_OPND_QLF_S_S
2928 || qualifier == AARCH64_OPND_QLF_S_D);
2929 return sve_reg[qualifier == AARCH64_OPND_QLF_S_D][regno];
2930}
2931
a06ea964
NC		 2932/* Types for expanding an encoded 8-bit value to a floating-point value. */
2933
2934typedef union
2935{
2936 uint64_t i;
2937 double d;
2938} double_conv_t;
2939
2940typedef union
2941{
2942 uint32_t i;
2943 float f;
2944} single_conv_t;
2945
cf86120b
MW		 2946typedef union
2947{
2948 uint32_t i;
2949 float f;
2950} half_conv_t;
2951
a06ea964
NC		 2952/* IMM8 is an 8-bit floating-point constant with sign, 3-bit exponent and
2953 normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h" or FLD_imm8
2954 (depending on the type of the instruction). IMM8 will be expanded to a
cf86120b
MW		 2955 single-precision floating-point value (SIZE == 4) or a double-precision
2956 floating-point value (SIZE == 8). A half-precision floating-point value
2957 (SIZE == 2) is expanded to a single-precision floating-point value. The
2958 expanded value is returned. */
a06ea964
NC		 2959
2960static uint64_t
cf86120b 2961expand_fp_imm (int size, uint32_t imm8)
a06ea964 2962{
57a024f4 2963 uint64_t imm = 0;
a06ea964
NC		 2964 uint32_t imm8_7, imm8_6_0, imm8_6, imm8_6_repl4;
2965
2966 imm8_7 = (imm8 >> 7) & 0x01; /* imm8<7> */
2967 imm8_6_0 = imm8 & 0x7f; /* imm8<6:0> */
2968 imm8_6 = imm8_6_0 >> 6; /* imm8<6> */
2969 imm8_6_repl4 = (imm8_6 << 3) | (imm8_6 << 2)
2970 | (imm8_6 << 1) | imm8_6; /* Replicate(imm8<6>,4) */
cf86120b 2971 if (size == 8)
a06ea964
NC		 2972 {
2973 imm = (imm8_7 << (63-32)) /* imm8<7> */
2974 | ((imm8_6 ^ 1) << (62-32)) /* NOT(imm8<6) */
2975 | (imm8_6_repl4 << (58-32)) | (imm8_6 << (57-32))
2976 | (imm8_6 << (56-32)) | (imm8_6 << (55-32)) /* Replicate(imm8<6>,7) */
2977 | (imm8_6_0 << (48-32)); /* imm8<6>:imm8<5:0> */
2978 imm <<= 32;
2979 }
cf86120b 2980 else if (size == 4 || size == 2)
a06ea964
NC		 2981 {
2982 imm = (imm8_7 << 31) /* imm8<7> */
2983 | ((imm8_6 ^ 1) << 30) /* NOT(imm8<6>) */
2984 | (imm8_6_repl4 << 26) /* Replicate(imm8<6>,4) */
2985 | (imm8_6_0 << 19); /* imm8<6>:imm8<5:0> */
2986 }
cf86120b
MW		 2987 else
2988 {
2989 /* An unsupported size. */
2990 assert (0);
2991 }
a06ea964
NC		 2992
2993 return imm;
2994}
2995
2996/* Produce the string representation of the register list operand *OPND
8a7f0c1b
RS		 2997 in the buffer pointed by BUF of size SIZE. PREFIX is the part of
2998 the register name that comes before the register number, such as "v". */
a06ea964 2999static void
8a7f0c1b
RS		 3000print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
3001 const char *prefix)
a06ea964
NC		 3002{
3003 const int num_regs = opnd->reglist.num_regs;
3004 const int first_reg = opnd->reglist.first_regno;
3005 const int last_reg = (first_reg + num_regs - 1) & 0x1f;
3006 const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
3007 char tb[8]; /* Temporary buffer. */
3008
3009 assert (opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index);
3010 assert (num_regs >= 1 && num_regs <= 4);
3011
3012 /* Prepare the index if any. */
3013 if (opnd->reglist.has_index)
1b7e3d2f
NC		 3014 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3015 snprintf (tb, 8, "[%" PRIi64 "]", (opnd->reglist.index % 100));
a06ea964
NC		 3016 else
3017 tb[0] = '\0';
3018
3019 /* The hyphenated form is preferred for disassembly if there are
3020 more than two registers in the list, and the register numbers
3021 are monotonically increasing in increments of one. */
3022 if (num_regs > 2 && last_reg > first_reg)
8a7f0c1b
RS		 3023 snprintf (buf, size, "{%s%d.%s-%s%d.%s}%s", prefix, first_reg, qlf_name,
3024 prefix, last_reg, qlf_name, tb);
a06ea964
NC		 3025 else
3026 {
3027 const int reg0 = first_reg;
3028 const int reg1 = (first_reg + 1) & 0x1f;
3029 const int reg2 = (first_reg + 2) & 0x1f;
3030 const int reg3 = (first_reg + 3) & 0x1f;
3031
3032 switch (num_regs)
3033 {
3034 case 1:
8a7f0c1b 3035 snprintf (buf, size, "{%s%d.%s}%s", prefix, reg0, qlf_name, tb);
a06ea964
NC		 3036 break;
3037 case 2:
8a7f0c1b
RS		 3038 snprintf (buf, size, "{%s%d.%s, %s%d.%s}%s", prefix, reg0, qlf_name,
3039 prefix, reg1, qlf_name, tb);
a06ea964
NC		 3040 break;
3041 case 3:
8a7f0c1b
RS		 3042 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s}%s",
3043 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
3044 prefix, reg2, qlf_name, tb);
a06ea964
NC		 3045 break;
3046 case 4:
8a7f0c1b
RS		 3047 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s, %s%d.%s}%s",
3048 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
3049 prefix, reg2, qlf_name, prefix, reg3, qlf_name, tb);
a06ea964
NC		 3050 break;
3051 }
3052 }
3053}
3054
01dbfe4c
RS		 3055/* Print the register+immediate address in OPND to BUF, which has SIZE
3056 characters. BASE is the name of the base register. */
3057
3058static void
3059print_immediate_offset_address (char *buf, size_t size,
3060 const aarch64_opnd_info *opnd,
3061 const char *base)
3062{
3063 if (opnd->addr.writeback)
3064 {
3065 if (opnd->addr.preind)
1820262b
DB		 3066 {
3067 if (opnd->type == AARCH64_OPND_ADDR_SIMM10 && !opnd->addr.offset.imm)
3068 snprintf (buf, size, "[%s]!", base);
3069 else
3070 snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
3071 }
01dbfe4c 3072 else
ad43e107 3073 snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
01dbfe4c
RS		 3074 }
3075 else
3076 {
98907a70
RS		 3077 if (opnd->shifter.operator_present)
3078 {
3079 assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
ad43e107 3080 snprintf (buf, size, "[%s, #%d, mul vl]",
98907a70
RS		 3081 base, opnd->addr.offset.imm);
3082 }
3083 else if (opnd->addr.offset.imm)
ad43e107 3084 snprintf (buf, size, "[%s, #%d]", base, opnd->addr.offset.imm);
01dbfe4c
RS		 3085 else
3086 snprintf (buf, size, "[%s]", base);
3087 }
3088}
3089
a06ea964 3090/* Produce the string representation of the register offset address operand
01dbfe4c
RS		 3091 *OPND in the buffer pointed by BUF of size SIZE. BASE and OFFSET are
3092 the names of the base and offset registers. */
a06ea964
NC		 3093static void
3094print_register_offset_address (char *buf, size_t size,
01dbfe4c
RS		 3095 const aarch64_opnd_info *opnd,
3096 const char *base, const char *offset)
a06ea964 3097{
0d2f91fe 3098 char tb[16]; /* Temporary buffer. */
a06ea964
NC		 3099 bfd_boolean print_extend_p = TRUE;
3100 bfd_boolean print_amount_p = TRUE;
3101 const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
3102
a06ea964
NC		 3103 if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
3104 || !opnd->shifter.amount_present))
3105 {
3106 /* Not print the shift/extend amount when the amount is zero and
3107 when it is not the special case of 8-bit load/store instruction. */
3108 print_amount_p = FALSE;
3109 /* Likewise, no need to print the shift operator LSL in such a
3110 situation. */
01dbfe4c 3111 if (opnd->shifter.kind == AARCH64_MOD_LSL)
a06ea964
NC		 3112 print_extend_p = FALSE;
3113 }
3114
3115 /* Prepare for the extend/shift. */
3116 if (print_extend_p)
3117 {
3118 if (print_amount_p)
ad43e107 3119 snprintf (tb, sizeof (tb), ", %s #%" PRIi64, shift_name,
1b7e3d2f
NC		 3120 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3121 (opnd->shifter.amount % 100));
a06ea964 3122 else
ad43e107 3123 snprintf (tb, sizeof (tb), ", %s", shift_name);
a06ea964
NC		 3124 }
3125 else
3126 tb[0] = '\0';
3127
ad43e107 3128 snprintf (buf, size, "[%s, %s%s]", base, offset, tb);
a06ea964
NC		 3129}
3130
3131/* Generate the string representation of the operand OPNDS[IDX] for OPCODE
3132 in *BUF. The caller should pass in the maximum size of *BUF in SIZE.
3133 PC, PCREL_P and ADDRESS are used to pass in and return information about
3134 the PC-relative address calculation, where the PC value is passed in
3135 PC. If the operand is pc-relative related, *PCREL_P (if PCREL_P non-NULL)
3136 will return 1 and *ADDRESS (if ADDRESS non-NULL) will return the
3137 calculated address; otherwise, *PCREL_P (if PCREL_P non-NULL) returns 0.
3138
3139 The function serves both the disassembler and the assembler diagnostics
3140 issuer, which is the reason why it lives in this file. */
3141
3142void
3143aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
3144 const aarch64_opcode *opcode,
3145 const aarch64_opnd_info *opnds, int idx, int *pcrel_p,
bde90be2 3146 bfd_vma *address, char** notes)
a06ea964 3147{
bb7eff52 3148 unsigned int i, num_conds;
a06ea964
NC		 3149 const char *name = NULL;
3150 const aarch64_opnd_info *opnd = opnds + idx;
3151 enum aarch64_modifier_kind kind;
245d2e3f 3152 uint64_t addr, enum_value;
a06ea964
NC		 3153
3154 buf[0] = '\0';
3155 if (pcrel_p)
3156 *pcrel_p = 0;
3157
3158 switch (opnd->type)
3159 {
3160 case AARCH64_OPND_Rd:
3161 case AARCH64_OPND_Rn:
3162 case AARCH64_OPND_Rm:
3163 case AARCH64_OPND_Rt:
3164 case AARCH64_OPND_Rt2:
3165 case AARCH64_OPND_Rs:
3166 case AARCH64_OPND_Ra:
3167 case AARCH64_OPND_Rt_SYS:
ee804238 3168 case AARCH64_OPND_PAIRREG:
047cd301 3169 case AARCH64_OPND_SVE_Rm:
a06ea964 3170 /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
de194d85 3171 the <ic_op>, therefore we use opnd->present to override the
a06ea964 3172 generic optional-ness information. */
362c0c4d
JW		 3173 if (opnd->type == AARCH64_OPND_Rt_SYS)
3174 {
3175 if (!opnd->present)
3176 break;
3177 }
a06ea964 3178 /* Omit the operand, e.g. RET. */
362c0c4d
JW		 3179 else if (optional_operand_p (opcode, idx)
3180 && (opnd->reg.regno
3181 == get_optional_operand_default_value (opcode)))
a06ea964
NC		 3182 break;
3183 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3184 || opnd->qualifier == AARCH64_OPND_QLF_X);
3185 snprintf (buf, size, "%s",
3186 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3187 break;
3188
3189 case AARCH64_OPND_Rd_SP:
3190 case AARCH64_OPND_Rn_SP:
bd7ceb8d 3191 case AARCH64_OPND_Rt_SP:
047cd301 3192 case AARCH64_OPND_SVE_Rn_SP:
c84364ec 3193 case AARCH64_OPND_Rm_SP:
a06ea964
NC		 3194 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3195 || opnd->qualifier == AARCH64_OPND_QLF_WSP
3196 || opnd->qualifier == AARCH64_OPND_QLF_X
3197 || opnd->qualifier == AARCH64_OPND_QLF_SP);
3198 snprintf (buf, size, "%s",
3199 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 1));
3200 break;
3201
3202 case AARCH64_OPND_Rm_EXT:
3203 kind = opnd->shifter.kind;
3204 assert (idx == 1 || idx == 2);
3205 if ((aarch64_stack_pointer_p (opnds)
3206 || (idx == 2 && aarch64_stack_pointer_p (opnds + 1)))
3207 && ((opnd->qualifier == AARCH64_OPND_QLF_W
3208 && opnds[0].qualifier == AARCH64_OPND_QLF_W
3209 && kind == AARCH64_MOD_UXTW)
3210 || (opnd->qualifier == AARCH64_OPND_QLF_X
3211 && kind == AARCH64_MOD_UXTX)))
3212 {
3213 /* 'LSL' is the preferred form in this case. */
3214 kind = AARCH64_MOD_LSL;
3215 if (opnd->shifter.amount == 0)
3216 {
3217 /* Shifter omitted. */
3218 snprintf (buf, size, "%s",
3219 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3220 break;
3221 }
3222 }
3223 if (opnd->shifter.amount)
2442d846 3224 snprintf (buf, size, "%s, %s #%" PRIi64,
a06ea964
NC		 3225 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3226 aarch64_operand_modifiers[kind].name,
3227 opnd->shifter.amount);
3228 else
3229 snprintf (buf, size, "%s, %s",
3230 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3231 aarch64_operand_modifiers[kind].name);
3232 break;
3233
3234 case AARCH64_OPND_Rm_SFT:
3235 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3236 || opnd->qualifier == AARCH64_OPND_QLF_X);
3237 if (opnd->shifter.amount == 0 && opnd->shifter.kind == AARCH64_MOD_LSL)
3238 snprintf (buf, size, "%s",
3239 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3240 else
2442d846 3241 snprintf (buf, size, "%s, %s #%" PRIi64,
a06ea964
NC		 3242 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3243 aarch64_operand_modifiers[opnd->shifter.kind].name,
3244 opnd->shifter.amount);
3245 break;
3246
3247 case AARCH64_OPND_Fd:
3248 case AARCH64_OPND_Fn:
3249 case AARCH64_OPND_Fm:
3250 case AARCH64_OPND_Fa:
3251 case AARCH64_OPND_Ft:
3252 case AARCH64_OPND_Ft2:
3253 case AARCH64_OPND_Sd:
3254 case AARCH64_OPND_Sn:
3255 case AARCH64_OPND_Sm:
047cd301
RS		 3256 case AARCH64_OPND_SVE_VZn:
3257 case AARCH64_OPND_SVE_Vd:
3258 case AARCH64_OPND_SVE_Vm:
3259 case AARCH64_OPND_SVE_Vn:
a06ea964
NC		 3260 snprintf (buf, size, "%s%d", aarch64_get_qualifier_name (opnd->qualifier),
3261 opnd->reg.regno);
3262 break;
3263
f42f1a1d 3264 case AARCH64_OPND_Va:
a06ea964
NC		 3265 case AARCH64_OPND_Vd:
3266 case AARCH64_OPND_Vn:
3267 case AARCH64_OPND_Vm:
3268 snprintf (buf, size, "v%d.%s", opnd->reg.regno,
3269 aarch64_get_qualifier_name (opnd->qualifier));
3270 break;
3271
3272 case AARCH64_OPND_Ed:
3273 case AARCH64_OPND_En:
3274 case AARCH64_OPND_Em:
369c9167 3275 case AARCH64_OPND_Em16:
f42f1a1d 3276 case AARCH64_OPND_SM3_IMM2:
dab26bf4 3277 snprintf (buf, size, "v%d.%s[%" PRIi64 "]", opnd->reglane.regno,
a06ea964
NC		 3278 aarch64_get_qualifier_name (opnd->qualifier),
3279 opnd->reglane.index);
3280 break;
3281
3282 case AARCH64_OPND_VdD1:
3283 case AARCH64_OPND_VnD1:
3284 snprintf (buf, size, "v%d.d[1]", opnd->reg.regno);
3285 break;
3286
3287 case AARCH64_OPND_LVn:
3288 case AARCH64_OPND_LVt:
3289 case AARCH64_OPND_LVt_AL:
3290 case AARCH64_OPND_LEt:
8a7f0c1b 3291 print_register_list (buf, size, opnd, "v");
a06ea964
NC		 3292 break;
3293
f11ad6bc
RS		 3294 case AARCH64_OPND_SVE_Pd:
3295 case AARCH64_OPND_SVE_Pg3:
3296 case AARCH64_OPND_SVE_Pg4_5:
3297 case AARCH64_OPND_SVE_Pg4_10:
3298 case AARCH64_OPND_SVE_Pg4_16:
3299 case AARCH64_OPND_SVE_Pm:
3300 case AARCH64_OPND_SVE_Pn:
3301 case AARCH64_OPND_SVE_Pt:
3302 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3303 snprintf (buf, size, "p%d", opnd->reg.regno);
d50c751e
RS		 3304 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
3305 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
3306 snprintf (buf, size, "p%d/%s", opnd->reg.regno,
3307 aarch64_get_qualifier_name (opnd->qualifier));
f11ad6bc
RS		 3308 else
3309 snprintf (buf, size, "p%d.%s", opnd->reg.regno,
3310 aarch64_get_qualifier_name (opnd->qualifier));
3311 break;
3312
3313 case AARCH64_OPND_SVE_Za_5:
3314 case AARCH64_OPND_SVE_Za_16:
3315 case AARCH64_OPND_SVE_Zd:
3316 case AARCH64_OPND_SVE_Zm_5:
3317 case AARCH64_OPND_SVE_Zm_16:
3318 case AARCH64_OPND_SVE_Zn:
3319 case AARCH64_OPND_SVE_Zt:
3320 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3321 snprintf (buf, size, "z%d", opnd->reg.regno);
3322 else
3323 snprintf (buf, size, "z%d.%s", opnd->reg.regno,
3324 aarch64_get_qualifier_name (opnd->qualifier));
3325 break;
3326
3327 case AARCH64_OPND_SVE_ZnxN:
3328 case AARCH64_OPND_SVE_ZtxN:
3329 print_register_list (buf, size, opnd, "z");
3330 break;
3331
582e12bf
RS		 3332 case AARCH64_OPND_SVE_Zm3_INDEX:
3333 case AARCH64_OPND_SVE_Zm3_22_INDEX:
116adc27 3334 case AARCH64_OPND_SVE_Zm3_11_INDEX:
31e36ab3 3335 case AARCH64_OPND_SVE_Zm4_11_INDEX:
582e12bf 3336 case AARCH64_OPND_SVE_Zm4_INDEX:
f11ad6bc
RS		 3337 case AARCH64_OPND_SVE_Zn_INDEX:
3338 snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
3339 aarch64_get_qualifier_name (opnd->qualifier),
3340 opnd->reglane.index);
3341 break;
3342
a6a51754
RL		 3343 case AARCH64_OPND_CRn:
3344 case AARCH64_OPND_CRm:
3345 snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
a06ea964
NC		 3346 break;
3347
3348 case AARCH64_OPND_IDX:
f42f1a1d 3349 case AARCH64_OPND_MASK:
a06ea964 3350 case AARCH64_OPND_IMM:
f42f1a1d 3351 case AARCH64_OPND_IMM_2:
a06ea964
NC		 3352 case AARCH64_OPND_WIDTH:
3353 case AARCH64_OPND_UIMM3_OP1:
3354 case AARCH64_OPND_UIMM3_OP2:
3355 case AARCH64_OPND_BIT_NUM:
3356 case AARCH64_OPND_IMM_VLSL:
3357 case AARCH64_OPND_IMM_VLSR:
3358 case AARCH64_OPND_SHLL_IMM:
3359 case AARCH64_OPND_IMM0:
3360 case AARCH64_OPND_IMMR:
3361 case AARCH64_OPND_IMMS:
09c1e68a 3362 case AARCH64_OPND_UNDEFINED:
a06ea964 3363 case AARCH64_OPND_FBITS:
b83b4b13 3364 case AARCH64_OPND_TME_UIMM16:
e950b345
RS		 3365 case AARCH64_OPND_SIMM5:
3366 case AARCH64_OPND_SVE_SHLIMM_PRED:
3367 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
28ed815a 3368 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
e950b345
RS		 3369 case AARCH64_OPND_SVE_SHRIMM_PRED:
3370 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
3c17238b 3371 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
e950b345
RS		 3372 case AARCH64_OPND_SVE_SIMM5:
3373 case AARCH64_OPND_SVE_SIMM5B:
3374 case AARCH64_OPND_SVE_SIMM6:
3375 case AARCH64_OPND_SVE_SIMM8:
3376 case AARCH64_OPND_SVE_UIMM3:
3377 case AARCH64_OPND_SVE_UIMM7:
3378 case AARCH64_OPND_SVE_UIMM8:
3379 case AARCH64_OPND_SVE_UIMM8_53:
c2c4ff8d
SN		 3380 case AARCH64_OPND_IMM_ROT1:
3381 case AARCH64_OPND_IMM_ROT2:
3382 case AARCH64_OPND_IMM_ROT3:
582e12bf
RS		 3383 case AARCH64_OPND_SVE_IMM_ROT1:
3384 case AARCH64_OPND_SVE_IMM_ROT2:
adccc507 3385 case AARCH64_OPND_SVE_IMM_ROT3:
a06ea964
NC		 3386 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3387 break;
3388
165d4950
RS		 3389 case AARCH64_OPND_SVE_I1_HALF_ONE:
3390 case AARCH64_OPND_SVE_I1_HALF_TWO:
3391 case AARCH64_OPND_SVE_I1_ZERO_ONE:
3392 {
3393 single_conv_t c;
3394 c.i = opnd->imm.value;
3395 snprintf (buf, size, "#%.1f", c.f);
3396 break;
3397 }
3398
245d2e3f
RS		 3399 case AARCH64_OPND_SVE_PATTERN:
3400 if (optional_operand_p (opcode, idx)
3401 && opnd->imm.value == get_optional_operand_default_value (opcode))
3402 break;
3403 enum_value = opnd->imm.value;
3404 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3405 if (aarch64_sve_pattern_array[enum_value])
3406 snprintf (buf, size, "%s", aarch64_sve_pattern_array[enum_value]);
3407 else
3408 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3409 break;
3410
2442d846
RS		 3411 case AARCH64_OPND_SVE_PATTERN_SCALED:
3412 if (optional_operand_p (opcode, idx)
3413 && !opnd->shifter.operator_present
3414 && opnd->imm.value == get_optional_operand_default_value (opcode))
3415 break;
3416 enum_value = opnd->imm.value;
3417 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3418 if (aarch64_sve_pattern_array[opnd->imm.value])
3419 snprintf (buf, size, "%s", aarch64_sve_pattern_array[opnd->imm.value]);
3420 else
3421 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3422 if (opnd->shifter.operator_present)
3423 {
3424 size_t len = strlen (buf);
3425 snprintf (buf + len, size - len, ", %s #%" PRIi64,
3426 aarch64_operand_modifiers[opnd->shifter.kind].name,
3427 opnd->shifter.amount);
3428 }
3429 break;
3430
245d2e3f
RS		 3431 case AARCH64_OPND_SVE_PRFOP:
3432 enum_value = opnd->imm.value;
3433 assert (enum_value < ARRAY_SIZE (aarch64_sve_prfop_array));
3434 if (aarch64_sve_prfop_array[enum_value])
3435 snprintf (buf, size, "%s", aarch64_sve_prfop_array[enum_value]);
3436 else
3437 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3438 break;
3439
fb098a1e
YZ		 3440 case AARCH64_OPND_IMM_MOV:
3441 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3442 {
3443 case 4: /* e.g. MOV Wd, #<imm32>. */
3444 {
3445 int imm32 = opnd->imm.value;
3446 snprintf (buf, size, "#0x%-20x\t// #%d", imm32, imm32);
3447 }
3448 break;
3449 case 8: /* e.g. MOV Xd, #<imm64>. */
3450 snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64,
3451 opnd->imm.value, opnd->imm.value);
3452 break;
3453 default: assert (0);
3454 }
3455 break;
3456
a06ea964
NC		 3457 case AARCH64_OPND_FPIMM0:
3458 snprintf (buf, size, "#0.0");
3459 break;
3460
3461 case AARCH64_OPND_LIMM:
3462 case AARCH64_OPND_AIMM:
3463 case AARCH64_OPND_HALF:
e950b345
RS		 3464 case AARCH64_OPND_SVE_INV_LIMM:
3465 case AARCH64_OPND_SVE_LIMM:
3466 case AARCH64_OPND_SVE_LIMM_MOV:
a06ea964 3467 if (opnd->shifter.amount)
2442d846 3468 snprintf (buf, size, "#0x%" PRIx64 ", lsl #%" PRIi64, opnd->imm.value,
a06ea964
NC		 3469 opnd->shifter.amount);
3470 else
3471 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3472 break;
3473
3474 case AARCH64_OPND_SIMD_IMM:
3475 case AARCH64_OPND_SIMD_IMM_SFT:
3476 if ((! opnd->shifter.amount && opnd->shifter.kind == AARCH64_MOD_LSL)
3477 || opnd->shifter.kind == AARCH64_MOD_NONE)
3478 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3479 else
2442d846 3480 snprintf (buf, size, "#0x%" PRIx64 ", %s #%" PRIi64, opnd->imm.value,
a06ea964
NC		 3481 aarch64_operand_modifiers[opnd->shifter.kind].name,
3482 opnd->shifter.amount);
3483 break;
3484
e950b345
RS		 3485 case AARCH64_OPND_SVE_AIMM:
3486 case AARCH64_OPND_SVE_ASIMM:
3487 if (opnd->shifter.amount)
3488 snprintf (buf, size, "#%" PRIi64 ", lsl #%" PRIi64, opnd->imm.value,
3489 opnd->shifter.amount);
3490 else
3491 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3492 break;
3493
a06ea964
NC		 3494 case AARCH64_OPND_FPIMM:
3495 case AARCH64_OPND_SIMD_FPIMM:
165d4950 3496 case AARCH64_OPND_SVE_FPIMM8:
a06ea964
NC		 3497 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3498 {
cf86120b
MW		 3499 case 2: /* e.g. FMOV <Hd>, #<imm>. */
3500 {
3501 half_conv_t c;
3502 c.i = expand_fp_imm (2, opnd->imm.value);
3503 snprintf (buf, size, "#%.18e", c.f);
3504 }
3505 break;
a06ea964
NC		 3506 case 4: /* e.g. FMOV <Vd>.4S, #<imm>. */
3507 {
3508 single_conv_t c;
cf86120b 3509 c.i = expand_fp_imm (4, opnd->imm.value);
a06ea964
NC		 3510 snprintf (buf, size, "#%.18e", c.f);
3511 }
3512 break;
3513 case 8: /* e.g. FMOV <Sd>, #<imm>. */
3514 {
3515 double_conv_t c;
cf86120b 3516 c.i = expand_fp_imm (8, opnd->imm.value);
a06ea964
NC		 3517 snprintf (buf, size, "#%.18e", c.d);
3518 }
3519 break;
3520 default: assert (0);
3521 }
3522 break;
3523
3524 case AARCH64_OPND_CCMP_IMM:
3525 case AARCH64_OPND_NZCV:
3526 case AARCH64_OPND_EXCEPTION:
3527 case AARCH64_OPND_UIMM4:
193614f2 3528 case AARCH64_OPND_UIMM4_ADDG:
a06ea964 3529 case AARCH64_OPND_UIMM7:
193614f2 3530 case AARCH64_OPND_UIMM10:
a06ea964
NC		 3531 if (optional_operand_p (opcode, idx) == TRUE
3532 && (opnd->imm.value ==
3533 (int64_t) get_optional_operand_default_value (opcode)))
3534 /* Omit the operand, e.g. DCPS1. */
3535 break;
3536 snprintf (buf, size, "#0x%x", (unsigned int)opnd->imm.value);
3537 break;
3538
3539 case AARCH64_OPND_COND:
68a64283 3540 case AARCH64_OPND_COND1:
a06ea964 3541 snprintf (buf, size, "%s", opnd->cond->names[0]);
bb7eff52
RS		 3542 num_conds = ARRAY_SIZE (opnd->cond->names);
3543 for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
3544 {
3545 size_t len = strlen (buf);
3546 if (i == 1)
3547 snprintf (buf + len, size - len, " // %s = %s",
3548 opnd->cond->names[0], opnd->cond->names[i]);
3549 else
3550 snprintf (buf + len, size - len, ", %s",
3551 opnd->cond->names[i]);
3552 }
a06ea964
NC		 3553 break;
3554
3555 case AARCH64_OPND_ADDR_ADRP:
3556 addr = ((pc + AARCH64_PCREL_OFFSET) & ~(uint64_t)0xfff)
3557 + opnd->imm.value;
3558 if (pcrel_p)
3559 *pcrel_p = 1;
3560 if (address)
3561 *address = addr;
3562 /* This is not necessary during the disassembling, as print_address_func
3563 in the disassemble_info will take care of the printing. But some
3564 other callers may be still interested in getting the string in *STR,
3565 so here we do snprintf regardless. */
3566 snprintf (buf, size, "#0x%" PRIx64, addr);
3567 break;
3568
3569 case AARCH64_OPND_ADDR_PCREL14:
3570 case AARCH64_OPND_ADDR_PCREL19:
3571 case AARCH64_OPND_ADDR_PCREL21:
3572 case AARCH64_OPND_ADDR_PCREL26:
3573 addr = pc + AARCH64_PCREL_OFFSET + opnd->imm.value;
3574 if (pcrel_p)
3575 *pcrel_p = 1;
3576 if (address)
3577 *address = addr;
3578 /* This is not necessary during the disassembling, as print_address_func
3579 in the disassemble_info will take care of the printing. But some
3580 other callers may be still interested in getting the string in *STR,
3581 so here we do snprintf regardless. */
3582 snprintf (buf, size, "#0x%" PRIx64, addr);
3583 break;
3584
3585 case AARCH64_OPND_ADDR_SIMPLE:
3586 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
3587 case AARCH64_OPND_SIMD_ADDR_POST:
3588 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3589 if (opnd->type == AARCH64_OPND_SIMD_ADDR_POST)
3590 {
3591 if (opnd->addr.offset.is_reg)
3592 snprintf (buf, size, "[%s], x%d", name, opnd->addr.offset.regno);
3593 else
3594 snprintf (buf, size, "[%s], #%d", name, opnd->addr.offset.imm);
3595 }
3596 else
3597 snprintf (buf, size, "[%s]", name);
3598 break;
3599
3600 case AARCH64_OPND_ADDR_REGOFF:
c8d59609 3601 case AARCH64_OPND_SVE_ADDR_R:
4df068de
RS		 3602 case AARCH64_OPND_SVE_ADDR_RR:
3603 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
3604 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
3605 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
3606 case AARCH64_OPND_SVE_ADDR_RX:
3607 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
3608 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
3609 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
01dbfe4c
RS		 3610 print_register_offset_address
3611 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3612 get_offset_int_reg_name (opnd));
a06ea964
NC		 3613 break;
3614
c469c864
MM		 3615 case AARCH64_OPND_SVE_ADDR_ZX:
3616 print_register_offset_address
3617 (buf, size, opnd,
3618 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3619 get_64bit_int_reg_name (opnd->addr.offset.regno, 0));
3620 break;
3621
4df068de
RS		 3622 case AARCH64_OPND_SVE_ADDR_RZ:
3623 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
3624 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
3625 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
3626 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
3627 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
3628 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
3629 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
3630 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
3631 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
3632 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
3633 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
3634 print_register_offset_address
3635 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3636 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3637 break;
3638
a06ea964
NC		 3639 case AARCH64_OPND_ADDR_SIMM7:
3640 case AARCH64_OPND_ADDR_SIMM9:
3641 case AARCH64_OPND_ADDR_SIMM9_2:
3f06e550 3642 case AARCH64_OPND_ADDR_SIMM10:
fb3265b3
SD		 3643 case AARCH64_OPND_ADDR_SIMM11:
3644 case AARCH64_OPND_ADDR_SIMM13:
f42f1a1d 3645 case AARCH64_OPND_ADDR_OFFSET:
582e12bf 3646 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
8382113f 3647 case AARCH64_OPND_SVE_ADDR_RI_S4x32:
98907a70
RS		 3648 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
3649 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
3650 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
3651 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
3652 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
3653 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
4df068de
RS		 3654 case AARCH64_OPND_SVE_ADDR_RI_U6:
3655 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
3656 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
3657 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
01dbfe4c
RS		 3658 print_immediate_offset_address
3659 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1));
a06ea964
NC		 3660 break;
3661
4df068de
RS		 3662 case AARCH64_OPND_SVE_ADDR_ZI_U5:
3663 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
3664 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
3665 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
3666 print_immediate_offset_address
3667 (buf, size, opnd,
3668 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier));
3669 break;
3670
3671 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
3672 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
3673 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
3674 print_register_offset_address
3675 (buf, size, opnd,
3676 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3677 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3678 break;
3679
a06ea964
NC		 3680 case AARCH64_OPND_ADDR_UIMM12:
3681 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3682 if (opnd->addr.offset.imm)
ad43e107 3683 snprintf (buf, size, "[%s, #%d]", name, opnd->addr.offset.imm);
a06ea964
NC		 3684 else
3685 snprintf (buf, size, "[%s]", name);
3686 break;
3687
3688 case AARCH64_OPND_SYSREG:
3689 for (i = 0; aarch64_sys_regs[i].name; ++i)
f9830ec1
TC		 3690 {
3691 bfd_boolean exact_match
3692 = (aarch64_sys_regs[i].flags & opnd->sysreg.flags)
3693 == opnd->sysreg.flags;
3694
3695 /* Try and find an exact match, But if that fails, return the first
3696 partial match that was found. */
3697 if (aarch64_sys_regs[i].value == opnd->sysreg.value
f7cb161e 3698 && ! aarch64_sys_reg_deprecated_p (aarch64_sys_regs[i].flags)
f9830ec1
TC		 3699 && (name == NULL || exact_match))
3700 {
3701 name = aarch64_sys_regs[i].name;
3702 if (exact_match)
3703 {
3704 if (notes)
3705 *notes = NULL;
3706 break;
3707 }
3708
3709 /* If we didn't match exactly, that means the presense of a flag
3710 indicates what we didn't want for this instruction. e.g. If
3711 F_REG_READ is there, that means we were looking for a write
3712 register. See aarch64_ext_sysreg. */
3713 if (aarch64_sys_regs[i].flags & F_REG_WRITE)
bde90be2 3714 *notes = _("reading from a write-only register");
f9830ec1 3715 else if (aarch64_sys_regs[i].flags & F_REG_READ)
bde90be2 3716 *notes = _("writing to a read-only register");
f9830ec1
TC		 3717 }
3718 }
3719
3720 if (name)
3721 snprintf (buf, size, "%s", name);
a06ea964
NC		 3722 else
3723 {
3724 /* Implementation defined system register. */
561a72d4 3725 unsigned int value = opnd->sysreg.value;
a06ea964
NC		 3726 snprintf (buf, size, "s%u_%u_c%u_c%u_%u", (value >> 14) & 0x3,
3727 (value >> 11) & 0x7, (value >> 7) & 0xf, (value >> 3) & 0xf,
3728 value & 0x7);
3729 }
3730 break;
3731
3732 case AARCH64_OPND_PSTATEFIELD:
3733 for (i = 0; aarch64_pstatefields[i].name; ++i)
3734 if (aarch64_pstatefields[i].value == opnd->pstatefield)
3735 break;
3736 assert (aarch64_pstatefields[i].name);
3737 snprintf (buf, size, "%s", aarch64_pstatefields[i].name);
3738 break;
3739
3740 case AARCH64_OPND_SYSREG_AT:
3741 case AARCH64_OPND_SYSREG_DC:
3742 case AARCH64_OPND_SYSREG_IC:
3743 case AARCH64_OPND_SYSREG_TLBI:
2ac435d4 3744 case AARCH64_OPND_SYSREG_SR:
875880c6 3745 snprintf (buf, size, "%s", opnd->sysins_op->name);
a06ea964
NC		 3746 break;
3747
3748 case AARCH64_OPND_BARRIER:
3749 snprintf (buf, size, "%s", opnd->barrier->name);
3750 break;
3751
3752 case AARCH64_OPND_BARRIER_ISB:
3753 /* Operand can be omitted, e.g. in DCPS1. */
3754 if (! optional_operand_p (opcode, idx)
3755 || (opnd->barrier->value
3756 != get_optional_operand_default_value (opcode)))
3757 snprintf (buf, size, "#0x%x", opnd->barrier->value);
3758 break;
3759
3760 case AARCH64_OPND_PRFOP:
a1ccaec9
YZ		 3761 if (opnd->prfop->name != NULL)
3762 snprintf (buf, size, "%s", opnd->prfop->name);
3763 else
3764 snprintf (buf, size, "#0x%02x", opnd->prfop->value);
a06ea964
NC		 3765 break;
3766
1e6f4800 3767 case AARCH64_OPND_BARRIER_PSB:
c2e5c986
SD		 3768 snprintf (buf, size, "csync");
3769 break;
3770
ff605452
SD		 3771 case AARCH64_OPND_BTI_TARGET:
3772 if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
3773 snprintf (buf, size, "%s", opnd->hint_option->name);
1e6f4800
MW		 3774 break;
3775
a06ea964
NC		 3776 default:
3777 assert (0);
3778 }
3779}
3780\f
3781#define CPENC(op0,op1,crn,crm,op2) \
3782 ((((op0) << 19) | ((op1) << 16) | ((crn) << 12) | ((crm) << 8) | ((op2) << 5)) >> 5)
3783 /* for 3.9.3 Instructions for Accessing Special Purpose Registers */
3784#define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2))
3785 /* for 3.9.10 System Instructions */
3786#define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2))
3787
3788#define C0 0
3789#define C1 1
3790#define C2 2
3791#define C3 3
3792#define C4 4
3793#define C5 5
3794#define C6 6
3795#define C7 7
3796#define C8 8
3797#define C9 9
3798#define C10 10
3799#define C11 11
3800#define C12 12
3801#define C13 13
3802#define C14 14
3803#define C15 15
3804
14962256
AC		 3805#define SYSREG(name, encoding, flags, features) \
3806 { name, encoding, flags, features }
3807
3808#define SR_CORE(n,e,f) SYSREG (n,e,f,0)
3809
3810#define SR_FEAT(n,e,f,feat) \
3811 SYSREG ((n), (e), (f) | F_ARCHEXT, AARCH64_FEATURE_##feat)
3812
3813#define SR_RNG(n,e,f) \
3814 SYSREG ((n), (e), (f) | F_ARCHEXT, AARCH64_FEATURE_RNG | AARCH64_FEATURE_V8_5)
3815
3816#define SR_V8_1(n,e,f) SR_FEAT (n,e,f,V8_1)
3817#define SR_V8_2(n,e,f) SR_FEAT (n,e,f,V8_2)
3818#define SR_V8_3(n,e,f) SR_FEAT (n,e,f,V8_3)
3819#define SR_V8_4(n,e,f) SR_FEAT (n,e,f,V8_4)
3820#define SR_V8_4(n,e,f) SR_FEAT (n,e,f,V8_4)
3821#define SR_PAN(n,e,f) SR_FEAT (n,e,f,PAN)
3822#define SR_RAS(n,e,f) SR_FEAT (n,e,f,RAS)
3823#define SR_SSBS(n,e,f) SR_FEAT (n,e,f,SSBS)
3824#define SR_SVE(n,e,f) SR_FEAT (n,e,f,SVE)
3825#define SR_ID_PFR2(n,e,f) SR_FEAT (n,e,f,ID_PFR2)
3826#define SR_PROFILE(n,e,f) SR_FEAT (n,e,f,PROFILE)
3827#define SR_MEMTAG(n,e,f) SR_FEAT (n,e,f,MEMTAG)
3828#define SR_SCXTNUM(n,e,f) SR_FEAT (n,e,f,SCXTNUM)
3829
f9830ec1 3830/* TODO there is one more issues need to be resolved
14962256
AC		 3831 1. handle cpu-implementation-defined system registers.
3832
3833 Note that the F_REG_{READ,WRITE} flags mean read-only and write-only
3834 respectively. If neither of these are set then the register is read-write. */
49eec193
YZ		 3835const aarch64_sys_reg aarch64_sys_regs [] =
3836{
14962256
AC		 3837 SR_CORE ("spsr_el1", CPEN_ (0,C0,0), 0), /* = spsr_svc. */
3838 SR_V8_1 ("spsr_el12", CPEN_ (5,C0,0), 0),
3839 SR_CORE ("elr_el1", CPEN_ (0,C0,1), 0),
3840 SR_V8_1 ("elr_el12", CPEN_ (5,C0,1), 0),
3841 SR_CORE ("sp_el0", CPEN_ (0,C1,0), 0),
3842 SR_CORE ("spsel", CPEN_ (0,C2,0), 0),
3843 SR_CORE ("daif", CPEN_ (3,C2,1), 0),
3844 SR_CORE ("currentel", CPEN_ (0,C2,2), F_REG_READ),
3845 SR_PAN ("pan", CPEN_ (0,C2,3), 0),
3846 SR_V8_2 ("uao", CPEN_ (0,C2,4), 0),
3847 SR_CORE ("nzcv", CPEN_ (3,C2,0), 0),
3848 SR_SSBS ("ssbs", CPEN_ (3,C2,6), 0),
3849 SR_CORE ("fpcr", CPEN_ (3,C4,0), 0),
3850 SR_CORE ("fpsr", CPEN_ (3,C4,1), 0),
3851 SR_CORE ("dspsr_el0", CPEN_ (3,C5,0), 0),
3852 SR_CORE ("dlr_el0", CPEN_ (3,C5,1), 0),
3853 SR_CORE ("spsr_el2", CPEN_ (4,C0,0), 0), /* = spsr_hyp. */
3854 SR_CORE ("elr_el2", CPEN_ (4,C0,1), 0),
3855 SR_CORE ("sp_el1", CPEN_ (4,C1,0), 0),
3856 SR_CORE ("spsr_irq", CPEN_ (4,C3,0), 0),
3857 SR_CORE ("spsr_abt", CPEN_ (4,C3,1), 0),
3858 SR_CORE ("spsr_und", CPEN_ (4,C3,2), 0),
3859 SR_CORE ("spsr_fiq", CPEN_ (4,C3,3), 0),
3860 SR_CORE ("spsr_el3", CPEN_ (6,C0,0), 0),
3861 SR_CORE ("elr_el3", CPEN_ (6,C0,1), 0),
3862 SR_CORE ("sp_el2", CPEN_ (6,C1,0), 0),
3863 SR_CORE ("spsr_svc", CPEN_ (0,C0,0), F_DEPRECATED), /* = spsr_el1. */
3864 SR_CORE ("spsr_hyp", CPEN_ (4,C0,0), F_DEPRECATED), /* = spsr_el2. */
3865 SR_CORE ("midr_el1", CPENC (3,0,C0,C0,0), F_REG_READ),
3866 SR_CORE ("ctr_el0", CPENC (3,3,C0,C0,1), F_REG_READ),
3867 SR_CORE ("mpidr_el1", CPENC (3,0,C0,C0,5), F_REG_READ),
3868 SR_CORE ("revidr_el1", CPENC (3,0,C0,C0,6), F_REG_READ),
3869 SR_CORE ("aidr_el1", CPENC (3,1,C0,C0,7), F_REG_READ),
3870 SR_CORE ("dczid_el0", CPENC (3,3,C0,C0,7), F_REG_READ),
3871 SR_CORE ("id_dfr0_el1", CPENC (3,0,C0,C1,2), F_REG_READ),
3872 SR_CORE ("id_pfr0_el1", CPENC (3,0,C0,C1,0), F_REG_READ),
3873 SR_CORE ("id_pfr1_el1", CPENC (3,0,C0,C1,1), F_REG_READ),
3874 SR_ID_PFR2 ("id_pfr2_el1", CPENC (3,0,C0,C3,4), F_REG_READ),
3875 SR_CORE ("id_afr0_el1", CPENC (3,0,C0,C1,3), F_REG_READ),
3876 SR_CORE ("id_mmfr0_el1", CPENC (3,0,C0,C1,4), F_REG_READ),
3877 SR_CORE ("id_mmfr1_el1", CPENC (3,0,C0,C1,5), F_REG_READ),
3878 SR_CORE ("id_mmfr2_el1", CPENC (3,0,C0,C1,6), F_REG_READ),
3879 SR_CORE ("id_mmfr3_el1", CPENC (3,0,C0,C1,7), F_REG_READ),
3880 SR_CORE ("id_mmfr4_el1", CPENC (3,0,C0,C2,6), F_REG_READ),
3881 SR_CORE ("id_isar0_el1", CPENC (3,0,C0,C2,0), F_REG_READ),
3882 SR_CORE ("id_isar1_el1", CPENC (3,0,C0,C2,1), F_REG_READ),
3883 SR_CORE ("id_isar2_el1", CPENC (3,0,C0,C2,2), F_REG_READ),
3884 SR_CORE ("id_isar3_el1", CPENC (3,0,C0,C2,3), F_REG_READ),
3885 SR_CORE ("id_isar4_el1", CPENC (3,0,C0,C2,4), F_REG_READ),
3886 SR_CORE ("id_isar5_el1", CPENC (3,0,C0,C2,5), F_REG_READ),
3887 SR_CORE ("mvfr0_el1", CPENC (3,0,C0,C3,0), F_REG_READ),
3888 SR_CORE ("mvfr1_el1", CPENC (3,0,C0,C3,1), F_REG_READ),
3889 SR_CORE ("mvfr2_el1", CPENC (3,0,C0,C3,2), F_REG_READ),
3890 SR_CORE ("ccsidr_el1", CPENC (3,1,C0,C0,0), F_REG_READ),
3891 SR_CORE ("id_aa64pfr0_el1", CPENC (3,0,C0,C4,0), F_REG_READ),
3892 SR_CORE ("id_aa64pfr1_el1", CPENC (3,0,C0,C4,1), F_REG_READ),
3893 SR_CORE ("id_aa64dfr0_el1", CPENC (3,0,C0,C5,0), F_REG_READ),
3894 SR_CORE ("id_aa64dfr1_el1", CPENC (3,0,C0,C5,1), F_REG_READ),
3895 SR_CORE ("id_aa64isar0_el1", CPENC (3,0,C0,C6,0), F_REG_READ),
3896 SR_CORE ("id_aa64isar1_el1", CPENC (3,0,C0,C6,1), F_REG_READ),
3897 SR_CORE ("id_aa64mmfr0_el1", CPENC (3,0,C0,C7,0), F_REG_READ),
3898 SR_CORE ("id_aa64mmfr1_el1", CPENC (3,0,C0,C7,1), F_REG_READ),
3899 SR_V8_2 ("id_aa64mmfr2_el1", CPENC (3,0,C0,C7,2), F_REG_READ),
3900 SR_CORE ("id_aa64afr0_el1", CPENC (3,0,C0,C5,4), F_REG_READ),
3901 SR_CORE ("id_aa64afr1_el1", CPENC (3,0,C0,C5,5), F_REG_READ),
3902 SR_SVE ("id_aa64zfr0_el1", CPENC (3,0,C0,C4,4), F_REG_READ),
3903 SR_CORE ("clidr_el1", CPENC (3,1,C0,C0,1), F_REG_READ),
3904 SR_CORE ("csselr_el1", CPENC (3,2,C0,C0,0), 0),
3905 SR_CORE ("vpidr_el2", CPENC (3,4,C0,C0,0), 0),
3906 SR_CORE ("vmpidr_el2", CPENC (3,4,C0,C0,5), 0),
3907 SR_CORE ("sctlr_el1", CPENC (3,0,C1,C0,0), 0),
3908 SR_CORE ("sctlr_el2", CPENC (3,4,C1,C0,0), 0),
3909 SR_CORE ("sctlr_el3", CPENC (3,6,C1,C0,0), 0),
3910 SR_V8_1 ("sctlr_el12", CPENC (3,5,C1,C0,0), 0),
3911 SR_CORE ("actlr_el1", CPENC (3,0,C1,C0,1), 0),
3912 SR_CORE ("actlr_el2", CPENC (3,4,C1,C0,1), 0),
3913 SR_CORE ("actlr_el3", CPENC (3,6,C1,C0,1), 0),
3914 SR_CORE ("cpacr_el1", CPENC (3,0,C1,C0,2), 0),
3915 SR_V8_1 ("cpacr_el12", CPENC (3,5,C1,C0,2), 0),
3916 SR_CORE ("cptr_el2", CPENC (3,4,C1,C1,2), 0),
3917 SR_CORE ("cptr_el3", CPENC (3,6,C1,C1,2), 0),
3918 SR_CORE ("scr_el3", CPENC (3,6,C1,C1,0), 0),
3919 SR_CORE ("hcr_el2", CPENC (3,4,C1,C1,0), 0),
3920 SR_CORE ("mdcr_el2", CPENC (3,4,C1,C1,1), 0),
3921 SR_CORE ("mdcr_el3", CPENC (3,6,C1,C3,1), 0),
3922 SR_CORE ("hstr_el2", CPENC (3,4,C1,C1,3), 0),
3923 SR_CORE ("hacr_el2", CPENC (3,4,C1,C1,7), 0),
3924 SR_SVE ("zcr_el1", CPENC (3,0,C1,C2,0), 0),
3925 SR_SVE ("zcr_el12", CPENC (3,5,C1,C2,0), 0),
3926 SR_SVE ("zcr_el2", CPENC (3,4,C1,C2,0), 0),
3927 SR_SVE ("zcr_el3", CPENC (3,6,C1,C2,0), 0),
3928 SR_SVE ("zidr_el1", CPENC (3,0,C0,C0,7), 0),
3929 SR_CORE ("ttbr0_el1", CPENC (3,0,C2,C0,0), 0),
3930 SR_CORE ("ttbr1_el1", CPENC (3,0,C2,C0,1), 0),
3931 SR_CORE ("ttbr0_el2", CPENC (3,4,C2,C0,0), 0),
3932 SR_V8_1 ("ttbr1_el2", CPENC (3,4,C2,C0,1), 0),
3933 SR_CORE ("ttbr0_el3", CPENC (3,6,C2,C0,0), 0),
3934 SR_V8_1 ("ttbr0_el12", CPENC (3,5,C2,C0,0), 0),
3935 SR_V8_1 ("ttbr1_el12", CPENC (3,5,C2,C0,1), 0),
3936 SR_CORE ("vttbr_el2", CPENC (3,4,C2,C1,0), 0),
3937 SR_CORE ("tcr_el1", CPENC (3,0,C2,C0,2), 0),
3938 SR_CORE ("tcr_el2", CPENC (3,4,C2,C0,2), 0),
3939 SR_CORE ("tcr_el3", CPENC (3,6,C2,C0,2), 0),
3940 SR_V8_1 ("tcr_el12", CPENC (3,5,C2,C0,2), 0),
3941 SR_CORE ("vtcr_el2", CPENC (3,4,C2,C1,2), 0),
3942 SR_V8_3 ("apiakeylo_el1", CPENC (3,0,C2,C1,0), 0),
3943 SR_V8_3 ("apiakeyhi_el1", CPENC (3,0,C2,C1,1), 0),
3944 SR_V8_3 ("apibkeylo_el1", CPENC (3,0,C2,C1,2), 0),
3945 SR_V8_3 ("apibkeyhi_el1", CPENC (3,0,C2,C1,3), 0),
3946 SR_V8_3 ("apdakeylo_el1", CPENC (3,0,C2,C2,0), 0),
3947 SR_V8_3 ("apdakeyhi_el1", CPENC (3,0,C2,C2,1), 0),
3948 SR_V8_3 ("apdbkeylo_el1", CPENC (3,0,C2,C2,2), 0),
3949 SR_V8_3 ("apdbkeyhi_el1", CPENC (3,0,C2,C2,3), 0),
3950 SR_V8_3 ("apgakeylo_el1", CPENC (3,0,C2,C3,0), 0),
3951 SR_V8_3 ("apgakeyhi_el1", CPENC (3,0,C2,C3,1), 0),
3952 SR_CORE ("afsr0_el1", CPENC (3,0,C5,C1,0), 0),
3953 SR_CORE ("afsr1_el1", CPENC (3,0,C5,C1,1), 0),
3954 SR_CORE ("afsr0_el2", CPENC (3,4,C5,C1,0), 0),
3955 SR_CORE ("afsr1_el2", CPENC (3,4,C5,C1,1), 0),
3956 SR_CORE ("afsr0_el3", CPENC (3,6,C5,C1,0), 0),
3957 SR_V8_1 ("afsr0_el12", CPENC (3,5,C5,C1,0), 0),
3958 SR_CORE ("afsr1_el3", CPENC (3,6,C5,C1,1), 0),
3959 SR_V8_1 ("afsr1_el12", CPENC (3,5,C5,C1,1), 0),
3960 SR_CORE ("esr_el1", CPENC (3,0,C5,C2,0), 0),
3961 SR_CORE ("esr_el2", CPENC (3,4,C5,C2,0), 0),
3962 SR_CORE ("esr_el3", CPENC (3,6,C5,C2,0), 0),
3963 SR_V8_1 ("esr_el12", CPENC (3,5,C5,C2,0), 0),
3964 SR_RAS ("vsesr_el2", CPENC (3,4,C5,C2,3), 0),
3965 SR_CORE ("fpexc32_el2", CPENC (3,4,C5,C3,0), 0),
3966 SR_RAS ("erridr_el1", CPENC (3,0,C5,C3,0), F_REG_READ),
3967 SR_RAS ("errselr_el1", CPENC (3,0,C5,C3,1), 0),
3968 SR_RAS ("erxfr_el1", CPENC (3,0,C5,C4,0), F_REG_READ),
3969 SR_RAS ("erxctlr_el1", CPENC (3,0,C5,C4,1), 0),
3970 SR_RAS ("erxstatus_el1", CPENC (3,0,C5,C4,2), 0),
3971 SR_RAS ("erxaddr_el1", CPENC (3,0,C5,C4,3), 0),
3972 SR_RAS ("erxmisc0_el1", CPENC (3,0,C5,C5,0), 0),
3973 SR_RAS ("erxmisc1_el1", CPENC (3,0,C5,C5,1), 0),
3974 SR_CORE ("far_el1", CPENC (3,0,C6,C0,0), 0),
3975 SR_CORE ("far_el2", CPENC (3,4,C6,C0,0), 0),
3976 SR_CORE ("far_el3", CPENC (3,6,C6,C0,0), 0),
3977 SR_V8_1 ("far_el12", CPENC (3,5,C6,C0,0), 0),
3978 SR_CORE ("hpfar_el2", CPENC (3,4,C6,C0,4), 0),
3979 SR_CORE ("par_el1", CPENC (3,0,C7,C4,0), 0),
3980 SR_CORE ("mair_el1", CPENC (3,0,C10,C2,0), 0),
3981 SR_CORE ("mair_el2", CPENC (3,4,C10,C2,0), 0),
3982 SR_CORE ("mair_el3", CPENC (3,6,C10,C2,0), 0),
3983 SR_V8_1 ("mair_el12", CPENC (3,5,C10,C2,0), 0),
3984 SR_CORE ("amair_el1", CPENC (3,0,C10,C3,0), 0),
3985 SR_CORE ("amair_el2", CPENC (3,4,C10,C3,0), 0),
3986 SR_CORE ("amair_el3", CPENC (3,6,C10,C3,0), 0),
3987 SR_V8_1 ("amair_el12", CPENC (3,5,C10,C3,0), 0),
3988 SR_CORE ("vbar_el1", CPENC (3,0,C12,C0,0), 0),
3989 SR_CORE ("vbar_el2", CPENC (3,4,C12,C0,0), 0),
3990 SR_CORE ("vbar_el3", CPENC (3,6,C12,C0,0), 0),
3991 SR_V8_1 ("vbar_el12", CPENC (3,5,C12,C0,0), 0),
3992 SR_CORE ("rvbar_el1", CPENC (3,0,C12,C0,1), F_REG_READ),
3993 SR_CORE ("rvbar_el2", CPENC (3,4,C12,C0,1), F_REG_READ),
3994 SR_CORE ("rvbar_el3", CPENC (3,6,C12,C0,1), F_REG_READ),
3995 SR_CORE ("rmr_el1", CPENC (3,0,C12,C0,2), 0),
3996 SR_CORE ("rmr_el2", CPENC (3,4,C12,C0,2), 0),
3997 SR_CORE ("rmr_el3", CPENC (3,6,C12,C0,2), 0),
3998 SR_CORE ("isr_el1", CPENC (3,0,C12,C1,0), F_REG_READ),
3999 SR_RAS ("disr_el1", CPENC (3,0,C12,C1,1), 0),
4000 SR_RAS ("vdisr_el2", CPENC (3,4,C12,C1,1), 0),
4001 SR_CORE ("contextidr_el1", CPENC (3,0,C13,C0,1), 0),
4002 SR_V8_1 ("contextidr_el2", CPENC (3,4,C13,C0,1), 0),
4003 SR_V8_1 ("contextidr_el12", CPENC (3,5,C13,C0,1), 0),
4004 SR_RNG ("rndr", CPENC (3,3,C2,C4,0), F_REG_READ),
4005 SR_RNG ("rndrrs", CPENC (3,3,C2,C4,1), F_REG_READ),
4006 SR_MEMTAG ("tco", CPENC (3,3,C4,C2,7), 0),
4007 SR_MEMTAG ("tfsre0_el1", CPENC (3,0,C5,C6,1), 0),
4008 SR_MEMTAG ("tfsr_el1", CPENC (3,0,C5,C6,0), 0),
4009 SR_MEMTAG ("tfsr_el2", CPENC (3,4,C5,C6,0), 0),
4010 SR_MEMTAG ("tfsr_el3", CPENC (3,6,C5,C6,0), 0),
4011 SR_MEMTAG ("tfsr_el12", CPENC (3,5,C5,C6,0), 0),
4012 SR_MEMTAG ("rgsr_el1", CPENC (3,0,C1,C0,5), 0),
4013 SR_MEMTAG ("gcr_el1", CPENC (3,0,C1,C0,6), 0),
4014 SR_MEMTAG ("gmid_el1", CPENC (3,1,C0,C0,4), F_REG_READ),
4015 SR_CORE ("tpidr_el0", CPENC (3,3,C13,C0,2), 0),
4016 SR_CORE ("tpidrro_el0", CPENC (3,3,C13,C0,3), 0),
4017 SR_CORE ("tpidr_el1", CPENC (3,0,C13,C0,4), 0),
4018 SR_CORE ("tpidr_el2", CPENC (3,4,C13,C0,2), 0),
4019 SR_CORE ("tpidr_el3", CPENC (3,6,C13,C0,2), 0),
4020 SR_SCXTNUM ("scxtnum_el0", CPENC (3,3,C13,C0,7), 0),
4021 SR_SCXTNUM ("scxtnum_el1", CPENC (3,0,C13,C0,7), 0),
4022 SR_SCXTNUM ("scxtnum_el2", CPENC (3,4,C13,C0,7), 0),
4023 SR_SCXTNUM ("scxtnum_el12", CPENC (3,5,C13,C0,7), 0),
4024 SR_SCXTNUM ("scxtnum_el3", CPENC (3,6,C13,C0,7), 0),
4025 SR_CORE ("teecr32_el1", CPENC (2,2,C0, C0,0), 0), /* See section 3.9.7.1. */
4026 SR_CORE ("cntfrq_el0", CPENC (3,3,C14,C0,0), 0),
4027 SR_CORE ("cntpct_el0", CPENC (3,3,C14,C0,1), F_REG_READ),
4028 SR_CORE ("cntvct_el0", CPENC (3,3,C14,C0,2), F_REG_READ),
4029 SR_CORE ("cntvoff_el2", CPENC (3,4,C14,C0,3), 0),
4030 SR_CORE ("cntkctl_el1", CPENC (3,0,C14,C1,0), 0),
4031 SR_V8_1 ("cntkctl_el12", CPENC (3,5,C14,C1,0), 0),
4032 SR_CORE ("cnthctl_el2", CPENC (3,4,C14,C1,0), 0),
4033 SR_CORE ("cntp_tval_el0", CPENC (3,3,C14,C2,0), 0),
4034 SR_V8_1 ("cntp_tval_el02", CPENC (3,5,C14,C2,0), 0),
4035 SR_CORE ("cntp_ctl_el0", CPENC (3,3,C14,C2,1), 0),
4036 SR_V8_1 ("cntp_ctl_el02", CPENC (3,5,C14,C2,1), 0),
4037 SR_CORE ("cntp_cval_el0", CPENC (3,3,C14,C2,2), 0),
4038 SR_V8_1 ("cntp_cval_el02", CPENC (3,5,C14,C2,2), 0),
4039 SR_CORE ("cntv_tval_el0", CPENC (3,3,C14,C3,0), 0),
4040 SR_V8_1 ("cntv_tval_el02", CPENC (3,5,C14,C3,0), 0),
4041 SR_CORE ("cntv_ctl_el0", CPENC (3,3,C14,C3,1), 0),
4042 SR_V8_1 ("cntv_ctl_el02", CPENC (3,5,C14,C3,1), 0),
4043 SR_CORE ("cntv_cval_el0", CPENC (3,3,C14,C3,2), 0),
4044 SR_V8_1 ("cntv_cval_el02", CPENC (3,5,C14,C3,2), 0),
4045 SR_CORE ("cnthp_tval_el2", CPENC (3,4,C14,C2,0), 0),
4046 SR_CORE ("cnthp_ctl_el2", CPENC (3,4,C14,C2,1), 0),
4047 SR_CORE ("cnthp_cval_el2", CPENC (3,4,C14,C2,2), 0),
4048 SR_CORE ("cntps_tval_el1", CPENC (3,7,C14,C2,0), 0),
4049 SR_CORE ("cntps_ctl_el1", CPENC (3,7,C14,C2,1), 0),
4050 SR_CORE ("cntps_cval_el1", CPENC (3,7,C14,C2,2), 0),
4051 SR_V8_1 ("cnthv_tval_el2", CPENC (3,4,C14,C3,0), 0),
4052 SR_V8_1 ("cnthv_ctl_el2", CPENC (3,4,C14,C3,1), 0),
4053 SR_V8_1 ("cnthv_cval_el2", CPENC (3,4,C14,C3,2), 0),
4054 SR_CORE ("dacr32_el2", CPENC (3,4,C3,C0,0), 0),
4055 SR_CORE ("ifsr32_el2", CPENC (3,4,C5,C0,1), 0),
4056 SR_CORE ("teehbr32_el1", CPENC (2,2,C1,C0,0), 0),
4057 SR_CORE ("sder32_el3", CPENC (3,6,C1,C1,1), 0),
4058 SR_CORE ("mdscr_el1", CPENC (2,0,C0,C2,2), 0),
4059 SR_CORE ("mdccsr_el0", CPENC (2,3,C0,C1,0), F_REG_READ),
4060 SR_CORE ("mdccint_el1", CPENC (2,0,C0,C2,0), 0),
4061 SR_CORE ("dbgdtr_el0", CPENC (2,3,C0,C4,0), 0),
4062 SR_CORE ("dbgdtrrx_el0", CPENC (2,3,C0,C5,0), F_REG_READ),
4063 SR_CORE ("dbgdtrtx_el0", CPENC (2,3,C0,C5,0), F_REG_WRITE),
4064 SR_CORE ("osdtrrx_el1", CPENC (2,0,C0,C0,2), 0),
4065 SR_CORE ("osdtrtx_el1", CPENC (2,0,C0,C3,2), 0),
4066 SR_CORE ("oseccr_el1", CPENC (2,0,C0,C6,2), 0),
4067 SR_CORE ("dbgvcr32_el2", CPENC (2,4,C0,C7,0), 0),
4068 SR_CORE ("dbgbvr0_el1", CPENC (2,0,C0,C0,4), 0),
4069 SR_CORE ("dbgbvr1_el1", CPENC (2,0,C0,C1,4), 0),
4070 SR_CORE ("dbgbvr2_el1", CPENC (2,0,C0,C2,4), 0),
4071 SR_CORE ("dbgbvr3_el1", CPENC (2,0,C0,C3,4), 0),
4072 SR_CORE ("dbgbvr4_el1", CPENC (2,0,C0,C4,4), 0),
4073 SR_CORE ("dbgbvr5_el1", CPENC (2,0,C0,C5,4), 0),
4074 SR_CORE ("dbgbvr6_el1", CPENC (2,0,C0,C6,4), 0),
4075 SR_CORE ("dbgbvr7_el1", CPENC (2,0,C0,C7,4), 0),
4076 SR_CORE ("dbgbvr8_el1", CPENC (2,0,C0,C8,4), 0),
4077 SR_CORE ("dbgbvr9_el1", CPENC (2,0,C0,C9,4), 0),
4078 SR_CORE ("dbgbvr10_el1", CPENC (2,0,C0,C10,4), 0),
4079 SR_CORE ("dbgbvr11_el1", CPENC (2,0,C0,C11,4), 0),
4080 SR_CORE ("dbgbvr12_el1", CPENC (2,0,C0,C12,4), 0),
4081 SR_CORE ("dbgbvr13_el1", CPENC (2,0,C0,C13,4), 0),
4082 SR_CORE ("dbgbvr14_el1", CPENC (2,0,C0,C14,4), 0),
4083 SR_CORE ("dbgbvr15_el1", CPENC (2,0,C0,C15,4), 0),
4084 SR_CORE ("dbgbcr0_el1", CPENC (2,0,C0,C0,5), 0),
4085 SR_CORE ("dbgbcr1_el1", CPENC (2,0,C0,C1,5), 0),
4086 SR_CORE ("dbgbcr2_el1", CPENC (2,0,C0,C2,5), 0),
4087 SR_CORE ("dbgbcr3_el1", CPENC (2,0,C0,C3,5), 0),
4088 SR_CORE ("dbgbcr4_el1", CPENC (2,0,C0,C4,5), 0),
4089 SR_CORE ("dbgbcr5_el1", CPENC (2,0,C0,C5,5), 0),
4090 SR_CORE ("dbgbcr6_el1", CPENC (2,0,C0,C6,5), 0),
4091 SR_CORE ("dbgbcr7_el1", CPENC (2,0,C0,C7,5), 0),
4092 SR_CORE ("dbgbcr8_el1", CPENC (2,0,C0,C8,5), 0),
4093 SR_CORE ("dbgbcr9_el1", CPENC (2,0,C0,C9,5), 0),
4094 SR_CORE ("dbgbcr10_el1", CPENC (2,0,C0,C10,5), 0),
4095 SR_CORE ("dbgbcr11_el1", CPENC (2,0,C0,C11,5), 0),
4096 SR_CORE ("dbgbcr12_el1", CPENC (2,0,C0,C12,5), 0),
4097 SR_CORE ("dbgbcr13_el1", CPENC (2,0,C0,C13,5), 0),
4098 SR_CORE ("dbgbcr14_el1", CPENC (2,0,C0,C14,5), 0),
4099 SR_CORE ("dbgbcr15_el1", CPENC (2,0,C0,C15,5), 0),
4100 SR_CORE ("dbgwvr0_el1", CPENC (2,0,C0,C0,6), 0),
4101 SR_CORE ("dbgwvr1_el1", CPENC (2,0,C0,C1,6), 0),
4102 SR_CORE ("dbgwvr2_el1", CPENC (2,0,C0,C2,6), 0),
4103 SR_CORE ("dbgwvr3_el1", CPENC (2,0,C0,C3,6), 0),
4104 SR_CORE ("dbgwvr4_el1", CPENC (2,0,C0,C4,6), 0),
4105 SR_CORE ("dbgwvr5_el1", CPENC (2,0,C0,C5,6), 0),
4106 SR_CORE ("dbgwvr6_el1", CPENC (2,0,C0,C6,6), 0),
4107 SR_CORE ("dbgwvr7_el1", CPENC (2,0,C0,C7,6), 0),
4108 SR_CORE ("dbgwvr8_el1", CPENC (2,0,C0,C8,6), 0),
4109 SR_CORE ("dbgwvr9_el1", CPENC (2,0,C0,C9,6), 0),
4110 SR_CORE ("dbgwvr10_el1", CPENC (2,0,C0,C10,6), 0),
4111 SR_CORE ("dbgwvr11_el1", CPENC (2,0,C0,C11,6), 0),
4112 SR_CORE ("dbgwvr12_el1", CPENC (2,0,C0,C12,6), 0),
4113 SR_CORE ("dbgwvr13_el1", CPENC (2,0,C0,C13,6), 0),
4114 SR_CORE ("dbgwvr14_el1", CPENC (2,0,C0,C14,6), 0),
4115 SR_CORE ("dbgwvr15_el1", CPENC (2,0,C0,C15,6), 0),
4116 SR_CORE ("dbgwcr0_el1", CPENC (2,0,C0,C0,7), 0),
4117 SR_CORE ("dbgwcr1_el1", CPENC (2,0,C0,C1,7), 0),
4118 SR_CORE ("dbgwcr2_el1", CPENC (2,0,C0,C2,7), 0),
4119 SR_CORE ("dbgwcr3_el1", CPENC (2,0,C0,C3,7), 0),
4120 SR_CORE ("dbgwcr4_el1", CPENC (2,0,C0,C4,7), 0),
4121 SR_CORE ("dbgwcr5_el1", CPENC (2,0,C0,C5,7), 0),
4122 SR_CORE ("dbgwcr6_el1", CPENC (2,0,C0,C6,7), 0),
4123 SR_CORE ("dbgwcr7_el1", CPENC (2,0,C0,C7,7), 0),
4124 SR_CORE ("dbgwcr8_el1", CPENC (2,0,C0,C8,7), 0),
4125 SR_CORE ("dbgwcr9_el1", CPENC (2,0,C0,C9,7), 0),
4126 SR_CORE ("dbgwcr10_el1", CPENC (2,0,C0,C10,7), 0),
4127 SR_CORE ("dbgwcr11_el1", CPENC (2,0,C0,C11,7), 0),
4128 SR_CORE ("dbgwcr12_el1", CPENC (2,0,C0,C12,7), 0),
4129 SR_CORE ("dbgwcr13_el1", CPENC (2,0,C0,C13,7), 0),
4130 SR_CORE ("dbgwcr14_el1", CPENC (2,0,C0,C14,7), 0),
4131 SR_CORE ("dbgwcr15_el1", CPENC (2,0,C0,C15,7), 0),
4132 SR_CORE ("mdrar_el1", CPENC (2,0,C1,C0,0), F_REG_READ),
4133 SR_CORE ("oslar_el1", CPENC (2,0,C1,C0,4), F_REG_WRITE),
4134 SR_CORE ("oslsr_el1", CPENC (2,0,C1,C1,4), F_REG_READ),
4135 SR_CORE ("osdlr_el1", CPENC (2,0,C1,C3,4), 0),
4136 SR_CORE ("dbgprcr_el1", CPENC (2,0,C1,C4,4), 0),
4137 SR_CORE ("dbgclaimset_el1", CPENC (2,0,C7,C8,6), 0),
4138 SR_CORE ("dbgclaimclr_el1", CPENC (2,0,C7,C9,6), 0),
4139 SR_CORE ("dbgauthstatus_el1", CPENC (2,0,C7,C14,6), F_REG_READ),
4140 SR_PROFILE ("pmblimitr_el1", CPENC (3,0,C9,C10,0), 0),
4141 SR_PROFILE ("pmbptr_el1", CPENC (3,0,C9,C10,1), 0),
4142 SR_PROFILE ("pmbsr_el1", CPENC (3,0,C9,C10,3), 0),
4143 SR_PROFILE ("pmbidr_el1", CPENC (3,0,C9,C10,7), F_REG_READ),
4144 SR_PROFILE ("pmscr_el1", CPENC (3,0,C9,C9,0), 0),
4145 SR_PROFILE ("pmsicr_el1", CPENC (3,0,C9,C9,2), 0),
4146 SR_PROFILE ("pmsirr_el1", CPENC (3,0,C9,C9,3), 0),
4147 SR_PROFILE ("pmsfcr_el1", CPENC (3,0,C9,C9,4), 0),
4148 SR_PROFILE ("pmsevfr_el1", CPENC (3,0,C9,C9,5), 0),
4149 SR_PROFILE ("pmslatfr_el1", CPENC (3,0,C9,C9,6), 0),
4150 SR_PROFILE ("pmsidr_el1", CPENC (3,0,C9,C9,7), 0),
4151 SR_PROFILE ("pmscr_el2", CPENC (3,4,C9,C9,0), 0),
4152 SR_PROFILE ("pmscr_el12", CPENC (3,5,C9,C9,0), 0),
4153 SR_CORE ("pmcr_el0", CPENC (3,3,C9,C12,0), 0),
4154 SR_CORE ("pmcntenset_el0", CPENC (3,3,C9,C12,1), 0),
4155 SR_CORE ("pmcntenclr_el0", CPENC (3,3,C9,C12,2), 0),
4156 SR_CORE ("pmovsclr_el0", CPENC (3,3,C9,C12,3), 0),
4157 SR_CORE ("pmswinc_el0", CPENC (3,3,C9,C12,4), F_REG_WRITE),
4158 SR_CORE ("pmselr_el0", CPENC (3,3,C9,C12,5), 0),
4159 SR_CORE ("pmceid0_el0", CPENC (3,3,C9,C12,6), F_REG_READ),
4160 SR_CORE ("pmceid1_el0", CPENC (3,3,C9,C12,7), F_REG_READ),
4161 SR_CORE ("pmccntr_el0", CPENC (3,3,C9,C13,0), 0),
4162 SR_CORE ("pmxevtyper_el0", CPENC (3,3,C9,C13,1), 0),
4163 SR_CORE ("pmxevcntr_el0", CPENC (3,3,C9,C13,2), 0),
4164 SR_CORE ("pmuserenr_el0", CPENC (3,3,C9,C14,0), 0),
4165 SR_CORE ("pmintenset_el1", CPENC (3,0,C9,C14,1), 0),
4166 SR_CORE ("pmintenclr_el1", CPENC (3,0,C9,C14,2), 0),
4167 SR_CORE ("pmovsset_el0", CPENC (3,3,C9,C14,3), 0),
4168 SR_CORE ("pmevcntr0_el0", CPENC (3,3,C14,C8,0), 0),
4169 SR_CORE ("pmevcntr1_el0", CPENC (3,3,C14,C8,1), 0),
4170 SR_CORE ("pmevcntr2_el0", CPENC (3,3,C14,C8,2), 0),
4171 SR_CORE ("pmevcntr3_el0", CPENC (3,3,C14,C8,3), 0),
4172 SR_CORE ("pmevcntr4_el0", CPENC (3,3,C14,C8,4), 0),
4173 SR_CORE ("pmevcntr5_el0", CPENC (3,3,C14,C8,5), 0),
4174 SR_CORE ("pmevcntr6_el0", CPENC (3,3,C14,C8,6), 0),
4175 SR_CORE ("pmevcntr7_el0", CPENC (3,3,C14,C8,7), 0),
4176 SR_CORE ("pmevcntr8_el0", CPENC (3,3,C14,C9,0), 0),
4177 SR_CORE ("pmevcntr9_el0", CPENC (3,3,C14,C9,1), 0),
4178 SR_CORE ("pmevcntr10_el0", CPENC (3,3,C14,C9,2), 0),
4179 SR_CORE ("pmevcntr11_el0", CPENC (3,3,C14,C9,3), 0),
4180 SR_CORE ("pmevcntr12_el0", CPENC (3,3,C14,C9,4), 0),
4181 SR_CORE ("pmevcntr13_el0", CPENC (3,3,C14,C9,5), 0),
4182 SR_CORE ("pmevcntr14_el0", CPENC (3,3,C14,C9,6), 0),
4183 SR_CORE ("pmevcntr15_el0", CPENC (3,3,C14,C9,7), 0),
4184 SR_CORE ("pmevcntr16_el0", CPENC (3,3,C14,C10,0), 0),
4185 SR_CORE ("pmevcntr17_el0", CPENC (3,3,C14,C10,1), 0),
4186 SR_CORE ("pmevcntr18_el0", CPENC (3,3,C14,C10,2), 0),
4187 SR_CORE ("pmevcntr19_el0", CPENC (3,3,C14,C10,3), 0),
4188 SR_CORE ("pmevcntr20_el0", CPENC (3,3,C14,C10,4), 0),
4189 SR_CORE ("pmevcntr21_el0", CPENC (3,3,C14,C10,5), 0),
4190 SR_CORE ("pmevcntr22_el0", CPENC (3,3,C14,C10,6), 0),
4191 SR_CORE ("pmevcntr23_el0", CPENC (3,3,C14,C10,7), 0),
4192 SR_CORE ("pmevcntr24_el0", CPENC (3,3,C14,C11,0), 0),
4193 SR_CORE ("pmevcntr25_el0", CPENC (3,3,C14,C11,1), 0),
4194 SR_CORE ("pmevcntr26_el0", CPENC (3,3,C14,C11,2), 0),
4195 SR_CORE ("pmevcntr27_el0", CPENC (3,3,C14,C11,3), 0),
4196 SR_CORE ("pmevcntr28_el0", CPENC (3,3,C14,C11,4), 0),
4197 SR_CORE ("pmevcntr29_el0", CPENC (3,3,C14,C11,5), 0),
4198 SR_CORE ("pmevcntr30_el0", CPENC (3,3,C14,C11,6), 0),
4199 SR_CORE ("pmevtyper0_el0", CPENC (3,3,C14,C12,0), 0),
4200 SR_CORE ("pmevtyper1_el0", CPENC (3,3,C14,C12,1), 0),
4201 SR_CORE ("pmevtyper2_el0", CPENC (3,3,C14,C12,2), 0),
4202 SR_CORE ("pmevtyper3_el0", CPENC (3,3,C14,C12,3), 0),
4203 SR_CORE ("pmevtyper4_el0", CPENC (3,3,C14,C12,4), 0),
4204 SR_CORE ("pmevtyper5_el0", CPENC (3,3,C14,C12,5), 0),
4205 SR_CORE ("pmevtyper6_el0", CPENC (3,3,C14,C12,6), 0),
4206 SR_CORE ("pmevtyper7_el0", CPENC (3,3,C14,C12,7), 0),
4207 SR_CORE ("pmevtyper8_el0", CPENC (3,3,C14,C13,0), 0),
4208 SR_CORE ("pmevtyper9_el0", CPENC (3,3,C14,C13,1), 0),
4209 SR_CORE ("pmevtyper10_el0", CPENC (3,3,C14,C13,2), 0),
4210 SR_CORE ("pmevtyper11_el0", CPENC (3,3,C14,C13,3), 0),
4211 SR_CORE ("pmevtyper12_el0", CPENC (3,3,C14,C13,4), 0),
4212 SR_CORE ("pmevtyper13_el0", CPENC (3,3,C14,C13,5), 0),
4213 SR_CORE ("pmevtyper14_el0", CPENC (3,3,C14,C13,6), 0),
4214 SR_CORE ("pmevtyper15_el0", CPENC (3,3,C14,C13,7), 0),
4215 SR_CORE ("pmevtyper16_el0", CPENC (3,3,C14,C14,0), 0),
4216 SR_CORE ("pmevtyper17_el0", CPENC (3,3,C14,C14,1), 0),
4217 SR_CORE ("pmevtyper18_el0", CPENC (3,3,C14,C14,2), 0),
4218 SR_CORE ("pmevtyper19_el0", CPENC (3,3,C14,C14,3), 0),
4219 SR_CORE ("pmevtyper20_el0", CPENC (3,3,C14,C14,4), 0),
4220 SR_CORE ("pmevtyper21_el0", CPENC (3,3,C14,C14,5), 0),
4221 SR_CORE ("pmevtyper22_el0", CPENC (3,3,C14,C14,6), 0),
4222 SR_CORE ("pmevtyper23_el0", CPENC (3,3,C14,C14,7), 0),
4223 SR_CORE ("pmevtyper24_el0", CPENC (3,3,C14,C15,0), 0),
4224 SR_CORE ("pmevtyper25_el0", CPENC (3,3,C14,C15,1), 0),
4225 SR_CORE ("pmevtyper26_el0", CPENC (3,3,C14,C15,2), 0),
4226 SR_CORE ("pmevtyper27_el0", CPENC (3,3,C14,C15,3), 0),
4227 SR_CORE ("pmevtyper28_el0", CPENC (3,3,C14,C15,4), 0),
4228 SR_CORE ("pmevtyper29_el0", CPENC (3,3,C14,C15,5), 0),
4229 SR_CORE ("pmevtyper30_el0", CPENC (3,3,C14,C15,6), 0),
4230 SR_CORE ("pmccfiltr_el0", CPENC (3,3,C14,C15,7), 0),
4231
4232 SR_V8_4 ("dit", CPEN_ (3,C2,5), 0),
4233 SR_V8_4 ("vstcr_el2", CPENC (3,4,C2,C6,2), 0),
4234 SR_V8_4 ("vsttbr_el2", CPENC (3,4,C2,C6,0), 0),
4235 SR_V8_4 ("cnthvs_tval_el2", CPENC (3,4,C14,C4,0), 0),
4236 SR_V8_4 ("cnthvs_cval_el2", CPENC (3,4,C14,C4,2), 0),
4237 SR_V8_4 ("cnthvs_ctl_el2", CPENC (3,4,C14,C4,1), 0),
4238 SR_V8_4 ("cnthps_tval_el2", CPENC (3,4,C14,C5,0), 0),
4239 SR_V8_4 ("cnthps_cval_el2", CPENC (3,4,C14,C5,2), 0),
4240 SR_V8_4 ("cnthps_ctl_el2", CPENC (3,4,C14,C5,1), 0),
4241 SR_V8_4 ("sder32_el2", CPENC (3,4,C1,C3,1), 0),
4242 SR_V8_4 ("vncr_el2", CPENC (3,4,C2,C2,0), 0),
4243
2e49fd1e
AC		 4244 SR_CORE ("mpam0_el1", CPENC (3,0,C10,C5,1), 0),
4245 SR_CORE ("mpam1_el1", CPENC (3,0,C10,C5,0), 0),
4246 SR_CORE ("mpam1_el12", CPENC (3,5,C10,C5,0), 0),
4247 SR_CORE ("mpam2_el2", CPENC (3,4,C10,C5,0), 0),
4248 SR_CORE ("mpam3_el3", CPENC (3,6,C10,C5,0), 0),
4249 SR_CORE ("mpamhcr_el2", CPENC (3,4,C10,C4,0), 0),
4250 SR_CORE ("mpamidr_el1", CPENC (3,0,C10,C4,4), F_REG_READ),
4251 SR_CORE ("mpamvpm0_el2", CPENC (3,4,C10,C6,0), 0),
4252 SR_CORE ("mpamvpm1_el2", CPENC (3,4,C10,C6,1), 0),
4253 SR_CORE ("mpamvpm2_el2", CPENC (3,4,C10,C6,2), 0),
4254 SR_CORE ("mpamvpm3_el2", CPENC (3,4,C10,C6,3), 0),
4255 SR_CORE ("mpamvpm4_el2", CPENC (3,4,C10,C6,4), 0),
4256 SR_CORE ("mpamvpm5_el2", CPENC (3,4,C10,C6,5), 0),
4257 SR_CORE ("mpamvpm6_el2", CPENC (3,4,C10,C6,6), 0),
4258 SR_CORE ("mpamvpm7_el2", CPENC (3,4,C10,C6,7), 0),
4259 SR_CORE ("mpamvpmv_el2", CPENC (3,4,C10,C4,1), 0),
4260
14962256 4261 { 0, CPENC (0,0,0,0,0), 0, 0 }
a06ea964
NC		 4262};
4263
49eec193 4264bfd_boolean
f7cb161e 4265aarch64_sys_reg_deprecated_p (const uint32_t reg_flags)
49eec193 4266{
f7cb161e 4267 return (reg_flags & F_DEPRECATED) != 0;
f21cce2c
MW		 4268}
4269
793a1948
TC		 4270/* The CPENC below is fairly misleading, the fields
4271 here are not in CPENC form. They are in op2op1 form. The fields are encoded
4272 by ins_pstatefield, which just shifts the value by the width of the fields
4273 in a loop. So if you CPENC them only the first value will be set, the rest
4274 are masked out to 0. As an example. op2 = 3, op1=2. CPENC would produce a
4275 value of 0b110000000001000000 (0x30040) while what you want is
4276 0b011010 (0x1a). */
87b8eed7 4277const aarch64_sys_reg aarch64_pstatefields [] =
a06ea964 4278{
14962256
AC		 4279 SR_CORE ("spsel", 0x05, 0),
4280 SR_CORE ("daifset", 0x1e, 0),
4281 SR_CORE ("daifclr", 0x1f, 0),
4282 SR_PAN ("pan", 0x04, 0),
4283 SR_V8_2 ("uao", 0x03, 0),
4284 SR_SSBS ("ssbs", 0x19, 0),
4285 SR_V8_4 ("dit", 0x1a, 0),
4286 SR_MEMTAG ("tco", 0x1c, 0),
4287 { 0, CPENC (0,0,0,0,0), 0, 0 },
a06ea964
NC		 4288};
4289
f21cce2c
MW		 4290bfd_boolean
4291aarch64_pstatefield_supported_p (const aarch64_feature_set features,
4292 const aarch64_sys_reg *reg)
4293{
4294 if (!(reg->flags & F_ARCHEXT))
4295 return TRUE;
4296
14962256 4297 return AARCH64_CPU_HAS_ALL_FEATURES (features, reg->features);
f21cce2c
MW		 4298}
4299
a06ea964
NC		 4300const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
4301{
4302 { "ialluis", CPENS(0,C7,C1,0), 0 },
4303 { "iallu", CPENS(0,C7,C5,0), 0 },
ea2deeec 4304 { "ivau", CPENS (3, C7, C5, 1), F_HASXT },
a06ea964
NC		 4305 { 0, CPENS(0,0,0,0), 0 }
4306};
4307
4308const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
4309{
ea2deeec 4310 { "zva", CPENS (3, C7, C4, 1), F_HASXT },
3a0f69be
SD		 4311 { "gva", CPENS (3, C7, C4, 3), F_HASXT | F_ARCHEXT },
4312 { "gzva", CPENS (3, C7, C4, 4), F_HASXT | F_ARCHEXT },
ea2deeec 4313 { "ivac", CPENS (0, C7, C6, 1), F_HASXT },
3a0f69be
SD		 4314 { "igvac", CPENS (0, C7, C6, 3), F_HASXT | F_ARCHEXT },
4315 { "igsw", CPENS (0, C7, C6, 4), F_HASXT | F_ARCHEXT },
ea2deeec 4316 { "isw", CPENS (0, C7, C6, 2), F_HASXT },
3a0f69be
SD		 4317 { "igdvac", CPENS (0, C7, C6, 5), F_HASXT | F_ARCHEXT },
4318 { "igdsw", CPENS (0, C7, C6, 6), F_HASXT | F_ARCHEXT },
ea2deeec 4319 { "cvac", CPENS (3, C7, C10, 1), F_HASXT },
3a0f69be
SD		 4320 { "cgvac", CPENS (3, C7, C10, 3), F_HASXT | F_ARCHEXT },
4321 { "cgdvac", CPENS (3, C7, C10, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4322 { "csw", CPENS (0, C7, C10, 2), F_HASXT },
3a0f69be
SD		 4323 { "cgsw", CPENS (0, C7, C10, 4), F_HASXT | F_ARCHEXT },
4324 { "cgdsw", CPENS (0, C7, C10, 6), F_HASXT | F_ARCHEXT },
ea2deeec 4325 { "cvau", CPENS (3, C7, C11, 1), F_HASXT },
d6bf7ce6 4326 { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
3a0f69be
SD		 4327 { "cgvap", CPENS (3, C7, C12, 3), F_HASXT | F_ARCHEXT },
4328 { "cgdvap", CPENS (3, C7, C12, 5), F_HASXT | F_ARCHEXT },
3fd229a4 4329 { "cvadp", CPENS (3, C7, C13, 1), F_HASXT | F_ARCHEXT },
3a0f69be
SD		 4330 { "cgvadp", CPENS (3, C7, C13, 3), F_HASXT | F_ARCHEXT },
4331 { "cgdvadp", CPENS (3, C7, C13, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4332 { "civac", CPENS (3, C7, C14, 1), F_HASXT },
3a0f69be
SD		 4333 { "cigvac", CPENS (3, C7, C14, 3), F_HASXT | F_ARCHEXT },
4334 { "cigdvac", CPENS (3, C7, C14, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4335 { "cisw", CPENS (0, C7, C14, 2), F_HASXT },
3a0f69be
SD		 4336 { "cigsw", CPENS (0, C7, C14, 4), F_HASXT | F_ARCHEXT },
4337 { "cigdsw", CPENS (0, C7, C14, 6), F_HASXT | F_ARCHEXT },
a06ea964
NC		 4338 { 0, CPENS(0,0,0,0), 0 }
4339};
4340
4341const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
4342{
ea2deeec
MW		 4343 { "s1e1r", CPENS (0, C7, C8, 0), F_HASXT },
4344 { "s1e1w", CPENS (0, C7, C8, 1), F_HASXT },
4345 { "s1e0r", CPENS (0, C7, C8, 2), F_HASXT },
4346 { "s1e0w", CPENS (0, C7, C8, 3), F_HASXT },
4347 { "s12e1r", CPENS (4, C7, C8, 4), F_HASXT },
4348 { "s12e1w", CPENS (4, C7, C8, 5), F_HASXT },
4349 { "s12e0r", CPENS (4, C7, C8, 6), F_HASXT },
4350 { "s12e0w", CPENS (4, C7, C8, 7), F_HASXT },
4351 { "s1e2r", CPENS (4, C7, C8, 0), F_HASXT },
4352 { "s1e2w", CPENS (4, C7, C8, 1), F_HASXT },
4353 { "s1e3r", CPENS (6, C7, C8, 0), F_HASXT },
4354 { "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
22a5455c
MW		 4355 { "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
4356 { "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
a06ea964
NC		 4357 { 0, CPENS(0,0,0,0), 0 }
4358};
4359
4360const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
4361{
4362 { "vmalle1", CPENS(0,C8,C7,0), 0 },
ea2deeec
MW		 4363 { "vae1", CPENS (0, C8, C7, 1), F_HASXT },
4364 { "aside1", CPENS (0, C8, C7, 2), F_HASXT },
4365 { "vaae1", CPENS (0, C8, C7, 3), F_HASXT },
a06ea964 4366 { "vmalle1is", CPENS(0,C8,C3,0), 0 },
ea2deeec
MW		 4367 { "vae1is", CPENS (0, C8, C3, 1), F_HASXT },
4368 { "aside1is", CPENS (0, C8, C3, 2), F_HASXT },
4369 { "vaae1is", CPENS (0, C8, C3, 3), F_HASXT },
4370 { "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT },
4371 { "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT },
4372 { "ipas2e1", CPENS (4, C8, C4, 1), F_HASXT },
4373 { "ipas2le1", CPENS (4, C8, C4, 5), F_HASXT },
4374 { "vae2", CPENS (4, C8, C7, 1), F_HASXT },
4375 { "vae2is", CPENS (4, C8, C3, 1), F_HASXT },
a06ea964
NC		 4376 { "vmalls12e1",CPENS(4,C8,C7,6), 0 },
4377 { "vmalls12e1is",CPENS(4,C8,C3,6), 0 },
ea2deeec
MW		 4378 { "vae3", CPENS (6, C8, C7, 1), F_HASXT },
4379 { "vae3is", CPENS (6, C8, C3, 1), F_HASXT },
a06ea964
NC		 4380 { "alle2", CPENS(4,C8,C7,0), 0 },
4381 { "alle2is", CPENS(4,C8,C3,0), 0 },
4382 { "alle1", CPENS(4,C8,C7,4), 0 },
4383 { "alle1is", CPENS(4,C8,C3,4), 0 },
4384 { "alle3", CPENS(6,C8,C7,0), 0 },
4385 { "alle3is", CPENS(6,C8,C3,0), 0 },
ea2deeec
MW		 4386 { "vale1is", CPENS (0, C8, C3, 5), F_HASXT },
4387 { "vale2is", CPENS (4, C8, C3, 5), F_HASXT },
4388 { "vale3is", CPENS (6, C8, C3, 5), F_HASXT },
4389 { "vaale1is", CPENS (0, C8, C3, 7), F_HASXT },
4390 { "vale1", CPENS (0, C8, C7, 5), F_HASXT },
4391 { "vale2", CPENS (4, C8, C7, 5), F_HASXT },
4392 { "vale3", CPENS (6, C8, C7, 5), F_HASXT },
4393 { "vaale1", CPENS (0, C8, C7, 7), F_HASXT },
793a1948
TC		 4394
4395 { "vmalle1os", CPENS (0, C8, C1, 0), F_ARCHEXT },
4396 { "vae1os", CPENS (0, C8, C1, 1), F_HASXT | F_ARCHEXT },
4397 { "aside1os", CPENS (0, C8, C1, 2), F_HASXT | F_ARCHEXT },
4398 { "vaae1os", CPENS (0, C8, C1, 3), F_HASXT | F_ARCHEXT },
4399 { "vale1os", CPENS (0, C8, C1, 5), F_HASXT | F_ARCHEXT },
4400 { "vaale1os", CPENS (0, C8, C1, 7), F_HASXT | F_ARCHEXT },
4401 { "ipas2e1os", CPENS (4, C8, C4, 0), F_HASXT | F_ARCHEXT },
4402 { "ipas2le1os", CPENS (4, C8, C4, 4), F_HASXT | F_ARCHEXT },
4403 { "vae2os", CPENS (4, C8, C1, 1), F_HASXT | F_ARCHEXT },
4404 { "vale2os", CPENS (4, C8, C1, 5), F_HASXT | F_ARCHEXT },
4405 { "vmalls12e1os", CPENS (4, C8, C1, 6), F_ARCHEXT },
4406 { "vae3os", CPENS (6, C8, C1, 1), F_HASXT | F_ARCHEXT },
4407 { "vale3os", CPENS (6, C8, C1, 5), F_HASXT | F_ARCHEXT },
4408 { "alle2os", CPENS (4, C8, C1, 0), F_ARCHEXT },
4409 { "alle1os", CPENS (4, C8, C1, 4), F_ARCHEXT },
4410 { "alle3os", CPENS (6, C8, C1, 0), F_ARCHEXT },
4411
4412 { "rvae1", CPENS (0, C8, C6, 1), F_HASXT | F_ARCHEXT },
4413 { "rvaae1", CPENS (0, C8, C6, 3), F_HASXT | F_ARCHEXT },
4414 { "rvale1", CPENS (0, C8, C6, 5), F_HASXT | F_ARCHEXT },
4415 { "rvaale1", CPENS (0, C8, C6, 7), F_HASXT | F_ARCHEXT },
4416 { "rvae1is", CPENS (0, C8, C2, 1), F_HASXT | F_ARCHEXT },
4417 { "rvaae1is", CPENS (0, C8, C2, 3), F_HASXT | F_ARCHEXT },
4418 { "rvale1is", CPENS (0, C8, C2, 5), F_HASXT | F_ARCHEXT },
4419 { "rvaale1is", CPENS (0, C8, C2, 7), F_HASXT | F_ARCHEXT },
4420 { "rvae1os", CPENS (0, C8, C5, 1), F_HASXT | F_ARCHEXT },
4421 { "rvaae1os", CPENS (0, C8, C5, 3), F_HASXT | F_ARCHEXT },
4422 { "rvale1os", CPENS (0, C8, C5, 5), F_HASXT | F_ARCHEXT },
4423 { "rvaale1os", CPENS (0, C8, C5, 7), F_HASXT | F_ARCHEXT },
4424 { "ripas2e1is", CPENS (4, C8, C0, 2), F_HASXT | F_ARCHEXT },
4425 { "ripas2le1is",CPENS (4, C8, C0, 6), F_HASXT | F_ARCHEXT },
4426 { "ripas2e1", CPENS (4, C8, C4, 2), F_HASXT | F_ARCHEXT },
4427 { "ripas2le1", CPENS (4, C8, C4, 6), F_HASXT | F_ARCHEXT },
4428 { "ripas2e1os", CPENS (4, C8, C4, 3), F_HASXT | F_ARCHEXT },
4429 { "ripas2le1os",CPENS (4, C8, C4, 7), F_HASXT | F_ARCHEXT },
4430 { "rvae2", CPENS (4, C8, C6, 1), F_HASXT | F_ARCHEXT },
4431 { "rvale2", CPENS (4, C8, C6, 5), F_HASXT | F_ARCHEXT },
4432 { "rvae2is", CPENS (4, C8, C2, 1), F_HASXT | F_ARCHEXT },
4433 { "rvale2is", CPENS (4, C8, C2, 5), F_HASXT | F_ARCHEXT },
4434 { "rvae2os", CPENS (4, C8, C5, 1), F_HASXT | F_ARCHEXT },
4435 { "rvale2os", CPENS (4, C8, C5, 5), F_HASXT | F_ARCHEXT },
4436 { "rvae3", CPENS (6, C8, C6, 1), F_HASXT | F_ARCHEXT },
4437 { "rvale3", CPENS (6, C8, C6, 5), F_HASXT | F_ARCHEXT },
4438 { "rvae3is", CPENS (6, C8, C2, 1), F_HASXT | F_ARCHEXT },
4439 { "rvale3is", CPENS (6, C8, C2, 5), F_HASXT | F_ARCHEXT },
4440 { "rvae3os", CPENS (6, C8, C5, 1), F_HASXT | F_ARCHEXT },
4441 { "rvale3os", CPENS (6, C8, C5, 5), F_HASXT | F_ARCHEXT },
4442
a06ea964
NC		 4443 { 0, CPENS(0,0,0,0), 0 }
4444};
4445
2ac435d4
SD		 4446const aarch64_sys_ins_reg aarch64_sys_regs_sr[] =
4447{
4448 /* RCTX is somewhat unique in a way that it has different values
4449 (op2) based on the instruction in which it is used (cfp/dvp/cpp).
4450 Thus op2 is masked out and instead encoded directly in the
4451 aarch64_opcode_table entries for the respective instructions. */
4452 { "rctx", CPENS(3,C7,C3,0), F_HASXT | F_ARCHEXT | F_REG_WRITE}, /* WO */
4453
4454 { 0, CPENS(0,0,0,0), 0 }
4455};
4456
ea2deeec
MW		 4457bfd_boolean
4458aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
4459{
4460 return (sys_ins_reg->flags & F_HASXT) != 0;
4461}
4462
d6bf7ce6
MW		 4463extern bfd_boolean
4464aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
f7cb161e
PW		 4465 aarch64_insn reg_value,
4466 uint32_t reg_flags,
4467 aarch64_feature_set reg_features)
d6bf7ce6 4468{
f7cb161e
PW		 4469
4470 if (!(reg_flags & F_ARCHEXT))
4471 return TRUE;
4472
4473 if (reg_features
4474 && AARCH64_CPU_HAS_ALL_FEATURES (features, reg_features))
4475 return TRUE;
4476
4477 /* ARMv8.4 TLB instructions. */
4478 if ((reg_value == CPENS (0, C8, C1, 0)
4479 || reg_value == CPENS (0, C8, C1, 1)
4480 || reg_value == CPENS (0, C8, C1, 2)
4481 || reg_value == CPENS (0, C8, C1, 3)
4482 || reg_value == CPENS (0, C8, C1, 5)
4483 || reg_value == CPENS (0, C8, C1, 7)
4484 || reg_value == CPENS (4, C8, C4, 0)
4485 || reg_value == CPENS (4, C8, C4, 4)
4486 || reg_value == CPENS (4, C8, C1, 1)
4487 || reg_value == CPENS (4, C8, C1, 5)
4488 || reg_value == CPENS (4, C8, C1, 6)
4489 || reg_value == CPENS (6, C8, C1, 1)
4490 || reg_value == CPENS (6, C8, C1, 5)
4491 || reg_value == CPENS (4, C8, C1, 0)
4492 || reg_value == CPENS (4, C8, C1, 4)
4493 || reg_value == CPENS (6, C8, C1, 0)
4494 || reg_value == CPENS (0, C8, C6, 1)
4495 || reg_value == CPENS (0, C8, C6, 3)
4496 || reg_value == CPENS (0, C8, C6, 5)
4497 || reg_value == CPENS (0, C8, C6, 7)
4498 || reg_value == CPENS (0, C8, C2, 1)
4499 || reg_value == CPENS (0, C8, C2, 3)
4500 || reg_value == CPENS (0, C8, C2, 5)
4501 || reg_value == CPENS (0, C8, C2, 7)
4502 || reg_value == CPENS (0, C8, C5, 1)
4503 || reg_value == CPENS (0, C8, C5, 3)
4504 || reg_value == CPENS (0, C8, C5, 5)
4505 || reg_value == CPENS (0, C8, C5, 7)
4506 || reg_value == CPENS (4, C8, C0, 2)
4507 || reg_value == CPENS (4, C8, C0, 6)
4508 || reg_value == CPENS (4, C8, C4, 2)
4509 || reg_value == CPENS (4, C8, C4, 6)
4510 || reg_value == CPENS (4, C8, C4, 3)
4511 || reg_value == CPENS (4, C8, C4, 7)
4512 || reg_value == CPENS (4, C8, C6, 1)
4513 || reg_value == CPENS (4, C8, C6, 5)
4514 || reg_value == CPENS (4, C8, C2, 1)
4515 || reg_value == CPENS (4, C8, C2, 5)
4516 || reg_value == CPENS (4, C8, C5, 1)
4517 || reg_value == CPENS (4, C8, C5, 5)
4518 || reg_value == CPENS (6, C8, C6, 1)
4519 || reg_value == CPENS (6, C8, C6, 5)
4520 || reg_value == CPENS (6, C8, C2, 1)
4521 || reg_value == CPENS (6, C8, C2, 5)
4522 || reg_value == CPENS (6, C8, C5, 1)
4523 || reg_value == CPENS (6, C8, C5, 5))
4524 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
d6bf7ce6
MW		 4525 return TRUE;
4526
4527 /* DC CVAP. Values are from aarch64_sys_regs_dc. */
f7cb161e
PW		 4528 if (reg_value == CPENS (3, C7, C12, 1)
4529 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4530 return TRUE;
d6bf7ce6 4531
3fd229a4 4532 /* DC CVADP. Values are from aarch64_sys_regs_dc. */
f7cb161e
PW		 4533 if (reg_value == CPENS (3, C7, C13, 1)
4534 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
4535 return TRUE;
3fd229a4 4536
3a0f69be 4537 /* DC <dc_op> for ARMv8.5-A Memory Tagging Extension. */
f7cb161e
PW		 4538 if ((reg_value == CPENS (0, C7, C6, 3)
4539 || reg_value == CPENS (0, C7, C6, 4)
4540 || reg_value == CPENS (0, C7, C10, 4)
4541 || reg_value == CPENS (0, C7, C14, 4)
4542 || reg_value == CPENS (3, C7, C10, 3)
4543 || reg_value == CPENS (3, C7, C12, 3)
4544 || reg_value == CPENS (3, C7, C13, 3)
4545 || reg_value == CPENS (3, C7, C14, 3)
4546 || reg_value == CPENS (3, C7, C4, 3)
4547 || reg_value == CPENS (0, C7, C6, 5)
4548 || reg_value == CPENS (0, C7, C6, 6)
4549 || reg_value == CPENS (0, C7, C10, 6)
4550 || reg_value == CPENS (0, C7, C14, 6)
4551 || reg_value == CPENS (3, C7, C10, 5)
4552 || reg_value == CPENS (3, C7, C12, 5)
4553 || reg_value == CPENS (3, C7, C13, 5)
4554 || reg_value == CPENS (3, C7, C14, 5)
4555 || reg_value == CPENS (3, C7, C4, 4))
4556 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
4557 return TRUE;
3a0f69be 4558
63511907 4559 /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
f7cb161e
PW		 4560 if ((reg_value == CPENS (0, C7, C9, 0)
4561 || reg_value == CPENS (0, C7, C9, 1))
4562 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4563 return TRUE;
63511907 4564
2ac435d4 4565 /* CFP/DVP/CPP RCTX : Value are from aarch64_sys_regs_sr. */
f7cb161e
PW		 4566 if (reg_value == CPENS (3, C7, C3, 0)
4567 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PREDRES))
4568 return TRUE;
2ac435d4 4569
f7cb161e 4570 return FALSE;
d6bf7ce6
MW		 4571}
4572
a06ea964
NC		 4573#undef C0
4574#undef C1
4575#undef C2
4576#undef C3
4577#undef C4
4578#undef C5
4579#undef C6
4580#undef C7
4581#undef C8
4582#undef C9
4583#undef C10
4584#undef C11
4585#undef C12
4586#undef C13
4587#undef C14
4588#undef C15
4589
4bd13cde
NC		 4590#define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
4591#define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
4592
755b748f
TC		 4593static enum err_type
4594verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED,
4595 const aarch64_insn insn, bfd_vma pc ATTRIBUTE_UNUSED,
4596 bfd_boolean encoding ATTRIBUTE_UNUSED,
4597 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
a68f4cd2 4598 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
4bd13cde
NC		 4599{
4600 int t = BITS (insn, 4, 0);
4601 int n = BITS (insn, 9, 5);
4602 int t2 = BITS (insn, 14, 10);
4603
4604 if (BIT (insn, 23))
4605 {
4606 /* Write back enabled. */
4607 if ((t == n || t2 == n) && n != 31)
755b748f 4608 return ERR_UND;
4bd13cde
NC		 4609 }
4610
4611 if (BIT (insn, 22))
4612 {
4613 /* Load */
4614 if (t == t2)
755b748f 4615 return ERR_UND;
4bd13cde
NC		 4616 }
4617
755b748f 4618 return ERR_OK;
4bd13cde
NC		 4619}
4620
6456d318
TC		 4621/* Verifier for vector by element 3 operands functions where the
4622 conditions `if sz:L == 11 then UNDEFINED` holds. */
4623
4624static enum err_type
4625verify_elem_sd (const struct aarch64_inst *inst, const aarch64_insn insn,
4626 bfd_vma pc ATTRIBUTE_UNUSED, bfd_boolean encoding,
4627 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
4628 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
4629{
4630 const aarch64_insn undef_pattern = 0x3;
4631 aarch64_insn value;
4632
4633 assert (inst->opcode);
4634 assert (inst->opcode->operands[2] == AARCH64_OPND_Em);
4635 value = encoding ? inst->value : insn;
4636 assert (value);
4637
4638 if (undef_pattern == extract_fields (value, 0, 2, FLD_sz, FLD_L))
4639 return ERR_UND;
4640
4641 return ERR_OK;
4642}
4643
a68f4cd2
TC		 4644/* Initialize an instruction sequence insn_sequence with the instruction INST.
4645 If INST is NULL the given insn_sequence is cleared and the sequence is left
4646 uninitialized. */
4647
4648void
4649init_insn_sequence (const struct aarch64_inst *inst,
4650 aarch64_instr_sequence *insn_sequence)
4651{
4652 int num_req_entries = 0;
4653 insn_sequence->next_insn = 0;
4654 insn_sequence->num_insns = num_req_entries;
4655 if (insn_sequence->instr)
4656 XDELETE (insn_sequence->instr);
4657 insn_sequence->instr = NULL;
4658
4659 if (inst)
4660 {
4661 insn_sequence->instr = XNEW (aarch64_inst);
4662 memcpy (insn_sequence->instr, inst, sizeof (aarch64_inst));
4663 }
4664
4665 /* Handle all the cases here. May need to think of something smarter than
4666 a giant if/else chain if this grows. At that time, a lookup table may be
4667 best. */
4668 if (inst && inst->opcode->constraints & C_SCAN_MOVPRFX)
4669 num_req_entries = 1;
4670
4671 if (insn_sequence->current_insns)
4672 XDELETEVEC (insn_sequence->current_insns);
4673 insn_sequence->current_insns = NULL;
4674
4675 if (num_req_entries != 0)
4676 {
4677 size_t size = num_req_entries * sizeof (aarch64_inst);
4678 insn_sequence->current_insns
4679 = (aarch64_inst**) XNEWVEC (aarch64_inst, num_req_entries);
4680 memset (insn_sequence->current_insns, 0, size);
4681 }
4682}
4683
4684
4685/* This function verifies that the instruction INST adheres to its specified
4686 constraints. If it does then ERR_OK is returned, if not then ERR_VFI is
4687 returned and MISMATCH_DETAIL contains the reason why verification failed.
4688
4689 The function is called both during assembly and disassembly. If assembling
4690 then ENCODING will be TRUE, else FALSE. If dissassembling PC will be set
4691 and will contain the PC of the current instruction w.r.t to the section.
4692
4693 If ENCODING and PC=0 then you are at a start of a section. The constraints
4694 are verified against the given state insn_sequence which is updated as it
4695 transitions through the verification. */
4696
4697enum err_type
4698verify_constraints (const struct aarch64_inst *inst,
4699 const aarch64_insn insn ATTRIBUTE_UNUSED,
4700 bfd_vma pc,
4701 bfd_boolean encoding,
4702 aarch64_operand_error *mismatch_detail,
4703 aarch64_instr_sequence *insn_sequence)
4704{
4705 assert (inst);
4706 assert (inst->opcode);
4707
4708 const struct aarch64_opcode *opcode = inst->opcode;
4709 if (!opcode->constraints && !insn_sequence->instr)
4710 return ERR_OK;
4711
4712 assert (insn_sequence);
4713
4714 enum err_type res = ERR_OK;
4715
4716 /* This instruction puts a constraint on the insn_sequence. */
4717 if (opcode->flags & F_SCAN)
4718 {
4719 if (insn_sequence->instr)
4720 {
4721 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4722 mismatch_detail->error = _("instruction opens new dependency "
4723 "sequence without ending previous one");
4724 mismatch_detail->index = -1;
4725 mismatch_detail->non_fatal = TRUE;
4726 res = ERR_VFI;
4727 }
4728
4729 init_insn_sequence (inst, insn_sequence);
4730 return res;
4731 }
4732
4733 /* Verify constraints on an existing sequence. */
4734 if (insn_sequence->instr)
4735 {
4736 const struct aarch64_opcode* inst_opcode = insn_sequence->instr->opcode;
4737 /* If we're decoding and we hit PC=0 with an open sequence then we haven't
4738 closed a previous one that we should have. */
4739 if (!encoding && pc == 0)
4740 {
4741 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4742 mismatch_detail->error = _("previous `movprfx' sequence not closed");
4743 mismatch_detail->index = -1;
4744 mismatch_detail->non_fatal = TRUE;
4745 res = ERR_VFI;
4746 /* Reset the sequence. */
4747 init_insn_sequence (NULL, insn_sequence);
4748 return res;
4749 }
4750
4751 /* Validate C_SCAN_MOVPRFX constraints. Move this to a lookup table. */
4752 if (inst_opcode->constraints & C_SCAN_MOVPRFX)
4753 {
4754 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4755 instruction for better error messages. */
5cd99750
MM		 4756 if (!opcode->avariant
4757 || !(*opcode->avariant &
4758 (AARCH64_FEATURE_SVE | AARCH64_FEATURE_SVE2)))
a68f4cd2
TC		 4759 {
4760 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4761 mismatch_detail->error = _("SVE instruction expected after "
4762 "`movprfx'");
4763 mismatch_detail->index = -1;
4764 mismatch_detail->non_fatal = TRUE;
4765 res = ERR_VFI;
4766 goto done;
4767 }
4768
4769 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4770 instruction that is allowed to be used with a MOVPRFX. */
4771 if (!(opcode->constraints & C_SCAN_MOVPRFX))
4772 {
4773 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4774 mismatch_detail->error = _("SVE `movprfx' compatible instruction "
4775 "expected");
4776 mismatch_detail->index = -1;
4777 mismatch_detail->non_fatal = TRUE;
4778 res = ERR_VFI;
4779 goto done;
4780 }
4781
4782 /* Next check for usage of the predicate register. */
4783 aarch64_opnd_info blk_dest = insn_sequence->instr->operands[0];
780f601c
TC		 4784 aarch64_opnd_info blk_pred, inst_pred;
4785 memset (&blk_pred, 0, sizeof (aarch64_opnd_info));
4786 memset (&inst_pred, 0, sizeof (aarch64_opnd_info));
a68f4cd2
TC		 4787 bfd_boolean predicated = FALSE;
4788 assert (blk_dest.type == AARCH64_OPND_SVE_Zd);
4789
4790 /* Determine if the movprfx instruction used is predicated or not. */
4791 if (insn_sequence->instr->operands[1].type == AARCH64_OPND_SVE_Pg3)
4792 {
4793 predicated = TRUE;
4794 blk_pred = insn_sequence->instr->operands[1];
4795 }
4796
4797 unsigned char max_elem_size = 0;
4798 unsigned char current_elem_size;
4799 int num_op_used = 0, last_op_usage = 0;
4800 int i, inst_pred_idx = -1;
4801 int num_ops = aarch64_num_of_operands (opcode);
4802 for (i = 0; i < num_ops; i++)
4803 {
4804 aarch64_opnd_info inst_op = inst->operands[i];
4805 switch (inst_op.type)
4806 {
4807 case AARCH64_OPND_SVE_Zd:
4808 case AARCH64_OPND_SVE_Zm_5:
4809 case AARCH64_OPND_SVE_Zm_16:
4810 case AARCH64_OPND_SVE_Zn:
4811 case AARCH64_OPND_SVE_Zt:
4812 case AARCH64_OPND_SVE_Vm:
4813 case AARCH64_OPND_SVE_Vn:
4814 case AARCH64_OPND_Va:
4815 case AARCH64_OPND_Vn:
4816 case AARCH64_OPND_Vm:
4817 case AARCH64_OPND_Sn:
4818 case AARCH64_OPND_Sm:
a68f4cd2
TC		 4819 if (inst_op.reg.regno == blk_dest.reg.regno)
4820 {
4821 num_op_used++;
4822 last_op_usage = i;
4823 }
4824 current_elem_size
4825 = aarch64_get_qualifier_esize (inst_op.qualifier);
4826 if (current_elem_size > max_elem_size)
4827 max_elem_size = current_elem_size;
4828 break;
4829 case AARCH64_OPND_SVE_Pd:
4830 case AARCH64_OPND_SVE_Pg3:
4831 case AARCH64_OPND_SVE_Pg4_5:
4832 case AARCH64_OPND_SVE_Pg4_10:
4833 case AARCH64_OPND_SVE_Pg4_16:
4834 case AARCH64_OPND_SVE_Pm:
4835 case AARCH64_OPND_SVE_Pn:
4836 case AARCH64_OPND_SVE_Pt:
4837 inst_pred = inst_op;
4838 inst_pred_idx = i;
4839 break;
4840 default:
4841 break;
4842 }
4843 }
4844
4845 assert (max_elem_size != 0);
4846 aarch64_opnd_info inst_dest = inst->operands[0];
4847 /* Determine the size that should be used to compare against the
4848 movprfx size. */
4849 current_elem_size
4850 = opcode->constraints & C_MAX_ELEM
4851 ? max_elem_size
4852 : aarch64_get_qualifier_esize (inst_dest.qualifier);
4853
4854 /* If movprfx is predicated do some extra checks. */
4855 if (predicated)
4856 {
4857 /* The instruction must be predicated. */
4858 if (inst_pred_idx < 0)
4859 {
4860 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4861 mismatch_detail->error = _("predicated instruction expected "
4862 "after `movprfx'");
4863 mismatch_detail->index = -1;
4864 mismatch_detail->non_fatal = TRUE;
4865 res = ERR_VFI;
4866 goto done;
4867 }
4868
4869 /* The instruction must have a merging predicate. */
4870 if (inst_pred.qualifier != AARCH64_OPND_QLF_P_M)
4871 {
4872 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4873 mismatch_detail->error = _("merging predicate expected due "
4874 "to preceding `movprfx'");
4875 mismatch_detail->index = inst_pred_idx;
4876 mismatch_detail->non_fatal = TRUE;
4877 res = ERR_VFI;
4878 goto done;
4879 }
4880
4881 /* The same register must be used in instruction. */
4882 if (blk_pred.reg.regno != inst_pred.reg.regno)
4883 {
4884 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4885 mismatch_detail->error = _("predicate register differs "
4886 "from that in preceding "
4887 "`movprfx'");
4888 mismatch_detail->index = inst_pred_idx;
4889 mismatch_detail->non_fatal = TRUE;
4890 res = ERR_VFI;
4891 goto done;
4892 }
4893 }
4894
4895 /* Destructive operations by definition must allow one usage of the
4896 same register. */
4897 int allowed_usage
4898 = aarch64_is_destructive_by_operands (opcode) ? 2 : 1;
4899
4900 /* Operand is not used at all. */
4901 if (num_op_used == 0)
4902 {
4903 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4904 mismatch_detail->error = _("output register of preceding "
4905 "`movprfx' not used in current "
4906 "instruction");
4907 mismatch_detail->index = 0;
4908 mismatch_detail->non_fatal = TRUE;
4909 res = ERR_VFI;
4910 goto done;
4911 }
4912
4913 /* We now know it's used, now determine exactly where it's used. */
4914 if (blk_dest.reg.regno != inst_dest.reg.regno)
4915 {
4916 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4917 mismatch_detail->error = _("output register of preceding "
4918 "`movprfx' expected as output");
4919 mismatch_detail->index = 0;
4920 mismatch_detail->non_fatal = TRUE;
4921 res = ERR_VFI;
4922 goto done;
4923 }
4924
4925 /* Operand used more than allowed for the specific opcode type. */
4926 if (num_op_used > allowed_usage)
4927 {
4928 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4929 mismatch_detail->error = _("output register of preceding "
4930 "`movprfx' used as input");
4931 mismatch_detail->index = last_op_usage;
4932 mismatch_detail->non_fatal = TRUE;
4933 res = ERR_VFI;
4934 goto done;
4935 }
4936
4937 /* Now the only thing left is the qualifiers checks. The register
4938 must have the same maximum element size. */
4939 if (inst_dest.qualifier
4940 && blk_dest.qualifier
4941 && current_elem_size
4942 != aarch64_get_qualifier_esize (blk_dest.qualifier))
4943 {
4944 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4945 mismatch_detail->error = _("register size not compatible with "
4946 "previous `movprfx'");
4947 mismatch_detail->index = 0;
4948 mismatch_detail->non_fatal = TRUE;
4949 res = ERR_VFI;
4950 goto done;
4951 }
4952 }
4953
dc1e8a47 4954 done:
a68f4cd2
TC		 4955 /* Add the new instruction to the sequence. */
4956 memcpy (insn_sequence->current_insns + insn_sequence->next_insn++,
4957 inst, sizeof (aarch64_inst));
4958
4959 /* Check if sequence is now full. */
4960 if (insn_sequence->next_insn >= insn_sequence->num_insns)
4961 {
4962 /* Sequence is full, but we don't have anything special to do for now,
4963 so clear and reset it. */
4964 init_insn_sequence (NULL, insn_sequence);
4965 }
4966 }
4967
4968 return res;
4969}
4970
4971
e950b345
RS		 4972/* Return true if VALUE cannot be moved into an SVE register using DUP
4973 (with any element size, not just ESIZE) and if using DUPM would
4974 therefore be OK. ESIZE is the number of bytes in the immediate. */
4975
4976bfd_boolean
4977aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, int esize)
4978{
4979 int64_t svalue = uvalue;
4980 uint64_t upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
4981
4982 if ((uvalue & ~upper) != uvalue && (uvalue | upper) != uvalue)
4983 return FALSE;
4984 if (esize <= 4 || (uint32_t) uvalue == (uint32_t) (uvalue >> 32))
4985 {
4986 svalue = (int32_t) uvalue;
4987 if (esize <= 2 || (uint16_t) uvalue == (uint16_t) (uvalue >> 16))
4988 {
4989 svalue = (int16_t) uvalue;
4990 if (esize == 1 || (uint8_t) uvalue == (uint8_t) (uvalue >> 8))
4991 return FALSE;
4992 }
4993 }
4994 if ((svalue & 0xff) == 0)
4995 svalue /= 256;
4996 return svalue < -128 || svalue >= 128;
4997}
4998
a06ea964
NC		 4999/* Include the opcode description table as well as the operand description
5000 table. */
20f55f38 5001#define VERIFIER(x) verify_##x
a06ea964 5002#include "aarch64-tbl.h"
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