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[thirdparty/binutils-gdb.git] / opcodes / arm-dis.c
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252b5132 1/* Instruction printing code for the ARM
250d07de 2 Copyright (C) 1994-2021 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
6b5d3a4d 42/* FIXME: Belongs in global header. */
01c7f630 43#ifndef strneq
58efb6c0
NC		 44#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
1fbaefec
PB		 60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
796d6298
TC		 65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
1fbaefec 68 bfd_vma last_mapping_addr;
b0e28b39
DJ		 69};
70
73cd51e5
AV		 71enum mve_instructions
72{
143275ea
AV		 73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
9743db03
AV		 90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
04d54ace
AV		 101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
aef6d006
AV		 105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
ef1576a1
AV		 115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
c507f10b
AV		 132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
14925797
AV		 147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
d3b63143
AV		 155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
1c8f2df8
AV		 178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
897b9bbc
AV		 182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
ed63aa17
AV		 187 MVE_VQRSHL_T1,
188 MVE_VQRSHL_T2,
189 MVE_VQRSHRN,
190 MVE_VQRSHRUN,
191 MVE_VQSHL_T1,
192 MVE_VQSHL_T2,
193 MVE_VQSHLU_T3,
194 MVE_VQSHL_T4,
195 MVE_VQSHRN,
196 MVE_VQSHRUN,
197 MVE_VRSHL_T1,
198 MVE_VRSHL_T2,
199 MVE_VRSHR,
200 MVE_VRSHRN,
201 MVE_VSHL_T1,
202 MVE_VSHL_T2,
203 MVE_VSHL_T3,
204 MVE_VSHLC,
205 MVE_VSHLL_T1,
206 MVE_VSHLL_T2,
207 MVE_VSHR,
208 MVE_VSHRN,
209 MVE_VSLI,
210 MVE_VSRI,
66dcaa5d
AV		 211 MVE_VADC,
212 MVE_VABAV,
213 MVE_VABD_FP,
214 MVE_VABD_VEC,
215 MVE_VABS_FP,
216 MVE_VABS_VEC,
217 MVE_VADD_FP_T1,
218 MVE_VADD_FP_T2,
219 MVE_VADD_VEC_T1,
220 MVE_VADD_VEC_T2,
221 MVE_VSBC,
222 MVE_VSUB_FP_T1,
223 MVE_VSUB_FP_T2,
224 MVE_VSUB_VEC_T1,
225 MVE_VSUB_VEC_T2,
e523f101
AV		 226 MVE_VAND,
227 MVE_VBRSR,
228 MVE_VCLS,
229 MVE_VCLZ,
230 MVE_VCTP,
56858bea
AV		 231 MVE_VMAX,
232 MVE_VMAXA,
233 MVE_VMAXNM_FP,
234 MVE_VMAXNMA_FP,
235 MVE_VMAXNMV_FP,
236 MVE_VMAXNMAV_FP,
237 MVE_VMAXV,
238 MVE_VMAXAV,
239 MVE_VMIN,
240 MVE_VMINA,
241 MVE_VMINNM_FP,
242 MVE_VMINNMA_FP,
243 MVE_VMINNMV_FP,
244 MVE_VMINNMAV_FP,
245 MVE_VMINV,
246 MVE_VMINAV,
247 MVE_VMLA,
f49bb598
AV		 248 MVE_VMUL_FP_T1,
249 MVE_VMUL_FP_T2,
250 MVE_VMUL_VEC_T1,
251 MVE_VMUL_VEC_T2,
252 MVE_VMULH,
253 MVE_VRMULH,
254 MVE_VNEG_FP,
255 MVE_VNEG_VEC,
14b456f2
AV		 256 MVE_VPNOT,
257 MVE_VPSEL,
258 MVE_VQABS,
259 MVE_VQADD_T1,
260 MVE_VQADD_T2,
261 MVE_VQSUB_T1,
262 MVE_VQSUB_T2,
263 MVE_VQNEG,
264 MVE_VREV16,
265 MVE_VREV32,
266 MVE_VREV64,
23d00a41
SD		 267 MVE_LSLL,
268 MVE_LSLLI,
269 MVE_LSRL,
270 MVE_ASRL,
271 MVE_ASRLI,
272 MVE_SQRSHRL,
273 MVE_SQRSHR,
274 MVE_UQRSHL,
275 MVE_UQRSHLL,
276 MVE_UQSHL,
277 MVE_UQSHLL,
278 MVE_URSHRL,
279 MVE_URSHR,
280 MVE_SRSHRL,
281 MVE_SRSHR,
282 MVE_SQSHLL,
283 MVE_SQSHL,
e39c1607
SD		 284 MVE_CINC,
285 MVE_CINV,
286 MVE_CNEG,
287 MVE_CSINC,
288 MVE_CSINV,
289 MVE_CSET,
290 MVE_CSETM,
291 MVE_CSNEG,
292 MVE_CSEL,
73cd51e5
AV		 293 MVE_NONE
294};
295
296enum mve_unpredictable
297{
298 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
299 */
143275ea
AV		 300 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
301 fcB = 1 (vpt). */
302 UNPRED_R13, /* Unpredictable because r13 (sp) or
303 r15 (sp) used. */
9743db03 304 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 305 UNPRED_Q_GT_4, /* Unpredictable because
306 vec reg start > 4 (vld4/st4). */
307 UNPRED_Q_GT_6, /* Unpredictable because
308 vec reg start > 6 (vld2/st2). */
309 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
310 and WB bit = 1. */
ef1576a1
AV		 311 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
312 equal. */
313 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 314 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
315 same. */
c507f10b
AV		 316 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
317 size = 1. */
318 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
319 size = 2. */
73cd51e5
AV		 320 UNPRED_NONE /* No unpredictable behavior. */
321};
322
323enum mve_undefined
324{
ed63aa17 325 UNDEF_SIZE, /* undefined size. */
bf0b396d 326 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 327 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 328 UNDEF_SIZE_3, /* undefined because size == 3. */
329 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
14b456f2 330 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
ef1576a1
AV		 331 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
332 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
333 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
334 size == 0. */
335 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
336 size == 1. */
337 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 338 UNDEF_VCVT_IMM6, /* imm6 < 32. */
339 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 340 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
341 op1 == (0 or 1). */
342 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
343 op2 == 0 and op1 == (0 or 1). */
344 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
345 in {0xx1, x0x1}. */
d3b63143 346 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 347 UNDEF_NONE /* no undefined behavior. */
348};
349
6b5d3a4d
ZW		 350struct opcode32
351{
823d2571
TG		 352 arm_feature_set arch; /* Architecture defining this insn. */
353 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 354 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 355 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 356};
357
4934a27c
MM		 358struct cdeopcode32
359{
360 arm_feature_set arch; /* Architecture defining this insn. */
361 uint8_t coproc_shift; /* coproc is this far into op. */
362 uint16_t coproc_mask; /* Length of coproc field in op. */
363 unsigned long value; /* If arch is 0 then value is a sentinel. */
364 unsigned long mask; /* Recognise insn if (op & mask) == value. */
365 const char * assembler; /* How to disassemble this insn. */
366};
367
73cd51e5
AV		 368/* MVE opcodes. */
369
370struct mopcode32
371{
372 arm_feature_set arch; /* Architecture defining this insn. */
373 enum mve_instructions mve_op; /* Specific mve instruction for faster
374 decoding. */
375 unsigned long value; /* If arch is 0 then value is a sentinel. */
376 unsigned long mask; /* Recognise insn if (op & mask) == value. */
377 const char * assembler; /* How to disassemble this insn. */
378};
379
6b0dd094
AV		 380enum isa {
381 ANY,
382 T32,
383 ARM
384};
385
386
387/* Shared (between Arm and Thumb mode) opcode. */
388struct sopcode32
389{
390 enum isa isa; /* Execution mode instruction availability. */
391 arm_feature_set arch; /* Architecture defining this insn. */
392 unsigned long value; /* If arch is 0 then value is a sentinel. */
393 unsigned long mask; /* Recognise insn if (op & mask) == value. */
394 const char * assembler; /* How to disassemble this insn. */
395};
396
6b5d3a4d
ZW		 397struct opcode16
398{
823d2571 399 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 400 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 401 const char *assembler; /* How to disassemble this insn. */
402};
b7693d02 403
8f06b2d8 404/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 405
2fbad815 406 %% %
4a5329c6 407
c22aaad1 408 %c print condition code (always bits 28-31 in ARM mode)
aab2c27d 409 %b print condition code allowing cp_num == 9
37b37b2d 410 %q print shifter argument
e2efe87d
MGD		 411 %u print condition code (unconditional in ARM mode,
412 UNPREDICTABLE if not AL in Thumb)
4a5329c6 413 %A print address for ldc/stc/ldf/stf instruction
16980d0b 414 %B print vstm/vldm register list
efd6b359 415 %C print vscclrm register list
4a5329c6 416 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 417 %J print register for VLDR instruction
418 %K print address for VLDR instruction
4a5329c6
ZW		 419 %F print the COUNT field of a LFM/SFM instruction.
420 %P print floating point precision in arithmetic insn
421 %Q print floating point precision in ldf/stf insn
422 %R print floating point rounding mode
423
33399f07 424 %<bitfield>c print as a condition code (for vsel)
4a5329c6 425 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 426 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
427 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 428 %<bitfield>d print the bitfield in decimal
16980d0b 429 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 430 %<bitfield>x print the bitfield in hex
431 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 432 %<bitfield>f print a floating point constant if >7 else a
433 floating point register
4a5329c6
ZW		 434 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
435 %<bitfield>g print as an iWMMXt 64-bit register
436 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 437 %<bitfield>D print as a NEON D register
438 %<bitfield>Q print as a NEON Q register
c28eeff2 439 %<bitfield>V print as a NEON D or Q register
6f1c2142 440 %<bitfield>E print a quarter-float immediate value
4a5329c6 441
16980d0b 442 %y<code> print a single precision VFP reg.
2fbad815 443 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 444 %z<code> print a double precision VFP reg
2fbad815 445 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 446
16980d0b
JB		 447 %<bitfield>'c print specified char iff bitfield is all ones
448 %<bitfield>`c print specified char iff bitfield is all zeroes
449 %<bitfield>?ab... select from array of values in big endian order
43e65147 450
2fbad815 451 %L print as an iWMMXt N/M width field.
4a5329c6 452 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 453 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 454 versions.
455 %i print 5-bit immediate in bits 8,3..0
456 (print "32" when 0)
fe56b6ce 457 %r print register offset address for wldt/wstr instruction. */
2fbad815 458
21d799b5 459enum opcode_sentinel_enum
05413229
NC		 460{
461 SENTINEL_IWMMXT_START = 1,
462 SENTINEL_IWMMXT_END,
463 SENTINEL_GENERIC_START
464} opcode_sentinels;
465
aefd8a40 466#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 467#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
468#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 469#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 470
8f06b2d8 471/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 472
4934a27c
MM		 473/* print_insn_cde recognizes the following format control codes:
474
475 %% %
476
477 %a print 'a' iff bit 28 is 1
478 %p print bits 8-10 as coprocessor
479 %<bitfield>d print as decimal
480 %<bitfield>r print as an ARM register
481 %<bitfield>n print as an ARM register but r15 is APSR_nzcv
482 %<bitfield>T print as an ARM register + 1
483 %<bitfield>R as %r but r13 is UNPREDICTABLE
484 %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE
485 %j print immediate taken from bits (16..21,7,0..5)
486 %k print immediate taken from bits (20..21,7,0..5).
487 %l print immediate taken from bits (20..22,7,4..5). */
488
489/* At the moment there is only one valid position for the coprocessor number,
490 and hence that's encoded in the macro below. */
491#define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
492 { ARCH, 8, 7, VALUE, MASK, ASM }
493static const struct cdeopcode32 cde_opcodes[] =
494{
495 /* Custom Datapath Extension instructions. */
496 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
497 0xee000000, 0xefc00840,
498 "cx1%a\t%p, %12-15n, #%0-5,7,16-21d"),
499 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
500 0xee000040, 0xefc00840,
501 "cx1d%a\t%p, %12-15S, %12-15T, #%0-5,7,16-21d"),
502
503 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
504 0xee400000, 0xefc00840,
505 "cx2%a\t%p, %12-15n, %16-19n, #%0-5,7,20-21d"),
506 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
507 0xee400040, 0xefc00840,
508 "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, #%0-5,7,20-21d"),
509
510 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
511 0xee800000, 0xef800840,
512 "cx3%a\t%p, %0-3n, %16-19n, %12-15n, #%4-5,7,20-22d"),
513 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
514 0xee800040, 0xef800840,
515 "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, #%4-5,7,20-22d"),
516
5aae9ae9
MM		 517 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
518 0xec200000, 0xeeb00840,
519 "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19d"),
520 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
521 0xec200040, 0xeeb00840,
522 "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19,24d"),
523
524 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
525 0xec300000, 0xeeb00840,
526 "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19d"),
527 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
528 0xec300040, 0xeeb00840,
529 "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19,24d"),
530
531 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
532 0xec800000, 0xee800840,
533 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21d"),
534 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
535 0xec800040, 0xee800840,
536 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21,24d"),
537
4934a27c
MM		 538 CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
539
540};
541
6b0dd094 542static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 543{
2fbad815 544 /* XScale instructions. */
6b0dd094 545 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 546 0x0e200010, 0x0fff0ff0,
547 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 549 0x0e280010, 0x0fff0ff0,
550 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 551 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 552 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 553 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 554 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 555 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 556 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 557
2fbad815 558 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 559 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
560 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 561 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 562 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 563 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 564 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 565 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 566 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 567 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 568 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 569 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 570 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 571 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 572 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 573 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 574 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 575 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 576 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 577 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 578 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 579 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 580 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 581 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 582 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 583 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 584 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 585 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 586 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 587 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 588 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 589 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 590 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 591 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 592 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 593 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 594 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 595 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 596 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 597 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 598 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 599 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 600 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 601 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 602 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 603 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 604 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 605 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 606 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 607 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 608 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 609 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 610 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 611 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 612 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 613 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 614 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 615 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 616 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 617 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 618 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 619 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 620 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 621 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 622 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 623 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 624 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 625 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 626 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 627 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 628 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 629 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 630 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 631 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 632 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 633 0x0e800120, 0x0f800ff0,
634 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 635 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 636 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 637 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 638 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 639 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 640 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 641 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 642 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 643 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 644 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 645 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 646 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 647 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 648 0x0e8000a0, 0x0f800ff0,
649 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 650 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 651 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 652 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 653 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 654 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 655 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 656 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 657 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 658 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 659 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 660 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 661 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 662 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 663 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 664 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 665 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 666 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 667 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 668 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 669 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 670 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 671 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 672 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 673 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 674 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 675 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 676 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 677 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 678 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 679 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 680 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 681 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 682 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 683 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 684 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 685 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 686 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 687 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 688 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 689 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 690 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 691 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 692 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 693 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 694 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 695 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 696 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 697 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 698 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 699 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 700 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 701 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 702 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 703 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 704 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 705 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 706 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 707 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 708 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 709 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 710 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 711 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 712 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 713 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 714
fe56b6ce 715 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 716 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 717 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 718 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 719 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 720 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 721 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 722 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 723 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 724 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 725 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 726 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 727 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 728 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 729 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 730 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 731 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 732 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 733 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 734 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 735 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 736 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 737 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 738 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 739 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 740 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 741 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 742 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 743 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 744 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 745 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 746 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 747 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 748 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 749 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 750 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 751 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 752 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 753 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 754 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 755 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 756 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 757 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 758 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 759 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 760 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 761 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 762 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 763 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 764 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 765 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 766 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 767 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 768 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 769 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 770 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 771 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 772 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 773 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 774 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 775 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 776 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 777 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 778 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 779 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 780 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 781 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 782 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 783 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 784 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 785 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 786 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 787 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 788 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 789 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 790 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 791 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 792 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 793 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 794 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 795 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 796 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 797 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 798 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 799 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 800 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 801 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 802
efd6b359
AV		 803 /* Armv8.1-M Mainline instructions. */
804 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
805 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
806 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
807 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
808
16a1fa25 809 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 810 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 811 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 812 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 813 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
814
fe56b6ce 815 /* Register load/store. */
6b0dd094 816 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 817 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 818 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 819 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 820 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 821 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 822 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 823 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 824 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 825 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 826 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 827 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 828 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 829 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 830 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 831 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 832 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 833 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 834 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 835 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 836 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 837 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 838 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 839 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 840 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 841 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 842 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 843 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 844 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 845 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 846 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 847 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 848 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
849 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
850 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
851 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 852
6b0dd094 853 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 854 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 855 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 856 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 857 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 858 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 859 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 860 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 861
fe56b6ce 862 /* Data transfer between ARM and NEON registers. */
6b0dd094 863 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 864 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 865 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 866 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 867 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 868 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 869 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 870 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 871 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 872 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 873 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 874 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 875 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 876 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 877 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 878 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 879 /* Half-precision conversion instructions. */
6b0dd094 880 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 881 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 882 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 883 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 884 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 885 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 886 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 887 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 888
fe56b6ce 889 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 890 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 891 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
2da2eaf4 892 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
823d2571 893 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
ba6cd17f
SD		 894 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
895 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
6b0dd094 896 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 897 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 898 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 899 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 900 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 901 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 902 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 903 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 904 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 905 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 906 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 907 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
2da2eaf4 908 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f 909 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
2da2eaf4 910 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f
SD		 911 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
912 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
913 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
914 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
915 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
6b0dd094 916 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 917 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 918 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 919 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
2da2eaf4 920 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
823d2571 921 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
ba6cd17f
SD		 922 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
923 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
6b0dd094 924 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 925 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 926 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 927 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 928 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 929 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 930 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 931 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 932 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 933 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 934 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 935 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
2da2eaf4 936 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f 937 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
2da2eaf4 938 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f
SD		 939 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
940 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
941 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
942 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
943 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
6b0dd094 944 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 945 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 946 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 947 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 948 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 949 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 950 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 951 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 952 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 953 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 954 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 955 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 956 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 957 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 958 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 959 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 960 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 961 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 962 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 963 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 964 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 965 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 966 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 967 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 968 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 969 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 970 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 971 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 972 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 973 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 974 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 975 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 976 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 977 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 978 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 979 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 980 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 981 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 982 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 983 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 984 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 985 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 986 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 987 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 988 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 989 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 990 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 991 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 992 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 993 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 994 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 995 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 996 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 997 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 998 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 999 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 1000 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1001 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 1002 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 1003 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 1004 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 1005 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 1006 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1007 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 1008 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1009 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 1010 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1011 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 1012 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1013 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 1014 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1015 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 1016 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1017 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 1018 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1019 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 1020 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1021 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 1022 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1023 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 1024 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1025 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 1026 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1027 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 1028 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1029 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 1030 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1031 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 1032 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1033 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 1034 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1035 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 1036 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1037 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 1038 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1039 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 1040 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1041 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 1042 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1043 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 1044 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1045 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 1046 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1047 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 1048
1049 /* Cirrus coprocessor instructions. */
6b0dd094 1050 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1051 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 1052 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1053 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 1054 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1055 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 1056 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1057 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 1058 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1059 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 1060 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1061 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 1062 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1063 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 1064 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1065 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 1066 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1067 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 1068 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1069 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 1070 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1071 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 1072 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1073 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 1074 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1075 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 1076 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1077 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 1078 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1079 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1080 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1081 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1082 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1083 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 1084 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1085 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 1086 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1087 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1088 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1089 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 1090 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1091 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1092 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1093 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 1094 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1095 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1096 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1097 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1098 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1099 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1100 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1101 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1102 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1103 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1104 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1105 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1106 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1107 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1108 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1109 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1110 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1111 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1112 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1113 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1114 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1115 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1116 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1117 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1118 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1119 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 1120 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1121 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 1122 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1123 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 1124 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1125 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 1126 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1127 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1128 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1129 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1130 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1131 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 1132 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1133 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 1134 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1135 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 1136 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1137 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 1138 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1139 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 1140 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1141 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 1142 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1143 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1144 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1145 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1146 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1147 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1148 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1149 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1150 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1151 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 1152 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1153 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 1154 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1155 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 1156 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1157 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 1158 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1159 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 1160 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1161 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 1162 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1163 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1164 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1165 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1166 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1167 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1168 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1169 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1170 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1171 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1172 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1173 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1174 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1175 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1176 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1177 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1178 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1179 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1180 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1181 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1182 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1183 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1184 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1185 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1186 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1187 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1188 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1189 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1190 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1191 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1192 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1193 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1194 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1195 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1196 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1197 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1198 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1199 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1200 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1201 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1202 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1203 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1204 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1205 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1206 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1207 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1208 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1209 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1210 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1211 0x0e000600, 0x0ff00f10,
1212 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1213 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1214 0x0e100600, 0x0ff00f10,
1215 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1216 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1217 0x0e200600, 0x0ff00f10,
1218 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1219 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1220 0x0e300600, 0x0ff00f10,
1221 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 1222
62f3b8c8 1223 /* VFP Fused multiply add instructions. */
6b0dd094 1224 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1225 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1226 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1227 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1228 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1229 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1230 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1231 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1232 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1233 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1234 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1235 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1236 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1237 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1238 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1239 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1240
33399f07 1241 /* FP v5. */
6b0dd094 1242 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1243 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1244 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1245 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1246 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1247 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1248 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1249 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1250 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1251 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1252 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1253 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1254 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1255 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1256 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1257 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1258 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1259 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1260 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1261 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1262 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1263 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1264 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1265 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1266
6b0dd094 1267 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
c28eeff2 1268 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1269 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1270 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1271 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1272 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1273 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1274 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1275 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1276 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1277 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1278 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1279 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1280 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1281 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1282 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 1283 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1284 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 1285 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1286 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 1287 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1288 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 1289
aab2c27d
MM		 1290 /* BFloat16 instructions. */
1291 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1292 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1293
c604a79a 1294 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1295 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1296 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1297 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
aab2c27d 1298 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
c604a79a 1299
dec41383 1300 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1301 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1302 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1303 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1304 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1305 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1306 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1307 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1308 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1309 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1310 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1311 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1312 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1313 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1314 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 1315 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 1316 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1317
b0c11777
RL		 1318 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1319 cp_num: bit <11:8> == 0b1001.
1320 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1321 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1322 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1323 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1324 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1325 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1326 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1327 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1328 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1329 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1330 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1331 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1332 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1333 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1334 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1335 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1336 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1337 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1338 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1339 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1340 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1341 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1342 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1343 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1344 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1345 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1346 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1347 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1348 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1349 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1350 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1351 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1352 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1353 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1354 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1355 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1356 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1357 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1358 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1359 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1360 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1361 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1362 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1363 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1364 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1365 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1366 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1367 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1368 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1369 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1370 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1371 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1372 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1373 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1374 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1375 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1376 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1377 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1378 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1379 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1380 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1381 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1382 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1383 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1384 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1385 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1386 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1387 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1388 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1389 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1390 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1391
49e8a725 1392 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1393 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1394 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1395
6b0dd094 1396 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1397};
1398
33593eaf
MM		 1399/* Generic coprocessor instructions. These are only matched if a more specific
1400 SIMD or co-processor instruction does not match first. */
1401
1402static const struct sopcode32 generic_coprocessor_opcodes[] =
1403{
1404 /* Generic coprocessor instructions. */
1405 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1406 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1407 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1408 0x0c500000, 0x0ff00000,
1409 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1410 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1411 0x0e000000, 0x0f000010,
1412 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1413 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1414 0x0e10f010, 0x0f10f010,
1415 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1416 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1417 0x0e100010, 0x0f100010,
1418 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1419 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1420 0x0e000010, 0x0f100010,
1421 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1422 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1423 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1424 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1425 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1426
1427 /* V6 coprocessor instructions. */
1428 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1429 0xfc500000, 0xfff00000,
1430 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1431 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1432 0xfc400000, 0xfff00000,
1433 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1434
1435 /* V5 coprocessor instructions. */
1436 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1437 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1438 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1439 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1440 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1441 0xfe000000, 0xff000010,
1442 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1443 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1444 0xfe000010, 0xff100010,
1445 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1446 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1447 0xfe100010, 0xff100010,
1448 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1449
1450 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1451};
1452
16980d0b
JB		 1453/* Neon opcode table: This does not encode the top byte -- that is
1454 checked by the print_insn_neon routine, as it depends on whether we are
1455 doing thumb32 or arm32 disassembly. */
1456
1457/* print_insn_neon recognizes the following format control codes:
1458
1459 %% %
1460
c22aaad1 1461 %c print condition code
e2efe87d
MGD		 1462 %u print condition code (unconditional in ARM mode,
1463 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1464 %A print v{st,ld}[1234] operands
1465 %B print v{st,ld}[1234] any one operands
1466 %C print v{st,ld}[1234] single->all operands
1467 %D print scalar
1468 %E print vmov, vmvn, vorr, vbic encoded constant
1469 %F print vtbl,vtbx register list
1470
1471 %<bitfield>r print as an ARM register
1472 %<bitfield>d print the bitfield in decimal
1473 %<bitfield>e print the 2^N - bitfield in decimal
1474 %<bitfield>D print as a NEON D register
1475 %<bitfield>Q print as a NEON Q register
1476 %<bitfield>R print as a NEON D or Q register
1477 %<bitfield>Sn print byte scaled width limited by n
1478 %<bitfield>Tn print short scaled width limited by n
1479 %<bitfield>Un print long scaled width limited by n
43e65147 1480
16980d0b
JB		 1481 %<bitfield>'c print specified char iff bitfield is all ones
1482 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1483 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1484
1485static const struct opcode32 neon_opcodes[] =
1486{
fe56b6ce 1487 /* Extract. */
823d2571
TG		 1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489 0xf2b00840, 0xffb00850,
1490 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf2b00000, 0xffb00810,
1493 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1494
9743db03
AV		 1495 /* Data transfer between ARM and NEON registers. */
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1497 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
9743db03 1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1499 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
9743db03 1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1501 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
9743db03 1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1503 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
9743db03 1504 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1505 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
9743db03 1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1507 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
9743db03 1508
fe56b6ce 1509 /* Move data element to all lanes. */
823d2571
TG		 1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1511 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1513 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1515 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1516
fe56b6ce 1517 /* Table lookup. */
823d2571
TG		 1518 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1519 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1521 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1522
8e79c3df 1523 /* Half-precision conversions. */
823d2571
TG		 1524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1525 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1527 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1528
1529 /* NEON fused multiply add instructions. */
823d2571 1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1531 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1532 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1533 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1535 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1537 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1538
aab2c27d
MM		 1539 /* BFloat16 instructions. */
1540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1541 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1542 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1543 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1544 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1545 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1546 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1547 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1548 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1549 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1551 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
1552
616ce08e
MM		 1553 /* Matrix Multiply instructions. */
1554 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1555 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1556 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1557 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1559 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1561 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1562 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1563 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1564 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1565 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1566
fe56b6ce 1567 /* Two registers, miscellaneous. */
823d2571
TG		 1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1569 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1571 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1573 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1574 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1575 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1576 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1577 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1578 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1579 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1580 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1581 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1582 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1583 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1584 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1585 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1586 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1587 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1588 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1589 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1594 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1595 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1601 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1603 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1605 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1607 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1611 0xf3b20300, 0xffb30fd0,
1612 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1615 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1616 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1620 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1622 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1656 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1660 0xf3bb0600, 0xffbf0e10,
823d2571 1661 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1662 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1663 0xf3b70600, 0xffbf0e10,
1664 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1665
fe56b6ce 1666 /* Three registers of the same length. */
823d2571
TG		 1667 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1668 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1669 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1670 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1671 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1672 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1673 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1674 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1675 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1676 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1677 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1678 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1679 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1680 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1682 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1683 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1684 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1686 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1687 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1688 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1706 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1707 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1708 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1710 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1711 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1712 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1714 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1715 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1716 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1718 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1719 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1720 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1721 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1722 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1723 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1724 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1726 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1727 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1728 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1730 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1731 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1732 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1733 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1734 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1735 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1736 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1738 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1740 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1741 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1742 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1743 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1744 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1745 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1746 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1747 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1748 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1750 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1752 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1753 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1754 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1755 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1756 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1757 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1758 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1759 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1760 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1761 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1762 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1763 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1764 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1765 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1766 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1767 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1768 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1769 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1770 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1771 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1772 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1774 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1775 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1776 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1777 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1778 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1779 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1780 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1784 0xf2000b00, 0xff800f10,
1785 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1787 0xf2000b10, 0xff800f10,
1788 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1790 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1792 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796 0xf3000b00, 0xff800f10,
1797 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1798 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1799 0xf2000000, 0xfe800f10,
1800 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802 0xf2000010, 0xfe800f10,
1803 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1804 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1805 0xf2000100, 0xfe800f10,
1806 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1807 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1808 0xf2000200, 0xfe800f10,
1809 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1810 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1811 0xf2000210, 0xfe800f10,
1812 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1813 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1814 0xf2000300, 0xfe800f10,
1815 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1817 0xf2000310, 0xfe800f10,
1818 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1819 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1820 0xf2000400, 0xfe800f10,
1821 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1823 0xf2000410, 0xfe800f10,
1824 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1825 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1826 0xf2000500, 0xfe800f10,
1827 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1829 0xf2000510, 0xfe800f10,
1830 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1831 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1832 0xf2000600, 0xfe800f10,
1833 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1835 0xf2000610, 0xfe800f10,
1836 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1837 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1838 0xf2000700, 0xfe800f10,
1839 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1841 0xf2000710, 0xfe800f10,
1842 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1843 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1844 0xf2000910, 0xfe800f10,
1845 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1847 0xf2000a00, 0xfe800f10,
1848 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1850 0xf2000a10, 0xfe800f10,
1851 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1852 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1853 0xf3000b10, 0xff800f10,
1854 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1856 0xf3000c10, 0xff800f10,
1857 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1858
fe56b6ce 1859 /* One register and an immediate value. */
823d2571
TG		 1860 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1861 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1862 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1863 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1864 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1865 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1866 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1867 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1868 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1869 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1870 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1871 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1872 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1873 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1874 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1875 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1876 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1877 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1878 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1879 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1880 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1881 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1882 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1883 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1884 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1885 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1886
fe56b6ce 1887 /* Two registers and a shift amount. */
823d2571
TG		 1888 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1889 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1891 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1893 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1895 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1897 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1899 0xf2880950, 0xfeb80fd0,
1900 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1901 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1902 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1904 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1905 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1906 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1907 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1908 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1910 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1911 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1912 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1913 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1914 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1916 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1917 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1918 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1919 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1920 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1922 0xf2900950, 0xfeb00fd0,
1923 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1925 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1926 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1927 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1928 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1929 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1930 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1931 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1932 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1933 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1934 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1935 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1936 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1937 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1938 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1939 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1940 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1941 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1943 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1945 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1946 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1947 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1949 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1951 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1952 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1953 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1954 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1955 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1956 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1957 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1958 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1959 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1960 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1961 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1962 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1963 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1965 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1967 0xf2a00950, 0xfea00fd0,
1968 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1969 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1970 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1971 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1972 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1973 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1974 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1975 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1976 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1977 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1978 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1979 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1980 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1981 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1982 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1983 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1984 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1985 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1986 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1987 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1988 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1989 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1990 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1991 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1992 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1993 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1994 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1995 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1996 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1997 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1998 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1999 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2000 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
2001 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2002 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
2003 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2004 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
2005 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2006 0xf2a00e10, 0xfea00e90,
2007 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 2008 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
2009 0xf2a00c10, 0xfea00e90,
2010 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 2011
fe56b6ce 2012 /* Three registers of different lengths. */
823d2571
TG		 2013 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
2014 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2016 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2017 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2018 0xf2800400, 0xff800f50,
2019 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2020 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2021 0xf2800600, 0xff800f50,
2022 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2024 0xf2800900, 0xff800f50,
2025 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2026 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2027 0xf2800b00, 0xff800f50,
2028 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2030 0xf2800d00, 0xff800f50,
2031 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2032 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2033 0xf3800400, 0xff800f50,
2034 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2036 0xf3800600, 0xff800f50,
2037 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2038 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2039 0xf2800000, 0xfe800f50,
2040 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2042 0xf2800100, 0xfe800f50,
2043 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2044 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2045 0xf2800200, 0xfe800f50,
2046 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2048 0xf2800300, 0xfe800f50,
2049 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2050 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2051 0xf2800500, 0xfe800f50,
2052 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2053 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2054 0xf2800700, 0xfe800f50,
2055 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2056 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2057 0xf2800800, 0xfe800f50,
2058 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2059 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2060 0xf2800a00, 0xfe800f50,
2061 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2063 0xf2800c00, 0xfe800f50,
2064 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 2065
fe56b6ce 2066 /* Two registers and a scalar. */
823d2571
TG		 2067 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2068 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2069 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2070 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2071 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2072 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2073 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2074 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2075 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2076 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2077 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2078 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2079 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2080 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2081 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2082 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2083 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2084 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2085 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2086 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2087 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2088 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2089 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2090 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2091 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2092 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2093 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2094 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2095 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2096 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2097 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2098 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2099 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2100 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2101 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2102 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2103 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2104 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2105 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2106 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2107 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2108 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2109 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2110 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2111 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2112 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2113 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2114 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2116 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2117 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2118 0xf2800240, 0xfe800f50,
2119 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2120 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2121 0xf2800640, 0xfe800f50,
2122 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2123 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2124 0xf2800a40, 0xfe800f50,
2125 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 2126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2127 0xf2800e40, 0xff800f50,
2128 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2129 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2130 0xf2800f40, 0xff800f50,
2131 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2132 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2133 0xf3800e40, 0xff800f50,
2134 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2135 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2136 0xf3800f40, 0xff800f50,
2137 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2138 },
16980d0b 2139
fe56b6ce 2140 /* Element and structure load/store. */
823d2571
TG		 2141 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2142 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2143 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2144 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2145 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2146 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2147 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2148 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2149 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2150 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2151 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2152 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2153 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2154 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2155 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2156 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2158 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2159 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2160 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2161 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2162 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2164 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2165 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2166 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2168 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2169 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2170 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2171 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2172 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2174 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2176 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2177 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2178 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2179
2180 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 2181};
2182
73cd51e5
AV		 2183/* mve opcode table. */
2184
2185/* print_insn_mve recognizes the following format control codes:
2186
2187 %% %
2188
ef1576a1
AV		 2189 %a print '+' or '-' or imm offset in vldr[bhwd] and
2190 vstr[bhwd]
9743db03 2191 %c print condition code
aef6d006
AV		 2192 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2193 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 2194 %i print MVE predicate(s) for vpt and vpst
23d00a41 2195 %j print a 5-bit immediate from hw2[14:12,7:6]
08132bdd 2196 %k print 48 if the 7th position bit is set else print 64.
bf0b396d 2197 %m print rounding mode for vcvt and vrint
143275ea 2198 %n print vector comparison code for predicated instruction
bf0b396d 2199 %s print size for various vcvt instructions
143275ea
AV		 2200 %v print vector predicate for instruction in predicated
2201 block
ef1576a1 2202 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 2203 %w print writeback mode for MVE v{st,ld}[24]
2204 %B print v{st,ld}[24] any one operands
c507f10b
AV		 2205 %E print vmov, vmvn, vorr, vbic encoded constant
2206 %N print generic index for vmov
14925797 2207 %T print bottom ('b') or top ('t') of source register
d3b63143 2208 %X print exchange field in vmla* instructions
04d54ace 2209
9743db03 2210 %<bitfield>r print as an ARM register
04d54ace 2211 %<bitfield>d print the bitfield in decimal
d3b63143 2212 %<bitfield>A print accumulate or not
e39c1607
SD		 2213 %<bitfield>c print bitfield as a condition code
2214 %<bitfield>C print bitfield as an inverted condition code
143275ea 2215 %<bitfield>Q print as a MVE Q register
c507f10b 2216 %<bitfield>F print as a MVE S register
143275ea
AV		 2217 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2218 UNPREDICTABLE
23d00a41
SD		 2219
2220 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
143275ea 2221 %<bitfield>s print size for vector predicate & non VMOV instructions
66dcaa5d 2222 %<bitfield>I print carry flag or not
ef1576a1 2223 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 2224 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 2225 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8 2226 %<bitfield>l print low half of 64-bit destination reg
897b9bbc 2227 %<bitfield>o print rotate value for vcmul
1c8f2df8 2228 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 2229 %<bitfield>x print the bitfield in hex.
1c8f2df8 2230 */
73cd51e5
AV		 2231
2232static const struct mopcode32 mve_opcodes[] =
2233{
143275ea
AV		 2234 /* MVE. */
2235
2da2eaf4 2236 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2237 MVE_VPST,
2238 0xfe310f4d, 0xffbf1fff,
2239 "vpst%i"
2240 },
2241
2242 /* Floating point VPT T1. */
2da2eaf4 2243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2244 MVE_VPT_FP_T1,
2245 0xee310f00, 0xefb10f50,
2246 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2247 /* Floating point VPT T2. */
2da2eaf4 2248 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2249 MVE_VPT_FP_T2,
2250 0xee310f40, 0xefb10f50,
2251 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2252
2253 /* Vector VPT T1. */
2da2eaf4 2254 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2255 MVE_VPT_VEC_T1,
2256 0xfe010f00, 0xff811f51,
2257 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2258 /* Vector VPT T2. */
2da2eaf4 2259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2260 MVE_VPT_VEC_T2,
2261 0xfe010f01, 0xff811f51,
2262 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2263 /* Vector VPT T3. */
2da2eaf4 2264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2265 MVE_VPT_VEC_T3,
2266 0xfe011f00, 0xff811f50,
2267 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2268 /* Vector VPT T4. */
2da2eaf4 2269 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2270 MVE_VPT_VEC_T4,
2271 0xfe010f40, 0xff811f70,
2272 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2273 /* Vector VPT T5. */
2da2eaf4 2274 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2275 MVE_VPT_VEC_T5,
2276 0xfe010f60, 0xff811f70,
2277 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2278 /* Vector VPT T6. */
2da2eaf4 2279 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2280 MVE_VPT_VEC_T6,
2281 0xfe011f40, 0xff811f50,
2282 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2283
c507f10b 2284 /* Vector VBIC immediate. */
2da2eaf4 2285 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2286 MVE_VBIC_IMM,
2287 0xef800070, 0xefb81070,
2288 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2289
2290 /* Vector VBIC register. */
2da2eaf4 2291 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2292 MVE_VBIC_REG,
2293 0xef100150, 0xffb11f51,
2294 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2295
66dcaa5d 2296 /* Vector VABAV. */
2da2eaf4 2297 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2298 MVE_VABAV,
2299 0xee800f01, 0xefc10f51,
2300 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2301
2302 /* Vector VABD floating point. */
2da2eaf4 2303 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2304 MVE_VABD_FP,
2305 0xff200d40, 0xffa11f51,
2306 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2307
2308 /* Vector VABD. */
2da2eaf4 2309 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2310 MVE_VABD_VEC,
2311 0xef000740, 0xef811f51,
2312 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2313
2314 /* Vector VABS floating point. */
2da2eaf4 2315 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2316 MVE_VABS_FP,
2317 0xFFB10740, 0xFFB31FD1,
2318 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2319 /* Vector VABS. */
2da2eaf4 2320 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2321 MVE_VABS_VEC,
2322 0xffb10340, 0xffb31fd1,
2323 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2324
2325 /* Vector VADD floating point T1. */
2da2eaf4 2326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2327 MVE_VADD_FP_T1,
2328 0xef000d40, 0xffa11f51,
2329 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2330 /* Vector VADD floating point T2. */
2da2eaf4 2331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2332 MVE_VADD_FP_T2,
2333 0xee300f40, 0xefb11f70,
2334 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2335 /* Vector VADD T1. */
2da2eaf4 2336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2337 MVE_VADD_VEC_T1,
2338 0xef000840, 0xff811f51,
2339 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2340 /* Vector VADD T2. */
2da2eaf4 2341 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2342 MVE_VADD_VEC_T2,
2343 0xee010f40, 0xff811f70,
2344 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2345
d3b63143 2346 /* Vector VADDLV. */
2da2eaf4 2347 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2348 MVE_VADDLV,
2349 0xee890f00, 0xef8f1fd1,
2350 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2351
2352 /* Vector VADDV. */
2da2eaf4 2353 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2354 MVE_VADDV,
2355 0xeef10f00, 0xeff31fd1,
2356 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2357
66dcaa5d 2358 /* Vector VADC. */
2da2eaf4 2359 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2360 MVE_VADC,
2361 0xee300f00, 0xffb10f51,
2362 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2363
e523f101 2364 /* Vector VAND. */
2da2eaf4 2365 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2366 MVE_VAND,
2367 0xef000150, 0xffb11f51,
2368 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2369
2370 /* Vector VBRSR register. */
2da2eaf4 2371 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2372 MVE_VBRSR,
2373 0xfe011e60, 0xff811f70,
2374 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2375
897b9bbc 2376 /* Vector VCADD floating point. */
2da2eaf4 2377 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2378 MVE_VCADD_FP,
2379 0xfc800840, 0xfea11f51,
2380 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2381
2382 /* Vector VCADD. */
2da2eaf4 2383 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
897b9bbc
AV		 2384 MVE_VCADD_VEC,
2385 0xfe000f00, 0xff810f51,
2386 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2387
e523f101 2388 /* Vector VCLS. */
2da2eaf4 2389 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2390 MVE_VCLS,
2391 0xffb00440, 0xffb31fd1,
2392 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2393
2394 /* Vector VCLZ. */
2da2eaf4 2395 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2396 MVE_VCLZ,
2397 0xffb004c0, 0xffb31fd1,
2398 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2399
897b9bbc 2400 /* Vector VCMLA. */
2da2eaf4 2401 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2402 MVE_VCMLA_FP,
2403 0xfc200840, 0xfe211f51,
2404 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2405
143275ea 2406 /* Vector VCMP floating point T1. */
2da2eaf4 2407 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2408 MVE_VCMP_FP_T1,
2409 0xee310f00, 0xeff1ef50,
2410 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2411
2412 /* Vector VCMP floating point T2. */
2da2eaf4 2413 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2414 MVE_VCMP_FP_T2,
2415 0xee310f40, 0xeff1ef50,
2416 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2417
2418 /* Vector VCMP T1. */
2da2eaf4 2419 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2420 MVE_VCMP_VEC_T1,
2421 0xfe010f00, 0xffc1ff51,
2422 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2423 /* Vector VCMP T2. */
2da2eaf4 2424 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2425 MVE_VCMP_VEC_T2,
2426 0xfe010f01, 0xffc1ff51,
2427 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2428 /* Vector VCMP T3. */
2da2eaf4 2429 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2430 MVE_VCMP_VEC_T3,
2431 0xfe011f00, 0xffc1ff50,
2432 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2433 /* Vector VCMP T4. */
2da2eaf4 2434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2435 MVE_VCMP_VEC_T4,
2436 0xfe010f40, 0xffc1ff70,
2437 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2438 /* Vector VCMP T5. */
2da2eaf4 2439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2440 MVE_VCMP_VEC_T5,
2441 0xfe010f60, 0xffc1ff70,
2442 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2443 /* Vector VCMP T6. */
2da2eaf4 2444 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2445 MVE_VCMP_VEC_T6,
2446 0xfe011f40, 0xffc1ff50,
2447 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2448
9743db03 2449 /* Vector VDUP. */
2da2eaf4 2450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2451 MVE_VDUP,
2452 0xeea00b10, 0xffb10f5f,
2453 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2454
2455 /* Vector VEOR. */
2da2eaf4 2456 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2457 MVE_VEOR,
2458 0xff000150, 0xffd11f51,
2459 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2460
2461 /* Vector VFMA, vector * scalar. */
2da2eaf4 2462 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2463 MVE_VFMA_FP_SCALAR,
2464 0xee310e40, 0xefb11f70,
2465 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2466
2467 /* Vector VFMA floating point. */
2da2eaf4 2468 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2469 MVE_VFMA_FP,
2470 0xef000c50, 0xffa11f51,
2471 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2472
2473 /* Vector VFMS floating point. */
2da2eaf4 2474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2475 MVE_VFMS_FP,
2476 0xef200c50, 0xffa11f51,
2477 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2478
2479 /* Vector VFMAS, vector * scalar. */
2da2eaf4 2480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2481 MVE_VFMAS_FP_SCALAR,
2482 0xee311e40, 0xefb11f70,
2483 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2484
2485 /* Vector VHADD T1. */
2da2eaf4 2486 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2487 MVE_VHADD_T1,
2488 0xef000040, 0xef811f51,
2489 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2490
2491 /* Vector VHADD T2. */
2da2eaf4 2492 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2493 MVE_VHADD_T2,
2494 0xee000f40, 0xef811f70,
2495 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2496
2497 /* Vector VHSUB T1. */
2da2eaf4 2498 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2499 MVE_VHSUB_T1,
2500 0xef000240, 0xef811f51,
2501 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2502
2503 /* Vector VHSUB T2. */
2da2eaf4 2504 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2505 MVE_VHSUB_T2,
2506 0xee001f40, 0xef811f70,
2507 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2508
897b9bbc 2509 /* Vector VCMUL. */
2da2eaf4 2510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2511 MVE_VCMUL_FP,
2512 0xee300e00, 0xefb10f50,
2513 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2514
e523f101 2515 /* Vector VCTP. */
2da2eaf4 2516 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2517 MVE_VCTP,
2518 0xf000e801, 0xffc0ffff,
2519 "vctp%v.%20-21s\t%16-19r"},
2520
9743db03 2521 /* Vector VDUP. */
2da2eaf4 2522 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2523 MVE_VDUP,
2524 0xeea00b10, 0xffb10f5f,
2525 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2526
2527 /* Vector VRHADD. */
2da2eaf4 2528 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2529 MVE_VRHADD,
2530 0xef000140, 0xef811f51,
2531 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2532
bf0b396d 2533 /* Vector VCVT. */
2da2eaf4 2534 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2535 MVE_VCVT_FP_FIX_VEC,
2536 0xef800c50, 0xef801cd1,
2537 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2538
2539 /* Vector VCVT. */
2da2eaf4 2540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2541 MVE_VCVT_BETWEEN_FP_INT,
2542 0xffb30640, 0xffb31e51,
2543 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2544
2545 /* Vector VCVT between single and half-precision float, bottom half. */
2da2eaf4 2546 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2547 MVE_VCVT_FP_HALF_FP,
2548 0xee3f0e01, 0xefbf1fd1,
2549 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2550
2551 /* Vector VCVT between single and half-precision float, top half. */
2da2eaf4 2552 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2553 MVE_VCVT_FP_HALF_FP,
2554 0xee3f1e01, 0xefbf1fd1,
2555 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2556
2557 /* Vector VCVT. */
2da2eaf4 2558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2559 MVE_VCVT_FROM_FP_TO_INT,
2560 0xffb30040, 0xffb31c51,
2561 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2562
1c8f2df8 2563 /* Vector VDDUP. */
2da2eaf4 2564 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2565 MVE_VDDUP,
2566 0xee011f6e, 0xff811f7e,
2567 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2568
2569 /* Vector VDWDUP. */
2da2eaf4 2570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2571 MVE_VDWDUP,
2572 0xee011f60, 0xff811f70,
2573 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2574
897b9bbc 2575 /* Vector VHCADD. */
2da2eaf4 2576 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
897b9bbc
AV		 2577 MVE_VHCADD,
2578 0xee000f00, 0xff810f51,
2579 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2580
1c8f2df8 2581 /* Vector VIWDUP. */
2da2eaf4 2582 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2583 MVE_VIWDUP,
2584 0xee010f60, 0xff811f70,
2585 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2586
2587 /* Vector VIDUP. */
2da2eaf4 2588 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2589 MVE_VIDUP,
2590 0xee010f6e, 0xff811f7e,
2591 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2592
04d54ace 2593 /* Vector VLD2. */
2da2eaf4 2594 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 2595 MVE_VLD2,
2596 0xfc901e00, 0xff901e5f,
2597 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2598
2599 /* Vector VLD4. */
2da2eaf4 2600 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 2601 MVE_VLD4,
2602 0xfc901e01, 0xff901e1f,
2603 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2604
ef1576a1 2605 /* Vector VLDRB gather load. */
2da2eaf4 2606 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2607 MVE_VLDRB_GATHER_T1,
2608 0xec900e00, 0xefb01e50,
2609 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2610
2611 /* Vector VLDRH gather load. */
2da2eaf4 2612 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2613 MVE_VLDRH_GATHER_T2,
2614 0xec900e10, 0xefb01e50,
2615 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2616
2617 /* Vector VLDRW gather load. */
2da2eaf4 2618 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2619 MVE_VLDRW_GATHER_T3,
2620 0xfc900f40, 0xffb01fd0,
2621 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2622
2623 /* Vector VLDRD gather load. */
2da2eaf4 2624 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2625 MVE_VLDRD_GATHER_T4,
2626 0xec900fd0, 0xefb01fd0,
2627 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2628
2629 /* Vector VLDRW gather load. */
2da2eaf4 2630 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2631 MVE_VLDRW_GATHER_T5,
2632 0xfd101e00, 0xff111f00,
2633 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2634
2635 /* Vector VLDRD gather load, variant T6. */
2da2eaf4 2636 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2637 MVE_VLDRD_GATHER_T6,
2638 0xfd101f00, 0xff111f00,
2639 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2640
aef6d006 2641 /* Vector VLDRB. */
2da2eaf4 2642 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2643 MVE_VLDRB_T1,
2644 0xec100e00, 0xee581e00,
2645 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2646
2647 /* Vector VLDRH. */
2da2eaf4 2648 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2649 MVE_VLDRH_T2,
2650 0xec180e00, 0xee581e00,
2651 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2652
2653 /* Vector VLDRB unsigned, variant T5. */
2da2eaf4 2654 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2655 MVE_VLDRB_T5,
2656 0xec101e00, 0xfe101f80,
2657 "vldrb%v.u8\t%13-15,22Q, %d"},
2658
2659 /* Vector VLDRH unsigned, variant T6. */
2da2eaf4 2660 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2661 MVE_VLDRH_T6,
2662 0xec101e80, 0xfe101f80,
2663 "vldrh%v.u16\t%13-15,22Q, %d"},
2664
2665 /* Vector VLDRW unsigned, variant T7. */
2da2eaf4 2666 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2667 MVE_VLDRW_T7,
2668 0xec101f00, 0xfe101f80,
2669 "vldrw%v.u32\t%13-15,22Q, %d"},
2670
56858bea 2671 /* Vector VMAX. */
2da2eaf4 2672 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2673 MVE_VMAX,
2674 0xef000640, 0xef811f51,
2675 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2676
2677 /* Vector VMAXA. */
2da2eaf4 2678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2679 MVE_VMAXA,
2680 0xee330e81, 0xffb31fd1,
2681 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2682
2683 /* Vector VMAXNM floating point. */
2da2eaf4 2684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2685 MVE_VMAXNM_FP,
2686 0xff000f50, 0xffa11f51,
2687 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2688
2689 /* Vector VMAXNMA floating point. */
2da2eaf4 2690 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2691 MVE_VMAXNMA_FP,
2692 0xee3f0e81, 0xefbf1fd1,
2693 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2694
2695 /* Vector VMAXNMV floating point. */
2da2eaf4 2696 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2697 MVE_VMAXNMV_FP,
2698 0xeeee0f00, 0xefff0fd1,
2699 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2700
2701 /* Vector VMAXNMAV floating point. */
2da2eaf4 2702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2703 MVE_VMAXNMAV_FP,
2704 0xeeec0f00, 0xefff0fd1,
2705 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2706
2707 /* Vector VMAXV. */
2da2eaf4 2708 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2709 MVE_VMAXV,
2710 0xeee20f00, 0xeff30fd1,
2711 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2712
2713 /* Vector VMAXAV. */
2da2eaf4 2714 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2715 MVE_VMAXAV,
2716 0xeee00f00, 0xfff30fd1,
2717 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2718
2719 /* Vector VMIN. */
2da2eaf4 2720 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2721 MVE_VMIN,
2722 0xef000650, 0xef811f51,
2723 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2724
2725 /* Vector VMINA. */
2da2eaf4 2726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2727 MVE_VMINA,
2728 0xee331e81, 0xffb31fd1,
2729 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2730
2731 /* Vector VMINNM floating point. */
2da2eaf4 2732 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2733 MVE_VMINNM_FP,
2734 0xff200f50, 0xffa11f51,
2735 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2736
2737 /* Vector VMINNMA floating point. */
2da2eaf4 2738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2739 MVE_VMINNMA_FP,
2740 0xee3f1e81, 0xefbf1fd1,
2741 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2742
2743 /* Vector VMINNMV floating point. */
2da2eaf4 2744 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2745 MVE_VMINNMV_FP,
2746 0xeeee0f80, 0xefff0fd1,
2747 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2748
2749 /* Vector VMINNMAV floating point. */
2da2eaf4 2750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2751 MVE_VMINNMAV_FP,
2752 0xeeec0f80, 0xefff0fd1,
2753 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2754
2755 /* Vector VMINV. */
2da2eaf4 2756 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2757 MVE_VMINV,
2758 0xeee20f80, 0xeff30fd1,
2759 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2760
2761 /* Vector VMINAV. */
2da2eaf4 2762 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2763 MVE_VMINAV,
2764 0xeee00f80, 0xfff30fd1,
2765 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2766
2767 /* Vector VMLA. */
2da2eaf4 2768 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2769 MVE_VMLA,
2770 0xee010e40, 0xef811f70,
2771 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2772
d3b63143
AV		 2773 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2774 opcode aliasing. */
2da2eaf4 2775 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2776 MVE_VMLALDAV,
2777 0xee801e00, 0xef801f51,
2778 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2779
2da2eaf4 2780 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2781 MVE_VMLALDAV,
2782 0xee800e00, 0xef801f51,
2783 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2784
2785 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2da2eaf4 2786 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2787 MVE_VMLADAV_T1,
2788 0xeef00e00, 0xeff01f51,
2789 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2790
2791 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2da2eaf4 2792 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2793 MVE_VMLADAV_T2,
2794 0xeef00f00, 0xeff11f51,
2795 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2796
2797 /* Vector VMLADAV T1 variant. */
2da2eaf4 2798 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2799 MVE_VMLADAV_T1,
2800 0xeef01e00, 0xeff01f51,
2801 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2802
2803 /* Vector VMLADAV T2 variant. */
2da2eaf4 2804 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2805 MVE_VMLADAV_T2,
2806 0xeef01f00, 0xeff11f51,
2807 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2808
2809 /* Vector VMLAS. */
2da2eaf4 2810 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2811 MVE_VMLAS,
2812 0xee011e40, 0xef811f70,
2813 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2814
2815 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2816 opcode aliasing. */
2da2eaf4 2817 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2818 MVE_VRMLSLDAVH,
2819 0xfe800e01, 0xff810f51,
2820 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2821
2822 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2823 opcdoe aliasing. */
2da2eaf4 2824 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2825 MVE_VMLSLDAV,
2826 0xee800e01, 0xff800f51,
2827 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2828
2829 /* Vector VMLSDAV T1 Variant. */
2da2eaf4 2830 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2831 MVE_VMLSDAV_T1,
2832 0xeef00e01, 0xfff00f51,
2833 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2834
2835 /* Vector VMLSDAV T2 Variant. */
2da2eaf4 2836 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2837 MVE_VMLSDAV_T2,
2838 0xfef00e01, 0xfff10f51,
2839 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2840
c507f10b 2841 /* Vector VMOV between gpr and half precision register, op == 0. */
2da2eaf4 2842 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2843 MVE_VMOV_HFP_TO_GP,
2844 0xee000910, 0xfff00f7f,
2845 "vmov.f16\t%7,16-19F, %12-15r"},
2846
2847 /* Vector VMOV between gpr and half precision register, op == 1. */
2da2eaf4 2848 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2849 MVE_VMOV_HFP_TO_GP,
2850 0xee100910, 0xfff00f7f,
2851 "vmov.f16\t%12-15r, %7,16-19F"},
2852
2da2eaf4 2853 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2854 MVE_VMOV_GP_TO_VEC_LANE,
2855 0xee000b10, 0xff900f1f,
2856 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2857
2858 /* Vector VORR immediate to vector.
2859 NOTE: MVE_VORR_IMM must appear in the table
2860 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2861 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2862 MVE_VORR_IMM,
2863 0xef800050, 0xefb810f0,
2864 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2865
ed63aa17
AV		 2866 /* Vector VQSHL T2 Variant.
2867 NOTE: MVE_VQSHL_T2 must appear in the table before
2868 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2869 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2870 MVE_VQSHL_T2,
2871 0xef800750, 0xef801fd1,
2872 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2873
2874 /* Vector VQSHLU T3 Variant
2875 NOTE: MVE_VQSHL_T2 must appear in the table before
2876 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2877
2da2eaf4 2878 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2879 MVE_VQSHLU_T3,
2880 0xff800650, 0xff801fd1,
2881 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2882
2883 /* Vector VRSHR
2884 NOTE: MVE_VRSHR must appear in the table before
2885 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2886 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2887 MVE_VRSHR,
2888 0xef800250, 0xef801fd1,
2889 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2890
2891 /* Vector VSHL.
2892 NOTE: MVE_VSHL must appear in the table before
2893 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2894 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2895 MVE_VSHL_T1,
2896 0xef800550, 0xff801fd1,
2897 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2898
2899 /* Vector VSHR
2900 NOTE: MVE_VSHR must appear in the table before
2901 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2902 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2903 MVE_VSHR,
2904 0xef800050, 0xef801fd1,
2905 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2906
2907 /* Vector VSLI
2908 NOTE: MVE_VSLI must appear in the table before
2909 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2910 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2911 MVE_VSLI,
2912 0xff800550, 0xff801fd1,
2913 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2914
2915 /* Vector VSRI
2916 NOTE: MVE_VSRI must appear in the table before
2917 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2918 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2919 MVE_VSRI,
2920 0xff800450, 0xff801fd1,
2921 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2922
c507f10b 2923 /* Vector VMOV immediate to vector,
ce760a76 2924 undefinded for cmode == 1111 */
2da2eaf4 2925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ce760a76
MI		 2926 MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
2927
2928 /* Vector VMOV immediate to vector,
2929 cmode == 1101 */
2da2eaf4 2930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ce760a76
MI		 2931 MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
2932 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
c507f10b
AV		 2933
2934 /* Vector VMOV immediate to vector. */
2da2eaf4 2935 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2936 MVE_VMOV_IMM_TO_VEC,
2937 0xef800050, 0xefb810d0,
2938 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2939
2940 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2da2eaf4 2941 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2942 MVE_VMOV2_VEC_LANE_TO_GP,
2943 0xec000f00, 0xffb01ff0,
2944 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2945
2946 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2da2eaf4 2947 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2948 MVE_VMOV2_VEC_LANE_TO_GP,
2949 0xec000f10, 0xffb01ff0,
2950 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2951
2952 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2da2eaf4 2953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2954 MVE_VMOV2_GP_TO_VEC_LANE,
2955 0xec100f00, 0xffb01ff0,
2956 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2957
2958 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2da2eaf4 2959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2960 MVE_VMOV2_GP_TO_VEC_LANE,
2961 0xec100f10, 0xffb01ff0,
2962 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2963
2964 /* Vector VMOV Vector lane to gpr. */
2da2eaf4 2965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2966 MVE_VMOV_VEC_LANE_TO_GP,
2967 0xee100b10, 0xff100f1f,
2968 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2969
ed63aa17
AV		 2970 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2971 to instruction opcode aliasing. */
2da2eaf4 2972 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2973 MVE_VSHLL_T1,
2974 0xeea00f40, 0xefa00fd1,
2975 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2976
14925797 2977 /* Vector VMOVL long. */
2da2eaf4 2978 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2979 MVE_VMOVL,
2980 0xeea00f40, 0xefa70fd1,
2981 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2982
2983 /* Vector VMOV and narrow. */
2da2eaf4 2984 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2985 MVE_VMOVN,
2986 0xfe310e81, 0xffb30fd1,
2987 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2988
c507f10b 2989 /* Floating point move extract. */
2da2eaf4 2990 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2991 MVE_VMOVX,
2992 0xfeb00a40, 0xffbf0fd0,
2993 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2994
f49bb598 2995 /* Vector VMUL floating-point T1 variant. */
2da2eaf4 2996 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 2997 MVE_VMUL_FP_T1,
2998 0xff000d50, 0xffa11f51,
2999 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3000
3001 /* Vector VMUL floating-point T2 variant. */
2da2eaf4 3002 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 3003 MVE_VMUL_FP_T2,
3004 0xee310e60, 0xefb11f70,
3005 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3006
3007 /* Vector VMUL T1 variant. */
2da2eaf4 3008 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3009 MVE_VMUL_VEC_T1,
3010 0xef000950, 0xff811f51,
3011 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3012
3013 /* Vector VMUL T2 variant. */
2da2eaf4 3014 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3015 MVE_VMUL_VEC_T2,
3016 0xee011e60, 0xff811f70,
3017 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3018
3019 /* Vector VMULH. */
2da2eaf4 3020 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3021 MVE_VMULH,
3022 0xee010e01, 0xef811f51,
3023 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3024
3025 /* Vector VRMULH. */
2da2eaf4 3026 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3027 MVE_VRMULH,
3028 0xee011e01, 0xef811f51,
3029 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3030
14925797 3031 /* Vector VMULL integer. */
2da2eaf4 3032 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3033 MVE_VMULL_INT,
3034 0xee010e00, 0xef810f51,
3035 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3036
3037 /* Vector VMULL polynomial. */
2da2eaf4 3038 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3039 MVE_VMULL_POLY,
3040 0xee310e00, 0xefb10f51,
3041 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3042
c507f10b 3043 /* Vector VMVN immediate to vector. */
2da2eaf4 3044 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3045 MVE_VMVN_IMM,
3046 0xef800070, 0xefb810f0,
3047 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
3048
3049 /* Vector VMVN register. */
2da2eaf4 3050 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3051 MVE_VMVN_REG,
3052 0xffb005c0, 0xffbf1fd1,
3053 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
3054
f49bb598 3055 /* Vector VNEG floating point. */
2da2eaf4 3056 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 3057 MVE_VNEG_FP,
3058 0xffb107c0, 0xffb31fd1,
3059 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3060
3061 /* Vector VNEG. */
2da2eaf4 3062 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3063 MVE_VNEG_VEC,
3064 0xffb103c0, 0xffb31fd1,
3065 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3066
c507f10b 3067 /* Vector VORN, vector bitwise or not. */
2da2eaf4 3068 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3069 MVE_VORN,
3070 0xef300150, 0xffb11f51,
3071 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3072
3073 /* Vector VORR register. */
2da2eaf4 3074 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3075 MVE_VORR_REG,
3076 0xef200150, 0xffb11f51,
3077 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3078
c4a23bf8
SP		 3079 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
3080 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
3081 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
3082 array. */
3083
2da2eaf4 3084 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c4a23bf8
SP		 3085 MVE_VMOV_VEC_TO_VEC,
3086 0xef200150, 0xffb11f51,
3087 "vmov%v\t%13-15,22Q, %17-19,7Q"},
3088
14925797 3089 /* Vector VQDMULL T1 variant. */
2da2eaf4 3090 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3091 MVE_VQDMULL_T1,
3092 0xee300f01, 0xefb10f51,
3093 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3094
14b456f2 3095 /* Vector VPNOT. */
2da2eaf4 3096 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3097 MVE_VPNOT,
3098 0xfe310f4d, 0xffffffff,
3099 "vpnot%v"},
3100
3101 /* Vector VPSEL. */
2da2eaf4 3102 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3103 MVE_VPSEL,
3104 0xfe310f01, 0xffb11f51,
3105 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3106
3107 /* Vector VQABS. */
2da2eaf4 3108 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3109 MVE_VQABS,
3110 0xffb00740, 0xffb31fd1,
3111 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3112
3113 /* Vector VQADD T1 variant. */
2da2eaf4 3114 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3115 MVE_VQADD_T1,
3116 0xef000050, 0xef811f51,
3117 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3118
3119 /* Vector VQADD T2 variant. */
2da2eaf4 3120 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3121 MVE_VQADD_T2,
3122 0xee000f60, 0xef811f70,
3123 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3124
14925797 3125 /* Vector VQDMULL T2 variant. */
2da2eaf4 3126 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3127 MVE_VQDMULL_T2,
3128 0xee300f60, 0xefb10f70,
3129 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3130
3131 /* Vector VQMOVN. */
2da2eaf4 3132 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3133 MVE_VQMOVN,
3134 0xee330e01, 0xefb30fd1,
3135 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3136
3137 /* Vector VQMOVUN. */
2da2eaf4 3138 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3139 MVE_VQMOVUN,
3140 0xee310e81, 0xffb30fd1,
3141 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3142
d3b63143 3143 /* Vector VQDMLADH. */
2da2eaf4 3144 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3145 MVE_VQDMLADH,
3146 0xee000e00, 0xff810f51,
3147 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3148
3149 /* Vector VQRDMLADH. */
2da2eaf4 3150 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3151 MVE_VQRDMLADH,
3152 0xee000e01, 0xff810f51,
3153 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3154
3155 /* Vector VQDMLAH. */
2da2eaf4 3156 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3157 MVE_VQDMLAH,
23d188c7 3158 0xee000e60, 0xff811f70,
d3b63143
AV		 3159 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3160
3161 /* Vector VQRDMLAH. */
2da2eaf4 3162 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3163 MVE_VQRDMLAH,
23d188c7 3164 0xee000e40, 0xff811f70,
d3b63143
AV		 3165 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3166
3167 /* Vector VQDMLASH. */
2da2eaf4 3168 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3169 MVE_VQDMLASH,
23d188c7 3170 0xee001e60, 0xff811f70,
d3b63143
AV		 3171 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3172
3173 /* Vector VQRDMLASH. */
2da2eaf4 3174 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3175 MVE_VQRDMLASH,
23d188c7 3176 0xee001e40, 0xff811f70,
d3b63143
AV		 3177 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3178
3179 /* Vector VQDMLSDH. */
2da2eaf4 3180 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3181 MVE_VQDMLSDH,
3182 0xfe000e00, 0xff810f51,
3183 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3184
3185 /* Vector VQRDMLSDH. */
2da2eaf4 3186 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3187 MVE_VQRDMLSDH,
3188 0xfe000e01, 0xff810f51,
3189 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3190
3191 /* Vector VQDMULH T1 variant. */
2da2eaf4 3192 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3193 MVE_VQDMULH_T1,
3194 0xef000b40, 0xff811f51,
3195 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3196
3197 /* Vector VQRDMULH T2 variant. */
2da2eaf4 3198 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3199 MVE_VQRDMULH_T2,
3200 0xff000b40, 0xff811f51,
3201 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3202
3203 /* Vector VQDMULH T3 variant. */
2da2eaf4 3204 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3205 MVE_VQDMULH_T3,
3206 0xee010e60, 0xff811f70,
3207 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3208
3209 /* Vector VQRDMULH T4 variant. */
2da2eaf4 3210 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3211 MVE_VQRDMULH_T4,
3212 0xfe010e60, 0xff811f70,
3213 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3214
14b456f2 3215 /* Vector VQNEG. */
2da2eaf4 3216 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3217 MVE_VQNEG,
3218 0xffb007c0, 0xffb31fd1,
3219 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3220
ed63aa17 3221 /* Vector VQRSHL T1 variant. */
2da2eaf4 3222 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3223 MVE_VQRSHL_T1,
3224 0xef000550, 0xef811f51,
3225 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3226
3227 /* Vector VQRSHL T2 variant. */
2da2eaf4 3228 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3229 MVE_VQRSHL_T2,
3230 0xee331ee0, 0xefb31ff0,
3231 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3232
3233 /* Vector VQRSHRN. */
2da2eaf4 3234 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3235 MVE_VQRSHRN,
3236 0xee800f41, 0xefa00fd1,
3237 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3238
3239 /* Vector VQRSHRUN. */
2da2eaf4 3240 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3241 MVE_VQRSHRUN,
3242 0xfe800fc0, 0xffa00fd1,
3243 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3244
3245 /* Vector VQSHL T1 Variant. */
2da2eaf4 3246 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3247 MVE_VQSHL_T1,
3248 0xee311ee0, 0xefb31ff0,
3249 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3250
3251 /* Vector VQSHL T4 Variant. */
2da2eaf4 3252 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3253 MVE_VQSHL_T4,
3254 0xef000450, 0xef811f51,
3255 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3256
3257 /* Vector VQSHRN. */
2da2eaf4 3258 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3259 MVE_VQSHRN,
3260 0xee800f40, 0xefa00fd1,
3261 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3262
3263 /* Vector VQSHRUN. */
2da2eaf4 3264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3265 MVE_VQSHRUN,
3266 0xee800fc0, 0xffa00fd1,
3267 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3268
14b456f2 3269 /* Vector VQSUB T1 Variant. */
2da2eaf4 3270 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3271 MVE_VQSUB_T1,
3272 0xef000250, 0xef811f51,
3273 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3274
3275 /* Vector VQSUB T2 Variant. */
2da2eaf4 3276 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3277 MVE_VQSUB_T2,
3278 0xee001f60, 0xef811f70,
3279 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3280
3281 /* Vector VREV16. */
2da2eaf4 3282 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3283 MVE_VREV16,
3284 0xffb00140, 0xffb31fd1,
3285 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3286
3287 /* Vector VREV32. */
2da2eaf4 3288 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3289 MVE_VREV32,
3290 0xffb000c0, 0xffb31fd1,
3291 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3292
3293 /* Vector VREV64. */
2da2eaf4 3294 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3295 MVE_VREV64,
3296 0xffb00040, 0xffb31fd1,
3297 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3298
bf0b396d 3299 /* Vector VRINT floating point. */
2da2eaf4 3300 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 3301 MVE_VRINT_FP,
3302 0xffb20440, 0xffb31c51,
3303 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3304
d3b63143 3305 /* Vector VRMLALDAVH. */
2da2eaf4 3306 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3307 MVE_VRMLALDAVH,
3308 0xee800f00, 0xef811f51,
3309 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3310
3311 /* Vector VRMLALDAVH. */
2da2eaf4 3312 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3313 MVE_VRMLALDAVH,
3314 0xee801f00, 0xef811f51,
3315 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3316
ed63aa17 3317 /* Vector VRSHL T1 Variant. */
2da2eaf4 3318 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3319 MVE_VRSHL_T1,
3320 0xef000540, 0xef811f51,
3321 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3322
3323 /* Vector VRSHL T2 Variant. */
2da2eaf4 3324 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3325 MVE_VRSHL_T2,
3326 0xee331e60, 0xefb31ff0,
3327 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3328
3329 /* Vector VRSHRN. */
2da2eaf4 3330 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3331 MVE_VRSHRN,
3332 0xfe800fc1, 0xffa00fd1,
3333 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3334
66dcaa5d 3335 /* Vector VSBC. */
2da2eaf4 3336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3337 MVE_VSBC,
3338 0xfe300f00, 0xffb10f51,
3339 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3340
ed63aa17 3341 /* Vector VSHL T2 Variant. */
2da2eaf4 3342 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3343 MVE_VSHL_T2,
3344 0xee311e60, 0xefb31ff0,
3345 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3346
3347 /* Vector VSHL T3 Variant. */
2da2eaf4 3348 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3349 MVE_VSHL_T3,
3350 0xef000440, 0xef811f51,
3351 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3352
3353 /* Vector VSHLC. */
2da2eaf4 3354 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3355 MVE_VSHLC,
3356 0xeea00fc0, 0xffa01ff0,
3357 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3358
3359 /* Vector VSHLL T2 Variant. */
2da2eaf4 3360 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3361 MVE_VSHLL_T2,
3362 0xee310e01, 0xefb30fd1,
3363 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3364
3365 /* Vector VSHRN. */
2da2eaf4 3366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3367 MVE_VSHRN,
3368 0xee800fc1, 0xffa00fd1,
3369 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3370
04d54ace 3371 /* Vector VST2 no writeback. */
2da2eaf4 3372 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3373 MVE_VST2,
3374 0xfc801e00, 0xffb01e5f,
3375 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3376
3377 /* Vector VST2 writeback. */
2da2eaf4 3378 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3379 MVE_VST2,
3380 0xfca01e00, 0xffb01e5f,
3381 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3382
3383 /* Vector VST4 no writeback. */
2da2eaf4 3384 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3385 MVE_VST4,
3386 0xfc801e01, 0xffb01e1f,
3387 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3388
3389 /* Vector VST4 writeback. */
2da2eaf4 3390 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3391 MVE_VST4,
3392 0xfca01e01, 0xffb01e1f,
3393 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3394
ef1576a1 3395 /* Vector VSTRB scatter store, T1 variant. */
2da2eaf4 3396 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3397 MVE_VSTRB_SCATTER_T1,
3398 0xec800e00, 0xffb01e50,
3399 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3400
3401 /* Vector VSTRH scatter store, T2 variant. */
2da2eaf4 3402 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3403 MVE_VSTRH_SCATTER_T2,
3404 0xec800e10, 0xffb01e50,
3405 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3406
3407 /* Vector VSTRW scatter store, T3 variant. */
2da2eaf4 3408 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3409 MVE_VSTRW_SCATTER_T3,
3410 0xec800e40, 0xffb01e50,
3411 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3412
3413 /* Vector VSTRD scatter store, T4 variant. */
2da2eaf4 3414 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3415 MVE_VSTRD_SCATTER_T4,
3416 0xec800fd0, 0xffb01fd0,
3417 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3418
3419 /* Vector VSTRW scatter store, T5 variant. */
2da2eaf4 3420 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3421 MVE_VSTRW_SCATTER_T5,
3422 0xfd001e00, 0xff111f00,
3423 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3424
3425 /* Vector VSTRD scatter store, T6 variant. */
2da2eaf4 3426 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3427 MVE_VSTRD_SCATTER_T6,
3428 0xfd001f00, 0xff111f00,
3429 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3430
aef6d006 3431 /* Vector VSTRB. */
2da2eaf4 3432 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3433 MVE_VSTRB_T1,
3434 0xec000e00, 0xfe581e00,
3435 "vstrb%v.%7-8s\t%13-15Q, %d"},
3436
3437 /* Vector VSTRH. */
2da2eaf4 3438 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3439 MVE_VSTRH_T2,
3440 0xec080e00, 0xfe581e00,
3441 "vstrh%v.%7-8s\t%13-15Q, %d"},
3442
3443 /* Vector VSTRB variant T5. */
2da2eaf4 3444 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3445 MVE_VSTRB_T5,
3446 0xec001e00, 0xfe101f80,
3447 "vstrb%v.8\t%13-15,22Q, %d"},
3448
3449 /* Vector VSTRH variant T6. */
2da2eaf4 3450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3451 MVE_VSTRH_T6,
3452 0xec001e80, 0xfe101f80,
3453 "vstrh%v.16\t%13-15,22Q, %d"},
3454
3455 /* Vector VSTRW variant T7. */
2da2eaf4 3456 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3457 MVE_VSTRW_T7,
3458 0xec001f00, 0xfe101f80,
3459 "vstrw%v.32\t%13-15,22Q, %d"},
3460
66dcaa5d 3461 /* Vector VSUB floating point T1 variant. */
2da2eaf4 3462 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 3463 MVE_VSUB_FP_T1,
3464 0xef200d40, 0xffa11f51,
3465 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3466
3467 /* Vector VSUB floating point T2 variant. */
2da2eaf4 3468 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 3469 MVE_VSUB_FP_T2,
3470 0xee301f40, 0xefb11f70,
3471 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3472
3473 /* Vector VSUB T1 variant. */
2da2eaf4 3474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3475 MVE_VSUB_VEC_T1,
3476 0xff000840, 0xff811f51,
3477 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3478
3479 /* Vector VSUB T2 variant. */
2da2eaf4 3480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3481 MVE_VSUB_VEC_T2,
3482 0xee011f40, 0xff811f70,
3483 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3484
2da2eaf4 3485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3486 MVE_ASRLI,
3487 0xea50012f, 0xfff1813f,
3488 "asrl%c\t%17-19l, %9-11h, %j"},
3489
2da2eaf4 3490 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3491 MVE_ASRL,
3492 0xea50012d, 0xfff101ff,
3493 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3494
2da2eaf4 3495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3496 MVE_LSLLI,
3497 0xea50010f, 0xfff1813f,
3498 "lsll%c\t%17-19l, %9-11h, %j"},
3499
2da2eaf4 3500 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3501 MVE_LSLL,
3502 0xea50010d, 0xfff101ff,
3503 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3504
2da2eaf4 3505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3506 MVE_LSRL,
3507 0xea50011f, 0xfff1813f,
3508 "lsrl%c\t%17-19l, %9-11h, %j"},
3509
2da2eaf4 3510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41 3511 MVE_SQRSHRL,
08132bdd
SP		 3512 0xea51012d, 0xfff1017f,
3513 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41 3514
2da2eaf4 3515 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3516 MVE_SQRSHR,
3517 0xea500f2d, 0xfff00fff,
3518 "sqrshr%c\t%16-19S, %12-15S"},
3519
2da2eaf4 3520 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3521 MVE_SQSHLL,
3522 0xea51013f, 0xfff1813f,
3523 "sqshll%c\t%17-19l, %9-11h, %j"},
3524
2da2eaf4 3525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3526 MVE_SQSHL,
3527 0xea500f3f, 0xfff08f3f,
3528 "sqshl%c\t%16-19S, %j"},
3529
2da2eaf4 3530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3531 MVE_SRSHRL,
3532 0xea51012f, 0xfff1813f,
3533 "srshrl%c\t%17-19l, %9-11h, %j"},
3534
2da2eaf4 3535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3536 MVE_SRSHR,
3537 0xea500f2f, 0xfff08f3f,
3538 "srshr%c\t%16-19S, %j"},
3539
2da2eaf4 3540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41 3541 MVE_UQRSHLL,
08132bdd
SP		 3542 0xea51010d, 0xfff1017f,
3543 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41 3544
2da2eaf4 3545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3546 MVE_UQRSHL,
3547 0xea500f0d, 0xfff00fff,
3548 "uqrshl%c\t%16-19S, %12-15S"},
3549
2da2eaf4 3550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3551 MVE_UQSHLL,
3552 0xea51010f, 0xfff1813f,
3553 "uqshll%c\t%17-19l, %9-11h, %j"},
3554
2da2eaf4 3555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3556 MVE_UQSHL,
3557 0xea500f0f, 0xfff08f3f,
3558 "uqshl%c\t%16-19S, %j"},
3559
2da2eaf4 3560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3561 MVE_URSHRL,
3562 0xea51011f, 0xfff1813f,
3563 "urshrl%c\t%17-19l, %9-11h, %j"},
3564
2da2eaf4 3565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3566 MVE_URSHR,
3567 0xea500f1f, 0xfff08f3f,
3568 "urshr%c\t%16-19S, %j"},
3569
e39c1607
SD		 3570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3571 MVE_CSINC,
3572 0xea509000, 0xfff0f000,
3573 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3574
3575 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3576 MVE_CSINV,
3577 0xea50a000, 0xfff0f000,
3578 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3579
3580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3581 MVE_CSET,
3582 0xea5f900f, 0xfffff00f,
3583 "cset\t%8-11S, %4-7C"},
3584
3585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3586 MVE_CSETM,
3587 0xea5fa00f, 0xfffff00f,
3588 "csetm\t%8-11S, %4-7C"},
3589
3590 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3591 MVE_CSEL,
3592 0xea508000, 0xfff0f000,
3593 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3594
3595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3596 MVE_CSNEG,
3597 0xea50b000, 0xfff0f000,
3598 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3599
3600 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3601 MVE_CINC,
3602 0xea509000, 0xfff0f000,
3603 "cinc\t%8-11S, %16-19Z, %4-7C"},
3604
3605 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3606 MVE_CINV,
3607 0xea50a000, 0xfff0f000,
3608 "cinv\t%8-11S, %16-19Z, %4-7C"},
3609
3610 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3611 MVE_CNEG,
3612 0xea50b000, 0xfff0f000,
3613 "cneg\t%8-11S, %16-19Z, %4-7C"},
3614
143275ea
AV		 3615 {ARM_FEATURE_CORE_LOW (0),
3616 MVE_NONE,
3617 0x00000000, 0x00000000, 0}
73cd51e5
AV		 3618};
3619
8f06b2d8
PB		 3620/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3621 ordered: they must be searched linearly from the top to obtain a correct
3622 match. */
3623
3624/* print_insn_arm recognizes the following format control codes:
3625
3626 %% %
3627
3628 %a print address for ldr/str instruction
3629 %s print address for ldr/str halfword/signextend instruction
c1e26897 3630 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 3631 %b print branch destination
3632 %c print condition code (always bits 28-31)
3633 %m print register mask for ldm/stm instruction
3634 %o print operand2 (immediate or register + shift)
3635 %p print 'p' iff bits 12-15 are 15
3636 %t print 't' iff bit 21 set and bit 24 clear
3637 %B print arm BLX(1) destination
3638 %C print the PSR sub type.
62b3e311
PB		 3639 %U print barrier type.
3640 %P print address for pli instruction.
8f06b2d8
PB		 3641
3642 %<bitfield>r print as an ARM register
9eb6c0f1 3643 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 3644 %<bitfield>R as %r but r15 is UNPREDICTABLE
3645 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3646 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 3647 %<bitfield>d print the bitfield in decimal
43e65147 3648 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 3649 %<bitfield>x print the bitfield in hex
3650 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 3651
16980d0b
JB		 3652 %<bitfield>'c print specified char iff bitfield is all ones
3653 %<bitfield>`c print specified char iff bitfield is all zeroes
3654 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 3655
8f06b2d8
PB		 3656 %e print arm SMI operand (bits 0..7,8..19).
3657 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 3658 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3659 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 3660
8f06b2d8
PB		 3661static const struct opcode32 arm_opcodes[] =
3662{
3663 /* ARM instructions. */
823d2571
TG		 3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3665 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3667 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3668
3669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3670 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3672 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3674 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3676 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3678 0x00800090, 0x0fa000f0,
3679 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3681 0x00a00090, 0x0fa000f0,
3682 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 3683
105bde57 3684 /* V8.2 RAS extension instructions. */
4d1464f2 3685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3686 0xe320f010, 0xffffffff, "esb"},
3687
26417f19
AC		 3688 /* V8-R instructions. */
3689 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
3690 0xf57ff04c, 0xffffffff, "dfb"},
3691
53c4b28b 3692 /* V8 instructions. */
823d2571
TG		 3693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3694 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 3695 /* Defined in V8 but is in NOP space so available to all arch. */
3696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 3697 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 3698 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 3699 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3700 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 3701 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3703 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3705 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 3706 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3707 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3708 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3709 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3710 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3711 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3712 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3713 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3714 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3715 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3716 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3717 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3718 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3719 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3720 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3721 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3722 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3723 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3724 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 3725 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 3726 /* CRC32 instructions. */
8b301fbb 3727 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3728 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3729 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3730 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3731 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3732 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3733 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3734 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3735 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3736 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3737 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3738 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 3739
ddfded2f
MW		 3740 /* Privileged Access Never extension instructions. */
3741 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3742 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3743
90ec0d68 3744 /* Virtualization Extension instructions. */
823d2571
TG		 3745 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 3747
eea54501 3748 /* Integer Divide Extension instructions. */
823d2571
TG		 3749 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3750 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3752 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 3753
60e5ef9f 3754 /* MP Extension instructions. */
823d2571 3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 3756
c597cc3d
SD		 3757 /* Speculation Barriers. */
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3761
62b3e311 3762 /* V7 instructions. */
823d2571
TG		 3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 3770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3771 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 3772
c19d1205 3773 /* ARM V6T2 instructions. */
823d2571
TG		 3774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3775 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3777 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3779 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3781 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3782
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3784 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3786 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3787
ff8646ee 3788 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3789 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 3790 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3791 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3793 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3795 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 3796
f4c65163 3797 /* ARM Security extension instructions. */
823d2571
TG		 3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3799 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 3800
8f06b2d8 3801 /* ARM V6K instructions. */
823d2571
TG		 3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3803 0xf57ff01f, 0xffffffff, "clrex"},
3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3805 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3807 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3809 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3811 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3813 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3815 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 3816
7fadb25d
SD		 3817 /* ARMv8.5-A instructions. */
3818 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3819
8f06b2d8 3820 /* ARM V6K NOP hints. */
823d2571
TG		 3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3822 0x0320f001, 0x0fffffff, "yield%c"},
3823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3824 0x0320f002, 0x0fffffff, "wfe%c"},
3825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3826 0x0320f003, 0x0fffffff, "wfi%c"},
3827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3828 0x0320f004, 0x0fffffff, "sev%c"},
3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3830 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 3831
fe56b6ce 3832 /* ARM V6 instructions. */
823d2571
TG		 3833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3834 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3836 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3838 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3840 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3842 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3844 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3846 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3848 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3850 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3852 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3854 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3856 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3858 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3860 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3862 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3864 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3866 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3868 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3870 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3872 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3874 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3876 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3878 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3880 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3882 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3884 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3886 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3888 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3890 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3892 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3894 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3896 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3898 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3900 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3902 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3904 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3906 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3908 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3910 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3912 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3914 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3916 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3918 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3920 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3922 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3924 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3926 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3928 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3930 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3932 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3934 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3936 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3938 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3940 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3942 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3944 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3946 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3948 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3950 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3952 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3954 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3956 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3958 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3960 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3962 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3964 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3966 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3968 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3970 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3972 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3974 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3976 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3978 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3980 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3982 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3984 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3986 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3988 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3990 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3992 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3994 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3996 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3998 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4000 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4002 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4004 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4006 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
4007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4008 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4010 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4012 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4014 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
4015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4016 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4018 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4020 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4022 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4024 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4026 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4028 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4030 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
4031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4032 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
4033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4034 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
4035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4036 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4038 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4040 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4042 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4044 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4046 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
4047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4048 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4050 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4052 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4054 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4056 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
4057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4058 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
4059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4060 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
4061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4062 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4064 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4066 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4068 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4070 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4072 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4074 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4076 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 4077
8f06b2d8 4078 /* V5J instruction. */
823d2571
TG		 4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
4080 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 4081
8f06b2d8 4082 /* V5 Instructions. */
823d2571
TG		 4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4084 0xe1200070, 0xfff000f0,
4085 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
4086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4087 0xfa000000, 0xfe000000, "blx\t%B"},
4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4089 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4091 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
4092
4093 /* V5E "El Segundo" Instructions. */
4094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4095 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
4096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4097 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
4098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4099 0xf450f000, 0xfc70f000, "pld\t%a"},
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4101 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4103 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4105 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4107 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4108
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4110 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4112 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4113
4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4115 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4117 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4119 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4121 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4122
4123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4124 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4126 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4128 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4130 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4131
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4133 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4135 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4136
4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4138 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4140 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4142 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4144 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 4145
8f06b2d8 4146 /* ARM Instructions. */
823d2571
TG		 4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4148 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4149
4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4151 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4153 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4155 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4157 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4161 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4162
4163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4164 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4166 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4168 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4170 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4171
4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4173 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4175 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4177 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4179 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4180
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4182 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4184 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4186 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4187
4188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4189 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4191 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4193 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4194
4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4196 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4198 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4200 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4201
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4203 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4205 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4207 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4208
4209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4210 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4212 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4214 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4215
4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4217 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4219 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4221 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4222
4223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4224 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4226 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4228 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4229
4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4231 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4233 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4235 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4236
4237 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4238 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4240 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4242 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4243
4244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4245 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4247 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4249 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4250
4251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4252 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4254 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4256 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 4257
4258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4259 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4261 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4263 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4264
4265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4266 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4268 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4270 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4271
4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4273 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4275 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4277 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4278
4279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4280 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4282 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4284 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4286 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4288 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4290 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4292 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4293
4294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4295 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4297 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4299 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4300
4301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4302 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4304 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4306 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4307
4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4309 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4311 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4312
4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4314 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4315
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4317 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4319 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4320
4321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4322 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4324 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4326 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4328 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4330 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4332 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4334 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4336 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4338 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4340 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4342 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4344 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4346 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4348 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4350 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4352 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4354 0x092d0000, 0x0fff0000, "push%c\t%m"},
4355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4356 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4358 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4359
4360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4361 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4363 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4365 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4367 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4369 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4371 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4373 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4375 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4377 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4379 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4381 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4383 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4385 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4387 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4389 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4391 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4393 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4395 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4397 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4398
4399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4400 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4402 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 4403
4404 /* The rest. */
4ab90a7a
AV		 4405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4406 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 4407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4408 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4409 {ARM_FEATURE_CORE_LOW (0),
4410 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 4411};
4412
4413/* print_insn_thumb16 recognizes the following format control codes:
4414
4415 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4416 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4417 %<bitfield>I print bitfield as a signed decimal
4418 (top bit of range being the sign bit)
4419 %N print Thumb register mask (with LR)
4420 %O print Thumb register mask (with PC)
4421 %M print Thumb register mask
4422 %b print CZB's 6-bit unsigned branch destination
4423 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 4424 %c print the condition code
4425 %C print the condition code, or "s" if not conditional
4426 %x print warning if conditional an not at end of IT block"
4427 %X print "\t; unpredictable <IT:code>" if conditional
4428 %I print IT instruction suffix and operands
4547cb56 4429 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 4430 %<bitfield>r print bitfield as an ARM register
4431 %<bitfield>d print bitfield as a decimal
4432 %<bitfield>H print (bitfield * 2) as a decimal
4433 %<bitfield>W print (bitfield * 4) as a decimal
4434 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4435 %<bitfield>B print Thumb branch destination (signed displacement)
4436 %<bitfield>c print bitfield as a condition code
4437 %<bitnum>'c print specified char iff bit is one
4438 %<bitnum>?ab print a if bit is one else print b. */
4439
4440static const struct opcode16 thumb_opcodes[] =
4441{
4442 /* Thumb instructions. */
4443
16a1fa25
TP		 4444 /* ARMv8-M Security Extensions instructions. */
4445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 4446 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 4447
53c4b28b 4448 /* ARM V8 instructions. */
823d2571
TG		 4449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 4451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 4452
8f06b2d8 4453 /* ARM V6K no-argument instructions. */
823d2571
TG		 4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 4460
4461 /* ARM V6T2 instructions. */
ff8646ee
TP		 4462 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4463 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4464 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4465 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 4467
4468 /* ARM V6. */
823d2571
TG		 4469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 4480
4481 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 4482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4483 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 4484 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 4485 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4486 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 4487 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 4488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4489 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 4490 /* Format 4. */
823d2571
TG		 4491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 4507 /* format 13 */
823d2571
TG		 4508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 4510 /* format 5 */
823d2571
TG		 4511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 4515 /* format 14 */
823d2571
TG		 4516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 4518 /* format 2 */
823d2571
TG		 4519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4520 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4522 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4524 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4526 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 4527 /* format 8 */
823d2571
TG		 4528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4529 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4531 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4533 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4534 /* format 7 */
823d2571
TG		 4535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4536 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4538 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4539 /* format 1 */
823d2571
TG		 4540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4542 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 4545 /* format 3 */
823d2571
TG		 4546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 4550 /* format 6 */
823d2571
TG		 4551 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4553 0x4800, 0xF800,
4554 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 4555 /* format 9 */
823d2571
TG		 4556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4557 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4559 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4561 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4563 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 4564 /* format 10 */
823d2571
TG		 4565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4566 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4568 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 4569 /* format 11 */
823d2571
TG		 4570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4571 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4573 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 4574 /* format 12 */
823d2571
TG		 4575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4576 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4578 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 4579 /* format 15 */
823d2571
TG		 4580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 4582 /* format 17 */
823d2571 4583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 4584 /* format 16 */
823d2571
TG		 4585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 4588 /* format 18 */
823d2571 4589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 4590
4591 /* The E800 .. FFFF range is unconditionally redirected to the
4592 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4593 are processed via that table. Thus, we can never encounter a
4594 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 4595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4596 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 4597};
4598
4599/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4600 We adopt the convention that hw1 is the high 16 bits of .value and
4601 .mask, hw2 the low 16 bits.
4602
4603 print_insn_thumb32 recognizes the following format control codes:
4604
4605 %% %
4606
4607 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4608 %M print a modified 12-bit immediate (same location)
4609 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4610 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 4611 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 4612 %S print a possibly-shifted Rm
4613
32a94698 4614 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 4615 %a print the address of a plain load/store
4616 %w print the width and signedness of a core load/store
4617 %m print register mask for ldm/stm
4b5a202f 4618 %n print register mask for clrm
8f06b2d8
PB		 4619
4620 %E print the lsb and width fields of a bfc/bfi instruction
4621 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 4622 %G print a fallback offset for Branch Future instructions
e5d6e09e 4623 %W print an offset for BF instruction
1caf72a5 4624 %Y print an offset for BFL instruction
1889da70 4625 %Z print an offset for BFCSEL instruction
60f993ce
AV		 4626 %Q print an offset for Low Overhead Loop instructions
4627 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 4628 %b print a conditional branch offset
4629 %B print an unconditional branch offset
4630 %s print the shift field of an SSAT instruction
4631 %R print the rotation field of an SXT instruction
62b3e311
PB		 4632 %U print barrier type.
4633 %P print address for pli instruction.
c22aaad1
PB		 4634 %c print the condition code
4635 %x print warning if conditional an not at end of IT block"
4636 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 4637
4638 %<bitfield>d print bitfield in decimal
f0fba320 4639 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 4640 %<bitfield>W print bitfield*4 in decimal
4641 %<bitfield>r print bitfield as an ARM register
dd5181d5 4642 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 4643 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 4644 %<bitfield>c print bitfield as a condition code
4645
16980d0b
JB		 4646 %<bitfield>'c print specified char iff bitfield is all ones
4647 %<bitfield>`c print specified char iff bitfield is all zeroes
4648 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 4649
4650 With one exception at the bottom (done because BL and BLX(1) need
4651 to come dead last), this table was machine-sorted first in
4652 decreasing order of number of bits set in the mask, then in
4653 increasing numeric order of mask, then in increasing numeric order
4654 of opcode. This order is not the clearest for a human reader, but
4655 is guaranteed never to catch a special-case bit pattern with a more
4656 general mask, which is important, because this instruction encoding
4657 makes heavy use of special-case bit patterns. */
4658static const struct opcode32 thumb32_opcodes[] =
4659{
4b5a202f
AV		 4660 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4661 instructions. */
60f993ce 4662 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
d052b9b7 4663 0xf00fe001, 0xffffffff, "lctp%c"},
60f993ce
AV		 4664 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4665 0xf02fc001, 0xfffff001, "le\t%P"},
4666 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4667 0xf00fc001, 0xfffff001, "le\tlr, %P"},
d052b9b7
AV		 4668 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4669 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4670 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4671 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4672 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4673 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4674 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4675 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4676 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4677 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
60f993ce 4678
4389b29a
AV		 4679 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4680 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 4681 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4682 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 4683 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4684 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 4685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4686 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 4687 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4688 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 4689
4b5a202f
AV		 4690 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4691 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 4692
16a1fa25
TP		 4693 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4694 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 4695 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4696 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4698 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 4699 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4700 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4701 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4702 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 4703
105bde57 4704 /* ARM V8.2 RAS extension instructions. */
4d1464f2 4705 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 4706 0xf3af8010, 0xffffffff, "esb"},
4707
53c4b28b 4708 /* V8 instructions. */
823d2571
TG		 4709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4710 0xf3af8005, 0xffffffff, "sevl%c.w"},
4711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4712 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4714 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4716 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4718 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4720 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4722 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4724 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4726 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4728 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4730 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4732 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4734 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4736 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4738 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4740 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 4741
26417f19
AC		 4742 /* V8-R instructions. */
4743 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
4744 0xf3bf8f4c, 0xffffffff, "dfb%c"},
4745
dd5181d5 4746 /* CRC32 instructions. */
8b301fbb 4747 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4748 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4749 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4750 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
8b301fbb 4751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4752 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4753 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4754 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4755 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4756 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4757 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4758 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 4759
c597cc3d
SD		 4760 /* Speculation Barriers. */
4761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4764
62b3e311 4765 /* V7 instructions. */
823d2571
TG		 4766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4773 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4774 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4775 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4776 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 4777
90ec0d68 4778 /* Virtualization Extension instructions. */
823d2571 4779 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 4780 /* We skip ERET as that is SUBS pc, lr, #0. */
4781
60e5ef9f 4782 /* MP Extension instructions. */
823d2571 4783 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 4784
f4c65163 4785 /* Security extension instructions. */
823d2571 4786 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 4787
7fadb25d
SD		 4788 /* ARMv8.5-A instructions. */
4789 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4790
8f06b2d8 4791 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 4792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4798 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4800
ff8646ee 4801 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4802 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4804 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4806 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4808 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4810 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4812 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4814 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4816 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4818 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4820 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4822 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4824 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4826 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4828 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 4829 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 4830 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 4831 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4832 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4834 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4836 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4838 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4840 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4842 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4844 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4846 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4848 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 4849 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4850 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4852 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4854 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4856 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4858 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4860 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4862 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4864 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4866 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4868 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4870 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4872 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4874 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4876 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4878 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4880 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4882 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4884 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4886 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4888 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4890 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4892 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4894 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4896 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4898 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4900 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4902 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4904 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4906 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4908 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4910 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4912 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4914 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4916 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4918 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4920 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4922 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4924 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4926 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4928 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4930 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4932 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4934 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4936 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4938 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4940 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4942 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4944 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4946 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4948 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4950 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4952 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4954 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4956 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4958 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4960 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 4961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4962 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4964 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4966 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4968 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4970 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4972 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4974 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4976 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4978 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4980 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4982 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4984 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4986 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4988 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4990 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4992 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4994 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4996 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4998 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5000 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
5001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5002 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
5003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5004 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
5005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5006 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
5007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5008 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
5009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5010 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5012 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5014 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5016 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5018 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5020 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5022 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5024 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 5025 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5026 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
5027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5028 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
5029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5030 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
5031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5032 0xf810f000, 0xff70f000, "pld%c\t%a"},
5033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5034 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5036 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5038 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5040 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5042 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5044 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5046 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5048 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
5049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5050 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
5051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5052 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
5053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5054 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
5055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5056 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
5057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5058 0xfb100000, 0xfff000c0,
5059 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5061 0xfbc00080, 0xfff000c0,
5062 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
5063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5064 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
5065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5066 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
5067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 5068 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 5069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5070 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
5071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5072 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 5073 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5074 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
5075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5076 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 5077 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5078 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
5079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5080 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
5081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5082 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
5083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5084 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
5085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5086 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
5087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5088 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
5089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5090 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
5091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5092 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
5093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5094 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
5095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5096 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
5097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5098 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 5099 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5100 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
5101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5102 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
5103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5104 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
5105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5106 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5108 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5110 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5112 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5114 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5116 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5118 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5120 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5122 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5124 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5126 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5128 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5130 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5132 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5134 0xe9400000, 0xff500000,
5135 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5137 0xe9500000, 0xff500000,
5138 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5140 0xe8600000, 0xff700000,
5141 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5143 0xe8700000, 0xff700000,
5144 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5146 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5148 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 5149
5150 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 5151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5152 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5154 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5156 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5158 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 5159
8f06b2d8 5160 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 5161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5162 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5164 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 5165
5166 /* Fallback. */
823d2571
TG		 5167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5168 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5169 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 5170};
ff4a8d2b 5171
8f06b2d8
PB		 5172static const char *const arm_conditional[] =
5173{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 5174 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 5175
5176static const char *const arm_fp_const[] =
5177{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5178
5179static const char *const arm_shift[] =
5180{"lsl", "lsr", "asr", "ror"};
5181
5182typedef struct
5183{
5184 const char *name;
5185 const char *description;
5186 const char *reg_names[16];
5187}
5188arm_regname;
5189
5190static const arm_regname regnames[] =
5191{
65b48a81 5192 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 5193 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 5194 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 5195 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5196 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 5197 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 5198 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5199 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5200 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 5201 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5202 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 5203 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81 5204 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4934a27c
MM		 5205 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
5206 { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } }
8f06b2d8
PB		 5207};
5208
5209static const char *const iwmmxt_wwnames[] =
5210{"b", "h", "w", "d"};
5211
5212static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 5213{"b", "bus", "bc", "bss",
5214 "h", "hus", "hc", "hss",
5215 "w", "wus", "wc", "wss",
5216 "d", "dus", "dc", "dss"
8f06b2d8
PB		 5217};
5218
5219static const char *const iwmmxt_regnames[] =
5220{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5221 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5222};
5223
5224static const char *const iwmmxt_cregnames[] =
5225{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5226 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5227};
5228
143275ea
AV		 5229static const char *const vec_condnames[] =
5230{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5231};
5232
5233static const char *const mve_predicatenames[] =
5234{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5235 "eee", "ee", "eet", "e", "ett", "et", "ete"
5236};
5237
5238/* Names for 2-bit size field for mve vector isntructions. */
5239static const char *const mve_vec_sizename[] =
5240 { "8", "16", "32", "64"};
5241
5242/* Indicates whether we are processing a then predicate,
5243 else predicate or none at all. */
5244enum vpt_pred_state
5245{
5246 PRED_NONE,
5247 PRED_THEN,
5248 PRED_ELSE
5249};
5250
5251/* Information used to process a vpt block and subsequent instructions. */
5252struct vpt_block
5253{
5254 /* Are we in a vpt block. */
5255 bfd_boolean in_vpt_block;
5256
5257 /* Next predicate state if in vpt block. */
5258 enum vpt_pred_state next_pred_state;
5259
5260 /* Mask from vpt/vpst instruction. */
5261 long predicate_mask;
5262
5263 /* Instruction number in vpt block. */
5264 long current_insn_num;
5265
5266 /* Number of instructions in vpt block.. */
5267 long num_pred_insn;
5268};
5269
5270static struct vpt_block vpt_block_state =
5271{
5272 FALSE,
5273 PRED_NONE,
5274 0,
5275 0,
5276 0
5277};
5278
8f06b2d8
PB		 5279/* Default to GCC register name set. */
5280static unsigned int regname_selected = 1;
5281
65b48a81 5282#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 5283#define arm_regnames regnames[regname_selected].reg_names
5284
5285static bfd_boolean force_thumb = FALSE;
4934a27c 5286static uint16_t cde_coprocs = 0;
8f06b2d8 5287
c22aaad1
PB		 5288/* Current IT instruction state. This contains the same state as the IT
5289 bits in the CPSR. */
5290static unsigned int ifthen_state;
5291/* IT state for the next instruction. */
5292static unsigned int ifthen_next_state;
5293/* The address of the insn for which the IT state is valid. */
5294static bfd_vma ifthen_address;
5295#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 5296/* Indicates that the current Conditional state is unconditional or outside
5297 an IT block. */
5298#define COND_UNCOND 16
c22aaad1 5299
8f06b2d8
PB		 5300\f
5301/* Functions. */
143275ea
AV		 5302/* Extract the predicate mask for a VPT or VPST instruction.
5303 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5304
5305static long
5306mve_extract_pred_mask (long given)
5307{
5308 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5309}
5310
5311/* Return the number of instructions in a MVE predicate block. */
5312static long
5313num_instructions_vpt_block (long given)
5314{
5315 long mask = mve_extract_pred_mask (given);
5316 if (mask == 0)
5317 return 0;
5318
5319 if (mask == 8)
5320 return 1;
5321
5322 if ((mask & 7) == 4)
5323 return 2;
5324
5325 if ((mask & 3) == 2)
5326 return 3;
5327
5328 if ((mask & 1) == 1)
5329 return 4;
5330
5331 return 0;
5332}
5333
5334static void
5335mark_outside_vpt_block (void)
5336{
5337 vpt_block_state.in_vpt_block = FALSE;
5338 vpt_block_state.next_pred_state = PRED_NONE;
5339 vpt_block_state.predicate_mask = 0;
5340 vpt_block_state.current_insn_num = 0;
5341 vpt_block_state.num_pred_insn = 0;
5342}
5343
5344static void
5345mark_inside_vpt_block (long given)
5346{
5347 vpt_block_state.in_vpt_block = TRUE;
5348 vpt_block_state.next_pred_state = PRED_THEN;
5349 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5350 vpt_block_state.current_insn_num = 0;
5351 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5352 assert (vpt_block_state.num_pred_insn >= 1);
5353}
5354
5355static enum vpt_pred_state
5356invert_next_predicate_state (enum vpt_pred_state astate)
5357{
5358 if (astate == PRED_THEN)
5359 return PRED_ELSE;
5360 else if (astate == PRED_ELSE)
5361 return PRED_THEN;
5362 else
5363 return PRED_NONE;
5364}
5365
5366static enum vpt_pred_state
5367update_next_predicate_state (void)
5368{
5369 long pred_mask = vpt_block_state.predicate_mask;
5370 long mask_for_insn = 0;
5371
5372 switch (vpt_block_state.current_insn_num)
5373 {
5374 case 1:
5375 mask_for_insn = 8;
5376 break;
5377
5378 case 2:
5379 mask_for_insn = 4;
5380 break;
5381
5382 case 3:
5383 mask_for_insn = 2;
5384 break;
5385
5386 case 4:
5387 return PRED_NONE;
5388 }
5389
5390 if (pred_mask & mask_for_insn)
5391 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5392 else
5393 return vpt_block_state.next_pred_state;
5394}
5395
5396static void
5397update_vpt_block_state (void)
5398{
5399 vpt_block_state.current_insn_num++;
5400 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5401 {
5402 /* No more instructions to process in vpt block. */
5403 mark_outside_vpt_block ();
5404 return;
5405 }
5406
5407 vpt_block_state.next_pred_state = update_next_predicate_state ();
5408}
8f06b2d8 5409
16980d0b
JB		 5410/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5411 Returns pointer to following character of the format string and
5412 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 5413 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 5414
5415static const char *
fe56b6ce
NC		 5416arm_decode_bitfield (const char *ptr,
5417 unsigned long insn,
5418 unsigned long *valuep,
5419 int *widthp)
16980d0b
JB		 5420{
5421 unsigned long value = 0;
5422 int width = 0;
43e65147
L		 5423
5424 do
16980d0b
JB		 5425 {
5426 int start, end;
5427 int bits;
5428
5429 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5430 start = start * 10 + *ptr - '0';
5431 if (*ptr == '-')
5432 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5433 end = end * 10 + *ptr - '0';
5434 else
5435 end = start;
5436 bits = end - start;
5437 if (bits < 0)
5438 abort ();
5439 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5440 width += bits + 1;
5441 }
5442 while (*ptr++ == ',');
5443 *valuep = value;
5444 if (widthp)
5445 *widthp = width;
5446 return ptr - 1;
5447}
5448
8f06b2d8 5449static void
37b37b2d 5450arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 5451 bfd_boolean print_shift)
8f06b2d8
PB		 5452{
5453 func (stream, "%s", arm_regnames[given & 0xf]);
5454
5455 if ((given & 0xff0) != 0)
5456 {
5457 if ((given & 0x10) == 0)
5458 {
5459 int amount = (given & 0xf80) >> 7;
5460 int shift = (given & 0x60) >> 5;
5461
5462 if (amount == 0)
5463 {
5464 if (shift == 3)
5465 {
5466 func (stream, ", rrx");
5467 return;
5468 }
5469
5470 amount = 32;
5471 }
5472
37b37b2d
RE		 5473 if (print_shift)
5474 func (stream, ", %s #%d", arm_shift[shift], amount);
5475 else
5476 func (stream, ", #%d", amount);
8f06b2d8 5477 }
74bdfecf 5478 else if ((given & 0x80) == 0x80)
aefd8a40 5479 func (stream, "\t; <illegal shifter operand>");
37b37b2d 5480 else if (print_shift)
8f06b2d8
PB		 5481 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5482 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 5483 else
5484 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 5485 }
5486}
5487
73cd51e5
AV		 5488/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5489
5490static bfd_boolean
5491is_mve_okay_in_it (enum mve_instructions matched_insn)
5492{
c507f10b
AV		 5493 switch (matched_insn)
5494 {
5495 case MVE_VMOV_GP_TO_VEC_LANE:
5496 case MVE_VMOV2_VEC_LANE_TO_GP:
5497 case MVE_VMOV2_GP_TO_VEC_LANE:
5498 case MVE_VMOV_VEC_LANE_TO_GP:
23d00a41
SD		 5499 case MVE_LSLL:
5500 case MVE_LSLLI:
5501 case MVE_LSRL:
5502 case MVE_ASRL:
5503 case MVE_ASRLI:
5504 case MVE_SQRSHRL:
5505 case MVE_SQRSHR:
5506 case MVE_UQRSHL:
5507 case MVE_UQRSHLL:
5508 case MVE_UQSHL:
5509 case MVE_UQSHLL:
5510 case MVE_URSHRL:
5511 case MVE_URSHR:
5512 case MVE_SRSHRL:
5513 case MVE_SRSHR:
5514 case MVE_SQSHLL:
5515 case MVE_SQSHL:
c507f10b
AV		 5516 return TRUE;
5517 default:
5518 return FALSE;
5519 }
73cd51e5
AV		 5520}
5521
5522static bfd_boolean
5523is_mve_architecture (struct disassemble_info *info)
5524{
5525 struct arm_private_data *private_data = info->private_data;
5526 arm_feature_set allowed_arches = private_data->features;
5527
5528 arm_feature_set arm_ext_v8_1m_main
5529 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5530
5531 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5532 && !ARM_CPU_IS_ANY (allowed_arches))
5533 return TRUE;
5534 else
5535 return FALSE;
5536}
5537
143275ea
AV		 5538static bfd_boolean
5539is_vpt_instruction (long given)
5540{
5541
5542 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5543 if ((given & 0x0040e000) == 0)
5544 return FALSE;
5545
5546 /* VPT floating point T1 variant. */
5547 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5548 /* VPT floating point T2 variant. */
5549 || ((given & 0xefb10f50) == 0xee310f40)
5550 /* VPT vector T1 variant. */
5551 || ((given & 0xff811f51) == 0xfe010f00)
5552 /* VPT vector T2 variant. */
5553 || ((given & 0xff811f51) == 0xfe010f01
5554 && ((given & 0x300000) != 0x300000))
5555 /* VPT vector T3 variant. */
5556 || ((given & 0xff811f50) == 0xfe011f00)
5557 /* VPT vector T4 variant. */
5558 || ((given & 0xff811f70) == 0xfe010f40)
5559 /* VPT vector T5 variant. */
5560 || ((given & 0xff811f70) == 0xfe010f60)
5561 /* VPT vector T6 variant. */
5562 || ((given & 0xff811f50) == 0xfe011f40)
5563 /* VPST vector T variant. */
5564 || ((given & 0xffbf1fff) == 0xfe310f4d))
5565 return TRUE;
5566 else
5567 return FALSE;
5568}
5569
73cd51e5
AV		 5570/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5571 and ending bitfield = END. END must be greater than START. */
5572
5573static unsigned long
5574arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5575{
5576 int bits = end - start;
5577
5578 if (bits < 0)
5579 abort ();
5580
5581 return ((given >> start) & ((2ul << bits) - 1));
5582}
5583
5584/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5585 START:END and START2:END2. END/END2 must be greater than
5586 START/START2. */
5587
5588static unsigned long
5589arm_decode_field_multiple (unsigned long given, unsigned int start,
5590 unsigned int end, unsigned int start2,
5591 unsigned int end2)
5592{
5593 int bits = end - start;
5594 int bits2 = end2 - start2;
5595 unsigned long value = 0;
5596 int width = 0;
5597
5598 if (bits2 < 0)
5599 abort ();
5600
5601 value = arm_decode_field (given, start, end);
5602 width += bits + 1;
5603
5604 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5605 return value;
5606}
5607
5608/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5609 This helps us decode instructions that change mnemonic depending on specific
5610 operand values/encodings. */
5611
5612static bfd_boolean
5613is_mve_encoding_conflict (unsigned long given,
5614 enum mve_instructions matched_insn)
5615{
143275ea
AV		 5616 switch (matched_insn)
5617 {
5618 case MVE_VPST:
5619 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5620 return TRUE;
5621 else
5622 return FALSE;
5623
5624 case MVE_VPT_FP_T1:
5625 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5626 return TRUE;
5627 if ((arm_decode_field (given, 12, 12) == 0)
5628 && (arm_decode_field (given, 0, 0) == 1))
5629 return TRUE;
5630 return FALSE;
5631
5632 case MVE_VPT_FP_T2:
5633 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5634 return TRUE;
5635 if (arm_decode_field (given, 0, 3) == 0xd)
5636 return TRUE;
5637 return FALSE;
5638
5639 case MVE_VPT_VEC_T1:
5640 case MVE_VPT_VEC_T2:
5641 case MVE_VPT_VEC_T3:
5642 case MVE_VPT_VEC_T4:
5643 case MVE_VPT_VEC_T5:
5644 case MVE_VPT_VEC_T6:
5645 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5646 return TRUE;
5647 if (arm_decode_field (given, 20, 21) == 3)
5648 return TRUE;
5649 return FALSE;
5650
5651 case MVE_VCMP_FP_T1:
5652 if ((arm_decode_field (given, 12, 12) == 0)
5653 && (arm_decode_field (given, 0, 0) == 1))
5654 return TRUE;
5655 else
5656 return FALSE;
5657
5658 case MVE_VCMP_FP_T2:
5659 if (arm_decode_field (given, 0, 3) == 0xd)
5660 return TRUE;
5661 else
5662 return FALSE;
5663
14b456f2
AV		 5664 case MVE_VQADD_T2:
5665 case MVE_VQSUB_T2:
f49bb598
AV		 5666 case MVE_VMUL_VEC_T2:
5667 case MVE_VMULH:
5668 case MVE_VRMULH:
56858bea
AV		 5669 case MVE_VMLA:
5670 case MVE_VMAX:
5671 case MVE_VMIN:
e523f101 5672 case MVE_VBRSR:
66dcaa5d
AV		 5673 case MVE_VADD_VEC_T2:
5674 case MVE_VSUB_VEC_T2:
5675 case MVE_VABAV:
ed63aa17
AV		 5676 case MVE_VQRSHL_T1:
5677 case MVE_VQSHL_T4:
5678 case MVE_VRSHL_T1:
5679 case MVE_VSHL_T3:
897b9bbc
AV		 5680 case MVE_VCADD_VEC:
5681 case MVE_VHCADD:
1c8f2df8
AV		 5682 case MVE_VDDUP:
5683 case MVE_VIDUP:
d3b63143
AV		 5684 case MVE_VQRDMLADH:
5685 case MVE_VQDMLAH:
5686 case MVE_VQRDMLAH:
5687 case MVE_VQDMLASH:
5688 case MVE_VQRDMLASH:
5689 case MVE_VQDMLSDH:
5690 case MVE_VQRDMLSDH:
5691 case MVE_VQDMULH_T3:
5692 case MVE_VQRDMULH_T4:
5693 case MVE_VQDMLADH:
5694 case MVE_VMLAS:
14925797 5695 case MVE_VMULL_INT:
9743db03
AV		 5696 case MVE_VHADD_T2:
5697 case MVE_VHSUB_T2:
143275ea
AV		 5698 case MVE_VCMP_VEC_T1:
5699 case MVE_VCMP_VEC_T2:
5700 case MVE_VCMP_VEC_T3:
5701 case MVE_VCMP_VEC_T4:
5702 case MVE_VCMP_VEC_T5:
5703 case MVE_VCMP_VEC_T6:
5704 if (arm_decode_field (given, 20, 21) == 3)
5705 return TRUE;
5706 else
5707 return FALSE;
5708
04d54ace
AV		 5709 case MVE_VLD2:
5710 case MVE_VLD4:
5711 case MVE_VST2:
5712 case MVE_VST4:
5713 if (arm_decode_field (given, 7, 8) == 3)
5714 return TRUE;
5715 else
5716 return FALSE;
5717
aef6d006
AV		 5718 case MVE_VSTRB_T1:
5719 case MVE_VSTRH_T2:
5720 if ((arm_decode_field (given, 24, 24) == 0)
5721 && (arm_decode_field (given, 21, 21) == 0))
5722 {
5723 return TRUE;
5724 }
5725 else if ((arm_decode_field (given, 7, 8) == 3))
5726 return TRUE;
5727 else
5728 return FALSE;
5729
5730 case MVE_VSTRB_T5:
5731 case MVE_VSTRH_T6:
5732 case MVE_VSTRW_T7:
5733 if ((arm_decode_field (given, 24, 24) == 0)
5734 && (arm_decode_field (given, 21, 21) == 0))
5735 {
5736 return TRUE;
5737 }
5738 else
5739 return FALSE;
5740
bf0b396d
AV		 5741 case MVE_VCVT_FP_FIX_VEC:
5742 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5743
c507f10b
AV		 5744 case MVE_VBIC_IMM:
5745 case MVE_VORR_IMM:
5746 {
5747 unsigned long cmode = arm_decode_field (given, 8, 11);
5748
5749 if ((cmode & 1) == 0)
5750 return TRUE;
5751 else if ((cmode & 0xc) == 0xc)
5752 return TRUE;
5753 else
5754 return FALSE;
5755 }
5756
5757 case MVE_VMVN_IMM:
5758 {
5759 unsigned long cmode = arm_decode_field (given, 8, 11);
5760
ce760a76 5761 if (cmode == 0xe)
c507f10b 5762 return TRUE;
ce760a76 5763 else if ((cmode & 0x9) == 1)
c507f10b 5764 return TRUE;
ce760a76 5765 else if ((cmode & 0xd) == 9)
c507f10b
AV		 5766 return TRUE;
5767 else
5768 return FALSE;
5769 }
5770
5771 case MVE_VMOV_IMM_TO_VEC:
5772 if ((arm_decode_field (given, 5, 5) == 1)
5773 && (arm_decode_field (given, 8, 11) != 0xe))
5774 return TRUE;
5775 else
5776 return FALSE;
5777
14925797
AV		 5778 case MVE_VMOVL:
5779 {
5780 unsigned long size = arm_decode_field (given, 19, 20);
5781 if ((size == 0) || (size == 3))
5782 return TRUE;
5783 else
5784 return FALSE;
5785 }
5786
56858bea
AV		 5787 case MVE_VMAXA:
5788 case MVE_VMINA:
5789 case MVE_VMAXV:
5790 case MVE_VMAXAV:
5791 case MVE_VMINV:
5792 case MVE_VMINAV:
ed63aa17
AV		 5793 case MVE_VQRSHL_T2:
5794 case MVE_VQSHL_T1:
5795 case MVE_VRSHL_T2:
5796 case MVE_VSHL_T2:
5797 case MVE_VSHLL_T2:
d3b63143 5798 case MVE_VADDV:
14925797
AV		 5799 case MVE_VMOVN:
5800 case MVE_VQMOVUN:
5801 case MVE_VQMOVN:
5802 if (arm_decode_field (given, 18, 19) == 3)
5803 return TRUE;
5804 else
5805 return FALSE;
5806
d3b63143
AV		 5807 case MVE_VMLSLDAV:
5808 case MVE_VRMLSLDAVH:
5809 case MVE_VMLALDAV:
5810 case MVE_VADDLV:
5811 if (arm_decode_field (given, 20, 22) == 7)
5812 return TRUE;
5813 else
5814 return FALSE;
5815
5816 case MVE_VRMLALDAVH:
5817 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5818 return TRUE;
5819 else
5820 return FALSE;
5821
1c8f2df8
AV		 5822 case MVE_VDWDUP:
5823 case MVE_VIWDUP:
5824 if ((arm_decode_field (given, 20, 21) == 3)
5825 || (arm_decode_field (given, 1, 3) == 7))
5826 return TRUE;
5827 else
5828 return FALSE;
5829
ed63aa17
AV		 5830
5831 case MVE_VSHLL_T1:
5832 if (arm_decode_field (given, 16, 18) == 0)
5833 {
5834 unsigned long sz = arm_decode_field (given, 19, 20);
5835
5836 if ((sz == 1) || (sz == 2))
5837 return TRUE;
5838 else
5839 return FALSE;
5840 }
5841 else
5842 return FALSE;
5843
5844 case MVE_VQSHL_T2:
5845 case MVE_VQSHLU_T3:
5846 case MVE_VRSHR:
5847 case MVE_VSHL_T1:
5848 case MVE_VSHR:
5849 case MVE_VSLI:
5850 case MVE_VSRI:
5851 if (arm_decode_field (given, 19, 21) == 0)
5852 return TRUE;
5853 else
5854 return FALSE;
5855
e523f101
AV		 5856 case MVE_VCTP:
5857 if (arm_decode_field (given, 16, 19) == 0xf)
5858 return TRUE;
5859 else
5860 return FALSE;
5861
23d00a41
SD		 5862 case MVE_ASRLI:
5863 case MVE_ASRL:
5864 case MVE_LSLLI:
5865 case MVE_LSLL:
5866 case MVE_LSRL:
5867 case MVE_SQRSHRL:
5868 case MVE_SQSHLL:
5869 case MVE_SRSHRL:
5870 case MVE_UQRSHLL:
5871 case MVE_UQSHLL:
5872 case MVE_URSHRL:
5873 if (arm_decode_field (given, 9, 11) == 0x7)
5874 return TRUE;
5875 else
5876 return FALSE;
5877
e39c1607
SD		 5878 case MVE_CSINC:
5879 case MVE_CSINV:
5880 {
5881 unsigned long rm, rn;
5882 rm = arm_decode_field (given, 0, 3);
5883 rn = arm_decode_field (given, 16, 19);
5884 /* CSET/CSETM. */
5885 if (rm == 0xf && rn == 0xf)
5886 return TRUE;
5887 /* CINC/CINV. */
5888 else if (rn == rm && rn != 0xf)
5889 return TRUE;
5890 }
5891 /* Fall through. */
5892 case MVE_CSEL:
5893 case MVE_CSNEG:
5894 if (arm_decode_field (given, 0, 3) == 0xd)
5895 return TRUE;
5896 /* CNEG. */
5897 else if (matched_insn == MVE_CSNEG)
5898 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5899 return TRUE;
5900 return FALSE;
5901
143275ea 5902 default:
66dcaa5d
AV		 5903 case MVE_VADD_FP_T1:
5904 case MVE_VADD_FP_T2:
5905 case MVE_VADD_VEC_T1:
143275ea
AV		 5906 return FALSE;
5907
5908 }
73cd51e5
AV		 5909}
5910
aef6d006
AV		 5911static void
5912print_mve_vld_str_addr (struct disassemble_info *info,
5913 unsigned long given,
5914 enum mve_instructions matched_insn)
5915{
5916 void *stream = info->stream;
5917 fprintf_ftype func = info->fprintf_func;
5918
5919 unsigned long p, w, gpr, imm, add, mod_imm;
5920
5921 imm = arm_decode_field (given, 0, 6);
5922 mod_imm = imm;
5923
5924 switch (matched_insn)
5925 {
5926 case MVE_VLDRB_T1:
5927 case MVE_VSTRB_T1:
5928 gpr = arm_decode_field (given, 16, 18);
5929 break;
5930
5931 case MVE_VLDRH_T2:
5932 case MVE_VSTRH_T2:
5933 gpr = arm_decode_field (given, 16, 18);
5934 mod_imm = imm << 1;
5935 break;
5936
5937 case MVE_VLDRH_T6:
5938 case MVE_VSTRH_T6:
5939 gpr = arm_decode_field (given, 16, 19);
5940 mod_imm = imm << 1;
5941 break;
5942
5943 case MVE_VLDRW_T7:
5944 case MVE_VSTRW_T7:
5945 gpr = arm_decode_field (given, 16, 19);
5946 mod_imm = imm << 2;
5947 break;
5948
5949 case MVE_VLDRB_T5:
5950 case MVE_VSTRB_T5:
5951 gpr = arm_decode_field (given, 16, 19);
5952 break;
5953
5954 default:
5955 return;
5956 }
5957
5958 p = arm_decode_field (given, 24, 24);
5959 w = arm_decode_field (given, 21, 21);
5960
5961 add = arm_decode_field (given, 23, 23);
5962
5963 char * add_sub;
5964
5965 /* Don't print anything for '+' as it is implied. */
5966 if (add == 1)
5967 add_sub = "";
5968 else
5969 add_sub = "-";
5970
5971 if (p == 1)
5972 {
5973 /* Offset mode. */
5974 if (w == 0)
5975 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5976 /* Pre-indexed mode. */
5977 else
5978 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5979 }
5980 else if ((p == 0) && (w == 1))
5981 /* Post-index mode. */
5982 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5983}
5984
73cd51e5
AV		 5985/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5986 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5987 this encoding is undefined. */
5988
5989static bfd_boolean
5990is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5991 enum mve_undefined *undefined_code)
5992{
5993 *undefined_code = UNDEF_NONE;
5994
9743db03
AV		 5995 switch (matched_insn)
5996 {
5997 case MVE_VDUP:
5998 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5999 {
6000 *undefined_code = UNDEF_SIZE_3;
6001 return TRUE;
6002 }
6003 else
6004 return FALSE;
6005
14b456f2
AV		 6006 case MVE_VQADD_T1:
6007 case MVE_VQSUB_T1:
f49bb598 6008 case MVE_VMUL_VEC_T1:
66dcaa5d
AV		 6009 case MVE_VABD_VEC:
6010 case MVE_VADD_VEC_T1:
6011 case MVE_VSUB_VEC_T1:
d3b63143
AV		 6012 case MVE_VQDMULH_T1:
6013 case MVE_VQRDMULH_T2:
9743db03
AV		 6014 case MVE_VRHADD:
6015 case MVE_VHADD_T1:
6016 case MVE_VHSUB_T1:
6017 if (arm_decode_field (given, 20, 21) == 3)
6018 {
6019 *undefined_code = UNDEF_SIZE_3;
6020 return TRUE;
6021 }
6022 else
6023 return FALSE;
6024
aef6d006
AV		 6025 case MVE_VLDRB_T1:
6026 if (arm_decode_field (given, 7, 8) == 3)
6027 {
6028 *undefined_code = UNDEF_SIZE_3;
6029 return TRUE;
6030 }
6031 else
6032 return FALSE;
6033
6034 case MVE_VLDRH_T2:
6035 if (arm_decode_field (given, 7, 8) <= 1)
6036 {
6037 *undefined_code = UNDEF_SIZE_LE_1;
6038 return TRUE;
6039 }
6040 else
6041 return FALSE;
6042
6043 case MVE_VSTRB_T1:
6044 if ((arm_decode_field (given, 7, 8) == 0))
6045 {
6046 *undefined_code = UNDEF_SIZE_0;
6047 return TRUE;
6048 }
6049 else
6050 return FALSE;
6051
6052 case MVE_VSTRH_T2:
6053 if ((arm_decode_field (given, 7, 8) <= 1))
6054 {
6055 *undefined_code = UNDEF_SIZE_LE_1;
6056 return TRUE;
6057 }
6058 else
6059 return FALSE;
6060
ef1576a1
AV		 6061 case MVE_VLDRB_GATHER_T1:
6062 if (arm_decode_field (given, 7, 8) == 3)
6063 {
6064 *undefined_code = UNDEF_SIZE_3;
6065 return TRUE;
6066 }
6067 else if ((arm_decode_field (given, 28, 28) == 0)
6068 && (arm_decode_field (given, 7, 8) == 0))
6069 {
6070 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
6071 return TRUE;
6072 }
6073 else
6074 return FALSE;
6075
6076 case MVE_VLDRH_GATHER_T2:
6077 if (arm_decode_field (given, 7, 8) == 3)
6078 {
6079 *undefined_code = UNDEF_SIZE_3;
6080 return TRUE;
6081 }
6082 else if ((arm_decode_field (given, 28, 28) == 0)
6083 && (arm_decode_field (given, 7, 8) == 1))
6084 {
6085 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
6086 return TRUE;
6087 }
6088 else if (arm_decode_field (given, 7, 8) == 0)
6089 {
6090 *undefined_code = UNDEF_SIZE_0;
6091 return TRUE;
6092 }
6093 else
6094 return FALSE;
6095
6096 case MVE_VLDRW_GATHER_T3:
6097 if (arm_decode_field (given, 7, 8) != 2)
6098 {
6099 *undefined_code = UNDEF_SIZE_NOT_2;
6100 return TRUE;
6101 }
6102 else if (arm_decode_field (given, 28, 28) == 0)
6103 {
6104 *undefined_code = UNDEF_NOT_UNSIGNED;
6105 return TRUE;
6106 }
6107 else
6108 return FALSE;
6109
6110 case MVE_VLDRD_GATHER_T4:
6111 if (arm_decode_field (given, 7, 8) != 3)
6112 {
6113 *undefined_code = UNDEF_SIZE_NOT_3;
6114 return TRUE;
6115 }
6116 else if (arm_decode_field (given, 28, 28) == 0)
6117 {
6118 *undefined_code = UNDEF_NOT_UNSIGNED;
6119 return TRUE;
6120 }
6121 else
6122 return FALSE;
6123
6124 case MVE_VSTRB_SCATTER_T1:
6125 if (arm_decode_field (given, 7, 8) == 3)
6126 {
6127 *undefined_code = UNDEF_SIZE_3;
6128 return TRUE;
6129 }
6130 else
6131 return FALSE;
6132
6133 case MVE_VSTRH_SCATTER_T2:
6134 {
6135 unsigned long size = arm_decode_field (given, 7, 8);
6136 if (size == 3)
6137 {
6138 *undefined_code = UNDEF_SIZE_3;
6139 return TRUE;
6140 }
6141 else if (size == 0)
6142 {
6143 *undefined_code = UNDEF_SIZE_0;
6144 return TRUE;
6145 }
6146 else
6147 return FALSE;
6148 }
6149
6150 case MVE_VSTRW_SCATTER_T3:
6151 if (arm_decode_field (given, 7, 8) != 2)
6152 {
6153 *undefined_code = UNDEF_SIZE_NOT_2;
6154 return TRUE;
6155 }
6156 else
6157 return FALSE;
6158
6159 case MVE_VSTRD_SCATTER_T4:
6160 if (arm_decode_field (given, 7, 8) != 3)
6161 {
6162 *undefined_code = UNDEF_SIZE_NOT_3;
6163 return TRUE;
6164 }
6165 else
6166 return FALSE;
6167
bf0b396d
AV		 6168 case MVE_VCVT_FP_FIX_VEC:
6169 {
6170 unsigned long imm6 = arm_decode_field (given, 16, 21);
6171 if ((imm6 & 0x20) == 0)
6172 {
6173 *undefined_code = UNDEF_VCVT_IMM6;
6174 return TRUE;
6175 }
6176
6177 if ((arm_decode_field (given, 9, 9) == 0)
6178 && ((imm6 & 0x30) == 0x20))
6179 {
6180 *undefined_code = UNDEF_VCVT_FSI_IMM6;
6181 return TRUE;
6182 }
6183
6184 return FALSE;
6185 }
6186
f49bb598 6187 case MVE_VNEG_FP:
66dcaa5d 6188 case MVE_VABS_FP:
bf0b396d
AV		 6189 case MVE_VCVT_BETWEEN_FP_INT:
6190 case MVE_VCVT_FROM_FP_TO_INT:
6191 {
6192 unsigned long size = arm_decode_field (given, 18, 19);
6193 if (size == 0)
6194 {
6195 *undefined_code = UNDEF_SIZE_0;
6196 return TRUE;
6197 }
6198 else if (size == 3)
6199 {
6200 *undefined_code = UNDEF_SIZE_3;
6201 return TRUE;
6202 }
6203 else
6204 return FALSE;
6205 }
6206
c507f10b
AV		 6207 case MVE_VMOV_VEC_LANE_TO_GP:
6208 {
6209 unsigned long op1 = arm_decode_field (given, 21, 22);
6210 unsigned long op2 = arm_decode_field (given, 5, 6);
6211 unsigned long u = arm_decode_field (given, 23, 23);
6212
6213 if ((op2 == 0) && (u == 1))
6214 {
6215 if ((op1 == 0) || (op1 == 1))
6216 {
6217 *undefined_code = UNDEF_BAD_U_OP1_OP2;
6218 return TRUE;
6219 }
6220 else
6221 return FALSE;
6222 }
6223 else if (op2 == 2)
6224 {
6225 if ((op1 == 0) || (op1 == 1))
6226 {
6227 *undefined_code = UNDEF_BAD_OP1_OP2;
6228 return TRUE;
6229 }
6230 else
6231 return FALSE;
6232 }
6233
6234 return FALSE;
6235 }
6236
6237 case MVE_VMOV_GP_TO_VEC_LANE:
6238 if (arm_decode_field (given, 5, 6) == 2)
6239 {
6240 unsigned long op1 = arm_decode_field (given, 21, 22);
6241 if ((op1 == 0) || (op1 == 1))
6242 {
6243 *undefined_code = UNDEF_BAD_OP1_OP2;
6244 return TRUE;
6245 }
6246 else
6247 return FALSE;
6248 }
6249 else
6250 return FALSE;
6251
c4a23bf8
SP		 6252 case MVE_VMOV_VEC_TO_VEC:
6253 if ((arm_decode_field (given, 5, 5) == 1)
6254 || (arm_decode_field (given, 22, 22) == 1))
6255 return TRUE;
6256 return FALSE;
6257
c507f10b
AV		 6258 case MVE_VMOV_IMM_TO_VEC:
6259 if (arm_decode_field (given, 5, 5) == 0)
6260 {
6261 unsigned long cmode = arm_decode_field (given, 8, 11);
6262
6263 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6264 {
6265 *undefined_code = UNDEF_OP_0_BAD_CMODE;
6266 return TRUE;
6267 }
6268 else
6269 return FALSE;
6270 }
6271 else
6272 return FALSE;
6273
ed63aa17 6274 case MVE_VSHLL_T2:
14925797
AV		 6275 case MVE_VMOVN:
6276 if (arm_decode_field (given, 18, 19) == 2)
6277 {
6278 *undefined_code = UNDEF_SIZE_2;
6279 return TRUE;
6280 }
6281 else
6282 return FALSE;
6283
d3b63143
AV		 6284 case MVE_VRMLALDAVH:
6285 case MVE_VMLADAV_T1:
6286 case MVE_VMLADAV_T2:
6287 case MVE_VMLALDAV:
6288 if ((arm_decode_field (given, 28, 28) == 1)
6289 && (arm_decode_field (given, 12, 12) == 1))
6290 {
6291 *undefined_code = UNDEF_XCHG_UNS;
6292 return TRUE;
6293 }
6294 else
6295 return FALSE;
6296
ed63aa17
AV		 6297 case MVE_VQSHRN:
6298 case MVE_VQSHRUN:
6299 case MVE_VSHLL_T1:
6300 case MVE_VSHRN:
6301 {
6302 unsigned long sz = arm_decode_field (given, 19, 20);
6303 if (sz == 1)
6304 return FALSE;
6305 else if ((sz & 2) == 2)
6306 return FALSE;
6307 else
6308 {
6309 *undefined_code = UNDEF_SIZE;
6310 return TRUE;
6311 }
6312 }
6313 break;
6314
6315 case MVE_VQSHL_T2:
6316 case MVE_VQSHLU_T3:
6317 case MVE_VRSHR:
6318 case MVE_VSHL_T1:
6319 case MVE_VSHR:
6320 case MVE_VSLI:
6321 case MVE_VSRI:
6322 {
6323 unsigned long sz = arm_decode_field (given, 19, 21);
6324 if ((sz & 7) == 1)
6325 return FALSE;
6326 else if ((sz & 6) == 2)
6327 return FALSE;
6328 else if ((sz & 4) == 4)
6329 return FALSE;
6330 else
6331 {
6332 *undefined_code = UNDEF_SIZE;
6333 return TRUE;
6334 }
6335 }
6336
6337 case MVE_VQRSHRN:
6338 case MVE_VQRSHRUN:
6339 if (arm_decode_field (given, 19, 20) == 0)
6340 {
6341 *undefined_code = UNDEF_SIZE_0;
6342 return TRUE;
6343 }
6344 else
6345 return FALSE;
6346
66dcaa5d
AV		 6347 case MVE_VABS_VEC:
6348 if (arm_decode_field (given, 18, 19) == 3)
6349 {
6350 *undefined_code = UNDEF_SIZE_3;
6351 return TRUE;
6352 }
6353 else
6354 return FALSE;
6355
14b456f2
AV		 6356 case MVE_VQNEG:
6357 case MVE_VQABS:
f49bb598 6358 case MVE_VNEG_VEC:
e523f101
AV		 6359 case MVE_VCLS:
6360 case MVE_VCLZ:
6361 if (arm_decode_field (given, 18, 19) == 3)
6362 {
6363 *undefined_code = UNDEF_SIZE_3;
6364 return TRUE;
6365 }
6366 else
6367 return FALSE;
6368
14b456f2
AV		 6369 case MVE_VREV16:
6370 if (arm_decode_field (given, 18, 19) == 0)
6371 return FALSE;
6372 else
6373 {
6374 *undefined_code = UNDEF_SIZE_NOT_0;
6375 return TRUE;
6376 }
6377
6378 case MVE_VREV32:
6379 {
6380 unsigned long size = arm_decode_field (given, 18, 19);
6381 if ((size & 2) == 2)
6382 {
6383 *undefined_code = UNDEF_SIZE_2;
6384 return TRUE;
6385 }
6386 else
6387 return FALSE;
6388 }
6389
6390 case MVE_VREV64:
6391 if (arm_decode_field (given, 18, 19) != 3)
6392 return FALSE;
6393 else
6394 {
6395 *undefined_code = UNDEF_SIZE_3;
6396 return TRUE;
6397 }
6398
9743db03
AV		 6399 default:
6400 return FALSE;
6401 }
73cd51e5
AV		 6402}
6403
6404/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6405 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6406 why this encoding is unpredictable. */
6407
6408static bfd_boolean
6409is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6410 enum mve_unpredictable *unpredictable_code)
6411{
6412 *unpredictable_code = UNPRED_NONE;
6413
143275ea
AV		 6414 switch (matched_insn)
6415 {
6416 case MVE_VCMP_FP_T2:
6417 case MVE_VPT_FP_T2:
6418 if ((arm_decode_field (given, 12, 12) == 0)
6419 && (arm_decode_field (given, 5, 5) == 1))
6420 {
6421 *unpredictable_code = UNPRED_FCA_0_FCB_1;
6422 return TRUE;
6423 }
6424 else
6425 return FALSE;
73cd51e5 6426
143275ea
AV		 6427 case MVE_VPT_VEC_T4:
6428 case MVE_VPT_VEC_T5:
6429 case MVE_VPT_VEC_T6:
6430 case MVE_VCMP_VEC_T4:
6431 case MVE_VCMP_VEC_T5:
6432 case MVE_VCMP_VEC_T6:
6433 if (arm_decode_field (given, 0, 3) == 0xd)
6434 {
6435 *unpredictable_code = UNPRED_R13;
6436 return TRUE;
6437 }
6438 else
6439 return FALSE;
c1e26897 6440
9743db03
AV		 6441 case MVE_VDUP:
6442 {
6443 unsigned long gpr = arm_decode_field (given, 12, 15);
6444 if (gpr == 0xd)
6445 {
6446 *unpredictable_code = UNPRED_R13;
6447 return TRUE;
6448 }
6449 else if (gpr == 0xf)
6450 {
6451 *unpredictable_code = UNPRED_R15;
6452 return TRUE;
6453 }
6454
6455 return FALSE;
6456 }
6457
14b456f2
AV		 6458 case MVE_VQADD_T2:
6459 case MVE_VQSUB_T2:
f49bb598
AV		 6460 case MVE_VMUL_FP_T2:
6461 case MVE_VMUL_VEC_T2:
56858bea 6462 case MVE_VMLA:
e523f101 6463 case MVE_VBRSR:
66dcaa5d
AV		 6464 case MVE_VADD_FP_T2:
6465 case MVE_VSUB_FP_T2:
6466 case MVE_VADD_VEC_T2:
6467 case MVE_VSUB_VEC_T2:
ed63aa17
AV		 6468 case MVE_VQRSHL_T2:
6469 case MVE_VQSHL_T1:
6470 case MVE_VRSHL_T2:
6471 case MVE_VSHL_T2:
6472 case MVE_VSHLC:
d3b63143
AV		 6473 case MVE_VQDMLAH:
6474 case MVE_VQRDMLAH:
6475 case MVE_VQDMLASH:
6476 case MVE_VQRDMLASH:
6477 case MVE_VQDMULH_T3:
6478 case MVE_VQRDMULH_T4:
6479 case MVE_VMLAS:
9743db03
AV		 6480 case MVE_VFMA_FP_SCALAR:
6481 case MVE_VFMAS_FP_SCALAR:
6482 case MVE_VHADD_T2:
6483 case MVE_VHSUB_T2:
6484 {
6485 unsigned long gpr = arm_decode_field (given, 0, 3);
6486 if (gpr == 0xd)
6487 {
6488 *unpredictable_code = UNPRED_R13;
6489 return TRUE;
6490 }
6491 else if (gpr == 0xf)
6492 {
6493 *unpredictable_code = UNPRED_R15;
6494 return TRUE;
6495 }
6496
6497 return FALSE;
6498 }
6499
04d54ace
AV		 6500 case MVE_VLD2:
6501 case MVE_VST2:
6502 {
6503 unsigned long rn = arm_decode_field (given, 16, 19);
6504
6505 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6506 {
6507 *unpredictable_code = UNPRED_R13_AND_WB;
6508 return TRUE;
6509 }
6510
6511 if (rn == 0xf)
6512 {
6513 *unpredictable_code = UNPRED_R15;
6514 return TRUE;
6515 }
6516
6517 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6518 {
6519 *unpredictable_code = UNPRED_Q_GT_6;
6520 return TRUE;
6521 }
6522 else
6523 return FALSE;
6524 }
6525
6526 case MVE_VLD4:
6527 case MVE_VST4:
6528 {
6529 unsigned long rn = arm_decode_field (given, 16, 19);
6530
6531 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6532 {
6533 *unpredictable_code = UNPRED_R13_AND_WB;
6534 return TRUE;
6535 }
6536
6537 if (rn == 0xf)
6538 {
6539 *unpredictable_code = UNPRED_R15;
6540 return TRUE;
6541 }
6542
6543 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6544 {
6545 *unpredictable_code = UNPRED_Q_GT_4;
6546 return TRUE;
6547 }
6548 else
6549 return FALSE;
6550 }
6551
aef6d006
AV		 6552 case MVE_VLDRB_T5:
6553 case MVE_VLDRH_T6:
6554 case MVE_VLDRW_T7:
6555 case MVE_VSTRB_T5:
6556 case MVE_VSTRH_T6:
6557 case MVE_VSTRW_T7:
6558 {
6559 unsigned long rn = arm_decode_field (given, 16, 19);
6560
6561 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6562 {
6563 *unpredictable_code = UNPRED_R13_AND_WB;
6564 return TRUE;
6565 }
6566 else if (rn == 0xf)
6567 {
6568 *unpredictable_code = UNPRED_R15;
6569 return TRUE;
6570 }
6571 else
6572 return FALSE;
6573 }
6574
ef1576a1
AV		 6575 case MVE_VLDRB_GATHER_T1:
6576 if (arm_decode_field (given, 0, 0) == 1)
6577 {
6578 *unpredictable_code = UNPRED_OS;
6579 return TRUE;
6580 }
6581
6582 /* fall through. */
6583 /* To handle common code with T2-T4 variants. */
6584 case MVE_VLDRH_GATHER_T2:
6585 case MVE_VLDRW_GATHER_T3:
6586 case MVE_VLDRD_GATHER_T4:
6587 {
6588 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6589 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6590
6591 if (qd == qm)
6592 {
6593 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6594 return TRUE;
6595 }
6596
6597 if (arm_decode_field (given, 16, 19) == 0xf)
6598 {
6599 *unpredictable_code = UNPRED_R15;
6600 return TRUE;
6601 }
6602
6603 return FALSE;
6604 }
6605
6606 case MVE_VLDRW_GATHER_T5:
6607 case MVE_VLDRD_GATHER_T6:
6608 {
6609 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6610 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6611
6612 if (qd == qm)
6613 {
6614 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6615 return TRUE;
6616 }
6617 else
6618 return FALSE;
6619 }
6620
6621 case MVE_VSTRB_SCATTER_T1:
6622 if (arm_decode_field (given, 16, 19) == 0xf)
6623 {
6624 *unpredictable_code = UNPRED_R15;
6625 return TRUE;
6626 }
6627 else if (arm_decode_field (given, 0, 0) == 1)
6628 {
6629 *unpredictable_code = UNPRED_OS;
6630 return TRUE;
6631 }
6632 else
6633 return FALSE;
6634
6635 case MVE_VSTRH_SCATTER_T2:
6636 case MVE_VSTRW_SCATTER_T3:
6637 case MVE_VSTRD_SCATTER_T4:
6638 if (arm_decode_field (given, 16, 19) == 0xf)
6639 {
6640 *unpredictable_code = UNPRED_R15;
6641 return TRUE;
6642 }
6643 else
6644 return FALSE;
6645
c507f10b
AV		 6646 case MVE_VMOV2_VEC_LANE_TO_GP:
6647 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 6648 case MVE_VCVT_BETWEEN_FP_INT:
6649 case MVE_VCVT_FROM_FP_TO_INT:
6650 {
6651 unsigned long rt = arm_decode_field (given, 0, 3);
6652 unsigned long rt2 = arm_decode_field (given, 16, 19);
6653
6654 if ((rt == 0xd) || (rt2 == 0xd))
6655 {
6656 *unpredictable_code = UNPRED_R13;
6657 return TRUE;
6658 }
6659 else if ((rt == 0xf) || (rt2 == 0xf))
6660 {
6661 *unpredictable_code = UNPRED_R15;
6662 return TRUE;
6663 }
6664 else if (rt == rt2)
6665 {
6666 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6667 return TRUE;
6668 }
6669
6670 return FALSE;
6671 }
6672
56858bea
AV		 6673 case MVE_VMAXV:
6674 case MVE_VMAXAV:
6675 case MVE_VMAXNMV_FP:
6676 case MVE_VMAXNMAV_FP:
6677 case MVE_VMINNMV_FP:
6678 case MVE_VMINNMAV_FP:
6679 case MVE_VMINV:
6680 case MVE_VMINAV:
66dcaa5d 6681 case MVE_VABAV:
c507f10b
AV		 6682 case MVE_VMOV_HFP_TO_GP:
6683 case MVE_VMOV_GP_TO_VEC_LANE:
6684 case MVE_VMOV_VEC_LANE_TO_GP:
6685 {
6686 unsigned long rda = arm_decode_field (given, 12, 15);
6687 if (rda == 0xd)
6688 {
6689 *unpredictable_code = UNPRED_R13;
6690 return TRUE;
6691 }
6692 else if (rda == 0xf)
6693 {
6694 *unpredictable_code = UNPRED_R15;
6695 return TRUE;
6696 }
6697
6698 return FALSE;
6699 }
6700
14925797
AV		 6701 case MVE_VMULL_INT:
6702 {
6703 unsigned long Qd;
6704 unsigned long Qm;
6705 unsigned long Qn;
6706
6707 if (arm_decode_field (given, 20, 21) == 2)
6708 {
6709 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6710 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6711 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6712
6713 if ((Qd == Qn) || (Qd == Qm))
6714 {
6715 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6716 return TRUE;
6717 }
6718 else
6719 return FALSE;
6720 }
6721 else
6722 return FALSE;
6723 }
6724
897b9bbc 6725 case MVE_VCMUL_FP:
14925797
AV		 6726 case MVE_VQDMULL_T1:
6727 {
6728 unsigned long Qd;
6729 unsigned long Qm;
6730 unsigned long Qn;
6731
6732 if (arm_decode_field (given, 28, 28) == 1)
6733 {
6734 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6735 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6736 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6737
6738 if ((Qd == Qn) || (Qd == Qm))
6739 {
6740 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6741 return TRUE;
6742 }
6743 else
6744 return FALSE;
6745 }
6746 else
6747 return FALSE;
6748 }
6749
6750 case MVE_VQDMULL_T2:
6751 {
6752 unsigned long gpr = arm_decode_field (given, 0, 3);
6753 if (gpr == 0xd)
6754 {
6755 *unpredictable_code = UNPRED_R13;
6756 return TRUE;
6757 }
6758 else if (gpr == 0xf)
6759 {
6760 *unpredictable_code = UNPRED_R15;
6761 return TRUE;
6762 }
6763
6764 if (arm_decode_field (given, 28, 28) == 1)
6765 {
6766 unsigned long Qd
6767 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6768 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6769
a9d96ab9 6770 if (Qd == Qn)
14925797
AV		 6771 {
6772 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6773 return TRUE;
6774 }
6775 else
6776 return FALSE;
6777 }
6778
6779 return FALSE;
6780 }
6781
d3b63143
AV		 6782 case MVE_VMLSLDAV:
6783 case MVE_VRMLSLDAVH:
6784 case MVE_VMLALDAV:
6785 case MVE_VADDLV:
6786 if (arm_decode_field (given, 20, 22) == 6)
6787 {
6788 *unpredictable_code = UNPRED_R13;
6789 return TRUE;
6790 }
6791 else
6792 return FALSE;
6793
1c8f2df8
AV		 6794 case MVE_VDWDUP:
6795 case MVE_VIWDUP:
6796 if (arm_decode_field (given, 1, 3) == 6)
6797 {
6798 *unpredictable_code = UNPRED_R13;
6799 return TRUE;
6800 }
6801 else
6802 return FALSE;
6803
897b9bbc
AV		 6804 case MVE_VCADD_VEC:
6805 case MVE_VHCADD:
6806 {
6807 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6808 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6809 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6810 {
6811 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6812 return TRUE;
6813 }
6814 else
6815 return FALSE;
6816 }
6817
6818 case MVE_VCADD_FP:
6819 {
6820 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6821 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6822 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6823 {
6824 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6825 return TRUE;
6826 }
6827 else
6828 return FALSE;
6829 }
6830
6831 case MVE_VCMLA_FP:
6832 {
6833 unsigned long Qda;
6834 unsigned long Qm;
6835 unsigned long Qn;
6836
6837 if (arm_decode_field (given, 20, 20) == 1)
6838 {
6839 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6840 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6841 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6842
6843 if ((Qda == Qn) || (Qda == Qm))
6844 {
6845 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6846 return TRUE;
6847 }
6848 else
6849 return FALSE;
6850 }
6851 else
6852 return FALSE;
6853
6854 }
6855
e523f101
AV		 6856 case MVE_VCTP:
6857 if (arm_decode_field (given, 16, 19) == 0xd)
6858 {
6859 *unpredictable_code = UNPRED_R13;
6860 return TRUE;
6861 }
6862 else
6863 return FALSE;
6864
14b456f2
AV		 6865 case MVE_VREV64:
6866 {
6867 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6868 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6869
6870 if (qd == qm)
6871 {
6872 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6873 return TRUE;
6874 }
6875 else
6876 return FALSE;
6877 }
6878
23d00a41
SD		 6879 case MVE_LSLL:
6880 case MVE_LSLLI:
6881 case MVE_LSRL:
6882 case MVE_ASRL:
6883 case MVE_ASRLI:
6884 case MVE_UQSHLL:
6885 case MVE_UQRSHLL:
6886 case MVE_URSHRL:
6887 case MVE_SRSHRL:
6888 case MVE_SQSHLL:
6889 case MVE_SQRSHRL:
6890 {
6891 unsigned long gpr = arm_decode_field (given, 9, 11);
6892 gpr = ((gpr << 1) | 1);
6893 if (gpr == 0xd)
6894 {
6895 *unpredictable_code = UNPRED_R13;
6896 return TRUE;
6897 }
6898 else if (gpr == 0xf)
6899 {
6900 *unpredictable_code = UNPRED_R15;
6901 return TRUE;
6902 }
6903
6904 return FALSE;
6905 }
6906
143275ea
AV		 6907 default:
6908 return FALSE;
6909 }
6910}
c1e26897 6911
c507f10b
AV		 6912static void
6913print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6914{
6915 unsigned long op1 = arm_decode_field (given, 21, 22);
6916 unsigned long op2 = arm_decode_field (given, 5, 6);
6917 unsigned long h = arm_decode_field (given, 16, 16);
43dd7626 6918 unsigned long index_operand, esize, targetBeat, idx;
c507f10b
AV		 6919 void *stream = info->stream;
6920 fprintf_ftype func = info->fprintf_func;
6921
6922 if ((op1 & 0x2) == 0x2)
6923 {
43dd7626 6924 index_operand = op2;
c507f10b
AV		 6925 esize = 8;
6926 }
6927 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6928 {
43dd7626 6929 index_operand = op2 >> 1;
c507f10b
AV		 6930 esize = 16;
6931 }
6932 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6933 {
43dd7626 6934 index_operand = 0;
c507f10b
AV		 6935 esize = 32;
6936 }
6937 else
6938 {
6939 func (stream, "<undefined index>");
6940 return;
6941 }
6942
6943 targetBeat = (op1 & 0x1) | (h << 1);
43dd7626 6944 idx = index_operand + targetBeat * (32/esize);
c507f10b
AV		 6945
6946 func (stream, "%lu", idx);
6947}
6948
6949/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6950 in length and integer of floating-point type. */
6951static void
6952print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6953 unsigned int ibit_loc, const struct mopcode32 *insn)
6954{
6955 int bits = 0;
6956 int cmode = (given >> 8) & 0xf;
6957 int op = (given >> 5) & 0x1;
6958 unsigned long value = 0, hival = 0;
6959 unsigned shift;
6960 int size = 0;
6961 int isfloat = 0;
6962 void *stream = info->stream;
6963 fprintf_ftype func = info->fprintf_func;
6964
6965 /* On Neon the 'i' bit is at bit 24, on mve it is
6966 at bit 28. */
6967 bits |= ((given >> ibit_loc) & 1) << 7;
6968 bits |= ((given >> 16) & 7) << 4;
6969 bits |= ((given >> 0) & 15) << 0;
6970
6971 if (cmode < 8)
6972 {
6973 shift = (cmode >> 1) & 3;
6974 value = (unsigned long) bits << (8 * shift);
6975 size = 32;
6976 }
6977 else if (cmode < 12)
6978 {
6979 shift = (cmode >> 1) & 1;
6980 value = (unsigned long) bits << (8 * shift);
6981 size = 16;
6982 }
6983 else if (cmode < 14)
6984 {
6985 shift = (cmode & 1) + 1;
6986 value = (unsigned long) bits << (8 * shift);
6987 value |= (1ul << (8 * shift)) - 1;
6988 size = 32;
6989 }
6990 else if (cmode == 14)
6991 {
6992 if (op)
6993 {
6994 /* Bit replication into bytes. */
6995 int ix;
6996 unsigned long mask;
6997
6998 value = 0;
6999 hival = 0;
7000 for (ix = 7; ix >= 0; ix--)
7001 {
7002 mask = ((bits >> ix) & 1) ? 0xff : 0;
7003 if (ix <= 3)
7004 value = (value << 8) | mask;
7005 else
7006 hival = (hival << 8) | mask;
7007 }
7008 size = 64;
7009 }
7010 else
7011 {
7012 /* Byte replication. */
7013 value = (unsigned long) bits;
7014 size = 8;
7015 }
7016 }
7017 else if (!op)
7018 {
7019 /* Floating point encoding. */
7020 int tmp;
7021
7022 value = (unsigned long) (bits & 0x7f) << 19;
7023 value |= (unsigned long) (bits & 0x80) << 24;
7024 tmp = bits & 0x40 ? 0x3c : 0x40;
7025 value |= (unsigned long) tmp << 24;
7026 size = 32;
7027 isfloat = 1;
7028 }
7029 else
7030 {
7031 func (stream, "<illegal constant %.8x:%x:%x>",
7032 bits, cmode, op);
7033 size = 32;
7034 return;
7035 }
7036
279edac5
AM		 7037 /* printU determines whether the immediate value should be printed as
7038 unsigned. */
c507f10b
AV		 7039 unsigned printU = 0;
7040 switch (insn->mve_op)
7041 {
7042 default:
7043 break;
279edac5 7044 /* We want this for instructions that don't have a 'signed' type. */
c507f10b
AV		 7045 case MVE_VBIC_IMM:
7046 case MVE_VORR_IMM:
7047 case MVE_VMVN_IMM:
7048 case MVE_VMOV_IMM_TO_VEC:
7049 printU = 1;
7050 break;
7051 }
7052 switch (size)
7053 {
7054 case 8:
7055 func (stream, "#%ld\t; 0x%.2lx", value, value);
7056 break;
7057
7058 case 16:
7059 func (stream,
7060 printU
7061 ? "#%lu\t; 0x%.4lx"
7062 : "#%ld\t; 0x%.4lx", value, value);
7063 break;
7064
7065 case 32:
7066 if (isfloat)
7067 {
7068 unsigned char valbytes[4];
7069 double fvalue;
7070
7071 /* Do this a byte at a time so we don't have to
7072 worry about the host's endianness. */
7073 valbytes[0] = value & 0xff;
7074 valbytes[1] = (value >> 8) & 0xff;
7075 valbytes[2] = (value >> 16) & 0xff;
7076 valbytes[3] = (value >> 24) & 0xff;
7077
7078 floatformat_to_double
7079 (& floatformat_ieee_single_little, valbytes,
7080 & fvalue);
7081
7082 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
7083 value);
7084 }
7085 else
7086 func (stream,
7087 printU
7088 ? "#%lu\t; 0x%.8lx"
7089 : "#%ld\t; 0x%.8lx",
7090 (long) (((value & 0x80000000L) != 0)
7091 && !printU
7092 ? value | ~0xffffffffL : value),
7093 value);
7094 break;
7095
7096 case 64:
7097 func (stream, "#0x%.8lx%.8lx", hival, value);
7098 break;
7099
7100 default:
7101 abort ();
7102 }
7103
7104}
7105
73cd51e5
AV		 7106static void
7107print_mve_undefined (struct disassemble_info *info,
7108 enum mve_undefined undefined_code)
7109{
7110 void *stream = info->stream;
7111 fprintf_ftype func = info->fprintf_func;
7112
7113 func (stream, "\t\tundefined instruction: ");
7114
7115 switch (undefined_code)
7116 {
ed63aa17
AV		 7117 case UNDEF_SIZE:
7118 func (stream, "illegal size");
7119 break;
7120
aef6d006
AV		 7121 case UNDEF_SIZE_0:
7122 func (stream, "size equals zero");
7123 break;
7124
c507f10b
AV		 7125 case UNDEF_SIZE_2:
7126 func (stream, "size equals two");
7127 break;
7128
9743db03
AV		 7129 case UNDEF_SIZE_3:
7130 func (stream, "size equals three");
7131 break;
7132
aef6d006
AV		 7133 case UNDEF_SIZE_LE_1:
7134 func (stream, "size <= 1");
7135 break;
7136
14b456f2
AV		 7137 case UNDEF_SIZE_NOT_0:
7138 func (stream, "size not equal to 0");
7139 break;
7140
ef1576a1
AV		 7141 case UNDEF_SIZE_NOT_2:
7142 func (stream, "size not equal to 2");
7143 break;
7144
7145 case UNDEF_SIZE_NOT_3:
7146 func (stream, "size not equal to 3");
7147 break;
7148
7149 case UNDEF_NOT_UNS_SIZE_0:
7150 func (stream, "not unsigned and size = zero");
7151 break;
7152
7153 case UNDEF_NOT_UNS_SIZE_1:
7154 func (stream, "not unsigned and size = one");
7155 break;
7156
7157 case UNDEF_NOT_UNSIGNED:
7158 func (stream, "not unsigned");
7159 break;
7160
bf0b396d
AV		 7161 case UNDEF_VCVT_IMM6:
7162 func (stream, "invalid imm6");
7163 break;
7164
7165 case UNDEF_VCVT_FSI_IMM6:
7166 func (stream, "fsi = 0 and invalid imm6");
7167 break;
7168
c507f10b
AV		 7169 case UNDEF_BAD_OP1_OP2:
7170 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
7171 break;
7172
7173 case UNDEF_BAD_U_OP1_OP2:
7174 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
7175 break;
7176
7177 case UNDEF_OP_0_BAD_CMODE:
7178 func (stream, "op field equal 0 and bad cmode");
7179 break;
7180
d3b63143
AV		 7181 case UNDEF_XCHG_UNS:
7182 func (stream, "exchange and unsigned together");
7183 break;
7184
73cd51e5
AV		 7185 case UNDEF_NONE:
7186 break;
7187 }
7188
7189}
7190
7191static void
7192print_mve_unpredictable (struct disassemble_info *info,
7193 enum mve_unpredictable unpredict_code)
7194{
7195 void *stream = info->stream;
7196 fprintf_ftype func = info->fprintf_func;
7197
7198 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
7199
7200 switch (unpredict_code)
7201 {
7202 case UNPRED_IT_BLOCK:
7203 func (stream, "mve instruction in it block");
7204 break;
7205
143275ea
AV		 7206 case UNPRED_FCA_0_FCB_1:
7207 func (stream, "condition bits, fca = 0 and fcb = 1");
7208 break;
7209
7210 case UNPRED_R13:
7211 func (stream, "use of r13 (sp)");
7212 break;
7213
9743db03
AV		 7214 case UNPRED_R15:
7215 func (stream, "use of r15 (pc)");
7216 break;
7217
04d54ace
AV		 7218 case UNPRED_Q_GT_4:
7219 func (stream, "start register block > r4");
7220 break;
7221
7222 case UNPRED_Q_GT_6:
7223 func (stream, "start register block > r6");
7224 break;
7225
7226 case UNPRED_R13_AND_WB:
7227 func (stream, "use of r13 and write back");
7228 break;
7229
ef1576a1
AV		 7230 case UNPRED_Q_REGS_EQUAL:
7231 func (stream,
7232 "same vector register used for destination and other operand");
7233 break;
7234
7235 case UNPRED_OS:
7236 func (stream, "use of offset scaled");
7237 break;
7238
bf0b396d
AV		 7239 case UNPRED_GP_REGS_EQUAL:
7240 func (stream, "same general-purpose register used for both operands");
7241 break;
7242
c507f10b
AV		 7243 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7244 func (stream, "use of identical q registers and size = 1");
7245 break;
7246
7247 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7248 func (stream, "use of identical q registers and size = 1");
7249 break;
7250
73cd51e5
AV		 7251 case UNPRED_NONE:
7252 break;
7253 }
7254}
7255
04d54ace
AV		 7256/* Print register block operand for mve vld2/vld4/vst2/vld4. */
7257
7258static void
7259print_mve_register_blocks (struct disassemble_info *info,
7260 unsigned long given,
7261 enum mve_instructions matched_insn)
7262{
7263 void *stream = info->stream;
7264 fprintf_ftype func = info->fprintf_func;
7265
7266 unsigned long q_reg_start = arm_decode_field_multiple (given,
7267 13, 15,
7268 22, 22);
7269 switch (matched_insn)
7270 {
7271 case MVE_VLD2:
7272 case MVE_VST2:
7273 if (q_reg_start <= 6)
7274 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
7275 else
7276 func (stream, "<illegal reg q%ld>", q_reg_start);
7277 break;
7278
7279 case MVE_VLD4:
7280 case MVE_VST4:
7281 if (q_reg_start <= 4)
7282 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
7283 q_reg_start + 1, q_reg_start + 2,
7284 q_reg_start + 3);
7285 else
7286 func (stream, "<illegal reg q%ld>", q_reg_start);
7287 break;
7288
7289 default:
7290 break;
7291 }
7292}
7293
bf0b396d
AV		 7294static void
7295print_mve_rounding_mode (struct disassemble_info *info,
7296 unsigned long given,
7297 enum mve_instructions matched_insn)
7298{
7299 void *stream = info->stream;
7300 fprintf_ftype func = info->fprintf_func;
7301
7302 switch (matched_insn)
7303 {
7304 case MVE_VCVT_FROM_FP_TO_INT:
7305 {
7306 switch (arm_decode_field (given, 8, 9))
7307 {
7308 case 0:
7309 func (stream, "a");
7310 break;
7311
7312 case 1:
7313 func (stream, "n");
7314 break;
7315
7316 case 2:
7317 func (stream, "p");
7318 break;
7319
7320 case 3:
7321 func (stream, "m");
7322 break;
7323
7324 default:
7325 break;
7326 }
7327 }
7328 break;
7329
7330 case MVE_VRINT_FP:
7331 {
7332 switch (arm_decode_field (given, 7, 9))
7333 {
7334 case 0:
7335 func (stream, "n");
7336 break;
7337
7338 case 1:
7339 func (stream, "x");
7340 break;
7341
7342 case 2:
7343 func (stream, "a");
7344 break;
7345
7346 case 3:
7347 func (stream, "z");
7348 break;
7349
7350 case 5:
7351 func (stream, "m");
7352 break;
7353
7354 case 7:
7355 func (stream, "p");
7356
7357 case 4:
7358 case 6:
7359 default:
7360 break;
7361 }
7362 }
7363 break;
7364
7365 default:
7366 break;
7367 }
7368}
7369
7370static void
7371print_mve_vcvt_size (struct disassemble_info *info,
7372 unsigned long given,
7373 enum mve_instructions matched_insn)
7374{
7375 unsigned long mode = 0;
7376 void *stream = info->stream;
7377 fprintf_ftype func = info->fprintf_func;
7378
7379 switch (matched_insn)
7380 {
7381 case MVE_VCVT_FP_FIX_VEC:
7382 {
7383 mode = (((given & 0x200) >> 7)
7384 | ((given & 0x10000000) >> 27)
7385 | ((given & 0x100) >> 8));
7386
7387 switch (mode)
7388 {
7389 case 0:
7390 func (stream, "f16.s16");
7391 break;
7392
7393 case 1:
7394 func (stream, "s16.f16");
7395 break;
7396
7397 case 2:
7398 func (stream, "f16.u16");
7399 break;
7400
7401 case 3:
7402 func (stream, "u16.f16");
7403 break;
7404
7405 case 4:
7406 func (stream, "f32.s32");
7407 break;
7408
7409 case 5:
7410 func (stream, "s32.f32");
7411 break;
7412
7413 case 6:
7414 func (stream, "f32.u32");
7415 break;
7416
7417 case 7:
7418 func (stream, "u32.f32");
7419 break;
7420
7421 default:
7422 break;
7423 }
7424 break;
7425 }
7426 case MVE_VCVT_BETWEEN_FP_INT:
7427 {
7428 unsigned long size = arm_decode_field (given, 18, 19);
7429 unsigned long op = arm_decode_field (given, 7, 8);
7430
7431 if (size == 1)
7432 {
7433 switch (op)
7434 {
7435 case 0:
7436 func (stream, "f16.s16");
7437 break;
7438
7439 case 1:
7440 func (stream, "f16.u16");
7441 break;
7442
7443 case 2:
7444 func (stream, "s16.f16");
7445 break;
7446
7447 case 3:
7448 func (stream, "u16.f16");
7449 break;
7450
7451 default:
7452 break;
7453 }
7454 }
7455 else if (size == 2)
7456 {
7457 switch (op)
7458 {
7459 case 0:
7460 func (stream, "f32.s32");
7461 break;
7462
7463 case 1:
7464 func (stream, "f32.u32");
7465 break;
7466
7467 case 2:
7468 func (stream, "s32.f32");
7469 break;
7470
7471 case 3:
7472 func (stream, "u32.f32");
7473 break;
7474 }
7475 }
7476 }
7477 break;
7478
7479 case MVE_VCVT_FP_HALF_FP:
7480 {
7481 unsigned long op = arm_decode_field (given, 28, 28);
7482 if (op == 0)
7483 func (stream, "f16.f32");
7484 else if (op == 1)
7485 func (stream, "f32.f16");
7486 }
7487 break;
7488
7489 case MVE_VCVT_FROM_FP_TO_INT:
7490 {
7491 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7492
7493 switch (size)
7494 {
7495 case 2:
7496 func (stream, "s16.f16");
7497 break;
7498
7499 case 3:
7500 func (stream, "u16.f16");
7501 break;
7502
7503 case 4:
7504 func (stream, "s32.f32");
7505 break;
7506
7507 case 5:
7508 func (stream, "u32.f32");
7509 break;
7510
7511 default:
7512 break;
7513 }
7514 }
7515 break;
7516
7517 default:
7518 break;
7519 }
7520}
7521
897b9bbc
AV		 7522static void
7523print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7524 unsigned long rot_width)
7525{
7526 void *stream = info->stream;
7527 fprintf_ftype func = info->fprintf_func;
7528
7529 if (rot_width == 1)
7530 {
7531 switch (rot)
7532 {
7533 case 0:
7534 func (stream, "90");
7535 break;
7536 case 1:
7537 func (stream, "270");
7538 break;
7539 default:
7540 break;
7541 }
7542 }
7543 else if (rot_width == 2)
7544 {
7545 switch (rot)
7546 {
7547 case 0:
7548 func (stream, "0");
7549 break;
7550 case 1:
7551 func (stream, "90");
7552 break;
7553 case 2:
7554 func (stream, "180");
7555 break;
7556 case 3:
7557 func (stream, "270");
7558 break;
7559 default:
7560 break;
7561 }
7562 }
7563}
7564
143275ea
AV		 7565static void
7566print_instruction_predicate (struct disassemble_info *info)
7567{
7568 void *stream = info->stream;
7569 fprintf_ftype func = info->fprintf_func;
7570
7571 if (vpt_block_state.next_pred_state == PRED_THEN)
7572 func (stream, "t");
7573 else if (vpt_block_state.next_pred_state == PRED_ELSE)
7574 func (stream, "e");
7575}
7576
7577static void
7578print_mve_size (struct disassemble_info *info,
7579 unsigned long size,
7580 enum mve_instructions matched_insn)
7581{
7582 void *stream = info->stream;
7583 fprintf_ftype func = info->fprintf_func;
7584
7585 switch (matched_insn)
7586 {
66dcaa5d
AV		 7587 case MVE_VABAV:
7588 case MVE_VABD_VEC:
7589 case MVE_VABS_FP:
7590 case MVE_VABS_VEC:
7591 case MVE_VADD_VEC_T1:
7592 case MVE_VADD_VEC_T2:
d3b63143 7593 case MVE_VADDV:
e523f101 7594 case MVE_VBRSR:
897b9bbc 7595 case MVE_VCADD_VEC:
e523f101
AV		 7596 case MVE_VCLS:
7597 case MVE_VCLZ:
143275ea
AV		 7598 case MVE_VCMP_VEC_T1:
7599 case MVE_VCMP_VEC_T2:
7600 case MVE_VCMP_VEC_T3:
7601 case MVE_VCMP_VEC_T4:
7602 case MVE_VCMP_VEC_T5:
7603 case MVE_VCMP_VEC_T6:
e523f101 7604 case MVE_VCTP:
1c8f2df8
AV		 7605 case MVE_VDDUP:
7606 case MVE_VDWDUP:
9743db03
AV		 7607 case MVE_VHADD_T1:
7608 case MVE_VHADD_T2:
897b9bbc 7609 case MVE_VHCADD:
9743db03
AV		 7610 case MVE_VHSUB_T1:
7611 case MVE_VHSUB_T2:
1c8f2df8
AV		 7612 case MVE_VIDUP:
7613 case MVE_VIWDUP:
04d54ace
AV		 7614 case MVE_VLD2:
7615 case MVE_VLD4:
ef1576a1
AV		 7616 case MVE_VLDRB_GATHER_T1:
7617 case MVE_VLDRH_GATHER_T2:
7618 case MVE_VLDRW_GATHER_T3:
7619 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 7620 case MVE_VLDRB_T1:
7621 case MVE_VLDRH_T2:
56858bea
AV		 7622 case MVE_VMAX:
7623 case MVE_VMAXA:
7624 case MVE_VMAXV:
7625 case MVE_VMAXAV:
7626 case MVE_VMIN:
7627 case MVE_VMINA:
7628 case MVE_VMINV:
7629 case MVE_VMINAV:
7630 case MVE_VMLA:
d3b63143 7631 case MVE_VMLAS:
f49bb598
AV		 7632 case MVE_VMUL_VEC_T1:
7633 case MVE_VMUL_VEC_T2:
7634 case MVE_VMULH:
7635 case MVE_VRMULH:
7636 case MVE_VMULL_INT:
7637 case MVE_VNEG_FP:
7638 case MVE_VNEG_VEC:
143275ea
AV		 7639 case MVE_VPT_VEC_T1:
7640 case MVE_VPT_VEC_T2:
7641 case MVE_VPT_VEC_T3:
7642 case MVE_VPT_VEC_T4:
7643 case MVE_VPT_VEC_T5:
7644 case MVE_VPT_VEC_T6:
14b456f2
AV		 7645 case MVE_VQABS:
7646 case MVE_VQADD_T1:
7647 case MVE_VQADD_T2:
d3b63143
AV		 7648 case MVE_VQDMLADH:
7649 case MVE_VQRDMLADH:
7650 case MVE_VQDMLAH:
7651 case MVE_VQRDMLAH:
7652 case MVE_VQDMLASH:
7653 case MVE_VQRDMLASH:
7654 case MVE_VQDMLSDH:
7655 case MVE_VQRDMLSDH:
7656 case MVE_VQDMULH_T1:
7657 case MVE_VQRDMULH_T2:
7658 case MVE_VQDMULH_T3:
7659 case MVE_VQRDMULH_T4:
14b456f2 7660 case MVE_VQNEG:
ed63aa17
AV		 7661 case MVE_VQRSHL_T1:
7662 case MVE_VQRSHL_T2:
7663 case MVE_VQSHL_T1:
7664 case MVE_VQSHL_T4:
14b456f2
AV		 7665 case MVE_VQSUB_T1:
7666 case MVE_VQSUB_T2:
7667 case MVE_VREV32:
7668 case MVE_VREV64:
9743db03 7669 case MVE_VRHADD:
bf0b396d 7670 case MVE_VRINT_FP:
ed63aa17
AV		 7671 case MVE_VRSHL_T1:
7672 case MVE_VRSHL_T2:
7673 case MVE_VSHL_T2:
7674 case MVE_VSHL_T3:
7675 case MVE_VSHLL_T2:
04d54ace
AV		 7676 case MVE_VST2:
7677 case MVE_VST4:
ef1576a1
AV		 7678 case MVE_VSTRB_SCATTER_T1:
7679 case MVE_VSTRH_SCATTER_T2:
7680 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 7681 case MVE_VSTRB_T1:
7682 case MVE_VSTRH_T2:
66dcaa5d
AV		 7683 case MVE_VSUB_VEC_T1:
7684 case MVE_VSUB_VEC_T2:
143275ea
AV		 7685 if (size <= 3)
7686 func (stream, "%s", mve_vec_sizename[size]);
7687 else
7688 func (stream, "<undef size>");
7689 break;
7690
66dcaa5d
AV		 7691 case MVE_VABD_FP:
7692 case MVE_VADD_FP_T1:
7693 case MVE_VADD_FP_T2:
7694 case MVE_VSUB_FP_T1:
7695 case MVE_VSUB_FP_T2:
143275ea
AV		 7696 case MVE_VCMP_FP_T1:
7697 case MVE_VCMP_FP_T2:
9743db03
AV		 7698 case MVE_VFMA_FP_SCALAR:
7699 case MVE_VFMA_FP:
7700 case MVE_VFMS_FP:
7701 case MVE_VFMAS_FP_SCALAR:
56858bea
AV		 7702 case MVE_VMAXNM_FP:
7703 case MVE_VMAXNMA_FP:
7704 case MVE_VMAXNMV_FP:
7705 case MVE_VMAXNMAV_FP:
7706 case MVE_VMINNM_FP:
7707 case MVE_VMINNMA_FP:
7708 case MVE_VMINNMV_FP:
7709 case MVE_VMINNMAV_FP:
f49bb598
AV		 7710 case MVE_VMUL_FP_T1:
7711 case MVE_VMUL_FP_T2:
143275ea
AV		 7712 case MVE_VPT_FP_T1:
7713 case MVE_VPT_FP_T2:
7714 if (size == 0)
7715 func (stream, "32");
7716 else if (size == 1)
7717 func (stream, "16");
7718 break;
7719
897b9bbc
AV		 7720 case MVE_VCADD_FP:
7721 case MVE_VCMLA_FP:
7722 case MVE_VCMUL_FP:
d3b63143
AV		 7723 case MVE_VMLADAV_T1:
7724 case MVE_VMLALDAV:
7725 case MVE_VMLSDAV_T1:
7726 case MVE_VMLSLDAV:
14925797
AV		 7727 case MVE_VMOVN:
7728 case MVE_VQDMULL_T1:
7729 case MVE_VQDMULL_T2:
7730 case MVE_VQMOVN:
7731 case MVE_VQMOVUN:
7732 if (size == 0)
7733 func (stream, "16");
7734 else if (size == 1)
7735 func (stream, "32");
7736 break;
7737
7738 case MVE_VMOVL:
7739 if (size == 1)
7740 func (stream, "8");
7741 else if (size == 2)
7742 func (stream, "16");
7743 break;
7744
9743db03
AV		 7745 case MVE_VDUP:
7746 switch (size)
7747 {
7748 case 0:
7749 func (stream, "32");
7750 break;
7751 case 1:
7752 func (stream, "16");
7753 break;
7754 case 2:
7755 func (stream, "8");
7756 break;
7757 default:
7758 break;
7759 }
7760 break;
7761
c507f10b
AV		 7762 case MVE_VMOV_GP_TO_VEC_LANE:
7763 case MVE_VMOV_VEC_LANE_TO_GP:
7764 switch (size)
7765 {
7766 case 0: case 4:
7767 func (stream, "32");
7768 break;
7769
7770 case 1: case 3:
7771 case 5: case 7:
7772 func (stream, "16");
7773 break;
7774
7775 case 8: case 9: case 10: case 11:
7776 case 12: case 13: case 14: case 15:
7777 func (stream, "8");
7778 break;
7779
7780 default:
7781 break;
7782 }
7783 break;
7784
7785 case MVE_VMOV_IMM_TO_VEC:
7786 switch (size)
7787 {
7788 case 0: case 4: case 8:
7789 case 12: case 24: case 26:
7790 func (stream, "i32");
7791 break;
7792 case 16: case 20:
7793 func (stream, "i16");
7794 break;
7795 case 28:
7796 func (stream, "i8");
7797 break;
7798 case 29:
7799 func (stream, "i64");
7800 break;
7801 case 30:
7802 func (stream, "f32");
7803 break;
7804 default:
7805 break;
7806 }
7807 break;
7808
14925797
AV		 7809 case MVE_VMULL_POLY:
7810 if (size == 0)
7811 func (stream, "p8");
7812 else if (size == 1)
7813 func (stream, "p16");
7814 break;
7815
c507f10b
AV		 7816 case MVE_VMVN_IMM:
7817 switch (size)
7818 {
7819 case 0: case 2: case 4:
7820 case 6: case 12: case 13:
7821 func (stream, "32");
7822 break;
7823
7824 case 8: case 10:
7825 func (stream, "16");
7826 break;
7827
7828 default:
7829 break;
7830 }
7831 break;
7832
7833 case MVE_VBIC_IMM:
7834 case MVE_VORR_IMM:
7835 switch (size)
7836 {
7837 case 1: case 3:
7838 case 5: case 7:
7839 func (stream, "32");
7840 break;
7841
7842 case 9: case 11:
7843 func (stream, "16");
7844 break;
7845
7846 default:
7847 break;
7848 }
7849 break;
7850
ed63aa17
AV		 7851 case MVE_VQSHRN:
7852 case MVE_VQSHRUN:
7853 case MVE_VQRSHRN:
7854 case MVE_VQRSHRUN:
7855 case MVE_VRSHRN:
7856 case MVE_VSHRN:
7857 {
7858 switch (size)
7859 {
7860 case 1:
7861 func (stream, "16");
7862 break;
7863
7864 case 2: case 3:
7865 func (stream, "32");
7866 break;
7867
7868 default:
7869 break;
7870 }
7871 }
7872 break;
7873
7874 case MVE_VQSHL_T2:
7875 case MVE_VQSHLU_T3:
7876 case MVE_VRSHR:
7877 case MVE_VSHL_T1:
7878 case MVE_VSHLL_T1:
7879 case MVE_VSHR:
7880 case MVE_VSLI:
7881 case MVE_VSRI:
7882 {
7883 switch (size)
7884 {
7885 case 1:
7886 func (stream, "8");
7887 break;
7888
7889 case 2: case 3:
7890 func (stream, "16");
7891 break;
7892
7893 case 4: case 5: case 6: case 7:
7894 func (stream, "32");
7895 break;
7896
7897 default:
7898 break;
7899 }
7900 }
7901 break;
7902
143275ea
AV		 7903 default:
7904 break;
7905 }
7906}
7907
ed63aa17
AV		 7908static void
7909print_mve_shift_n (struct disassemble_info *info, long given,
7910 enum mve_instructions matched_insn)
7911{
7912 void *stream = info->stream;
7913 fprintf_ftype func = info->fprintf_func;
7914
7915 int startAt0
7916 = matched_insn == MVE_VQSHL_T2
7917 || matched_insn == MVE_VQSHLU_T3
7918 || matched_insn == MVE_VSHL_T1
7919 || matched_insn == MVE_VSHLL_T1
7920 || matched_insn == MVE_VSLI;
7921
7922 unsigned imm6 = (given & 0x3f0000) >> 16;
7923
7924 if (matched_insn == MVE_VSHLL_T1)
7925 imm6 &= 0x1f;
7926
7927 unsigned shiftAmount = 0;
7928 if ((imm6 & 0x20) != 0)
7929 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7930 else if ((imm6 & 0x10) != 0)
7931 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7932 else if ((imm6 & 0x08) != 0)
7933 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7934 else
7935 print_mve_undefined (info, UNDEF_SIZE_0);
7936
7937 func (stream, "%u", shiftAmount);
7938}
7939
143275ea
AV		 7940static void
7941print_vec_condition (struct disassemble_info *info, long given,
7942 enum mve_instructions matched_insn)
7943{
7944 void *stream = info->stream;
7945 fprintf_ftype func = info->fprintf_func;
7946 long vec_cond = 0;
7947
7948 switch (matched_insn)
7949 {
7950 case MVE_VPT_FP_T1:
7951 case MVE_VCMP_FP_T1:
7952 vec_cond = (((given & 0x1000) >> 10)
7953 | ((given & 1) << 1)
7954 | ((given & 0x0080) >> 7));
7955 func (stream, "%s",vec_condnames[vec_cond]);
7956 break;
7957
7958 case MVE_VPT_FP_T2:
7959 case MVE_VCMP_FP_T2:
7960 vec_cond = (((given & 0x1000) >> 10)
7961 | ((given & 0x0020) >> 4)
7962 | ((given & 0x0080) >> 7));
7963 func (stream, "%s",vec_condnames[vec_cond]);
7964 break;
7965
7966 case MVE_VPT_VEC_T1:
7967 case MVE_VCMP_VEC_T1:
7968 vec_cond = (given & 0x0080) >> 7;
7969 func (stream, "%s",vec_condnames[vec_cond]);
7970 break;
7971
7972 case MVE_VPT_VEC_T2:
7973 case MVE_VCMP_VEC_T2:
7974 vec_cond = 2 | ((given & 0x0080) >> 7);
7975 func (stream, "%s",vec_condnames[vec_cond]);
7976 break;
7977
7978 case MVE_VPT_VEC_T3:
7979 case MVE_VCMP_VEC_T3:
7980 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7981 func (stream, "%s",vec_condnames[vec_cond]);
7982 break;
7983
7984 case MVE_VPT_VEC_T4:
7985 case MVE_VCMP_VEC_T4:
7986 vec_cond = (given & 0x0080) >> 7;
7987 func (stream, "%s",vec_condnames[vec_cond]);
7988 break;
7989
7990 case MVE_VPT_VEC_T5:
7991 case MVE_VCMP_VEC_T5:
7992 vec_cond = 2 | ((given & 0x0080) >> 7);
7993 func (stream, "%s",vec_condnames[vec_cond]);
7994 break;
7995
7996 case MVE_VPT_VEC_T6:
7997 case MVE_VCMP_VEC_T6:
7998 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7999 func (stream, "%s",vec_condnames[vec_cond]);
8000 break;
8001
8002 case MVE_NONE:
8003 case MVE_VPST:
8004 default:
8005 break;
8006 }
8007}
8008
8009#define W_BIT 21
8010#define I_BIT 22
8011#define U_BIT 23
8012#define P_BIT 24
8013
8014#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
8015#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
8016#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
8017#define PRE_BIT_SET (given & (1 << P_BIT))
8018
8019
8f06b2d8
PB		 8020/* Print one coprocessor instruction on INFO->STREAM.
8021 Return TRUE if the instuction matched, FALSE if this is not a
8022 recognised coprocessor instruction. */
8023
8024static bfd_boolean
33593eaf
MM		 8025print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
8026 bfd_vma pc,
8027 struct disassemble_info *info,
8028 long given,
8029 bfd_boolean thumb)
8f06b2d8 8030{
6b0dd094 8031 const struct sopcode32 *insn;
8f06b2d8
PB		 8032 void *stream = info->stream;
8033 fprintf_ftype func = info->fprintf_func;
8034 unsigned long mask;
2edcd244 8035 unsigned long value = 0;
c22aaad1 8036 int cond;
8afc7bea 8037 int cp_num;
823d2571
TG		 8038 struct arm_private_data *private_data = info->private_data;
8039 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 8040 arm_feature_set arm_ext_v8_1m_main =
8041 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 8042
5b616bef 8043 allowed_arches = private_data->features;
8f06b2d8 8044
33593eaf 8045 for (insn = opcodes; insn->assembler; insn++)
8f06b2d8 8046 {
ff4a8d2b
NC		 8047 unsigned long u_reg = 16;
8048 bfd_boolean is_unpredictable = FALSE;
05413229 8049 signed long value_in_comment = 0;
0313a2b8
NC		 8050 const char *c;
8051
823d2571 8052 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 8053 switch (insn->value)
8054 {
8055 case SENTINEL_IWMMXT_START:
8056 if (info->mach != bfd_mach_arm_XScale
8057 && info->mach != bfd_mach_arm_iWMMXt
8058 && info->mach != bfd_mach_arm_iWMMXt2)
8059 do
8060 insn++;
823d2571
TG		 8061 while ((! ARM_FEATURE_ZERO (insn->arch))
8062 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 8063 continue;
8064
8065 case SENTINEL_IWMMXT_END:
8066 continue;
8067
8068 case SENTINEL_GENERIC_START:
5b616bef 8069 allowed_arches = private_data->features;
05413229
NC		 8070 continue;
8071
8072 default:
8073 abort ();
8074 }
8f06b2d8
PB		 8075
8076 mask = insn->mask;
8077 value = insn->value;
8afc7bea
RL		 8078 cp_num = (given >> 8) & 0xf;
8079
8f06b2d8
PB		 8080 if (thumb)
8081 {
8082 /* The high 4 bits are 0xe for Arm conditional instructions, and
8083 0xe for arm unconditional instructions. The rest of the
8084 encoding is the same. */
8085 mask |= 0xf0000000;
8086 value |= 0xe0000000;
c22aaad1
PB		 8087 if (ifthen_state)
8088 cond = IFTHEN_COND;
8089 else
e2efe87d 8090 cond = COND_UNCOND;
8f06b2d8
PB		 8091 }
8092 else
8093 {
8094 /* Only match unconditional instuctions against unconditional
8095 patterns. */
8096 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 8097 {
8098 mask |= 0xf0000000;
e2efe87d 8099 cond = COND_UNCOND;
c22aaad1
PB		 8100 }
8101 else
8102 {
8103 cond = (given >> 28) & 0xf;
8104 if (cond == 0xe)
e2efe87d 8105 cond = COND_UNCOND;
c22aaad1 8106 }
8f06b2d8 8107 }
823d2571 8108
6b0dd094
AV		 8109 if ((insn->isa == T32 && !thumb)
8110 || (insn->isa == ARM && thumb))
8111 continue;
8112
0313a2b8
NC		 8113 if ((given & mask) != value)
8114 continue;
8f06b2d8 8115
823d2571 8116 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 8117 continue;
8118
8afc7bea
RL		 8119 if (insn->value == 0xfe000010 /* mcr2 */
8120 || insn->value == 0xfe100010 /* mrc2 */
8121 || insn->value == 0xfc100000 /* ldc2 */
8122 || insn->value == 0xfc000000) /* stc2 */
8123 {
b0c11777 8124 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 8125 is_unpredictable = TRUE;
f08d8ce3
AV		 8126
8127 /* Armv8.1-M Mainline FP & MVE instructions. */
8128 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8129 && !ARM_CPU_IS_ANY (allowed_arches)
8130 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8131 continue;
8132
8afc7bea
RL		 8133 }
8134 else if (insn->value == 0x0e000000 /* cdp */
8135 || insn->value == 0xfe000000 /* cdp2 */
8136 || insn->value == 0x0e000010 /* mcr */
8137 || insn->value == 0x0e100010 /* mrc */
8138 || insn->value == 0x0c100000 /* ldc */
8139 || insn->value == 0x0c000000) /* stc */
8140 {
8141 /* Floating-point instructions. */
b0c11777 8142 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 8143 continue;
32c36c3c
AV		 8144
8145 /* Armv8.1-M Mainline FP & MVE instructions. */
8146 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8147 && !ARM_CPU_IS_ANY (allowed_arches)
8148 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8149 continue;
8afc7bea 8150 }
aef6d006
AV		 8151 else if ((insn->value == 0xec100f80 /* vldr (system register) */
8152 || insn->value == 0xec000f80) /* vstr (system register) */
8153 && arm_decode_field (given, 24, 24) == 0
8154 && arm_decode_field (given, 21, 21) == 0)
8155 /* If the P and W bits are both 0 then these encodings match the MVE
8156 VLDR and VSTR instructions, these are in a different table, so we
8157 don't let it match here. */
8158 continue;
8159
0313a2b8
NC		 8160 for (c = insn->assembler; *c; c++)
8161 {
8162 if (*c == '%')
8f06b2d8 8163 {
32c36c3c
AV		 8164 const char mod = *++c;
8165 switch (mod)
8f06b2d8 8166 {
0313a2b8
NC		 8167 case '%':
8168 func (stream, "%%");
8169 break;
8170
8171 case 'A':
32c36c3c 8172 case 'K':
05413229 8173 {
79862e45 8174 int rn = (given >> 16) & 0xf;
b0c11777 8175 bfd_vma offset = given & 0xff;
0313a2b8 8176
32c36c3c
AV		 8177 if (mod == 'K')
8178 offset = given & 0x7f;
8179
05413229 8180 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 8181
79862e45
DJ		 8182 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8183 {
8184 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 8185 if (cp_num == 9)
8186 /* vldr.16/vstr.16 will shift the address
8187 left by 1 bit only. */
8188 offset = offset * 2;
8189 else
8190 offset = offset * 4;
8191
79862e45
DJ		 8192 if (NEGATIVE_BIT_SET)
8193 offset = - offset;
8194 if (rn != 15)
8195 value_in_comment = offset;
8196 }
8197
c1e26897 8198 if (PRE_BIT_SET)
05413229
NC		 8199 {
8200 if (offset)
fe56b6ce 8201 func (stream, ", #%d]%s",
d908c8af 8202 (int) offset,
c1e26897 8203 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 8204 else if (NEGATIVE_BIT_SET)
8205 func (stream, ", #-0]");
05413229
NC		 8206 else
8207 func (stream, "]");
8208 }
8209 else
8210 {
0313a2b8 8211 func (stream, "]");
8f06b2d8 8212
c1e26897 8213 if (WRITEBACK_BIT_SET)
05413229
NC		 8214 {
8215 if (offset)
d908c8af 8216 func (stream, ", #%d", (int) offset);
26d97720
NS		 8217 else if (NEGATIVE_BIT_SET)
8218 func (stream, ", #-0");
05413229
NC		 8219 }
8220 else
fe56b6ce 8221 {
26d97720
NS		 8222 func (stream, ", {%s%d}",
8223 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 8224 (int) offset);
fe56b6ce
NC		 8225 value_in_comment = offset;
8226 }
05413229 8227 }
79862e45
DJ		 8228 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8229 {
8230 func (stream, "\t; ");
6844b2c2
MGD		 8231 /* For unaligned PCs, apply off-by-alignment
8232 correction. */
43e65147 8233 info->print_address_func (offset + pc
6844b2c2
MGD		 8234 + info->bytes_per_chunk * 2
8235 - (pc & 3),
dffaa15c 8236 info);
79862e45 8237 }
05413229 8238 }
0313a2b8 8239 break;
8f06b2d8 8240
0313a2b8
NC		 8241 case 'B':
8242 {
8243 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8244 int offset = (given >> 1) & 0x3f;
8245
8246 if (offset == 1)
8247 func (stream, "{d%d}", regno);
8248 else if (regno + offset > 32)
8249 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
8250 else
8251 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
8252 }
8253 break;
8f06b2d8 8254
efd6b359
AV		 8255 case 'C':
8256 {
8257 bfd_boolean single = ((given >> 8) & 1) == 0;
8258 char reg_prefix = single ? 's' : 'd';
8259 int Dreg = (given >> 22) & 0x1;
8260 int Vdreg = (given >> 12) & 0xf;
8261 int reg = single ? ((Vdreg << 1) | Dreg)
8262 : ((Dreg << 4) | Vdreg);
8263 int num = (given >> (single ? 0 : 1)) & 0x7f;
8264 int maxreg = single ? 31 : 15;
8265 int topreg = reg + num - 1;
8266
8267 if (!num)
8268 func (stream, "{VPR}");
8269 else if (num == 1)
8270 func (stream, "{%c%d, VPR}", reg_prefix, reg);
8271 else if (topreg > maxreg)
8272 func (stream, "{%c%d-<overflow reg d%d, VPR}",
8273 reg_prefix, reg, single ? topreg >> 1 : topreg);
8274 else
8275 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
8276 reg_prefix, topreg);
8277 }
8278 break;
8279
e2efe87d
MGD		 8280 case 'u':
8281 if (cond != COND_UNCOND)
8282 is_unpredictable = TRUE;
8283
8284 /* Fall through. */
0313a2b8 8285 case 'c':
b0c11777
RL		 8286 if (cond != COND_UNCOND && cp_num == 9)
8287 is_unpredictable = TRUE;
8288
aab2c27d
MM		 8289 /* Fall through. */
8290 case 'b':
0313a2b8
NC		 8291 func (stream, "%s", arm_conditional[cond]);
8292 break;
8f06b2d8 8293
0313a2b8
NC		 8294 case 'I':
8295 /* Print a Cirrus/DSP shift immediate. */
8296 /* Immediates are 7bit signed ints with bits 0..3 in
8297 bits 0..3 of opcode and bits 4..6 in bits 5..7
8298 of opcode. */
8299 {
8300 int imm;
8f06b2d8 8301
0313a2b8 8302 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 8303
0313a2b8
NC		 8304 /* Is ``imm'' a negative number? */
8305 if (imm & 0x40)
24b4cf66 8306 imm -= 0x80;
8f06b2d8 8307
0313a2b8
NC		 8308 func (stream, "%d", imm);
8309 }
8310
8311 break;
8f06b2d8 8312
32c36c3c
AV		 8313 case 'J':
8314 {
73cd51e5
AV		 8315 unsigned long regno
8316 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 8317
8318 switch (regno)
8319 {
8320 case 0x1:
8321 func (stream, "FPSCR");
8322 break;
8323 case 0x2:
8324 func (stream, "FPSCR_nzcvqc");
8325 break;
8326 case 0xc:
8327 func (stream, "VPR");
8328 break;
8329 case 0xd:
8330 func (stream, "P0");
8331 break;
8332 case 0xe:
8333 func (stream, "FPCXTNS");
8334 break;
8335 case 0xf:
8336 func (stream, "FPCXTS");
8337 break;
8338 default:
73cd51e5 8339 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 8340 break;
8341 }
8342 }
8343 break;
8344
0313a2b8
NC		 8345 case 'F':
8346 switch (given & 0x00408000)
8347 {
8348 case 0:
8349 func (stream, "4");
8350 break;
8351 case 0x8000:
8352 func (stream, "1");
8353 break;
8354 case 0x00400000:
8355 func (stream, "2");
8f06b2d8 8356 break;
0313a2b8
NC		 8357 default:
8358 func (stream, "3");
8359 }
8360 break;
8f06b2d8 8361
0313a2b8
NC		 8362 case 'P':
8363 switch (given & 0x00080080)
8364 {
8365 case 0:
8366 func (stream, "s");
8367 break;
8368 case 0x80:
8369 func (stream, "d");
8370 break;
8371 case 0x00080000:
8372 func (stream, "e");
8373 break;
8374 default:
8375 func (stream, _("<illegal precision>"));
8f06b2d8 8376 break;
0313a2b8
NC		 8377 }
8378 break;
8f06b2d8 8379
0313a2b8
NC		 8380 case 'Q':
8381 switch (given & 0x00408000)
8382 {
8383 case 0:
8384 func (stream, "s");
8f06b2d8 8385 break;
0313a2b8
NC		 8386 case 0x8000:
8387 func (stream, "d");
8f06b2d8 8388 break;
0313a2b8
NC		 8389 case 0x00400000:
8390 func (stream, "e");
8391 break;
8392 default:
8393 func (stream, "p");
8f06b2d8 8394 break;
0313a2b8
NC		 8395 }
8396 break;
8f06b2d8 8397
0313a2b8
NC		 8398 case 'R':
8399 switch (given & 0x60)
8400 {
8401 case 0:
8402 break;
8403 case 0x20:
8404 func (stream, "p");
8405 break;
8406 case 0x40:
8407 func (stream, "m");
8408 break;
8409 default:
8410 func (stream, "z");
8411 break;
8412 }
8413 break;
16980d0b 8414
0313a2b8
NC		 8415 case '0': case '1': case '2': case '3': case '4':
8416 case '5': case '6': case '7': case '8': case '9':
8417 {
8418 int width;
8f06b2d8 8419
0313a2b8 8420 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 8421
0313a2b8
NC		 8422 switch (*c)
8423 {
ff4a8d2b
NC		 8424 case 'R':
8425 if (value == 15)
8426 is_unpredictable = TRUE;
8427 /* Fall through. */
0313a2b8 8428 case 'r':
ff4a8d2b
NC		 8429 if (c[1] == 'u')
8430 {
8431 /* Eat the 'u' character. */
8432 ++ c;
8433
8434 if (u_reg == value)
8435 is_unpredictable = TRUE;
8436 u_reg = value;
8437 }
0313a2b8
NC		 8438 func (stream, "%s", arm_regnames[value]);
8439 break;
c28eeff2
SN		 8440 case 'V':
8441 if (given & (1 << 6))
8442 goto Q;
8443 /* FALLTHROUGH */
0313a2b8
NC		 8444 case 'D':
8445 func (stream, "d%ld", value);
8446 break;
8447 case 'Q':
c28eeff2 8448 Q:
0313a2b8
NC		 8449 if (value & 1)
8450 func (stream, "<illegal reg q%ld.5>", value >> 1);
8451 else
8452 func (stream, "q%ld", value >> 1);
8453 break;
8454 case 'd':
8455 func (stream, "%ld", value);
05413229 8456 value_in_comment = value;
0313a2b8 8457 break;
6f1c2142
AM		 8458 case 'E':
8459 {
8460 /* Converts immediate 8 bit back to float value. */
8461 unsigned floatVal = (value & 0x80) << 24
8462 | (value & 0x3F) << 19
8463 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8464
8465 /* Quarter float have a maximum value of 31.0.
8466 Get floating point value multiplied by 1e7.
8467 The maximum value stays in limit of a 32-bit int. */
8468 unsigned decVal =
8469 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8470 (16 + (value & 0xF));
8471
8472 if (!(decVal % 1000000))
8473 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
8474 floatVal, value & 0x80 ? '-' : ' ',
8475 decVal / 10000000,
8476 decVal % 10000000 / 1000000);
8477 else if (!(decVal % 10000))
8478 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
8479 floatVal, value & 0x80 ? '-' : ' ',
8480 decVal / 10000000,
8481 decVal % 10000000 / 10000);
8482 else
8483 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
8484 floatVal, value & 0x80 ? '-' : ' ',
8485 decVal / 10000000, decVal % 10000000);
8486 break;
8487 }
0313a2b8
NC		 8488 case 'k':
8489 {
8490 int from = (given & (1 << 7)) ? 32 : 16;
8491 func (stream, "%ld", from - value);
8492 }
8493 break;
8f06b2d8 8494
0313a2b8
NC		 8495 case 'f':
8496 if (value > 7)
8497 func (stream, "#%s", arm_fp_const[value & 7]);
8498 else
8499 func (stream, "f%ld", value);
8500 break;
4146fd53 8501
0313a2b8
NC		 8502 case 'w':
8503 if (width == 2)
8504 func (stream, "%s", iwmmxt_wwnames[value]);
8505 else
8506 func (stream, "%s", iwmmxt_wwssnames[value]);
8507 break;
4146fd53 8508
0313a2b8
NC		 8509 case 'g':
8510 func (stream, "%s", iwmmxt_regnames[value]);
8511 break;
8512 case 'G':
8513 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 8514 break;
8f06b2d8 8515
0313a2b8 8516 case 'x':
d1aaab3c 8517 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 8518 break;
8f06b2d8 8519
33399f07
MGD		 8520 case 'c':
8521 switch (value)
8522 {
8523 case 0:
8524 func (stream, "eq");
8525 break;
8526
8527 case 1:
8528 func (stream, "vs");
8529 break;
8530
8531 case 2:
8532 func (stream, "ge");
8533 break;
8534
8535 case 3:
8536 func (stream, "gt");
8537 break;
8538
8539 default:
8540 func (stream, "??");
8541 break;
8542 }
8543 break;
8544
0313a2b8
NC		 8545 case '`':
8546 c++;
8547 if (value == 0)
8548 func (stream, "%c", *c);
8549 break;
8550 case '\'':
8551 c++;
8552 if (value == ((1ul << width) - 1))
8553 func (stream, "%c", *c);
8554 break;
8555 case '?':
fe56b6ce 8556 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 8557 c += 1 << width;
8558 break;
8559 default:
8560 abort ();
8561 }
dffaa15c
AM		 8562 }
8563 break;
0313a2b8 8564
dffaa15c
AM		 8565 case 'y':
8566 case 'z':
8567 {
8568 int single = *c++ == 'y';
8569 int regno;
8f06b2d8 8570
dffaa15c
AM		 8571 switch (*c)
8572 {
8573 case '4': /* Sm pair */
8574 case '0': /* Sm, Dm */
8575 regno = given & 0x0000000f;
8576 if (single)
8577 {
8578 regno <<= 1;
8579 regno += (given >> 5) & 1;
8580 }
8581 else
8582 regno += ((given >> 5) & 1) << 4;
8583 break;
8f06b2d8 8584
dffaa15c
AM		 8585 case '1': /* Sd, Dd */
8586 regno = (given >> 12) & 0x0000000f;
8587 if (single)
8588 {
8589 regno <<= 1;
8590 regno += (given >> 22) & 1;
8591 }
8592 else
8593 regno += ((given >> 22) & 1) << 4;
8594 break;
7df76b80 8595
dffaa15c
AM		 8596 case '2': /* Sn, Dn */
8597 regno = (given >> 16) & 0x0000000f;
8598 if (single)
8599 {
8600 regno <<= 1;
8601 regno += (given >> 7) & 1;
8602 }
8603 else
8604 regno += ((given >> 7) & 1) << 4;
8605 break;
a7f8487e 8606
dffaa15c
AM		 8607 case '3': /* List */
8608 func (stream, "{");
8609 regno = (given >> 12) & 0x0000000f;
8610 if (single)
8611 {
8612 regno <<= 1;
8613 regno += (given >> 22) & 1;
8614 }
8615 else
8616 regno += ((given >> 22) & 1) << 4;
8617 break;
a7f8487e 8618
dffaa15c
AM		 8619 default:
8620 abort ();
8621 }
0313a2b8 8622
dffaa15c 8623 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 8624
dffaa15c
AM		 8625 if (*c == '3')
8626 {
8627 int count = given & 0xff;
b34976b6 8628
dffaa15c
AM		 8629 if (single == 0)
8630 count >>= 1;
0313a2b8 8631
dffaa15c
AM		 8632 if (--count)
8633 {
8634 func (stream, "-%c%d",
8635 single ? 's' : 'd',
8636 regno + count);
8637 }
0313a2b8 8638
dffaa15c 8639 func (stream, "}");
0313a2b8 8640 }
dffaa15c
AM		 8641 else if (*c == '4')
8642 func (stream, ", %c%d", single ? 's' : 'd',
8643 regno + 1);
8644 }
8645 break;
b34976b6 8646
dffaa15c
AM		 8647 case 'L':
8648 switch (given & 0x00400100)
0313a2b8 8649 {
dffaa15c
AM		 8650 case 0x00000000: func (stream, "b"); break;
8651 case 0x00400000: func (stream, "h"); break;
8652 case 0x00000100: func (stream, "w"); break;
8653 case 0x00400100: func (stream, "d"); break;
8654 default:
8655 break;
0313a2b8 8656 }
dffaa15c 8657 break;
2d447fca 8658
dffaa15c
AM		 8659 case 'Z':
8660 {
8661 /* given (20, 23) | given (0, 3) */
8662 value = ((given >> 16) & 0xf0) | (given & 0xf);
8663 func (stream, "%d", (int) value);
8664 }
8665 break;
0313a2b8 8666
dffaa15c
AM		 8667 case 'l':
8668 /* This is like the 'A' operator, except that if
8669 the width field "M" is zero, then the offset is
8670 *not* multiplied by four. */
8671 {
8672 int offset = given & 0xff;
8673 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 8674
dffaa15c 8675 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 8676
dffaa15c
AM		 8677 if (multiplier > 1)
8678 {
8679 value_in_comment = offset * multiplier;
8680 if (NEGATIVE_BIT_SET)
8681 value_in_comment = - value_in_comment;
8682 }
0313a2b8 8683
dffaa15c
AM		 8684 if (offset)
8685 {
8686 if (PRE_BIT_SET)
8687 func (stream, ", #%s%d]%s",
8688 NEGATIVE_BIT_SET ? "-" : "",
8689 offset * multiplier,
8690 WRITEBACK_BIT_SET ? "!" : "");
8691 else
8692 func (stream, "], #%s%d",
8693 NEGATIVE_BIT_SET ? "-" : "",
8694 offset * multiplier);
8695 }
8696 else
8697 func (stream, "]");
8698 }
8699 break;
2d447fca 8700
dffaa15c
AM		 8701 case 'r':
8702 {
8703 int imm4 = (given >> 4) & 0xf;
8704 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8705 int ubit = ! NEGATIVE_BIT_SET;
8706 const char *rm = arm_regnames [given & 0xf];
8707 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 8708
dffaa15c
AM		 8709 switch (puw_bits)
8710 {
8711 case 1:
8712 case 3:
8713 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8714 if (imm4)
8715 func (stream, ", lsl #%d", imm4);
8716 break;
0313a2b8 8717
dffaa15c
AM		 8718 case 4:
8719 case 5:
8720 case 6:
8721 case 7:
8722 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8723 if (imm4 > 0)
8724 func (stream, ", lsl #%d", imm4);
8725 func (stream, "]");
8726 if (puw_bits == 5 || puw_bits == 7)
8727 func (stream, "!");
8728 break;
2d447fca 8729
dffaa15c
AM		 8730 default:
8731 func (stream, "INVALID");
8732 }
8733 }
8734 break;
0313a2b8 8735
dffaa15c
AM		 8736 case 'i':
8737 {
8738 long imm5;
8739 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8740 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 8741 }
dffaa15c
AM		 8742 break;
8743
8744 default:
8745 abort ();
252b5132 8746 }
252b5132 8747 }
0313a2b8
NC		 8748 else
8749 func (stream, "%c", *c);
252b5132 8750 }
05413229
NC		 8751
8752 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 8753 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 8754
ff4a8d2b
NC		 8755 if (is_unpredictable)
8756 func (stream, UNPREDICTABLE_INSTRUCTION);
8757
0313a2b8 8758 return TRUE;
252b5132 8759 }
8f06b2d8 8760 return FALSE;
252b5132
RH		 8761}
8762
33593eaf
MM		 8763static bfd_boolean
8764print_insn_coprocessor (bfd_vma pc,
8765 struct disassemble_info *info,
8766 long given,
8767 bfd_boolean thumb)
8768{
8769 return print_insn_coprocessor_1 (coprocessor_opcodes,
8770 pc, info, given, thumb);
8771}
8772
8773static bfd_boolean
8774print_insn_generic_coprocessor (bfd_vma pc,
8775 struct disassemble_info *info,
8776 long given,
8777 bfd_boolean thumb)
8778{
8779 return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
8780 pc, info, given, thumb);
8781}
8782
05413229
NC		 8783/* Decodes and prints ARM addressing modes. Returns the offset
8784 used in the address, if any, if it is worthwhile printing the
8785 offset as a hexadecimal value in a comment at the end of the
8786 line of disassembly. */
8787
8788static signed long
62b3e311
PB		 8789print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8790{
8791 void *stream = info->stream;
8792 fprintf_ftype func = info->fprintf_func;
f8b960bc 8793 bfd_vma offset = 0;
62b3e311
PB		 8794
8795 if (((given & 0x000f0000) == 0x000f0000)
8796 && ((given & 0x02000000) == 0))
8797 {
05413229 8798 offset = given & 0xfff;
62b3e311
PB		 8799
8800 func (stream, "[pc");
8801
c1e26897 8802 if (PRE_BIT_SET)
62b3e311 8803 {
26d97720
NS		 8804 /* Pre-indexed. Elide offset of positive zero when
8805 non-writeback. */
8806 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8807 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 8808
8809 if (NEGATIVE_BIT_SET)
8810 offset = -offset;
62b3e311
PB		 8811
8812 offset += pc + 8;
8813
8814 /* Cope with the possibility of write-back
8815 being used. Probably a very dangerous thing
8816 for the programmer to do, but who are we to
8817 argue ? */
26d97720 8818 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 8819 }
c1e26897 8820 else /* Post indexed. */
62b3e311 8821 {
d908c8af 8822 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 8823
c1e26897 8824 /* Ie ignore the offset. */
62b3e311
PB		 8825 offset = pc + 8;
8826 }
8827
8828 func (stream, "\t; ");
8829 info->print_address_func (offset, info);
05413229 8830 offset = 0;
62b3e311
PB		 8831 }
8832 else
8833 {
8834 func (stream, "[%s",
8835 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 8836
8837 if (PRE_BIT_SET)
62b3e311
PB		 8838 {
8839 if ((given & 0x02000000) == 0)
8840 {
26d97720 8841 /* Elide offset of positive zero when non-writeback. */
05413229 8842 offset = given & 0xfff;
26d97720 8843 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8844 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8845 }
8846 else
8847 {
26d97720 8848 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8849 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8850 }
8851
8852 func (stream, "]%s",
c1e26897 8853 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 8854 }
8855 else
8856 {
8857 if ((given & 0x02000000) == 0)
8858 {
26d97720 8859 /* Always show offset. */
05413229 8860 offset = given & 0xfff;
26d97720 8861 func (stream, "], #%s%d",
d908c8af 8862 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8863 }
8864 else
8865 {
8866 func (stream, "], %s",
c1e26897 8867 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8868 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8869 }
8870 }
84919466
MR		 8871 if (NEGATIVE_BIT_SET)
8872 offset = -offset;
62b3e311 8873 }
05413229
NC		 8874
8875 return (signed long) offset;
62b3e311
PB		 8876}
8877
4934a27c
MM		 8878
8879/* Print one cde instruction on INFO->STREAM.
8880 Return TRUE if the instuction matched, FALSE if this is not a
8881 recognised cde instruction. */
8882static bfd_boolean
8883print_insn_cde (struct disassemble_info *info, long given, bfd_boolean thumb)
8884{
8885 const struct cdeopcode32 *insn;
8886 void *stream = info->stream;
8887 fprintf_ftype func = info->fprintf_func;
8888
8889 if (thumb)
8890 {
8891 /* Manually extract the coprocessor code from a known point.
8892 This position is the same across all CDE instructions. */
8893 for (insn = cde_opcodes; insn->assembler; insn++)
8894 {
8895 uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask;
8896 uint16_t coproc_mask = 1 << coproc;
8897 if (! (coproc_mask & cde_coprocs))
8898 continue;
8899
8900 if ((given & insn->mask) == insn->value)
8901 {
8902 bfd_boolean is_unpredictable = FALSE;
8903 const char *c;
8904
8905 for (c = insn->assembler; *c; c++)
8906 {
8907 if (*c == '%')
8908 {
8909 switch (*++c)
8910 {
8911 case '%':
8912 func (stream, "%%");
8913 break;
8914
8915 case '0': case '1': case '2': case '3': case '4':
8916 case '5': case '6': case '7': case '8': case '9':
8917 {
8918 int width;
8919 unsigned long value;
8920
8921 c = arm_decode_bitfield (c, given, &value, &width);
8922
8923 switch (*c)
8924 {
8925 case 'S':
8926 if (value > 10)
8927 is_unpredictable = TRUE;
8928 /* Fall through. */
8929 case 'R':
8930 if (value == 13)
8931 is_unpredictable = TRUE;
8932 /* Fall through. */
8933 case 'r':
8934 func (stream, "%s", arm_regnames[value]);
8935 break;
8936
8937 case 'n':
8938 if (value == 15)
8939 func (stream, "%s", "APSR_nzcv");
8940 else
8941 func (stream, "%s", arm_regnames[value]);
8942 break;
8943
8944 case 'T':
8945 func (stream, "%s", arm_regnames[value + 1]);
8946 break;
8947
8948 case 'd':
8949 func (stream, "%ld", value);
8950 break;
8951
5aae9ae9
MM		 8952 case 'V':
8953 if (given & (1 << 6))
8954 func (stream, "q%ld", value >> 1);
8955 else if (given & (1 << 24))
8956 func (stream, "d%ld", value);
8957 else
8958 {
8959 /* Encoding for S register is different than for D and
8960 Q registers. S registers are encoded using the top
8961 single bit in position 22 as the lowest bit of the
8962 register number, while for Q and D it represents the
8963 highest bit of the register number. */
8964 uint8_t top_bit = (value >> 4) & 1;
8965 uint8_t tmp = (value << 1) & 0x1e;
8966 uint8_t res = tmp | top_bit;
8967 func (stream, "s%u", res);
8968 }
8969 break;
8970
4934a27c
MM		 8971 default:
8972 abort ();
8973 }
8974 }
8975 break;
8976
8977 case 'p':
8978 {
8979 uint8_t proc_number = (given >> 8) & 0x7;
8980 func (stream, "p%u", proc_number);
8981 break;
8982 }
8983
8984 case 'a':
8985 {
8986 uint8_t a_offset = 28;
8987 if (given & (1 << a_offset))
8988 func (stream, "a");
8989 break;
8990 }
8991 default:
8992 abort ();
8993 }
8994 }
8995 else
8996 func (stream, "%c", *c);
8997 }
8998
8999 if (is_unpredictable)
9000 func (stream, UNPREDICTABLE_INSTRUCTION);
9001
9002 return TRUE;
9003 }
9004 }
9005 return FALSE;
9006 }
9007 else
9008 return FALSE;
9009}
9010
9011
16980d0b
JB		 9012/* Print one neon instruction on INFO->STREAM.
9013 Return TRUE if the instuction matched, FALSE if this is not a
9014 recognised neon instruction. */
9015
9016static bfd_boolean
9017print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
9018{
9019 const struct opcode32 *insn;
9020 void *stream = info->stream;
9021 fprintf_ftype func = info->fprintf_func;
9022
9023 if (thumb)
9024 {
9025 if ((given & 0xef000000) == 0xef000000)
9026 {
0313a2b8 9027 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 9028 unsigned long bit28 = given & (1 << 28);
9029
9030 given &= 0x00ffffff;
9031 if (bit28)
9032 given |= 0xf3000000;
9033 else
9034 given |= 0xf2000000;
9035 }
9036 else if ((given & 0xff000000) == 0xf9000000)
9037 given ^= 0xf9000000 ^ 0xf4000000;
aab2c27d
MM		 9038 /* BFloat16 neon instructions without special top byte handling. */
9039 else if ((given & 0xff000000) == 0xfe000000
9040 || (given & 0xff000000) == 0xfc000000)
9041 ;
9743db03 9042 /* vdup is also a valid neon instruction. */
e409955d 9043 else if ((given & 0xff900f5f) != 0xee800b10)
16980d0b
JB		 9044 return FALSE;
9045 }
43e65147 9046
16980d0b
JB		 9047 for (insn = neon_opcodes; insn->assembler; insn++)
9048 {
e409955d
FS		 9049 unsigned long cond_mask = insn->mask;
9050 unsigned long cond_value = insn->value;
9051 int cond;
9052
9053 if (thumb)
9054 {
9055 if ((cond_mask & 0xf0000000) == 0) {
9056 /* For the entries in neon_opcodes, an opcode mask/value with
9057 the high 4 bits equal to 0 indicates a conditional
9058 instruction. For thumb however, we need to include those
9059 bits in the instruction matching. */
9060 cond_mask |= 0xf0000000;
9061 /* Furthermore, the thumb encoding of a conditional instruction
9062 will have the high 4 bits equal to 0xe. */
9063 cond_value |= 0xe0000000;
9064 }
9065 if (ifthen_state)
9066 cond = IFTHEN_COND;
9067 else
9068 cond = COND_UNCOND;
9069 }
9070 else
9071 {
9072 if ((given & 0xf0000000) == 0xf0000000)
9073 {
9074 /* If the instruction is unconditional, update the mask to only
9075 match against unconditional opcode values. */
9076 cond_mask |= 0xf0000000;
9077 cond = COND_UNCOND;
9078 }
9079 else
9080 {
9081 cond = (given >> 28) & 0xf;
9082 if (cond == 0xe)
9083 cond = COND_UNCOND;
9084 }
9085 }
9086
9087 if ((given & cond_mask) == cond_value)
16980d0b 9088 {
05413229 9089 signed long value_in_comment = 0;
e2efe87d 9090 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 9091 const char *c;
9092
9093 for (c = insn->assembler; *c; c++)
9094 {
9095 if (*c == '%')
9096 {
9097 switch (*++c)
9098 {
9099 case '%':
9100 func (stream, "%%");
9101 break;
9102
e2efe87d
MGD		 9103 case 'u':
9104 if (thumb && ifthen_state)
9105 is_unpredictable = TRUE;
9106
9107 /* Fall through. */
c22aaad1 9108 case 'c':
e409955d 9109 func (stream, "%s", arm_conditional[cond]);
c22aaad1
PB		 9110 break;
9111
16980d0b
JB		 9112 case 'A':
9113 {
43e65147 9114 static const unsigned char enc[16] =
16980d0b
JB		 9115 {
9116 0x4, 0x14, /* st4 0,1 */
9117 0x4, /* st1 2 */
9118 0x4, /* st2 3 */
9119 0x3, /* st3 4 */
9120 0x13, /* st3 5 */
9121 0x3, /* st1 6 */
9122 0x1, /* st1 7 */
9123 0x2, /* st2 8 */
9124 0x12, /* st2 9 */
9125 0x2, /* st1 10 */
9126 0, 0, 0, 0, 0
9127 };
9128 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9129 int rn = ((given >> 16) & 0xf);
9130 int rm = ((given >> 0) & 0xf);
9131 int align = ((given >> 4) & 0x3);
9132 int type = ((given >> 8) & 0xf);
9133 int n = enc[type] & 0xf;
9134 int stride = (enc[type] >> 4) + 1;
9135 int ix;
43e65147 9136
16980d0b
JB		 9137 func (stream, "{");
9138 if (stride > 1)
9139 for (ix = 0; ix != n; ix++)
9140 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
9141 else if (n == 1)
9142 func (stream, "d%d", rd);
9143 else
9144 func (stream, "d%d-d%d", rd, rd + n - 1);
9145 func (stream, "}, [%s", arm_regnames[rn]);
9146 if (align)
8e560766 9147 func (stream, " :%d", 32 << align);
16980d0b
JB		 9148 func (stream, "]");
9149 if (rm == 0xd)
9150 func (stream, "!");
9151 else if (rm != 0xf)
9152 func (stream, ", %s", arm_regnames[rm]);
9153 }
9154 break;
43e65147 9155
16980d0b
JB		 9156 case 'B':
9157 {
9158 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9159 int rn = ((given >> 16) & 0xf);
9160 int rm = ((given >> 0) & 0xf);
9161 int idx_align = ((given >> 4) & 0xf);
9162 int align = 0;
9163 int size = ((given >> 10) & 0x3);
9164 int idx = idx_align >> (size + 1);
9165 int length = ((given >> 8) & 3) + 1;
9166 int stride = 1;
9167 int i;
9168
9169 if (length > 1 && size > 0)
9170 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 9171
16980d0b
JB		 9172 switch (length)
9173 {
9174 case 1:
9175 {
9176 int amask = (1 << size) - 1;
9177 if ((idx_align & (1 << size)) != 0)
9178 return FALSE;
9179 if (size > 0)
9180 {
9181 if ((idx_align & amask) == amask)
9182 align = 8 << size;
9183 else if ((idx_align & amask) != 0)
9184 return FALSE;
9185 }
9186 }
9187 break;
43e65147 9188
16980d0b
JB		 9189 case 2:
9190 if (size == 2 && (idx_align & 2) != 0)
9191 return FALSE;
9192 align = (idx_align & 1) ? 16 << size : 0;
9193 break;
43e65147 9194
16980d0b
JB		 9195 case 3:
9196 if ((size == 2 && (idx_align & 3) != 0)
9197 || (idx_align & 1) != 0)
9198 return FALSE;
9199 break;
43e65147 9200
16980d0b
JB		 9201 case 4:
9202 if (size == 2)
9203 {
9204 if ((idx_align & 3) == 3)
9205 return FALSE;
9206 align = (idx_align & 3) * 64;
9207 }
9208 else
9209 align = (idx_align & 1) ? 32 << size : 0;
9210 break;
43e65147 9211
16980d0b
JB		 9212 default:
9213 abort ();
9214 }
43e65147 9215
16980d0b
JB		 9216 func (stream, "{");
9217 for (i = 0; i < length; i++)
9218 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
9219 rd + i * stride, idx);
9220 func (stream, "}, [%s", arm_regnames[rn]);
9221 if (align)
8e560766 9222 func (stream, " :%d", align);
16980d0b
JB		 9223 func (stream, "]");
9224 if (rm == 0xd)
9225 func (stream, "!");
9226 else if (rm != 0xf)
9227 func (stream, ", %s", arm_regnames[rm]);
9228 }
9229 break;
43e65147 9230
16980d0b
JB		 9231 case 'C':
9232 {
9233 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9234 int rn = ((given >> 16) & 0xf);
9235 int rm = ((given >> 0) & 0xf);
9236 int align = ((given >> 4) & 0x1);
9237 int size = ((given >> 6) & 0x3);
9238 int type = ((given >> 8) & 0x3);
9239 int n = type + 1;
9240 int stride = ((given >> 5) & 0x1);
9241 int ix;
43e65147 9242
16980d0b
JB		 9243 if (stride && (n == 1))
9244 n++;
9245 else
9246 stride++;
43e65147 9247
16980d0b
JB		 9248 func (stream, "{");
9249 if (stride > 1)
9250 for (ix = 0; ix != n; ix++)
9251 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
9252 else if (n == 1)
9253 func (stream, "d%d[]", rd);
9254 else
9255 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
9256 func (stream, "}, [%s", arm_regnames[rn]);
9257 if (align)
9258 {
91d6fa6a 9259 align = (8 * (type + 1)) << size;
16980d0b
JB		 9260 if (type == 3)
9261 align = (size > 1) ? align >> 1 : align;
9262 if (type == 2 || (type == 0 && !size))
8e560766 9263 func (stream, " :<bad align %d>", align);
16980d0b 9264 else
8e560766 9265 func (stream, " :%d", align);
16980d0b
JB		 9266 }
9267 func (stream, "]");
9268 if (rm == 0xd)
9269 func (stream, "!");
9270 else if (rm != 0xf)
9271 func (stream, ", %s", arm_regnames[rm]);
9272 }
9273 break;
43e65147 9274
16980d0b
JB		 9275 case 'D':
9276 {
9277 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9278 int size = (given >> 20) & 3;
9279 int reg = raw_reg & ((4 << size) - 1);
9280 int ix = raw_reg >> size >> 2;
43e65147 9281
16980d0b
JB		 9282 func (stream, "d%d[%d]", reg, ix);
9283 }
9284 break;
43e65147 9285
16980d0b 9286 case 'E':
fe56b6ce 9287 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 9288 {
9289 int bits = 0;
9290 int cmode = (given >> 8) & 0xf;
9291 int op = (given >> 5) & 0x1;
9292 unsigned long value = 0, hival = 0;
9293 unsigned shift;
9294 int size = 0;
0dbde4cf 9295 int isfloat = 0;
43e65147 9296
16980d0b
JB		 9297 bits |= ((given >> 24) & 1) << 7;
9298 bits |= ((given >> 16) & 7) << 4;
9299 bits |= ((given >> 0) & 15) << 0;
43e65147 9300
16980d0b
JB		 9301 if (cmode < 8)
9302 {
9303 shift = (cmode >> 1) & 3;
fe56b6ce 9304 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9305 size = 32;
9306 }
9307 else if (cmode < 12)
9308 {
9309 shift = (cmode >> 1) & 1;
fe56b6ce 9310 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9311 size = 16;
9312 }
9313 else if (cmode < 14)
9314 {
9315 shift = (cmode & 1) + 1;
fe56b6ce 9316 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9317 value |= (1ul << (8 * shift)) - 1;
9318 size = 32;
9319 }
9320 else if (cmode == 14)
9321 {
9322 if (op)
9323 {
fe56b6ce 9324 /* Bit replication into bytes. */
16980d0b
JB		 9325 int ix;
9326 unsigned long mask;
43e65147 9327
16980d0b
JB		 9328 value = 0;
9329 hival = 0;
9330 for (ix = 7; ix >= 0; ix--)
9331 {
9332 mask = ((bits >> ix) & 1) ? 0xff : 0;
9333 if (ix <= 3)
9334 value = (value << 8) | mask;
9335 else
9336 hival = (hival << 8) | mask;
9337 }
9338 size = 64;
9339 }
9340 else
9341 {
fe56b6ce
NC		 9342 /* Byte replication. */
9343 value = (unsigned long) bits;
16980d0b
JB		 9344 size = 8;
9345 }
9346 }
9347 else if (!op)
9348 {
fe56b6ce 9349 /* Floating point encoding. */
16980d0b 9350 int tmp;
43e65147 9351
fe56b6ce
NC		 9352 value = (unsigned long) (bits & 0x7f) << 19;
9353 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 9354 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 9355 value |= (unsigned long) tmp << 24;
16980d0b 9356 size = 32;
0dbde4cf 9357 isfloat = 1;
16980d0b
JB		 9358 }
9359 else
9360 {
9361 func (stream, "<illegal constant %.8x:%x:%x>",
9362 bits, cmode, op);
9363 size = 32;
9364 break;
9365 }
9366 switch (size)
9367 {
9368 case 8:
9369 func (stream, "#%ld\t; 0x%.2lx", value, value);
9370 break;
43e65147 9371
16980d0b
JB		 9372 case 16:
9373 func (stream, "#%ld\t; 0x%.4lx", value, value);
9374 break;
9375
9376 case 32:
0dbde4cf
JB		 9377 if (isfloat)
9378 {
9379 unsigned char valbytes[4];
9380 double fvalue;
43e65147 9381
0dbde4cf
JB		 9382 /* Do this a byte at a time so we don't have to
9383 worry about the host's endianness. */
9384 valbytes[0] = value & 0xff;
9385 valbytes[1] = (value >> 8) & 0xff;
9386 valbytes[2] = (value >> 16) & 0xff;
9387 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 9388
9389 floatformat_to_double
c1e26897
NC		 9390 (& floatformat_ieee_single_little, valbytes,
9391 & fvalue);
43e65147 9392
0dbde4cf
JB		 9393 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
9394 value);
9395 }
9396 else
4e9d3b81 9397 func (stream, "#%ld\t; 0x%.8lx",
43e65147 9398 (long) (((value & 0x80000000L) != 0)
9d82ec38 9399 ? value | ~0xffffffffL : value),
c1e26897 9400 value);
16980d0b
JB		 9401 break;
9402
9403 case 64:
9404 func (stream, "#0x%.8lx%.8lx", hival, value);
9405 break;
43e65147 9406
16980d0b
JB		 9407 default:
9408 abort ();
9409 }
9410 }
9411 break;
43e65147 9412
16980d0b
JB		 9413 case 'F':
9414 {
9415 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9416 int num = (given >> 8) & 0x3;
43e65147 9417
16980d0b
JB		 9418 if (!num)
9419 func (stream, "{d%d}", regno);
9420 else if (num + regno >= 32)
9421 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
9422 else
9423 func (stream, "{d%d-d%d}", regno, regno + num);
9424 }
9425 break;
7e8e6784 9426
16980d0b
JB		 9427
9428 case '0': case '1': case '2': case '3': case '4':
9429 case '5': case '6': case '7': case '8': case '9':
9430 {
9431 int width;
9432 unsigned long value;
9433
9434 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9435
16980d0b
JB		 9436 switch (*c)
9437 {
9438 case 'r':
9439 func (stream, "%s", arm_regnames[value]);
9440 break;
9441 case 'd':
9442 func (stream, "%ld", value);
05413229 9443 value_in_comment = value;
16980d0b
JB		 9444 break;
9445 case 'e':
9446 func (stream, "%ld", (1ul << width) - value);
9447 break;
43e65147 9448
16980d0b
JB		 9449 case 'S':
9450 case 'T':
9451 case 'U':
05413229 9452 /* Various width encodings. */
16980d0b
JB		 9453 {
9454 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9455 int limit;
9456 unsigned low, high;
9457
9458 c++;
9459 if (*c >= '0' && *c <= '9')
9460 limit = *c - '0';
9461 else if (*c >= 'a' && *c <= 'f')
9462 limit = *c - 'a' + 10;
9463 else
9464 abort ();
9465 low = limit >> 2;
9466 high = limit & 3;
9467
9468 if (value < low || value > high)
9469 func (stream, "<illegal width %d>", base << value);
9470 else
9471 func (stream, "%d", base << value);
9472 }
9473 break;
9474 case 'R':
9475 if (given & (1 << 6))
9476 goto Q;
9477 /* FALLTHROUGH */
9478 case 'D':
9479 func (stream, "d%ld", value);
9480 break;
9481 case 'Q':
9482 Q:
9483 if (value & 1)
9484 func (stream, "<illegal reg q%ld.5>", value >> 1);
9485 else
9486 func (stream, "q%ld", value >> 1);
9487 break;
43e65147 9488
16980d0b
JB		 9489 case '`':
9490 c++;
9491 if (value == 0)
9492 func (stream, "%c", *c);
9493 break;
9494 case '\'':
9495 c++;
9496 if (value == ((1ul << width) - 1))
9497 func (stream, "%c", *c);
9498 break;
9499 case '?':
fe56b6ce 9500 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 9501 c += 1 << width;
9502 break;
9503 default:
9504 abort ();
9505 }
16980d0b 9506 }
dffaa15c
AM		 9507 break;
9508
9509 default:
9510 abort ();
16980d0b
JB		 9511 }
9512 }
9513 else
9514 func (stream, "%c", *c);
9515 }
05413229
NC		 9516
9517 if (value_in_comment > 32 || value_in_comment < -16)
9518 func (stream, "\t; 0x%lx", value_in_comment);
9519
e2efe87d
MGD		 9520 if (is_unpredictable)
9521 func (stream, UNPREDICTABLE_INSTRUCTION);
9522
16980d0b
JB		 9523 return TRUE;
9524 }
9525 }
9526 return FALSE;
9527}
9528
73cd51e5
AV		 9529/* Print one mve instruction on INFO->STREAM.
9530 Return TRUE if the instuction matched, FALSE if this is not a
9531 recognised mve instruction. */
9532
9533static bfd_boolean
9534print_insn_mve (struct disassemble_info *info, long given)
9535{
9536 const struct mopcode32 *insn;
9537 void *stream = info->stream;
9538 fprintf_ftype func = info->fprintf_func;
9539
9540 for (insn = mve_opcodes; insn->assembler; insn++)
9541 {
9542 if (((given & insn->mask) == insn->value)
9543 && !is_mve_encoding_conflict (given, insn->mve_op))
9544 {
9545 signed long value_in_comment = 0;
9546 bfd_boolean is_unpredictable = FALSE;
9547 bfd_boolean is_undefined = FALSE;
9548 const char *c;
9549 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9550 enum mve_undefined undefined_cond = UNDEF_NONE;
9551
9552 /* Most vector mve instruction are illegal in a it block.
9553 There are a few exceptions; check for them. */
9554 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9555 {
9556 is_unpredictable = TRUE;
9557 unpredictable_cond = UNPRED_IT_BLOCK;
9558 }
9559 else if (is_mve_unpredictable (given, insn->mve_op,
9560 &unpredictable_cond))
9561 is_unpredictable = TRUE;
9562
9563 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9564 is_undefined = TRUE;
9565
c4a23bf8
SP		 9566 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9567 i.e "VMOV Qd, Qm". */
9568 if ((insn->mve_op == MVE_VORR_REG)
9569 && (arm_decode_field (given, 1, 3)
9570 == arm_decode_field (given, 17, 19)))
9571 continue;
9572
73cd51e5
AV		 9573 for (c = insn->assembler; *c; c++)
9574 {
9575 if (*c == '%')
9576 {
9577 switch (*++c)
9578 {
9579 case '%':
9580 func (stream, "%%");
9581 break;
9582
ef1576a1
AV		 9583 case 'a':
9584 /* Don't print anything for '+' as it is implied. */
9585 if (arm_decode_field (given, 23, 23) == 0)
9586 func (stream, "-");
9587 break;
9588
143275ea
AV		 9589 case 'c':
9590 if (ifthen_state)
9591 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9592 break;
9593
aef6d006
AV		 9594 case 'd':
9595 print_mve_vld_str_addr (info, given, insn->mve_op);
9596 break;
9597
143275ea
AV		 9598 case 'i':
9599 {
9600 long mve_mask = mve_extract_pred_mask (given);
9601 func (stream, "%s", mve_predicatenames[mve_mask]);
9602 }
9603 break;
9604
23d00a41
SD		 9605 case 'j':
9606 {
9607 unsigned int imm5 = 0;
9608 imm5 |= arm_decode_field (given, 6, 7);
9609 imm5 |= (arm_decode_field (given, 12, 14) << 2);
9610 func (stream, "#%u", (imm5 == 0) ? 32 : imm5);
9611 }
9612 break;
9613
08132bdd
SP		 9614 case 'k':
9615 func (stream, "#%u",
9616 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9617 break;
9618
143275ea
AV		 9619 case 'n':
9620 print_vec_condition (info, given, insn->mve_op);
9621 break;
9622
ef1576a1
AV		 9623 case 'o':
9624 if (arm_decode_field (given, 0, 0) == 1)
9625 {
9626 unsigned long size
9627 = arm_decode_field (given, 4, 4)
9628 | (arm_decode_field (given, 6, 6) << 1);
9629
9630 func (stream, ", uxtw #%lu", size);
9631 }
9632 break;
9633
bf0b396d
AV		 9634 case 'm':
9635 print_mve_rounding_mode (info, given, insn->mve_op);
9636 break;
9637
9638 case 's':
9639 print_mve_vcvt_size (info, given, insn->mve_op);
9640 break;
9641
aef6d006
AV		 9642 case 'u':
9643 {
c507f10b
AV		 9644 unsigned long op1 = arm_decode_field (given, 21, 22);
9645
9646 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9647 {
9648 /* Check for signed. */
9649 if (arm_decode_field (given, 23, 23) == 0)
9650 {
9651 /* We don't print 's' for S32. */
9652 if ((arm_decode_field (given, 5, 6) == 0)
9653 && ((op1 == 0) || (op1 == 1)))
9654 ;
9655 else
9656 func (stream, "s");
9657 }
9658 else
9659 func (stream, "u");
9660 }
aef6d006 9661 else
c507f10b
AV		 9662 {
9663 if (arm_decode_field (given, 28, 28) == 0)
9664 func (stream, "s");
9665 else
9666 func (stream, "u");
9667 }
aef6d006 9668 }
ef1576a1 9669 break;
aef6d006 9670
143275ea
AV		 9671 case 'v':
9672 print_instruction_predicate (info);
9673 break;
9674
04d54ace
AV		 9675 case 'w':
9676 if (arm_decode_field (given, 21, 21) == 1)
9677 func (stream, "!");
9678 break;
9679
9680 case 'B':
9681 print_mve_register_blocks (info, given, insn->mve_op);
9682 break;
9683
c507f10b
AV		 9684 case 'E':
9685 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9686
9687 print_simd_imm8 (info, given, 28, insn);
9688 break;
9689
9690 case 'N':
9691 print_mve_vmov_index (info, given);
9692 break;
9693
14925797
AV		 9694 case 'T':
9695 if (arm_decode_field (given, 12, 12) == 0)
9696 func (stream, "b");
9697 else
9698 func (stream, "t");
9699 break;
9700
d3b63143
AV		 9701 case 'X':
9702 if (arm_decode_field (given, 12, 12) == 1)
9703 func (stream, "x");
9704 break;
9705
143275ea
AV		 9706 case '0': case '1': case '2': case '3': case '4':
9707 case '5': case '6': case '7': case '8': case '9':
9708 {
9709 int width;
9710 unsigned long value;
9711
9712 c = arm_decode_bitfield (c, given, &value, &width);
9713
9714 switch (*c)
9715 {
9716 case 'Z':
9717 if (value == 13)
9718 is_unpredictable = TRUE;
9719 else if (value == 15)
9720 func (stream, "zr");
9721 else
9722 func (stream, "%s", arm_regnames[value]);
9723 break;
23d00a41 9724
e39c1607
SD		 9725 case 'c':
9726 func (stream, "%s", arm_conditional[value]);
9727 break;
9728
9729 case 'C':
9730 value ^= 1;
9731 func (stream, "%s", arm_conditional[value]);
9732 break;
9733
23d00a41
SD		 9734 case 'S':
9735 if (value == 13 || value == 15)
9736 is_unpredictable = TRUE;
9737 else
9738 func (stream, "%s", arm_regnames[value]);
9739 break;
9740
143275ea
AV		 9741 case 's':
9742 print_mve_size (info,
9743 value,
9744 insn->mve_op);
9745 break;
66dcaa5d
AV		 9746 case 'I':
9747 if (value == 1)
9748 func (stream, "i");
9749 break;
d3b63143
AV		 9750 case 'A':
9751 if (value == 1)
9752 func (stream, "a");
9753 break;
1c8f2df8
AV		 9754 case 'h':
9755 {
9756 unsigned int odd_reg = (value << 1) | 1;
9757 func (stream, "%s", arm_regnames[odd_reg]);
9758 }
9759 break;
ef1576a1
AV		 9760 case 'i':
9761 {
9762 unsigned long imm
9763 = arm_decode_field (given, 0, 6);
9764 unsigned long mod_imm = imm;
9765
9766 switch (insn->mve_op)
9767 {
9768 case MVE_VLDRW_GATHER_T5:
9769 case MVE_VSTRW_SCATTER_T5:
9770 mod_imm = mod_imm << 2;
9771 break;
9772 case MVE_VSTRD_SCATTER_T6:
9773 case MVE_VLDRD_GATHER_T6:
9774 mod_imm = mod_imm << 3;
9775 break;
9776
9777 default:
9778 break;
9779 }
9780
9781 func (stream, "%lu", mod_imm);
9782 }
9783 break;
bf0b396d
AV		 9784 case 'k':
9785 func (stream, "%lu", 64 - value);
9786 break;
1c8f2df8
AV		 9787 case 'l':
9788 {
9789 unsigned int even_reg = value << 1;
9790 func (stream, "%s", arm_regnames[even_reg]);
9791 }
9792 break;
9793 case 'u':
9794 switch (value)
9795 {
9796 case 0:
9797 func (stream, "1");
9798 break;
9799 case 1:
9800 func (stream, "2");
9801 break;
9802 case 2:
9803 func (stream, "4");
9804 break;
9805 case 3:
9806 func (stream, "8");
9807 break;
9808 default:
9809 break;
9810 }
9811 break;
897b9bbc
AV		 9812 case 'o':
9813 print_mve_rotate (info, value, width);
9814 break;
9743db03
AV		 9815 case 'r':
9816 func (stream, "%s", arm_regnames[value]);
9817 break;
04d54ace 9818 case 'd':
ed63aa17
AV		 9819 if (insn->mve_op == MVE_VQSHL_T2
9820 || insn->mve_op == MVE_VQSHLU_T3
9821 || insn->mve_op == MVE_VRSHR
9822 || insn->mve_op == MVE_VRSHRN
9823 || insn->mve_op == MVE_VSHL_T1
9824 || insn->mve_op == MVE_VSHLL_T1
9825 || insn->mve_op == MVE_VSHR
9826 || insn->mve_op == MVE_VSHRN
9827 || insn->mve_op == MVE_VSLI
9828 || insn->mve_op == MVE_VSRI)
9829 print_mve_shift_n (info, given, insn->mve_op);
9830 else if (insn->mve_op == MVE_VSHLL_T2)
9831 {
9832 switch (value)
9833 {
9834 case 0x00:
9835 func (stream, "8");
9836 break;
9837 case 0x01:
9838 func (stream, "16");
9839 break;
9840 case 0x10:
9841 print_mve_undefined (info, UNDEF_SIZE_0);
9842 break;
9843 default:
9844 assert (0);
9845 break;
9846 }
9847 }
9848 else
9849 {
9850 if (insn->mve_op == MVE_VSHLC && value == 0)
9851 value = 32;
9852 func (stream, "%ld", value);
9853 value_in_comment = value;
9854 }
04d54ace 9855 break;
c507f10b
AV		 9856 case 'F':
9857 func (stream, "s%ld", value);
9858 break;
143275ea
AV		 9859 case 'Q':
9860 if (value & 0x8)
9861 func (stream, "<illegal reg q%ld.5>", value);
9862 else
9863 func (stream, "q%ld", value);
9864 break;
c507f10b
AV		 9865 case 'x':
9866 func (stream, "0x%08lx", value);
9867 break;
143275ea
AV		 9868 default:
9869 abort ();
9870 }
9871 break;
9872 default:
9873 abort ();
9874 }
73cd51e5
AV		 9875 }
9876 }
9877 else
9878 func (stream, "%c", *c);
9879 }
9880
9881 if (value_in_comment > 32 || value_in_comment < -16)
9882 func (stream, "\t; 0x%lx", value_in_comment);
9883
9884 if (is_unpredictable)
9885 print_mve_unpredictable (info, unpredictable_cond);
9886
9887 if (is_undefined)
9888 print_mve_undefined (info, undefined_cond);
9889
143275ea
AV		 9890 if ((vpt_block_state.in_vpt_block == FALSE)
9891 && !ifthen_state
9892 && (is_vpt_instruction (given) == TRUE))
9893 mark_inside_vpt_block (given);
9894 else if (vpt_block_state.in_vpt_block == TRUE)
9895 update_vpt_block_state ();
9896
73cd51e5
AV		 9897 return TRUE;
9898 }
9899 }
9900 return FALSE;
9901}
9902
9903
90ec0d68
MGD		 9904/* Return the name of a v7A special register. */
9905
43e65147 9906static const char *
90ec0d68
MGD		 9907banked_regname (unsigned reg)
9908{
9909 switch (reg)
9910 {
9911 case 15: return "CPSR";
43e65147 9912 case 32: return "R8_usr";
90ec0d68
MGD		 9913 case 33: return "R9_usr";
9914 case 34: return "R10_usr";
9915 case 35: return "R11_usr";
9916 case 36: return "R12_usr";
9917 case 37: return "SP_usr";
9918 case 38: return "LR_usr";
43e65147 9919 case 40: return "R8_fiq";
90ec0d68
MGD		 9920 case 41: return "R9_fiq";
9921 case 42: return "R10_fiq";
9922 case 43: return "R11_fiq";
9923 case 44: return "R12_fiq";
9924 case 45: return "SP_fiq";
9925 case 46: return "LR_fiq";
9926 case 48: return "LR_irq";
9927 case 49: return "SP_irq";
9928 case 50: return "LR_svc";
9929 case 51: return "SP_svc";
9930 case 52: return "LR_abt";
9931 case 53: return "SP_abt";
9932 case 54: return "LR_und";
9933 case 55: return "SP_und";
9934 case 60: return "LR_mon";
9935 case 61: return "SP_mon";
9936 case 62: return "ELR_hyp";
9937 case 63: return "SP_hyp";
9938 case 79: return "SPSR";
9939 case 110: return "SPSR_fiq";
9940 case 112: return "SPSR_irq";
9941 case 114: return "SPSR_svc";
9942 case 116: return "SPSR_abt";
9943 case 118: return "SPSR_und";
9944 case 124: return "SPSR_mon";
9945 case 126: return "SPSR_hyp";
9946 default: return NULL;
9947 }
9948}
9949
e797f7e0
MGD		 9950/* Return the name of the DMB/DSB option. */
9951static const char *
9952data_barrier_option (unsigned option)
9953{
9954 switch (option & 0xf)
9955 {
9956 case 0xf: return "sy";
9957 case 0xe: return "st";
9958 case 0xd: return "ld";
9959 case 0xb: return "ish";
9960 case 0xa: return "ishst";
9961 case 0x9: return "ishld";
9962 case 0x7: return "un";
9963 case 0x6: return "unst";
9964 case 0x5: return "nshld";
9965 case 0x3: return "osh";
9966 case 0x2: return "oshst";
9967 case 0x1: return "oshld";
9968 default: return NULL;
9969 }
9970}
9971
4a5329c6
ZW		 9972/* Print one ARM instruction from PC on INFO->STREAM. */
9973
9974static void
9975print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 9976{
6b5d3a4d 9977 const struct opcode32 *insn;
6a51a8a8 9978 void *stream = info->stream;
6b5d3a4d 9979 fprintf_ftype func = info->fprintf_func;
b0e28b39 9980 struct arm_private_data *private_data = info->private_data;
252b5132 9981
16980d0b
JB		 9982 if (print_insn_coprocessor (pc, info, given, FALSE))
9983 return;
9984
9985 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 9986 return;
9987
33593eaf
MM		 9988 if (print_insn_generic_coprocessor (pc, info, given, FALSE))
9989 return;
9990
252b5132
RH		 9991 for (insn = arm_opcodes; insn->assembler; insn++)
9992 {
0313a2b8
NC		 9993 if ((given & insn->mask) != insn->value)
9994 continue;
823d2571
TG		 9995
9996 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 9997 continue;
9998
9999 /* Special case: an instruction with all bits set in the condition field
10000 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
10001 or by the catchall at the end of the table. */
10002 if ((given & 0xF0000000) != 0xF0000000
10003 || (insn->mask & 0xF0000000) == 0xF0000000
10004 || (insn->mask == 0 && insn->value == 0))
252b5132 10005 {
ff4a8d2b
NC		 10006 unsigned long u_reg = 16;
10007 unsigned long U_reg = 16;
ab8e2090 10008 bfd_boolean is_unpredictable = FALSE;
05413229 10009 signed long value_in_comment = 0;
6b5d3a4d 10010 const char *c;
b34976b6 10011
252b5132
RH		 10012 for (c = insn->assembler; *c; c++)
10013 {
10014 if (*c == '%')
10015 {
c1e26897
NC		 10016 bfd_boolean allow_unpredictable = FALSE;
10017
252b5132
RH		 10018 switch (*++c)
10019 {
10020 case '%':
10021 func (stream, "%%");
10022 break;
10023
10024 case 'a':
05413229 10025 value_in_comment = print_arm_address (pc, info, given);
62b3e311 10026 break;
252b5132 10027
62b3e311
PB		 10028 case 'P':
10029 /* Set P address bit and use normal address
10030 printing routine. */
c1e26897 10031 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 10032 break;
10033
c1e26897
NC		 10034 case 'S':
10035 allow_unpredictable = TRUE;
1a0670f3 10036 /* Fall through. */
252b5132
RH		 10037 case 's':
10038 if ((given & 0x004f0000) == 0x004f0000)
10039 {
58efb6c0 10040 /* PC relative with immediate offset. */
f8b960bc 10041 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 10042
aefd8a40
NC		 10043 if (PRE_BIT_SET)
10044 {
26d97720
NS		 10045 /* Elide positive zero offset. */
10046 if (offset || NEGATIVE_BIT_SET)
10047 func (stream, "[pc, #%s%d]\t; ",
d908c8af 10048 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 10049 else
26d97720
NS		 10050 func (stream, "[pc]\t; ");
10051 if (NEGATIVE_BIT_SET)
10052 offset = -offset;
aefd8a40
NC		 10053 info->print_address_func (offset + pc + 8, info);
10054 }
10055 else
10056 {
26d97720
NS		 10057 /* Always show the offset. */
10058 func (stream, "[pc], #%s%d",
d908c8af 10059 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 10060 if (! allow_unpredictable)
10061 is_unpredictable = TRUE;
aefd8a40 10062 }
252b5132
RH		 10063 }
10064 else
10065 {
fe56b6ce
NC		 10066 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
10067
b34976b6 10068 func (stream, "[%s",
252b5132 10069 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 10070
c1e26897 10071 if (PRE_BIT_SET)
252b5132 10072 {
c1e26897 10073 if (IMMEDIATE_BIT_SET)
252b5132 10074 {
26d97720
NS		 10075 /* Elide offset for non-writeback
10076 positive zero. */
10077 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
10078 || offset)
10079 func (stream, ", #%s%d",
10080 NEGATIVE_BIT_SET ? "-" : "", offset);
10081
10082 if (NEGATIVE_BIT_SET)
10083 offset = -offset;
945ee430 10084
fe56b6ce 10085 value_in_comment = offset;
252b5132 10086 }
945ee430 10087 else
ff4a8d2b
NC		 10088 {
10089 /* Register Offset or Register Pre-Indexed. */
10090 func (stream, ", %s%s",
10091 NEGATIVE_BIT_SET ? "-" : "",
10092 arm_regnames[given & 0xf]);
10093
10094 /* Writing back to the register that is the source/
10095 destination of the load/store is unpredictable. */
10096 if (! allow_unpredictable
10097 && WRITEBACK_BIT_SET
10098 && ((given & 0xf) == ((given >> 12) & 0xf)))
10099 is_unpredictable = TRUE;
10100 }
252b5132 10101
b34976b6 10102 func (stream, "]%s",
c1e26897 10103 WRITEBACK_BIT_SET ? "!" : "");
252b5132 10104 }
945ee430 10105 else
252b5132 10106 {
c1e26897 10107 if (IMMEDIATE_BIT_SET)
252b5132 10108 {
945ee430 10109 /* Immediate Post-indexed. */
aefd8a40 10110 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 10111 func (stream, "], #%s%d",
10112 NEGATIVE_BIT_SET ? "-" : "", offset);
10113 if (NEGATIVE_BIT_SET)
10114 offset = -offset;
fe56b6ce 10115 value_in_comment = offset;
252b5132 10116 }
945ee430 10117 else
ff4a8d2b
NC		 10118 {
10119 /* Register Post-indexed. */
10120 func (stream, "], %s%s",
10121 NEGATIVE_BIT_SET ? "-" : "",
10122 arm_regnames[given & 0xf]);
10123
10124 /* Writing back to the register that is the source/
10125 destination of the load/store is unpredictable. */
10126 if (! allow_unpredictable
10127 && (given & 0xf) == ((given >> 12) & 0xf))
10128 is_unpredictable = TRUE;
10129 }
c1e26897 10130
07a28fab
NC		 10131 if (! allow_unpredictable)
10132 {
10133 /* Writeback is automatically implied by post- addressing.
10134 Setting the W bit is unnecessary and ARM specify it as
10135 being unpredictable. */
10136 if (WRITEBACK_BIT_SET
10137 /* Specifying the PC register as the post-indexed
10138 registers is also unpredictable. */
ab8e2090
NC		 10139 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
10140 is_unpredictable = TRUE;
07a28fab 10141 }
252b5132
RH		 10142 }
10143 }
10144 break;
b34976b6 10145
252b5132 10146 case 'b':
6b5d3a4d 10147 {
f8b960bc 10148 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
1d67fe3b
TT		 10149 bfd_vma target = disp * 4 + pc + 8;
10150 info->print_address_func (target, info);
10151
10152 /* Fill in instruction information. */
10153 info->insn_info_valid = 1;
10154 info->insn_type = dis_branch;
10155 info->target = target;
6b5d3a4d 10156 }
252b5132
RH		 10157 break;
10158
10159 case 'c':
c22aaad1
PB		 10160 if (((given >> 28) & 0xf) != 0xe)
10161 func (stream, "%s",
10162 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 10163 break;
10164
10165 case 'm':
10166 {
10167 int started = 0;
10168 int reg;
10169
10170 func (stream, "{");
10171 for (reg = 0; reg < 16; reg++)
10172 if ((given & (1 << reg)) != 0)
10173 {
10174 if (started)
10175 func (stream, ", ");
10176 started = 1;
10177 func (stream, "%s", arm_regnames[reg]);
10178 }
10179 func (stream, "}");
ab8e2090
NC		 10180 if (! started)
10181 is_unpredictable = TRUE;
252b5132
RH		 10182 }
10183 break;
10184
37b37b2d 10185 case 'q':
78c66db8 10186 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 10187 break;
10188
252b5132
RH		 10189 case 'o':
10190 if ((given & 0x02000000) != 0)
10191 {
a415b1cd
JB		 10192 unsigned int rotate = (given & 0xf00) >> 7;
10193 unsigned int immed = (given & 0xff);
10194 unsigned int a, i;
10195
ebd1c6d1
AM		 10196 a = (immed << ((32 - rotate) & 31)
10197 | immed >> rotate) & 0xffffffff;
a415b1cd
JB		 10198 /* If there is another encoding with smaller rotate,
10199 the rotate should be specified directly. */
10200 for (i = 0; i < 32; i += 2)
ebd1c6d1 10201 if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
a415b1cd
JB		 10202 break;
10203
10204 if (i != rotate)
10205 func (stream, "#%d, %d", immed, rotate);
10206 else
10207 func (stream, "#%d", a);
10208 value_in_comment = a;
252b5132
RH		 10209 }
10210 else
78c66db8 10211 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 10212 break;
10213
10214 case 'p':
10215 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 10216 {
823d2571
TG		 10217 arm_feature_set arm_ext_v6 =
10218 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
10219
aefd8a40
NC		 10220 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
10221 mechanism for setting PSR flag bits. They are
10222 obsolete in V6 onwards. */
823d2571
TG		 10223 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
10224 arm_ext_v6))
aefd8a40 10225 func (stream, "p");
4ab90a7a
AV		 10226 else
10227 is_unpredictable = TRUE;
aefd8a40 10228 }
252b5132
RH		 10229 break;
10230
10231 case 't':
10232 if ((given & 0x01200000) == 0x00200000)
10233 func (stream, "t");
10234 break;
10235
252b5132 10236 case 'A':
05413229
NC		 10237 {
10238 int offset = given & 0xff;
f02232aa 10239
05413229 10240 value_in_comment = offset * 4;
c1e26897 10241 if (NEGATIVE_BIT_SET)
05413229 10242 value_in_comment = - value_in_comment;
f02232aa 10243
05413229 10244 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 10245
c1e26897 10246 if (PRE_BIT_SET)
05413229
NC		 10247 {
10248 if (offset)
fe56b6ce 10249 func (stream, ", #%d]%s",
d908c8af 10250 (int) value_in_comment,
c1e26897 10251 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 10252 else
10253 func (stream, "]");
10254 }
10255 else
10256 {
10257 func (stream, "]");
f02232aa 10258
c1e26897 10259 if (WRITEBACK_BIT_SET)
05413229
NC		 10260 {
10261 if (offset)
d908c8af 10262 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 10263 }
10264 else
fe56b6ce 10265 {
d908c8af 10266 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 10267 value_in_comment = offset;
10268 }
05413229
NC		 10269 }
10270 }
252b5132
RH		 10271 break;
10272
077b8428
NC		 10273 case 'B':
10274 /* Print ARM V5 BLX(1) address: pc+25 bits. */
10275 {
10276 bfd_vma address;
10277 bfd_vma offset = 0;
b34976b6 10278
c1e26897 10279 if (! NEGATIVE_BIT_SET)
077b8428
NC		 10280 /* Is signed, hi bits should be ones. */
10281 offset = (-1) ^ 0x00ffffff;
10282
10283 /* Offset is (SignExtend(offset field)<<2). */
10284 offset += given & 0x00ffffff;
10285 offset <<= 2;
10286 address = offset + pc + 8;
b34976b6 10287
8f06b2d8
PB		 10288 if (given & 0x01000000)
10289 /* H bit allows addressing to 2-byte boundaries. */
10290 address += 2;
b1ee46c5 10291
8f06b2d8 10292 info->print_address_func (address, info);
1d67fe3b
TT		 10293
10294 /* Fill in instruction information. */
10295 info->insn_info_valid = 1;
10296 info->insn_type = dis_branch;
10297 info->target = address;
b1ee46c5 10298 }
b1ee46c5
AH		 10299 break;
10300
252b5132 10301 case 'C':
90ec0d68
MGD		 10302 if ((given & 0x02000200) == 0x200)
10303 {
10304 const char * name;
10305 unsigned sysm = (given & 0x004f0000) >> 16;
10306
10307 sysm |= (given & 0x300) >> 4;
10308 name = banked_regname (sysm);
10309
10310 if (name != NULL)
10311 func (stream, "%s", name);
10312 else
d908c8af 10313 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 10314 }
10315 else
10316 {
43e65147 10317 func (stream, "%cPSR_",
90ec0d68
MGD		 10318 (given & 0x00400000) ? 'S' : 'C');
10319 if (given & 0x80000)
10320 func (stream, "f");
10321 if (given & 0x40000)
10322 func (stream, "s");
10323 if (given & 0x20000)
10324 func (stream, "x");
10325 if (given & 0x10000)
10326 func (stream, "c");
10327 }
252b5132
RH		 10328 break;
10329
62b3e311 10330 case 'U':
43e65147 10331 if ((given & 0xf0) == 0x60)
62b3e311 10332 {
52e7f43d
RE		 10333 switch (given & 0xf)
10334 {
10335 case 0xf: func (stream, "sy"); break;
10336 default:
10337 func (stream, "#%d", (int) given & 0xf);
10338 break;
10339 }
43e65147
L		 10340 }
10341 else
52e7f43d 10342 {
e797f7e0
MGD		 10343 const char * opt = data_barrier_option (given & 0xf);
10344 if (opt != NULL)
10345 func (stream, "%s", opt);
10346 else
52e7f43d 10347 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 10348 }
10349 break;
10350
b34976b6 10351 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 10352 case '5': case '6': case '7': case '8': case '9':
10353 {
16980d0b
JB		 10354 int width;
10355 unsigned long value;
252b5132 10356
16980d0b 10357 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 10358
252b5132
RH		 10359 switch (*c)
10360 {
ab8e2090
NC		 10361 case 'R':
10362 if (value == 15)
10363 is_unpredictable = TRUE;
10364 /* Fall through. */
16980d0b 10365 case 'r':
9eb6c0f1
MGD		 10366 case 'T':
10367 /* We want register + 1 when decoding T. */
10368 if (*c == 'T')
2bddb71a 10369 value = (value + 1) & 0xf;
9eb6c0f1 10370
ff4a8d2b
NC		 10371 if (c[1] == 'u')
10372 {
10373 /* Eat the 'u' character. */
10374 ++ c;
10375
10376 if (u_reg == value)
10377 is_unpredictable = TRUE;
10378 u_reg = value;
10379 }
10380 if (c[1] == 'U')
10381 {
10382 /* Eat the 'U' character. */
10383 ++ c;
10384
10385 if (U_reg == value)
10386 is_unpredictable = TRUE;
10387 U_reg = value;
10388 }
16980d0b
JB		 10389 func (stream, "%s", arm_regnames[value]);
10390 break;
10391 case 'd':
10392 func (stream, "%ld", value);
05413229 10393 value_in_comment = value;
16980d0b
JB		 10394 break;
10395 case 'b':
10396 func (stream, "%ld", value * 8);
05413229 10397 value_in_comment = value * 8;
16980d0b
JB		 10398 break;
10399 case 'W':
10400 func (stream, "%ld", value + 1);
05413229 10401 value_in_comment = value + 1;
16980d0b
JB		 10402 break;
10403 case 'x':
10404 func (stream, "0x%08lx", value);
10405
10406 /* Some SWI instructions have special
10407 meanings. */
10408 if ((given & 0x0fffffff) == 0x0FF00000)
10409 func (stream, "\t; IMB");
10410 else if ((given & 0x0fffffff) == 0x0FF00001)
10411 func (stream, "\t; IMBRange");
10412 break;
10413 case 'X':
10414 func (stream, "%01lx", value & 0xf);
05413229 10415 value_in_comment = value;
252b5132
RH		 10416 break;
10417 case '`':
10418 c++;
16980d0b 10419 if (value == 0)
252b5132
RH		 10420 func (stream, "%c", *c);
10421 break;
10422 case '\'':
10423 c++;
16980d0b 10424 if (value == ((1ul << width) - 1))
252b5132
RH		 10425 func (stream, "%c", *c);
10426 break;
10427 case '?':
fe56b6ce 10428 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 10429 c += 1 << width;
252b5132
RH		 10430 break;
10431 default:
10432 abort ();
10433 }
dffaa15c
AM		 10434 }
10435 break;
0dd132b6 10436
dffaa15c
AM		 10437 case 'e':
10438 {
10439 int imm;
0dd132b6 10440
dffaa15c
AM		 10441 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10442 func (stream, "%d", imm);
10443 value_in_comment = imm;
10444 }
10445 break;
fe56b6ce 10446
dffaa15c
AM		 10447 case 'E':
10448 /* LSB and WIDTH fields of BFI or BFC. The machine-
10449 language instruction encodes LSB and MSB. */
10450 {
10451 long msb = (given & 0x001f0000) >> 16;
10452 long lsb = (given & 0x00000f80) >> 7;
10453 long w = msb - lsb + 1;
0a003adc 10454
dffaa15c
AM		 10455 if (w > 0)
10456 func (stream, "#%lu, #%lu", lsb, w);
10457 else
10458 func (stream, "(invalid: %lu:%lu)", lsb, msb);
10459 }
10460 break;
90ec0d68 10461
dffaa15c
AM		 10462 case 'R':
10463 /* Get the PSR/banked register name. */
10464 {
10465 const char * name;
10466 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 10467
dffaa15c
AM		 10468 sysm |= (given & 0x300) >> 4;
10469 name = banked_regname (sysm);
90ec0d68 10470
dffaa15c
AM		 10471 if (name != NULL)
10472 func (stream, "%s", name);
10473 else
10474 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10475 }
10476 break;
fe56b6ce 10477
dffaa15c
AM		 10478 case 'V':
10479 /* 16-bit unsigned immediate from a MOVT or MOVW
10480 instruction, encoded in bits 0:11 and 15:19. */
10481 {
10482 long hi = (given & 0x000f0000) >> 4;
10483 long lo = (given & 0x00000fff);
10484 long imm16 = hi | lo;
0a003adc 10485
dffaa15c
AM		 10486 func (stream, "#%lu", imm16);
10487 value_in_comment = imm16;
252b5132 10488 }
dffaa15c
AM		 10489 break;
10490
10491 default:
10492 abort ();
252b5132
RH		 10493 }
10494 }
10495 else
10496 func (stream, "%c", *c);
10497 }
05413229
NC		 10498
10499 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 10500 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 10501
10502 if (is_unpredictable)
10503 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 10504
4a5329c6 10505 return;
252b5132
RH		 10506 }
10507 }
0b347048
TC		 10508 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10509 return;
252b5132
RH		 10510}
10511
4a5329c6 10512/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 10513
4a5329c6
ZW		 10514static void
10515print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 10516{
6b5d3a4d 10517 const struct opcode16 *insn;
6a51a8a8
AM		 10518 void *stream = info->stream;
10519 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 10520
10521 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 10522 if ((given & insn->mask) == insn->value)
10523 {
05413229 10524 signed long value_in_comment = 0;
6b5d3a4d 10525 const char *c = insn->assembler;
05413229 10526
c19d1205
ZW		 10527 for (; *c; c++)
10528 {
10529 int domaskpc = 0;
10530 int domasklr = 0;
10531
10532 if (*c != '%')
10533 {
10534 func (stream, "%c", *c);
10535 continue;
10536 }
252b5132 10537
c19d1205
ZW		 10538 switch (*++c)
10539 {
10540 case '%':
10541 func (stream, "%%");
10542 break;
b34976b6 10543
c22aaad1
PB		 10544 case 'c':
10545 if (ifthen_state)
10546 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10547 break;
10548
10549 case 'C':
10550 if (ifthen_state)
10551 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10552 else
10553 func (stream, "s");
10554 break;
10555
10556 case 'I':
10557 {
10558 unsigned int tmp;
10559
10560 ifthen_next_state = given & 0xff;
10561 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10562 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
10563 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
10564 }
10565 break;
10566
10567 case 'x':
10568 if (ifthen_next_state)
10569 func (stream, "\t; unpredictable branch in IT block\n");
10570 break;
10571
10572 case 'X':
10573 if (ifthen_state)
10574 func (stream, "\t; unpredictable <IT:%s>",
10575 arm_conditional[IFTHEN_COND]);
10576 break;
10577
c19d1205
ZW		 10578 case 'S':
10579 {
10580 long reg;
10581
10582 reg = (given >> 3) & 0x7;
10583 if (given & (1 << 6))
10584 reg += 8;
4f3c3dbb 10585
c19d1205
ZW		 10586 func (stream, "%s", arm_regnames[reg]);
10587 }
10588 break;
baf0cc5e 10589
c19d1205 10590 case 'D':
4f3c3dbb 10591 {
c19d1205
ZW		 10592 long reg;
10593
10594 reg = given & 0x7;
10595 if (given & (1 << 7))
10596 reg += 8;
10597
10598 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 10599 }
c19d1205
ZW		 10600 break;
10601
10602 case 'N':
10603 if (given & (1 << 8))
10604 domasklr = 1;
10605 /* Fall through. */
10606 case 'O':
10607 if (*c == 'O' && (given & (1 << 8)))
10608 domaskpc = 1;
10609 /* Fall through. */
10610 case 'M':
10611 {
10612 int started = 0;
10613 int reg;
10614
10615 func (stream, "{");
10616
10617 /* It would be nice if we could spot
10618 ranges, and generate the rS-rE format: */
10619 for (reg = 0; (reg < 8); reg++)
10620 if ((given & (1 << reg)) != 0)
10621 {
10622 if (started)
10623 func (stream, ", ");
10624 started = 1;
10625 func (stream, "%s", arm_regnames[reg]);
10626 }
10627
10628 if (domasklr)
10629 {
10630 if (started)
10631 func (stream, ", ");
10632 started = 1;
d908c8af 10633 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 10634 }
10635
10636 if (domaskpc)
10637 {
10638 if (started)
10639 func (stream, ", ");
d908c8af 10640 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 10641 }
10642
10643 func (stream, "}");
10644 }
10645 break;
10646
4547cb56
NC		 10647 case 'W':
10648 /* Print writeback indicator for a LDMIA. We are doing a
10649 writeback if the base register is not in the register
10650 mask. */
10651 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10652 func (stream, "!");
dffaa15c 10653 break;
4547cb56 10654
c19d1205
ZW		 10655 case 'b':
10656 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10657 {
10658 bfd_vma address = (pc + 4
10659 + ((given & 0x00f8) >> 2)
10660 + ((given & 0x0200) >> 3));
10661 info->print_address_func (address, info);
1d67fe3b
TT		 10662
10663 /* Fill in instruction information. */
10664 info->insn_info_valid = 1;
10665 info->insn_type = dis_branch;
10666 info->target = address;
c19d1205
ZW		 10667 }
10668 break;
10669
10670 case 's':
10671 /* Right shift immediate -- bits 6..10; 1-31 print
10672 as themselves, 0 prints as 32. */
10673 {
10674 long imm = (given & 0x07c0) >> 6;
10675 if (imm == 0)
10676 imm = 32;
0fd3a477 10677 func (stream, "#%ld", imm);
c19d1205
ZW		 10678 }
10679 break;
10680
10681 case '0': case '1': case '2': case '3': case '4':
10682 case '5': case '6': case '7': case '8': case '9':
10683 {
10684 int bitstart = *c++ - '0';
10685 int bitend = 0;
10686
10687 while (*c >= '0' && *c <= '9')
10688 bitstart = (bitstart * 10) + *c++ - '0';
10689
10690 switch (*c)
10691 {
10692 case '-':
10693 {
f8b960bc 10694 bfd_vma reg;
c19d1205
ZW		 10695
10696 c++;
10697 while (*c >= '0' && *c <= '9')
10698 bitend = (bitend * 10) + *c++ - '0';
10699 if (!bitend)
10700 abort ();
10701 reg = given >> bitstart;
10702 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 10703
c19d1205
ZW		 10704 switch (*c)
10705 {
10706 case 'r':
10707 func (stream, "%s", arm_regnames[reg]);
10708 break;
10709
10710 case 'd':
d908c8af 10711 func (stream, "%ld", (long) reg);
05413229 10712 value_in_comment = reg;
c19d1205
ZW		 10713 break;
10714
10715 case 'H':
d908c8af 10716 func (stream, "%ld", (long) (reg << 1));
05413229 10717 value_in_comment = reg << 1;
c19d1205
ZW		 10718 break;
10719
10720 case 'W':
d908c8af 10721 func (stream, "%ld", (long) (reg << 2));
05413229 10722 value_in_comment = reg << 2;
c19d1205
ZW		 10723 break;
10724
10725 case 'a':
10726 /* PC-relative address -- the bottom two
10727 bits of the address are dropped
10728 before the calculation. */
10729 info->print_address_func
10730 (((pc + 4) & ~3) + (reg << 2), info);
05413229 10731 value_in_comment = 0;
c19d1205
ZW		 10732 break;
10733
10734 case 'x':
d908c8af 10735 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 10736 break;
10737
c19d1205
ZW		 10738 case 'B':
10739 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
1d67fe3b
TT		 10740 bfd_vma target = reg * 2 + pc + 4;
10741 info->print_address_func (target, info);
05413229 10742 value_in_comment = 0;
1d67fe3b
TT		 10743
10744 /* Fill in instruction information. */
10745 info->insn_info_valid = 1;
10746 info->insn_type = dis_branch;
10747 info->target = target;
c19d1205
ZW		 10748 break;
10749
10750 case 'c':
c22aaad1 10751 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 10752 break;
10753
10754 default:
10755 abort ();
10756 }
10757 }
10758 break;
10759
10760 case '\'':
10761 c++;
10762 if ((given & (1 << bitstart)) != 0)
10763 func (stream, "%c", *c);
10764 break;
10765
10766 case '?':
10767 ++c;
10768 if ((given & (1 << bitstart)) != 0)
10769 func (stream, "%c", *c++);
10770 else
10771 func (stream, "%c", *++c);
10772 break;
10773
10774 default:
10775 abort ();
10776 }
10777 }
10778 break;
10779
10780 default:
10781 abort ();
10782 }
10783 }
05413229
NC		 10784
10785 if (value_in_comment > 32 || value_in_comment < -16)
10786 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 10787 return;
c19d1205
ZW		 10788 }
10789
10790 /* No match. */
0b347048
TC		 10791 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
10792 return;
c19d1205
ZW		 10793}
10794
62b3e311 10795/* Return the name of an V7M special register. */
fe56b6ce 10796
62b3e311
PB		 10797static const char *
10798psr_name (int regno)
10799{
10800 switch (regno)
10801 {
1a336194
TP		 10802 case 0x0: return "APSR";
10803 case 0x1: return "IAPSR";
10804 case 0x2: return "EAPSR";
10805 case 0x3: return "PSR";
10806 case 0x5: return "IPSR";
10807 case 0x6: return "EPSR";
10808 case 0x7: return "IEPSR";
10809 case 0x8: return "MSP";
10810 case 0x9: return "PSP";
10811 case 0xa: return "MSPLIM";
10812 case 0xb: return "PSPLIM";
10813 case 0x10: return "PRIMASK";
10814 case 0x11: return "BASEPRI";
10815 case 0x12: return "BASEPRI_MAX";
10816 case 0x13: return "FAULTMASK";
10817 case 0x14: return "CONTROL";
16a1fa25
TP		 10818 case 0x88: return "MSP_NS";
10819 case 0x89: return "PSP_NS";
1a336194
TP		 10820 case 0x8a: return "MSPLIM_NS";
10821 case 0x8b: return "PSPLIM_NS";
10822 case 0x90: return "PRIMASK_NS";
10823 case 0x91: return "BASEPRI_NS";
10824 case 0x93: return "FAULTMASK_NS";
10825 case 0x94: return "CONTROL_NS";
10826 case 0x98: return "SP_NS";
62b3e311
PB		 10827 default: return "<unknown>";
10828 }
10829}
10830
4a5329c6
ZW		 10831/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10832
10833static void
10834print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 10835{
6b5d3a4d 10836 const struct opcode32 *insn;
c19d1205
ZW		 10837 void *stream = info->stream;
10838 fprintf_ftype func = info->fprintf_func;
73cd51e5 10839 bfd_boolean is_mve = is_mve_architecture (info);
c19d1205 10840
16980d0b
JB		 10841 if (print_insn_coprocessor (pc, info, given, TRUE))
10842 return;
10843
73cd51e5
AV		 10844 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
10845 return;
10846
10847 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 10848 return;
10849
4934a27c
MM		 10850 if (print_insn_cde (info, given, TRUE))
10851 return;
10852
33593eaf
MM		 10853 if (print_insn_generic_coprocessor (pc, info, given, TRUE))
10854 return;
10855
c19d1205
ZW		 10856 for (insn = thumb32_opcodes; insn->assembler; insn++)
10857 if ((given & insn->mask) == insn->value)
10858 {
4b5a202f 10859 bfd_boolean is_clrm = FALSE;
ff4a8d2b 10860 bfd_boolean is_unpredictable = FALSE;
05413229 10861 signed long value_in_comment = 0;
6b5d3a4d 10862 const char *c = insn->assembler;
05413229 10863
c19d1205
ZW		 10864 for (; *c; c++)
10865 {
10866 if (*c != '%')
10867 {
10868 func (stream, "%c", *c);
10869 continue;
10870 }
10871
10872 switch (*++c)
10873 {
10874 case '%':
10875 func (stream, "%%");
10876 break;
10877
c22aaad1
PB		 10878 case 'c':
10879 if (ifthen_state)
10880 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10881 break;
10882
10883 case 'x':
10884 if (ifthen_next_state)
10885 func (stream, "\t; unpredictable branch in IT block\n");
10886 break;
10887
10888 case 'X':
10889 if (ifthen_state)
10890 func (stream, "\t; unpredictable <IT:%s>",
10891 arm_conditional[IFTHEN_COND]);
10892 break;
10893
c19d1205
ZW		 10894 case 'I':
10895 {
10896 unsigned int imm12 = 0;
fe56b6ce 10897
c19d1205
ZW		 10898 imm12 |= (given & 0x000000ffu);
10899 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 10900 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 10901 func (stream, "#%u", imm12);
10902 value_in_comment = imm12;
c19d1205
ZW		 10903 }
10904 break;
10905
10906 case 'M':
10907 {
10908 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 10909
c19d1205
ZW		 10910 bits |= (given & 0x000000ffu);
10911 bits |= (given & 0x00007000u) >> 4;
10912 bits |= (given & 0x04000000u) >> 15;
10913 imm8 = (bits & 0x0ff);
10914 mod = (bits & 0xf00) >> 8;
10915 switch (mod)
10916 {
10917 case 0: imm = imm8; break;
c1e26897
NC		 10918 case 1: imm = ((imm8 << 16) | imm8); break;
10919 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10920 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 10921 default:
10922 mod = (bits & 0xf80) >> 7;
10923 imm8 = (bits & 0x07f) | 0x80;
10924 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10925 }
fe56b6ce
NC		 10926 func (stream, "#%u", imm);
10927 value_in_comment = imm;
c19d1205
ZW		 10928 }
10929 break;
43e65147 10930
c19d1205
ZW		 10931 case 'J':
10932 {
10933 unsigned int imm = 0;
fe56b6ce 10934
c19d1205
ZW		 10935 imm |= (given & 0x000000ffu);
10936 imm |= (given & 0x00007000u) >> 4;
10937 imm |= (given & 0x04000000u) >> 15;
10938 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 10939 func (stream, "#%u", imm);
10940 value_in_comment = imm;
c19d1205
ZW		 10941 }
10942 break;
10943
10944 case 'K':
10945 {
10946 unsigned int imm = 0;
fe56b6ce 10947
c19d1205
ZW		 10948 imm |= (given & 0x000f0000u) >> 16;
10949 imm |= (given & 0x00000ff0u) >> 0;
10950 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 10951 func (stream, "#%u", imm);
10952 value_in_comment = imm;
c19d1205
ZW		 10953 }
10954 break;
10955
74db7efb
NC		 10956 case 'H':
10957 {
10958 unsigned int imm = 0;
10959
10960 imm |= (given & 0x000f0000u) >> 4;
10961 imm |= (given & 0x00000fffu) >> 0;
10962 func (stream, "#%u", imm);
10963 value_in_comment = imm;
10964 }
10965 break;
10966
90ec0d68
MGD		 10967 case 'V':
10968 {
10969 unsigned int imm = 0;
10970
10971 imm |= (given & 0x00000fffu);
10972 imm |= (given & 0x000f0000u) >> 4;
10973 func (stream, "#%u", imm);
10974 value_in_comment = imm;
10975 }
10976 break;
10977
c19d1205
ZW		 10978 case 'S':
10979 {
10980 unsigned int reg = (given & 0x0000000fu);
10981 unsigned int stp = (given & 0x00000030u) >> 4;
10982 unsigned int imm = 0;
10983 imm |= (given & 0x000000c0u) >> 6;
10984 imm |= (given & 0x00007000u) >> 10;
10985
10986 func (stream, "%s", arm_regnames[reg]);
10987 switch (stp)
10988 {
10989 case 0:
10990 if (imm > 0)
10991 func (stream, ", lsl #%u", imm);
10992 break;
10993
10994 case 1:
10995 if (imm == 0)
10996 imm = 32;
10997 func (stream, ", lsr #%u", imm);
10998 break;
10999
11000 case 2:
11001 if (imm == 0)
11002 imm = 32;
11003 func (stream, ", asr #%u", imm);
11004 break;
11005
11006 case 3:
11007 if (imm == 0)
11008 func (stream, ", rrx");
11009 else
11010 func (stream, ", ror #%u", imm);
11011 }
11012 }
11013 break;
11014
11015 case 'a':
11016 {
11017 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 11018 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 11019 unsigned int op = (given & 0x00000f00) >> 8;
11020 unsigned int i12 = (given & 0x00000fff);
11021 unsigned int i8 = (given & 0x000000ff);
11022 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 11023 bfd_vma offset = 0;
c19d1205
ZW		 11024
11025 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 11026 if (U) /* 12-bit positive immediate offset. */
11027 {
11028 offset = i12;
11029 if (Rn != 15)
11030 value_in_comment = offset;
11031 }
11032 else if (Rn == 15) /* 12-bit negative immediate offset. */
11033 offset = - (int) i12;
11034 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 11035 {
11036 unsigned int Rm = (i8 & 0x0f);
11037 unsigned int sh = (i8 & 0x30) >> 4;
05413229 11038
c19d1205
ZW		 11039 func (stream, ", %s", arm_regnames[Rm]);
11040 if (sh)
11041 func (stream, ", lsl #%u", sh);
11042 func (stream, "]");
11043 break;
11044 }
11045 else switch (op)
11046 {
05413229 11047 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 11048 offset = i8;
11049 break;
11050
05413229 11051 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 11052 offset = -i8;
11053 break;
11054
05413229 11055 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 11056 offset = i8;
11057 writeback = TRUE;
11058 break;
11059
05413229 11060 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 11061 offset = -i8;
11062 writeback = TRUE;
11063 break;
11064
05413229 11065 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 11066 offset = i8;
11067 postind = TRUE;
11068 break;
11069
05413229 11070 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 11071 offset = -i8;
11072 postind = TRUE;
11073 break;
11074
11075 default:
11076 func (stream, ", <undefined>]");
11077 goto skip;
11078 }
11079
11080 if (postind)
d908c8af 11081 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 11082 else
11083 {
11084 if (offset)
d908c8af 11085 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 11086 func (stream, writeback ? "]!" : "]");
11087 }
11088
11089 if (Rn == 15)
11090 {
11091 func (stream, "\t; ");
11092 info->print_address_func (((pc + 4) & ~3) + offset, info);
11093 }
11094 }
11095 skip:
11096 break;
11097
11098 case 'A':
11099 {
c1e26897
NC		 11100 unsigned int U = ! NEGATIVE_BIT_SET;
11101 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 11102 unsigned int Rn = (given & 0x000f0000) >> 16;
11103 unsigned int off = (given & 0x000000ff);
11104
11105 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 11106
11107 if (PRE_BIT_SET)
c19d1205
ZW		 11108 {
11109 if (off || !U)
05413229
NC		 11110 {
11111 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 11112 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 11113 }
c19d1205
ZW		 11114 func (stream, "]");
11115 if (W)
11116 func (stream, "!");
11117 }
11118 else
11119 {
11120 func (stream, "], ");
11121 if (W)
05413229
NC		 11122 {
11123 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 11124 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 11125 }
c19d1205 11126 else
fe56b6ce
NC		 11127 {
11128 func (stream, "{%u}", off);
11129 value_in_comment = off;
11130 }
c19d1205
ZW		 11131 }
11132 }
11133 break;
11134
11135 case 'w':
11136 {
11137 unsigned int Sbit = (given & 0x01000000) >> 24;
11138 unsigned int type = (given & 0x00600000) >> 21;
05413229 11139
c19d1205
ZW		 11140 switch (type)
11141 {
11142 case 0: func (stream, Sbit ? "sb" : "b"); break;
11143 case 1: func (stream, Sbit ? "sh" : "h"); break;
11144 case 2:
11145 if (Sbit)
11146 func (stream, "??");
11147 break;
11148 case 3:
11149 func (stream, "??");
11150 break;
11151 }
11152 }
11153 break;
11154
4b5a202f
AV		 11155 case 'n':
11156 is_clrm = TRUE;
11157 /* Fall through. */
c19d1205
ZW		 11158 case 'm':
11159 {
11160 int started = 0;
11161 int reg;
11162
11163 func (stream, "{");
11164 for (reg = 0; reg < 16; reg++)
11165 if ((given & (1 << reg)) != 0)
11166 {
11167 if (started)
11168 func (stream, ", ");
11169 started = 1;
4b5a202f
AV		 11170 if (is_clrm && reg == 13)
11171 func (stream, "(invalid: %s)", arm_regnames[reg]);
11172 else if (is_clrm && reg == 15)
11173 func (stream, "%s", "APSR");
11174 else
11175 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 11176 }
11177 func (stream, "}");
11178 }
11179 break;
11180
11181 case 'E':
11182 {
11183 unsigned int msb = (given & 0x0000001f);
11184 unsigned int lsb = 0;
fe56b6ce 11185
c19d1205
ZW		 11186 lsb |= (given & 0x000000c0u) >> 6;
11187 lsb |= (given & 0x00007000u) >> 10;
11188 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
11189 }
11190 break;
11191
11192 case 'F':
11193 {
11194 unsigned int width = (given & 0x0000001f) + 1;
11195 unsigned int lsb = 0;
fe56b6ce 11196
c19d1205
ZW		 11197 lsb |= (given & 0x000000c0u) >> 6;
11198 lsb |= (given & 0x00007000u) >> 10;
11199 func (stream, "#%u, #%u", lsb, width);
11200 }
11201 break;
11202
e12437dc
AV		 11203 case 'G':
11204 {
11205 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
11206 func (stream, "%x", boff);
11207 }
11208 break;
11209
e5d6e09e
AV		 11210 case 'W':
11211 {
11212 unsigned int immA = (given & 0x001f0000u) >> 16;
11213 unsigned int immB = (given & 0x000007feu) >> 1;
11214 unsigned int immC = (given & 0x00000800u) >> 11;
11215 bfd_vma offset = 0;
11216
11217 offset |= immA << 12;
11218 offset |= immB << 2;
11219 offset |= immC << 1;
11220 /* Sign extend. */
11221 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
11222
11223 info->print_address_func (pc + 4 + offset, info);
11224 }
11225 break;
11226
1caf72a5
AV		 11227 case 'Y':
11228 {
11229 unsigned int immA = (given & 0x007f0000u) >> 16;
11230 unsigned int immB = (given & 0x000007feu) >> 1;
11231 unsigned int immC = (given & 0x00000800u) >> 11;
11232 bfd_vma offset = 0;
11233
11234 offset |= immA << 12;
11235 offset |= immB << 2;
11236 offset |= immC << 1;
11237 /* Sign extend. */
11238 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
11239
11240 info->print_address_func (pc + 4 + offset, info);
11241 }
11242 break;
11243
1889da70
AV		 11244 case 'Z':
11245 {
11246 unsigned int immA = (given & 0x00010000u) >> 16;
11247 unsigned int immB = (given & 0x000007feu) >> 1;
11248 unsigned int immC = (given & 0x00000800u) >> 11;
11249 bfd_vma offset = 0;
11250
11251 offset |= immA << 12;
11252 offset |= immB << 2;
11253 offset |= immC << 1;
11254 /* Sign extend. */
11255 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
11256
11257 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 11258
11259 unsigned int T = (given & 0x00020000u) >> 17;
11260 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
11261 unsigned int boffset = (T == 1) ? 4 : 2;
11262 func (stream, ", ");
11263 func (stream, "%x", endoffset + boffset);
1889da70
AV		 11264 }
11265 break;
11266
60f993ce
AV		 11267 case 'Q':
11268 {
11269 unsigned int immh = (given & 0x000007feu) >> 1;
11270 unsigned int imml = (given & 0x00000800u) >> 11;
11271 bfd_vma imm32 = 0;
11272
11273 imm32 |= immh << 2;
11274 imm32 |= imml << 1;
11275
11276 info->print_address_func (pc + 4 + imm32, info);
11277 }
11278 break;
11279
11280 case 'P':
11281 {
11282 unsigned int immh = (given & 0x000007feu) >> 1;
11283 unsigned int imml = (given & 0x00000800u) >> 11;
11284 bfd_vma imm32 = 0;
11285
11286 imm32 |= immh << 2;
11287 imm32 |= imml << 1;
11288
11289 info->print_address_func (pc + 4 - imm32, info);
11290 }
11291 break;
11292
c19d1205
ZW		 11293 case 'b':
11294 {
11295 unsigned int S = (given & 0x04000000u) >> 26;
11296 unsigned int J1 = (given & 0x00002000u) >> 13;
11297 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 11298 bfd_vma offset = 0;
c19d1205
ZW		 11299
11300 offset |= !S << 20;
11301 offset |= J2 << 19;
11302 offset |= J1 << 18;
11303 offset |= (given & 0x003f0000) >> 4;
11304 offset |= (given & 0x000007ff) << 1;
11305 offset -= (1 << 20);
11306
1d67fe3b
TT		 11307 bfd_vma target = pc + 4 + offset;
11308 info->print_address_func (target, info);
11309
11310 /* Fill in instruction information. */
11311 info->insn_info_valid = 1;
11312 info->insn_type = dis_branch;
11313 info->target = target;
c19d1205
ZW		 11314 }
11315 break;
11316
11317 case 'B':
11318 {
11319 unsigned int S = (given & 0x04000000u) >> 26;
11320 unsigned int I1 = (given & 0x00002000u) >> 13;
11321 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 11322 bfd_vma offset = 0;
c19d1205
ZW		 11323
11324 offset |= !S << 24;
11325 offset |= !(I1 ^ S) << 23;
11326 offset |= !(I2 ^ S) << 22;
11327 offset |= (given & 0x03ff0000u) >> 4;
11328 offset |= (given & 0x000007ffu) << 1;
11329 offset -= (1 << 24);
36b0c57d 11330 offset += pc + 4;
c19d1205 11331
36b0c57d
PB		 11332 /* BLX target addresses are always word aligned. */
11333 if ((given & 0x00001000u) == 0)
11334 offset &= ~2u;
11335
11336 info->print_address_func (offset, info);
1d67fe3b
TT		 11337
11338 /* Fill in instruction information. */
11339 info->insn_info_valid = 1;
11340 info->insn_type = dis_branch;
11341 info->target = offset;
c19d1205
ZW		 11342 }
11343 break;
11344
11345 case 's':
11346 {
11347 unsigned int shift = 0;
fe56b6ce 11348
c19d1205
ZW		 11349 shift |= (given & 0x000000c0u) >> 6;
11350 shift |= (given & 0x00007000u) >> 10;
c1e26897 11351 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 11352 func (stream, ", asr #%u", shift);
11353 else if (shift)
11354 func (stream, ", lsl #%u", shift);
11355 /* else print nothing - lsl #0 */
11356 }
11357 break;
11358
11359 case 'R':
11360 {
11361 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 11362
c19d1205
ZW		 11363 if (rot)
11364 func (stream, ", ror #%u", rot * 8);
11365 }
11366 break;
11367
62b3e311 11368 case 'U':
43e65147 11369 if ((given & 0xf0) == 0x60)
62b3e311 11370 {
52e7f43d
RE		 11371 switch (given & 0xf)
11372 {
11373 case 0xf: func (stream, "sy"); break;
11374 default:
11375 func (stream, "#%d", (int) given & 0xf);
11376 break;
11377 }
62b3e311 11378 }
43e65147 11379 else
52e7f43d 11380 {
e797f7e0
MGD		 11381 const char * opt = data_barrier_option (given & 0xf);
11382 if (opt != NULL)
11383 func (stream, "%s", opt);
11384 else
11385 func (stream, "#%d", (int) given & 0xf);
52e7f43d 11386 }
62b3e311
PB		 11387 break;
11388
11389 case 'C':
11390 if ((given & 0xff) == 0)
11391 {
11392 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
11393 if (given & 0x800)
11394 func (stream, "f");
11395 if (given & 0x400)
11396 func (stream, "s");
11397 if (given & 0x200)
11398 func (stream, "x");
11399 if (given & 0x100)
11400 func (stream, "c");
11401 }
90ec0d68
MGD		 11402 else if ((given & 0x20) == 0x20)
11403 {
11404 char const* name;
11405 unsigned sysm = (given & 0xf00) >> 8;
11406
11407 sysm |= (given & 0x30);
11408 sysm |= (given & 0x00100000) >> 14;
11409 name = banked_regname (sysm);
43e65147 11410
90ec0d68
MGD		 11411 if (name != NULL)
11412 func (stream, "%s", name);
11413 else
d908c8af 11414 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 11415 }
62b3e311
PB		 11416 else
11417 {
d908c8af 11418 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11419 }
11420 break;
11421
11422 case 'D':
90ec0d68
MGD		 11423 if (((given & 0xff) == 0)
11424 || ((given & 0x20) == 0x20))
11425 {
11426 char const* name;
11427 unsigned sm = (given & 0xf0000) >> 16;
11428
11429 sm |= (given & 0x30);
11430 sm |= (given & 0x00100000) >> 14;
11431 name = banked_regname (sm);
11432
11433 if (name != NULL)
11434 func (stream, "%s", name);
11435 else
d908c8af 11436 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 11437 }
62b3e311 11438 else
d908c8af 11439 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11440 break;
11441
c19d1205
ZW		 11442 case '0': case '1': case '2': case '3': case '4':
11443 case '5': case '6': case '7': case '8': case '9':
11444 {
16980d0b
JB		 11445 int width;
11446 unsigned long val;
c19d1205 11447
16980d0b 11448 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 11449
c19d1205
ZW		 11450 switch (*c)
11451 {
d052b9b7
AV		 11452 case 's':
11453 if (val <= 3)
11454 func (stream, "%s", mve_vec_sizename[val]);
11455 else
11456 func (stream, "<undef size>");
11457 break;
11458
05413229
NC		 11459 case 'd':
11460 func (stream, "%lu", val);
11461 value_in_comment = val;
11462 break;
ff4a8d2b 11463
f0fba320
RL		 11464 case 'D':
11465 func (stream, "%lu", val + 1);
11466 value_in_comment = val + 1;
11467 break;
11468
05413229
NC		 11469 case 'W':
11470 func (stream, "%lu", val * 4);
11471 value_in_comment = val * 4;
11472 break;
ff4a8d2b 11473
f1c7f421
AV		 11474 case 'S':
11475 if (val == 13)
11476 is_unpredictable = TRUE;
11477 /* Fall through. */
ff4a8d2b
NC		 11478 case 'R':
11479 if (val == 15)
11480 is_unpredictable = TRUE;
11481 /* Fall through. */
11482 case 'r':
11483 func (stream, "%s", arm_regnames[val]);
11484 break;
c19d1205
ZW		 11485
11486 case 'c':
c22aaad1 11487 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 11488 break;
11489
11490 case '\'':
c19d1205 11491 c++;
16980d0b
JB		 11492 if (val == ((1ul << width) - 1))
11493 func (stream, "%c", *c);
c19d1205 11494 break;
43e65147 11495
c19d1205 11496 case '`':
c19d1205 11497 c++;
16980d0b
JB		 11498 if (val == 0)
11499 func (stream, "%c", *c);
c19d1205
ZW		 11500 break;
11501
11502 case '?':
fe56b6ce 11503 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 11504 c += 1 << width;
c19d1205 11505 break;
43e65147 11506
0bb027fd
RR		 11507 case 'x':
11508 func (stream, "0x%lx", val & 0xffffffffUL);
11509 break;
c19d1205
ZW		 11510
11511 default:
11512 abort ();
11513 }
11514 }
11515 break;
11516
32a94698
NC		 11517 case 'L':
11518 /* PR binutils/12534
11519 If we have a PC relative offset in an LDRD or STRD
11520 instructions then display the decoded address. */
11521 if (((given >> 16) & 0xf) == 0xf)
11522 {
11523 bfd_vma offset = (given & 0xff) * 4;
11524
11525 if ((given & (1 << 23)) == 0)
11526 offset = - offset;
11527 func (stream, "\t; ");
11528 info->print_address_func ((pc & ~3) + 4 + offset, info);
11529 }
11530 break;
11531
c19d1205
ZW		 11532 default:
11533 abort ();
11534 }
11535 }
05413229
NC		 11536
11537 if (value_in_comment > 32 || value_in_comment < -16)
11538 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 11539
11540 if (is_unpredictable)
11541 func (stream, UNPREDICTABLE_INSTRUCTION);
11542
4a5329c6 11543 return;
c19d1205 11544 }
252b5132 11545
58efb6c0 11546 /* No match. */
0b347048
TC		 11547 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
11548 return;
252b5132
RH		 11549}
11550
e821645d
DJ		 11551/* Print data bytes on INFO->STREAM. */
11552
11553static void
fe56b6ce
NC		 11554print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11555 struct disassemble_info *info,
e821645d
DJ		 11556 long given)
11557{
11558 switch (info->bytes_per_chunk)
11559 {
11560 case 1:
11561 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
11562 break;
11563 case 2:
11564 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
11565 break;
11566 case 4:
11567 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
11568 break;
11569 default:
11570 abort ();
11571 }
11572}
11573
22a398e1 11574/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 11575 being displayed in symbol relative addresses.
11576
11577 Also disallow private symbol, with __tagsym$$ prefix,
11578 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 11579
11580bfd_boolean
11581arm_symbol_is_valid (asymbol * sym,
11582 struct disassemble_info * info ATTRIBUTE_UNUSED)
11583{
11584 const char * name;
43e65147 11585
22a398e1
NC		 11586 if (sym == NULL)
11587 return FALSE;
11588
11589 name = bfd_asymbol_name (sym);
11590
d8282f0e 11591 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 11592}
11593
65b48a81 11594/* Parse the string of disassembler options. */
baf0cc5e 11595
65b48a81 11596static void
f995bbe8 11597parse_arm_disassembler_options (const char *options)
dd92f639 11598{
f995bbe8 11599 const char *opt;
b34976b6 11600
65b48a81 11601 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 11602 {
65b48a81
PB		 11603 if (CONST_STRNEQ (opt, "reg-names-"))
11604 {
11605 unsigned int i;
11606 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11607 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
11608 {
11609 regname_selected = i;
11610 break;
11611 }
b34976b6 11612
65b48a81 11613 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 11614 /* xgettext: c-format */
11615 opcodes_error_handler (_("unrecognised register name set: %s"),
11616 opt);
65b48a81
PB		 11617 }
11618 else if (CONST_STRNEQ (opt, "force-thumb"))
11619 force_thumb = 1;
11620 else if (CONST_STRNEQ (opt, "no-force-thumb"))
11621 force_thumb = 0;
4934a27c
MM		 11622 else if (CONST_STRNEQ (opt, "coproc"))
11623 {
11624 const char *procptr = opt + sizeof ("coproc") - 1;
11625 char *endptr;
11626 uint8_t coproc_number = strtol (procptr, &endptr, 10);
11627 if (endptr != procptr + 1 || coproc_number > 7)
11628 {
11629 opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
11630 opt);
11631 continue;
11632 }
11633 if (*endptr != '=')
11634 {
11635 opcodes_error_handler (_("coproc must have an argument: %s"),
11636 opt);
11637 continue;
11638 }
11639 endptr += 1;
11640 if (CONST_STRNEQ (endptr, "generic"))
11641 cde_coprocs &= ~(1 << coproc_number);
11642 else if (CONST_STRNEQ (endptr, "cde")
11643 || CONST_STRNEQ (endptr, "CDE"))
11644 cde_coprocs |= (1 << coproc_number);
11645 else
11646 {
11647 opcodes_error_handler (
11648 _("coprocN argument takes options \"generic\","
11649 " \"cde\", or \"CDE\": %s"), opt);
11650 }
11651 }
65b48a81 11652 else
a6743a54
AM		 11653 /* xgettext: c-format */
11654 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 11655 }
b34976b6 11656
dd92f639
NC		 11657 return;
11658}
11659
5bc5ae88
RL		 11660static bfd_boolean
11661mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11662 enum map_type *map_symbol);
11663
c22aaad1
PB		 11664/* Search back through the insn stream to determine if this instruction is
11665 conditionally executed. */
fe56b6ce 11666
c22aaad1 11667static void
fe56b6ce
NC		 11668find_ifthen_state (bfd_vma pc,
11669 struct disassemble_info *info,
c22aaad1
PB		 11670 bfd_boolean little)
11671{
11672 unsigned char b[2];
11673 unsigned int insn;
11674 int status;
11675 /* COUNT is twice the number of instructions seen. It will be odd if we
11676 just crossed an instruction boundary. */
11677 int count;
11678 int it_count;
11679 unsigned int seen_it;
11680 bfd_vma addr;
11681
11682 ifthen_address = pc;
11683 ifthen_state = 0;
11684
11685 addr = pc;
11686 count = 1;
11687 it_count = 0;
11688 seen_it = 0;
11689 /* Scan backwards looking for IT instructions, keeping track of where
11690 instruction boundaries are. We don't know if something is actually an
11691 IT instruction until we find a definite instruction boundary. */
11692 for (;;)
11693 {
fe56b6ce 11694 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 11695 {
11696 /* A symbol must be on an instruction boundary, and will not
11697 be within an IT block. */
11698 if (seen_it && (count & 1))
11699 break;
11700
11701 return;
11702 }
11703 addr -= 2;
fe56b6ce 11704 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 11705 if (status)
11706 return;
11707
11708 if (little)
11709 insn = (b[0]) | (b[1] << 8);
11710 else
11711 insn = (b[1]) | (b[0] << 8);
11712 if (seen_it)
11713 {
11714 if ((insn & 0xf800) < 0xe800)
11715 {
11716 /* Addr + 2 is an instruction boundary. See if this matches
11717 the expected boundary based on the position of the last
11718 IT candidate. */
11719 if (count & 1)
11720 break;
11721 seen_it = 0;
11722 }
11723 }
11724 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
11725 {
5bc5ae88
RL		 11726 enum map_type type = MAP_ARM;
11727 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
11728
11729 if (!found || (found && type == MAP_THUMB))
11730 {
11731 /* This could be an IT instruction. */
11732 seen_it = insn;
11733 it_count = count >> 1;
11734 }
c22aaad1
PB		 11735 }
11736 if ((insn & 0xf800) >= 0xe800)
11737 count++;
11738 else
11739 count = (count + 2) | 1;
11740 /* IT blocks contain at most 4 instructions. */
11741 if (count >= 8 && !seen_it)
11742 return;
11743 }
11744 /* We found an IT instruction. */
11745 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
11746 if ((ifthen_state & 0xf) == 0)
11747 ifthen_state = 0;
11748}
11749
b0e28b39
DJ		 11750/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11751 mapping symbol. */
11752
11753static int
11754is_mapping_symbol (struct disassemble_info *info, int n,
11755 enum map_type *map_type)
11756{
11757 const char *name;
11758
11759 name = bfd_asymbol_name (info->symtab[n]);
11760 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
11761 && (name[2] == 0 || name[2] == '.'))
11762 {
11763 *map_type = ((name[1] == 'a') ? MAP_ARM
11764 : (name[1] == 't') ? MAP_THUMB
11765 : MAP_DATA);
11766 return TRUE;
11767 }
11768
11769 return FALSE;
11770}
11771
11772/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11773 Returns nonzero if *MAP_TYPE was set. */
11774
11775static int
11776get_map_sym_type (struct disassemble_info *info,
11777 int n,
11778 enum map_type *map_type)
11779{
11780 /* If the symbol is in a different section, ignore it. */
11781 if (info->section != NULL && info->section != info->symtab[n]->section)
11782 return FALSE;
11783
11784 return is_mapping_symbol (info, n, map_type);
11785}
11786
11787/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 11788 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 11789
11790static int
fe56b6ce
NC		 11791get_sym_code_type (struct disassemble_info *info,
11792 int n,
e821645d 11793 enum map_type *map_type)
2087ad84
PB		 11794{
11795 elf_symbol_type *es;
11796 unsigned int type;
b0e28b39
DJ		 11797
11798 /* If the symbol is in a different section, ignore it. */
11799 if (info->section != NULL && info->section != info->symtab[n]->section)
11800 return FALSE;
2087ad84 11801
e821645d 11802 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 11803 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11804
11805 /* If the symbol has function type then use that. */
34e77a92 11806 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 11807 {
39d911fc
TP		 11808 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11809 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 11810 *map_type = MAP_THUMB;
11811 else
11812 *map_type = MAP_ARM;
2087ad84
PB		 11813 return TRUE;
11814 }
11815
2087ad84
PB		 11816 return FALSE;
11817}
11818
5bc5ae88
RL		 11819/* Search the mapping symbol state for instruction at pc. This is only
11820 applicable for elf target.
11821
11822 There is an assumption Here, info->private_data contains the correct AND
11823 up-to-date information about current scan process. The information will be
11824 used to speed this search process.
11825
11826 Return TRUE if the mapping state can be determined, and map_symbol
11827 will be updated accordingly. Otherwise, return FALSE. */
11828
11829static bfd_boolean
11830mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11831 enum map_type *map_symbol)
11832{
796d6298
TC		 11833 bfd_vma addr, section_vma = 0;
11834 int n, last_sym = -1;
5bc5ae88 11835 bfd_boolean found = FALSE;
796d6298
TC		 11836 bfd_boolean can_use_search_opt_p = FALSE;
11837
11838 /* Default to DATA. A text section is required by the ABI to contain an
11839 INSN mapping symbol at the start. A data section has no such
11840 requirement, hence if no mapping symbol is found the section must
11841 contain only data. This however isn't very useful if the user has
11842 fully stripped the binaries. If this is the case use the section
11843 attributes to determine the default. If we have no section default to
11844 INSN as well, as we may be disassembling some raw bytes on a baremetal
11845 HEX file or similar. */
11846 enum map_type type = MAP_DATA;
11847 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
11848 type = MAP_ARM;
5bc5ae88
RL		 11849 struct arm_private_data *private_data;
11850
796d6298 11851 if (info->private_data == NULL
5bc5ae88
RL		 11852 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
11853 return FALSE;
11854
11855 private_data = info->private_data;
5bc5ae88 11856
796d6298
TC		 11857 /* First, look for mapping symbols. */
11858 if (info->symtab_size != 0)
11859 {
11860 if (pc <= private_data->last_mapping_addr)
11861 private_data->last_mapping_sym = -1;
11862
11863 /* Start scanning at the start of the function, or wherever
11864 we finished last time. */
11865 n = info->symtab_pos + 1;
11866
11867 /* If the last stop offset is different from the current one it means we
11868 are disassembling a different glob of bytes. As such the optimization
11869 would not be safe and we should start over. */
11870 can_use_search_opt_p
11871 = private_data->last_mapping_sym >= 0
11872 && info->stop_offset == private_data->last_stop_offset;
11873
11874 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11875 n = private_data->last_mapping_sym;
11876
11877 /* Look down while we haven't passed the location being disassembled.
11878 The reason for this is that there's no defined order between a symbol
11879 and an mapping symbol that may be at the same address. We may have to
11880 look at least one position ahead. */
11881 for (; n < info->symtab_size; n++)
11882 {
11883 addr = bfd_asymbol_value (info->symtab[n]);
11884 if (addr > pc)
11885 break;
11886 if (get_map_sym_type (info, n, &type))
11887 {
11888 last_sym = n;
11889 found = TRUE;
11890 }
11891 }
5bc5ae88 11892
796d6298
TC		 11893 if (!found)
11894 {
11895 n = info->symtab_pos;
11896 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11897 n = private_data->last_mapping_sym;
11898
11899 /* No mapping symbol found at this address. Look backwards
11900 for a preceeding one, but don't go pass the section start
11901 otherwise a data section with no mapping symbol can pick up
11902 a text mapping symbol of a preceeding section. The documentation
11903 says section can be NULL, in which case we will seek up all the
11904 way to the top. */
11905 if (info->section)
11906 section_vma = info->section->vma;
11907
11908 for (; n >= 0; n--)
11909 {
11910 addr = bfd_asymbol_value (info->symtab[n]);
11911 if (addr < section_vma)
11912 break;
11913
11914 if (get_map_sym_type (info, n, &type))
11915 {
11916 last_sym = n;
11917 found = TRUE;
11918 break;
11919 }
11920 }
11921 }
11922 }
11923
11924 /* If no mapping symbol was found, try looking up without a mapping
11925 symbol. This is done by walking up from the current PC to the nearest
11926 symbol. We don't actually have to loop here since symtab_pos will
11927 contain the nearest symbol already. */
11928 if (!found)
5bc5ae88 11929 {
796d6298
TC		 11930 n = info->symtab_pos;
11931 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 11932 {
796d6298
TC		 11933 last_sym = n;
11934 found = TRUE;
5bc5ae88
RL		 11935 }
11936 }
11937
796d6298
TC		 11938 private_data->last_mapping_sym = last_sym;
11939 private_data->last_type = type;
11940 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 11941
11942 *map_symbol = type;
11943 return found;
11944}
11945
0313a2b8
NC		 11946/* Given a bfd_mach_arm_XXX value, this function fills in the fields
11947 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 11948 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 11949
11950 FIXME: This could more efficiently implemented as a constant array,
11951 although it would also be less robust. */
11952
11953static void
11954select_arm_features (unsigned long mach,
11955 arm_feature_set * features)
11956{
c0c468d5
TP		 11957 arm_feature_set arch_fset;
11958 const arm_feature_set fpu_any = FPU_ANY;
11959
1af1dd51
MW		 11960#undef ARM_SET_FEATURES
11961#define ARM_SET_FEATURES(FSET) \
11962 { \
11963 const arm_feature_set fset = FSET; \
c0c468d5 11964 arch_fset = fset; \
1af1dd51 11965 }
823d2571 11966
c0c468d5
TP		 11967 /* When several architecture versions share the same bfd_mach_arm_XXX value
11968 the most featureful is chosen. */
0313a2b8
NC		 11969 switch (mach)
11970 {
c0c468d5
TP		 11971 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
11972 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11973 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
11974 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11975 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
11976 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11977 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
11978 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11979 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11980 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 11981 case bfd_mach_arm_ep9312:
c0c468d5
TP		 11982 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11983 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 11984 break;
c0c468d5
TP		 11985 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11986 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
11987 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
11988 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
11989 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
11990 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
11991 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
11992 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
11993 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
11994 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
11995 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
11996 case bfd_mach_arm_8:
11997 {
aab2c27d
MM		 11998 /* Add bits for extensions that Armv8.6-A recognizes. */
11999 arm_feature_set armv8_6_ext_fset
0632eeea 12000 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
aab2c27d
MM		 12001 ARM_SET_FEATURES (ARM_ARCH_V8_6A);
12002 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
c0c468d5
TP		 12003 break;
12004 }
12005 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
12006 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
12007 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 12008 case bfd_mach_arm_8_1M_MAIN:
12009 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
2da2eaf4
AV		 12010 arm_feature_set mve_all
12011 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP);
12012 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
73cd51e5
AV		 12013 force_thumb = 1;
12014 break;
c0c468d5 12015 /* If the machine type is unknown allow all architecture types and all
2da2eaf4
AV		 12016 extensions, with the exception of MVE as that clashes with NEON. */
12017 case bfd_mach_arm_unknown:
12018 ARM_SET_FEATURES (ARM_FEATURE (-1,
12019 -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP),
12020 -1));
12021 break;
0313a2b8
NC		 12022 default:
12023 abort ();
12024 }
1af1dd51 12025#undef ARM_SET_FEATURES
c0c468d5
TP		 12026
12027 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
12028 and thus on bfd_mach_arm_XXX value. Therefore for a given
12029 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
12030 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 12031}
12032
12033
58efb6c0
NC		 12034/* NOTE: There are no checks in these routines that
12035 the relevant number of data bytes exist. */
baf0cc5e 12036
58efb6c0 12037static int
4a5329c6 12038print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 12039{
c19d1205 12040 unsigned char b[4];
2480b6fa 12041 unsigned long given;
c19d1205 12042 int status;
e821645d 12043 int is_thumb = FALSE;
b0e28b39 12044 int is_data = FALSE;
bd2e2557 12045 int little_code;
e821645d 12046 unsigned int size = 4;
4a5329c6 12047 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 12048 bfd_boolean found = FALSE;
b0e28b39 12049 struct arm_private_data *private_data;
58efb6c0 12050
1d67fe3b
TT		 12051 /* Clear instruction information field. */
12052 info->insn_info_valid = 0;
12053 info->branch_delay_insns = 0;
12054 info->data_size = 0;
12055 info->insn_type = dis_noninsn;
12056 info->target = 0;
12057 info->target2 = 0;
12058
dd92f639
NC		 12059 if (info->disassembler_options)
12060 {
65b48a81 12061 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 12062
58efb6c0 12063 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 12064 info->disassembler_options = NULL;
12065 }
b34976b6 12066
0313a2b8
NC		 12067 /* PR 10288: Control which instructions will be disassembled. */
12068 if (info->private_data == NULL)
12069 {
b0e28b39 12070 static struct arm_private_data private;
0313a2b8
NC		 12071
12072 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
12073 /* If the user did not use the -m command line switch then default to
12074 disassembling all types of ARM instruction.
43e65147 12075
0313a2b8
NC		 12076 The info->mach value has to be ignored as this will be based on
12077 the default archictecture for the target and/or hints in the notes
12078 section, but it will never be greater than the current largest arm
12079 machine value (iWMMXt2), which is only equivalent to the V5TE
12080 architecture. ARM architectures have advanced beyond the machine
12081 value encoding, and these newer architectures would be ignored if
12082 the machine value was used.
12083
12084 Ie the -m switch is used to restrict which instructions will be
12085 disassembled. If it is necessary to use the -m switch to tell
12086 objdump that an ARM binary is being disassembled, eg because the
12087 input is a raw binary file, but it is also desired to disassemble
12088 all ARM instructions then use "-marm". This will select the
12089 "unknown" arm architecture which is compatible with any ARM
12090 instruction. */
12091 info->mach = bfd_mach_arm_unknown;
12092
12093 /* Compute the architecture bitmask from the machine number.
12094 Note: This assumes that the machine number will not change
12095 during disassembly.... */
b0e28b39 12096 select_arm_features (info->mach, & private.features);
0313a2b8 12097
1fbaefec
PB		 12098 private.last_mapping_sym = -1;
12099 private.last_mapping_addr = 0;
796d6298 12100 private.last_stop_offset = 0;
b0e28b39
DJ		 12101
12102 info->private_data = & private;
0313a2b8 12103 }
b0e28b39
DJ		 12104
12105 private_data = info->private_data;
12106
bd2e2557
SS		 12107 /* Decide if our code is going to be little-endian, despite what the
12108 function argument might say. */
12109 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
12110
b0e28b39
DJ		 12111 /* For ELF, consult the symbol table to determine what kind of code
12112 or data we have. */
8977d4b2 12113 if (info->symtab_size != 0
e821645d
DJ		 12114 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
12115 {
12116 bfd_vma addr;
796d6298 12117 int n;
e821645d 12118 int last_sym = -1;
b0e28b39 12119 enum map_type type = MAP_ARM;
e821645d 12120
796d6298
TC		 12121 found = mapping_symbol_for_insn (pc, info, &type);
12122 last_sym = private_data->last_mapping_sym;
e821645d 12123
1fbaefec
PB		 12124 is_thumb = (private_data->last_type == MAP_THUMB);
12125 is_data = (private_data->last_type == MAP_DATA);
b34976b6 12126
e821645d
DJ		 12127 /* Look a little bit ahead to see if we should print out
12128 two or four bytes of data. If there's a symbol,
12129 mapping or otherwise, after two bytes then don't
12130 print more. */
12131 if (is_data)
12132 {
12133 size = 4 - (pc & 3);
12134 for (n = last_sym + 1; n < info->symtab_size; n++)
12135 {
12136 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 12137 if (addr > pc
12138 && (info->section == NULL
12139 || info->section == info->symtab[n]->section))
e821645d
DJ		 12140 {
12141 if (addr - pc < size)
12142 size = addr - pc;
12143 break;
12144 }
12145 }
12146 /* If the next symbol is after three bytes, we need to
12147 print only part of the data, so that we can use either
12148 .byte or .short. */
12149 if (size == 3)
12150 size = (pc & 1) ? 1 : 2;
12151 }
12152 }
12153
12154 if (info->symbols != NULL)
252b5132 12155 {
5876e06d
NC		 12156 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
12157 {
2f0ca46a 12158 coff_symbol_type * cs;
b34976b6 12159
5876e06d
NC		 12160 cs = coffsymbol (*info->symbols);
12161 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
12162 || cs->native->u.syment.n_sclass == C_THUMBSTAT
12163 || cs->native->u.syment.n_sclass == C_THUMBLABEL
12164 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
12165 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
12166 }
e821645d
DJ		 12167 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
12168 && !found)
5876e06d 12169 {
2087ad84
PB		 12170 /* If no mapping symbol has been found then fall back to the type
12171 of the function symbol. */
e821645d
DJ		 12172 elf_symbol_type * es;
12173 unsigned int type;
2087ad84 12174
e821645d
DJ		 12175 es = *(elf_symbol_type **)(info->symbols);
12176 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 12177
39d911fc
TP		 12178 is_thumb =
12179 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12180 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 12181 }
e49d43ff
TG		 12182 else if (bfd_asymbol_flavour (*info->symbols)
12183 == bfd_target_mach_o_flavour)
12184 {
12185 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
12186
12187 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
12188 }
5876e06d 12189 }
b34976b6 12190
e821645d
DJ		 12191 if (force_thumb)
12192 is_thumb = TRUE;
12193
b8f9ee44
CL		 12194 if (is_data)
12195 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12196 else
12197 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12198
c19d1205 12199 info->bytes_per_line = 4;
252b5132 12200
1316c8b3
NC		 12201 /* PR 10263: Disassemble data if requested to do so by the user. */
12202 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 12203 {
12204 int i;
12205
1316c8b3 12206 /* Size was already set above. */
e821645d
DJ		 12207 info->bytes_per_chunk = size;
12208 printer = print_insn_data;
12209
fe56b6ce 12210 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 12211 given = 0;
12212 if (little)
12213 for (i = size - 1; i >= 0; i--)
12214 given = b[i] | (given << 8);
12215 else
12216 for (i = 0; i < (int) size; i++)
12217 given = b[i] | (given << 8);
12218 }
12219 else if (!is_thumb)
252b5132 12220 {
c19d1205
ZW		 12221 /* In ARM mode endianness is a straightforward issue: the instruction
12222 is four bytes long and is either ordered 0123 or 3210. */
12223 printer = print_insn_arm;
12224 info->bytes_per_chunk = 4;
4a5329c6 12225 size = 4;
c19d1205 12226
0313a2b8 12227 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 12228 if (little_code)
2480b6fa 12229 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
c19d1205 12230 else
2480b6fa 12231 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
252b5132 12232 }
58efb6c0 12233 else
252b5132 12234 {
c19d1205
ZW		 12235 /* In Thumb mode we have the additional wrinkle of two
12236 instruction lengths. Fortunately, the bits that determine
12237 the length of the current instruction are always to be found
12238 in the first two bytes. */
4a5329c6 12239 printer = print_insn_thumb16;
c19d1205 12240 info->bytes_per_chunk = 2;
4a5329c6
ZW		 12241 size = 2;
12242
fe56b6ce 12243 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 12244 if (little_code)
9a2ff3f5
AM		 12245 given = (b[0]) | (b[1] << 8);
12246 else
12247 given = (b[1]) | (b[0] << 8);
12248
c19d1205 12249 if (!status)
252b5132 12250 {
c19d1205
ZW		 12251 /* These bit patterns signal a four-byte Thumb
12252 instruction. */
12253 if ((given & 0xF800) == 0xF800
12254 || (given & 0xF800) == 0xF000
12255 || (given & 0xF800) == 0xE800)
252b5132 12256 {
0313a2b8 12257 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 12258 if (little_code)
c19d1205 12259 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 12260 else
c19d1205
ZW		 12261 given = (b[1]) | (b[0] << 8) | (given << 16);
12262
12263 printer = print_insn_thumb32;
4a5329c6 12264 size = 4;
252b5132 12265 }
252b5132 12266 }
c22aaad1
PB		 12267
12268 if (ifthen_address != pc)
0313a2b8 12269 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 12270
12271 if (ifthen_state)
12272 {
12273 if ((ifthen_state & 0xf) == 0x8)
12274 ifthen_next_state = 0;
12275 else
12276 ifthen_next_state = (ifthen_state & 0xe0)
12277 | ((ifthen_state & 0xf) << 1);
12278 }
252b5132 12279 }
b34976b6 12280
c19d1205
ZW		 12281 if (status)
12282 {
12283 info->memory_error_func (status, pc, info);
12284 return -1;
12285 }
6a56ec7e
NC		 12286 if (info->flags & INSN_HAS_RELOC)
12287 /* If the instruction has a reloc associated with it, then
12288 the offset field in the instruction will actually be the
12289 addend for the reloc. (We are using REL type relocs).
12290 In such cases, we can ignore the pc when computing
12291 addresses, since the addend is not currently pc-relative. */
12292 pc = 0;
b34976b6 12293
4a5329c6 12294 printer (pc, info, given);
c22aaad1
PB		 12295
12296 if (is_thumb)
12297 {
12298 ifthen_state = ifthen_next_state;
12299 ifthen_address += size;
12300 }
4a5329c6 12301 return size;
252b5132
RH		 12302}
12303
12304int
4a5329c6 12305print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 12306{
bd2e2557
SS		 12307 /* Detect BE8-ness and record it in the disassembler info. */
12308 if (info->flavour == bfd_target_elf_flavour
12309 && info->section != NULL
12310 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
12311 info->endian_code = BFD_ENDIAN_LITTLE;
12312
b34976b6 12313 return print_insn (pc, info, FALSE);
58efb6c0 12314}
01c7f630 12315
58efb6c0 12316int
4a5329c6 12317print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 12318{
b34976b6 12319 return print_insn (pc, info, TRUE);
58efb6c0 12320}
252b5132 12321
471b9d15 12322const disasm_options_and_args_t *
65b48a81
PB		 12323disassembler_options_arm (void)
12324{
471b9d15 12325 static disasm_options_and_args_t *opts_and_args;
65b48a81 12326
471b9d15 12327 if (opts_and_args == NULL)
65b48a81 12328 {
471b9d15 12329 disasm_options_t *opts;
65b48a81 12330 unsigned int i;
471b9d15
MR		 12331
12332 opts_and_args = XNEW (disasm_options_and_args_t);
12333 opts_and_args->args = NULL;
12334
12335 opts = &opts_and_args->options;
65b48a81
PB		 12336 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12337 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 12338 opts->arg = NULL;
65b48a81
PB		 12339 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12340 {
12341 opts->name[i] = regnames[i].name;
12342 if (regnames[i].description != NULL)
12343 opts->description[i] = _(regnames[i].description);
12344 else
12345 opts->description[i] = NULL;
12346 }
12347 /* The array we return must be NULL terminated. */
12348 opts->name[i] = NULL;
12349 opts->description[i] = NULL;
12350 }
12351
471b9d15 12352 return opts_and_args;
65b48a81
PB		 12353}
12354
58efb6c0 12355void
4a5329c6 12356print_arm_disassembler_options (FILE *stream)
58efb6c0 12357{
65b48a81 12358 unsigned int i, max_len = 0;
58efb6c0
NC		 12359 fprintf (stream, _("\n\
12360The following ARM specific disassembler options are supported for use with\n\
12361the -M switch:\n"));
b34976b6 12362
65b48a81
PB		 12363 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12364 {
12365 unsigned int len = strlen (regnames[i].name);
12366 if (max_len < len)
12367 max_len = len;
12368 }
58efb6c0 12369
65b48a81
PB		 12370 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
12371 fprintf (stream, " %s%*c %s\n",
12372 regnames[i].name,
12373 (int)(max_len - strlen (regnames[i].name)), ' ',
12374 _(regnames[i].description));
252b5132 12375}
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