[thirdparty/binutils-gdb.git] / opcodes / d30v-dis.c

/* Disassemble D30V instructions.
   Copyright (C) 1997-2017 Free Software Foundation, Inc.

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#include "sysdep.h"
#include <stdio.h>
#include "opcode/d30v.h"
#include "dis-asm.h"
#include "opintl.h"

#define PC_MASK 0xFFFFFFFF

/* Return 0 if lookup fails,
   1 if found and only one form,
   2 if found and there are short and long forms.  */

static int
lookup_opcode (struct d30v_insn *insn, long num, int is_long)
{
  int i = 0, op_index;
  struct d30v_format *f;
  struct d30v_opcode *op = (struct d30v_opcode *) d30v_opcode_table;
  int op1 = (num >> 25) & 0x7;
  int op2 = (num >> 20) & 0x1f;
  int mod = (num >> 18) & 0x3;

  /* Find the opcode.  */
  do
    {
      if ((op->op1 == op1) && (op->op2 == op2))
	break;
      op++;
    }
  while (op->name);

  if (!op || !op->name)
    return 0;

  while (op->op1 == op1 && op->op2 == op2)
    {
      /* Scan through all the formats for the opcode.  */
      op_index = op->format[i++];
      do
	{
	  f = (struct d30v_format *) &d30v_format_table[op_index];
	  while (f->form == op_index)
	    {
	      if ((!is_long || f->form >= LONG) && (f->modifier == mod))
		{
		  insn->form = f;
		  break;
		}
	      f++;
	    }
	  if (insn->form)
	    break;
	}
      while ((op_index = op->format[i++]) != 0);
      if (insn->form)
	break;
      op++;
      i = 0;
    }
  if (insn->form == NULL)
    return 0;

  insn->op = op;
  insn->ecc = (num >> 28) & 0x7;
  if (op->format[1])
    return 2;
  else
    return 1;
}

static int
extract_value (long long num, struct d30v_operand *oper, int is_long)
{
  int val;
  int shift = 12 - oper->position;
  int mask = (0xFFFFFFFF >> (32 - oper->bits));

  if (is_long)
    {
      if (oper->bits == 32)
	/* Piece together 32-bit constant.  */
	val = ((num & 0x3FFFF)
	       | ((num & 0xFF00000) >> 2)
	       | ((num & 0x3F00000000LL) >> 6));
      else
	val = (num >> (32 + shift)) & mask;
    }
  else
    val = (num >> shift) & mask;

  if (oper->flags & OPERAND_SHIFT)
    val <<= 3;

  return val;
}

static void
print_insn (struct disassemble_info *info,
	    bfd_vma memaddr,
	    long long num,
	    struct d30v_insn *insn,
	    int is_long,
	    int show_ext)
{
  int val, opnum, need_comma = 0;
  struct d30v_operand *oper;
  int i, match, opind = 0, need_paren = 0, found_control = 0;

  (*info->fprintf_func) (info->stream, "%s", insn->op->name);

  /* Check for CMP or CMPU.  */
  if (d30v_operand_table[insn->form->operands[0]].flags & OPERAND_NAME)
    {
      opind++;
      val =
	extract_value (num,
		       (struct d30v_operand *) &d30v_operand_table[insn->form->operands[0]],
		       is_long);
      (*info->fprintf_func) (info->stream, "%s", d30v_cc_names[val]);
    }

  /* Add in ".s" or ".l".  */
  if (show_ext == 2)
    {
      if (is_long)
	(*info->fprintf_func) (info->stream, ".l");
      else
	(*info->fprintf_func) (info->stream, ".s");
    }

  if (insn->ecc)
    (*info->fprintf_func) (info->stream, "/%s", d30v_ecc_names[insn->ecc]);

  (*info->fprintf_func) (info->stream, "\t");

  while ((opnum = insn->form->operands[opind++]) != 0)
    {
      int bits;

      oper = (struct d30v_operand *) &d30v_operand_table[opnum];
      bits = oper->bits;
      if (oper->flags & OPERAND_SHIFT)
	bits += 3;

      if (need_comma
	  && oper->flags != OPERAND_PLUS
	  && oper->flags != OPERAND_MINUS)
	{
	  need_comma = 0;
	  (*info->fprintf_func) (info->stream, ", ");
	}

      if (oper->flags == OPERAND_ATMINUS)
	{
	  (*info->fprintf_func) (info->stream, "@-");
	  continue;
	}
      if (oper->flags == OPERAND_MINUS)
	{
	  (*info->fprintf_func) (info->stream, "-");
	  continue;
	}
      if (oper->flags == OPERAND_PLUS)
	{
	  (*info->fprintf_func) (info->stream, "+");
	  continue;
	}
      if (oper->flags == OPERAND_ATSIGN)
	{
	  (*info->fprintf_func) (info->stream, "@");
	  continue;
	}
      if (oper->flags == OPERAND_ATPAR)
	{
	  (*info->fprintf_func) (info->stream, "@(");
	  need_paren = 1;
	  continue;
	}

      if (oper->flags == OPERAND_SPECIAL)
	continue;

      val = extract_value (num, oper, is_long);

      if (oper->flags & OPERAND_REG)
	{
	  match = 0;
	  if (oper->flags & OPERAND_CONTROL)
	    {
	      struct d30v_operand *oper3 =
		(struct d30v_operand *) &d30v_operand_table[insn->form->operands[2]];
	      int id = extract_value (num, oper3, is_long);

	      found_control = 1;
	      switch (id)
		{
		case 0:
		  val |= OPERAND_CONTROL;
		  break;
		case 1:
		case 2:
		  val = OPERAND_CONTROL + MAX_CONTROL_REG + id;
		  break;
		case 3:
		  val |= OPERAND_FLAG;
		  break;
		default:
		  fprintf (stderr, "illegal id (%d)\n", id);
		}
	    }
	  else if (oper->flags & OPERAND_ACC)
	    val |= OPERAND_ACC;
	  else if (oper->flags & OPERAND_FLAG)
	    val |= OPERAND_FLAG;
	  for (i = 0; i < reg_name_cnt (); i++)
	    {
	      if (val == pre_defined_registers[i].value)
		{
		  if (pre_defined_registers[i].pname)
		    (*info->fprintf_func)
		      (info->stream, "%s", pre_defined_registers[i].pname);
		  else
		    (*info->fprintf_func)
		      (info->stream, "%s", pre_defined_registers[i].name);
		  match = 1;
		  break;
		}
	    }
	  if (match == 0)
	    {
	      /* This would only get executed if a register was not in
		 the register table.  */
	      (*info->fprintf_func)
		(info->stream, _("<unknown register %d>"), val & 0x3F);
	    }
	}
      /* repeati has a relocation, but its first argument is a plain
	 immediate.  OTOH instructions like djsri have a pc-relative
	 delay target, but an absolute jump target.  Therefore, a test
	 of insn->op->reloc_flag is not specific enough; we must test
	 if the actual operand we are handling now is pc-relative.  */
      else if (oper->flags & OPERAND_PCREL)
	{
	  int neg = 0;

	  /* IMM6S3 is unsigned.  */
	  if (oper->flags & OPERAND_SIGNED || bits == 32)
	    {
	      long max;
	      max = (1 << (bits - 1));
	      if (val & max)
		{
		  if (bits == 32)
		    val = -val;
		  else
		    val = -val & ((1 << bits) - 1);
		  neg = 1;
		}
	    }
	  if (neg)
	    {
	      (*info->fprintf_func) (info->stream, "-%x\t(", val);
	      (*info->print_address_func) ((memaddr - val) & PC_MASK, info);
	      (*info->fprintf_func) (info->stream, ")");
	    }
	  else
	    {
	      (*info->fprintf_func) (info->stream, "%x\t(", val);
	      (*info->print_address_func) ((memaddr + val) & PC_MASK, info);
	      (*info->fprintf_func) (info->stream, ")");
	    }
	}
      else if (insn->op->reloc_flag == RELOC_ABS)
	{
	  (*info->print_address_func) (val, info);
	}
      else
	{
	  if (oper->flags & OPERAND_SIGNED)
	    {
	      int max = (1 << (bits - 1));

	      if (val & max)
		{
		  val = -val;
		  if (bits < 32)
		    val &= ((1 << bits) - 1);
		  (*info->fprintf_func) (info->stream, "-");
		}
	    }
	  (*info->fprintf_func) (info->stream, "0x%x", val);
	}
      /* If there is another operand, then write a comma and space.  */
      if (insn->form->operands[opind] && !(found_control && opind == 2))
	need_comma = 1;
    }
  if (need_paren)
    (*info->fprintf_func) (info->stream, ")");
}

int
print_insn_d30v (bfd_vma memaddr, struct disassemble_info *info)
{
  int status, result;
  bfd_byte buffer[12];
  unsigned long in1, in2;
  struct d30v_insn insn;
  long long num;

  insn.form = NULL;

  info->bytes_per_line = 8;
  info->bytes_per_chunk = 4;
  info->display_endian = BFD_ENDIAN_BIG;

  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }
  in1 = bfd_getb32 (buffer);

  status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
  if (status != 0)
    {
      info->bytes_per_line = 8;
      if (!(result = lookup_opcode (&insn, in1, 0)))
	(*info->fprintf_func) (info->stream, ".long\t0x%lx", in1);
      else
	print_insn (info, memaddr, (long long) in1, &insn, 0, result);
      return 4;
    }
  in2 = bfd_getb32 (buffer);

  if (in1 & in2 & FM01)
    {
      /* LONG instruction.  */
      if (!(result = lookup_opcode (&insn, in1, 1)))
	{
	  (*info->fprintf_func) (info->stream, ".long\t0x%lx,0x%lx", in1, in2);
	  return 8;
	}
      num = (long long) in1 << 32 | in2;
      print_insn (info, memaddr, num, &insn, 1, result);
    }
  else
    {
      num = in1;
      if (!(result = lookup_opcode (&insn, in1, 0)))
	(*info->fprintf_func) (info->stream, ".long\t0x%lx", in1);
      else
	print_insn (info, memaddr, num, &insn, 0, result);

      switch (((in1 >> 31) << 1) | (in2 >> 31))
	{
	case 0:
	  (*info->fprintf_func) (info->stream, "\t||\t");
	  break;
	case 1:
	  (*info->fprintf_func) (info->stream, "\t->\t");
	  break;
	case 2:
	  (*info->fprintf_func) (info->stream, "\t<-\t");
	default:
	  break;
	}

      insn.form = NULL;
      num = in2;
      if (!(result = lookup_opcode (&insn, in2, 0)))
	(*info->fprintf_func) (info->stream, ".long\t0x%lx", in2);
      else
	print_insn (info, memaddr, num, &insn, 0, result);
    }
  return 8;
}
Commit	Line	Data
252b5132	1	/* Disassemble D30V instructions.
2571583a	2	Copyright (C) 1997-2017 Free Software Foundation, Inc.
252b5132	3
9b201bb5 NC	4	This file is part of the GNU opcodes library.
	5
	6	This library is free software; you can redistribute it and/or modify
47b0e7ad	7	it under the terms of the GNU General Public License as published by
9b201bb5 NC	8	the Free Software Foundation; either version 3, or (at your option)
9b201bb5 NC	9	any later version.
252b5132	10
9b201bb5 NC	11	It is distributed in the hope that it will be useful, but WITHOUT
	12	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	13	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	14	License for more details.
252b5132	15
47b0e7ad NC	16	You should have received a copy of the GNU General Public License
	17	along with this program; if not, write to the Free Software
	18	Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
	19	MA 02110-1301, USA. */
252b5132	20
0d8dfecf	21	#include "sysdep.h"
df7b86aa	22	#include <stdio.h>
2dcee538	23	#include "opcode/d30v.h"
252b5132 RH	24	#include "dis-asm.h"
	25	#include "opintl.h"
	26
	27	#define PC_MASK 0xFFFFFFFF
	28
2dcee538 KH	29	/* Return 0 if lookup fails,
	30	1 if found and only one form,
	31	2 if found and there are short and long forms. */
252b5132	32
252b5132	33	static int
47b0e7ad	34	lookup_opcode (struct d30v_insn *insn, long num, int is_long)
252b5132	35	{
91d6fa6a	36	int i = 0, op_index;
252b5132	37	struct d30v_format *f;
2dcee538	38	struct d30v_opcode op = (struct d30v_opcode ) d30v_opcode_table;
252b5132 RH	39	int op1 = (num >> 25) & 0x7;
	40	int op2 = (num >> 20) & 0x1f;
	41	int mod = (num >> 18) & 0x3;
	42
2dcee538 KH	43	/* Find the opcode. */
	44	do
	45	{
	46	if ((op->op1 == op1) && (op->op2 == op2))
	47	break;
	48	op++;
	49	}
	50	while (op->name);
252b5132 RH	51
	52	if (!op \|\| !op->name)
	53	return 0;
	54
	55	while (op->op1 == op1 && op->op2 == op2)
	56	{
2dcee538	57	/* Scan through all the formats for the opcode. */
91d6fa6a	58	op_index = op->format[i++];
2dcee538	59	do
252b5132	60	{
91d6fa6a NC	61	f = (struct d30v_format *) &d30v_format_table[op_index];
91d6fa6a NC	62	while (f->form == op_index)
252b5132 RH	63	{
	64	if ((!is_long \|\| f->form >= LONG) && (f->modifier == mod))
	65	{
	66	insn->form = f;
	67	break;
	68	}
	69	f++;
	70	}
	71	if (insn->form)
	72	break;
2dcee538	73	}
91d6fa6a	74	while ((op_index = op->format[i++]) != 0);
252b5132 RH	75	if (insn->form)
	76	break;
	77	op++;
2dcee538	78	i = 0;
252b5132 RH	79	}
	80	if (insn->form == NULL)
	81	return 0;
	82
	83	insn->op = op;
	84	insn->ecc = (num >> 28) & 0x7;
	85	if (op->format[1])
	86	return 2;
	87	else
	88	return 1;
	89	}
	90
47b0e7ad NC	91	static int
	92	extract_value (long long num, struct d30v_operand *oper, int is_long)
	93	{
	94	int val;
	95	int shift = 12 - oper->position;
	96	int mask = (0xFFFFFFFF >> (32 - oper->bits));
	97
	98	if (is_long)
	99	{
	100	if (oper->bits == 32)
	101	/* Piece together 32-bit constant. */
	102	val = ((num & 0x3FFFF)
	103	\| ((num & 0xFF00000) >> 2)
	104	\| ((num & 0x3F00000000LL) >> 6));
	105	else
	106	val = (num >> (32 + shift)) & mask;
	107	}
	108	else
	109	val = (num >> shift) & mask;
	110
	111	if (oper->flags & OPERAND_SHIFT)
	112	val <<= 3;
	113
	114	return val;
	115	}
	116
2dcee538	117	static void
47b0e7ad NC	118	print_insn (struct disassemble_info *info,
	119	bfd_vma memaddr,
	120	long long num,
	121	struct d30v_insn *insn,
	122	int is_long,
	123	int show_ext)
252b5132	124	{
2dcee538	125	int val, opnum, need_comma = 0;
252b5132	126	struct d30v_operand *oper;
2dcee538	127	int i, match, opind = 0, need_paren = 0, found_control = 0;
252b5132	128
2dcee538	129	(*info->fprintf_func) (info->stream, "%s", insn->op->name);
252b5132	130
2dcee538	131	/* Check for CMP or CMPU. */
252b5132 RH	132	if (d30v_operand_table[insn->form->operands[0]].flags & OPERAND_NAME)
	133	{
	134	opind++;
2dcee538 KH	135	val =
	136	extract_value (num,
	137	(struct d30v_operand *) &d30v_operand_table[insn->form->operands[0]],
	138	is_long);
	139	(*info->fprintf_func) (info->stream, "%s", d30v_cc_names[val]);
252b5132 RH	140	}
252b5132 RH	141
2dcee538	142	/* Add in ".s" or ".l". */
252b5132 RH	143	if (show_ext == 2)
	144	{
	145	if (is_long)
	146	(*info->fprintf_func) (info->stream, ".l");
	147	else
	148	(*info->fprintf_func) (info->stream, ".s");
	149	}
	150
	151	if (insn->ecc)
2dcee538	152	(*info->fprintf_func) (info->stream, "/%s", d30v_ecc_names[insn->ecc]);
252b5132 RH	153
	154	(*info->fprintf_func) (info->stream, "\t");
	155
	156	while ((opnum = insn->form->operands[opind++]) != 0)
	157	{
	158	int bits;
47b0e7ad	159
2dcee538	160	oper = (struct d30v_operand *) &d30v_operand_table[opnum];
252b5132 RH	161	bits = oper->bits;
	162	if (oper->flags & OPERAND_SHIFT)
	163	bits += 3;
	164
2dcee538 KH	165	if (need_comma
	166	&& oper->flags != OPERAND_PLUS
	167	&& oper->flags != OPERAND_MINUS)
252b5132	168	{
2dcee538	169	need_comma = 0;
252b5132 RH	170	(*info->fprintf_func) (info->stream, ", ");
	171	}
	172
	173	if (oper->flags == OPERAND_ATMINUS)
	174	{
	175	(*info->fprintf_func) (info->stream, "@-");
	176	continue;
	177	}
	178	if (oper->flags == OPERAND_MINUS)
	179	{
2dcee538	180	(*info->fprintf_func) (info->stream, "-");
252b5132 RH	181	continue;
	182	}
	183	if (oper->flags == OPERAND_PLUS)
	184	{
2dcee538	185	(*info->fprintf_func) (info->stream, "+");
252b5132 RH	186	continue;
	187	}
	188	if (oper->flags == OPERAND_ATSIGN)
	189	{
2dcee538	190	(*info->fprintf_func) (info->stream, "@");
252b5132 RH	191	continue;
	192	}
	193	if (oper->flags == OPERAND_ATPAR)
	194	{
2dcee538	195	(*info->fprintf_func) (info->stream, "@(");
252b5132 RH	196	need_paren = 1;
	197	continue;
	198	}
	199
	200	if (oper->flags == OPERAND_SPECIAL)
	201	continue;
	202
2dcee538 KH	203	val = extract_value (num, oper, is_long);
2dcee538 KH	204
252b5132 RH	205	if (oper->flags & OPERAND_REG)
	206	{
	207	match = 0;
	208	if (oper->flags & OPERAND_CONTROL)
	209	{
2dcee538 KH	210	struct d30v_operand *oper3 =
	211	(struct d30v_operand *) &d30v_operand_table[insn->form->operands[2]];
	212	int id = extract_value (num, oper3, is_long);
47b0e7ad	213
252b5132	214	found_control = 1;
2dcee538	215	switch (id)
252b5132 RH	216	{
	217	case 0:
	218	val \|= OPERAND_CONTROL;
	219	break;
	220	case 1:
	221	case 2:
	222	val = OPERAND_CONTROL + MAX_CONTROL_REG + id;
	223	break;
	224	case 3:
	225	val \|= OPERAND_FLAG;
	226	break;
	227	default:
2dcee538	228	fprintf (stderr, "illegal id (%d)\n", id);
252b5132 RH	229	}
	230	}
	231	else if (oper->flags & OPERAND_ACC)
	232	val \|= OPERAND_ACC;
	233	else if (oper->flags & OPERAND_FLAG)
	234	val \|= OPERAND_FLAG;
2dcee538	235	for (i = 0; i < reg_name_cnt (); i++)
252b5132 RH	236	{
	237	if (val == pre_defined_registers[i].value)
	238	{
	239	if (pre_defined_registers[i].pname)
	240	(*info->fprintf_func)
2dcee538	241	(info->stream, "%s", pre_defined_registers[i].pname);
252b5132 RH	242	else
252b5132 RH	243	(*info->fprintf_func)
2dcee538 KH	244	(info->stream, "%s", pre_defined_registers[i].name);
2dcee538 KH	245	match = 1;
252b5132 RH	246	break;
	247	}
	248	}
2dcee538	249	if (match == 0)
252b5132	250	{
2dcee538 KH	251	/* This would only get executed if a register was not in
2dcee538 KH	252	the register table. */
252b5132	253	(*info->fprintf_func)
2dcee538	254	(info->stream, _("<unknown register %d>"), val & 0x3F);
252b5132 RH	255	}
252b5132 RH	256	}
866afedc NC	257	/* repeati has a relocation, but its first argument is a plain
866afedc NC	258	immediate. OTOH instructions like djsri have a pc-relative
d9a35582	259	delay target, but an absolute jump target. Therefore, a test
866afedc NC	260	of insn->op->reloc_flag is not specific enough; we must test
	261	if the actual operand we are handling now is pc-relative. */
	262	else if (oper->flags & OPERAND_PCREL)
252b5132	263	{
866afedc	264	int neg = 0;
2dcee538	265
866afedc NC	266	/* IMM6S3 is unsigned. */
866afedc NC	267	if (oper->flags & OPERAND_SIGNED \|\| bits == 32)
252b5132	268	{
866afedc NC	269	long max;
	270	max = (1 << (bits - 1));
	271	if (val & max)
	272	{
	273	if (bits == 32)
	274	val = -val;
	275	else
2dcee538	276	val = -val & ((1 << bits) - 1);
866afedc NC	277	neg = 1;
	278	}
	279	}
	280	if (neg)
	281	{
2dcee538	282	(*info->fprintf_func) (info->stream, "-%x\t(", val);
866afedc NC	283	(*info->print_address_func) ((memaddr - val) & PC_MASK, info);
866afedc NC	284	(*info->fprintf_func) (info->stream, ")");
252b5132	285	}
866afedc	286	else
252b5132	287	{
2dcee538	288	(*info->fprintf_func) (info->stream, "%x\t(", val);
866afedc NC	289	(*info->print_address_func) ((memaddr + val) & PC_MASK, info);
866afedc NC	290	(*info->fprintf_func) (info->stream, ")");
252b5132	291	}
252b5132 RH	292	}
	293	else if (insn->op->reloc_flag == RELOC_ABS)
	294	{
	295	(*info->print_address_func) (val, info);
	296	}
	297	else
	298	{
	299	if (oper->flags & OPERAND_SIGNED)
	300	{
	301	int max = (1 << (bits - 1));
47b0e7ad	302
252b5132 RH	303	if (val & max)
	304	{
	305	val = -val;
	306	if (bits < 32)
	307	val &= ((1 << bits) - 1);
	308	(*info->fprintf_func) (info->stream, "-");
	309	}
	310	}
2dcee538	311	(*info->fprintf_func) (info->stream, "0x%x", val);
252b5132	312	}
2dcee538	313	/* If there is another operand, then write a comma and space. */
252b5132 RH	314	if (insn->form->operands[opind] && !(found_control && opind == 2))
	315	need_comma = 1;
	316	}
	317	if (need_paren)
	318	(*info->fprintf_func) (info->stream, ")");
	319	}
	320
47b0e7ad NC	321	int
47b0e7ad NC	322	print_insn_d30v (bfd_vma memaddr, struct disassemble_info *info)
252b5132	323	{
47b0e7ad NC	324	int status, result;
	325	bfd_byte buffer[12];
	326	unsigned long in1, in2;
	327	struct d30v_insn insn;
	328	long long num;
252b5132	329
47b0e7ad NC	330	insn.form = NULL;
	331
	332	info->bytes_per_line = 8;
	333	info->bytes_per_chunk = 4;
	334	info->display_endian = BFD_ENDIAN_BIG;
	335
	336	status = (*info->read_memory_func) (memaddr, buffer, 4, info);
	337	if (status != 0)
252b5132	338	{
47b0e7ad NC	339	(*info->memory_error_func) (status, memaddr, info);
	340	return -1;
	341	}
	342	in1 = bfd_getb32 (buffer);
	343
	344	status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
	345	if (status != 0)
	346	{
	347	info->bytes_per_line = 8;
	348	if (!(result = lookup_opcode (&insn, in1, 0)))
0fd3a477	349	(*info->fprintf_func) (info->stream, ".long\t0x%lx", in1);
47b0e7ad NC	350	else
	351	print_insn (info, memaddr, (long long) in1, &insn, 0, result);
	352	return 4;
	353	}
	354	in2 = bfd_getb32 (buffer);
	355
	356	if (in1 & in2 & FM01)
	357	{
	358	/* LONG instruction. */
	359	if (!(result = lookup_opcode (&insn, in1, 1)))
252b5132	360	{
0fd3a477	361	(*info->fprintf_func) (info->stream, ".long\t0x%lx,0x%lx", in1, in2);
47b0e7ad	362	return 8;
252b5132	363	}
47b0e7ad NC	364	num = (long long) in1 << 32 \| in2;
47b0e7ad NC	365	print_insn (info, memaddr, num, &insn, 1, result);
252b5132 RH	366	}
252b5132 RH	367	else
47b0e7ad NC	368	{
	369	num = in1;
	370	if (!(result = lookup_opcode (&insn, in1, 0)))
0fd3a477	371	(*info->fprintf_func) (info->stream, ".long\t0x%lx", in1);
47b0e7ad NC	372	else
47b0e7ad NC	373	print_insn (info, memaddr, num, &insn, 0, result);
252b5132	374
47b0e7ad NC	375	switch (((in1 >> 31) << 1) \| (in2 >> 31))
	376	{
	377	case 0:
	378	(*info->fprintf_func) (info->stream, "\t\|\|\t");
	379	break;
	380	case 1:
	381	(*info->fprintf_func) (info->stream, "\t->\t");
	382	break;
	383	case 2:
	384	(*info->fprintf_func) (info->stream, "\t<-\t");
	385	default:
	386	break;
	387	}
252b5132	388
47b0e7ad NC	389	insn.form = NULL;
	390	num = in2;
	391	if (!(result = lookup_opcode (&insn, in2, 0)))
0fd3a477	392	(*info->fprintf_func) (info->stream, ".long\t0x%lx", in2);
47b0e7ad NC	393	else
	394	print_insn (info, memaddr, num, &insn, 0, result);
	395	}
	396	return 8;
252b5132	397	}