]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - opcodes/disassemble.c
Update year range in copyright notice of binutils files
[thirdparty/binutils-gdb.git] / opcodes / disassemble.c
CommitLineData
252b5132 1/* Select disassembly routine for specified architecture.
250d07de 2 Copyright (C) 1994-2021 Free Software Foundation, Inc.
252b5132 3
9b201bb5
NC
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7499d566 7 it under the terms of the GNU General Public License as published by
9b201bb5 8 the Free Software Foundation; either version 3 of the License, or
7499d566 9 (at your option) any later version.
252b5132 10
7499d566
NC
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
252b5132 15
7499d566
NC
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
9b201bb5
NC
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
0d8dfecf 21#include "sysdep.h"
88c1242d 22#include "disassemble.h"
65b48a81 23#include "safe-ctype.h"
832a5807 24#include "opintl.h"
252b5132
RH
25
26#ifdef ARCH_all
a06ea964 27#define ARCH_aarch64
252b5132
RH
28#define ARCH_alpha
29#define ARCH_arc
30#define ARCH_arm
adde6300 31#define ARCH_avr
4b7f6baa 32#define ARCH_bfin
3d3d428f 33#define ARCH_cr16
6c95a37f 34#define ARCH_cris
1fe1f39c 35#define ARCH_crx
b8891f8d 36#define ARCH_csky
252b5132
RH
37#define ARCH_d10v
38#define ARCH_d30v
d172d4ba 39#define ARCH_dlx
79472b45 40#define ARCH_bpf
56b13185 41#define ARCH_epiphany
e729279b
NC
42#define ARCH_fr30
43#define ARCH_frv
3f8107ab 44#define ARCH_ft32
252b5132 45#define ARCH_h8300
252b5132
RH
46#define ARCH_hppa
47#define ARCH_i386
800eeca4 48#define ARCH_ia64
e729279b
NC
49#define ARCH_ip2k
50#define ARCH_iq2000
84e94c90 51#define ARCH_lm32
e729279b 52#define ARCH_m32c
252b5132 53#define ARCH_m32r
60bcf0fa
NC
54#define ARCH_m68hc11
55#define ARCH_m68hc12
e729279b 56#define ARCH_m68k
252b5132 57#define ARCH_mcore
bd2f2e55 58#define ARCH_mep
a3c62988 59#define ARCH_metag
7ba29e2a 60#define ARCH_microblaze
252b5132 61#define ARCH_mips
3c3bdf30 62#define ARCH_mmix
252b5132
RH
63#define ARCH_mn10200
64#define ARCH_mn10300
59b1530d 65#define ARCH_moxie
d031aafb 66#define ARCH_mt
2469cfa2 67#define ARCH_msp430
35c08157 68#define ARCH_nds32
fe944acf 69#define ARCH_nfp
36591ba1 70#define ARCH_nios2
252b5132 71#define ARCH_ns32k
73589c9d 72#define ARCH_or1k
e135f41b 73#define ARCH_pdp11
1e608f98 74#define ARCH_pj
252b5132 75#define ARCH_powerpc
11146849 76#define ARCH_pru
0bccfb29 77#define ARCH_riscv
252b5132 78#define ARCH_rs6000
99c513f6 79#define ARCH_rl78
c7927a3c 80#define ARCH_rx
9da4dfd6 81#define ARCH_s12z
a85d7ed0 82#define ARCH_s390
1c0d3aa6 83#define ARCH_score
252b5132
RH
84#define ARCH_sh
85#define ARCH_sparc
e9f53129 86#define ARCH_spu
252b5132 87#define ARCH_tic30
026df7c5 88#define ARCH_tic4x
5c84d377 89#define ARCH_tic54x
40b36596 90#define ARCH_tic6x
aa137e4d
NC
91#define ARCH_tilegx
92#define ARCH_tilepro
252b5132
RH
93#define ARCH_v850
94#define ARCH_vax
1945cfa5 95#define ARCH_visium
62ecb94c 96#define ARCH_wasm32
93fbbb04 97#define ARCH_xstormy16
d70c5fc7 98#define ARCH_xc16x
f6c1a2d5 99#define ARCH_xgate
e0001a05 100#define ARCH_xtensa
3c9b82ba 101#define ARCH_z80
252b5132
RH
102#define ARCH_z8k
103#endif
104
49f58d10
JB
105#ifdef ARCH_m32c
106#include "m32c-desc.h"
107#endif
252b5132 108
79472b45
JM
109#ifdef ARCH_bpf
110/* XXX this should be including bpf-desc.h instead of this hackery,
111 but at the moment it is not possible to include several CGEN
112 generated *-desc.h files simultaneously. To be fixed in
113 CGEN... */
114
115# ifdef ARCH_m32c
116enum epbf_isa_attr
117{
31b3f3e6 118 ISA_EBPFLE, ISA_EBPFBE, ISA_XBPFLE, ISA_XBPFBE, ISA_EBPFMAX
79472b45
JM
119};
120# else
121# include "bpf-desc.h"
122# define ISA_EBPFMAX ISA_MAX
123# endif
124#endif /* ARCH_bpf */
125
252b5132 126disassembler_ftype
b28b8b5e
L
127disassembler (enum bfd_architecture a,
128 bfd_boolean big ATTRIBUTE_UNUSED,
129 unsigned long mach ATTRIBUTE_UNUSED,
e347efc3 130 bfd *abfd ATTRIBUTE_UNUSED)
252b5132 131{
252b5132
RH
132 disassembler_ftype disassemble;
133
134 switch (a)
135 {
136 /* If you add a case to this table, also add it to the
137 ARCH_all definition right above this function. */
a06ea964
NC
138#ifdef ARCH_aarch64
139 case bfd_arch_aarch64:
140 disassemble = print_insn_aarch64;
141 break;
142#endif
252b5132
RH
143#ifdef ARCH_alpha
144 case bfd_arch_alpha:
145 disassemble = print_insn_alpha;
146 break;
147#endif
148#ifdef ARCH_arc
149 case bfd_arch_arc:
6ca4eb77
AM
150 disassemble = arc_get_disassembler (abfd);
151 break;
252b5132
RH
152#endif
153#ifdef ARCH_arm
154 case bfd_arch_arm:
003ca0fd 155 if (big)
252b5132
RH
156 disassemble = print_insn_big_arm;
157 else
158 disassemble = print_insn_little_arm;
159 break;
160#endif
adde6300
AM
161#ifdef ARCH_avr
162 case bfd_arch_avr:
163 disassemble = print_insn_avr;
164 break;
165#endif
4b7f6baa
CM
166#ifdef ARCH_bfin
167 case bfd_arch_bfin:
168 disassemble = print_insn_bfin;
169 break;
170#endif
3d3d428f
NC
171#ifdef ARCH_cr16
172 case bfd_arch_cr16:
173 disassemble = print_insn_cr16;
174 break;
175#endif
6c95a37f
HPN
176#ifdef ARCH_cris
177 case bfd_arch_cris:
78966507 178 disassemble = cris_get_disassembler (abfd);
6c95a37f 179 break;
1fe1f39c
NC
180#endif
181#ifdef ARCH_crx
182 case bfd_arch_crx:
183 disassemble = print_insn_crx;
184 break;
6c95a37f 185#endif
b8891f8d
AJ
186#ifdef ARCH_csky
187 case bfd_arch_csky:
188 disassemble = csky_get_disassembler (abfd);
189 break;
190#endif
191
252b5132
RH
192#ifdef ARCH_d10v
193 case bfd_arch_d10v:
194 disassemble = print_insn_d10v;
195 break;
196#endif
197#ifdef ARCH_d30v
198 case bfd_arch_d30v:
199 disassemble = print_insn_d30v;
200 break;
201#endif
d172d4ba
NC
202#ifdef ARCH_dlx
203 case bfd_arch_dlx:
204 /* As far as I know we only handle big-endian DLX objects. */
205 disassemble = print_insn_dlx;
206 break;
207#endif
252b5132
RH
208#ifdef ARCH_h8300
209 case bfd_arch_h8300:
003ca0fd 210 if (mach == bfd_mach_h8300h || mach == bfd_mach_h8300hn)
252b5132 211 disassemble = print_insn_h8300h;
003ca0fd
YQ
212 else if (mach == bfd_mach_h8300s
213 || mach == bfd_mach_h8300sn
214 || mach == bfd_mach_h8300sx
215 || mach == bfd_mach_h8300sxn)
252b5132 216 disassemble = print_insn_h8300s;
b7ed8fad 217 else
252b5132
RH
218 disassemble = print_insn_h8300;
219 break;
220#endif
252b5132
RH
221#ifdef ARCH_hppa
222 case bfd_arch_hppa:
223 disassemble = print_insn_hppa;
224 break;
225#endif
226#ifdef ARCH_i386
227 case bfd_arch_i386:
7b6d09fb 228 case bfd_arch_iamcu:
8a9036a4 229 case bfd_arch_l1om:
7a9068fe 230 case bfd_arch_k1om:
e396998b 231 disassemble = print_insn_i386;
252b5132
RH
232 break;
233#endif
800eeca4
JW
234#ifdef ARCH_ia64
235 case bfd_arch_ia64:
236 disassemble = print_insn_ia64;
237 break;
238#endif
a40cbfa3
NC
239#ifdef ARCH_ip2k
240 case bfd_arch_ip2k:
241 disassemble = print_insn_ip2k;
242 break;
243#endif
79472b45
JM
244#ifdef ARCH_bpf
245 case bfd_arch_bpf:
246 disassemble = print_insn_bpf;
247 break;
248#endif
cfb8c092
NC
249#ifdef ARCH_epiphany
250 case bfd_arch_epiphany:
251 disassemble = print_insn_epiphany;
252 break;
253#endif
252b5132
RH
254#ifdef ARCH_fr30
255 case bfd_arch_fr30:
256 disassemble = print_insn_fr30;
257 break;
258#endif
84e94c90
NC
259#ifdef ARCH_lm32
260 case bfd_arch_lm32:
261 disassemble = print_insn_lm32;
262 break;
263#endif
252b5132
RH
264#ifdef ARCH_m32r
265 case bfd_arch_m32r:
266 disassemble = print_insn_m32r;
267 break;
268#endif
6927f982
NC
269#if defined(ARCH_m68hc11) || defined(ARCH_m68hc12) \
270 || defined(ARCH_9s12x) || defined(ARCH_m9s12xg)
60bcf0fa
NC
271 case bfd_arch_m68hc11:
272 disassemble = print_insn_m68hc11;
273 break;
274 case bfd_arch_m68hc12:
275 disassemble = print_insn_m68hc12;
276 break;
6927f982
NC
277 case bfd_arch_m9s12x:
278 disassemble = print_insn_m9s12x;
279 break;
280 case bfd_arch_m9s12xg:
281 disassemble = print_insn_m9s12xg;
282 break;
60bcf0fa 283#endif
7b4ae824
JD
284#if defined(ARCH_s12z)
285 case bfd_arch_s12z:
286 disassemble = print_insn_s12z;
287 break;
288#endif
252b5132
RH
289#ifdef ARCH_m68k
290 case bfd_arch_m68k:
291 disassemble = print_insn_m68k;
292 break;
293#endif
d031aafb
NS
294#ifdef ARCH_mt
295 case bfd_arch_mt:
296 disassemble = print_insn_mt;
ac188222
DB
297 break;
298#endif
7ba29e2a
NC
299#ifdef ARCH_microblaze
300 case bfd_arch_microblaze:
301 disassemble = print_insn_microblaze;
302 break;
303#endif
2469cfa2
NC
304#ifdef ARCH_msp430
305 case bfd_arch_msp430:
306 disassemble = print_insn_msp430;
307 break;
308#endif
35c08157
KLC
309#ifdef ARCH_nds32
310 case bfd_arch_nds32:
311 disassemble = print_insn_nds32;
312 break;
313#endif
fe944acf
FT
314#ifdef ARCH_nfp
315 case bfd_arch_nfp:
316 disassemble = print_insn_nfp;
317 break;
318#endif
252b5132
RH
319#ifdef ARCH_ns32k
320 case bfd_arch_ns32k:
321 disassemble = print_insn_ns32k;
322 break;
323#endif
324#ifdef ARCH_mcore
325 case bfd_arch_mcore:
326 disassemble = print_insn_mcore;
327 break;
328#endif
bd2f2e55
DB
329#ifdef ARCH_mep
330 case bfd_arch_mep:
331 disassemble = print_insn_mep;
332 break;
333#endif
a3c62988
NC
334#ifdef ARCH_metag
335 case bfd_arch_metag:
336 disassemble = print_insn_metag;
337 break;
338#endif
252b5132
RH
339#ifdef ARCH_mips
340 case bfd_arch_mips:
003ca0fd 341 if (big)
252b5132
RH
342 disassemble = print_insn_big_mips;
343 else
344 disassemble = print_insn_little_mips;
345 break;
346#endif
3c3bdf30
NC
347#ifdef ARCH_mmix
348 case bfd_arch_mmix:
349 disassemble = print_insn_mmix;
350 break;
351#endif
252b5132
RH
352#ifdef ARCH_mn10200
353 case bfd_arch_mn10200:
354 disassemble = print_insn_mn10200;
355 break;
356#endif
357#ifdef ARCH_mn10300
358 case bfd_arch_mn10300:
359 disassemble = print_insn_mn10300;
360 break;
361#endif
36591ba1
SL
362#ifdef ARCH_nios2
363 case bfd_arch_nios2:
003ca0fd 364 if (big)
36591ba1
SL
365 disassemble = print_insn_big_nios2;
366 else
367 disassemble = print_insn_little_nios2;
368 break;
369#endif
73589c9d
CS
370#ifdef ARCH_or1k
371 case bfd_arch_or1k:
372 disassemble = print_insn_or1k;
3b16e843
NC
373 break;
374#endif
e135f41b
NC
375#ifdef ARCH_pdp11
376 case bfd_arch_pdp11:
377 disassemble = print_insn_pdp11;
378 break;
379#endif
1e608f98
ILT
380#ifdef ARCH_pj
381 case bfd_arch_pj:
382 disassemble = print_insn_pj;
383 break;
384#endif
252b5132
RH
385#ifdef ARCH_powerpc
386 case bfd_arch_powerpc:
52fe4420
AM
387#endif
388#ifdef ARCH_rs6000
389 case bfd_arch_rs6000:
390#endif
391#if defined ARCH_powerpc || defined ARCH_rs6000
003ca0fd 392 if (big)
252b5132
RH
393 disassemble = print_insn_big_powerpc;
394 else
395 disassemble = print_insn_little_powerpc;
396 break;
397#endif
11146849
DD
398#ifdef ARCH_pru
399 case bfd_arch_pru:
400 disassemble = print_insn_pru;
401 break;
402#endif
e23eba97
NC
403#ifdef ARCH_riscv
404 case bfd_arch_riscv:
8152e040 405 disassemble = riscv_get_disassembler (abfd);
ae4c0df4 406 break;
e23eba97 407#endif
99c513f6
DD
408#ifdef ARCH_rl78
409 case bfd_arch_rl78:
0952813b 410 disassemble = rl78_get_disassembler (abfd);
99c513f6
DD
411 break;
412#endif
c7927a3c
NC
413#ifdef ARCH_rx
414 case bfd_arch_rx:
415 disassemble = print_insn_rx;
416 break;
417#endif
a85d7ed0
NC
418#ifdef ARCH_s390
419 case bfd_arch_s390:
420 disassemble = print_insn_s390;
421 break;
422#endif
1c0d3aa6
NC
423#ifdef ARCH_score
424 case bfd_arch_score:
003ca0fd 425 if (big)
6ca4eb77 426 disassemble = print_insn_big_score;
1c0d3aa6 427 else
6ca4eb77 428 disassemble = print_insn_little_score;
1c0d3aa6
NC
429 break;
430#endif
252b5132
RH
431#ifdef ARCH_sh
432 case bfd_arch_sh:
1c509ca8 433 disassemble = print_insn_sh;
252b5132
RH
434 break;
435#endif
436#ifdef ARCH_sparc
437 case bfd_arch_sparc:
438 disassemble = print_insn_sparc;
439 break;
440#endif
e9f53129
AM
441#ifdef ARCH_spu
442 case bfd_arch_spu:
443 disassemble = print_insn_spu;
444 break;
445#endif
252b5132
RH
446#ifdef ARCH_tic30
447 case bfd_arch_tic30:
448 disassemble = print_insn_tic30;
449 break;
450#endif
026df7c5
NC
451#ifdef ARCH_tic4x
452 case bfd_arch_tic4x:
453 disassemble = print_insn_tic4x;
454 break;
455#endif
5c84d377
TW
456#ifdef ARCH_tic54x
457 case bfd_arch_tic54x:
458 disassemble = print_insn_tic54x;
459 break;
460#endif
40b36596
JM
461#ifdef ARCH_tic6x
462 case bfd_arch_tic6x:
463 disassemble = print_insn_tic6x;
464 break;
465#endif
3f8107ab
AM
466#ifdef ARCH_ft32
467 case bfd_arch_ft32:
468 disassemble = print_insn_ft32;
469 break;
470#endif
252b5132
RH
471#ifdef ARCH_v850
472 case bfd_arch_v850:
de863c74 473 case bfd_arch_v850_rh850:
252b5132
RH
474 disassemble = print_insn_v850;
475 break;
476#endif
62ecb94c
PC
477#ifdef ARCH_wasm32
478 case bfd_arch_wasm32:
479 disassemble = print_insn_wasm32;
480 break;
481#endif
f6c1a2d5
NC
482#ifdef ARCH_xgate
483 case bfd_arch_xgate:
484 disassemble = print_insn_xgate;
485 break;
486#endif
93fbbb04
GK
487#ifdef ARCH_xstormy16
488 case bfd_arch_xstormy16:
489 disassemble = print_insn_xstormy16;
490 break;
491#endif
d70c5fc7
NC
492#ifdef ARCH_xc16x
493 case bfd_arch_xc16x:
494 disassemble = print_insn_xc16x;
495 break;
496#endif
e0001a05
NC
497#ifdef ARCH_xtensa
498 case bfd_arch_xtensa:
499 disassemble = print_insn_xtensa;
500 break;
501#endif
3c9b82ba
NC
502#ifdef ARCH_z80
503 case bfd_arch_z80:
504 disassemble = print_insn_z80;
505 break;
506#endif
252b5132
RH
507#ifdef ARCH_z8k
508 case bfd_arch_z8k:
003ca0fd 509 if (mach == bfd_mach_z8001)
252b5132 510 disassemble = print_insn_z8001;
b7ed8fad 511 else
252b5132
RH
512 disassemble = print_insn_z8002;
513 break;
514#endif
515#ifdef ARCH_vax
516 case bfd_arch_vax:
517 disassemble = print_insn_vax;
518 break;
fd3c93d5 519#endif
1945cfa5
EB
520#ifdef ARCH_visium
521 case bfd_arch_visium:
522 disassemble = print_insn_visium;
523 break;
524#endif
fd3c93d5
DB
525#ifdef ARCH_frv
526 case bfd_arch_frv:
527 disassemble = print_insn_frv;
528 break;
47b1a55a 529#endif
59b1530d
AG
530#ifdef ARCH_moxie
531 case bfd_arch_moxie:
532 disassemble = print_insn_moxie;
533 break;
534#endif
47b1a55a
SC
535#ifdef ARCH_iq2000
536 case bfd_arch_iq2000:
537 disassemble = print_insn_iq2000;
538 break;
49f58d10
JB
539#endif
540#ifdef ARCH_m32c
541 case bfd_arch_m32c:
542 disassemble = print_insn_m32c;
543 break;
aa137e4d
NC
544#endif
545#ifdef ARCH_tilegx
546 case bfd_arch_tilegx:
547 disassemble = print_insn_tilegx;
548 break;
549#endif
550#ifdef ARCH_tilepro
551 case bfd_arch_tilepro:
552 disassemble = print_insn_tilepro;
553 break;
252b5132
RH
554#endif
555 default:
556 return 0;
557 }
558 return disassemble;
559}
94470b23
NC
560
561void
e6c7cdec 562disassembler_usage (FILE *stream ATTRIBUTE_UNUSED)
94470b23 563{
a06ea964
NC
564#ifdef ARCH_aarch64
565 print_aarch64_disassembler_options (stream);
566#endif
37fd5ef3
CZ
567#ifdef ARCH_arc
568 print_arc_disassembler_options (stream);
569#endif
58efb6c0
NC
570#ifdef ARCH_arm
571 print_arm_disassembler_options (stream);
572#endif
640c0ccd
CD
573#ifdef ARCH_mips
574 print_mips_disassembler_options (stream);
575#endif
fe944acf
FT
576#ifdef ARCH_nfp
577 print_nfp_disassembler_options (stream);
578#endif
07dd56a9
NC
579#ifdef ARCH_powerpc
580 print_ppc_disassembler_options (stream);
581#endif
e23eba97
NC
582#ifdef ARCH_riscv
583 print_riscv_disassembler_options (stream);
584#endif
f59a29b9
L
585#ifdef ARCH_i386
586 print_i386_disassembler_options (stream);
587#endif
112b7c50
AK
588#ifdef ARCH_s390
589 print_s390_disassembler_options (stream);
590#endif
62ecb94c
PC
591#ifdef ARCH_wasm32
592 print_wasm32_disassembler_options (stream);
593#endif
b7ed8fad 594
94470b23
NC
595 return;
596}
22a398e1
NC
597
598void
599disassemble_init_for_target (struct disassemble_info * info)
600{
601 if (info == NULL)
602 return;
603
604 switch (info->arch)
605 {
a06ea964
NC
606#ifdef ARCH_aarch64
607 case bfd_arch_aarch64:
608 info->symbol_is_valid = aarch64_symbol_is_valid;
609 info->disassembler_needs_relocs = TRUE;
610 break;
611#endif
22a398e1
NC
612#ifdef ARCH_arm
613 case bfd_arch_arm:
614 info->symbol_is_valid = arm_symbol_is_valid;
d99b6465 615 info->disassembler_needs_relocs = TRUE;
22a398e1 616 break;
0bcb06d2 617#endif
b8891f8d
AJ
618#ifdef ARCH_csky
619 case bfd_arch_csky:
620 info->symbol_is_valid = csky_symbol_is_valid;
621 info->disassembler_needs_relocs = TRUE;
622 break;
623#endif
624
0bcb06d2
AS
625#ifdef ARCH_ia64
626 case bfd_arch_ia64:
627 info->skip_zeroes = 16;
628 break;
629#endif
630#ifdef ARCH_tic4x
631 case bfd_arch_tic4x:
632 info->skip_zeroes = 32;
fb53f5a8 633 break;
49f58d10 634#endif
bd2f2e55
DB
635#ifdef ARCH_mep
636 case bfd_arch_mep:
637 info->skip_zeroes = 256;
638 info->skip_zeroes_at_end = 0;
639 break;
640#endif
a3c62988
NC
641#ifdef ARCH_metag
642 case bfd_arch_metag:
643 info->disassembler_needs_relocs = TRUE;
644 break;
645#endif
49f58d10
JB
646#ifdef ARCH_m32c
647 case bfd_arch_m32c:
6ca4eb77
AM
648 /* This processor in fact is little endian. The value set here
649 reflects the way opcodes are written in the cgen description. */
49f58d10 650 info->endian = BFD_ENDIAN_BIG;
103ebbc3 651 if (!info->private_data)
fb53f5a8 652 {
103ebbc3 653 info->private_data = cgen_bitset_create (ISA_MAX);
fb53f5a8 654 if (info->mach == bfd_mach_m16c)
103ebbc3 655 cgen_bitset_set (info->private_data, ISA_M16C);
fb53f5a8 656 else
103ebbc3 657 cgen_bitset_set (info->private_data, ISA_M32C);
fb53f5a8 658 }
49f58d10 659 break;
b240011a 660#endif
79472b45
JM
661#ifdef ARCH_bpf
662 case bfd_arch_bpf:
d8740be1 663 info->endian_code = BFD_ENDIAN_LITTLE;
103ebbc3
AM
664 if (!info->private_data)
665 {
4449c81a 666 info->private_data = cgen_bitset_create (ISA_MAX);
103ebbc3 667 if (info->endian == BFD_ENDIAN_BIG)
4449c81a
DF
668 {
669 cgen_bitset_set (info->private_data, ISA_EBPFBE);
670 if (info->mach == bfd_mach_xbpf)
671 cgen_bitset_set (info->private_data, ISA_XBPFBE);
672 }
103ebbc3 673 else
4449c81a
DF
674 {
675 cgen_bitset_set (info->private_data, ISA_EBPFLE);
676 if (info->mach == bfd_mach_xbpf)
677 cgen_bitset_set (info->private_data, ISA_XBPFLE);
678 }
103ebbc3 679 }
79472b45
JM
680 break;
681#endif
024d185c
DD
682#ifdef ARCH_pru
683 case bfd_arch_pru:
684 info->disassembler_needs_relocs = TRUE;
685 break;
686#endif
fbc22555
DD
687#ifdef ARCH_powerpc
688 case bfd_arch_powerpc:
689#endif
b240011a
AM
690#ifdef ARCH_rs6000
691 case bfd_arch_rs6000:
692#endif
693#if defined (ARCH_powerpc) || defined (ARCH_rs6000)
694 disassemble_init_powerpc (info);
695 break;
65b48a81 696#endif
884b49e3
AB
697#ifdef ARCH_riscv
698 case bfd_arch_riscv:
699 info->symbol_is_valid = riscv_symbol_is_valid;
700 break;
701#endif
62ecb94c
PC
702#ifdef ARCH_wasm32
703 case bfd_arch_wasm32:
704 disassemble_init_wasm32 (info);
705 break;
706#endif
65b48a81
PB
707#ifdef ARCH_s390
708 case bfd_arch_s390:
709 disassemble_init_s390 (info);
710 break;
22a398e1 711#endif
fbaf61ad
NC
712#ifdef ARCH_nds32
713 case bfd_arch_nds32:
714 disassemble_init_nds32 (info);
715 break;
716 #endif
22a398e1
NC
717 default:
718 break;
719 }
720}
65b48a81 721
20135676
AM
722void
723disassemble_free_target (struct disassemble_info *info)
724{
725 if (info == NULL)
726 return;
727
728 switch (info->arch)
729 {
730 default:
731 return;
732
733#ifdef ARCH_bpf
734 case bfd_arch_bpf:
735#endif
736#ifdef ARCH_m32c
737 case bfd_arch_m32c:
738#endif
739#if defined ARCH_bpf || defined ARCH_m32c
740 if (info->private_data)
741 {
742 CGEN_BITSET *mask = info->private_data;
743 free (mask->bits);
744 }
745 break;
746#endif
747
748#ifdef ARCH_arc
749 case bfd_arch_arc:
750 break;
751#endif
752#ifdef ARCH_cris
753 case bfd_arch_cris:
754 break;
755#endif
756#ifdef ARCH_mmix
757 case bfd_arch_mmix:
758 break;
759#endif
760#ifdef ARCH_nfp
761 case bfd_arch_nfp:
762 break;
763#endif
764#ifdef ARCH_powerpc
765 case bfd_arch_powerpc:
766 break;
767#endif
768#ifdef ARCH_riscv
769 case bfd_arch_riscv:
770 break;
771#endif
772#ifdef ARCH_rs6000
773 case bfd_arch_rs6000:
774 break;
775#endif
776 }
777
778 free (info->private_data);
779}
780
65b48a81
PB
781/* Remove whitespace and consecutive commas from OPTIONS. */
782
783char *
784remove_whitespace_and_extra_commas (char *options)
785{
786 char *str;
787 size_t i, len;
788
789 if (options == NULL)
790 return NULL;
791
792 /* Strip off all trailing whitespace and commas. */
793 for (len = strlen (options); len > 0; len--)
794 {
795 if (!ISSPACE (options[len - 1]) && options[len - 1] != ',')
796 break;
797 options[len - 1] = '\0';
798 }
799
800 /* Convert all remaining whitespace to commas. */
801 for (i = 0; options[i] != '\0'; i++)
802 if (ISSPACE (options[i]))
803 options[i] = ',';
804
805 /* Remove consecutive commas. */
806 for (str = options; *str != '\0'; str++)
807 if (*str == ',' && (*(str + 1) == ',' || str == options))
808 {
809 char *next = str + 1;
810 while (*next == ',')
811 next++;
812 len = strlen (next);
813 if (str != options)
814 str++;
815 memmove (str, next, len);
816 next[len - (size_t)(next - str)] = '\0';
817 }
818 return (strlen (options) != 0) ? options : NULL;
819}
820
821/* Like STRCMP, but treat ',' the same as '\0' so that we match
822 strings like "foobar" against "foobar,xxyyzz,...". */
823
824int
825disassembler_options_cmp (const char *s1, const char *s2)
826{
827 unsigned char c1, c2;
828
829 do
830 {
831 c1 = (unsigned char) *s1++;
832 if (c1 == ',')
833 c1 = '\0';
834 c2 = (unsigned char) *s2++;
835 if (c2 == ',')
836 c2 = '\0';
837 if (c1 == '\0')
838 return c1 - c2;
839 }
840 while (c1 == c2);
841
842 return c1 - c2;
843}
832a5807
AM
844
845void
846opcodes_assert (const char *file, int line)
847{
848 opcodes_error_handler (_("assertion fail %s:%d"), file, line);
849 opcodes_error_handler (_("Please report this bug"));
850 abort ();
851}