[thirdparty/binutils-gdb.git] / opcodes / iq2000-dis.c

/* Disassembler interface for targets using CGEN. -*- C -*-
   CGEN: Cpu tools GENerator

   THIS FILE IS MACHINE GENERATED WITH CGEN.
   - the resultant file is machine generated, cgen-dis.in isn't

   Copyright (C) 1996-2017 Free Software Foundation, Inc.

   This file is part of libopcodes.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software Foundation, Inc.,
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */

/* ??? Eventually more and more of this stuff can go to cpu-independent files.
   Keep that in mind.  */

#include "sysdep.h"
#include <stdio.h>
#include "ansidecl.h"
#include "dis-asm.h"
#include "bfd.h"
#include "symcat.h"
#include "libiberty.h"
#include "iq2000-desc.h"
#include "iq2000-opc.h"
#include "opintl.h"

/* Default text to print if an instruction isn't recognized.  */
#define UNKNOWN_INSN_MSG _("*unknown*")

static void print_normal
  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
static void print_address
  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
static void print_keyword
  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
static void print_insn_normal
  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
static int print_insn
  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, bfd_byte *, unsigned);
static int default_print_insn
  (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
static int read_insn
  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
   unsigned long *);
\f
/* -- disassembler routines inserted here.  */


void iq2000_cgen_print_operand
  (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);

/* Main entry point for printing operands.
   XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
   of dis-asm.h on cgen.h.

   This function is basically just a big switch statement.  Earlier versions
   used tables to look up the function to use, but
   - if the table contains both assembler and disassembler functions then
     the disassembler contains much of the assembler and vice-versa,
   - there's a lot of inlining possibilities as things grow,
   - using a switch statement avoids the function call overhead.

   This function could be moved into `print_insn_normal', but keeping it
   separate makes clear the interface between `print_insn_normal' and each of
   the handlers.  */

void
iq2000_cgen_print_operand (CGEN_CPU_DESC cd,
			   int opindex,
			   void * xinfo,
			   CGEN_FIELDS *fields,
			   void const *attrs ATTRIBUTE_UNUSED,
			   bfd_vma pc,
			   int length)
{
  disassemble_info *info = (disassemble_info *) xinfo;

  switch (opindex)
    {
    case IQ2000_OPERAND__INDEX :
      print_normal (cd, info, fields->f_index, 0, pc, length);
      break;
    case IQ2000_OPERAND_BASE :
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
      break;
    case IQ2000_OPERAND_BASEOFF :
      print_address (cd, info, fields->f_imm, 0, pc, length);
      break;
    case IQ2000_OPERAND_BITNUM :
      print_normal (cd, info, fields->f_rt, 0, pc, length);
      break;
    case IQ2000_OPERAND_BYTECOUNT :
      print_normal (cd, info, fields->f_bytecount, 0, pc, length);
      break;
    case IQ2000_OPERAND_CAM_Y :
      print_normal (cd, info, fields->f_cam_y, 0, pc, length);
      break;
    case IQ2000_OPERAND_CAM_Z :
      print_normal (cd, info, fields->f_cam_z, 0, pc, length);
      break;
    case IQ2000_OPERAND_CM_3FUNC :
      print_normal (cd, info, fields->f_cm_3func, 0, pc, length);
      break;
    case IQ2000_OPERAND_CM_3Z :
      print_normal (cd, info, fields->f_cm_3z, 0, pc, length);
      break;
    case IQ2000_OPERAND_CM_4FUNC :
      print_normal (cd, info, fields->f_cm_4func, 0, pc, length);
      break;
    case IQ2000_OPERAND_CM_4Z :
      print_normal (cd, info, fields->f_cm_4z, 0, pc, length);
      break;
    case IQ2000_OPERAND_COUNT :
      print_normal (cd, info, fields->f_count, 0, pc, length);
      break;
    case IQ2000_OPERAND_EXECODE :
      print_normal (cd, info, fields->f_excode, 0, pc, length);
      break;
    case IQ2000_OPERAND_HI16 :
      print_normal (cd, info, fields->f_imm, 0, pc, length);
      break;
    case IQ2000_OPERAND_IMM :
      print_normal (cd, info, fields->f_imm, 0, pc, length);
      break;
    case IQ2000_OPERAND_JMPTARG :
      print_address (cd, info, fields->f_jtarg, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
      break;
    case IQ2000_OPERAND_JMPTARGQ10 :
      print_address (cd, info, fields->f_jtargq10, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
      break;
    case IQ2000_OPERAND_LO16 :
      print_normal (cd, info, fields->f_imm, 0, pc, length);
      break;
    case IQ2000_OPERAND_MASK :
      print_normal (cd, info, fields->f_mask, 0, pc, length);
      break;
    case IQ2000_OPERAND_MASKL :
      print_normal (cd, info, fields->f_maskl, 0, pc, length);
      break;
    case IQ2000_OPERAND_MASKQ10 :
      print_normal (cd, info, fields->f_maskq10, 0, pc, length);
      break;
    case IQ2000_OPERAND_MASKR :
      print_normal (cd, info, fields->f_rs, 0, pc, length);
      break;
    case IQ2000_OPERAND_MLO16 :
      print_normal (cd, info, fields->f_imm, 0, pc, length);
      break;
    case IQ2000_OPERAND_OFFSET :
      print_address (cd, info, fields->f_offset, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
      break;
    case IQ2000_OPERAND_RD :
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd, 0);
      break;
    case IQ2000_OPERAND_RD_RS :
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rs, 0|(1<<CGEN_OPERAND_VIRTUAL));
      break;
    case IQ2000_OPERAND_RD_RT :
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rt, 0|(1<<CGEN_OPERAND_VIRTUAL));
      break;
    case IQ2000_OPERAND_RS :
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
      break;
    case IQ2000_OPERAND_RT :
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt, 0);
      break;
    case IQ2000_OPERAND_RT_RS :
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt_rs, 0|(1<<CGEN_OPERAND_VIRTUAL));
      break;
    case IQ2000_OPERAND_SHAMT :
      print_normal (cd, info, fields->f_shamt, 0, pc, length);
      break;

    default :
      /* xgettext:c-format */
      fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
	       opindex);
    abort ();
  }
}

cgen_print_fn * const iq2000_cgen_print_handlers[] =
{
  print_insn_normal,
};


void
iq2000_cgen_init_dis (CGEN_CPU_DESC cd)
{
  iq2000_cgen_init_opcode_table (cd);
  iq2000_cgen_init_ibld_table (cd);
  cd->print_handlers = & iq2000_cgen_print_handlers[0];
  cd->print_operand = iq2000_cgen_print_operand;
}

\f
/* Default print handler.  */

static void
print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	      void *dis_info,
	      long value,
	      unsigned int attrs,
	      bfd_vma pc ATTRIBUTE_UNUSED,
	      int length ATTRIBUTE_UNUSED)
{
  disassemble_info *info = (disassemble_info *) dis_info;

  /* Print the operand as directed by the attributes.  */
  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
    ; /* nothing to do */
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
    (*info->fprintf_func) (info->stream, "%ld", value);
  else
    (*info->fprintf_func) (info->stream, "0x%lx", value);
}

/* Default address handler.  */

static void
print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	       void *dis_info,
	       bfd_vma value,
	       unsigned int attrs,
	       bfd_vma pc ATTRIBUTE_UNUSED,
	       int length ATTRIBUTE_UNUSED)
{
  disassemble_info *info = (disassemble_info *) dis_info;

  /* Print the operand as directed by the attributes.  */
  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
    ; /* Nothing to do.  */
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
    (*info->print_address_func) (value, info);
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
    (*info->print_address_func) (value, info);
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
    (*info->fprintf_func) (info->stream, "%ld", (long) value);
  else
    (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
}

/* Keyword print handler.  */

static void
print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	       void *dis_info,
	       CGEN_KEYWORD *keyword_table,
	       long value,
	       unsigned int attrs ATTRIBUTE_UNUSED)
{
  disassemble_info *info = (disassemble_info *) dis_info;
  const CGEN_KEYWORD_ENTRY *ke;

  ke = cgen_keyword_lookup_value (keyword_table, value);
  if (ke != NULL)
    (*info->fprintf_func) (info->stream, "%s", ke->name);
  else
    (*info->fprintf_func) (info->stream, "???");
}
\f
/* Default insn printer.

   DIS_INFO is defined as `void *' so the disassembler needn't know anything
   about disassemble_info.  */

static void
print_insn_normal (CGEN_CPU_DESC cd,
		   void *dis_info,
		   const CGEN_INSN *insn,
		   CGEN_FIELDS *fields,
		   bfd_vma pc,
		   int length)
{
  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
  disassemble_info *info = (disassemble_info *) dis_info;
  const CGEN_SYNTAX_CHAR_TYPE *syn;

  CGEN_INIT_PRINT (cd);

  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
    {
      if (CGEN_SYNTAX_MNEMONIC_P (*syn))
	{
	  (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
	  continue;
	}
      if (CGEN_SYNTAX_CHAR_P (*syn))
	{
	  (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
	  continue;
	}

      /* We have an operand.  */
      iq2000_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
				 fields, CGEN_INSN_ATTRS (insn), pc, length);
    }
}
\f
/* Subroutine of print_insn. Reads an insn into the given buffers and updates
   the extract info.
   Returns 0 if all is well, non-zero otherwise.  */

static int
read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	   bfd_vma pc,
	   disassemble_info *info,
	   bfd_byte *buf,
	   int buflen,
	   CGEN_EXTRACT_INFO *ex_info,
	   unsigned long *insn_value)
{
  int status = (*info->read_memory_func) (pc, buf, buflen, info);

  if (status != 0)
    {
      (*info->memory_error_func) (status, pc, info);
      return -1;
    }

  ex_info->dis_info = info;
  ex_info->valid = (1 << buflen) - 1;
  ex_info->insn_bytes = buf;

  *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
  return 0;
}

/* Utility to print an insn.
   BUF is the base part of the insn, target byte order, BUFLEN bytes long.
   The result is the size of the insn in bytes or zero for an unknown insn
   or -1 if an error occurs fetching data (memory_error_func will have
   been called).  */

static int
print_insn (CGEN_CPU_DESC cd,
	    bfd_vma pc,
	    disassemble_info *info,
	    bfd_byte *buf,
	    unsigned int buflen)
{
  CGEN_INSN_INT insn_value;
  const CGEN_INSN_LIST *insn_list;
  CGEN_EXTRACT_INFO ex_info;
  int basesize;

  /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
  basesize = cd->base_insn_bitsize < buflen * 8 ?
                                     cd->base_insn_bitsize : buflen * 8;
  insn_value = cgen_get_insn_value (cd, buf, basesize);


  /* Fill in ex_info fields like read_insn would.  Don't actually call
     read_insn, since the incoming buffer is already read (and possibly
     modified a la m32r).  */
  ex_info.valid = (1 << buflen) - 1;
  ex_info.dis_info = info;
  ex_info.insn_bytes = buf;

  /* The instructions are stored in hash lists.
     Pick the first one and keep trying until we find the right one.  */

  insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
  while (insn_list != NULL)
    {
      const CGEN_INSN *insn = insn_list->insn;
      CGEN_FIELDS fields;
      int length;
      unsigned long insn_value_cropped;

#ifdef CGEN_VALIDATE_INSN_SUPPORTED
      /* Not needed as insn shouldn't be in hash lists if not supported.  */
      /* Supported by this cpu?  */
      if (! iq2000_cgen_insn_supported (cd, insn))
        {
          insn_list = CGEN_DIS_NEXT_INSN (insn_list);
	  continue;
        }
#endif

      /* Basic bit mask must be correct.  */
      /* ??? May wish to allow target to defer this check until the extract
	 handler.  */

      /* Base size may exceed this instruction's size.  Extract the
         relevant part from the buffer. */
      if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
	  (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
					   info->endian == BFD_ENDIAN_BIG);
      else
	insn_value_cropped = insn_value;

      if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
	  == CGEN_INSN_BASE_VALUE (insn))
	{
	  /* Printing is handled in two passes.  The first pass parses the
	     machine insn and extracts the fields.  The second pass prints
	     them.  */

	  /* Make sure the entire insn is loaded into insn_value, if it
	     can fit.  */
	  if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
	      (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	    {
	      unsigned long full_insn_value;
	      int rc = read_insn (cd, pc, info, buf,
				  CGEN_INSN_BITSIZE (insn) / 8,
				  & ex_info, & full_insn_value);
	      if (rc != 0)
		return rc;
	      length = CGEN_EXTRACT_FN (cd, insn)
		(cd, insn, &ex_info, full_insn_value, &fields, pc);
	    }
	  else
	    length = CGEN_EXTRACT_FN (cd, insn)
	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);

	  /* Length < 0 -> error.  */
	  if (length < 0)
	    return length;
	  if (length > 0)
	    {
	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
	      /* Length is in bits, result is in bytes.  */
	      return length / 8;
	    }
	}

      insn_list = CGEN_DIS_NEXT_INSN (insn_list);
    }

  return 0;
}

/* Default value for CGEN_PRINT_INSN.
   The result is the size of the insn in bytes or zero for an unknown insn
   or -1 if an error occured fetching bytes.  */

#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
#endif

static int
default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
{
  bfd_byte buf[CGEN_MAX_INSN_SIZE];
  int buflen;
  int status;

  /* Attempt to read the base part of the insn.  */
  buflen = cd->base_insn_bitsize / 8;
  status = (*info->read_memory_func) (pc, buf, buflen, info);

  /* Try again with the minimum part, if min < base.  */
  if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
    {
      buflen = cd->min_insn_bitsize / 8;
      status = (*info->read_memory_func) (pc, buf, buflen, info);
    }

  if (status != 0)
    {
      (*info->memory_error_func) (status, pc, info);
      return -1;
    }

  return print_insn (cd, pc, info, buf, buflen);
}

/* Main entry point.
   Print one instruction from PC on INFO->STREAM.
   Return the size of the instruction (in bytes).  */

typedef struct cpu_desc_list
{
  struct cpu_desc_list *next;
  CGEN_BITSET *isa;
  int mach;
  int endian;
  CGEN_CPU_DESC cd;
} cpu_desc_list;

int
print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
{
  static cpu_desc_list *cd_list = 0;
  cpu_desc_list *cl = 0;
  static CGEN_CPU_DESC cd = 0;
  static CGEN_BITSET *prev_isa;
  static int prev_mach;
  static int prev_endian;
  int length;
  CGEN_BITSET *isa;
  int mach;
  int endian = (info->endian == BFD_ENDIAN_BIG
		? CGEN_ENDIAN_BIG
		: CGEN_ENDIAN_LITTLE);
  enum bfd_architecture arch;

  /* ??? gdb will set mach but leave the architecture as "unknown" */
#ifndef CGEN_BFD_ARCH
#define CGEN_BFD_ARCH bfd_arch_iq2000
#endif
  arch = info->arch;
  if (arch == bfd_arch_unknown)
    arch = CGEN_BFD_ARCH;

  /* There's no standard way to compute the machine or isa number
     so we leave it to the target.  */
#ifdef CGEN_COMPUTE_MACH
  mach = CGEN_COMPUTE_MACH (info);
#else
  mach = info->mach;
#endif

#ifdef CGEN_COMPUTE_ISA
  {
    static CGEN_BITSET *permanent_isa;

    if (!permanent_isa)
      permanent_isa = cgen_bitset_create (MAX_ISAS);
    isa = permanent_isa;
    cgen_bitset_clear (isa);
    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
  }
#else
  isa = info->insn_sets;
#endif

  /* If we've switched cpu's, try to find a handle we've used before */
  if (cd
      && (cgen_bitset_compare (isa, prev_isa) != 0
	  || mach != prev_mach
	  || endian != prev_endian))
    {
      cd = 0;
      for (cl = cd_list; cl; cl = cl->next)
	{
	  if (cgen_bitset_compare (cl->isa, isa) == 0 &&
	      cl->mach == mach &&
	      cl->endian == endian)
	    {
	      cd = cl->cd;
 	      prev_isa = cd->isas;
	      break;
	    }
	}
    }

  /* If we haven't initialized yet, initialize the opcode table.  */
  if (! cd)
    {
      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
      const char *mach_name;

      if (!arch_type)
	abort ();
      mach_name = arch_type->printable_name;

      prev_isa = cgen_bitset_copy (isa);
      prev_mach = mach;
      prev_endian = endian;
      cd = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
				 CGEN_CPU_OPEN_BFDMACH, mach_name,
				 CGEN_CPU_OPEN_ENDIAN, prev_endian,
				 CGEN_CPU_OPEN_END);
      if (!cd)
	abort ();

      /* Save this away for future reference.  */
      cl = xmalloc (sizeof (struct cpu_desc_list));
      cl->cd = cd;
      cl->isa = prev_isa;
      cl->mach = mach;
      cl->endian = endian;
      cl->next = cd_list;
      cd_list = cl;

      iq2000_cgen_init_dis (cd);
    }

  /* We try to have as much common code as possible.
     But at this point some targets need to take over.  */
  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
     but if not possible try to move this hook elsewhere rather than
     have two hooks.  */
  length = CGEN_PRINT_INSN (cd, pc, info);
  if (length > 0)
    return length;
  if (length < 0)
    return -1;

  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
  return cd->default_insn_bitsize / 8;
}
Commit	Line	Data
47b1a55a SC	1	/* Disassembler interface for targets using CGEN. -- C --
	2	CGEN: Cpu tools GENerator
	3
47b0e7ad NC	4	THIS FILE IS MACHINE GENERATED WITH CGEN.
47b0e7ad NC	5	- the resultant file is machine generated, cgen-dis.in isn't
47b1a55a	6
2571583a	7	Copyright (C) 1996-2017 Free Software Foundation, Inc.
47b1a55a	8
9b201bb5	9	This file is part of libopcodes.
47b1a55a	10
9b201bb5	11	This library is free software; you can redistribute it and/or modify
47b0e7ad	12	it under the terms of the GNU General Public License as published by
9b201bb5	13	the Free Software Foundation; either version 3, or (at your option)
47b0e7ad	14	any later version.
47b1a55a	15
9b201bb5 NC	16	It is distributed in the hope that it will be useful, but WITHOUT
	17	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	18	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	19	License for more details.
47b1a55a	20
47b0e7ad NC	21	You should have received a copy of the GNU General Public License
	22	along with this program; if not, write to the Free Software Foundation, Inc.,
	23	51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
47b1a55a SC	24
	25	/* ??? Eventually more and more of this stuff can go to cpu-independent files.
	26	Keep that in mind. */
	27
	28	#include "sysdep.h"
	29	#include <stdio.h>
	30	#include "ansidecl.h"
	31	#include "dis-asm.h"
	32	#include "bfd.h"
	33	#include "symcat.h"
75798298	34	#include "libiberty.h"
47b1a55a SC	35	#include "iq2000-desc.h"
	36	#include "iq2000-opc.h"
	37	#include "opintl.h"
	38
	39	/* Default text to print if an instruction isn't recognized. */
	40	#define UNKNOWN_INSN_MSG _("unknown")
	41
	42	static void print_normal
ffead7ae	43	(CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
47b1a55a	44	static void print_address
bf143b25	45	(CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
47b1a55a	46	static void print_keyword
bf143b25	47	(CGEN_CPU_DESC, void , CGEN_KEYWORD , long, unsigned int) ATTRIBUTE_UNUSED;
47b1a55a	48	static void print_insn_normal
ffead7ae	49	(CGEN_CPU_DESC, void , const CGEN_INSN , CGEN_FIELDS *, bfd_vma, int);
47b1a55a	50	static int print_insn
33b71eeb	51	(CGEN_CPU_DESC, bfd_vma, disassemble_info , bfd_byte , unsigned);
47b1a55a	52	static int default_print_insn
bf143b25	53	(CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
47b1a55a	54	static int read_insn
33b71eeb	55	(CGEN_CPU_DESC, bfd_vma, disassemble_info , bfd_byte , int, CGEN_EXTRACT_INFO *,
ffead7ae	56	unsigned long *);
47b1a55a	57	\f
47b0e7ad	58	/* -- disassembler routines inserted here. */
47b1a55a SC	59
	60
	61	void iq2000_cgen_print_operand
47b0e7ad	62	(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS , void const , bfd_vma, int);
47b1a55a SC	63
	64	/* Main entry point for printing operands.
	65	XINFO is a `void ' and not a `disassemble_info ' to not put a requirement
	66	of dis-asm.h on cgen.h.
	67
	68	This function is basically just a big switch statement. Earlier versions
	69	used tables to look up the function to use, but
	70	- if the table contains both assembler and disassembler functions then
	71	the disassembler contains much of the assembler and vice-versa,
	72	- there's a lot of inlining possibilities as things grow,
	73	- using a switch statement avoids the function call overhead.
	74
	75	This function could be moved into `print_insn_normal', but keeping it
	76	separate makes clear the interface between `print_insn_normal' and each of
	77	the handlers. */
	78
	79	void
47b0e7ad NC	80	iq2000_cgen_print_operand (CGEN_CPU_DESC cd,
	81	int opindex,
	82	void * xinfo,
	83	CGEN_FIELDS *fields,
	84	void const *attrs ATTRIBUTE_UNUSED,
	85	bfd_vma pc,
	86	int length)
47b1a55a	87	{
47b0e7ad	88	disassemble_info info = (disassemble_info ) xinfo;
47b1a55a SC	89
	90	switch (opindex)
	91	{
4030fa5a NC	92	case IQ2000_OPERAND__INDEX :
	93	print_normal (cd, info, fields->f_index, 0, pc, length);
	94	break;
47b1a55a SC	95	case IQ2000_OPERAND_BASE :
	96	print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
	97	break;
	98	case IQ2000_OPERAND_BASEOFF :
	99	print_address (cd, info, fields->f_imm, 0, pc, length);
	100	break;
	101	case IQ2000_OPERAND_BITNUM :
	102	print_normal (cd, info, fields->f_rt, 0, pc, length);
	103	break;
	104	case IQ2000_OPERAND_BYTECOUNT :
	105	print_normal (cd, info, fields->f_bytecount, 0, pc, length);
	106	break;
	107	case IQ2000_OPERAND_CAM_Y :
	108	print_normal (cd, info, fields->f_cam_y, 0, pc, length);
	109	break;
	110	case IQ2000_OPERAND_CAM_Z :
	111	print_normal (cd, info, fields->f_cam_z, 0, pc, length);
	112	break;
	113	case IQ2000_OPERAND_CM_3FUNC :
	114	print_normal (cd, info, fields->f_cm_3func, 0, pc, length);
	115	break;
	116	case IQ2000_OPERAND_CM_3Z :
	117	print_normal (cd, info, fields->f_cm_3z, 0, pc, length);
	118	break;
	119	case IQ2000_OPERAND_CM_4FUNC :
	120	print_normal (cd, info, fields->f_cm_4func, 0, pc, length);
	121	break;
	122	case IQ2000_OPERAND_CM_4Z :
	123	print_normal (cd, info, fields->f_cm_4z, 0, pc, length);
	124	break;
	125	case IQ2000_OPERAND_COUNT :
	126	print_normal (cd, info, fields->f_count, 0, pc, length);
	127	break;
	128	case IQ2000_OPERAND_EXECODE :
	129	print_normal (cd, info, fields->f_excode, 0, pc, length);
	130	break;
	131	case IQ2000_OPERAND_HI16 :
	132	print_normal (cd, info, fields->f_imm, 0, pc, length);
	133	break;
	134	case IQ2000_OPERAND_IMM :
	135	print_normal (cd, info, fields->f_imm, 0, pc, length);
	136	break;
47b1a55a SC	137	case IQ2000_OPERAND_JMPTARG :
	138	print_address (cd, info, fields->f_jtarg, 0\|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
	139	break;
	140	case IQ2000_OPERAND_JMPTARGQ10 :
	141	print_address (cd, info, fields->f_jtargq10, 0\|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
	142	break;
	143	case IQ2000_OPERAND_LO16 :
	144	print_normal (cd, info, fields->f_imm, 0, pc, length);
	145	break;
	146	case IQ2000_OPERAND_MASK :
	147	print_normal (cd, info, fields->f_mask, 0, pc, length);
	148	break;
	149	case IQ2000_OPERAND_MASKL :
	150	print_normal (cd, info, fields->f_maskl, 0, pc, length);
	151	break;
	152	case IQ2000_OPERAND_MASKQ10 :
	153	print_normal (cd, info, fields->f_maskq10, 0, pc, length);
	154	break;
	155	case IQ2000_OPERAND_MASKR :
	156	print_normal (cd, info, fields->f_rs, 0, pc, length);
	157	break;
	158	case IQ2000_OPERAND_MLO16 :
	159	print_normal (cd, info, fields->f_imm, 0, pc, length);
	160	break;
	161	case IQ2000_OPERAND_OFFSET :
	162	print_address (cd, info, fields->f_offset, 0\|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
	163	break;
	164	case IQ2000_OPERAND_RD :
	165	print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd, 0);
	166	break;
	167	case IQ2000_OPERAND_RD_RS :
	168	print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rs, 0\|(1<<CGEN_OPERAND_VIRTUAL));
	169	break;
	170	case IQ2000_OPERAND_RD_RT :
	171	print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rt, 0\|(1<<CGEN_OPERAND_VIRTUAL));
	172	break;
	173	case IQ2000_OPERAND_RS :
	174	print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
	175	break;
	176	case IQ2000_OPERAND_RT :
	177	print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt, 0);
	178	break;
	179	case IQ2000_OPERAND_RT_RS :
	180	print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt_rs, 0\|(1<<CGEN_OPERAND_VIRTUAL));
	181	break;
	182	case IQ2000_OPERAND_SHAMT :
	183	print_normal (cd, info, fields->f_shamt, 0, pc, length);
	184	break;
	185
	186	default :
	187	/* xgettext:c-format */
	188	fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
	189	opindex);
	190	abort ();
	191	}
	192	}
	193
43e65147	194	cgen_print_fn * const iq2000_cgen_print_handlers[] =
47b1a55a SC	195	{
	196	print_insn_normal,
	197	};
	198
	199
	200	void
47b0e7ad	201	iq2000_cgen_init_dis (CGEN_CPU_DESC cd)
47b1a55a SC	202	{
	203	iq2000_cgen_init_opcode_table (cd);
	204	iq2000_cgen_init_ibld_table (cd);
	205	cd->print_handlers = & iq2000_cgen_print_handlers[0];
	206	cd->print_operand = iq2000_cgen_print_operand;
	207	}
	208
	209	\f
	210	/* Default print handler. */
	211
	212	static void
ffead7ae MM	213	print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	214	void *dis_info,
	215	long value,
	216	unsigned int attrs,
	217	bfd_vma pc ATTRIBUTE_UNUSED,
	218	int length ATTRIBUTE_UNUSED)
47b1a55a SC	219	{
	220	disassemble_info info = (disassemble_info ) dis_info;
	221
47b1a55a SC	222	/* Print the operand as directed by the attributes. */
	223	if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
	224	; /* nothing to do */
	225	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
	226	(*info->fprintf_func) (info->stream, "%ld", value);
	227	else
	228	(*info->fprintf_func) (info->stream, "0x%lx", value);
	229	}
	230
	231	/* Default address handler. */
	232
	233	static void
ffead7ae MM	234	print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	235	void *dis_info,
	236	bfd_vma value,
	237	unsigned int attrs,
	238	bfd_vma pc ATTRIBUTE_UNUSED,
	239	int length ATTRIBUTE_UNUSED)
47b1a55a SC	240	{
	241	disassemble_info info = (disassemble_info ) dis_info;
	242
47b1a55a SC	243	/* Print the operand as directed by the attributes. */
47b1a55a SC	244	if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
47b0e7ad	245	; /* Nothing to do. */
47b1a55a SC	246	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
	247	(*info->print_address_func) (value, info);
	248	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
	249	(*info->print_address_func) (value, info);
	250	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
	251	(*info->fprintf_func) (info->stream, "%ld", (long) value);
	252	else
	253	(*info->fprintf_func) (info->stream, "0x%lx", (long) value);
	254	}
	255
	256	/* Keyword print handler. */
	257
	258	static void
ffead7ae MM	259	print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	260	void *dis_info,
	261	CGEN_KEYWORD *keyword_table,
	262	long value,
	263	unsigned int attrs ATTRIBUTE_UNUSED)
47b1a55a SC	264	{
	265	disassemble_info info = (disassemble_info ) dis_info;
	266	const CGEN_KEYWORD_ENTRY *ke;
	267
	268	ke = cgen_keyword_lookup_value (keyword_table, value);
	269	if (ke != NULL)
	270	(*info->fprintf_func) (info->stream, "%s", ke->name);
	271	else
	272	(*info->fprintf_func) (info->stream, "???");
	273	}
	274	\f
	275	/* Default insn printer.
	276
ffead7ae	277	DIS_INFO is defined as `void *' so the disassembler needn't know anything
47b1a55a SC	278	about disassemble_info. */
	279
	280	static void
ffead7ae MM	281	print_insn_normal (CGEN_CPU_DESC cd,
	282	void *dis_info,
	283	const CGEN_INSN *insn,
	284	CGEN_FIELDS *fields,
	285	bfd_vma pc,
	286	int length)
47b1a55a SC	287	{
	288	const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
	289	disassemble_info info = (disassemble_info ) dis_info;
	290	const CGEN_SYNTAX_CHAR_TYPE *syn;
	291
	292	CGEN_INIT_PRINT (cd);
	293
	294	for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
	295	{
	296	if (CGEN_SYNTAX_MNEMONIC_P (*syn))
	297	{
	298	(*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
	299	continue;
	300	}
	301	if (CGEN_SYNTAX_CHAR_P (*syn))
	302	{
	303	(info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (syn));
	304	continue;
	305	}
	306
	307	/* We have an operand. */
	308	iq2000_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
	309	fields, CGEN_INSN_ATTRS (insn), pc, length);
	310	}
	311	}
	312	\f
	313	/* Subroutine of print_insn. Reads an insn into the given buffers and updates
	314	the extract info.
	315	Returns 0 if all is well, non-zero otherwise. */
	316
	317	static int
ffead7ae MM	318	read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	319	bfd_vma pc,
	320	disassemble_info *info,
33b71eeb	321	bfd_byte *buf,
ffead7ae MM	322	int buflen,
	323	CGEN_EXTRACT_INFO *ex_info,
	324	unsigned long *insn_value)
47b1a55a SC	325	{
47b1a55a SC	326	int status = (*info->read_memory_func) (pc, buf, buflen, info);
47b0e7ad	327
47b1a55a SC	328	if (status != 0)
	329	{
	330	(*info->memory_error_func) (status, pc, info);
	331	return -1;
	332	}
	333
	334	ex_info->dis_info = info;
	335	ex_info->valid = (1 << buflen) - 1;
	336	ex_info->insn_bytes = buf;
	337
	338	insn_value = bfd_get_bits (buf, buflen 8, info->endian == BFD_ENDIAN_BIG);
	339	return 0;
	340	}
	341
	342	/* Utility to print an insn.
	343	BUF is the base part of the insn, target byte order, BUFLEN bytes long.
	344	The result is the size of the insn in bytes or zero for an unknown insn
	345	or -1 if an error occurs fetching data (memory_error_func will have
	346	been called). */
	347
	348	static int
ffead7ae MM	349	print_insn (CGEN_CPU_DESC cd,
	350	bfd_vma pc,
	351	disassemble_info *info,
33b71eeb	352	bfd_byte *buf,
ffead7ae	353	unsigned int buflen)
47b1a55a SC	354	{
	355	CGEN_INSN_INT insn_value;
	356	const CGEN_INSN_LIST *insn_list;
	357	CGEN_EXTRACT_INFO ex_info;
	358	int basesize;
	359
	360	/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
	361	basesize = cd->base_insn_bitsize < buflen * 8 ?
	362	cd->base_insn_bitsize : buflen * 8;
	363	insn_value = cgen_get_insn_value (cd, buf, basesize);
	364
	365
	366	/* Fill in ex_info fields like read_insn would. Don't actually call
	367	read_insn, since the incoming buffer is already read (and possibly
	368	modified a la m32r). */
	369	ex_info.valid = (1 << buflen) - 1;
	370	ex_info.dis_info = info;
	371	ex_info.insn_bytes = buf;
	372
	373	/* The instructions are stored in hash lists.
	374	Pick the first one and keep trying until we find the right one. */
	375
33b71eeb	376	insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
47b1a55a SC	377	while (insn_list != NULL)
	378	{
	379	const CGEN_INSN *insn = insn_list->insn;
	380	CGEN_FIELDS fields;
	381	int length;
	382	unsigned long insn_value_cropped;
	383
43e65147	384	#ifdef CGEN_VALIDATE_INSN_SUPPORTED
47b1a55a SC	385	/* Not needed as insn shouldn't be in hash lists if not supported. */
	386	/* Supported by this cpu? */
	387	if (! iq2000_cgen_insn_supported (cd, insn))
	388	{
	389	insn_list = CGEN_DIS_NEXT_INSN (insn_list);
	390	continue;
	391	}
	392	#endif
	393
	394	/* Basic bit mask must be correct. */
	395	/* ??? May wish to allow target to defer this check until the extract
	396	handler. */
	397
	398	/* Base size may exceed this instruction's size. Extract the
	399	relevant part from the buffer. */
	400	if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
	401	(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
43e65147	402	insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
47b1a55a SC	403	info->endian == BFD_ENDIAN_BIG);
	404	else
	405	insn_value_cropped = insn_value;
	406
	407	if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
	408	== CGEN_INSN_BASE_VALUE (insn))
	409	{
	410	/* Printing is handled in two passes. The first pass parses the
	411	machine insn and extracts the fields. The second pass prints
	412	them. */
	413
	414	/* Make sure the entire insn is loaded into insn_value, if it
	415	can fit. */
	416	if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
	417	(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	418	{
	419	unsigned long full_insn_value;
	420	int rc = read_insn (cd, pc, info, buf,
	421	CGEN_INSN_BITSIZE (insn) / 8,
	422	& ex_info, & full_insn_value);
	423	if (rc != 0)
	424	return rc;
	425	length = CGEN_EXTRACT_FN (cd, insn)
	426	(cd, insn, &ex_info, full_insn_value, &fields, pc);
	427	}
	428	else
	429	length = CGEN_EXTRACT_FN (cd, insn)
	430	(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
	431
47b0e7ad	432	/* Length < 0 -> error. */
47b1a55a SC	433	if (length < 0)
	434	return length;
	435	if (length > 0)
	436	{
	437	CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
47b0e7ad	438	/* Length is in bits, result is in bytes. */
47b1a55a SC	439	return length / 8;
	440	}
	441	}
	442
	443	insn_list = CGEN_DIS_NEXT_INSN (insn_list);
	444	}
	445
	446	return 0;
	447	}
	448
	449	/* Default value for CGEN_PRINT_INSN.
	450	The result is the size of the insn in bytes or zero for an unknown insn
	451	or -1 if an error occured fetching bytes. */
	452
	453	#ifndef CGEN_PRINT_INSN
	454	#define CGEN_PRINT_INSN default_print_insn
	455	#endif
	456
	457	static int
ffead7ae	458	default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
47b1a55a	459	{
33b71eeb	460	bfd_byte buf[CGEN_MAX_INSN_SIZE];
47b1a55a SC	461	int buflen;
	462	int status;
	463
	464	/* Attempt to read the base part of the insn. */
	465	buflen = cd->base_insn_bitsize / 8;
	466	status = (*info->read_memory_func) (pc, buf, buflen, info);
	467
	468	/* Try again with the minimum part, if min < base. */
	469	if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
	470	{
	471	buflen = cd->min_insn_bitsize / 8;
	472	status = (*info->read_memory_func) (pc, buf, buflen, info);
	473	}
	474
	475	if (status != 0)
	476	{
	477	(*info->memory_error_func) (status, pc, info);
	478	return -1;
	479	}
	480
	481	return print_insn (cd, pc, info, buf, buflen);
	482	}
	483
	484	/* Main entry point.
	485	Print one instruction from PC on INFO->STREAM.
	486	Return the size of the instruction (in bytes). */
	487
47b0e7ad NC	488	typedef struct cpu_desc_list
47b0e7ad NC	489	{
47b1a55a	490	struct cpu_desc_list *next;
a92e0d0a	491	CGEN_BITSET *isa;
47b1a55a SC	492	int mach;
	493	int endian;
	494	CGEN_CPU_DESC cd;
	495	} cpu_desc_list;
	496
	497	int
ffead7ae	498	print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
47b1a55a SC	499	{
	500	static cpu_desc_list *cd_list = 0;
	501	cpu_desc_list *cl = 0;
	502	static CGEN_CPU_DESC cd = 0;
a92e0d0a	503	static CGEN_BITSET *prev_isa;
47b1a55a SC	504	static int prev_mach;
	505	static int prev_endian;
	506	int length;
a92e0d0a L	507	CGEN_BITSET *isa;
a92e0d0a L	508	int mach;
47b1a55a SC	509	int endian = (info->endian == BFD_ENDIAN_BIG
	510	? CGEN_ENDIAN_BIG
	511	: CGEN_ENDIAN_LITTLE);
	512	enum bfd_architecture arch;
	513
	514	/* ??? gdb will set mach but leave the architecture as "unknown" */
	515	#ifndef CGEN_BFD_ARCH
	516	#define CGEN_BFD_ARCH bfd_arch_iq2000
	517	#endif
	518	arch = info->arch;
	519	if (arch == bfd_arch_unknown)
	520	arch = CGEN_BFD_ARCH;
43e65147	521
47b1a55a SC	522	/* There's no standard way to compute the machine or isa number
	523	so we leave it to the target. */
	524	#ifdef CGEN_COMPUTE_MACH
	525	mach = CGEN_COMPUTE_MACH (info);
	526	#else
	527	mach = info->mach;
	528	#endif
	529
	530	#ifdef CGEN_COMPUTE_ISA
a92e0d0a L	531	{
	532	static CGEN_BITSET *permanent_isa;
	533
	534	if (!permanent_isa)
	535	permanent_isa = cgen_bitset_create (MAX_ISAS);
	536	isa = permanent_isa;
	537	cgen_bitset_clear (isa);
	538	cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
	539	}
47b1a55a SC	540	#else
	541	isa = info->insn_sets;
	542	#endif
	543
	544	/* If we've switched cpu's, try to find a handle we've used before */
	545	if (cd
a92e0d0a	546	&& (cgen_bitset_compare (isa, prev_isa) != 0
47b1a55a SC	547	\|\| mach != prev_mach
	548	\|\| endian != prev_endian))
	549	{
	550	cd = 0;
	551	for (cl = cd_list; cl; cl = cl->next)
	552	{
a92e0d0a	553	if (cgen_bitset_compare (cl->isa, isa) == 0 &&
47b1a55a SC	554	cl->mach == mach &&
	555	cl->endian == endian)
	556	{
	557	cd = cl->cd;
a92e0d0a	558	prev_isa = cd->isas;
47b1a55a SC	559	break;
	560	}
	561	}
43e65147	562	}
47b1a55a SC	563
	564	/* If we haven't initialized yet, initialize the opcode table. */
	565	if (! cd)
	566	{
	567	const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
	568	const char *mach_name;
	569
	570	if (!arch_type)
	571	abort ();
	572	mach_name = arch_type->printable_name;
	573
a92e0d0a	574	prev_isa = cgen_bitset_copy (isa);
47b1a55a SC	575	prev_mach = mach;
	576	prev_endian = endian;
	577	cd = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
	578	CGEN_CPU_OPEN_BFDMACH, mach_name,
	579	CGEN_CPU_OPEN_ENDIAN, prev_endian,
	580	CGEN_CPU_OPEN_END);
	581	if (!cd)
	582	abort ();
	583
47b0e7ad	584	/* Save this away for future reference. */
47b1a55a SC	585	cl = xmalloc (sizeof (struct cpu_desc_list));
47b1a55a SC	586	cl->cd = cd;
a92e0d0a	587	cl->isa = prev_isa;
47b1a55a SC	588	cl->mach = mach;
	589	cl->endian = endian;
	590	cl->next = cd_list;
	591	cd_list = cl;
	592
	593	iq2000_cgen_init_dis (cd);
	594	}
	595
	596	/* We try to have as much common code as possible.
	597	But at this point some targets need to take over. */
	598	/* ??? Some targets may need a hook elsewhere. Try to avoid this,
	599	but if not possible try to move this hook elsewhere rather than
	600	have two hooks. */
	601	length = CGEN_PRINT_INSN (cd, pc, info);
	602	if (length > 0)
	603	return length;
	604	if (length < 0)
	605	return -1;
	606
	607	(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
	608	return cd->default_insn_bitsize / 8;
	609	}