[thirdparty/binutils-gdb.git] / opcodes / iq2000-dis.c

/* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
/* Disassembler interface for targets using CGEN. -*- C -*-
   CGEN: Cpu tools GENerator

   THIS FILE IS MACHINE GENERATED WITH CGEN.
   - the resultant file is machine generated, cgen-dis.in isn't

   Copyright (C) 1996-2023 Free Software Foundation, Inc.

   This file is part of libopcodes.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software Foundation, Inc.,
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */

/* ??? Eventually more and more of this stuff can go to cpu-independent files.
   Keep that in mind.  */

#include "sysdep.h"
#include <stdio.h>
#include "ansidecl.h"
#include "disassemble.h"
#include "bfd.h"
#include "symcat.h"
#include "libiberty.h"
#include "iq2000-desc.h"
#include "iq2000-opc.h"
#include "opintl.h"

/* Default text to print if an instruction isn't recognized.  */
#define UNKNOWN_INSN_MSG _("*unknown*")

static void print_normal
  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
static void print_address
  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
static void print_keyword
  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
static void print_insn_normal
  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
static int print_insn
  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, bfd_byte *, unsigned);
static int default_print_insn
  (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
static int read_insn
  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
   unsigned long *);
\f
/* -- disassembler routines inserted here.  */


void iq2000_cgen_print_operand
  (CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);

/* Main entry point for printing operands.
   XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
   of dis-asm.h on cgen.h.

   This function is basically just a big switch statement.  Earlier versions
   used tables to look up the function to use, but
   - if the table contains both assembler and disassembler functions then
     the disassembler contains much of the assembler and vice-versa,
   - there's a lot of inlining possibilities as things grow,
   - using a switch statement avoids the function call overhead.

   This function could be moved into `print_insn_normal', but keeping it
   separate makes clear the interface between `print_insn_normal' and each of
   the handlers.  */

void
iq2000_cgen_print_operand (CGEN_CPU_DESC cd,
			   int opindex,
			   void * xinfo,
			   CGEN_FIELDS *fields,
			   void const *attrs ATTRIBUTE_UNUSED,
			   bfd_vma pc,
			   int length)
{
  disassemble_info *info = (disassemble_info *) xinfo;

  switch (opindex)
    {
    case IQ2000_OPERAND__INDEX :
      print_normal (cd, info, fields->f_index, 0, pc, length);
      break;
    case IQ2000_OPERAND_BASE :
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
      break;
    case IQ2000_OPERAND_BASEOFF :
      print_address (cd, info, fields->f_imm, 0, pc, length);
      break;
    case IQ2000_OPERAND_BITNUM :
      print_normal (cd, info, fields->f_rt, 0, pc, length);
      break;
    case IQ2000_OPERAND_BYTECOUNT :
      print_normal (cd, info, fields->f_bytecount, 0, pc, length);
      break;
    case IQ2000_OPERAND_CAM_Y :
      print_normal (cd, info, fields->f_cam_y, 0, pc, length);
      break;
    case IQ2000_OPERAND_CAM_Z :
      print_normal (cd, info, fields->f_cam_z, 0, pc, length);
      break;
    case IQ2000_OPERAND_CM_3FUNC :
      print_normal (cd, info, fields->f_cm_3func, 0, pc, length);
      break;
    case IQ2000_OPERAND_CM_3Z :
      print_normal (cd, info, fields->f_cm_3z, 0, pc, length);
      break;
    case IQ2000_OPERAND_CM_4FUNC :
      print_normal (cd, info, fields->f_cm_4func, 0, pc, length);
      break;
    case IQ2000_OPERAND_CM_4Z :
      print_normal (cd, info, fields->f_cm_4z, 0, pc, length);
      break;
    case IQ2000_OPERAND_COUNT :
      print_normal (cd, info, fields->f_count, 0, pc, length);
      break;
    case IQ2000_OPERAND_EXECODE :
      print_normal (cd, info, fields->f_excode, 0, pc, length);
      break;
    case IQ2000_OPERAND_HI16 :
      print_normal (cd, info, fields->f_imm, 0, pc, length);
      break;
    case IQ2000_OPERAND_IMM :
      print_normal (cd, info, fields->f_imm, 0, pc, length);
      break;
    case IQ2000_OPERAND_JMPTARG :
      print_address (cd, info, fields->f_jtarg, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
      break;
    case IQ2000_OPERAND_JMPTARGQ10 :
      print_address (cd, info, fields->f_jtargq10, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
      break;
    case IQ2000_OPERAND_LO16 :
      print_normal (cd, info, fields->f_imm, 0, pc, length);
      break;
    case IQ2000_OPERAND_MASK :
      print_normal (cd, info, fields->f_mask, 0, pc, length);
      break;
    case IQ2000_OPERAND_MASKL :
      print_normal (cd, info, fields->f_maskl, 0, pc, length);
      break;
    case IQ2000_OPERAND_MASKQ10 :
      print_normal (cd, info, fields->f_maskq10, 0, pc, length);
      break;
    case IQ2000_OPERAND_MASKR :
      print_normal (cd, info, fields->f_rs, 0, pc, length);
      break;
    case IQ2000_OPERAND_MLO16 :
      print_normal (cd, info, fields->f_imm, 0, pc, length);
      break;
    case IQ2000_OPERAND_OFFSET :
      print_address (cd, info, fields->f_offset, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
      break;
    case IQ2000_OPERAND_RD :
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd, 0);
      break;
    case IQ2000_OPERAND_RD_RS :
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rs, 0|(1<<CGEN_OPERAND_VIRTUAL));
      break;
    case IQ2000_OPERAND_RD_RT :
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rt, 0|(1<<CGEN_OPERAND_VIRTUAL));
      break;
    case IQ2000_OPERAND_RS :
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
      break;
    case IQ2000_OPERAND_RT :
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt, 0);
      break;
    case IQ2000_OPERAND_RT_RS :
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt_rs, 0|(1<<CGEN_OPERAND_VIRTUAL));
      break;
    case IQ2000_OPERAND_SHAMT :
      print_normal (cd, info, fields->f_shamt, 0, pc, length);
      break;

    default :
      /* xgettext:c-format */
      opcodes_error_handler
	(_("internal error: unrecognized field %d while printing insn"),
	 opindex);
      abort ();
  }
}

cgen_print_fn * const iq2000_cgen_print_handlers[] =
{
  print_insn_normal,
};


void
iq2000_cgen_init_dis (CGEN_CPU_DESC cd)
{
  iq2000_cgen_init_opcode_table (cd);
  iq2000_cgen_init_ibld_table (cd);
  cd->print_handlers = & iq2000_cgen_print_handlers[0];
  cd->print_operand = iq2000_cgen_print_operand;
}

\f
/* Default print handler.  */

static void
print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	      void *dis_info,
	      long value,
	      unsigned int attrs,
	      bfd_vma pc ATTRIBUTE_UNUSED,
	      int length ATTRIBUTE_UNUSED)
{
  disassemble_info *info = (disassemble_info *) dis_info;

  /* Print the operand as directed by the attributes.  */
  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
    ; /* nothing to do */
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
    (*info->fprintf_func) (info->stream, "%ld", value);
  else
    (*info->fprintf_func) (info->stream, "0x%lx", value);
}

/* Default address handler.  */

static void
print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	       void *dis_info,
	       bfd_vma value,
	       unsigned int attrs,
	       bfd_vma pc ATTRIBUTE_UNUSED,
	       int length ATTRIBUTE_UNUSED)
{
  disassemble_info *info = (disassemble_info *) dis_info;

  /* Print the operand as directed by the attributes.  */
  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
    ; /* Nothing to do.  */
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
    (*info->print_address_func) (value, info);
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
    (*info->print_address_func) (value, info);
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
    (*info->fprintf_func) (info->stream, "%ld", (long) value);
  else
    (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
}

/* Keyword print handler.  */

static void
print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	       void *dis_info,
	       CGEN_KEYWORD *keyword_table,
	       long value,
	       unsigned int attrs ATTRIBUTE_UNUSED)
{
  disassemble_info *info = (disassemble_info *) dis_info;
  const CGEN_KEYWORD_ENTRY *ke;

  ke = cgen_keyword_lookup_value (keyword_table, value);
  if (ke != NULL)
    (*info->fprintf_func) (info->stream, "%s", ke->name);
  else
    (*info->fprintf_func) (info->stream, "???");
}
\f
/* Default insn printer.

   DIS_INFO is defined as `void *' so the disassembler needn't know anything
   about disassemble_info.  */

static void
print_insn_normal (CGEN_CPU_DESC cd,
		   void *dis_info,
		   const CGEN_INSN *insn,
		   CGEN_FIELDS *fields,
		   bfd_vma pc,
		   int length)
{
  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
  disassemble_info *info = (disassemble_info *) dis_info;
  const CGEN_SYNTAX_CHAR_TYPE *syn;

  CGEN_INIT_PRINT (cd);

  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
    {
      if (CGEN_SYNTAX_MNEMONIC_P (*syn))
	{
	  (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
	  continue;
	}
      if (CGEN_SYNTAX_CHAR_P (*syn))
	{
	  (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
	  continue;
	}

      /* We have an operand.  */
      iq2000_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
				 fields, CGEN_INSN_ATTRS (insn), pc, length);
    }
}
\f
/* Subroutine of print_insn. Reads an insn into the given buffers and updates
   the extract info.
   Returns 0 if all is well, non-zero otherwise.  */

static int
read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	   bfd_vma pc,
	   disassemble_info *info,
	   bfd_byte *buf,
	   int buflen,
	   CGEN_EXTRACT_INFO *ex_info,
	   unsigned long *insn_value)
{
  int status = (*info->read_memory_func) (pc, buf, buflen, info);

  if (status != 0)
    {
      (*info->memory_error_func) (status, pc, info);
      return -1;
    }

  ex_info->dis_info = info;
  ex_info->valid = (1 << buflen) - 1;
  ex_info->insn_bytes = buf;

  *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
  return 0;
}

/* Utility to print an insn.
   BUF is the base part of the insn, target byte order, BUFLEN bytes long.
   The result is the size of the insn in bytes or zero for an unknown insn
   or -1 if an error occurs fetching data (memory_error_func will have
   been called).  */

static int
print_insn (CGEN_CPU_DESC cd,
	    bfd_vma pc,
	    disassemble_info *info,
	    bfd_byte *buf,
	    unsigned int buflen)
{
  CGEN_INSN_INT insn_value;
  const CGEN_INSN_LIST *insn_list;
  CGEN_EXTRACT_INFO ex_info;
  int basesize;

  /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
  basesize = cd->base_insn_bitsize < buflen * 8 ?
                                     cd->base_insn_bitsize : buflen * 8;
  insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);


  /* Fill in ex_info fields like read_insn would.  Don't actually call
     read_insn, since the incoming buffer is already read (and possibly
     modified a la m32r).  */
  ex_info.valid = (1 << buflen) - 1;
  ex_info.dis_info = info;
  ex_info.insn_bytes = buf;

  /* The instructions are stored in hash lists.
     Pick the first one and keep trying until we find the right one.  */

  insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
  while (insn_list != NULL)
    {
      const CGEN_INSN *insn = insn_list->insn;
      CGEN_FIELDS fields;
      int length;
      unsigned long insn_value_cropped;

#ifdef CGEN_VALIDATE_INSN_SUPPORTED
      /* Not needed as insn shouldn't be in hash lists if not supported.  */
      /* Supported by this cpu?  */
      if (! iq2000_cgen_insn_supported (cd, insn))
        {
          insn_list = CGEN_DIS_NEXT_INSN (insn_list);
	  continue;
        }
#endif

      /* Basic bit mask must be correct.  */
      /* ??? May wish to allow target to defer this check until the extract
	 handler.  */

      /* Base size may exceed this instruction's size.  Extract the
         relevant part from the buffer. */
      if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
	  (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
					   info->endian == BFD_ENDIAN_BIG);
      else
	insn_value_cropped = insn_value;

      if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
	  == CGEN_INSN_BASE_VALUE (insn))
	{
	  /* Printing is handled in two passes.  The first pass parses the
	     machine insn and extracts the fields.  The second pass prints
	     them.  */

	  /* Make sure the entire insn is loaded into insn_value, if it
	     can fit.  */
	  if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
	      (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	    {
	      unsigned long full_insn_value;
	      int rc = read_insn (cd, pc, info, buf,
				  CGEN_INSN_BITSIZE (insn) / 8,
				  & ex_info, & full_insn_value);
	      if (rc != 0)
		return rc;
	      length = CGEN_EXTRACT_FN (cd, insn)
		(cd, insn, &ex_info, full_insn_value, &fields, pc);
	    }
	  else
	    length = CGEN_EXTRACT_FN (cd, insn)
	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);

	  /* Length < 0 -> error.  */
	  if (length < 0)
	    return length;
	  if (length > 0)
	    {
	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
	      /* Length is in bits, result is in bytes.  */
	      return length / 8;
	    }
	}

      insn_list = CGEN_DIS_NEXT_INSN (insn_list);
    }

  return 0;
}

/* Default value for CGEN_PRINT_INSN.
   The result is the size of the insn in bytes or zero for an unknown insn
   or -1 if an error occured fetching bytes.  */

#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
#endif

static int
default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
{
  bfd_byte buf[CGEN_MAX_INSN_SIZE];
  int buflen;
  int status;

  /* Attempt to read the base part of the insn.  */
  buflen = cd->base_insn_bitsize / 8;
  status = (*info->read_memory_func) (pc, buf, buflen, info);

  /* Try again with the minimum part, if min < base.  */
  if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
    {
      buflen = cd->min_insn_bitsize / 8;
      status = (*info->read_memory_func) (pc, buf, buflen, info);
    }

  if (status != 0)
    {
      (*info->memory_error_func) (status, pc, info);
      return -1;
    }

  return print_insn (cd, pc, info, buf, buflen);
}

/* Main entry point.
   Print one instruction from PC on INFO->STREAM.
   Return the size of the instruction (in bytes).  */

typedef struct cpu_desc_list
{
  struct cpu_desc_list *next;
  CGEN_BITSET *isa;
  int mach;
  int endian;
  int insn_endian;
  CGEN_CPU_DESC cd;
} cpu_desc_list;

int
print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
{
  static cpu_desc_list *cd_list = 0;
  cpu_desc_list *cl = 0;
  static CGEN_CPU_DESC cd = 0;
  static CGEN_BITSET *prev_isa;
  static int prev_mach;
  static int prev_endian;
  static int prev_insn_endian;
  int length;
  CGEN_BITSET *isa;
  int mach;
  int endian = (info->endian == BFD_ENDIAN_BIG
		? CGEN_ENDIAN_BIG
		: CGEN_ENDIAN_LITTLE);
  int insn_endian = (info->endian_code == BFD_ENDIAN_BIG
                     ? CGEN_ENDIAN_BIG
                     : CGEN_ENDIAN_LITTLE);
  enum bfd_architecture arch;

  /* ??? gdb will set mach but leave the architecture as "unknown" */
#ifndef CGEN_BFD_ARCH
#define CGEN_BFD_ARCH bfd_arch_iq2000
#endif
  arch = info->arch;
  if (arch == bfd_arch_unknown)
    arch = CGEN_BFD_ARCH;

  /* There's no standard way to compute the machine or isa number
     so we leave it to the target.  */
#ifdef CGEN_COMPUTE_MACH
  mach = CGEN_COMPUTE_MACH (info);
#else
  mach = info->mach;
#endif

#ifdef CGEN_COMPUTE_ISA
  {
    static CGEN_BITSET *permanent_isa;

    if (!permanent_isa)
      permanent_isa = cgen_bitset_create (MAX_ISAS);
    isa = permanent_isa;
    cgen_bitset_clear (isa);
    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
  }
#else
  isa = info->private_data;
#endif

  /* If we've switched cpu's, try to find a handle we've used before */
  if (cd
      && (cgen_bitset_compare (isa, prev_isa) != 0
	  || mach != prev_mach
	  || endian != prev_endian))
    {
      cd = 0;
      for (cl = cd_list; cl; cl = cl->next)
	{
	  if (cgen_bitset_compare (cl->isa, isa) == 0 &&
	      cl->mach == mach &&
	      cl->endian == endian)
	    {
	      cd = cl->cd;
 	      prev_isa = cd->isas;
	      break;
	    }
	}
    }

  /* If we haven't initialized yet, initialize the opcode table.  */
  if (! cd)
    {
      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
      const char *mach_name;

      if (!arch_type)
	abort ();
      mach_name = arch_type->printable_name;

      prev_isa = cgen_bitset_copy (isa);
      prev_mach = mach;
      prev_endian = endian;
      prev_insn_endian = insn_endian;
      cd = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
				 CGEN_CPU_OPEN_BFDMACH, mach_name,
				 CGEN_CPU_OPEN_ENDIAN, prev_endian,
                                 CGEN_CPU_OPEN_INSN_ENDIAN, prev_insn_endian,
				 CGEN_CPU_OPEN_END);
      if (!cd)
	abort ();

      /* Save this away for future reference.  */
      cl = xmalloc (sizeof (struct cpu_desc_list));
      cl->cd = cd;
      cl->isa = prev_isa;
      cl->mach = mach;
      cl->endian = endian;
      cl->next = cd_list;
      cd_list = cl;

      iq2000_cgen_init_dis (cd);
    }

  /* We try to have as much common code as possible.
     But at this point some targets need to take over.  */
  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
     but if not possible try to move this hook elsewhere rather than
     have two hooks.  */
  length = CGEN_PRINT_INSN (cd, pc, info);
  if (length > 0)
    return length;
  if (length < 0)
    return -1;

  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
  return cd->default_insn_bitsize / 8;
}
Commit	Line	Data
4162bb66	1	/* DO NOT EDIT! -- buffer-read-only: t -- vi:set ro: */
47b1a55a SC	2	/* Disassembler interface for targets using CGEN. -- C --
	3	CGEN: Cpu tools GENerator
	4
47b0e7ad NC	5	THIS FILE IS MACHINE GENERATED WITH CGEN.
47b0e7ad NC	6	- the resultant file is machine generated, cgen-dis.in isn't
47b1a55a	7
d87bef3a	8	Copyright (C) 1996-2023 Free Software Foundation, Inc.
47b1a55a	9
9b201bb5	10	This file is part of libopcodes.
47b1a55a	11
9b201bb5	12	This library is free software; you can redistribute it and/or modify
47b0e7ad	13	it under the terms of the GNU General Public License as published by
9b201bb5	14	the Free Software Foundation; either version 3, or (at your option)
47b0e7ad	15	any later version.
47b1a55a	16
9b201bb5 NC	17	It is distributed in the hope that it will be useful, but WITHOUT
	18	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	19	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	20	License for more details.
47b1a55a	21
47b0e7ad NC	22	You should have received a copy of the GNU General Public License
	23	along with this program; if not, write to the Free Software Foundation, Inc.,
	24	51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
47b1a55a SC	25
	26	/* ??? Eventually more and more of this stuff can go to cpu-independent files.
	27	Keep that in mind. */
	28
	29	#include "sysdep.h"
	30	#include <stdio.h>
	31	#include "ansidecl.h"
88c1242d	32	#include "disassemble.h"
47b1a55a SC	33	#include "bfd.h"
47b1a55a SC	34	#include "symcat.h"
75798298	35	#include "libiberty.h"
47b1a55a SC	36	#include "iq2000-desc.h"
	37	#include "iq2000-opc.h"
	38	#include "opintl.h"
	39
	40	/* Default text to print if an instruction isn't recognized. */
	41	#define UNKNOWN_INSN_MSG _("unknown")
	42
	43	static void print_normal
ffead7ae	44	(CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
47b1a55a	45	static void print_address
bf143b25	46	(CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
47b1a55a	47	static void print_keyword
bf143b25	48	(CGEN_CPU_DESC, void , CGEN_KEYWORD , long, unsigned int) ATTRIBUTE_UNUSED;
47b1a55a	49	static void print_insn_normal
ffead7ae	50	(CGEN_CPU_DESC, void , const CGEN_INSN , CGEN_FIELDS *, bfd_vma, int);
47b1a55a	51	static int print_insn
33b71eeb	52	(CGEN_CPU_DESC, bfd_vma, disassemble_info , bfd_byte , unsigned);
47b1a55a	53	static int default_print_insn
bf143b25	54	(CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
47b1a55a	55	static int read_insn
33b71eeb	56	(CGEN_CPU_DESC, bfd_vma, disassemble_info , bfd_byte , int, CGEN_EXTRACT_INFO *,
ffead7ae	57	unsigned long *);
47b1a55a	58	\f
47b0e7ad	59	/* -- disassembler routines inserted here. */
47b1a55a SC	60
	61
	62	void iq2000_cgen_print_operand
0dfdb523	63	(CGEN_CPU_DESC, int, void , CGEN_FIELDS , void const *, bfd_vma, int);
47b1a55a SC	64
	65	/* Main entry point for printing operands.
	66	XINFO is a `void ' and not a `disassemble_info ' to not put a requirement
	67	of dis-asm.h on cgen.h.
	68
	69	This function is basically just a big switch statement. Earlier versions
	70	used tables to look up the function to use, but
	71	- if the table contains both assembler and disassembler functions then
	72	the disassembler contains much of the assembler and vice-versa,
	73	- there's a lot of inlining possibilities as things grow,
	74	- using a switch statement avoids the function call overhead.
	75
	76	This function could be moved into `print_insn_normal', but keeping it
	77	separate makes clear the interface between `print_insn_normal' and each of
	78	the handlers. */
	79
	80	void
47b0e7ad NC	81	iq2000_cgen_print_operand (CGEN_CPU_DESC cd,
	82	int opindex,
	83	void * xinfo,
	84	CGEN_FIELDS *fields,
	85	void const *attrs ATTRIBUTE_UNUSED,
	86	bfd_vma pc,
	87	int length)
47b1a55a	88	{
47b0e7ad	89	disassemble_info info = (disassemble_info ) xinfo;
47b1a55a SC	90
	91	switch (opindex)
	92	{
4030fa5a NC	93	case IQ2000_OPERAND__INDEX :
	94	print_normal (cd, info, fields->f_index, 0, pc, length);
	95	break;
47b1a55a SC	96	case IQ2000_OPERAND_BASE :
	97	print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
	98	break;
	99	case IQ2000_OPERAND_BASEOFF :
	100	print_address (cd, info, fields->f_imm, 0, pc, length);
	101	break;
	102	case IQ2000_OPERAND_BITNUM :
	103	print_normal (cd, info, fields->f_rt, 0, pc, length);
	104	break;
	105	case IQ2000_OPERAND_BYTECOUNT :
	106	print_normal (cd, info, fields->f_bytecount, 0, pc, length);
	107	break;
	108	case IQ2000_OPERAND_CAM_Y :
	109	print_normal (cd, info, fields->f_cam_y, 0, pc, length);
	110	break;
	111	case IQ2000_OPERAND_CAM_Z :
	112	print_normal (cd, info, fields->f_cam_z, 0, pc, length);
	113	break;
	114	case IQ2000_OPERAND_CM_3FUNC :
	115	print_normal (cd, info, fields->f_cm_3func, 0, pc, length);
	116	break;
	117	case IQ2000_OPERAND_CM_3Z :
	118	print_normal (cd, info, fields->f_cm_3z, 0, pc, length);
	119	break;
	120	case IQ2000_OPERAND_CM_4FUNC :
	121	print_normal (cd, info, fields->f_cm_4func, 0, pc, length);
	122	break;
	123	case IQ2000_OPERAND_CM_4Z :
	124	print_normal (cd, info, fields->f_cm_4z, 0, pc, length);
	125	break;
	126	case IQ2000_OPERAND_COUNT :
	127	print_normal (cd, info, fields->f_count, 0, pc, length);
	128	break;
	129	case IQ2000_OPERAND_EXECODE :
	130	print_normal (cd, info, fields->f_excode, 0, pc, length);
	131	break;
	132	case IQ2000_OPERAND_HI16 :
	133	print_normal (cd, info, fields->f_imm, 0, pc, length);
	134	break;
	135	case IQ2000_OPERAND_IMM :
	136	print_normal (cd, info, fields->f_imm, 0, pc, length);
	137	break;
47b1a55a SC	138	case IQ2000_OPERAND_JMPTARG :
	139	print_address (cd, info, fields->f_jtarg, 0\|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
	140	break;
	141	case IQ2000_OPERAND_JMPTARGQ10 :
	142	print_address (cd, info, fields->f_jtargq10, 0\|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
	143	break;
	144	case IQ2000_OPERAND_LO16 :
	145	print_normal (cd, info, fields->f_imm, 0, pc, length);
	146	break;
	147	case IQ2000_OPERAND_MASK :
	148	print_normal (cd, info, fields->f_mask, 0, pc, length);
	149	break;
	150	case IQ2000_OPERAND_MASKL :
	151	print_normal (cd, info, fields->f_maskl, 0, pc, length);
	152	break;
	153	case IQ2000_OPERAND_MASKQ10 :
	154	print_normal (cd, info, fields->f_maskq10, 0, pc, length);
	155	break;
	156	case IQ2000_OPERAND_MASKR :
	157	print_normal (cd, info, fields->f_rs, 0, pc, length);
	158	break;
	159	case IQ2000_OPERAND_MLO16 :
	160	print_normal (cd, info, fields->f_imm, 0, pc, length);
	161	break;
	162	case IQ2000_OPERAND_OFFSET :
	163	print_address (cd, info, fields->f_offset, 0\|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
	164	break;
	165	case IQ2000_OPERAND_RD :
	166	print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd, 0);
	167	break;
	168	case IQ2000_OPERAND_RD_RS :
	169	print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rs, 0\|(1<<CGEN_OPERAND_VIRTUAL));
	170	break;
	171	case IQ2000_OPERAND_RD_RT :
	172	print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rt, 0\|(1<<CGEN_OPERAND_VIRTUAL));
	173	break;
	174	case IQ2000_OPERAND_RS :
	175	print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
	176	break;
	177	case IQ2000_OPERAND_RT :
	178	print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt, 0);
	179	break;
	180	case IQ2000_OPERAND_RT_RS :
	181	print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt_rs, 0\|(1<<CGEN_OPERAND_VIRTUAL));
	182	break;
	183	case IQ2000_OPERAND_SHAMT :
	184	print_normal (cd, info, fields->f_shamt, 0, pc, length);
	185	break;
	186
	187	default :
	188	/* xgettext:c-format */
a6743a54 AM	189	opcodes_error_handler
	190	(_("internal error: unrecognized field %d while printing insn"),
	191	opindex);
	192	abort ();
47b1a55a SC	193	}
	194	}
	195
43e65147	196	cgen_print_fn * const iq2000_cgen_print_handlers[] =
47b1a55a SC	197	{
	198	print_insn_normal,
	199	};
	200
	201
	202	void
47b0e7ad	203	iq2000_cgen_init_dis (CGEN_CPU_DESC cd)
47b1a55a SC	204	{
	205	iq2000_cgen_init_opcode_table (cd);
	206	iq2000_cgen_init_ibld_table (cd);
	207	cd->print_handlers = & iq2000_cgen_print_handlers[0];
	208	cd->print_operand = iq2000_cgen_print_operand;
	209	}
	210
	211	\f
	212	/* Default print handler. */
	213
	214	static void
ffead7ae MM	215	print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	216	void *dis_info,
	217	long value,
	218	unsigned int attrs,
	219	bfd_vma pc ATTRIBUTE_UNUSED,
	220	int length ATTRIBUTE_UNUSED)
47b1a55a SC	221	{
	222	disassemble_info info = (disassemble_info ) dis_info;
	223
47b1a55a SC	224	/* Print the operand as directed by the attributes. */
	225	if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
	226	; /* nothing to do */
	227	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
	228	(*info->fprintf_func) (info->stream, "%ld", value);
	229	else
	230	(*info->fprintf_func) (info->stream, "0x%lx", value);
	231	}
	232
	233	/* Default address handler. */
	234
	235	static void
ffead7ae MM	236	print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	237	void *dis_info,
	238	bfd_vma value,
	239	unsigned int attrs,
	240	bfd_vma pc ATTRIBUTE_UNUSED,
	241	int length ATTRIBUTE_UNUSED)
47b1a55a SC	242	{
	243	disassemble_info info = (disassemble_info ) dis_info;
	244
47b1a55a SC	245	/* Print the operand as directed by the attributes. */
47b1a55a SC	246	if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
47b0e7ad	247	; /* Nothing to do. */
47b1a55a SC	248	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
	249	(*info->print_address_func) (value, info);
	250	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
	251	(*info->print_address_func) (value, info);
	252	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
	253	(*info->fprintf_func) (info->stream, "%ld", (long) value);
	254	else
	255	(*info->fprintf_func) (info->stream, "0x%lx", (long) value);
	256	}
	257
	258	/* Keyword print handler. */
	259
	260	static void
ffead7ae MM	261	print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	262	void *dis_info,
	263	CGEN_KEYWORD *keyword_table,
	264	long value,
	265	unsigned int attrs ATTRIBUTE_UNUSED)
47b1a55a SC	266	{
	267	disassemble_info info = (disassemble_info ) dis_info;
	268	const CGEN_KEYWORD_ENTRY *ke;
	269
	270	ke = cgen_keyword_lookup_value (keyword_table, value);
	271	if (ke != NULL)
	272	(*info->fprintf_func) (info->stream, "%s", ke->name);
	273	else
	274	(*info->fprintf_func) (info->stream, "???");
	275	}
	276	\f
	277	/* Default insn printer.
	278
ffead7ae	279	DIS_INFO is defined as `void *' so the disassembler needn't know anything
47b1a55a SC	280	about disassemble_info. */
	281
	282	static void
ffead7ae MM	283	print_insn_normal (CGEN_CPU_DESC cd,
	284	void *dis_info,
	285	const CGEN_INSN *insn,
	286	CGEN_FIELDS *fields,
	287	bfd_vma pc,
	288	int length)
47b1a55a SC	289	{
	290	const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
	291	disassemble_info info = (disassemble_info ) dis_info;
	292	const CGEN_SYNTAX_CHAR_TYPE *syn;
	293
	294	CGEN_INIT_PRINT (cd);
	295
	296	for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
	297	{
	298	if (CGEN_SYNTAX_MNEMONIC_P (*syn))
	299	{
	300	(*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
	301	continue;
	302	}
	303	if (CGEN_SYNTAX_CHAR_P (*syn))
	304	{
	305	(info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (syn));
	306	continue;
	307	}
	308
	309	/* We have an operand. */
	310	iq2000_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
	311	fields, CGEN_INSN_ATTRS (insn), pc, length);
	312	}
	313	}
	314	\f
	315	/* Subroutine of print_insn. Reads an insn into the given buffers and updates
	316	the extract info.
	317	Returns 0 if all is well, non-zero otherwise. */
	318
	319	static int
ffead7ae MM	320	read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	321	bfd_vma pc,
	322	disassemble_info *info,
33b71eeb	323	bfd_byte *buf,
ffead7ae MM	324	int buflen,
	325	CGEN_EXTRACT_INFO *ex_info,
	326	unsigned long *insn_value)
47b1a55a SC	327	{
47b1a55a SC	328	int status = (*info->read_memory_func) (pc, buf, buflen, info);
47b0e7ad	329
47b1a55a SC	330	if (status != 0)
	331	{
	332	(*info->memory_error_func) (status, pc, info);
	333	return -1;
	334	}
	335
	336	ex_info->dis_info = info;
	337	ex_info->valid = (1 << buflen) - 1;
	338	ex_info->insn_bytes = buf;
	339
	340	insn_value = bfd_get_bits (buf, buflen 8, info->endian == BFD_ENDIAN_BIG);
	341	return 0;
	342	}
	343
	344	/* Utility to print an insn.
	345	BUF is the base part of the insn, target byte order, BUFLEN bytes long.
	346	The result is the size of the insn in bytes or zero for an unknown insn
	347	or -1 if an error occurs fetching data (memory_error_func will have
	348	been called). */
	349
	350	static int
ffead7ae MM	351	print_insn (CGEN_CPU_DESC cd,
	352	bfd_vma pc,
	353	disassemble_info *info,
33b71eeb	354	bfd_byte *buf,
ffead7ae	355	unsigned int buflen)
47b1a55a SC	356	{
	357	CGEN_INSN_INT insn_value;
	358	const CGEN_INSN_LIST *insn_list;
	359	CGEN_EXTRACT_INFO ex_info;
	360	int basesize;
	361
	362	/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
	363	basesize = cd->base_insn_bitsize < buflen * 8 ?
	364	cd->base_insn_bitsize : buflen * 8;
e9bffec9	365	insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
47b1a55a SC	366
	367
	368	/* Fill in ex_info fields like read_insn would. Don't actually call
	369	read_insn, since the incoming buffer is already read (and possibly
	370	modified a la m32r). */
	371	ex_info.valid = (1 << buflen) - 1;
	372	ex_info.dis_info = info;
	373	ex_info.insn_bytes = buf;
	374
	375	/* The instructions are stored in hash lists.
	376	Pick the first one and keep trying until we find the right one. */
	377
33b71eeb	378	insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
47b1a55a SC	379	while (insn_list != NULL)
	380	{
	381	const CGEN_INSN *insn = insn_list->insn;
	382	CGEN_FIELDS fields;
	383	int length;
	384	unsigned long insn_value_cropped;
	385
43e65147	386	#ifdef CGEN_VALIDATE_INSN_SUPPORTED
47b1a55a SC	387	/* Not needed as insn shouldn't be in hash lists if not supported. */
	388	/* Supported by this cpu? */
	389	if (! iq2000_cgen_insn_supported (cd, insn))
	390	{
	391	insn_list = CGEN_DIS_NEXT_INSN (insn_list);
	392	continue;
	393	}
	394	#endif
	395
	396	/* Basic bit mask must be correct. */
	397	/* ??? May wish to allow target to defer this check until the extract
	398	handler. */
	399
	400	/* Base size may exceed this instruction's size. Extract the
	401	relevant part from the buffer. */
	402	if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
	403	(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
43e65147	404	insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
47b1a55a SC	405	info->endian == BFD_ENDIAN_BIG);
	406	else
	407	insn_value_cropped = insn_value;
	408
	409	if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
	410	== CGEN_INSN_BASE_VALUE (insn))
	411	{
	412	/* Printing is handled in two passes. The first pass parses the
	413	machine insn and extracts the fields. The second pass prints
	414	them. */
	415
	416	/* Make sure the entire insn is loaded into insn_value, if it
	417	can fit. */
	418	if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
	419	(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	420	{
	421	unsigned long full_insn_value;
	422	int rc = read_insn (cd, pc, info, buf,
	423	CGEN_INSN_BITSIZE (insn) / 8,
	424	& ex_info, & full_insn_value);
	425	if (rc != 0)
	426	return rc;
	427	length = CGEN_EXTRACT_FN (cd, insn)
	428	(cd, insn, &ex_info, full_insn_value, &fields, pc);
	429	}
	430	else
	431	length = CGEN_EXTRACT_FN (cd, insn)
	432	(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
	433
47b0e7ad	434	/* Length < 0 -> error. */
47b1a55a SC	435	if (length < 0)
	436	return length;
	437	if (length > 0)
	438	{
	439	CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
47b0e7ad	440	/* Length is in bits, result is in bytes. */
47b1a55a SC	441	return length / 8;
	442	}
	443	}
	444
	445	insn_list = CGEN_DIS_NEXT_INSN (insn_list);
	446	}
	447
	448	return 0;
	449	}
	450
	451	/* Default value for CGEN_PRINT_INSN.
	452	The result is the size of the insn in bytes or zero for an unknown insn
	453	or -1 if an error occured fetching bytes. */
	454
	455	#ifndef CGEN_PRINT_INSN
	456	#define CGEN_PRINT_INSN default_print_insn
	457	#endif
	458
	459	static int
ffead7ae	460	default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
47b1a55a	461	{
33b71eeb	462	bfd_byte buf[CGEN_MAX_INSN_SIZE];
47b1a55a SC	463	int buflen;
	464	int status;
	465
	466	/* Attempt to read the base part of the insn. */
	467	buflen = cd->base_insn_bitsize / 8;
	468	status = (*info->read_memory_func) (pc, buf, buflen, info);
	469
	470	/* Try again with the minimum part, if min < base. */
	471	if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
	472	{
	473	buflen = cd->min_insn_bitsize / 8;
	474	status = (*info->read_memory_func) (pc, buf, buflen, info);
	475	}
	476
	477	if (status != 0)
	478	{
	479	(*info->memory_error_func) (status, pc, info);
	480	return -1;
	481	}
	482
	483	return print_insn (cd, pc, info, buf, buflen);
	484	}
	485
	486	/* Main entry point.
	487	Print one instruction from PC on INFO->STREAM.
	488	Return the size of the instruction (in bytes). */
	489
47b0e7ad NC	490	typedef struct cpu_desc_list
47b0e7ad NC	491	{
47b1a55a	492	struct cpu_desc_list *next;
a92e0d0a	493	CGEN_BITSET *isa;
47b1a55a SC	494	int mach;
47b1a55a SC	495	int endian;
b3db6d07	496	int insn_endian;
47b1a55a SC	497	CGEN_CPU_DESC cd;
	498	} cpu_desc_list;
	499
	500	int
ffead7ae	501	print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
47b1a55a SC	502	{
	503	static cpu_desc_list *cd_list = 0;
	504	cpu_desc_list *cl = 0;
	505	static CGEN_CPU_DESC cd = 0;
a92e0d0a	506	static CGEN_BITSET *prev_isa;
47b1a55a SC	507	static int prev_mach;
47b1a55a SC	508	static int prev_endian;
b3db6d07	509	static int prev_insn_endian;
47b1a55a	510	int length;
a92e0d0a L	511	CGEN_BITSET *isa;
a92e0d0a L	512	int mach;
47b1a55a SC	513	int endian = (info->endian == BFD_ENDIAN_BIG
	514	? CGEN_ENDIAN_BIG
	515	: CGEN_ENDIAN_LITTLE);
b3db6d07 JM	516	int insn_endian = (info->endian_code == BFD_ENDIAN_BIG
	517	? CGEN_ENDIAN_BIG
	518	: CGEN_ENDIAN_LITTLE);
47b1a55a SC	519	enum bfd_architecture arch;
	520
	521	/* ??? gdb will set mach but leave the architecture as "unknown" */
	522	#ifndef CGEN_BFD_ARCH
	523	#define CGEN_BFD_ARCH bfd_arch_iq2000
	524	#endif
	525	arch = info->arch;
	526	if (arch == bfd_arch_unknown)
	527	arch = CGEN_BFD_ARCH;
43e65147	528
47b1a55a SC	529	/* There's no standard way to compute the machine or isa number
	530	so we leave it to the target. */
	531	#ifdef CGEN_COMPUTE_MACH
	532	mach = CGEN_COMPUTE_MACH (info);
	533	#else
	534	mach = info->mach;
	535	#endif
	536
	537	#ifdef CGEN_COMPUTE_ISA
a92e0d0a L	538	{
	539	static CGEN_BITSET *permanent_isa;
	540
	541	if (!permanent_isa)
	542	permanent_isa = cgen_bitset_create (MAX_ISAS);
	543	isa = permanent_isa;
	544	cgen_bitset_clear (isa);
	545	cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
	546	}
47b1a55a	547	#else
103ebbc3	548	isa = info->private_data;
47b1a55a SC	549	#endif
	550
	551	/* If we've switched cpu's, try to find a handle we've used before */
	552	if (cd
a92e0d0a	553	&& (cgen_bitset_compare (isa, prev_isa) != 0
47b1a55a SC	554	\|\| mach != prev_mach
	555	\|\| endian != prev_endian))
	556	{
	557	cd = 0;
	558	for (cl = cd_list; cl; cl = cl->next)
	559	{
a92e0d0a	560	if (cgen_bitset_compare (cl->isa, isa) == 0 &&
47b1a55a SC	561	cl->mach == mach &&
	562	cl->endian == endian)
	563	{
	564	cd = cl->cd;
a92e0d0a	565	prev_isa = cd->isas;
47b1a55a SC	566	break;
	567	}
	568	}
43e65147	569	}
47b1a55a SC	570
	571	/* If we haven't initialized yet, initialize the opcode table. */
	572	if (! cd)
	573	{
	574	const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
	575	const char *mach_name;
	576
	577	if (!arch_type)
	578	abort ();
	579	mach_name = arch_type->printable_name;
	580
a92e0d0a	581	prev_isa = cgen_bitset_copy (isa);
47b1a55a SC	582	prev_mach = mach;
47b1a55a SC	583	prev_endian = endian;
b3db6d07	584	prev_insn_endian = insn_endian;
47b1a55a SC	585	cd = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
	586	CGEN_CPU_OPEN_BFDMACH, mach_name,
	587	CGEN_CPU_OPEN_ENDIAN, prev_endian,
b3db6d07	588	CGEN_CPU_OPEN_INSN_ENDIAN, prev_insn_endian,
47b1a55a SC	589	CGEN_CPU_OPEN_END);
	590	if (!cd)
	591	abort ();
	592
47b0e7ad	593	/* Save this away for future reference. */
47b1a55a SC	594	cl = xmalloc (sizeof (struct cpu_desc_list));
47b1a55a SC	595	cl->cd = cd;
a92e0d0a	596	cl->isa = prev_isa;
47b1a55a SC	597	cl->mach = mach;
	598	cl->endian = endian;
	599	cl->next = cd_list;
	600	cd_list = cl;
	601
	602	iq2000_cgen_init_dis (cd);
	603	}
	604
	605	/* We try to have as much common code as possible.
	606	But at this point some targets need to take over. */
	607	/* ??? Some targets may need a hook elsewhere. Try to avoid this,
	608	but if not possible try to move this hook elsewhere rather than
	609	have two hooks. */
	610	length = CGEN_PRINT_INSN (cd, pc, info);
	611	if (length > 0)
	612	return length;
	613	if (length < 0)
	614	return -1;
	615
	616	(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
	617	return cd->default_insn_bitsize / 8;
	618	}