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4162bb66 1/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
73589c9d 2/* Instruction building/extraction support for or1k. -*- C -*-
87e6d782 3
47b0e7ad
NC
4 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
5 - the resultant file is machine generated, cgen-ibld.in isn't
87e6d782 6
82704155 7 Copyright (C) 1996-2019 Free Software Foundation, Inc.
87e6d782 8
9b201bb5 9 This file is part of libopcodes.
87e6d782 10
9b201bb5 11 This library is free software; you can redistribute it and/or modify
47b0e7ad 12 it under the terms of the GNU General Public License as published by
9b201bb5 13 the Free Software Foundation; either version 3, or (at your option)
47b0e7ad 14 any later version.
87e6d782 15
9b201bb5
NC
16 It is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
87e6d782 20
47b0e7ad
NC
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software Foundation, Inc.,
23 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
87e6d782
NC
24
25/* ??? Eventually more and more of this stuff can go to cpu-independent files.
26 Keep that in mind. */
27
28#include "sysdep.h"
87e6d782
NC
29#include <stdio.h>
30#include "ansidecl.h"
31#include "dis-asm.h"
32#include "bfd.h"
33#include "symcat.h"
73589c9d
CS
34#include "or1k-desc.h"
35#include "or1k-opc.h"
fe8afbc4 36#include "cgen/basic-modes.h"
87e6d782 37#include "opintl.h"
37111cc7 38#include "safe-ctype.h"
87e6d782 39
47b0e7ad 40#undef min
87e6d782 41#define min(a,b) ((a) < (b) ? (a) : (b))
47b0e7ad 42#undef max
87e6d782
NC
43#define max(a,b) ((a) > (b) ? (a) : (b))
44
45/* Used by the ifield rtx function. */
46#define FLD(f) (fields->f)
47
48static const char * insert_normal
ffead7ae
MM
49 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
50 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
87e6d782 51static const char * insert_insn_normal
ffead7ae
MM
52 (CGEN_CPU_DESC, const CGEN_INSN *,
53 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
87e6d782 54static int extract_normal
ffead7ae
MM
55 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
56 unsigned int, unsigned int, unsigned int, unsigned int,
57 unsigned int, unsigned int, bfd_vma, long *);
87e6d782 58static int extract_insn_normal
ffead7ae
MM
59 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
60 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 61#if CGEN_INT_INSN_P
87e6d782 62static void put_insn_int_value
ffead7ae 63 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
0e2ee3ca
NC
64#endif
65#if ! CGEN_INT_INSN_P
66static CGEN_INLINE void insert_1
ffead7ae 67 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
0e2ee3ca 68static CGEN_INLINE int fill_cache
ffead7ae 69 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
0e2ee3ca 70static CGEN_INLINE long extract_1
ffead7ae 71 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
0e2ee3ca 72#endif
87e6d782
NC
73\f
74/* Operand insertion. */
75
76#if ! CGEN_INT_INSN_P
77
78/* Subroutine of insert_normal. */
79
80static CGEN_INLINE void
ffead7ae
MM
81insert_1 (CGEN_CPU_DESC cd,
82 unsigned long value,
83 int start,
84 int length,
85 int word_length,
86 unsigned char *bufp)
87e6d782
NC
87{
88 unsigned long x,mask;
89 int shift;
87e6d782 90
0e2ee3ca 91 x = cgen_get_insn_value (cd, bufp, word_length);
87e6d782
NC
92
93 /* Written this way to avoid undefined behaviour. */
94 mask = (((1L << (length - 1)) - 1) << 1) | 1;
95 if (CGEN_INSN_LSB0_P)
96 shift = (start + 1) - length;
97 else
98 shift = (word_length - (start + length));
99 x = (x & ~(mask << shift)) | ((value & mask) << shift);
100
0e2ee3ca 101 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
87e6d782
NC
102}
103
104#endif /* ! CGEN_INT_INSN_P */
105
106/* Default insertion routine.
107
108 ATTRS is a mask of the boolean attributes.
109 WORD_OFFSET is the offset in bits from the start of the insn of the value.
110 WORD_LENGTH is the length of the word in bits in which the value resides.
111 START is the starting bit number in the word, architecture origin.
112 LENGTH is the length of VALUE in bits.
113 TOTAL_LENGTH is the total length of the insn in bits.
114
115 The result is an error message or NULL if success. */
116
117/* ??? This duplicates functionality with bfd's howto table and
118 bfd_install_relocation. */
119/* ??? This doesn't handle bfd_vma's. Create another function when
120 necessary. */
121
122static const char *
ffead7ae
MM
123insert_normal (CGEN_CPU_DESC cd,
124 long value,
125 unsigned int attrs,
126 unsigned int word_offset,
127 unsigned int start,
128 unsigned int length,
129 unsigned int word_length,
130 unsigned int total_length,
131 CGEN_INSN_BYTES_PTR buffer)
87e6d782
NC
132{
133 static char errbuf[100];
134 /* Written this way to avoid undefined behaviour. */
135 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
136
137 /* If LENGTH is zero, this operand doesn't contribute to the value. */
138 if (length == 0)
139 return NULL;
140
b7cd1872 141 if (word_length > 8 * sizeof (CGEN_INSN_INT))
87e6d782
NC
142 abort ();
143
144 /* For architectures with insns smaller than the base-insn-bitsize,
145 word_length may be too big. */
146 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
147 {
148 if (word_offset == 0
149 && word_length > total_length)
150 word_length = total_length;
151 }
152
153 /* Ensure VALUE will fit. */
fc7bc883
RH
154 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
155 {
156 long minval = - (1L << (length - 1));
157 unsigned long maxval = mask;
43e65147 158
fc7bc883
RH
159 if ((value > 0 && (unsigned long) value > maxval)
160 || value < minval)
161 {
162 /* xgettext:c-format */
163 sprintf (errbuf,
164 _("operand out of range (%ld not between %ld and %lu)"),
165 value, minval, maxval);
166 return errbuf;
167 }
168 }
169 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
87e6d782
NC
170 {
171 unsigned long maxval = mask;
ed963e2d
NC
172 unsigned long val = (unsigned long) value;
173
174 /* For hosts with a word size > 32 check to see if value has been sign
175 extended beyond 32 bits. If so then ignore these higher sign bits
176 as the user is attempting to store a 32-bit signed value into an
177 unsigned 32-bit field which is allowed. */
178 if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
179 val &= 0xFFFFFFFF;
180
181 if (val > maxval)
87e6d782
NC
182 {
183 /* xgettext:c-format */
184 sprintf (errbuf,
ed963e2d
NC
185 _("operand out of range (0x%lx not between 0 and 0x%lx)"),
186 val, maxval);
87e6d782
NC
187 return errbuf;
188 }
189 }
190 else
191 {
192 if (! cgen_signed_overflow_ok_p (cd))
193 {
194 long minval = - (1L << (length - 1));
195 long maxval = (1L << (length - 1)) - 1;
43e65147 196
87e6d782
NC
197 if (value < minval || value > maxval)
198 {
199 sprintf
200 /* xgettext:c-format */
201 (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
202 value, minval, maxval);
203 return errbuf;
204 }
205 }
206 }
207
208#if CGEN_INT_INSN_P
209
210 {
a143b004 211 int shift_within_word, shift_to_word, shift;
87e6d782 212
a143b004
AB
213 /* How to shift the value to BIT0 of the word. */
214 shift_to_word = total_length - (word_offset + word_length);
215
216 /* How to shift the value to the field within the word. */
87e6d782 217 if (CGEN_INSN_LSB0_P)
a143b004 218 shift_within_word = start + 1 - length;
87e6d782 219 else
a143b004
AB
220 shift_within_word = word_length - start - length;
221
222 /* The total SHIFT, then mask in the value. */
223 shift = shift_to_word + shift_within_word;
87e6d782
NC
224 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
225 }
226
227#else /* ! CGEN_INT_INSN_P */
228
229 {
230 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
231
232 insert_1 (cd, value, start, length, word_length, bufp);
233 }
234
235#endif /* ! CGEN_INT_INSN_P */
236
237 return NULL;
238}
239
240/* Default insn builder (insert handler).
241 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
242 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
243 recorded in host byte order, otherwise BUFFER is an array of bytes
244 and the value is recorded in target byte order).
245 The result is an error message or NULL if success. */
246
247static const char *
ffead7ae
MM
248insert_insn_normal (CGEN_CPU_DESC cd,
249 const CGEN_INSN * insn,
250 CGEN_FIELDS * fields,
251 CGEN_INSN_BYTES_PTR buffer,
252 bfd_vma pc)
87e6d782
NC
253{
254 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
255 unsigned long value;
256 const CGEN_SYNTAX_CHAR_TYPE * syn;
257
258 CGEN_INIT_INSERT (cd);
259 value = CGEN_INSN_BASE_VALUE (insn);
260
261 /* If we're recording insns as numbers (rather than a string of bytes),
262 target byte order handling is deferred until later. */
263
264#if CGEN_INT_INSN_P
265
266 put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
267 CGEN_FIELDS_BITSIZE (fields), value);
268
269#else
270
0e2ee3ca
NC
271 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
272 (unsigned) CGEN_FIELDS_BITSIZE (fields)),
87e6d782
NC
273 value);
274
275#endif /* ! CGEN_INT_INSN_P */
276
277 /* ??? It would be better to scan the format's fields.
278 Still need to be able to insert a value based on the operand though;
279 e.g. storing a branch displacement that got resolved later.
280 Needs more thought first. */
281
282 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
283 {
284 const char *errmsg;
285
286 if (CGEN_SYNTAX_CHAR_P (* syn))
287 continue;
288
289 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
290 fields, buffer, pc);
291 if (errmsg)
292 return errmsg;
293 }
294
295 return NULL;
296}
297
0e2ee3ca 298#if CGEN_INT_INSN_P
87e6d782 299/* Cover function to store an insn value into an integral insn. Must go here
47b0e7ad 300 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
87e6d782
NC
301
302static void
ffead7ae
MM
303put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
304 CGEN_INSN_BYTES_PTR buf,
305 int length,
306 int insn_length,
307 CGEN_INSN_INT value)
87e6d782
NC
308{
309 /* For architectures with insns smaller than the base-insn-bitsize,
310 length may be too big. */
311 if (length > insn_length)
312 *buf = value;
313 else
314 {
315 int shift = insn_length - length;
316 /* Written this way to avoid undefined behaviour. */
317 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
47b0e7ad 318
87e6d782
NC
319 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
320 }
321}
0e2ee3ca 322#endif
87e6d782
NC
323\f
324/* Operand extraction. */
325
326#if ! CGEN_INT_INSN_P
327
328/* Subroutine of extract_normal.
329 Ensure sufficient bytes are cached in EX_INFO.
330 OFFSET is the offset in bytes from the start of the insn of the value.
331 BYTES is the length of the needed value.
332 Returns 1 for success, 0 for failure. */
333
334static CGEN_INLINE int
ffead7ae
MM
335fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
336 CGEN_EXTRACT_INFO *ex_info,
337 int offset,
338 int bytes,
339 bfd_vma pc)
87e6d782
NC
340{
341 /* It's doubtful that the middle part has already been fetched so
342 we don't optimize that case. kiss. */
0e2ee3ca 343 unsigned int mask;
87e6d782
NC
344 disassemble_info *info = (disassemble_info *) ex_info->dis_info;
345
346 /* First do a quick check. */
347 mask = (1 << bytes) - 1;
348 if (((ex_info->valid >> offset) & mask) == mask)
349 return 1;
350
351 /* Search for the first byte we need to read. */
352 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
353 if (! (mask & ex_info->valid))
354 break;
355
356 if (bytes)
357 {
358 int status;
359
360 pc += offset;
361 status = (*info->read_memory_func)
362 (pc, ex_info->insn_bytes + offset, bytes, info);
363
364 if (status != 0)
365 {
366 (*info->memory_error_func) (status, pc, info);
367 return 0;
368 }
369
370 ex_info->valid |= ((1 << bytes) - 1) << offset;
371 }
372
373 return 1;
374}
375
376/* Subroutine of extract_normal. */
377
378static CGEN_INLINE long
ffead7ae
MM
379extract_1 (CGEN_CPU_DESC cd,
380 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
381 int start,
382 int length,
383 int word_length,
384 unsigned char *bufp,
385 bfd_vma pc ATTRIBUTE_UNUSED)
87e6d782
NC
386{
387 unsigned long x;
388 int shift;
47b0e7ad 389
e333d2c4
NC
390 x = cgen_get_insn_value (cd, bufp, word_length);
391
87e6d782
NC
392 if (CGEN_INSN_LSB0_P)
393 shift = (start + 1) - length;
394 else
395 shift = (word_length - (start + length));
396 return x >> shift;
397}
398
399#endif /* ! CGEN_INT_INSN_P */
400
401/* Default extraction routine.
402
403 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
404 or sometimes less for cases like the m32r where the base insn size is 32
405 but some insns are 16 bits.
406 ATTRS is a mask of the boolean attributes. We only need `SIGNED',
407 but for generality we take a bitmask of all of them.
408 WORD_OFFSET is the offset in bits from the start of the insn of the value.
409 WORD_LENGTH is the length of the word in bits in which the value resides.
410 START is the starting bit number in the word, architecture origin.
411 LENGTH is the length of VALUE in bits.
412 TOTAL_LENGTH is the total length of the insn in bits.
413
414 Returns 1 for success, 0 for failure. */
415
416/* ??? The return code isn't properly used. wip. */
417
418/* ??? This doesn't handle bfd_vma's. Create another function when
419 necessary. */
420
421static int
ffead7ae 422extract_normal (CGEN_CPU_DESC cd,
87e6d782 423#if ! CGEN_INT_INSN_P
ffead7ae 424 CGEN_EXTRACT_INFO *ex_info,
87e6d782 425#else
ffead7ae 426 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
87e6d782 427#endif
ffead7ae
MM
428 CGEN_INSN_INT insn_value,
429 unsigned int attrs,
430 unsigned int word_offset,
431 unsigned int start,
432 unsigned int length,
433 unsigned int word_length,
434 unsigned int total_length,
87e6d782 435#if ! CGEN_INT_INSN_P
ffead7ae 436 bfd_vma pc,
87e6d782 437#else
ffead7ae 438 bfd_vma pc ATTRIBUTE_UNUSED,
87e6d782 439#endif
ffead7ae 440 long *valuep)
87e6d782 441{
fc7bc883 442 long value, mask;
87e6d782
NC
443
444 /* If LENGTH is zero, this operand doesn't contribute to the value
445 so give it a standard value of zero. */
446 if (length == 0)
447 {
448 *valuep = 0;
449 return 1;
450 }
451
b7cd1872 452 if (word_length > 8 * sizeof (CGEN_INSN_INT))
87e6d782
NC
453 abort ();
454
455 /* For architectures with insns smaller than the insn-base-bitsize,
456 word_length may be too big. */
457 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
458 {
ed963e2d
NC
459 if (word_offset + word_length > total_length)
460 word_length = total_length - word_offset;
87e6d782
NC
461 }
462
fc7bc883 463 /* Does the value reside in INSN_VALUE, and at the right alignment? */
87e6d782 464
fc7bc883 465 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
87e6d782
NC
466 {
467 if (CGEN_INSN_LSB0_P)
468 value = insn_value >> ((word_offset + start + 1) - length);
469 else
470 value = insn_value >> (total_length - ( word_offset + start + length));
471 }
472
473#if ! CGEN_INT_INSN_P
474
475 else
476 {
477 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
478
b7cd1872 479 if (word_length > 8 * sizeof (CGEN_INSN_INT))
87e6d782
NC
480 abort ();
481
482 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
483 return 0;
484
485 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
486 }
487
488#endif /* ! CGEN_INT_INSN_P */
489
490 /* Written this way to avoid undefined behaviour. */
491 mask = (((1L << (length - 1)) - 1) << 1) | 1;
492
493 value &= mask;
494 /* sign extend? */
495 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
496 && (value & (1L << (length - 1))))
497 value |= ~mask;
498
499 *valuep = value;
500
501 return 1;
502}
503
504/* Default insn extractor.
505
506 INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
507 The extracted fields are stored in FIELDS.
508 EX_INFO is used to handle reading variable length insns.
509 Return the length of the insn in bits, or 0 if no match,
510 or -1 if an error occurs fetching data (memory_error_func will have
511 been called). */
512
513static int
ffead7ae
MM
514extract_insn_normal (CGEN_CPU_DESC cd,
515 const CGEN_INSN *insn,
516 CGEN_EXTRACT_INFO *ex_info,
517 CGEN_INSN_INT insn_value,
518 CGEN_FIELDS *fields,
519 bfd_vma pc)
87e6d782
NC
520{
521 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
522 const CGEN_SYNTAX_CHAR_TYPE *syn;
523
524 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
525
526 CGEN_INIT_EXTRACT (cd);
527
528 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
529 {
530 int length;
531
532 if (CGEN_SYNTAX_CHAR_P (*syn))
533 continue;
534
535 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
536 ex_info, insn_value, fields, pc);
537 if (length <= 0)
538 return length;
539 }
540
541 /* We recognized and successfully extracted this insn. */
542 return CGEN_INSN_BITSIZE (insn);
543}
544\f
47b0e7ad 545/* Machine generated code added here. */
87e6d782 546
73589c9d 547const char * or1k_cgen_insert_operand
47b0e7ad 548 (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
0e2ee3ca 549
87e6d782
NC
550/* Main entry point for operand insertion.
551
552 This function is basically just a big switch statement. Earlier versions
553 used tables to look up the function to use, but
554 - if the table contains both assembler and disassembler functions then
555 the disassembler contains much of the assembler and vice-versa,
556 - there's a lot of inlining possibilities as things grow,
557 - using a switch statement avoids the function call overhead.
558
559 This function could be moved into `parse_insn_normal', but keeping it
560 separate makes clear the interface between `parse_insn_normal' and each of
561 the handlers. It's also needed by GAS to insert operands that couldn't be
9a2e995d 562 resolved during parsing. */
87e6d782
NC
563
564const char *
73589c9d 565or1k_cgen_insert_operand (CGEN_CPU_DESC cd,
47b0e7ad
NC
566 int opindex,
567 CGEN_FIELDS * fields,
568 CGEN_INSN_BYTES_PTR buffer,
569 bfd_vma pc ATTRIBUTE_UNUSED)
87e6d782
NC
570{
571 const char * errmsg = NULL;
572 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
573
574 switch (opindex)
575 {
c8e98e36
SH
576 case OR1K_OPERAND_DISP21 :
577 {
578 long value = fields->f_disp21;
579 value = ((((DI) (value) >> (13))) - (((DI) (pc) >> (13))));
580 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 20, 21, 32, total_length, buffer);
581 }
582 break;
73589c9d 583 case OR1K_OPERAND_DISP26 :
87e6d782
NC
584 {
585 long value = fields->f_disp26;
c8e98e36 586 value = ((DI) (((value) - (pc))) >> (2));
87e6d782
NC
587 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, buffer);
588 }
589 break;
73589c9d
CS
590 case OR1K_OPERAND_RA :
591 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
87e6d782 592 break;
73589c9d
CS
593 case OR1K_OPERAND_RADF :
594 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
87e6d782 595 break;
73589c9d
CS
596 case OR1K_OPERAND_RASF :
597 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
87e6d782 598 break;
73589c9d
CS
599 case OR1K_OPERAND_RB :
600 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
87e6d782 601 break;
73589c9d
CS
602 case OR1K_OPERAND_RBDF :
603 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
87e6d782 604 break;
73589c9d 605 case OR1K_OPERAND_RBSF :
87e6d782
NC
606 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
607 break;
73589c9d 608 case OR1K_OPERAND_RD :
87e6d782
NC
609 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
610 break;
73589c9d
CS
611 case OR1K_OPERAND_RDDF :
612 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
87e6d782 613 break;
73589c9d
CS
614 case OR1K_OPERAND_RDSF :
615 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
616 break;
617 case OR1K_OPERAND_SIMM16 :
618 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_SIGN_OPT), 0, 15, 16, 32, total_length, buffer);
619 break;
620 case OR1K_OPERAND_SIMM16_SPLIT :
87e6d782
NC
621 {
622{
73589c9d
CS
623 FLD (f_imm16_25_5) = ((((INT) (FLD (f_simm16_split)) >> (11))) & (31));
624 FLD (f_imm16_10_11) = ((FLD (f_simm16_split)) & (2047));
87e6d782 625}
73589c9d 626 errmsg = insert_normal (cd, fields->f_imm16_25_5, 0, 0, 25, 5, 32, total_length, buffer);
87e6d782
NC
627 if (errmsg)
628 break;
73589c9d 629 errmsg = insert_normal (cd, fields->f_imm16_10_11, 0, 0, 10, 11, 32, total_length, buffer);
87e6d782
NC
630 if (errmsg)
631 break;
632 }
633 break;
73589c9d 634 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
635 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 15, 16, 32, total_length, buffer);
636 break;
73589c9d
CS
637 case OR1K_OPERAND_UIMM16_SPLIT :
638 {
639{
640 FLD (f_imm16_25_5) = ((((UINT) (FLD (f_uimm16_split)) >> (11))) & (31));
641 FLD (f_imm16_10_11) = ((FLD (f_uimm16_split)) & (2047));
642}
643 errmsg = insert_normal (cd, fields->f_imm16_25_5, 0, 0, 25, 5, 32, total_length, buffer);
644 if (errmsg)
645 break;
646 errmsg = insert_normal (cd, fields->f_imm16_10_11, 0, 0, 10, 11, 32, total_length, buffer);
647 if (errmsg)
648 break;
649 }
650 break;
651 case OR1K_OPERAND_UIMM6 :
652 errmsg = insert_normal (cd, fields->f_uimm6, 0, 0, 5, 6, 32, total_length, buffer);
87e6d782
NC
653 break;
654
655 default :
656 /* xgettext:c-format */
a6743a54
AM
657 opcodes_error_handler
658 (_("internal error: unrecognized field %d while building insn"),
659 opindex);
87e6d782
NC
660 abort ();
661 }
662
663 return errmsg;
664}
665
73589c9d 666int or1k_cgen_extract_operand
47b0e7ad 667 (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 668
87e6d782
NC
669/* Main entry point for operand extraction.
670 The result is <= 0 for error, >0 for success.
671 ??? Actual values aren't well defined right now.
672
673 This function is basically just a big switch statement. Earlier versions
674 used tables to look up the function to use, but
675 - if the table contains both assembler and disassembler functions then
676 the disassembler contains much of the assembler and vice-versa,
677 - there's a lot of inlining possibilities as things grow,
678 - using a switch statement avoids the function call overhead.
679
680 This function could be moved into `print_insn_normal', but keeping it
681 separate makes clear the interface between `print_insn_normal' and each of
9a2e995d 682 the handlers. */
87e6d782
NC
683
684int
73589c9d 685or1k_cgen_extract_operand (CGEN_CPU_DESC cd,
47b0e7ad
NC
686 int opindex,
687 CGEN_EXTRACT_INFO *ex_info,
688 CGEN_INSN_INT insn_value,
689 CGEN_FIELDS * fields,
690 bfd_vma pc)
87e6d782
NC
691{
692 /* Assume success (for those operands that are nops). */
693 int length = 1;
694 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
695
696 switch (opindex)
697 {
c8e98e36
SH
698 case OR1K_OPERAND_DISP21 :
699 {
700 long value;
701 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 20, 21, 32, total_length, pc, & value);
702 value = ((((value) + (((DI) (pc) >> (13))))) << (13));
703 fields->f_disp21 = value;
704 }
705 break;
73589c9d 706 case OR1K_OPERAND_DISP26 :
87e6d782
NC
707 {
708 long value;
709 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, pc, & value);
710 value = ((((value) << (2))) + (pc));
711 fields->f_disp26 = value;
712 }
713 break;
73589c9d
CS
714 case OR1K_OPERAND_RA :
715 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
87e6d782 716 break;
73589c9d
CS
717 case OR1K_OPERAND_RADF :
718 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
87e6d782 719 break;
73589c9d
CS
720 case OR1K_OPERAND_RASF :
721 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
87e6d782 722 break;
73589c9d
CS
723 case OR1K_OPERAND_RB :
724 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
87e6d782 725 break;
73589c9d
CS
726 case OR1K_OPERAND_RBDF :
727 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
87e6d782 728 break;
73589c9d 729 case OR1K_OPERAND_RBSF :
87e6d782
NC
730 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
731 break;
73589c9d
CS
732 case OR1K_OPERAND_RD :
733 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
734 break;
735 case OR1K_OPERAND_RDDF :
736 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
737 break;
738 case OR1K_OPERAND_RDSF :
87e6d782
NC
739 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
740 break;
73589c9d
CS
741 case OR1K_OPERAND_SIMM16 :
742 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_SIGN_OPT), 0, 15, 16, 32, total_length, pc, & fields->f_simm16);
87e6d782 743 break;
73589c9d 744 case OR1K_OPERAND_SIMM16_SPLIT :
87e6d782 745 {
73589c9d 746 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_imm16_25_5);
87e6d782 747 if (length <= 0) break;
73589c9d 748 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_imm16_10_11);
87e6d782 749 if (length <= 0) break;
73589c9d 750 FLD (f_simm16_split) = ((HI) (UINT) (((((FLD (f_imm16_25_5)) << (11))) | (FLD (f_imm16_10_11)))));
87e6d782
NC
751 }
752 break;
73589c9d 753 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
754 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm16);
755 break;
73589c9d
CS
756 case OR1K_OPERAND_UIMM16_SPLIT :
757 {
758 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_imm16_25_5);
759 if (length <= 0) break;
760 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_imm16_10_11);
761 if (length <= 0) break;
762 FLD (f_uimm16_split) = ((UHI) (UINT) (((((FLD (f_imm16_25_5)) << (11))) | (FLD (f_imm16_10_11)))));
763 }
764 break;
765 case OR1K_OPERAND_UIMM6 :
766 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_uimm6);
87e6d782
NC
767 break;
768
769 default :
770 /* xgettext:c-format */
a6743a54
AM
771 opcodes_error_handler
772 (_("internal error: unrecognized field %d while decoding insn"),
773 opindex);
87e6d782
NC
774 abort ();
775 }
776
777 return length;
778}
779
43e65147 780cgen_insert_fn * const or1k_cgen_insert_handlers[] =
87e6d782
NC
781{
782 insert_insn_normal,
783};
784
43e65147 785cgen_extract_fn * const or1k_cgen_extract_handlers[] =
87e6d782
NC
786{
787 extract_insn_normal,
788};
789
73589c9d
CS
790int or1k_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
791bfd_vma or1k_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
0e2ee3ca 792
87e6d782
NC
793/* Getting values from cgen_fields is handled by a collection of functions.
794 They are distinguished by the type of the VALUE argument they return.
795 TODO: floating point, inlining support, remove cases where result type
796 not appropriate. */
797
798int
73589c9d 799or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
800 int opindex,
801 const CGEN_FIELDS * fields)
87e6d782
NC
802{
803 int value;
804
805 switch (opindex)
806 {
c8e98e36
SH
807 case OR1K_OPERAND_DISP21 :
808 value = fields->f_disp21;
809 break;
73589c9d 810 case OR1K_OPERAND_DISP26 :
87e6d782
NC
811 value = fields->f_disp26;
812 break;
73589c9d
CS
813 case OR1K_OPERAND_RA :
814 value = fields->f_r2;
87e6d782 815 break;
73589c9d
CS
816 case OR1K_OPERAND_RADF :
817 value = fields->f_r1;
87e6d782 818 break;
73589c9d
CS
819 case OR1K_OPERAND_RASF :
820 value = fields->f_r2;
87e6d782 821 break;
73589c9d
CS
822 case OR1K_OPERAND_RB :
823 value = fields->f_r3;
87e6d782 824 break;
73589c9d
CS
825 case OR1K_OPERAND_RBDF :
826 value = fields->f_r1;
87e6d782 827 break;
73589c9d 828 case OR1K_OPERAND_RBSF :
87e6d782
NC
829 value = fields->f_r3;
830 break;
73589c9d
CS
831 case OR1K_OPERAND_RD :
832 value = fields->f_r1;
833 break;
834 case OR1K_OPERAND_RDDF :
87e6d782
NC
835 value = fields->f_r1;
836 break;
73589c9d
CS
837 case OR1K_OPERAND_RDSF :
838 value = fields->f_r1;
839 break;
840 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
841 value = fields->f_simm16;
842 break;
73589c9d
CS
843 case OR1K_OPERAND_SIMM16_SPLIT :
844 value = fields->f_simm16_split;
87e6d782 845 break;
73589c9d 846 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
847 value = fields->f_uimm16;
848 break;
73589c9d
CS
849 case OR1K_OPERAND_UIMM16_SPLIT :
850 value = fields->f_uimm16_split;
851 break;
852 case OR1K_OPERAND_UIMM6 :
853 value = fields->f_uimm6;
87e6d782
NC
854 break;
855
856 default :
857 /* xgettext:c-format */
a6743a54
AM
858 opcodes_error_handler
859 (_("internal error: unrecognized field %d while getting int operand"),
860 opindex);
87e6d782
NC
861 abort ();
862 }
863
864 return value;
865}
866
867bfd_vma
73589c9d 868or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
869 int opindex,
870 const CGEN_FIELDS * fields)
87e6d782
NC
871{
872 bfd_vma value;
873
874 switch (opindex)
875 {
c8e98e36
SH
876 case OR1K_OPERAND_DISP21 :
877 value = fields->f_disp21;
878 break;
73589c9d 879 case OR1K_OPERAND_DISP26 :
87e6d782
NC
880 value = fields->f_disp26;
881 break;
73589c9d
CS
882 case OR1K_OPERAND_RA :
883 value = fields->f_r2;
87e6d782 884 break;
73589c9d
CS
885 case OR1K_OPERAND_RADF :
886 value = fields->f_r1;
87e6d782 887 break;
73589c9d
CS
888 case OR1K_OPERAND_RASF :
889 value = fields->f_r2;
87e6d782 890 break;
73589c9d
CS
891 case OR1K_OPERAND_RB :
892 value = fields->f_r3;
87e6d782 893 break;
73589c9d
CS
894 case OR1K_OPERAND_RBDF :
895 value = fields->f_r1;
87e6d782 896 break;
73589c9d 897 case OR1K_OPERAND_RBSF :
87e6d782
NC
898 value = fields->f_r3;
899 break;
73589c9d
CS
900 case OR1K_OPERAND_RD :
901 value = fields->f_r1;
902 break;
903 case OR1K_OPERAND_RDDF :
904 value = fields->f_r1;
905 break;
906 case OR1K_OPERAND_RDSF :
87e6d782
NC
907 value = fields->f_r1;
908 break;
73589c9d 909 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
910 value = fields->f_simm16;
911 break;
73589c9d
CS
912 case OR1K_OPERAND_SIMM16_SPLIT :
913 value = fields->f_simm16_split;
87e6d782 914 break;
73589c9d 915 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
916 value = fields->f_uimm16;
917 break;
73589c9d
CS
918 case OR1K_OPERAND_UIMM16_SPLIT :
919 value = fields->f_uimm16_split;
920 break;
921 case OR1K_OPERAND_UIMM6 :
922 value = fields->f_uimm6;
87e6d782
NC
923 break;
924
925 default :
926 /* xgettext:c-format */
a6743a54
AM
927 opcodes_error_handler
928 (_("internal error: unrecognized field %d while getting vma operand"),
929 opindex);
87e6d782
NC
930 abort ();
931 }
932
933 return value;
934}
935
73589c9d
CS
936void or1k_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
937void or1k_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 938
87e6d782
NC
939/* Stuffing values in cgen_fields is handled by a collection of functions.
940 They are distinguished by the type of the VALUE argument they accept.
941 TODO: floating point, inlining support, remove cases where argument type
942 not appropriate. */
943
944void
73589c9d 945or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
946 int opindex,
947 CGEN_FIELDS * fields,
948 int value)
87e6d782
NC
949{
950 switch (opindex)
951 {
c8e98e36
SH
952 case OR1K_OPERAND_DISP21 :
953 fields->f_disp21 = value;
954 break;
73589c9d 955 case OR1K_OPERAND_DISP26 :
87e6d782
NC
956 fields->f_disp26 = value;
957 break;
73589c9d
CS
958 case OR1K_OPERAND_RA :
959 fields->f_r2 = value;
87e6d782 960 break;
73589c9d
CS
961 case OR1K_OPERAND_RADF :
962 fields->f_r1 = value;
87e6d782 963 break;
73589c9d
CS
964 case OR1K_OPERAND_RASF :
965 fields->f_r2 = value;
87e6d782 966 break;
73589c9d
CS
967 case OR1K_OPERAND_RB :
968 fields->f_r3 = value;
87e6d782 969 break;
73589c9d
CS
970 case OR1K_OPERAND_RBDF :
971 fields->f_r1 = value;
87e6d782 972 break;
73589c9d 973 case OR1K_OPERAND_RBSF :
87e6d782
NC
974 fields->f_r3 = value;
975 break;
73589c9d 976 case OR1K_OPERAND_RD :
87e6d782
NC
977 fields->f_r1 = value;
978 break;
73589c9d
CS
979 case OR1K_OPERAND_RDDF :
980 fields->f_r1 = value;
981 break;
982 case OR1K_OPERAND_RDSF :
983 fields->f_r1 = value;
984 break;
985 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
986 fields->f_simm16 = value;
987 break;
73589c9d
CS
988 case OR1K_OPERAND_SIMM16_SPLIT :
989 fields->f_simm16_split = value;
87e6d782 990 break;
73589c9d 991 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
992 fields->f_uimm16 = value;
993 break;
73589c9d
CS
994 case OR1K_OPERAND_UIMM16_SPLIT :
995 fields->f_uimm16_split = value;
996 break;
997 case OR1K_OPERAND_UIMM6 :
998 fields->f_uimm6 = value;
87e6d782
NC
999 break;
1000
1001 default :
1002 /* xgettext:c-format */
a6743a54
AM
1003 opcodes_error_handler
1004 (_("internal error: unrecognized field %d while setting int operand"),
1005 opindex);
87e6d782
NC
1006 abort ();
1007 }
1008}
1009
1010void
73589c9d 1011or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
1012 int opindex,
1013 CGEN_FIELDS * fields,
1014 bfd_vma value)
87e6d782
NC
1015{
1016 switch (opindex)
1017 {
c8e98e36
SH
1018 case OR1K_OPERAND_DISP21 :
1019 fields->f_disp21 = value;
1020 break;
73589c9d 1021 case OR1K_OPERAND_DISP26 :
87e6d782
NC
1022 fields->f_disp26 = value;
1023 break;
73589c9d
CS
1024 case OR1K_OPERAND_RA :
1025 fields->f_r2 = value;
87e6d782 1026 break;
73589c9d
CS
1027 case OR1K_OPERAND_RADF :
1028 fields->f_r1 = value;
87e6d782 1029 break;
73589c9d
CS
1030 case OR1K_OPERAND_RASF :
1031 fields->f_r2 = value;
87e6d782 1032 break;
73589c9d
CS
1033 case OR1K_OPERAND_RB :
1034 fields->f_r3 = value;
87e6d782 1035 break;
73589c9d
CS
1036 case OR1K_OPERAND_RBDF :
1037 fields->f_r1 = value;
87e6d782 1038 break;
73589c9d 1039 case OR1K_OPERAND_RBSF :
87e6d782
NC
1040 fields->f_r3 = value;
1041 break;
73589c9d
CS
1042 case OR1K_OPERAND_RD :
1043 fields->f_r1 = value;
1044 break;
1045 case OR1K_OPERAND_RDDF :
87e6d782
NC
1046 fields->f_r1 = value;
1047 break;
73589c9d
CS
1048 case OR1K_OPERAND_RDSF :
1049 fields->f_r1 = value;
1050 break;
1051 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
1052 fields->f_simm16 = value;
1053 break;
73589c9d
CS
1054 case OR1K_OPERAND_SIMM16_SPLIT :
1055 fields->f_simm16_split = value;
87e6d782 1056 break;
73589c9d 1057 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
1058 fields->f_uimm16 = value;
1059 break;
73589c9d
CS
1060 case OR1K_OPERAND_UIMM16_SPLIT :
1061 fields->f_uimm16_split = value;
1062 break;
1063 case OR1K_OPERAND_UIMM6 :
1064 fields->f_uimm6 = value;
87e6d782
NC
1065 break;
1066
1067 default :
1068 /* xgettext:c-format */
a6743a54
AM
1069 opcodes_error_handler
1070 (_("internal error: unrecognized field %d while setting vma operand"),
1071 opindex);
87e6d782
NC
1072 abort ();
1073 }
1074}
1075
1076/* Function to call before using the instruction builder tables. */
1077
1078void
73589c9d 1079or1k_cgen_init_ibld_table (CGEN_CPU_DESC cd)
87e6d782 1080{
73589c9d
CS
1081 cd->insert_handlers = & or1k_cgen_insert_handlers[0];
1082 cd->extract_handlers = & or1k_cgen_extract_handlers[0];
87e6d782 1083
73589c9d
CS
1084 cd->insert_operand = or1k_cgen_insert_operand;
1085 cd->extract_operand = or1k_cgen_extract_operand;
87e6d782 1086
73589c9d
CS
1087 cd->get_int_operand = or1k_cgen_get_int_operand;
1088 cd->set_int_operand = or1k_cgen_set_int_operand;
1089 cd->get_vma_operand = or1k_cgen_get_vma_operand;
1090 cd->set_vma_operand = or1k_cgen_set_vma_operand;
87e6d782 1091}